[INFO] fetching crate falcon_capstone 0.5.3...
[INFO] checking falcon_capstone-0.5.3 against 895980e0290783bb09b1ccf1b11f14eb09b10430 for pr-160186
[INFO] extracting crate falcon_capstone 0.5.3 into /workspace/builds/worker-3-tc2/source
[INFO] started tweaking crates.io crate falcon_capstone 0.5.3
[INFO] removed 0 missing examples
[INFO] removed 0 missing tests
[INFO] finished tweaking crates.io crate falcon_capstone 0.5.3
[INFO] tweaked toml for crates.io crate falcon_capstone 0.5.3 written to /workspace/builds/worker-3-tc2/source/Cargo.toml
[INFO] validating manifest of crates.io crate falcon_capstone 0.5.3 on toolchain 895980e0290783bb09b1ccf1b11f14eb09b10430
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+895980e0290783bb09b1ccf1b11f14eb09b10430" "metadata" "--manifest-path" "Cargo.toml" "--no-deps", kill_on_drop: false }`
[INFO] crate crates.io crate falcon_capstone 0.5.3 already has a lockfile, it will not be regenerated
[INFO] running `Command { std: CARGO_HOME="/workspace/cargo-home" RUSTUP_HOME="/workspace/rustup-home" "/workspace/cargo-home/bin/cargo" "+895980e0290783bb09b1ccf1b11f14eb09b10430" "fetch" "--manifest-path" "Cargo.toml", kill_on_drop: false }`
[INFO] [stderr] warning: `package.homepage` is redundant with `package.repository`
[INFO] [stderr]   --> Cargo.toml:43:12
[INFO] [stderr]    |
[INFO] [stderr] 43 | homepage = "https://github.com/falconre/falcon_capstone"
[INFO] [stderr]    |            ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stderr] ...
[INFO] [stderr] 47 | repository = "https://github.com/falconre/falcon_capstone"
[INFO] [stderr]    |              ---------------------------------------------
[INFO] [stderr]    |
[INFO] [stderr]    = note: `cargo::redundant_homepage` is set to `warn` by default
[INFO] [stderr] help: consider removing `package.homepage`
[INFO] [stderr] warning: `falcon_capstone` (manifest) generated 1 warning
[INFO] running `Command { std: "docker" "create" "-v" "/var/lib/crater-agent-workspace/builds/worker-3-tc2/source:/opt/rustwide/workdir:ro,Z" "-v" "/var/lib/crater-agent-workspace/builds/worker-3-tc2/target:/opt/rustwide/target:rw,Z" "-v" "/var/lib/crater-agent-workspace/cargo-home:/opt/rustwide/cargo-home:ro,Z" "-v" "/var/lib/crater-agent-workspace/rustup-home:/opt/rustwide/rustup-home:ro,Z" "-m" "1610612736" "--network" "none" "ghcr.io/rust-lang/crates-build-env/linux@sha256:77db811e55d90add9212f6832c23229e3de5f1c1f9905e8cb07319ea15df73ac" "sleep" "infinity", kill_on_drop: false }`
[INFO] [stdout] 7f2fd8ac16abf33e380527e3d91377f5ed5086ea369c16a71ed50adab43d269d
[INFO] running `Command { std: "docker" "start" "7f2fd8ac16abf33e380527e3d91377f5ed5086ea369c16a71ed50adab43d269d", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "inspect" "7f2fd8ac16abf33e380527e3d91377f5ed5086ea369c16a71ed50adab43d269d", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "exec" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-w" "/opt/rustwide/workdir" "--user" "0:0" "7f2fd8ac16abf33e380527e3d91377f5ed5086ea369c16a71ed50adab43d269d" "/opt/rustwide/cargo-home/bin/cargo" "+895980e0290783bb09b1ccf1b11f14eb09b10430" "metadata" "--no-deps" "--format-version=1", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "inspect" "7f2fd8ac16abf33e380527e3d91377f5ed5086ea369c16a71ed50adab43d269d", kill_on_drop: false }`
[INFO] running `Command { std: "docker" "exec" "-e" "SOURCE_DIR=/opt/rustwide/workdir" "-e" "CARGO_HOME=/opt/rustwide/cargo-home" "-e" "RUSTUP_HOME=/opt/rustwide/rustup-home" "-e" "CARGO_TARGET_DIR=/opt/rustwide/target" "-e" "CARGO_INCREMENTAL=0" "-e" "RUST_BACKTRACE=full" "-e" "RUSTFLAGS=--cap-lints=forbid" "-e" "RUSTDOCFLAGS=--cap-lints=forbid" "-w" "/opt/rustwide/workdir" "--user" "0:0" "7f2fd8ac16abf33e380527e3d91377f5ed5086ea369c16a71ed50adab43d269d" "/opt/rustwide/cargo-home/bin/cargo" "+895980e0290783bb09b1ccf1b11f14eb09b10430" "check" "--frozen" "--all" "--all-targets" "--message-format=json", kill_on_drop: false }`
[INFO] [stderr] warning: `package.homepage` is redundant with `package.repository`
[INFO] [stderr]   --> Cargo.toml:43:12
[INFO] [stderr]    |
[INFO] [stderr] 43 | homepage = "https://github.com/falconre/falcon_capstone"
[INFO] [stderr]    |            ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stderr] ...
[INFO] [stderr] 47 | repository = "https://github.com/falconre/falcon_capstone"
[INFO] [stderr]    |              ---------------------------------------------
[INFO] [stderr]    |
[INFO] [stderr]    = note: `cargo::redundant_homepage` is set to `warn` by default
[INFO] [stderr] help: consider removing `package.homepage`
[INFO] [stderr] warning: `falcon_capstone` (manifest) generated 1 warning
[INFO] [stderr]    Compiling glob v0.3.3
[INFO] [stderr]    Compiling quote v1.0.45
[INFO] [stderr]    Compiling prettyplease v0.2.37
[INFO] [stderr]    Compiling libc v0.2.183
[INFO] [stderr]    Compiling minimal-lexical v0.2.1
[INFO] [stderr]    Compiling regex-syntax v0.8.10
[INFO] [stderr]    Compiling memchr v2.8.0
[INFO] [stderr]    Compiling libloading v0.8.9
[INFO] [stderr]    Compiling either v1.15.0
[INFO] [stderr]    Compiling bindgen v0.72.1
[INFO] [stderr]    Compiling cc v1.2.56
[INFO] [stderr]    Compiling rustc-hash v2.1.1
[INFO] [stderr]    Compiling syn v2.0.117
[INFO] [stderr]    Compiling itertools v0.13.0
[INFO] [stderr]    Compiling bitflags v2.11.0
[INFO] [stderr]    Compiling clang-sys v1.8.1
[INFO] [stderr]    Compiling nom v7.1.3
[INFO] [stderr]    Compiling cmake v0.1.57
[INFO] [stderr]    Compiling regex-automata v0.4.14
[INFO] [stderr]    Compiling cexpr v0.6.0
[INFO] [stderr]    Compiling regex v1.12.3
[INFO] [stderr]    Compiling falcon_capstone v0.5.3 (/opt/rustwide/workdir)
[INFO] [stdout] warning: suspicious definition of the runtime `malloc` symbol used by the standard library
[INFO] [stdout]  --> /opt/rustwide/target/debug/build/falcon_capstone/f982cdb455ed4cf6/out/bindings.rs:3:62280
[INFO] [stdout]   |
[INFO] [stdout] 3 | ...afe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern ...
[INFO] [stdout]   |                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout]   = note: expected `unsafe extern "C" fn(usize) -> *mut c_void` (for the current target)
[INFO] [stdout]              found `unsafe extern "C" fn(u64) -> *mut c_void`
[INFO] [stdout]   = help: either fix the signature or remove any attributes like `#[unsafe(no_mangle)]`, `#[unsafe(export_name = "malloc")]`, or `#[link_name = "malloc"]`
[INFO] [stdout]   = help: allow this lint if the signature is compatible
[INFO] [stdout]   = note: `#[warn(suspicious_runtime_symbol_definitions)]` on by default
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: suspicious definition of the runtime `realloc` symbol used by the standard library
[INFO] [stdout]  --> /opt/rustwide/target/debug/build/falcon_capstone/f982cdb455ed4cf6/out/bindings.rs:3:62561
[INFO] [stdout]   |
[INFO] [stdout] 3 | ... { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } ...
[INFO] [stdout]   |       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout]   = note: expected `unsafe extern "C" fn(*mut c_void, usize) -> *mut c_void` (for the current target)
[INFO] [stdout]              found `unsafe extern "C" fn(*mut c_void, u64) -> *mut c_void`
[INFO] [stdout]   = help: either fix the signature or remove any attributes like `#[unsafe(no_mangle)]`, `#[unsafe(export_name = "realloc")]`, or `#[link_name = "realloc"]`
[INFO] [stdout]   = help: allow this lint if the signature is compatible
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: unnecessary transmute
[INFO] [stdout]  --> /opt/rustwide/target/debug/build/falcon_capstone/f982cdb455ed4cf6/out/bindings.rs:3:80141
[INFO] [stdout]   |
[INFO] [stdout] 3 | ...:: raw :: c_int { unsafe { :: std :: mem :: transmute (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set_...
[INFO] [stdout]   |                               ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout]   = note: `#[warn(unnecessary_transmutes)]` on by default
[INFO] [stdout] help: replace this with
[INFO] [stdout]   |
[INFO] [stdout] 3 - # [repr (C)] # [derive (Copy , Clone , Debug , Default , Eq , Hash , Ord , PartialEq , PartialOrd)] pub struct __BindgenBitfieldUnit < Storage > { storage : Storage , } impl < Storage > __BindgenBitfieldUnit < Storage > { # [inline] pub const fn new (storage : Storage) -> Self { Self { storage } } } impl < Storage > __BindgenBitfieldUnit < Storage > where Storage : AsRef < [u8] > + AsMut < [u8] >, { # [inline] fn extract_bit (byte : u8 , index : usize) -> bool { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; byte & mask == mask } # [inline] pub fn get_bit (& self , index : usize) -> bool { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = self . storage . as_ref () [byte_index] ; Self :: extract_bit (byte , index) } # [inline] pub unsafe fn raw_get_bit (this : * const Self , index : usize) -> bool { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { * (core :: ptr :: addr_of ! ((* this) . storage) as * const u8) . offset (byte_index as isize) } ; Self :: extract_bit (byte , index) } # [inline] fn change_bit (byte : u8 , index : usize , val : bool) -> u8 { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; if val { byte | mask } else { byte & ! mask } } # [inline] pub fn set_bit (& mut self , index : usize , val : bool) { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = & mut self . storage . as_mut () [byte_index] ; * byte = Self :: change_bit (* byte , index , val) ; } # [inline] pub unsafe fn raw_set_bit (this : * mut Self , index : usize , val : bool) { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { (core :: ptr :: addr_of_mut ! ((* this) . storage) as * mut u8) . offset (byte_index as isize) } ; unsafe { * byte = Self :: change_bit (* byte , index , val) } ; } # [inline] pub fn get (& self , bit_offset : usize , bit_width : u8) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if self . get_bit (i + bit_offset) { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub unsafe fn raw_get (this : * const Self , bit_offset : usize , bit_width : u8 ,) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if unsafe { Self :: raw_get_bit (this , i + bit_offset) } { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub fn set (& mut self , bit_offset : usize , bit_width : u8 , val : u64) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; self . set_bit (index + bit_offset , val_bit_is_set) ; } } # [inline] pub unsafe fn raw_set (this : * mut Self , bit_offset : usize , bit_width : u8 , val : u64 ,) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; unsafe { Self :: raw_set_bit (this , index + bit_offset , val_bit_is_set) } ; } } } # [derive (PartialEq , Copy , Clone , Hash , Debug , Default)] # [repr (C)] pub struct __BindgenComplex < T > { pub re : T , pub im : T } pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __GLIBC_USE_ISOC2Y : u32 = 0 ; pub const __GLIBC_USE_ISOC23 : u32 = 0 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 202405 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_XOPEN2K24 : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const __TIMESIZE : u32 = 64 ; pub const __USE_TIME_BITS64 : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_GETS : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_SCANF : u32 = 0 ; pub const __GLIBC_USE_C23_STRTOL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_60559_BFP__ : u32 = 201404 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_IEC_60559_COMPLEX__ : u32 = 201404 ; pub const __STDC_ISO_10646__ : u32 = 201706 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 43 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __glibc_c99_flexarr_available : u32 = 1 ; pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI : u32 = 0 ; pub const __HAVE_GENERIC_SELECTION : u32 = 1 ; pub const __GLIBC_USE_LIB_EXT2 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_TYPES_EXT : u32 = 0 ; pub const _STDLIB_H : u32 = 1 ; pub const WNOHANG : u32 = 1 ; pub const WUNTRACED : u32 = 2 ; pub const WSTOPPED : u32 = 2 ; pub const WEXITED : u32 = 4 ; pub const WCONTINUED : u32 = 8 ; pub const WNOWAIT : u32 = 16777216 ; pub const __WNOTHREAD : u32 = 536870912 ; pub const __WALL : u32 = 1073741824 ; pub const __WCLONE : u32 = 2147483648 ; pub const __W_CONTINUED : u32 = 65535 ; pub const __WCOREFLAG : u32 = 128 ; pub const __HAVE_FLOAT128 : u32 = 1 ; pub const __HAVE_DISTINCT_FLOAT128 : u32 = 1 ; pub const __HAVE_FLOAT64X : u32 = 1 ; pub const __HAVE_FLOAT64X_LONG_DOUBLE : u32 = 1 ; pub const __HAVE_FLOAT16 : u32 = 0 ; pub const __HAVE_FLOAT32 : u32 = 1 ; pub const __HAVE_FLOAT64 : u32 = 1 ; pub const __HAVE_FLOAT32X : u32 = 1 ; pub const __HAVE_FLOAT128X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT16 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT128X : u32 = 0 ; pub const __HAVE_FLOATN_NOT_TYPEDEF : u32 = 0 ; pub const __ldiv_t_defined : u32 = 1 ; pub const __lldiv_t_defined : u32 = 1 ; pub const RAND_MAX : u32 = 2147483647 ; pub const EXIT_FAILURE : u32 = 1 ; pub const EXIT_SUCCESS : u32 = 0 ; pub const _SYS_TYPES_H : u32 = 1 ; pub const _BITS_TYPES_H : u32 = 1 ; pub const _BITS_TYPESIZES_H : u32 = 1 ; pub const __OFF_T_MATCHES_OFF64_T : u32 = 1 ; pub const __INO_T_MATCHES_INO64_T : u32 = 1 ; pub const __RLIM_T_MATCHES_RLIM64_T : u32 = 1 ; pub const __STATFS_MATCHES_STATFS64 : u32 = 1 ; pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 : u32 = 1 ; pub const __FD_SETSIZE : u32 = 1024 ; pub const _BITS_TIME64_H : u32 = 1 ; pub const __clock_t_defined : u32 = 1 ; pub const __clockid_t_defined : u32 = 1 ; pub const __time_t_defined : u32 = 1 ; pub const __timer_t_defined : u32 = 1 ; pub const _BITS_STDINT_INTN_H : u32 = 1 ; pub const __BIT_TYPES_DEFINED__ : u32 = 1 ; pub const _ENDIAN_H : u32 = 1 ; pub const _BITS_ENDIAN_H : u32 = 1 ; pub const __LITTLE_ENDIAN : u32 = 1234 ; pub const __BIG_ENDIAN : u32 = 4321 ; pub const __PDP_ENDIAN : u32 = 3412 ; pub const _BITS_ENDIANNESS_H : u32 = 1 ; pub const __BYTE_ORDER : u32 = 1234 ; pub const __FLOAT_WORD_ORDER : u32 = 1234 ; pub const LITTLE_ENDIAN : u32 = 1234 ; pub const BIG_ENDIAN : u32 = 4321 ; pub const PDP_ENDIAN : u32 = 3412 ; pub const BYTE_ORDER : u32 = 1234 ; pub const _BITS_BYTESWAP_H : u32 = 1 ; pub const _BITS_UINTN_IDENTITY_H : u32 = 1 ; pub const _SYS_SELECT_H : u32 = 1 ; pub const __sigset_t_defined : u32 = 1 ; pub const __timeval_defined : u32 = 1 ; pub const _STRUCT_TIMESPEC : u32 = 1 ; pub const FD_SETSIZE : u32 = 1024 ; pub const _BITS_PTHREADTYPES_COMMON_H : u32 = 1 ; pub const _THREAD_SHARED_TYPES_H : u32 = 1 ; pub const _BITS_PTHREADTYPES_ARCH_H : u32 = 1 ; pub const __SIZEOF_PTHREAD_MUTEX_T : u32 = 40 ; pub const __SIZEOF_PTHREAD_ATTR_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_RWLOCK_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_BARRIER_T : u32 = 32 ; pub const __SIZEOF_PTHREAD_MUTEXATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_COND_T : u32 = 48 ; pub const __SIZEOF_PTHREAD_CONDATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_RWLOCKATTR_T : u32 = 8 ; pub const __SIZEOF_PTHREAD_BARRIERATTR_T : u32 = 4 ; pub const _THREAD_MUTEX_INTERNAL_H : u32 = 1 ; pub const __PTHREAD_MUTEX_HAVE_PREV : u32 = 1 ; pub const __have_pthread_attr_t : u32 = 1 ; pub const _ALLOCA_H : u32 = 1 ; pub const _STDIO_H : u32 = 1 ; pub const _____fpos_t_defined : u32 = 1 ; pub const ____mbstate_t_defined : u32 = 1 ; pub const _____fpos64_t_defined : u32 = 1 ; pub const ____FILE_defined : u32 = 1 ; pub const __FILE_defined : u32 = 1 ; pub const __struct_FILE_defined : u32 = 1 ; pub const _IO_EOF_SEEN : u32 = 16 ; pub const _IO_ERR_SEEN : u32 = 32 ; pub const _IO_USER_LOCK : u32 = 32768 ; pub const __cookie_io_functions_t_defined : u32 = 1 ; pub const _IOFBF : u32 = 0 ; pub const _IOLBF : u32 = 1 ; pub const _IONBF : u32 = 2 ; pub const BUFSIZ : u32 = 8192 ; pub const EOF : i32 = - 1 ; pub const SEEK_SET : u32 = 0 ; pub const SEEK_CUR : u32 = 1 ; pub const SEEK_END : u32 = 2 ; pub const P_tmpdir : & [u8 ; 5] = b"/tmp\0" ; pub const L_tmpnam : u32 = 20 ; pub const TMP_MAX : u32 = 238328 ; pub const _BITS_STDIO_LIM_H : u32 = 1 ; pub const FILENAME_MAX : u32 = 4096 ; pub const L_ctermid : u32 = 9 ; pub const FOPEN_MAX : u32 = 16 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const _INTTYPES_H : u32 = 1 ; pub const _STDINT_H : u32 = 1 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const _BITS_STDINT_UINTN_H : u32 = 1 ; pub const _BITS_STDINT_LEAST_H : u32 = 1 ; pub const INT8_MIN : i32 = - 128 ; pub const INT16_MIN : i32 = - 32768 ; pub const INT32_MIN : i32 = - 2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = - 128 ; pub const INT_LEAST16_MIN : i32 = - 32768 ; pub const INT_LEAST32_MIN : i32 = - 2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = - 128 ; pub const INT_FAST16_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST32_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = - 1 ; pub const UINT_FAST32_MAX : i32 = - 1 ; pub const INTPTR_MIN : i64 = - 9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = - 1 ; pub const PTRDIFF_MIN : i64 = - 9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = - 2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = - 1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const ____gwchar_t_defined : u32 = 1 ; pub const __PRI64_PREFIX : & [u8 ; 2] = b"l\0" ; pub const __PRIPTR_PREFIX : & [u8 ; 2] = b"l\0" ; pub const PRId8 : & [u8 ; 4] = b"hhd\0" ; pub const PRId16 : & [u8 ; 3] = b"hd\0" ; pub const PRId32 : & [u8 ; 2] = b"d\0" ; pub const PRId64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const PRIdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const PRIdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIi8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIi16 : & [u8 ; 3] = b"hi\0" ; pub const PRIi32 : & [u8 ; 2] = b"i\0" ; pub const PRIi64 : & [u8 ; 3] = b"li\0" ; pub const PRIiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const PRIiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const PRIiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiFAST16 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST32 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIo8 : & [u8 ; 4] = b"hho\0" ; pub const PRIo16 : & [u8 ; 3] = b"ho\0" ; pub const PRIo32 : & [u8 ; 2] = b"o\0" ; pub const PRIo64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const PRIoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const PRIoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIu8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIu16 : & [u8 ; 3] = b"hu\0" ; pub const PRIu32 : & [u8 ; 2] = b"u\0" ; pub const PRIu64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const PRIuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const PRIuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIx8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIx16 : & [u8 ; 3] = b"hx\0" ; pub const PRIx32 : & [u8 ; 2] = b"x\0" ; pub const PRIx64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const PRIxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const PRIxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIX8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIX16 : & [u8 ; 3] = b"hX\0" ; pub const PRIX32 : & [u8 ; 2] = b"X\0" ; pub const PRIX64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXLEAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXLEAST16 : & [u8 ; 3] = b"hX\0" ; pub const PRIXLEAST32 : & [u8 ; 2] = b"X\0" ; pub const PRIXLEAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXFAST16 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST32 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIdMAX : & [u8 ; 3] = b"ld\0" ; pub const PRIiMAX : & [u8 ; 3] = b"li\0" ; pub const PRIoMAX : & [u8 ; 3] = b"lo\0" ; pub const PRIuMAX : & [u8 ; 3] = b"lu\0" ; pub const PRIxMAX : & [u8 ; 3] = b"lx\0" ; pub const PRIXMAX : & [u8 ; 3] = b"lX\0" ; pub const PRIdPTR : & [u8 ; 3] = b"ld\0" ; pub const PRIiPTR : & [u8 ; 3] = b"li\0" ; pub const PRIoPTR : & [u8 ; 3] = b"lo\0" ; pub const PRIuPTR : & [u8 ; 3] = b"lu\0" ; pub const PRIxPTR : & [u8 ; 3] = b"lx\0" ; pub const PRIXPTR : & [u8 ; 3] = b"lX\0" ; pub const SCNd8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNd16 : & [u8 ; 3] = b"hd\0" ; pub const SCNd32 : & [u8 ; 2] = b"d\0" ; pub const SCNd64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const SCNdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const SCNdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNi8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNi16 : & [u8 ; 3] = b"hi\0" ; pub const SCNi32 : & [u8 ; 2] = b"i\0" ; pub const SCNi64 : & [u8 ; 3] = b"li\0" ; pub const SCNiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const SCNiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const SCNiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiFAST16 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST32 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNu8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNu16 : & [u8 ; 3] = b"hu\0" ; pub const SCNu32 : & [u8 ; 2] = b"u\0" ; pub const SCNu64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const SCNuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const SCNuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNo8 : & [u8 ; 4] = b"hho\0" ; pub const SCNo16 : & [u8 ; 3] = b"ho\0" ; pub const SCNo32 : & [u8 ; 2] = b"o\0" ; pub const SCNo64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const SCNoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const SCNoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNx8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNx16 : & [u8 ; 3] = b"hx\0" ; pub const SCNx32 : & [u8 ; 2] = b"x\0" ; pub const SCNx64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const SCNxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const SCNxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNdMAX : & [u8 ; 3] = b"ld\0" ; pub const SCNiMAX : & [u8 ; 3] = b"li\0" ; pub const SCNoMAX : & [u8 ; 3] = b"lo\0" ; pub const SCNuMAX : & [u8 ; 3] = b"lu\0" ; pub const SCNxMAX : & [u8 ; 3] = b"lx\0" ; pub const SCNdPTR : & [u8 ; 3] = b"ld\0" ; pub const SCNiPTR : & [u8 ; 3] = b"li\0" ; pub const SCNoPTR : & [u8 ; 3] = b"lo\0" ; pub const SCNuPTR : & [u8 ; 3] = b"lu\0" ; pub const SCNxPTR : & [u8 ; 3] = b"lx\0" ; pub const CS_API_MAJOR : u32 = 5 ; pub const CS_API_MINOR : u32 = 0 ; pub const CS_NEXT_VERSION : u32 = 5 ; pub const CS_VERSION_MAJOR : u32 = 5 ; pub const CS_VERSION_MINOR : u32 = 0 ; pub const CS_VERSION_EXTRA : u32 = 7 ; pub const CS_MNEMONIC_SIZE : u32 = 32 ; pub const M68K_OPERAND_COUNT : u32 = 4 ; pub const X86_EFLAGS_MODIFY_AF : u32 = 1 ; pub const X86_EFLAGS_MODIFY_CF : u32 = 2 ; pub const X86_EFLAGS_MODIFY_SF : u32 = 4 ; pub const X86_EFLAGS_MODIFY_ZF : u32 = 8 ; pub const X86_EFLAGS_MODIFY_PF : u32 = 16 ; pub const X86_EFLAGS_MODIFY_OF : u32 = 32 ; pub const X86_EFLAGS_MODIFY_TF : u32 = 64 ; pub const X86_EFLAGS_MODIFY_IF : u32 = 128 ; pub const X86_EFLAGS_MODIFY_DF : u32 = 256 ; pub const X86_EFLAGS_MODIFY_NT : u32 = 512 ; pub const X86_EFLAGS_MODIFY_RF : u32 = 1024 ; pub const X86_EFLAGS_PRIOR_OF : u32 = 2048 ; pub const X86_EFLAGS_PRIOR_SF : u32 = 4096 ; pub const X86_EFLAGS_PRIOR_ZF : u32 = 8192 ; pub const X86_EFLAGS_PRIOR_AF : u32 = 16384 ; pub const X86_EFLAGS_PRIOR_PF : u32 = 32768 ; pub const X86_EFLAGS_PRIOR_CF : u32 = 65536 ; pub const X86_EFLAGS_PRIOR_TF : u32 = 131072 ; pub const X86_EFLAGS_PRIOR_IF : u32 = 262144 ; pub const X86_EFLAGS_PRIOR_DF : u32 = 524288 ; pub const X86_EFLAGS_PRIOR_NT : u32 = 1048576 ; pub const X86_EFLAGS_RESET_OF : u32 = 2097152 ; pub const X86_EFLAGS_RESET_CF : u32 = 4194304 ; pub const X86_EFLAGS_RESET_DF : u32 = 8388608 ; pub const X86_EFLAGS_RESET_IF : u32 = 16777216 ; pub const X86_EFLAGS_RESET_SF : u32 = 33554432 ; pub const X86_EFLAGS_RESET_AF : u32 = 67108864 ; pub const X86_EFLAGS_RESET_TF : u32 = 134217728 ; pub const X86_EFLAGS_RESET_NT : u32 = 268435456 ; pub const X86_EFLAGS_RESET_PF : u32 = 536870912 ; pub const X86_EFLAGS_SET_CF : u32 = 1073741824 ; pub const X86_EFLAGS_SET_DF : u32 = 2147483648 ; pub const X86_EFLAGS_SET_IF : u64 = 4294967296 ; pub const X86_EFLAGS_TEST_OF : u64 = 8589934592 ; pub const X86_EFLAGS_TEST_SF : u64 = 17179869184 ; pub const X86_EFLAGS_TEST_ZF : u64 = 34359738368 ; pub const X86_EFLAGS_TEST_PF : u64 = 68719476736 ; pub const X86_EFLAGS_TEST_CF : u64 = 137438953472 ; pub const X86_EFLAGS_TEST_NT : u64 = 274877906944 ; pub const X86_EFLAGS_TEST_DF : u64 = 549755813888 ; pub const X86_EFLAGS_UNDEFINED_OF : u64 = 1099511627776 ; pub const X86_EFLAGS_UNDEFINED_SF : u64 = 2199023255552 ; pub const X86_EFLAGS_UNDEFINED_ZF : u64 = 4398046511104 ; pub const X86_EFLAGS_UNDEFINED_PF : u64 = 8796093022208 ; pub const X86_EFLAGS_UNDEFINED_AF : u64 = 17592186044416 ; pub const X86_EFLAGS_UNDEFINED_CF : u64 = 35184372088832 ; pub const X86_EFLAGS_RESET_RF : u64 = 70368744177664 ; pub const X86_EFLAGS_TEST_RF : u64 = 140737488355328 ; pub const X86_EFLAGS_TEST_IF : u64 = 281474976710656 ; pub const X86_EFLAGS_TEST_TF : u64 = 562949953421312 ; pub const X86_EFLAGS_TEST_AF : u64 = 1125899906842624 ; pub const X86_EFLAGS_RESET_ZF : u64 = 2251799813685248 ; pub const X86_EFLAGS_SET_OF : u64 = 4503599627370496 ; pub const X86_EFLAGS_SET_SF : u64 = 9007199254740992 ; pub const X86_EFLAGS_SET_ZF : u64 = 18014398509481984 ; pub const X86_EFLAGS_SET_AF : u64 = 36028797018963968 ; pub const X86_EFLAGS_SET_PF : u64 = 72057594037927936 ; pub const X86_EFLAGS_RESET_0F : u64 = 144115188075855872 ; pub const X86_EFLAGS_RESET_AC : u64 = 288230376151711744 ; pub const X86_FPU_FLAGS_MODIFY_C0 : u32 = 1 ; pub const X86_FPU_FLAGS_MODIFY_C1 : u32 = 2 ; pub const X86_FPU_FLAGS_MODIFY_C2 : u32 = 4 ; pub const X86_FPU_FLAGS_MODIFY_C3 : u32 = 8 ; pub const X86_FPU_FLAGS_RESET_C0 : u32 = 16 ; pub const X86_FPU_FLAGS_RESET_C1 : u32 = 32 ; pub const X86_FPU_FLAGS_RESET_C2 : u32 = 64 ; pub const X86_FPU_FLAGS_RESET_C3 : u32 = 128 ; pub const X86_FPU_FLAGS_SET_C0 : u32 = 256 ; pub const X86_FPU_FLAGS_SET_C1 : u32 = 512 ; pub const X86_FPU_FLAGS_SET_C2 : u32 = 1024 ; pub const X86_FPU_FLAGS_SET_C3 : u32 = 2048 ; pub const X86_FPU_FLAGS_UNDEFINED_C0 : u32 = 4096 ; pub const X86_FPU_FLAGS_UNDEFINED_C1 : u32 = 8192 ; pub const X86_FPU_FLAGS_UNDEFINED_C2 : u32 = 16384 ; pub const X86_FPU_FLAGS_UNDEFINED_C3 : u32 = 32768 ; pub const X86_FPU_FLAGS_TEST_C0 : u32 = 65536 ; pub const X86_FPU_FLAGS_TEST_C1 : u32 = 131072 ; pub const X86_FPU_FLAGS_TEST_C2 : u32 = 262144 ; pub const X86_FPU_FLAGS_TEST_C3 : u32 = 524288 ; pub const M680X_OPERAND_COUNT : u32 = 9 ; pub const M680X_OFFSET_NONE : u32 = 0 ; pub const M680X_OFFSET_BITS_5 : u32 = 5 ; pub const M680X_OFFSET_BITS_8 : u32 = 8 ; pub const M680X_OFFSET_BITS_9 : u32 = 9 ; pub const M680X_OFFSET_BITS_16 : u32 = 16 ; pub const M680X_IDX_INDIRECT : u32 = 1 ; pub const M680X_IDX_NO_COMMA : u32 = 2 ; pub const M680X_IDX_POST_INC_DEC : u32 = 4 ; pub const M680X_FIRST_OP_IN_MNEM : u32 = 1 ; pub const M680X_SECOND_OP_IN_MNEM : u32 = 2 ; pub const TRICORE_OP_COUNT : u32 = 8 ; pub const MAX_IMPL_W_REGS : u32 = 20 ; pub const MAX_IMPL_R_REGS : u32 = 20 ; pub const MAX_NUM_GROUPS : u32 = 8 ; pub type __gnuc_va_list = __builtin_va_list ; pub type va_list = __builtin_va_list ; pub type wchar_t = :: std :: os :: raw :: c_int ; pub type __cfloat128 = __BindgenComplex < u128 > ; pub type _Float128 = u128 ; pub type _Float32 = f32 ; pub type _Float64 = f64 ; pub type _Float32x = f64 ; pub type _Float64x = u128 ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct div_t { pub quot : :: std :: os :: raw :: c_int , pub rem : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of div_t"] [:: std :: mem :: size_of :: < div_t > () - 8usize] ; ["Alignment of div_t"] [:: std :: mem :: align_of :: < div_t > () - 4usize] ; ["Offset of field: div_t::quot"] [:: std :: mem :: offset_of ! (div_t , quot) - 0usize] ; ["Offset of field: div_t::rem"] [:: std :: mem :: offset_of ! (div_t , rem) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ldiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ldiv_t"] [:: std :: mem :: size_of :: < ldiv_t > () - 16usize] ; ["Alignment of ldiv_t"] [:: std :: mem :: align_of :: < ldiv_t > () - 8usize] ; ["Offset of field: ldiv_t::quot"] [:: std :: mem :: offset_of ! (ldiv_t , quot) - 0usize] ; ["Offset of field: ldiv_t::rem"] [:: std :: mem :: offset_of ! (ldiv_t , rem) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct lldiv_t { pub quot : :: std :: os :: raw :: c_longlong , pub rem : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of lldiv_t"] [:: std :: mem :: size_of :: < lldiv_t > () - 16usize] ; ["Alignment of lldiv_t"] [:: std :: mem :: align_of :: < lldiv_t > () - 8usize] ; ["Offset of field: lldiv_t::quot"] [:: std :: mem :: offset_of ! (lldiv_t , quot) - 0usize] ; ["Offset of field: lldiv_t::rem"] [:: std :: mem :: offset_of ! (lldiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn __ctype_get_mb_cur_max () -> usize ; } unsafe extern "C" { pub fn atof (__nptr : * const :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn atoi (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn atol (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn atoll (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtod (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn strtof (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f32 ; } unsafe extern "C" { pub fn strtold (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> u128 ; } unsafe extern "C" { pub fn strtol (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn strtoul (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn strtoq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtouq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn strtoll (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtoull (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn l64a (__n : :: std :: os :: raw :: c_long) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn a64l (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } pub type __u_char = :: std :: os :: raw :: c_uchar ; pub type __u_short = :: std :: os :: raw :: c_ushort ; pub type __u_int = :: std :: os :: raw :: c_uint ; pub type __u_long = :: std :: os :: raw :: c_ulong ; pub type __int8_t = :: std :: os :: raw :: c_schar ; pub type __uint8_t = :: std :: os :: raw :: c_uchar ; pub type __int16_t = :: std :: os :: raw :: c_short ; pub type __uint16_t = :: std :: os :: raw :: c_ushort ; pub type __int32_t = :: std :: os :: raw :: c_int ; pub type __uint32_t = :: std :: os :: raw :: c_uint ; pub type __int64_t = :: std :: os :: raw :: c_long ; pub type __uint64_t = :: std :: os :: raw :: c_ulong ; pub type __int_least8_t = __int8_t ; pub type __uint_least8_t = __uint8_t ; pub type __int_least16_t = __int16_t ; pub type __uint_least16_t = __uint16_t ; pub type __int_least32_t = __int32_t ; pub type __uint_least32_t = __uint32_t ; pub type __int_least64_t = __int64_t ; pub type __uint_least64_t = __uint64_t ; pub type __quad_t = :: std :: os :: raw :: c_long ; pub type __u_quad_t = :: std :: os :: raw :: c_ulong ; pub type __intmax_t = :: std :: os :: raw :: c_long ; pub type __uintmax_t = :: std :: os :: raw :: c_ulong ; pub type __dev_t = :: std :: os :: raw :: c_ulong ; pub type __uid_t = :: std :: os :: raw :: c_uint ; pub type __gid_t = :: std :: os :: raw :: c_uint ; pub type __ino_t = :: std :: os :: raw :: c_ulong ; pub type __ino64_t = :: std :: os :: raw :: c_ulong ; pub type __mode_t = :: std :: os :: raw :: c_uint ; pub type __nlink_t = :: std :: os :: raw :: c_ulong ; pub type __off_t = :: std :: os :: raw :: c_long ; pub type __off64_t = :: std :: os :: raw :: c_long ; pub type __pid_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __fsid_t { pub __val : [:: std :: os :: raw :: c_int ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __fsid_t"] [:: std :: mem :: size_of :: < __fsid_t > () - 8usize] ; ["Alignment of __fsid_t"] [:: std :: mem :: align_of :: < __fsid_t > () - 4usize] ; ["Offset of field: __fsid_t::__val"] [:: std :: mem :: offset_of ! (__fsid_t , __val) - 0usize] ; } ; pub type __clock_t = :: std :: os :: raw :: c_long ; pub type __rlim_t = :: std :: os :: raw :: c_ulong ; pub type __rlim64_t = :: std :: os :: raw :: c_ulong ; pub type __id_t = :: std :: os :: raw :: c_uint ; pub type __time_t = :: std :: os :: raw :: c_long ; pub type __useconds_t = :: std :: os :: raw :: c_uint ; pub type __suseconds_t = :: std :: os :: raw :: c_long ; pub type __suseconds64_t = :: std :: os :: raw :: c_long ; pub type __daddr_t = :: std :: os :: raw :: c_int ; pub type __key_t = :: std :: os :: raw :: c_int ; pub type __clockid_t = :: std :: os :: raw :: c_int ; pub type __timer_t = * mut :: std :: os :: raw :: c_void ; pub type __blksize_t = :: std :: os :: raw :: c_long ; pub type __blkcnt_t = :: std :: os :: raw :: c_long ; pub type __blkcnt64_t = :: std :: os :: raw :: c_long ; pub type __fsblkcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsblkcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsword_t = :: std :: os :: raw :: c_long ; pub type __ssize_t = :: std :: os :: raw :: c_long ; pub type __syscall_slong_t = :: std :: os :: raw :: c_long ; pub type __syscall_ulong_t = :: std :: os :: raw :: c_ulong ; pub type __loff_t = __off64_t ; pub type __caddr_t = * mut :: std :: os :: raw :: c_char ; pub type __intptr_t = :: std :: os :: raw :: c_long ; pub type __socklen_t = :: std :: os :: raw :: c_uint ; pub type __sig_atomic_t = :: std :: os :: raw :: c_int ; pub type u_char = __u_char ; pub type u_short = __u_short ; pub type u_int = __u_int ; pub type u_long = __u_long ; pub type quad_t = __quad_t ; pub type u_quad_t = __u_quad_t ; pub type fsid_t = __fsid_t ; pub type loff_t = __loff_t ; pub type ino_t = __ino_t ; pub type dev_t = __dev_t ; pub type gid_t = __gid_t ; pub type mode_t = __mode_t ; pub type nlink_t = __nlink_t ; pub type uid_t = __uid_t ; pub type off_t = __off_t ; pub type pid_t = __pid_t ; pub type id_t = __id_t ; pub type daddr_t = __daddr_t ; pub type caddr_t = __caddr_t ; pub type key_t = __key_t ; pub type clock_t = __clock_t ; pub type clockid_t = __clockid_t ; pub type time_t = __time_t ; pub type timer_t = __timer_t ; pub type ulong = :: std :: os :: raw :: c_ulong ; pub type ushort = :: std :: os :: raw :: c_ushort ; pub type uint = :: std :: os :: raw :: c_uint ; pub type u_int8_t = __uint8_t ; pub type u_int16_t = __uint16_t ; pub type u_int32_t = __uint32_t ; pub type u_int64_t = __uint64_t ; pub type register_t = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __sigset_t { pub __val : [:: std :: os :: raw :: c_ulong ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __sigset_t"] [:: std :: mem :: size_of :: < __sigset_t > () - 128usize] ; ["Alignment of __sigset_t"] [:: std :: mem :: align_of :: < __sigset_t > () - 8usize] ; ["Offset of field: __sigset_t::__val"] [:: std :: mem :: offset_of ! (__sigset_t , __val) - 0usize] ; } ; pub type sigset_t = __sigset_t ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timeval { pub tv_sec : __time_t , pub tv_usec : __suseconds_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timeval"] [:: std :: mem :: size_of :: < timeval > () - 16usize] ; ["Alignment of timeval"] [:: std :: mem :: align_of :: < timeval > () - 8usize] ; ["Offset of field: timeval::tv_sec"] [:: std :: mem :: offset_of ! (timeval , tv_sec) - 0usize] ; ["Offset of field: timeval::tv_usec"] [:: std :: mem :: offset_of ! (timeval , tv_usec) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timespec { pub tv_sec : __time_t , pub tv_nsec : __syscall_slong_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timespec"] [:: std :: mem :: size_of :: < timespec > () - 16usize] ; ["Alignment of timespec"] [:: std :: mem :: align_of :: < timespec > () - 8usize] ; ["Offset of field: timespec::tv_sec"] [:: std :: mem :: offset_of ! (timespec , tv_sec) - 0usize] ; ["Offset of field: timespec::tv_nsec"] [:: std :: mem :: offset_of ! (timespec , tv_nsec) - 8usize] ; } ; pub type suseconds_t = __suseconds_t ; pub type __fd_mask = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct fd_set { pub __fds_bits : [__fd_mask ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of fd_set"] [:: std :: mem :: size_of :: < fd_set > () - 128usize] ; ["Alignment of fd_set"] [:: std :: mem :: align_of :: < fd_set > () - 8usize] ; ["Offset of field: fd_set::__fds_bits"] [:: std :: mem :: offset_of ! (fd_set , __fds_bits) - 0usize] ; } ; pub type fd_mask = __fd_mask ; unsafe extern "C" { pub fn select (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * mut timeval) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pselect (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * const timespec , __sigmask : * const __sigset_t) -> :: std :: os :: raw :: c_int ; } pub type blksize_t = __blksize_t ; pub type blkcnt_t = __blkcnt_t ; pub type fsblkcnt_t = __fsblkcnt_t ; pub type fsfilcnt_t = __fsfilcnt_t ; # [repr (C)] # [derive (Copy , Clone)] pub union __atomic_wide_counter { pub __value64 : :: std :: os :: raw :: c_ulonglong , pub __value32 : __atomic_wide_counter__bindgen_ty_1 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __atomic_wide_counter__bindgen_ty_1 { pub __low : :: std :: os :: raw :: c_uint , pub __high : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: size_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 8usize] ; ["Alignment of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: align_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__low"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __low) - 0usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__high"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __high) - 4usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter"] [:: std :: mem :: size_of :: < __atomic_wide_counter > () - 8usize] ; ["Alignment of __atomic_wide_counter"] [:: std :: mem :: align_of :: < __atomic_wide_counter > () - 8usize] ; ["Offset of field: __atomic_wide_counter::__value64"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value64) - 0usize] ; ["Offset of field: __atomic_wide_counter::__value32"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value32) - 0usize] ; } ; impl :: std :: fmt :: Debug for __atomic_wide_counter { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__atomic_wide_counter {{ union }}") } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_list { pub __prev : * mut __pthread_internal_list , pub __next : * mut __pthread_internal_list , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_list"] [:: std :: mem :: size_of :: < __pthread_internal_list > () - 16usize] ; ["Alignment of __pthread_internal_list"] [:: std :: mem :: align_of :: < __pthread_internal_list > () - 8usize] ; ["Offset of field: __pthread_internal_list::__prev"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __prev) - 0usize] ; ["Offset of field: __pthread_internal_list::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __next) - 8usize] ; } ; pub type __pthread_list_t = __pthread_internal_list ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_slist { pub __next : * mut __pthread_internal_slist , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_slist"] [:: std :: mem :: size_of :: < __pthread_internal_slist > () - 8usize] ; ["Alignment of __pthread_internal_slist"] [:: std :: mem :: align_of :: < __pthread_internal_slist > () - 8usize] ; ["Offset of field: __pthread_internal_slist::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_slist , __next) - 0usize] ; } ; pub type __pthread_slist_t = __pthread_internal_slist ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_mutex_s { pub __lock : :: std :: os :: raw :: c_int , pub __count : :: std :: os :: raw :: c_uint , pub __owner : :: std :: os :: raw :: c_int , pub __nusers : :: std :: os :: raw :: c_uint , pub __kind : :: std :: os :: raw :: c_int , pub __spins : :: std :: os :: raw :: c_short , pub __unused : :: std :: os :: raw :: c_short , pub __list : __pthread_list_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_mutex_s"] [:: std :: mem :: size_of :: < __pthread_mutex_s > () - 40usize] ; ["Alignment of __pthread_mutex_s"] [:: std :: mem :: align_of :: < __pthread_mutex_s > () - 8usize] ; ["Offset of field: __pthread_mutex_s::__lock"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __lock) - 0usize] ; ["Offset of field: __pthread_mutex_s::__count"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __count) - 4usize] ; ["Offset of field: __pthread_mutex_s::__owner"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __owner) - 8usize] ; ["Offset of field: __pthread_mutex_s::__nusers"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __nusers) - 12usize] ; ["Offset of field: __pthread_mutex_s::__kind"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __kind) - 16usize] ; ["Offset of field: __pthread_mutex_s::__spins"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __spins) - 20usize] ; ["Offset of field: __pthread_mutex_s::__unused"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __unused) - 22usize] ; ["Offset of field: __pthread_mutex_s::__list"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __list) - 24usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_rwlock_arch_t { pub __readers : :: std :: os :: raw :: c_uint , pub __writers : :: std :: os :: raw :: c_uint , pub __wrphase_futex : :: std :: os :: raw :: c_uint , pub __writers_futex : :: std :: os :: raw :: c_uint , pub __pad3 : :: std :: os :: raw :: c_uint , pub __pad4 : :: std :: os :: raw :: c_uint , pub __cur_writer : :: std :: os :: raw :: c_int , pub __shared : :: std :: os :: raw :: c_int , pub __pad1 : :: std :: os :: raw :: c_ulong , pub __pad2 : :: std :: os :: raw :: c_ulong , pub __flags : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_rwlock_arch_t"] [:: std :: mem :: size_of :: < __pthread_rwlock_arch_t > () - 56usize] ; ["Alignment of __pthread_rwlock_arch_t"] [:: std :: mem :: align_of :: < __pthread_rwlock_arch_t > () - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__readers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __readers) - 0usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers) - 4usize] ; ["Offset of field: __pthread_rwlock_arch_t::__wrphase_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __wrphase_futex) - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers_futex) - 12usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad3"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad3) - 16usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad4"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad4) - 20usize] ; ["Offset of field: __pthread_rwlock_arch_t::__cur_writer"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __cur_writer) - 24usize] ; ["Offset of field: __pthread_rwlock_arch_t::__shared"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __shared) - 28usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad1"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad1) - 32usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad2"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad2) - 40usize] ; ["Offset of field: __pthread_rwlock_arch_t::__flags"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __flags) - 48usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct __pthread_cond_s { pub __wseq : __atomic_wide_counter , pub __g1_start : __atomic_wide_counter , pub __g_size : [:: std :: os :: raw :: c_uint ; 2usize] , pub __g1_orig_size : :: std :: os :: raw :: c_uint , pub __wrefs : :: std :: os :: raw :: c_uint , pub __g_signals : [:: std :: os :: raw :: c_uint ; 2usize] , pub __unused_initialized_1 : :: std :: os :: raw :: c_uint , pub __unused_initialized_2 : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_cond_s"] [:: std :: mem :: size_of :: < __pthread_cond_s > () - 48usize] ; ["Alignment of __pthread_cond_s"] [:: std :: mem :: align_of :: < __pthread_cond_s > () - 8usize] ; ["Offset of field: __pthread_cond_s::__wseq"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wseq) - 0usize] ; ["Offset of field: __pthread_cond_s::__g1_start"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_start) - 8usize] ; ["Offset of field: __pthread_cond_s::__g_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_size) - 16usize] ; ["Offset of field: __pthread_cond_s::__g1_orig_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_orig_size) - 24usize] ; ["Offset of field: __pthread_cond_s::__wrefs"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wrefs) - 28usize] ; ["Offset of field: __pthread_cond_s::__g_signals"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_signals) - 32usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_1"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_1) - 40usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_2"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_2) - 44usize] ; } ; impl :: std :: fmt :: Debug for __pthread_cond_s { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__pthread_cond_s {{ __wseq: {:?}, __g1_start: {:?}, __g_size: {:?}, __g1_orig_size: {:?}, __wrefs: {:?}, __g_signals: {:?}, __unused_initialized_1: {:?}, __unused_initialized_2: {:?} }}" , self . __wseq , self . __g1_start , self . __g_size , self . __g1_orig_size , self . __wrefs , self . __g_signals , self . __unused_initialized_1 , self . __unused_initialized_2) } } pub type __tss_t = :: std :: os :: raw :: c_uint ; pub type __thrd_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __once_flag { pub __data : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __once_flag"] [:: std :: mem :: size_of :: < __once_flag > () - 4usize] ; ["Alignment of __once_flag"] [:: std :: mem :: align_of :: < __once_flag > () - 4usize] ; ["Offset of field: __once_flag::__data"] [:: std :: mem :: offset_of ! (__once_flag , __data) - 0usize] ; } ; pub type pthread_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutexattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutexattr_t"] [:: std :: mem :: size_of :: < pthread_mutexattr_t > () - 4usize] ; ["Alignment of pthread_mutexattr_t"] [:: std :: mem :: align_of :: < pthread_mutexattr_t > () - 4usize] ; ["Offset of field: pthread_mutexattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __size) - 0usize] ; ["Offset of field: pthread_mutexattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutexattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutexattr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_condattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_condattr_t"] [:: std :: mem :: size_of :: < pthread_condattr_t > () - 4usize] ; ["Alignment of pthread_condattr_t"] [:: std :: mem :: align_of :: < pthread_condattr_t > () - 4usize] ; ["Offset of field: pthread_condattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __size) - 0usize] ; ["Offset of field: pthread_condattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_condattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_condattr_t {{ union }}") } } pub type pthread_key_t = :: std :: os :: raw :: c_uint ; pub type pthread_once_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_attr_t { pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_attr_t"] [:: std :: mem :: size_of :: < pthread_attr_t > () - 56usize] ; ["Alignment of pthread_attr_t"] [:: std :: mem :: align_of :: < pthread_attr_t > () - 8usize] ; ["Offset of field: pthread_attr_t::__size"] [:: std :: mem :: offset_of ! (pthread_attr_t , __size) - 0usize] ; ["Offset of field: pthread_attr_t::__align"] [:: std :: mem :: offset_of ! (pthread_attr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_attr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_attr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutex_t { pub __data : __pthread_mutex_s , pub __size : [:: std :: os :: raw :: c_char ; 40usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutex_t"] [:: std :: mem :: size_of :: < pthread_mutex_t > () - 40usize] ; ["Alignment of pthread_mutex_t"] [:: std :: mem :: align_of :: < pthread_mutex_t > () - 8usize] ; ["Offset of field: pthread_mutex_t::__data"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __data) - 0usize] ; ["Offset of field: pthread_mutex_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __size) - 0usize] ; ["Offset of field: pthread_mutex_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutex_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutex_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_cond_t { pub __data : __pthread_cond_s , pub __size : [:: std :: os :: raw :: c_char ; 48usize] , pub __align : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_cond_t"] [:: std :: mem :: size_of :: < pthread_cond_t > () - 48usize] ; ["Alignment of pthread_cond_t"] [:: std :: mem :: align_of :: < pthread_cond_t > () - 8usize] ; ["Offset of field: pthread_cond_t::__data"] [:: std :: mem :: offset_of ! (pthread_cond_t , __data) - 0usize] ; ["Offset of field: pthread_cond_t::__size"] [:: std :: mem :: offset_of ! (pthread_cond_t , __size) - 0usize] ; ["Offset of field: pthread_cond_t::__align"] [:: std :: mem :: offset_of ! (pthread_cond_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_cond_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_cond_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlock_t { pub __data : __pthread_rwlock_arch_t , pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlock_t"] [:: std :: mem :: size_of :: < pthread_rwlock_t > () - 56usize] ; ["Alignment of pthread_rwlock_t"] [:: std :: mem :: align_of :: < pthread_rwlock_t > () - 8usize] ; ["Offset of field: pthread_rwlock_t::__data"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __data) - 0usize] ; ["Offset of field: pthread_rwlock_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __size) - 0usize] ; ["Offset of field: pthread_rwlock_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlock_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlock_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlockattr_t { pub __size : [:: std :: os :: raw :: c_char ; 8usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlockattr_t"] [:: std :: mem :: size_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Alignment of pthread_rwlockattr_t"] [:: std :: mem :: align_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Offset of field: pthread_rwlockattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __size) - 0usize] ; ["Offset of field: pthread_rwlockattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlockattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlockattr_t {{ union }}") } } pub type pthread_spinlock_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrier_t { pub __size : [:: std :: os :: raw :: c_char ; 32usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrier_t"] [:: std :: mem :: size_of :: < pthread_barrier_t > () - 32usize] ; ["Alignment of pthread_barrier_t"] [:: std :: mem :: align_of :: < pthread_barrier_t > () - 8usize] ; ["Offset of field: pthread_barrier_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __size) - 0usize] ; ["Offset of field: pthread_barrier_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrier_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrier_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrierattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrierattr_t"] [:: std :: mem :: size_of :: < pthread_barrierattr_t > () - 4usize] ; ["Alignment of pthread_barrierattr_t"] [:: std :: mem :: align_of :: < pthread_barrierattr_t > () - 4usize] ; ["Offset of field: pthread_barrierattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __size) - 0usize] ; ["Offset of field: pthread_barrierattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrierattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrierattr_t {{ union }}") } } unsafe extern "C" { pub fn random () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srandom (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn initstate (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn setstate (__statebuf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct random_data { pub fptr : * mut i32 , pub rptr : * mut i32 , pub state : * mut i32 , pub rand_type : :: std :: os :: raw :: c_int , pub rand_deg : :: std :: os :: raw :: c_int , pub rand_sep : :: std :: os :: raw :: c_int , pub end_ptr : * mut i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of random_data"] [:: std :: mem :: size_of :: < random_data > () - 48usize] ; ["Alignment of random_data"] [:: std :: mem :: align_of :: < random_data > () - 8usize] ; ["Offset of field: random_data::fptr"] [:: std :: mem :: offset_of ! (random_data , fptr) - 0usize] ; ["Offset of field: random_data::rptr"] [:: std :: mem :: offset_of ! (random_data , rptr) - 8usize] ; ["Offset of field: random_data::state"] [:: std :: mem :: offset_of ! (random_data , state) - 16usize] ; ["Offset of field: random_data::rand_type"] [:: std :: mem :: offset_of ! (random_data , rand_type) - 24usize] ; ["Offset of field: random_data::rand_deg"] [:: std :: mem :: offset_of ! (random_data , rand_deg) - 28usize] ; ["Offset of field: random_data::rand_sep"] [:: std :: mem :: offset_of ! (random_data , rand_sep) - 32usize] ; ["Offset of field: random_data::end_ptr"] [:: std :: mem :: offset_of ! (random_data , end_ptr) - 40usize] ; } ; unsafe extern "C" { pub fn random_r (__buf : * mut random_data , __result : * mut i32) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srandom_r (__seed : :: std :: os :: raw :: c_uint , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn initstate_r (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setstate_r (__statebuf : * mut :: std :: os :: raw :: c_char , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rand () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn rand_r (__seed : * mut :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn drand48 () -> f64 ; } unsafe extern "C" { pub fn erand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> f64 ; } unsafe extern "C" { pub fn lrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn nrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn mrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn jrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srand48 (__seedval : :: std :: os :: raw :: c_long) ; } unsafe extern "C" { pub fn seed48 (__seed16v : * mut :: std :: os :: raw :: c_ushort) -> * mut :: std :: os :: raw :: c_ushort ; } unsafe extern "C" { pub fn lcong48 (__param : * mut :: std :: os :: raw :: c_ushort) ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct drand48_data { pub __x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __old_x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __c : :: std :: os :: raw :: c_ushort , pub __init : :: std :: os :: raw :: c_ushort , pub __a : :: std :: os :: raw :: c_ulonglong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of drand48_data"] [:: std :: mem :: size_of :: < drand48_data > () - 24usize] ; ["Alignment of drand48_data"] [:: std :: mem :: align_of :: < drand48_data > () - 8usize] ; ["Offset of field: drand48_data::__x"] [:: std :: mem :: offset_of ! (drand48_data , __x) - 0usize] ; ["Offset of field: drand48_data::__old_x"] [:: std :: mem :: offset_of ! (drand48_data , __old_x) - 6usize] ; ["Offset of field: drand48_data::__c"] [:: std :: mem :: offset_of ! (drand48_data , __c) - 12usize] ; ["Offset of field: drand48_data::__init"] [:: std :: mem :: offset_of ! (drand48_data , __init) - 14usize] ; ["Offset of field: drand48_data::__a"] [:: std :: mem :: offset_of ! (drand48_data , __a) - 16usize] ; } ; unsafe extern "C" { pub fn drand48_r (__buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn erand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn nrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn jrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand48_r (__seedval : :: std :: os :: raw :: c_long , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn seed48_r (__seed16v : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lcong48_r (__param : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn arc4random () -> __uint32_t ; } unsafe extern "C" { pub fn arc4random_buf (__buf : * mut :: std :: os :: raw :: c_void , __size : usize) ; } unsafe extern "C" { pub fn arc4random_uniform (__upper_bound : __uint32_t) -> __uint32_t ; } unsafe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn calloc (__nmemb : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn free (__ptr : * mut :: std :: os :: raw :: c_void) ; } unsafe extern "C" { pub fn reallocarray (__ptr : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn alloca (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn valloc (__size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn posix_memalign (__memptr : * mut * mut :: std :: os :: raw :: c_void , __alignment : usize , __size : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn aligned_alloc (__alignment : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn abort () -> ! ; } unsafe extern "C" { pub fn atexit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn at_quick_exit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn on_exit (__func : :: std :: option :: Option < unsafe extern "C" fn (__status : :: std :: os :: raw :: c_int , __arg : * mut :: std :: os :: raw :: c_void) > , __arg : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn quick_exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn _Exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn getenv (__name : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn putenv (__string : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setenv (__name : * const :: std :: os :: raw :: c_char , __value : * const :: std :: os :: raw :: c_char , __replace : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn unsetenv (__name : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearenv () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mktemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn mkstemp (__template : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkstemps (__template : * mut :: std :: os :: raw :: c_char , __suffixlen : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkdtemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn system (__command : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn realpath (__name : * const :: std :: os :: raw :: c_char , __resolved : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } pub type __compar_fn_t = :: std :: option :: Option < unsafe extern "C" fn (arg1 : * const :: std :: os :: raw :: c_void , arg2 : * const :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; unsafe extern "C" { pub fn bsearch (__key : * const :: std :: os :: raw :: c_void , __base : * const :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn qsort (__base : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) ; } unsafe extern "C" { pub fn abs (__x : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn labs (__x : :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn llabs (__x : :: std :: os :: raw :: c_longlong) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn div (__numer : :: std :: os :: raw :: c_int , __denom : :: std :: os :: raw :: c_int) -> div_t ; } unsafe extern "C" { pub fn ldiv (__numer : :: std :: os :: raw :: c_long , __denom : :: std :: os :: raw :: c_long) -> ldiv_t ; } unsafe extern "C" { pub fn lldiv (__numer : :: std :: os :: raw :: c_longlong , __denom : :: std :: os :: raw :: c_longlong) -> lldiv_t ; } unsafe extern "C" { pub fn ecvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn gcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qecvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qfcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qgcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn ecvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fcvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qecvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qfcvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mblen (__s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbtowc (__pwc : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn wctomb (__s : * mut :: std :: os :: raw :: c_char , __wchar : wchar_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbstowcs (__pwcs : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> usize ; } unsafe extern "C" { pub fn wcstombs (__s : * mut :: std :: os :: raw :: c_char , __pwcs : * const wchar_t , __n : usize) -> usize ; } unsafe extern "C" { pub fn rpmatch (__response : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getsubopt (__optionp : * mut * mut :: std :: os :: raw :: c_char , __tokens : * const * mut :: std :: os :: raw :: c_char , __valuep : * mut * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getloadavg (__loadavg : * mut f64 , __nelem : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } # [repr (C)] # [derive (Copy , Clone)] pub struct __mbstate_t { pub __count : :: std :: os :: raw :: c_int , pub __value : __mbstate_t__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union __mbstate_t__bindgen_ty_1 { pub __wch : :: std :: os :: raw :: c_uint , pub __wchb : [:: std :: os :: raw :: c_char ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: size_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Alignment of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: align_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wch"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wch) - 0usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wchb"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wchb) - 0usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t"] [:: std :: mem :: size_of :: < __mbstate_t > () - 8usize] ; ["Alignment of __mbstate_t"] [:: std :: mem :: align_of :: < __mbstate_t > () - 4usize] ; ["Offset of field: __mbstate_t::__count"] [:: std :: mem :: offset_of ! (__mbstate_t , __count) - 0usize] ; ["Offset of field: __mbstate_t::__value"] [:: std :: mem :: offset_of ! (__mbstate_t , __value) - 4usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t {{ __count: {:?}, __value: {:?} }}" , self . __count , self . __value) } } # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos_t { pub __pos : __off_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos_t"] [:: std :: mem :: size_of :: < _G_fpos_t > () - 16usize] ; ["Alignment of _G_fpos_t"] [:: std :: mem :: align_of :: < _G_fpos_t > () - 8usize] ; ["Offset of field: _G_fpos_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos_t , __pos) - 0usize] ; ["Offset of field: _G_fpos_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos_t = _G_fpos_t ; # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos64_t { pub __pos : __off64_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos64_t"] [:: std :: mem :: size_of :: < _G_fpos64_t > () - 16usize] ; ["Alignment of _G_fpos64_t"] [:: std :: mem :: align_of :: < _G_fpos64_t > () - 8usize] ; ["Offset of field: _G_fpos64_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __pos) - 0usize] ; ["Offset of field: _G_fpos64_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos64_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos64_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos64_t = _G_fpos64_t ; pub type __FILE = _IO_FILE ; pub type FILE = _IO_FILE ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_marker { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_codecvt { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_wide_data { _unused : [u8 ; 0] , } pub type _IO_lock_t = :: std :: os :: raw :: c_void ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_FILE { pub _flags : :: std :: os :: raw :: c_int , pub _IO_read_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_read_end : * mut :: std :: os :: raw :: c_char , pub _IO_read_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_write_end : * mut :: std :: os :: raw :: c_char , pub _IO_buf_base : * mut :: std :: os :: raw :: c_char , pub _IO_buf_end : * mut :: std :: os :: raw :: c_char , pub _IO_save_base : * mut :: std :: os :: raw :: c_char , pub _IO_backup_base : * mut :: std :: os :: raw :: c_char , pub _IO_save_end : * mut :: std :: os :: raw :: c_char , pub _markers : * mut _IO_marker , pub _chain : * mut _IO_FILE , pub _fileno : :: std :: os :: raw :: c_int , pub _bitfield_align_1 : [u32 ; 0] , pub _bitfield_1 : __BindgenBitfieldUnit < [u8 ; 3usize] > , pub _short_backupbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _old_offset : __off_t , pub _cur_column : :: std :: os :: raw :: c_ushort , pub _vtable_offset : :: std :: os :: raw :: c_schar , pub _shortbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _lock : * mut _IO_lock_t , pub _offset : __off64_t , pub _codecvt : * mut _IO_codecvt , pub _wide_data : * mut _IO_wide_data , pub _freeres_list : * mut _IO_FILE , pub _freeres_buf : * mut :: std :: os :: raw :: c_void , pub _prevchain : * mut * mut _IO_FILE , pub _mode : :: std :: os :: raw :: c_int , pub _unused3 : :: std :: os :: raw :: c_int , pub _total_written : __uint64_t , pub _unused2 : [:: std :: os :: raw :: c_char ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_FILE"] [:: std :: mem :: size_of :: < _IO_FILE > () - 216usize] ; ["Alignment of _IO_FILE"] [:: std :: mem :: align_of :: < _IO_FILE > () - 8usize] ; ["Offset of field: _IO_FILE::_flags"] [:: std :: mem :: offset_of ! (_IO_FILE , _flags) - 0usize] ; ["Offset of field: _IO_FILE::_IO_read_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_ptr) - 8usize] ; ["Offset of field: _IO_FILE::_IO_read_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_end) - 16usize] ; ["Offset of field: _IO_FILE::_IO_read_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_base) - 24usize] ; ["Offset of field: _IO_FILE::_IO_write_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_base) - 32usize] ; ["Offset of field: _IO_FILE::_IO_write_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_ptr) - 40usize] ; ["Offset of field: _IO_FILE::_IO_write_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_end) - 48usize] ; ["Offset of field: _IO_FILE::_IO_buf_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_base) - 56usize] ; ["Offset of field: _IO_FILE::_IO_buf_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_end) - 64usize] ; ["Offset of field: _IO_FILE::_IO_save_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_base) - 72usize] ; ["Offset of field: _IO_FILE::_IO_backup_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_backup_base) - 80usize] ; ["Offset of field: _IO_FILE::_IO_save_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_end) - 88usize] ; ["Offset of field: _IO_FILE::_markers"] [:: std :: mem :: offset_of ! (_IO_FILE , _markers) - 96usize] ; ["Offset of field: _IO_FILE::_chain"] [:: std :: mem :: offset_of ! (_IO_FILE , _chain) - 104usize] ; ["Offset of field: _IO_FILE::_fileno"] [:: std :: mem :: offset_of ! (_IO_FILE , _fileno) - 112usize] ; ["Offset of field: _IO_FILE::_short_backupbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _short_backupbuf) - 119usize] ; ["Offset of field: _IO_FILE::_old_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _old_offset) - 120usize] ; ["Offset of field: _IO_FILE::_cur_column"] [:: std :: mem :: offset_of ! (_IO_FILE , _cur_column) - 128usize] ; ["Offset of field: _IO_FILE::_vtable_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _vtable_offset) - 130usize] ; ["Offset of field: _IO_FILE::_shortbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _shortbuf) - 131usize] ; ["Offset of field: _IO_FILE::_lock"] [:: std :: mem :: offset_of ! (_IO_FILE , _lock) - 136usize] ; ["Offset of field: _IO_FILE::_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _offset) - 144usize] ; ["Offset of field: _IO_FILE::_codecvt"] [:: std :: mem :: offset_of ! (_IO_FILE , _codecvt) - 152usize] ; ["Offset of field: _IO_FILE::_wide_data"] [:: std :: mem :: offset_of ! (_IO_FILE , _wide_data) - 160usize] ; ["Offset of field: _IO_FILE::_freeres_list"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_list) - 168usize] ; ["Offset of field: _IO_FILE::_freeres_buf"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_buf) - 176usize] ; ["Offset of field: _IO_FILE::_prevchain"] [:: std :: mem :: offset_of ! (_IO_FILE , _prevchain) - 184usize] ; ["Offset of field: _IO_FILE::_mode"] [:: std :: mem :: offset_of ! (_IO_FILE , _mode) - 192usize] ; ["Offset of field: _IO_FILE::_unused3"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused3) - 196usize] ; ["Offset of field: _IO_FILE::_total_written"] [:: std :: mem :: offset_of ! (_IO_FILE , _total_written) - 200usize] ; ["Offset of field: _IO_FILE::_unused2"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused2) - 208usize] ; } ; impl _IO_FILE { # [inline] pub fn _flags2 (& self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set__flags2 (& mut self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; self . _bitfield_1 . set (0usize , 24u8 , val as u64) } } # [inline] pub unsafe fn _flags2_raw (this : * const Self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } } # [inline] pub unsafe fn set__flags2_raw (this : * mut Self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_set (:: std :: ptr :: addr_of_mut ! ((* this) . _bitfield_1) , 0usize , 24u8 , val as u64 ,) } } # [inline] pub fn new_bitfield_1 (_flags2 : :: std :: os :: raw :: c_int) -> __BindgenBitfieldUnit < [u8 ; 3usize] > { let mut __bindgen_bitfield_unit : __BindgenBitfieldUnit < [u8 ; 3usize] > = Default :: default () ; __bindgen_bitfield_unit . set (0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_unit } } pub type cookie_read_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * mut :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_write_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * const :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_seek_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __pos : * mut __off64_t , __w : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int > ; pub type cookie_close_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_cookie_io_functions_t { pub read : cookie_read_function_t , pub write : cookie_write_function_t , pub seek : cookie_seek_function_t , pub close : cookie_close_function_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_cookie_io_functions_t"] [:: std :: mem :: size_of :: < _IO_cookie_io_functions_t > () - 32usize] ; ["Alignment of _IO_cookie_io_functions_t"] [:: std :: mem :: align_of :: < _IO_cookie_io_functions_t > () - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::read"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , read) - 0usize] ; ["Offset of field: _IO_cookie_io_functions_t::write"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , write) - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::seek"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , seek) - 16usize] ; ["Offset of field: _IO_cookie_io_functions_t::close"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , close) - 24usize] ; } ; pub type cookie_io_functions_t = _IO_cookie_io_functions_t ; pub type fpos_t = __fpos_t ; unsafe extern "C" { pub static mut stdin : * mut FILE ; } unsafe extern "C" { pub static mut stdout : * mut FILE ; } unsafe extern "C" { pub static mut stderr : * mut FILE ; } unsafe extern "C" { pub fn remove (__filename : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rename (__old : * const :: std :: os :: raw :: c_char , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn renameat (__oldfd : :: std :: os :: raw :: c_int , __old : * const :: std :: os :: raw :: c_char , __newfd : :: std :: os :: raw :: c_int , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn tmpfile () -> * mut FILE ; } unsafe extern "C" { pub fn tmpnam (arg1 : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tmpnam_r (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tempnam (__dir : * const :: std :: os :: raw :: c_char , __pfx : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fflush (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fflush_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn freopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> * mut FILE ; } unsafe extern "C" { pub fn fdopen (__fd : :: std :: os :: raw :: c_int , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn fopencookie (__magic_cookie : * mut :: std :: os :: raw :: c_void , __modes : * const :: std :: os :: raw :: c_char , __io_funcs : cookie_io_functions_t) -> * mut FILE ; } unsafe extern "C" { pub fn fmemopen (__s : * mut :: std :: os :: raw :: c_void , __len : usize , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn open_memstream (__bufloc : * mut * mut :: std :: os :: raw :: c_char , __sizeloc : * mut usize) -> * mut FILE ; } unsafe extern "C" { pub fn setbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn setvbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __modes : :: std :: os :: raw :: c_int , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setbuffer (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __size : usize) ; } unsafe extern "C" { pub fn setlinebuf (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fprintf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn printf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfprintf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vprintf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn snprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsnprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vasprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __f : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vdprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn dprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fscanf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn scanf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_fscanf"] pub fn fscanf1 (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_scanf"] pub fn scanf1 (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_sscanf"] pub fn sscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfscanf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vscanf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vfscanf"] pub fn vfscanf1 (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vscanf"] pub fn vscanf1 (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vsscanf"] pub fn vsscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar_unlocked () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar_unlocked (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getw (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putw (__w : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgets (__s : * mut :: std :: os :: raw :: c_char , __n : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn __getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getline (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn fputs (__s : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn puts (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ungetc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fread (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __stream : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fwrite (__ptr : * const :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __s : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fread_unlocked (__ptr : * mut :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fwrite_unlocked (__ptr : * const :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fseek (__stream : * mut FILE , __off : :: std :: os :: raw :: c_long , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftell (__stream : * mut FILE) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn rewind (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fseeko (__stream : * mut FILE , __off : __off_t , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftello (__stream : * mut FILE) -> __off_t ; } unsafe extern "C" { pub fn fgetpos (__stream : * mut FILE , __pos : * mut fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fsetpos (__stream : * mut FILE , __pos : * const fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr_unlocked (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn perror (__s : * const :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn fileno (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fileno_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn popen (__command : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn ctermid (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn flockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn ftrylockfile (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn funlockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn __uflow (arg1 : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __overflow (arg1 : * mut FILE , arg2 : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } pub type int_least8_t = __int_least8_t ; pub type int_least16_t = __int_least16_t ; pub type int_least32_t = __int_least32_t ; pub type int_least64_t = __int_least64_t ; pub type uint_least8_t = __uint_least8_t ; pub type uint_least16_t = __uint_least16_t ; pub type uint_least32_t = __uint_least32_t ; pub type uint_least64_t = __uint_least64_t ; pub type int_fast8_t = :: std :: os :: raw :: c_schar ; pub type int_fast16_t = :: std :: os :: raw :: c_long ; pub type int_fast32_t = :: std :: os :: raw :: c_long ; pub type int_fast64_t = :: std :: os :: raw :: c_long ; pub type uint_fast8_t = :: std :: os :: raw :: c_uchar ; pub type uint_fast16_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast32_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast64_t = :: std :: os :: raw :: c_ulong ; pub type intmax_t = __intmax_t ; pub type uintmax_t = __uintmax_t ; pub type __gwchar_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct imaxdiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of imaxdiv_t"] [:: std :: mem :: size_of :: < imaxdiv_t > () - 16usize] ; ["Alignment of imaxdiv_t"] [:: std :: mem :: align_of :: < imaxdiv_t > () - 8usize] ; ["Offset of field: imaxdiv_t::quot"] [:: std :: mem :: offset_of ! (imaxdiv_t , quot) - 0usize] ; ["Offset of field: imaxdiv_t::rem"] [:: std :: mem :: offset_of ! (imaxdiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn imaxabs (__n : intmax_t) -> intmax_t ; } unsafe extern "C" { pub fn imaxdiv (__numer : intmax_t , __denom : intmax_t) -> imaxdiv_t ; } unsafe extern "C" { pub fn strtoimax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn strtoumax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } unsafe extern "C" { pub fn wcstoimax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn wcstoumax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } pub type csh = usize ; # [repr (u32)] # [doc = " Architecture type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_arch { # [doc = "< ARM architecture (including Thumb, Thumb-2)"] CS_ARCH_ARM = 0 , # [doc = "< ARM-64, also called AArch64"] CS_ARCH_ARM64 = 1 , # [doc = "< Mips architecture"] CS_ARCH_MIPS = 2 , # [doc = "< X86 architecture (including x86 & x86-64)"] CS_ARCH_X86 = 3 , # [doc = "< PowerPC architecture"] CS_ARCH_PPC = 4 , # [doc = "< Sparc architecture"] CS_ARCH_SPARC = 5 , # [doc = "< SystemZ architecture"] CS_ARCH_SYSZ = 6 , # [doc = "< XCore architecture"] CS_ARCH_XCORE = 7 , # [doc = "< 68K architecture"] CS_ARCH_M68K = 8 , # [doc = "< TMS320C64x architecture"] CS_ARCH_TMS320C64X = 9 , # [doc = "< 680X architecture"] CS_ARCH_M680X = 10 , # [doc = "< Ethereum architecture"] CS_ARCH_EVM = 11 , # [doc = "< MOS65XX architecture (including MOS6502)"] CS_ARCH_MOS65XX = 12 , # [doc = "< WebAssembly architecture"] CS_ARCH_WASM = 13 , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] CS_ARCH_BPF = 14 , # [doc = "< RISCV architecture"] CS_ARCH_RISCV = 15 , # [doc = "< SH architecture"] CS_ARCH_SH = 16 , # [doc = "< TriCore architecture"] CS_ARCH_TRICORE = 17 , CS_ARCH_MAX = 18 , CS_ARCH_ALL = 65535 , } # [doc = "< little-endian mode (default mode)"] pub const cs_mode_CS_MODE_LITTLE_ENDIAN : cs_mode = 0 ; # [doc = "< 32-bit ARM"] pub const cs_mode_CS_MODE_ARM : cs_mode = 0 ; # [doc = "< 16-bit mode (X86)"] pub const cs_mode_CS_MODE_16 : cs_mode = 2 ; # [doc = "< 32-bit mode (X86)"] pub const cs_mode_CS_MODE_32 : cs_mode = 4 ; # [doc = "< 64-bit mode (X86, PPC)"] pub const cs_mode_CS_MODE_64 : cs_mode = 8 ; # [doc = "< ARM's Thumb mode, including Thumb-2"] pub const cs_mode_CS_MODE_THUMB : cs_mode = 16 ; # [doc = "< ARM's Cortex-M series"] pub const cs_mode_CS_MODE_MCLASS : cs_mode = 32 ; # [doc = "< ARMv8 A32 encodings for ARM"] pub const cs_mode_CS_MODE_V8 : cs_mode = 64 ; # [doc = "< MicroMips mode (MIPS)"] pub const cs_mode_CS_MODE_MICRO : cs_mode = 16 ; # [doc = "< Mips III ISA"] pub const cs_mode_CS_MODE_MIPS3 : cs_mode = 32 ; # [doc = "< Mips32r6 ISA"] pub const cs_mode_CS_MODE_MIPS32R6 : cs_mode = 64 ; # [doc = "< Mips II ISA"] pub const cs_mode_CS_MODE_MIPS2 : cs_mode = 128 ; # [doc = "< SparcV9 mode (Sparc)"] pub const cs_mode_CS_MODE_V9 : cs_mode = 16 ; # [doc = "< Quad Processing eXtensions mode (PPC)"] pub const cs_mode_CS_MODE_QPX : cs_mode = 16 ; # [doc = "< Signal Processing Engine mode (PPC)"] pub const cs_mode_CS_MODE_SPE : cs_mode = 32 ; # [doc = "< Book-E mode (PPC)"] pub const cs_mode_CS_MODE_BOOKE : cs_mode = 64 ; # [doc = "< Paired-singles mode (PPC)"] pub const cs_mode_CS_MODE_PS : cs_mode = 128 ; # [doc = "< M68K 68000 mode"] pub const cs_mode_CS_MODE_M68K_000 : cs_mode = 2 ; # [doc = "< M68K 68010 mode"] pub const cs_mode_CS_MODE_M68K_010 : cs_mode = 4 ; # [doc = "< M68K 68020 mode"] pub const cs_mode_CS_MODE_M68K_020 : cs_mode = 8 ; # [doc = "< M68K 68030 mode"] pub const cs_mode_CS_MODE_M68K_030 : cs_mode = 16 ; # [doc = "< M68K 68040 mode"] pub const cs_mode_CS_MODE_M68K_040 : cs_mode = 32 ; # [doc = "< M68K 68060 mode"] pub const cs_mode_CS_MODE_M68K_060 : cs_mode = 64 ; # [doc = "< big-endian mode"] pub const cs_mode_CS_MODE_BIG_ENDIAN : cs_mode = 2147483648 ; # [doc = "< Mips32 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS32 : cs_mode = 4 ; # [doc = "< Mips64 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS64 : cs_mode = 8 ; # [doc = "< M680X Hitachi 6301,6303 mode"] pub const cs_mode_CS_MODE_M680X_6301 : cs_mode = 2 ; # [doc = "< M680X Hitachi 6309 mode"] pub const cs_mode_CS_MODE_M680X_6309 : cs_mode = 4 ; # [doc = "< M680X Motorola 6800,6802 mode"] pub const cs_mode_CS_MODE_M680X_6800 : cs_mode = 8 ; # [doc = "< M680X Motorola 6801,6803 mode"] pub const cs_mode_CS_MODE_M680X_6801 : cs_mode = 16 ; # [doc = "< M680X Motorola/Freescale 6805 mode"] pub const cs_mode_CS_MODE_M680X_6805 : cs_mode = 32 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"] pub const cs_mode_CS_MODE_M680X_6808 : cs_mode = 64 ; # [doc = "< M680X Motorola 6809 mode"] pub const cs_mode_CS_MODE_M680X_6809 : cs_mode = 128 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"] pub const cs_mode_CS_MODE_M680X_6811 : cs_mode = 256 ; # [doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"] pub const cs_mode_CS_MODE_M680X_CPU12 : cs_mode = 512 ; # [doc = "< M680X Freescale/NXP HCS08 mode"] pub const cs_mode_CS_MODE_M680X_HCS08 : cs_mode = 1024 ; # [doc = "< Classic BPF mode (default)"] pub const cs_mode_CS_MODE_BPF_CLASSIC : cs_mode = 0 ; # [doc = "< Extended BPF mode"] pub const cs_mode_CS_MODE_BPF_EXTENDED : cs_mode = 1 ; # [doc = "< RISCV RV32G"] pub const cs_mode_CS_MODE_RISCV32 : cs_mode = 1 ; # [doc = "< RISCV RV64G"] pub const cs_mode_CS_MODE_RISCV64 : cs_mode = 2 ; # [doc = "< RISCV compressed instructure mode"] pub const cs_mode_CS_MODE_RISCVC : cs_mode = 4 ; # [doc = "< MOS65XXX MOS 6502"] pub const cs_mode_CS_MODE_MOS65XX_6502 : cs_mode = 2 ; # [doc = "< MOS65XXX WDC 65c02"] pub const cs_mode_CS_MODE_MOS65XX_65C02 : cs_mode = 4 ; # [doc = "< MOS65XXX WDC W65c02"] pub const cs_mode_CS_MODE_MOS65XX_W65C02 : cs_mode = 8 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m/x"] pub const cs_mode_CS_MODE_MOS65XX_65816 : cs_mode = 16 ; # [doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_M : cs_mode = 32 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_X : cs_mode = 64 ; pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_MX : cs_mode = 96 ; # [doc = "< SH2"] pub const cs_mode_CS_MODE_SH2 : cs_mode = 2 ; # [doc = "< SH2A"] pub const cs_mode_CS_MODE_SH2A : cs_mode = 4 ; # [doc = "< SH3"] pub const cs_mode_CS_MODE_SH3 : cs_mode = 8 ; # [doc = "< SH4"] pub const cs_mode_CS_MODE_SH4 : cs_mode = 16 ; # [doc = "< SH4A"] pub const cs_mode_CS_MODE_SH4A : cs_mode = 32 ; # [doc = "< w/ FPU"] pub const cs_mode_CS_MODE_SHFPU : cs_mode = 64 ; # [doc = "< w/ DSP"] pub const cs_mode_CS_MODE_SHDSP : cs_mode = 128 ; # [doc = "< Tricore 1.1"] pub const cs_mode_CS_MODE_TRICORE_110 : cs_mode = 2 ; # [doc = "< Tricore 1.2"] pub const cs_mode_CS_MODE_TRICORE_120 : cs_mode = 4 ; # [doc = "< Tricore 1.3"] pub const cs_mode_CS_MODE_TRICORE_130 : cs_mode = 8 ; # [doc = "< Tricore 1.3.1"] pub const cs_mode_CS_MODE_TRICORE_131 : cs_mode = 16 ; # [doc = "< Tricore 1.6"] pub const cs_mode_CS_MODE_TRICORE_160 : cs_mode = 32 ; # [doc = "< Tricore 1.6.1"] pub const cs_mode_CS_MODE_TRICORE_161 : cs_mode = 64 ; # [doc = "< Tricore 1.6.2"] pub const cs_mode_CS_MODE_TRICORE_162 : cs_mode = 128 ; # [doc = " Mode type"] pub type cs_mode = :: std :: os :: raw :: c_uint ; pub type cs_malloc_t = :: std :: option :: Option < unsafe extern "C" fn (size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_calloc_t = :: std :: option :: Option < unsafe extern "C" fn (nmemb : usize , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_realloc_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_free_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void) > ; pub type cs_vsnprintf_t = :: std :: option :: Option < unsafe extern "C" fn (str_ : * mut :: std :: os :: raw :: c_char , size : usize , format : * const :: std :: os :: raw :: c_char , ap : * mut __va_list_tag) -> :: std :: os :: raw :: c_int > ; # [doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mem { pub malloc : cs_malloc_t , pub calloc : cs_calloc_t , pub realloc : cs_realloc_t , pub free : cs_free_t , pub vsnprintf : cs_vsnprintf_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mem"] [:: std :: mem :: size_of :: < cs_opt_mem > () - 40usize] ; ["Alignment of cs_opt_mem"] [:: std :: mem :: align_of :: < cs_opt_mem > () - 8usize] ; ["Offset of field: cs_opt_mem::malloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , malloc) - 0usize] ; ["Offset of field: cs_opt_mem::calloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , calloc) - 8usize] ; ["Offset of field: cs_opt_mem::realloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , realloc) - 16usize] ; ["Offset of field: cs_opt_mem::free"] [:: std :: mem :: offset_of ! (cs_opt_mem , free) - 24usize] ; ["Offset of field: cs_opt_mem::vsnprintf"] [:: std :: mem :: offset_of ! (cs_opt_mem , vsnprintf) - 32usize] ; } ; # [doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mnem { # [doc = " ID of instruction to be customized."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Customized instruction mnemonic."] pub mnemonic : * const :: std :: os :: raw :: c_char , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mnem"] [:: std :: mem :: size_of :: < cs_opt_mnem > () - 16usize] ; ["Alignment of cs_opt_mnem"] [:: std :: mem :: align_of :: < cs_opt_mnem > () - 8usize] ; ["Offset of field: cs_opt_mnem::id"] [:: std :: mem :: offset_of ! (cs_opt_mnem , id) - 0usize] ; ["Offset of field: cs_opt_mnem::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_mnem , mnemonic) - 8usize] ; } ; # [repr (u32)] # [doc = " Runtime option for the disassembled engine"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_type { # [doc = "< No option specified"] CS_OPT_INVALID = 0 , # [doc = "< Assembly output syntax"] CS_OPT_SYNTAX = 1 , # [doc = "< Break down instruction structure into details"] CS_OPT_DETAIL = 2 , # [doc = "< Change engine's mode at run-time"] CS_OPT_MODE = 3 , # [doc = "< User-defined dynamic memory related functions"] CS_OPT_MEM = 4 , # [doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."] CS_OPT_SKIPDATA = 5 , # [doc = "< Setup user-defined function for SKIPDATA option"] CS_OPT_SKIPDATA_SETUP = 6 , # [doc = "< Customize instruction mnemonic"] CS_OPT_MNEMONIC = 7 , # [doc = "< print immediate operands in unsigned form"] CS_OPT_UNSIGNED = 8 , # [doc = "< ARM, prints branch immediates without offset."] CS_OPT_NO_BRANCH_OFFSET = 9 , } impl cs_opt_value { pub const CS_OPT_SYNTAX_DEFAULT : cs_opt_value = cs_opt_value :: CS_OPT_OFF ; } impl cs_opt_value { pub const CS_OPT_SYNTAX_NOREGNAME : cs_opt_value = cs_opt_value :: CS_OPT_ON ; } # [repr (u32)] # [doc = " Runtime option value (associated with option type above)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_value { # [doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."] CS_OPT_OFF = 0 , # [doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."] CS_OPT_ON = 3 , # [doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_INTEL = 1 , # [doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_ATT = 2 , # [doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_MASM = 4 , # [doc = "< MOS65XX use $ as hex prefix"] CS_OPT_SYNTAX_MOTOROLA = 5 , } # [repr (u32)] # [doc = " Common instruction operand types - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_op_type { # [doc = "< uninitialized/invalid operand."] CS_OP_INVALID = 0 , # [doc = "< Register operand."] CS_OP_REG = 1 , # [doc = "< Immediate operand."] CS_OP_IMM = 2 , # [doc = "< Memory operand. Can be ORed with another operand type."] CS_OP_MEM = 3 , # [doc = "< Floating-Point operand."] CS_OP_FP = 4 , } # [repr (u32)] # [doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_ac_type { # [doc = "< Uninitialized/invalid access type."] CS_AC_INVALID = 0 , # [doc = "< Operand read from memory or register."] CS_AC_READ = 1 , # [doc = "< Operand write to memory or register."] CS_AC_WRITE = 2 , } # [repr (u32)] # [doc = " Common instruction groups - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_group_type { # [doc = "< uninitialized/invalid group."] CS_GRP_INVALID = 0 , # [doc = "< all jump instructions (conditional+direct+indirect jumps)"] CS_GRP_JUMP = 1 , # [doc = "< all call instructions"] CS_GRP_CALL = 2 , # [doc = "< all return instructions"] CS_GRP_RET = 3 , # [doc = "< all interrupt instructions (int+syscall)"] CS_GRP_INT = 4 , # [doc = "< all interrupt return instructions"] CS_GRP_IRET = 5 , # [doc = "< all privileged instructions"] CS_GRP_PRIVILEGE = 6 , # [doc = "< all relative branching instructions"] CS_GRP_BRANCH_RELATIVE = 7 , } # [doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."] pub type cs_skipdata_cb_t = :: std :: option :: Option < unsafe extern "C" fn (code : * const u8 , code_size : usize , offset : usize , user_data : * mut :: std :: os :: raw :: c_void) -> usize > ; # [doc = " User-customized setup for SKIPDATA option"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_skipdata { # [doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."] pub mnemonic : * const :: std :: os :: raw :: c_char , # [doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes.\n TriCore: 2 bytes."] pub callback : cs_skipdata_cb_t , # [doc = " User-defined data to be passed to @callback function pointer."] pub user_data : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_skipdata"] [:: std :: mem :: size_of :: < cs_opt_skipdata > () - 24usize] ; ["Alignment of cs_opt_skipdata"] [:: std :: mem :: align_of :: < cs_opt_skipdata > () - 8usize] ; ["Offset of field: cs_opt_skipdata::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , mnemonic) - 0usize] ; ["Offset of field: cs_opt_skipdata::callback"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , callback) - 8usize] ; ["Offset of field: cs_opt_skipdata::user_data"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , user_data) - 16usize] ; } ; # [repr (u32)] # [doc = " ARM shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_shifter { ARM_SFT_INVALID = 0 , # [doc = "< shift with immediate const"] ARM_SFT_ASR = 1 , # [doc = "< shift with immediate const"] ARM_SFT_LSL = 2 , # [doc = "< shift with immediate const"] ARM_SFT_LSR = 3 , # [doc = "< shift with immediate const"] ARM_SFT_ROR = 4 , # [doc = "< shift with immediate const"] ARM_SFT_RRX = 5 , # [doc = "< shift with register"] ARM_SFT_ASR_REG = 6 , # [doc = "< shift with register"] ARM_SFT_LSL_REG = 7 , # [doc = "< shift with register"] ARM_SFT_LSR_REG = 8 , # [doc = "< shift with register"] ARM_SFT_ROR_REG = 9 , # [doc = "< shift with register"] ARM_SFT_RRX_REG = 10 , } # [repr (u32)] # [doc = " ARM condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cc { ARM_CC_INVALID = 0 , # [doc = "< Equal                      Equal"] ARM_CC_EQ = 1 , # [doc = "< Not equal                  Not equal, or unordered"] ARM_CC_NE = 2 , # [doc = "< Carry set                  >, ==, or unordered"] ARM_CC_HS = 3 , # [doc = "< Carry clear                Less than"] ARM_CC_LO = 4 , # [doc = "< Minus, negative            Less than"] ARM_CC_MI = 5 , # [doc = "< Plus, positive or zero     >, ==, or unordered"] ARM_CC_PL = 6 , # [doc = "< Overflow                   Unordered"] ARM_CC_VS = 7 , # [doc = "< No overflow                Not unordered"] ARM_CC_VC = 8 , # [doc = "< Unsigned higher            Greater than, or unordered"] ARM_CC_HI = 9 , # [doc = "< Unsigned lower or same     Less than or equal"] ARM_CC_LS = 10 , # [doc = "< Greater than or equal      Greater than or equal"] ARM_CC_GE = 11 , # [doc = "< Less than                  Less than, or unordered"] ARM_CC_LT = 12 , # [doc = "< Greater than               Greater than"] ARM_CC_GT = 13 , # [doc = "< Less than or equal         <, ==, or unordered"] ARM_CC_LE = 14 , # [doc = "< Always (unconditional)     Always (unconditional)"] ARM_CC_AL = 15 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_sysreg { # [doc = " Special registers for MSR"] ARM_SYSREG_INVALID = 0 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_C = 1 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_X = 2 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_S = 4 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_F = 8 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_C = 16 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_X = 32 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_S = 64 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_F = 128 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR = 256 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_G = 257 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQ = 258 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQG = 259 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR = 260 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_G = 261 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQG = 262 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQ = 263 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR = 264 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_G = 265 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQG = 266 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQ = 267 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR = 268 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_G = 269 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQG = 270 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQ = 271 , # [doc = " Special registers for MSR"] ARM_SYSREG_IPSR = 272 , # [doc = " Special registers for MSR"] ARM_SYSREG_EPSR = 273 , # [doc = " Special registers for MSR"] ARM_SYSREG_IEPSR = 274 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP = 275 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP = 276 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK = 277 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI = 278 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_MAX = 279 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK = 280 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL = 281 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM = 282 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM = 283 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP_NS = 284 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP_NS = 285 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM_NS = 286 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM_NS = 287 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK_NS = 288 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_NS = 289 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK_NS = 290 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL_NS = 291 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_NS = 292 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_USR = 293 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_USR = 294 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_USR = 295 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_USR = 296 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_USR = 297 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_USR = 298 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_USR = 299 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_FIQ = 300 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_FIQ = 301 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_FIQ = 302 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_FIQ = 303 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_FIQ = 304 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_FIQ = 305 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_FIQ = 306 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_IRQ = 307 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_IRQ = 308 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_SVC = 309 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_SVC = 310 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_ABT = 311 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_ABT = 312 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_UND = 313 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_UND = 314 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_MON = 315 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_MON = 316 , # [doc = " Special registers for MSR"] ARM_SYSREG_ELR_HYP = 317 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_HYP = 318 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_FIQ = 319 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_IRQ = 320 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_SVC = 321 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_ABT = 322 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_UND = 323 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_MON = 324 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_HYP = 325 , } # [repr (u32)] # [doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_mem_barrier { ARM_MB_INVALID = 0 , ARM_MB_RESERVED_0 = 1 , ARM_MB_OSHLD = 2 , ARM_MB_OSHST = 3 , ARM_MB_OSH = 4 , ARM_MB_RESERVED_4 = 5 , ARM_MB_NSHLD = 6 , ARM_MB_NSHST = 7 , ARM_MB_NSH = 8 , ARM_MB_RESERVED_8 = 9 , ARM_MB_ISHLD = 10 , ARM_MB_ISHST = 11 , ARM_MB_ISH = 12 , ARM_MB_RESERVED_12 = 13 , ARM_MB_LD = 14 , ARM_MB_ST = 15 , ARM_MB_SY = 16 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM_OP_FP = 4 , # [doc = "< C-Immediate (coprocessor registers)"] ARM_OP_CIMM = 64 , # [doc = "< P-Immediate (coprocessor registers)"] ARM_OP_PIMM = 65 , # [doc = "< operand for SETEND instruction"] ARM_OP_SETEND = 66 , # [doc = "< MSR/MRS special register operand"] ARM_OP_SYSREG = 67 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_setend_type { # [doc = "< Uninitialized."] ARM_SETEND_INVALID = 0 , # [doc = "< BE operand."] ARM_SETEND_BE = 1 , # [doc = "< LE operand"] ARM_SETEND_LE = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0 , ARM_CPSMODE_IE = 2 , ARM_CPSMODE_ID = 3 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0 , ARM_CPSFLAG_F = 1 , ARM_CPSFLAG_I = 2 , ARM_CPSFLAG_A = 4 , # [doc = "< no flag"] ARM_CPSFLAG_NONE = 16 , } # [repr (u32)] # [doc = " Data type for elements of vector instructions."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0 , ARM_VECTORDATA_I8 = 1 , ARM_VECTORDATA_I16 = 2 , ARM_VECTORDATA_I32 = 3 , ARM_VECTORDATA_I64 = 4 , ARM_VECTORDATA_S8 = 5 , ARM_VECTORDATA_S16 = 6 , ARM_VECTORDATA_S32 = 7 , ARM_VECTORDATA_S64 = 8 , ARM_VECTORDATA_U8 = 9 , ARM_VECTORDATA_U16 = 10 , ARM_VECTORDATA_U32 = 11 , ARM_VECTORDATA_U64 = 12 , ARM_VECTORDATA_P8 = 13 , ARM_VECTORDATA_F16 = 14 , ARM_VECTORDATA_F32 = 15 , ARM_VECTORDATA_F64 = 16 , ARM_VECTORDATA_F16F64 = 17 , ARM_VECTORDATA_F64F16 = 18 , ARM_VECTORDATA_F32F16 = 19 , ARM_VECTORDATA_F16F32 = 20 , ARM_VECTORDATA_F64F32 = 21 , ARM_VECTORDATA_F32F64 = 22 , ARM_VECTORDATA_S32F32 = 23 , ARM_VECTORDATA_U32F32 = 24 , ARM_VECTORDATA_F32S32 = 25 , ARM_VECTORDATA_F32U32 = 26 , ARM_VECTORDATA_F64S16 = 27 , ARM_VECTORDATA_F32S16 = 28 , ARM_VECTORDATA_F64S32 = 29 , ARM_VECTORDATA_S16F64 = 30 , ARM_VECTORDATA_S16F32 = 31 , ARM_VECTORDATA_S32F64 = 32 , ARM_VECTORDATA_U16F64 = 33 , ARM_VECTORDATA_U16F32 = 34 , ARM_VECTORDATA_U32F64 = 35 , ARM_VECTORDATA_F64U16 = 36 , ARM_VECTORDATA_F32U16 = 37 , ARM_VECTORDATA_F64U32 = 38 , ARM_VECTORDATA_F16U16 = 39 , ARM_VECTORDATA_U16F16 = 40 , ARM_VECTORDATA_F16U32 = 41 , ARM_VECTORDATA_U32F16 = 42 , } impl arm_reg { pub const ARM_REG_R13 : arm_reg = arm_reg :: ARM_REG_SP ; } impl arm_reg { pub const ARM_REG_R14 : arm_reg = arm_reg :: ARM_REG_LR ; } impl arm_reg { pub const ARM_REG_R15 : arm_reg = arm_reg :: ARM_REG_PC ; } impl arm_reg { pub const ARM_REG_SB : arm_reg = arm_reg :: ARM_REG_R9 ; } impl arm_reg { pub const ARM_REG_SL : arm_reg = arm_reg :: ARM_REG_R10 ; } impl arm_reg { pub const ARM_REG_FP : arm_reg = arm_reg :: ARM_REG_R11 ; } impl arm_reg { pub const ARM_REG_IP : arm_reg = arm_reg :: ARM_REG_R12 ; } # [repr (u32)] # [doc = " ARM registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_reg { ARM_REG_INVALID = 0 , ARM_REG_APSR = 1 , ARM_REG_APSR_NZCV = 2 , ARM_REG_CPSR = 3 , ARM_REG_FPEXC = 4 , ARM_REG_FPINST = 5 , ARM_REG_FPSCR = 6 , ARM_REG_FPSCR_NZCV = 7 , ARM_REG_FPSID = 8 , ARM_REG_ITSTATE = 9 , ARM_REG_LR = 10 , ARM_REG_PC = 11 , ARM_REG_SP = 12 , ARM_REG_SPSR = 13 , ARM_REG_D0 = 14 , ARM_REG_D1 = 15 , ARM_REG_D2 = 16 , ARM_REG_D3 = 17 , ARM_REG_D4 = 18 , ARM_REG_D5 = 19 , ARM_REG_D6 = 20 , ARM_REG_D7 = 21 , ARM_REG_D8 = 22 , ARM_REG_D9 = 23 , ARM_REG_D10 = 24 , ARM_REG_D11 = 25 , ARM_REG_D12 = 26 , ARM_REG_D13 = 27 , ARM_REG_D14 = 28 , ARM_REG_D15 = 29 , ARM_REG_D16 = 30 , ARM_REG_D17 = 31 , ARM_REG_D18 = 32 , ARM_REG_D19 = 33 , ARM_REG_D20 = 34 , ARM_REG_D21 = 35 , ARM_REG_D22 = 36 , ARM_REG_D23 = 37 , ARM_REG_D24 = 38 , ARM_REG_D25 = 39 , ARM_REG_D26 = 40 , ARM_REG_D27 = 41 , ARM_REG_D28 = 42 , ARM_REG_D29 = 43 , ARM_REG_D30 = 44 , ARM_REG_D31 = 45 , ARM_REG_FPINST2 = 46 , ARM_REG_MVFR0 = 47 , ARM_REG_MVFR1 = 48 , ARM_REG_MVFR2 = 49 , ARM_REG_Q0 = 50 , ARM_REG_Q1 = 51 , ARM_REG_Q2 = 52 , ARM_REG_Q3 = 53 , ARM_REG_Q4 = 54 , ARM_REG_Q5 = 55 , ARM_REG_Q6 = 56 , ARM_REG_Q7 = 57 , ARM_REG_Q8 = 58 , ARM_REG_Q9 = 59 , ARM_REG_Q10 = 60 , ARM_REG_Q11 = 61 , ARM_REG_Q12 = 62 , ARM_REG_Q13 = 63 , ARM_REG_Q14 = 64 , ARM_REG_Q15 = 65 , ARM_REG_R0 = 66 , ARM_REG_R1 = 67 , ARM_REG_R2 = 68 , ARM_REG_R3 = 69 , ARM_REG_R4 = 70 , ARM_REG_R5 = 71 , ARM_REG_R6 = 72 , ARM_REG_R7 = 73 , ARM_REG_R8 = 74 , ARM_REG_R9 = 75 , ARM_REG_R10 = 76 , ARM_REG_R11 = 77 , ARM_REG_R12 = 78 , ARM_REG_S0 = 79 , ARM_REG_S1 = 80 , ARM_REG_S2 = 81 , ARM_REG_S3 = 82 , ARM_REG_S4 = 83 , ARM_REG_S5 = 84 , ARM_REG_S6 = 85 , ARM_REG_S7 = 86 , ARM_REG_S8 = 87 , ARM_REG_S9 = 88 , ARM_REG_S10 = 89 , ARM_REG_S11 = 90 , ARM_REG_S12 = 91 , ARM_REG_S13 = 92 , ARM_REG_S14 = 93 , ARM_REG_S15 = 94 , ARM_REG_S16 = 95 , ARM_REG_S17 = 96 , ARM_REG_S18 = 97 , ARM_REG_S19 = 98 , ARM_REG_S20 = 99 , ARM_REG_S21 = 100 , ARM_REG_S22 = 101 , ARM_REG_S23 = 102 , ARM_REG_S24 = 103 , ARM_REG_S25 = 104 , ARM_REG_S26 = 105 , ARM_REG_S27 = 106 , ARM_REG_S28 = 107 , ARM_REG_S29 = 108 , ARM_REG_S30 = 109 , ARM_REG_S31 = 110 , ARM_REG_ENDING = 111 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm_op_mem { # [doc = "< base register"] pub base : arm_reg , # [doc = "< index register"] pub index : arm_reg , # [doc = "< scale for index register (can be 1, or -1)"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_int , # [doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"] pub lshift : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm_op_mem"] [:: std :: mem :: size_of :: < arm_op_mem > () - 20usize] ; ["Alignment of arm_op_mem"] [:: std :: mem :: align_of :: < arm_op_mem > () - 4usize] ; ["Offset of field: arm_op_mem::base"] [:: std :: mem :: offset_of ! (arm_op_mem , base) - 0usize] ; ["Offset of field: arm_op_mem::index"] [:: std :: mem :: offset_of ! (arm_op_mem , index) - 4usize] ; ["Offset of field: arm_op_mem::scale"] [:: std :: mem :: offset_of ! (arm_op_mem , scale) - 8usize] ; ["Offset of field: arm_op_mem::disp"] [:: std :: mem :: offset_of ! (arm_op_mem , disp) - 12usize] ; ["Offset of field: arm_op_mem::lshift"] [:: std :: mem :: offset_of ! (arm_op_mem , lshift) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm_op { # [doc = "< Vector Index for some vector operands (or -1 if irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , pub shift : cs_arm_op__bindgen_ty_1 , # [doc = "< operand type"] pub type_ : arm_op_type , pub __bindgen_anon_1 : cs_arm_op__bindgen_ty_2 , # [doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."] pub subtracted : bool , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"] pub neon_lane : i8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm_op__bindgen_ty_1 { pub type_ : arm_shifter , pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm_op__bindgen_ty_2 { # [doc = "< register value for REG/SYSREG operand"] pub reg : :: std :: os :: raw :: c_int , # [doc = "< immediate value for C-IMM, P-IMM or IMM operand"] pub imm : i32 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm_op_mem , # [doc = "< SETEND instruction's operand type"] pub setend : arm_setend_type , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_2 > () - 24usize] ; ["Alignment of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::setend"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , setend) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op"] [:: std :: mem :: size_of :: < cs_arm_op > () - 48usize] ; ["Alignment of cs_arm_op"] [:: std :: mem :: align_of :: < cs_arm_op > () - 8usize] ; ["Offset of field: cs_arm_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm_op , vector_index) - 0usize] ; ["Offset of field: cs_arm_op::shift"] [:: std :: mem :: offset_of ! (cs_arm_op , shift) - 4usize] ; ["Offset of field: cs_arm_op::type_"] [:: std :: mem :: offset_of ! (cs_arm_op , type_) - 12usize] ; ["Offset of field: cs_arm_op::subtracted"] [:: std :: mem :: offset_of ! (cs_arm_op , subtracted) - 40usize] ; ["Offset of field: cs_arm_op::access"] [:: std :: mem :: offset_of ! (cs_arm_op , access) - 41usize] ; ["Offset of field: cs_arm_op::neon_lane"] [:: std :: mem :: offset_of ! (cs_arm_op , neon_lane) - 42usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm { # [doc = "< User-mode registers to be loaded (for LDM/STM instructions)"] pub usermode : bool , # [doc = "< Scalar size for vector instructions"] pub vector_size : :: std :: os :: raw :: c_int , # [doc = "< Data type for elements of vector instructions"] pub vector_data : arm_vectordata_type , # [doc = "< CPS mode for CPS instruction"] pub cps_mode : arm_cpsmode_type , # [doc = "< CPS mode for CPS instruction"] pub cps_flag : arm_cpsflag_type , # [doc = "< conditional code for this insn"] pub cc : arm_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn write-back?"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = "< Option for some memory barrier instructions"] pub mem_barrier : arm_mem_barrier , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm_op ; 36usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm"] [:: std :: mem :: size_of :: < cs_arm > () - 1768usize] ; ["Alignment of cs_arm"] [:: std :: mem :: align_of :: < cs_arm > () - 8usize] ; ["Offset of field: cs_arm::usermode"] [:: std :: mem :: offset_of ! (cs_arm , usermode) - 0usize] ; ["Offset of field: cs_arm::vector_size"] [:: std :: mem :: offset_of ! (cs_arm , vector_size) - 4usize] ; ["Offset of field: cs_arm::vector_data"] [:: std :: mem :: offset_of ! (cs_arm , vector_data) - 8usize] ; ["Offset of field: cs_arm::cps_mode"] [:: std :: mem :: offset_of ! (cs_arm , cps_mode) - 12usize] ; ["Offset of field: cs_arm::cps_flag"] [:: std :: mem :: offset_of ! (cs_arm , cps_flag) - 16usize] ; ["Offset of field: cs_arm::cc"] [:: std :: mem :: offset_of ! (cs_arm , cc) - 20usize] ; ["Offset of field: cs_arm::update_flags"] [:: std :: mem :: offset_of ! (cs_arm , update_flags) - 24usize] ; ["Offset of field: cs_arm::writeback"] [:: std :: mem :: offset_of ! (cs_arm , writeback) - 25usize] ; ["Offset of field: cs_arm::post_index"] [:: std :: mem :: offset_of ! (cs_arm , post_index) - 26usize] ; ["Offset of field: cs_arm::mem_barrier"] [:: std :: mem :: offset_of ! (cs_arm , mem_barrier) - 28usize] ; ["Offset of field: cs_arm::op_count"] [:: std :: mem :: offset_of ! (cs_arm , op_count) - 32usize] ; ["Offset of field: cs_arm::operands"] [:: std :: mem :: offset_of ! (cs_arm , operands) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_arm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . post_index , self . mem_barrier , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn { ARM_INS_INVALID = 0 , ARM_INS_ADC = 1 , ARM_INS_ADD = 2 , ARM_INS_ADDW = 3 , ARM_INS_ADR = 4 , ARM_INS_AESD = 5 , ARM_INS_AESE = 6 , ARM_INS_AESIMC = 7 , ARM_INS_AESMC = 8 , ARM_INS_AND = 9 , ARM_INS_ASR = 10 , ARM_INS_B = 11 , ARM_INS_BFC = 12 , ARM_INS_BFI = 13 , ARM_INS_BIC = 14 , ARM_INS_BKPT = 15 , ARM_INS_BL = 16 , ARM_INS_BLX = 17 , ARM_INS_BLXNS = 18 , ARM_INS_BX = 19 , ARM_INS_BXJ = 20 , ARM_INS_BXNS = 21 , ARM_INS_CBNZ = 22 , ARM_INS_CBZ = 23 , ARM_INS_CDP = 24 , ARM_INS_CDP2 = 25 , ARM_INS_CLREX = 26 , ARM_INS_CLZ = 27 , ARM_INS_CMN = 28 , ARM_INS_CMP = 29 , ARM_INS_CPS = 30 , ARM_INS_CRC32B = 31 , ARM_INS_CRC32CB = 32 , ARM_INS_CRC32CH = 33 , ARM_INS_CRC32CW = 34 , ARM_INS_CRC32H = 35 , ARM_INS_CRC32W = 36 , ARM_INS_CSDB = 37 , ARM_INS_DBG = 38 , ARM_INS_DCPS1 = 39 , ARM_INS_DCPS2 = 40 , ARM_INS_DCPS3 = 41 , ARM_INS_DFB = 42 , ARM_INS_DMB = 43 , ARM_INS_DSB = 44 , ARM_INS_EOR = 45 , ARM_INS_ERET = 46 , ARM_INS_ESB = 47 , ARM_INS_FADDD = 48 , ARM_INS_FADDS = 49 , ARM_INS_FCMPZD = 50 , ARM_INS_FCMPZS = 51 , ARM_INS_FCONSTD = 52 , ARM_INS_FCONSTS = 53 , ARM_INS_FLDMDBX = 54 , ARM_INS_FLDMIAX = 55 , ARM_INS_FMDHR = 56 , ARM_INS_FMDLR = 57 , ARM_INS_FMSTAT = 58 , ARM_INS_FSTMDBX = 59 , ARM_INS_FSTMIAX = 60 , ARM_INS_FSUBD = 61 , ARM_INS_FSUBS = 62 , ARM_INS_HINT = 63 , ARM_INS_HLT = 64 , ARM_INS_HVC = 65 , ARM_INS_ISB = 66 , ARM_INS_IT = 67 , ARM_INS_LDA = 68 , ARM_INS_LDAB = 69 , ARM_INS_LDAEX = 70 , ARM_INS_LDAEXB = 71 , ARM_INS_LDAEXD = 72 , ARM_INS_LDAEXH = 73 , ARM_INS_LDAH = 74 , ARM_INS_LDC = 75 , ARM_INS_LDC2 = 76 , ARM_INS_LDC2L = 77 , ARM_INS_LDCL = 78 , ARM_INS_LDM = 79 , ARM_INS_LDMDA = 80 , ARM_INS_LDMDB = 81 , ARM_INS_LDMIB = 82 , ARM_INS_LDR = 83 , ARM_INS_LDRB = 84 , ARM_INS_LDRBT = 85 , ARM_INS_LDRD = 86 , ARM_INS_LDREX = 87 , ARM_INS_LDREXB = 88 , ARM_INS_LDREXD = 89 , ARM_INS_LDREXH = 90 , ARM_INS_LDRH = 91 , ARM_INS_LDRHT = 92 , ARM_INS_LDRSB = 93 , ARM_INS_LDRSBT = 94 , ARM_INS_LDRSH = 95 , ARM_INS_LDRSHT = 96 , ARM_INS_LDRT = 97 , ARM_INS_LSL = 98 , ARM_INS_LSR = 99 , ARM_INS_MCR = 100 , ARM_INS_MCR2 = 101 , ARM_INS_MCRR = 102 , ARM_INS_MCRR2 = 103 , ARM_INS_MLA = 104 , ARM_INS_MLS = 105 , ARM_INS_MOV = 106 , ARM_INS_MOVS = 107 , ARM_INS_MOVT = 108 , ARM_INS_MOVW = 109 , ARM_INS_MRC = 110 , ARM_INS_MRC2 = 111 , ARM_INS_MRRC = 112 , ARM_INS_MRRC2 = 113 , ARM_INS_MRS = 114 , ARM_INS_MSR = 115 , ARM_INS_MUL = 116 , ARM_INS_MVN = 117 , ARM_INS_NEG = 118 , ARM_INS_NOP = 119 , ARM_INS_ORN = 120 , ARM_INS_ORR = 121 , ARM_INS_PKHBT = 122 , ARM_INS_PKHTB = 123 , ARM_INS_PLD = 124 , ARM_INS_PLDW = 125 , ARM_INS_PLI = 126 , ARM_INS_POP = 127 , ARM_INS_PUSH = 128 , ARM_INS_QADD = 129 , ARM_INS_QADD16 = 130 , ARM_INS_QADD8 = 131 , ARM_INS_QASX = 132 , ARM_INS_QDADD = 133 , ARM_INS_QDSUB = 134 , ARM_INS_QSAX = 135 , ARM_INS_QSUB = 136 , ARM_INS_QSUB16 = 137 , ARM_INS_QSUB8 = 138 , ARM_INS_RBIT = 139 , ARM_INS_REV = 140 , ARM_INS_REV16 = 141 , ARM_INS_REVSH = 142 , ARM_INS_RFEDA = 143 , ARM_INS_RFEDB = 144 , ARM_INS_RFEIA = 145 , ARM_INS_RFEIB = 146 , ARM_INS_ROR = 147 , ARM_INS_RRX = 148 , ARM_INS_RSB = 149 , ARM_INS_RSC = 150 , ARM_INS_SADD16 = 151 , ARM_INS_SADD8 = 152 , ARM_INS_SASX = 153 , ARM_INS_SBC = 154 , ARM_INS_SBFX = 155 , ARM_INS_SDIV = 156 , ARM_INS_SEL = 157 , ARM_INS_SETEND = 158 , ARM_INS_SETPAN = 159 , ARM_INS_SEV = 160 , ARM_INS_SEVL = 161 , ARM_INS_SG = 162 , ARM_INS_SHA1C = 163 , ARM_INS_SHA1H = 164 , ARM_INS_SHA1M = 165 , ARM_INS_SHA1P = 166 , ARM_INS_SHA1SU0 = 167 , ARM_INS_SHA1SU1 = 168 , ARM_INS_SHA256H = 169 , ARM_INS_SHA256H2 = 170 , ARM_INS_SHA256SU0 = 171 , ARM_INS_SHA256SU1 = 172 , ARM_INS_SHADD16 = 173 , ARM_INS_SHADD8 = 174 , ARM_INS_SHASX = 175 , ARM_INS_SHSAX = 176 , ARM_INS_SHSUB16 = 177 , ARM_INS_SHSUB8 = 178 , ARM_INS_SMC = 179 , ARM_INS_SMLABB = 180 , ARM_INS_SMLABT = 181 , ARM_INS_SMLAD = 182 , ARM_INS_SMLADX = 183 , ARM_INS_SMLAL = 184 , ARM_INS_SMLALBB = 185 , ARM_INS_SMLALBT = 186 , ARM_INS_SMLALD = 187 , ARM_INS_SMLALDX = 188 , ARM_INS_SMLALTB = 189 , ARM_INS_SMLALTT = 190 , ARM_INS_SMLATB = 191 , ARM_INS_SMLATT = 192 , ARM_INS_SMLAWB = 193 , ARM_INS_SMLAWT = 194 , ARM_INS_SMLSD = 195 , ARM_INS_SMLSDX = 196 , ARM_INS_SMLSLD = 197 , ARM_INS_SMLSLDX = 198 , ARM_INS_SMMLA = 199 , ARM_INS_SMMLAR = 200 , ARM_INS_SMMLS = 201 , ARM_INS_SMMLSR = 202 , ARM_INS_SMMUL = 203 , ARM_INS_SMMULR = 204 , ARM_INS_SMUAD = 205 , ARM_INS_SMUADX = 206 , ARM_INS_SMULBB = 207 , ARM_INS_SMULBT = 208 , ARM_INS_SMULL = 209 , ARM_INS_SMULTB = 210 , ARM_INS_SMULTT = 211 , ARM_INS_SMULWB = 212 , ARM_INS_SMULWT = 213 , ARM_INS_SMUSD = 214 , ARM_INS_SMUSDX = 215 , ARM_INS_SRSDA = 216 , ARM_INS_SRSDB = 217 , ARM_INS_SRSIA = 218 , ARM_INS_SRSIB = 219 , ARM_INS_SSAT = 220 , ARM_INS_SSAT16 = 221 , ARM_INS_SSAX = 222 , ARM_INS_SSUB16 = 223 , ARM_INS_SSUB8 = 224 , ARM_INS_STC = 225 , ARM_INS_STC2 = 226 , ARM_INS_STC2L = 227 , ARM_INS_STCL = 228 , ARM_INS_STL = 229 , ARM_INS_STLB = 230 , ARM_INS_STLEX = 231 , ARM_INS_STLEXB = 232 , ARM_INS_STLEXD = 233 , ARM_INS_STLEXH = 234 , ARM_INS_STLH = 235 , ARM_INS_STM = 236 , ARM_INS_STMDA = 237 , ARM_INS_STMDB = 238 , ARM_INS_STMIB = 239 , ARM_INS_STR = 240 , ARM_INS_STRB = 241 , ARM_INS_STRBT = 242 , ARM_INS_STRD = 243 , ARM_INS_STREX = 244 , ARM_INS_STREXB = 245 , ARM_INS_STREXD = 246 , ARM_INS_STREXH = 247 , ARM_INS_STRH = 248 , ARM_INS_STRHT = 249 , ARM_INS_STRT = 250 , ARM_INS_SUB = 251 , ARM_INS_SUBS = 252 , ARM_INS_SUBW = 253 , ARM_INS_SVC = 254 , ARM_INS_SWP = 255 , ARM_INS_SWPB = 256 , ARM_INS_SXTAB = 257 , ARM_INS_SXTAB16 = 258 , ARM_INS_SXTAH = 259 , ARM_INS_SXTB = 260 , ARM_INS_SXTB16 = 261 , ARM_INS_SXTH = 262 , ARM_INS_TBB = 263 , ARM_INS_TBH = 264 , ARM_INS_TEQ = 265 , ARM_INS_TRAP = 266 , ARM_INS_TSB = 267 , ARM_INS_TST = 268 , ARM_INS_TT = 269 , ARM_INS_TTA = 270 , ARM_INS_TTAT = 271 , ARM_INS_TTT = 272 , ARM_INS_UADD16 = 273 , ARM_INS_UADD8 = 274 , ARM_INS_UASX = 275 , ARM_INS_UBFX = 276 , ARM_INS_UDF = 277 , ARM_INS_UDIV = 278 , ARM_INS_UHADD16 = 279 , ARM_INS_UHADD8 = 280 , ARM_INS_UHASX = 281 , ARM_INS_UHSAX = 282 , ARM_INS_UHSUB16 = 283 , ARM_INS_UHSUB8 = 284 , ARM_INS_UMAAL = 285 , ARM_INS_UMLAL = 286 , ARM_INS_UMULL = 287 , ARM_INS_UQADD16 = 288 , ARM_INS_UQADD8 = 289 , ARM_INS_UQASX = 290 , ARM_INS_UQSAX = 291 , ARM_INS_UQSUB16 = 292 , ARM_INS_UQSUB8 = 293 , ARM_INS_USAD8 = 294 , ARM_INS_USADA8 = 295 , ARM_INS_USAT = 296 , ARM_INS_USAT16 = 297 , ARM_INS_USAX = 298 , ARM_INS_USUB16 = 299 , ARM_INS_USUB8 = 300 , ARM_INS_UXTAB = 301 , ARM_INS_UXTAB16 = 302 , ARM_INS_UXTAH = 303 , ARM_INS_UXTB = 304 , ARM_INS_UXTB16 = 305 , ARM_INS_UXTH = 306 , ARM_INS_VABA = 307 , ARM_INS_VABAL = 308 , ARM_INS_VABD = 309 , ARM_INS_VABDL = 310 , ARM_INS_VABS = 311 , ARM_INS_VACGE = 312 , ARM_INS_VACGT = 313 , ARM_INS_VACLE = 314 , ARM_INS_VACLT = 315 , ARM_INS_VADD = 316 , ARM_INS_VADDHN = 317 , ARM_INS_VADDL = 318 , ARM_INS_VADDW = 319 , ARM_INS_VAND = 320 , ARM_INS_VBIC = 321 , ARM_INS_VBIF = 322 , ARM_INS_VBIT = 323 , ARM_INS_VBSL = 324 , ARM_INS_VCADD = 325 , ARM_INS_VCEQ = 326 , ARM_INS_VCGE = 327 , ARM_INS_VCGT = 328 , ARM_INS_VCLE = 329 , ARM_INS_VCLS = 330 , ARM_INS_VCLT = 331 , ARM_INS_VCLZ = 332 , ARM_INS_VCMLA = 333 , ARM_INS_VCMP = 334 , ARM_INS_VCMPE = 335 , ARM_INS_VCNT = 336 , ARM_INS_VCVT = 337 , ARM_INS_VCVTA = 338 , ARM_INS_VCVTB = 339 , ARM_INS_VCVTM = 340 , ARM_INS_VCVTN = 341 , ARM_INS_VCVTP = 342 , ARM_INS_VCVTR = 343 , ARM_INS_VCVTT = 344 , ARM_INS_VDIV = 345 , ARM_INS_VDUP = 346 , ARM_INS_VEOR = 347 , ARM_INS_VEXT = 348 , ARM_INS_VFMA = 349 , ARM_INS_VFMS = 350 , ARM_INS_VFNMA = 351 , ARM_INS_VFNMS = 352 , ARM_INS_VHADD = 353 , ARM_INS_VHSUB = 354 , ARM_INS_VINS = 355 , ARM_INS_VJCVT = 356 , ARM_INS_VLD1 = 357 , ARM_INS_VLD2 = 358 , ARM_INS_VLD3 = 359 , ARM_INS_VLD4 = 360 , ARM_INS_VLDMDB = 361 , ARM_INS_VLDMIA = 362 , ARM_INS_VLDR = 363 , ARM_INS_VLLDM = 364 , ARM_INS_VLSTM = 365 , ARM_INS_VMAX = 366 , ARM_INS_VMAXNM = 367 , ARM_INS_VMIN = 368 , ARM_INS_VMINNM = 369 , ARM_INS_VMLA = 370 , ARM_INS_VMLAL = 371 , ARM_INS_VMLS = 372 , ARM_INS_VMLSL = 373 , ARM_INS_VMOV = 374 , ARM_INS_VMOVL = 375 , ARM_INS_VMOVN = 376 , ARM_INS_VMOVX = 377 , ARM_INS_VMRS = 378 , ARM_INS_VMSR = 379 , ARM_INS_VMUL = 380 , ARM_INS_VMULL = 381 , ARM_INS_VMVN = 382 , ARM_INS_VNEG = 383 , ARM_INS_VNMLA = 384 , ARM_INS_VNMLS = 385 , ARM_INS_VNMUL = 386 , ARM_INS_VORN = 387 , ARM_INS_VORR = 388 , ARM_INS_VPADAL = 389 , ARM_INS_VPADD = 390 , ARM_INS_VPADDL = 391 , ARM_INS_VPMAX = 392 , ARM_INS_VPMIN = 393 , ARM_INS_VPOP = 394 , ARM_INS_VPUSH = 395 , ARM_INS_VQABS = 396 , ARM_INS_VQADD = 397 , ARM_INS_VQDMLAL = 398 , ARM_INS_VQDMLSL = 399 , ARM_INS_VQDMULH = 400 , ARM_INS_VQDMULL = 401 , ARM_INS_VQMOVN = 402 , ARM_INS_VQMOVUN = 403 , ARM_INS_VQNEG = 404 , ARM_INS_VQRDMLAH = 405 , ARM_INS_VQRDMLSH = 406 , ARM_INS_VQRDMULH = 407 , ARM_INS_VQRSHL = 408 , ARM_INS_VQRSHRN = 409 , ARM_INS_VQRSHRUN = 410 , ARM_INS_VQSHL = 411 , ARM_INS_VQSHLU = 412 , ARM_INS_VQSHRN = 413 , ARM_INS_VQSHRUN = 414 , ARM_INS_VQSUB = 415 , ARM_INS_VRADDHN = 416 , ARM_INS_VRECPE = 417 , ARM_INS_VRECPS = 418 , ARM_INS_VREV16 = 419 , ARM_INS_VREV32 = 420 , ARM_INS_VREV64 = 421 , ARM_INS_VRHADD = 422 , ARM_INS_VRINTA = 423 , ARM_INS_VRINTM = 424 , ARM_INS_VRINTN = 425 , ARM_INS_VRINTP = 426 , ARM_INS_VRINTR = 427 , ARM_INS_VRINTX = 428 , ARM_INS_VRINTZ = 429 , ARM_INS_VRSHL = 430 , ARM_INS_VRSHR = 431 , ARM_INS_VRSHRN = 432 , ARM_INS_VRSQRTE = 433 , ARM_INS_VRSQRTS = 434 , ARM_INS_VRSRA = 435 , ARM_INS_VRSUBHN = 436 , ARM_INS_VSDOT = 437 , ARM_INS_VSELEQ = 438 , ARM_INS_VSELGE = 439 , ARM_INS_VSELGT = 440 , ARM_INS_VSELVS = 441 , ARM_INS_VSHL = 442 , ARM_INS_VSHLL = 443 , ARM_INS_VSHR = 444 , ARM_INS_VSHRN = 445 , ARM_INS_VSLI = 446 , ARM_INS_VSQRT = 447 , ARM_INS_VSRA = 448 , ARM_INS_VSRI = 449 , ARM_INS_VST1 = 450 , ARM_INS_VST2 = 451 , ARM_INS_VST3 = 452 , ARM_INS_VST4 = 453 , ARM_INS_VSTMDB = 454 , ARM_INS_VSTMIA = 455 , ARM_INS_VSTR = 456 , ARM_INS_VSUB = 457 , ARM_INS_VSUBHN = 458 , ARM_INS_VSUBL = 459 , ARM_INS_VSUBW = 460 , ARM_INS_VSWP = 461 , ARM_INS_VTBL = 462 , ARM_INS_VTBX = 463 , ARM_INS_VTRN = 464 , ARM_INS_VTST = 465 , ARM_INS_VUDOT = 466 , ARM_INS_VUZP = 467 , ARM_INS_VZIP = 468 , ARM_INS_WFE = 469 , ARM_INS_WFI = 470 , ARM_INS_YIELD = 471 , ARM_INS_ENDING = 472 , } # [repr (u32)] # [doc = " Group of ARM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] ARM_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] ARM_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM_GRP_BRANCH_RELATIVE = 7 , ARM_GRP_CRYPTO = 128 , ARM_GRP_DATABARRIER = 129 , ARM_GRP_DIVIDE = 130 , ARM_GRP_FPARMV8 = 131 , ARM_GRP_MULTPRO = 132 , ARM_GRP_NEON = 133 , ARM_GRP_T2EXTRACTPACK = 134 , ARM_GRP_THUMB2DSP = 135 , ARM_GRP_TRUSTZONE = 136 , ARM_GRP_V4T = 137 , ARM_GRP_V5T = 138 , ARM_GRP_V5TE = 139 , ARM_GRP_V6 = 140 , ARM_GRP_V6T2 = 141 , ARM_GRP_V7 = 142 , ARM_GRP_V8 = 143 , ARM_GRP_VFP2 = 144 , ARM_GRP_VFP3 = 145 , ARM_GRP_VFP4 = 146 , ARM_GRP_ARM = 147 , ARM_GRP_MCLASS = 148 , ARM_GRP_NOTMCLASS = 149 , ARM_GRP_THUMB = 150 , ARM_GRP_THUMB1ONLY = 151 , ARM_GRP_THUMB2 = 152 , ARM_GRP_PREV8 = 153 , ARM_GRP_FPVMLX = 154 , ARM_GRP_MULOPS = 155 , ARM_GRP_CRC = 156 , ARM_GRP_DPVFP = 157 , ARM_GRP_V6M = 158 , ARM_GRP_VIRTUALIZATION = 159 , ARM_GRP_ENDING = 160 , } # [repr (u32)] # [doc = " ARM64 shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_shifter { ARM64_SFT_INVALID = 0 , ARM64_SFT_LSL = 1 , ARM64_SFT_MSL = 2 , ARM64_SFT_LSR = 3 , ARM64_SFT_ASR = 4 , ARM64_SFT_ROR = 5 , } # [repr (u32)] # [doc = " ARM64 extender type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_extender { ARM64_EXT_INVALID = 0 , ARM64_EXT_UXTB = 1 , ARM64_EXT_UXTH = 2 , ARM64_EXT_UXTW = 3 , ARM64_EXT_UXTX = 4 , ARM64_EXT_SXTB = 5 , ARM64_EXT_SXTH = 6 , ARM64_EXT_SXTW = 7 , ARM64_EXT_SXTX = 8 , } # [repr (u32)] # [doc = " ARM64 condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_cc { ARM64_CC_INVALID = 0 , # [doc = "< Equal"] ARM64_CC_EQ = 1 , # [doc = "< Not equal:                 Not equal, or unordered"] ARM64_CC_NE = 2 , # [doc = "< Unsigned higher or same:   >, ==, or unordered"] ARM64_CC_HS = 3 , # [doc = "< Unsigned lower or same:    Less than"] ARM64_CC_LO = 4 , # [doc = "< Minus, negative:           Less than"] ARM64_CC_MI = 5 , # [doc = "< Plus, positive or zero:    >, ==, or unordered"] ARM64_CC_PL = 6 , # [doc = "< Overflow:                  Unordered"] ARM64_CC_VS = 7 , # [doc = "< No overflow:               Ordered"] ARM64_CC_VC = 8 , # [doc = "< Unsigned higher:           Greater than, or unordered"] ARM64_CC_HI = 9 , # [doc = "< Unsigned lower or same:    Less than or equal"] ARM64_CC_LS = 10 , # [doc = "< Greater than or equal:     Greater than or equal"] ARM64_CC_GE = 11 , # [doc = "< Less than:                 Less than, or unordered"] ARM64_CC_LT = 12 , # [doc = "< Signed greater than:       Greater than"] ARM64_CC_GT = 13 , # [doc = "< Signed less than or equal: <, ==, or unordered"] ARM64_CC_LE = 14 , # [doc = "< Always (unconditional):    Always (unconditional)"] ARM64_CC_AL = 15 , # [doc = "< Always (unconditional):   Always (unconditional)"] ARM64_CC_NV = 16 , } impl arm64_sysreg { pub const ARM64_SYSREG_DBGDTRTX_EL0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_DBGDTRRX_EL0 ; } impl arm64_sysreg { pub const ARM64_SYSREG_TRCEXTINSELR0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TRCEXTINSELR ; } impl arm64_sysreg { pub const ARM64_SYSREG_VSCTLR_EL2 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TTBR0_EL2 ; } # [repr (u32)] # [doc = " System registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sysreg { ARM64_SYSREG_INVALID = 0 , ARM64_SYSREG_ACCDATA_EL1 = 50821 , ARM64_SYSREG_ACTLR_EL1 = 49281 , ARM64_SYSREG_ACTLR_EL2 = 57473 , ARM64_SYSREG_ACTLR_EL3 = 61569 , ARM64_SYSREG_AFSR0_EL1 = 49800 , ARM64_SYSREG_AFSR0_EL12 = 60040 , ARM64_SYSREG_AFSR0_EL2 = 57992 , ARM64_SYSREG_AFSR0_EL3 = 62088 , ARM64_SYSREG_AFSR1_EL1 = 49801 , ARM64_SYSREG_AFSR1_EL12 = 60041 , ARM64_SYSREG_AFSR1_EL2 = 57993 , ARM64_SYSREG_AFSR1_EL3 = 62089 , ARM64_SYSREG_AIDR_EL1 = 51207 , ARM64_SYSREG_AMAIR_EL1 = 50456 , ARM64_SYSREG_AMAIR_EL12 = 60696 , ARM64_SYSREG_AMAIR_EL2 = 58648 , ARM64_SYSREG_AMAIR_EL3 = 62744 , ARM64_SYSREG_AMCFGR_EL0 = 56977 , ARM64_SYSREG_AMCGCR_EL0 = 56978 , ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980 , ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984 , ARM64_SYSREG_AMCNTENSET0_EL0 = 56981 , ARM64_SYSREG_AMCNTENSET1_EL0 = 56985 , ARM64_SYSREG_AMCR_EL0 = 56976 , ARM64_SYSREG_AMEVCNTR00_EL0 = 56992 , ARM64_SYSREG_AMEVCNTR01_EL0 = 56993 , ARM64_SYSREG_AMEVCNTR02_EL0 = 56994 , ARM64_SYSREG_AMEVCNTR03_EL0 = 56995 , ARM64_SYSREG_AMEVCNTR10_EL0 = 57056 , ARM64_SYSREG_AMEVCNTR110_EL0 = 57066 , ARM64_SYSREG_AMEVCNTR111_EL0 = 57067 , ARM64_SYSREG_AMEVCNTR112_EL0 = 57068 , ARM64_SYSREG_AMEVCNTR113_EL0 = 57069 , ARM64_SYSREG_AMEVCNTR114_EL0 = 57070 , ARM64_SYSREG_AMEVCNTR115_EL0 = 57071 , ARM64_SYSREG_AMEVCNTR11_EL0 = 57057 , ARM64_SYSREG_AMEVCNTR12_EL0 = 57058 , ARM64_SYSREG_AMEVCNTR13_EL0 = 57059 , ARM64_SYSREG_AMEVCNTR14_EL0 = 57060 , ARM64_SYSREG_AMEVCNTR15_EL0 = 57061 , ARM64_SYSREG_AMEVCNTR16_EL0 = 57062 , ARM64_SYSREG_AMEVCNTR17_EL0 = 57063 , ARM64_SYSREG_AMEVCNTR18_EL0 = 57064 , ARM64_SYSREG_AMEVCNTR19_EL0 = 57065 , ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 59072 , ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 59082 , ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 59083 , ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 59084 , ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 59085 , ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 59086 , ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 59087 , ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 59073 , ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 59074 , ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 59075 , ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 59076 , ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 59077 , ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 59078 , ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 59079 , ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 59080 , ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 59081 , ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 59088 , ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 59098 , ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 59099 , ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 59100 , ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 59101 , ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 59102 , ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 59103 , ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 59089 , ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 59090 , ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 59091 , ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 59092 , ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 59093 , ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 59094 , ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 59095 , ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 59096 , ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 59097 , ARM64_SYSREG_AMEVTYPER00_EL0 = 57008 , ARM64_SYSREG_AMEVTYPER01_EL0 = 57009 , ARM64_SYSREG_AMEVTYPER02_EL0 = 57010 , ARM64_SYSREG_AMEVTYPER03_EL0 = 57011 , ARM64_SYSREG_AMEVTYPER10_EL0 = 57072 , ARM64_SYSREG_AMEVTYPER110_EL0 = 57082 , ARM64_SYSREG_AMEVTYPER111_EL0 = 57083 , ARM64_SYSREG_AMEVTYPER112_EL0 = 57084 , ARM64_SYSREG_AMEVTYPER113_EL0 = 57085 , ARM64_SYSREG_AMEVTYPER114_EL0 = 57086 , ARM64_SYSREG_AMEVTYPER115_EL0 = 57087 , ARM64_SYSREG_AMEVTYPER11_EL0 = 57073 , ARM64_SYSREG_AMEVTYPER12_EL0 = 57074 , ARM64_SYSREG_AMEVTYPER13_EL0 = 57075 , ARM64_SYSREG_AMEVTYPER14_EL0 = 57076 , ARM64_SYSREG_AMEVTYPER15_EL0 = 57077 , ARM64_SYSREG_AMEVTYPER16_EL0 = 57078 , ARM64_SYSREG_AMEVTYPER17_EL0 = 57079 , ARM64_SYSREG_AMEVTYPER18_EL0 = 57080 , ARM64_SYSREG_AMEVTYPER19_EL0 = 57081 , ARM64_SYSREG_AMUSERENR_EL0 = 56979 , ARM64_SYSREG_APDAKEYHI_EL1 = 49425 , ARM64_SYSREG_APDAKEYLO_EL1 = 49424 , ARM64_SYSREG_APDBKEYHI_EL1 = 49427 , ARM64_SYSREG_APDBKEYLO_EL1 = 49426 , ARM64_SYSREG_APGAKEYHI_EL1 = 49433 , ARM64_SYSREG_APGAKEYLO_EL1 = 49432 , ARM64_SYSREG_APIAKEYHI_EL1 = 49417 , ARM64_SYSREG_APIAKEYLO_EL1 = 49416 , ARM64_SYSREG_APIBKEYHI_EL1 = 49419 , ARM64_SYSREG_APIBKEYLO_EL1 = 49418 , ARM64_SYSREG_BRBCR_EL1 = 35968 , ARM64_SYSREG_BRBCR_EL12 = 44160 , ARM64_SYSREG_BRBCR_EL2 = 42112 , ARM64_SYSREG_BRBFCR_EL1 = 35969 , ARM64_SYSREG_BRBIDR0_EL1 = 35984 , ARM64_SYSREG_BRBINF0_EL1 = 35840 , ARM64_SYSREG_BRBINF10_EL1 = 35920 , ARM64_SYSREG_BRBINF11_EL1 = 35928 , ARM64_SYSREG_BRBINF12_EL1 = 35936 , ARM64_SYSREG_BRBINF13_EL1 = 35944 , ARM64_SYSREG_BRBINF14_EL1 = 35952 , ARM64_SYSREG_BRBINF15_EL1 = 35960 , ARM64_SYSREG_BRBINF16_EL1 = 35844 , ARM64_SYSREG_BRBINF17_EL1 = 35852 , ARM64_SYSREG_BRBINF18_EL1 = 35860 , ARM64_SYSREG_BRBINF19_EL1 = 35868 , ARM64_SYSREG_BRBINF1_EL1 = 35848 , ARM64_SYSREG_BRBINF20_EL1 = 35876 , ARM64_SYSREG_BRBINF21_EL1 = 35884 , ARM64_SYSREG_BRBINF22_EL1 = 35892 , ARM64_SYSREG_BRBINF23_EL1 = 35900 , ARM64_SYSREG_BRBINF24_EL1 = 35908 , ARM64_SYSREG_BRBINF25_EL1 = 35916 , ARM64_SYSREG_BRBINF26_EL1 = 35924 , ARM64_SYSREG_BRBINF27_EL1 = 35932 , ARM64_SYSREG_BRBINF28_EL1 = 35940 , ARM64_SYSREG_BRBINF29_EL1 = 35948 , ARM64_SYSREG_BRBINF2_EL1 = 35856 , ARM64_SYSREG_BRBINF30_EL1 = 35956 , ARM64_SYSREG_BRBINF31_EL1 = 35964 , ARM64_SYSREG_BRBINF3_EL1 = 35864 , ARM64_SYSREG_BRBINF4_EL1 = 35872 , ARM64_SYSREG_BRBINF5_EL1 = 35880 , ARM64_SYSREG_BRBINF6_EL1 = 35888 , ARM64_SYSREG_BRBINF7_EL1 = 35896 , ARM64_SYSREG_BRBINF8_EL1 = 35904 , ARM64_SYSREG_BRBINF9_EL1 = 35912 , ARM64_SYSREG_BRBINFINJ_EL1 = 35976 , ARM64_SYSREG_BRBSRC0_EL1 = 35841 , ARM64_SYSREG_BRBSRC10_EL1 = 35921 , ARM64_SYSREG_BRBSRC11_EL1 = 35929 , ARM64_SYSREG_BRBSRC12_EL1 = 35937 , ARM64_SYSREG_BRBSRC13_EL1 = 35945 , ARM64_SYSREG_BRBSRC14_EL1 = 35953 , ARM64_SYSREG_BRBSRC15_EL1 = 35961 , ARM64_SYSREG_BRBSRC16_EL1 = 35845 , ARM64_SYSREG_BRBSRC17_EL1 = 35853 , ARM64_SYSREG_BRBSRC18_EL1 = 35861 , ARM64_SYSREG_BRBSRC19_EL1 = 35869 , ARM64_SYSREG_BRBSRC1_EL1 = 35849 , ARM64_SYSREG_BRBSRC20_EL1 = 35877 , ARM64_SYSREG_BRBSRC21_EL1 = 35885 , ARM64_SYSREG_BRBSRC22_EL1 = 35893 , ARM64_SYSREG_BRBSRC23_EL1 = 35901 , ARM64_SYSREG_BRBSRC24_EL1 = 35909 , ARM64_SYSREG_BRBSRC25_EL1 = 35917 , ARM64_SYSREG_BRBSRC26_EL1 = 35925 , ARM64_SYSREG_BRBSRC27_EL1 = 35933 , ARM64_SYSREG_BRBSRC28_EL1 = 35941 , ARM64_SYSREG_BRBSRC29_EL1 = 35949 , ARM64_SYSREG_BRBSRC2_EL1 = 35857 , ARM64_SYSREG_BRBSRC30_EL1 = 35957 , ARM64_SYSREG_BRBSRC31_EL1 = 35965 , ARM64_SYSREG_BRBSRC3_EL1 = 35865 , ARM64_SYSREG_BRBSRC4_EL1 = 35873 , ARM64_SYSREG_BRBSRC5_EL1 = 35881 , ARM64_SYSREG_BRBSRC6_EL1 = 35889 , ARM64_SYSREG_BRBSRC7_EL1 = 35897 , ARM64_SYSREG_BRBSRC8_EL1 = 35905 , ARM64_SYSREG_BRBSRC9_EL1 = 35913 , ARM64_SYSREG_BRBSRCINJ_EL1 = 35977 , ARM64_SYSREG_BRBTGT0_EL1 = 35842 , ARM64_SYSREG_BRBTGT10_EL1 = 35922 , ARM64_SYSREG_BRBTGT11_EL1 = 35930 , ARM64_SYSREG_BRBTGT12_EL1 = 35938 , ARM64_SYSREG_BRBTGT13_EL1 = 35946 , ARM64_SYSREG_BRBTGT14_EL1 = 35954 , ARM64_SYSREG_BRBTGT15_EL1 = 35962 , ARM64_SYSREG_BRBTGT16_EL1 = 35846 , ARM64_SYSREG_BRBTGT17_EL1 = 35854 , ARM64_SYSREG_BRBTGT18_EL1 = 35862 , ARM64_SYSREG_BRBTGT19_EL1 = 35870 , ARM64_SYSREG_BRBTGT1_EL1 = 35850 , ARM64_SYSREG_BRBTGT20_EL1 = 35878 , ARM64_SYSREG_BRBTGT21_EL1 = 35886 , ARM64_SYSREG_BRBTGT22_EL1 = 35894 , ARM64_SYSREG_BRBTGT23_EL1 = 35902 , ARM64_SYSREG_BRBTGT24_EL1 = 35910 , ARM64_SYSREG_BRBTGT25_EL1 = 35918 , ARM64_SYSREG_BRBTGT26_EL1 = 35926 , ARM64_SYSREG_BRBTGT27_EL1 = 35934 , ARM64_SYSREG_BRBTGT28_EL1 = 35942 , ARM64_SYSREG_BRBTGT29_EL1 = 35950 , ARM64_SYSREG_BRBTGT2_EL1 = 35858 , ARM64_SYSREG_BRBTGT30_EL1 = 35958 , ARM64_SYSREG_BRBTGT31_EL1 = 35966 , ARM64_SYSREG_BRBTGT3_EL1 = 35866 , ARM64_SYSREG_BRBTGT4_EL1 = 35874 , ARM64_SYSREG_BRBTGT5_EL1 = 35882 , ARM64_SYSREG_BRBTGT6_EL1 = 35890 , ARM64_SYSREG_BRBTGT7_EL1 = 35898 , ARM64_SYSREG_BRBTGT8_EL1 = 35906 , ARM64_SYSREG_BRBTGT9_EL1 = 35914 , ARM64_SYSREG_BRBTGTINJ_EL1 = 35978 , ARM64_SYSREG_BRBTS_EL1 = 35970 , ARM64_SYSREG_CCSIDR2_EL1 = 51202 , ARM64_SYSREG_CCSIDR_EL1 = 51200 , ARM64_SYSREG_CLIDR_EL1 = 51201 , ARM64_SYSREG_CNTFRQ_EL0 = 57088 , ARM64_SYSREG_CNTHCTL_EL2 = 59144 , ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177 , ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178 , ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176 , ARM64_SYSREG_CNTHP_CTL_EL2 = 59153 , ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154 , ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152 , ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169 , ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170 , ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168 , ARM64_SYSREG_CNTHV_CTL_EL2 = 59161 , ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162 , ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160 , ARM64_SYSREG_CNTISCALE_EL2 = 59141 , ARM64_SYSREG_CNTKCTL_EL1 = 50952 , ARM64_SYSREG_CNTKCTL_EL12 = 61192 , ARM64_SYSREG_CNTPCTSS_EL0 = 57093 , ARM64_SYSREG_CNTPCT_EL0 = 57089 , ARM64_SYSREG_CNTPOFF_EL2 = 59142 , ARM64_SYSREG_CNTPS_CTL_EL1 = 65297 , ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298 , ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296 , ARM64_SYSREG_CNTP_CTL_EL0 = 57105 , ARM64_SYSREG_CNTP_CTL_EL02 = 61201 , ARM64_SYSREG_CNTP_CVAL_EL0 = 57106 , ARM64_SYSREG_CNTP_CVAL_EL02 = 61202 , ARM64_SYSREG_CNTP_TVAL_EL0 = 57104 , ARM64_SYSREG_CNTP_TVAL_EL02 = 61200 , ARM64_SYSREG_CNTSCALE_EL2 = 59140 , ARM64_SYSREG_CNTVCTSS_EL0 = 57094 , ARM64_SYSREG_CNTVCT_EL0 = 57090 , ARM64_SYSREG_CNTVFRQ_EL2 = 59143 , ARM64_SYSREG_CNTVOFF_EL2 = 59139 , ARM64_SYSREG_CNTV_CTL_EL0 = 57113 , ARM64_SYSREG_CNTV_CTL_EL02 = 61209 , ARM64_SYSREG_CNTV_CVAL_EL0 = 57114 , ARM64_SYSREG_CNTV_CVAL_EL02 = 61210 , ARM64_SYSREG_CNTV_TVAL_EL0 = 57112 , ARM64_SYSREG_CNTV_TVAL_EL02 = 61208 , ARM64_SYSREG_CONTEXTIDR_EL1 = 50817 , ARM64_SYSREG_CONTEXTIDR_EL12 = 61057 , ARM64_SYSREG_CONTEXTIDR_EL2 = 59009 , ARM64_SYSREG_CPACR_EL1 = 49282 , ARM64_SYSREG_CPACR_EL12 = 59522 , ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424 , ARM64_SYSREG_CPTR_EL2 = 57482 , ARM64_SYSREG_CPTR_EL3 = 61578 , ARM64_SYSREG_CSSELR_EL1 = 53248 , ARM64_SYSREG_CTR_EL0 = 55297 , ARM64_SYSREG_CURRENTEL = 49682 , ARM64_SYSREG_DACR32_EL2 = 57728 , ARM64_SYSREG_DAIF = 55825 , ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782 , ARM64_SYSREG_DBGBCR0_EL1 = 32773 , ARM64_SYSREG_DBGBCR10_EL1 = 32853 , ARM64_SYSREG_DBGBCR11_EL1 = 32861 , ARM64_SYSREG_DBGBCR12_EL1 = 32869 , ARM64_SYSREG_DBGBCR13_EL1 = 32877 , ARM64_SYSREG_DBGBCR14_EL1 = 32885 , ARM64_SYSREG_DBGBCR15_EL1 = 32893 , ARM64_SYSREG_DBGBCR1_EL1 = 32781 , ARM64_SYSREG_DBGBCR2_EL1 = 32789 , ARM64_SYSREG_DBGBCR3_EL1 = 32797 , ARM64_SYSREG_DBGBCR4_EL1 = 32805 , ARM64_SYSREG_DBGBCR5_EL1 = 32813 , ARM64_SYSREG_DBGBCR6_EL1 = 32821 , ARM64_SYSREG_DBGBCR7_EL1 = 32829 , ARM64_SYSREG_DBGBCR8_EL1 = 32837 , ARM64_SYSREG_DBGBCR9_EL1 = 32845 , ARM64_SYSREG_DBGBVR0_EL1 = 32772 , ARM64_SYSREG_DBGBVR10_EL1 = 32852 , ARM64_SYSREG_DBGBVR11_EL1 = 32860 , ARM64_SYSREG_DBGBVR12_EL1 = 32868 , ARM64_SYSREG_DBGBVR13_EL1 = 32876 , ARM64_SYSREG_DBGBVR14_EL1 = 32884 , ARM64_SYSREG_DBGBVR15_EL1 = 32892 , ARM64_SYSREG_DBGBVR1_EL1 = 32780 , ARM64_SYSREG_DBGBVR2_EL1 = 32788 , ARM64_SYSREG_DBGBVR3_EL1 = 32796 , ARM64_SYSREG_DBGBVR4_EL1 = 32804 , ARM64_SYSREG_DBGBVR5_EL1 = 32812 , ARM64_SYSREG_DBGBVR6_EL1 = 32820 , ARM64_SYSREG_DBGBVR7_EL1 = 32828 , ARM64_SYSREG_DBGBVR8_EL1 = 32836 , ARM64_SYSREG_DBGBVR9_EL1 = 32844 , ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742 , ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734 , ARM64_SYSREG_DBGDTRRX_EL0 = 38952 , ARM64_SYSREG_DBGDTR_EL0 = 38944 , ARM64_SYSREG_DBGPRCR_EL1 = 32932 , ARM64_SYSREG_DBGVCR32_EL2 = 41016 , ARM64_SYSREG_DBGWCR0_EL1 = 32775 , ARM64_SYSREG_DBGWCR10_EL1 = 32855 , ARM64_SYSREG_DBGWCR11_EL1 = 32863 , ARM64_SYSREG_DBGWCR12_EL1 = 32871 , ARM64_SYSREG_DBGWCR13_EL1 = 32879 , ARM64_SYSREG_DBGWCR14_EL1 = 32887 , ARM64_SYSREG_DBGWCR15_EL1 = 32895 , ARM64_SYSREG_DBGWCR1_EL1 = 32783 , ARM64_SYSREG_DBGWCR2_EL1 = 32791 , ARM64_SYSREG_DBGWCR3_EL1 = 32799 , ARM64_SYSREG_DBGWCR4_EL1 = 32807 , ARM64_SYSREG_DBGWCR5_EL1 = 32815 , ARM64_SYSREG_DBGWCR6_EL1 = 32823 , ARM64_SYSREG_DBGWCR7_EL1 = 32831 , ARM64_SYSREG_DBGWCR8_EL1 = 32839 , ARM64_SYSREG_DBGWCR9_EL1 = 32847 , ARM64_SYSREG_DBGWVR0_EL1 = 32774 , ARM64_SYSREG_DBGWVR10_EL1 = 32854 , ARM64_SYSREG_DBGWVR11_EL1 = 32862 , ARM64_SYSREG_DBGWVR12_EL1 = 32870 , ARM64_SYSREG_DBGWVR13_EL1 = 32878 , ARM64_SYSREG_DBGWVR14_EL1 = 32886 , ARM64_SYSREG_DBGWVR15_EL1 = 32894 , ARM64_SYSREG_DBGWVR1_EL1 = 32782 , ARM64_SYSREG_DBGWVR2_EL1 = 32790 , ARM64_SYSREG_DBGWVR3_EL1 = 32798 , ARM64_SYSREG_DBGWVR4_EL1 = 32806 , ARM64_SYSREG_DBGWVR5_EL1 = 32814 , ARM64_SYSREG_DBGWVR6_EL1 = 32822 , ARM64_SYSREG_DBGWVR7_EL1 = 32830 , ARM64_SYSREG_DBGWVR8_EL1 = 32838 , ARM64_SYSREG_DBGWVR9_EL1 = 32846 , ARM64_SYSREG_DCZID_EL0 = 55303 , ARM64_SYSREG_DISR_EL1 = 50697 , ARM64_SYSREG_DIT = 55829 , ARM64_SYSREG_DLR_EL0 = 55849 , ARM64_SYSREG_DSPSR_EL0 = 55848 , ARM64_SYSREG_ELR_EL1 = 49665 , ARM64_SYSREG_ELR_EL12 = 59905 , ARM64_SYSREG_ELR_EL2 = 57857 , ARM64_SYSREG_ELR_EL3 = 61953 , ARM64_SYSREG_ERRIDR_EL1 = 49816 , ARM64_SYSREG_ERRSELR_EL1 = 49817 , ARM64_SYSREG_ERXADDR_EL1 = 49827 , ARM64_SYSREG_ERXCTLR_EL1 = 49825 , ARM64_SYSREG_ERXFR_EL1 = 49824 , ARM64_SYSREG_ERXMISC0_EL1 = 49832 , ARM64_SYSREG_ERXMISC1_EL1 = 49833 , ARM64_SYSREG_ERXMISC2_EL1 = 49834 , ARM64_SYSREG_ERXMISC3_EL1 = 49835 , ARM64_SYSREG_ERXPFGCDN_EL1 = 49830 , ARM64_SYSREG_ERXPFGCTL_EL1 = 49829 , ARM64_SYSREG_ERXPFGF_EL1 = 49828 , ARM64_SYSREG_ERXSTATUS_EL1 = 49826 , ARM64_SYSREG_ESR_EL1 = 49808 , ARM64_SYSREG_ESR_EL12 = 60048 , ARM64_SYSREG_ESR_EL2 = 58000 , ARM64_SYSREG_ESR_EL3 = 62096 , ARM64_SYSREG_FAR_EL1 = 49920 , ARM64_SYSREG_FAR_EL12 = 60160 , ARM64_SYSREG_FAR_EL2 = 58112 , ARM64_SYSREG_FAR_EL3 = 62208 , ARM64_SYSREG_FPCR = 55840 , ARM64_SYSREG_FPEXC32_EL2 = 58008 , ARM64_SYSREG_FPSR = 55841 , ARM64_SYSREG_GCR_EL1 = 49286 , ARM64_SYSREG_GMID_EL1 = 51204 , ARM64_SYSREG_GPCCR_EL3 = 61710 , ARM64_SYSREG_GPTBR_EL3 = 61708 , ARM64_SYSREG_HACR_EL2 = 57487 , ARM64_SYSREG_HCRX_EL2 = 57490 , ARM64_SYSREG_HCR_EL2 = 57480 , ARM64_SYSREG_HDFGRTR_EL2 = 57740 , ARM64_SYSREG_HDFGWTR_EL2 = 57741 , ARM64_SYSREG_HFGITR_EL2 = 57486 , ARM64_SYSREG_HFGRTR_EL2 = 57484 , ARM64_SYSREG_HFGWTR_EL2 = 57485 , ARM64_SYSREG_HPFAR_EL2 = 58116 , ARM64_SYSREG_HSTR_EL2 = 57483 , ARM64_SYSREG_ICC_AP0R0_EL1 = 50756 , ARM64_SYSREG_ICC_AP0R1_EL1 = 50757 , ARM64_SYSREG_ICC_AP0R2_EL1 = 50758 , ARM64_SYSREG_ICC_AP0R3_EL1 = 50759 , ARM64_SYSREG_ICC_AP1R0_EL1 = 50760 , ARM64_SYSREG_ICC_AP1R1_EL1 = 50761 , ARM64_SYSREG_ICC_AP1R2_EL1 = 50762 , ARM64_SYSREG_ICC_AP1R3_EL1 = 50763 , ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782 , ARM64_SYSREG_ICC_BPR0_EL1 = 50755 , ARM64_SYSREG_ICC_BPR1_EL1 = 50787 , ARM64_SYSREG_ICC_CTLR_EL1 = 50788 , ARM64_SYSREG_ICC_CTLR_EL3 = 63076 , ARM64_SYSREG_ICC_DIR_EL1 = 50777 , ARM64_SYSREG_ICC_EOIR0_EL1 = 50753 , ARM64_SYSREG_ICC_EOIR1_EL1 = 50785 , ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754 , ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786 , ARM64_SYSREG_ICC_IAR0_EL1 = 50752 , ARM64_SYSREG_ICC_IAR1_EL1 = 50784 , ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790 , ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791 , ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079 , ARM64_SYSREG_ICC_PMR_EL1 = 49712 , ARM64_SYSREG_ICC_RPR_EL1 = 50779 , ARM64_SYSREG_ICC_SGI0R_EL1 = 50783 , ARM64_SYSREG_ICC_SGI1R_EL1 = 50781 , ARM64_SYSREG_ICC_SRE_EL1 = 50789 , ARM64_SYSREG_ICC_SRE_EL2 = 58957 , ARM64_SYSREG_ICC_SRE_EL3 = 63077 , ARM64_SYSREG_ICH_AP0R0_EL2 = 58944 , ARM64_SYSREG_ICH_AP0R1_EL2 = 58945 , ARM64_SYSREG_ICH_AP0R2_EL2 = 58946 , ARM64_SYSREG_ICH_AP0R3_EL2 = 58947 , ARM64_SYSREG_ICH_AP1R0_EL2 = 58952 , ARM64_SYSREG_ICH_AP1R1_EL2 = 58953 , ARM64_SYSREG_ICH_AP1R2_EL2 = 58954 , ARM64_SYSREG_ICH_AP1R3_EL2 = 58955 , ARM64_SYSREG_ICH_EISR_EL2 = 58971 , ARM64_SYSREG_ICH_ELRSR_EL2 = 58973 , ARM64_SYSREG_ICH_HCR_EL2 = 58968 , ARM64_SYSREG_ICH_LR0_EL2 = 58976 , ARM64_SYSREG_ICH_LR10_EL2 = 58986 , ARM64_SYSREG_ICH_LR11_EL2 = 58987 , ARM64_SYSREG_ICH_LR12_EL2 = 58988 , ARM64_SYSREG_ICH_LR13_EL2 = 58989 , ARM64_SYSREG_ICH_LR14_EL2 = 58990 , ARM64_SYSREG_ICH_LR15_EL2 = 58991 , ARM64_SYSREG_ICH_LR1_EL2 = 58977 , ARM64_SYSREG_ICH_LR2_EL2 = 58978 , ARM64_SYSREG_ICH_LR3_EL2 = 58979 , ARM64_SYSREG_ICH_LR4_EL2 = 58980 , ARM64_SYSREG_ICH_LR5_EL2 = 58981 , ARM64_SYSREG_ICH_LR6_EL2 = 58982 , ARM64_SYSREG_ICH_LR7_EL2 = 58983 , ARM64_SYSREG_ICH_LR8_EL2 = 58984 , ARM64_SYSREG_ICH_LR9_EL2 = 58985 , ARM64_SYSREG_ICH_MISR_EL2 = 58970 , ARM64_SYSREG_ICH_VMCR_EL2 = 58975 , ARM64_SYSREG_ICH_VTR_EL2 = 58969 , ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196 , ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197 , ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192 , ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193 , ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200 , ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201 , ARM64_SYSREG_ID_AA64ISAR2_EL1 = 49202 , ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208 , ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209 , ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210 , ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184 , ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185 , ARM64_SYSREG_ID_AA64SMFR0_EL1 = 49189 , ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188 , ARM64_SYSREG_ID_AFR0_EL1 = 49163 , ARM64_SYSREG_ID_DFR0_EL1 = 49162 , ARM64_SYSREG_ID_ISAR0_EL1 = 49168 , ARM64_SYSREG_ID_ISAR1_EL1 = 49169 , ARM64_SYSREG_ID_ISAR2_EL1 = 49170 , ARM64_SYSREG_ID_ISAR3_EL1 = 49171 , ARM64_SYSREG_ID_ISAR4_EL1 = 49172 , ARM64_SYSREG_ID_ISAR5_EL1 = 49173 , ARM64_SYSREG_ID_ISAR6_EL1 = 49175 , ARM64_SYSREG_ID_MMFR0_EL1 = 49164 , ARM64_SYSREG_ID_MMFR1_EL1 = 49165 , ARM64_SYSREG_ID_MMFR2_EL1 = 49166 , ARM64_SYSREG_ID_MMFR3_EL1 = 49167 , ARM64_SYSREG_ID_MMFR4_EL1 = 49174 , ARM64_SYSREG_ID_MMFR5_EL1 = 49182 , ARM64_SYSREG_ID_PFR0_EL1 = 49160 , ARM64_SYSREG_ID_PFR1_EL1 = 49161 , ARM64_SYSREG_ID_PFR2_EL1 = 49180 , ARM64_SYSREG_IFSR32_EL2 = 57985 , ARM64_SYSREG_ISR_EL1 = 50696 , ARM64_SYSREG_LORC_EL1 = 50467 , ARM64_SYSREG_LOREA_EL1 = 50465 , ARM64_SYSREG_LORID_EL1 = 50471 , ARM64_SYSREG_LORN_EL1 = 50466 , ARM64_SYSREG_LORSA_EL1 = 50464 , ARM64_SYSREG_MAIR_EL1 = 50448 , ARM64_SYSREG_MAIR_EL12 = 60688 , ARM64_SYSREG_MAIR_EL2 = 58640 , ARM64_SYSREG_MAIR_EL3 = 62736 , ARM64_SYSREG_MDCCINT_EL1 = 32784 , ARM64_SYSREG_MDCCSR_EL0 = 38920 , ARM64_SYSREG_MDCR_EL2 = 57481 , ARM64_SYSREG_MDCR_EL3 = 61593 , ARM64_SYSREG_MDRAR_EL1 = 32896 , ARM64_SYSREG_MDSCR_EL1 = 32786 , ARM64_SYSREG_MFAR_EL3 = 62213 , ARM64_SYSREG_MIDR_EL1 = 49152 , ARM64_SYSREG_MPAM0_EL1 = 50473 , ARM64_SYSREG_MPAM1_EL1 = 50472 , ARM64_SYSREG_MPAM1_EL12 = 60712 , ARM64_SYSREG_MPAM2_EL2 = 58664 , ARM64_SYSREG_MPAM3_EL3 = 62760 , ARM64_SYSREG_MPAMHCR_EL2 = 58656 , ARM64_SYSREG_MPAMIDR_EL1 = 50468 , ARM64_SYSREG_MPAMSM_EL1 = 50475 , ARM64_SYSREG_MPAMVPM0_EL2 = 58672 , ARM64_SYSREG_MPAMVPM1_EL2 = 58673 , ARM64_SYSREG_MPAMVPM2_EL2 = 58674 , ARM64_SYSREG_MPAMVPM3_EL2 = 58675 , ARM64_SYSREG_MPAMVPM4_EL2 = 58676 , ARM64_SYSREG_MPAMVPM5_EL2 = 58677 , ARM64_SYSREG_MPAMVPM6_EL2 = 58678 , ARM64_SYSREG_MPAMVPM7_EL2 = 58679 , ARM64_SYSREG_MPAMVPMV_EL2 = 58657 , ARM64_SYSREG_MPIDR_EL1 = 49157 , ARM64_SYSREG_MPUIR_EL1 = 49156 , ARM64_SYSREG_MPUIR_EL2 = 57348 , ARM64_SYSREG_MVFR0_EL1 = 49176 , ARM64_SYSREG_MVFR1_EL1 = 49177 , ARM64_SYSREG_MVFR2_EL1 = 49178 , ARM64_SYSREG_NZCV = 55824 , ARM64_SYSREG_OSDLR_EL1 = 32924 , ARM64_SYSREG_OSDTRRX_EL1 = 32770 , ARM64_SYSREG_OSDTRTX_EL1 = 32794 , ARM64_SYSREG_OSECCR_EL1 = 32818 , ARM64_SYSREG_OSLAR_EL1 = 32900 , ARM64_SYSREG_OSLSR_EL1 = 32908 , ARM64_SYSREG_PAN = 49683 , ARM64_SYSREG_PAR_EL1 = 50080 , ARM64_SYSREG_PMBIDR_EL1 = 50391 , ARM64_SYSREG_PMBLIMITR_EL1 = 50384 , ARM64_SYSREG_PMBPTR_EL1 = 50385 , ARM64_SYSREG_PMBSR_EL1 = 50387 , ARM64_SYSREG_PMCCFILTR_EL0 = 57215 , ARM64_SYSREG_PMCCNTR_EL0 = 56552 , ARM64_SYSREG_PMCEID0_EL0 = 56550 , ARM64_SYSREG_PMCEID1_EL0 = 56551 , ARM64_SYSREG_PMCNTENCLR_EL0 = 56546 , ARM64_SYSREG_PMCNTENSET_EL0 = 56545 , ARM64_SYSREG_PMCR_EL0 = 56544 , ARM64_SYSREG_PMEVCNTR0_EL0 = 57152 , ARM64_SYSREG_PMEVCNTR10_EL0 = 57162 , ARM64_SYSREG_PMEVCNTR11_EL0 = 57163 , ARM64_SYSREG_PMEVCNTR12_EL0 = 57164 , ARM64_SYSREG_PMEVCNTR13_EL0 = 57165 , ARM64_SYSREG_PMEVCNTR14_EL0 = 57166 , ARM64_SYSREG_PMEVCNTR15_EL0 = 57167 , ARM64_SYSREG_PMEVCNTR16_EL0 = 57168 , ARM64_SYSREG_PMEVCNTR17_EL0 = 57169 , ARM64_SYSREG_PMEVCNTR18_EL0 = 57170 , ARM64_SYSREG_PMEVCNTR19_EL0 = 57171 , ARM64_SYSREG_PMEVCNTR1_EL0 = 57153 , ARM64_SYSREG_PMEVCNTR20_EL0 = 57172 , ARM64_SYSREG_PMEVCNTR21_EL0 = 57173 , ARM64_SYSREG_PMEVCNTR22_EL0 = 57174 , ARM64_SYSREG_PMEVCNTR23_EL0 = 57175 , ARM64_SYSREG_PMEVCNTR24_EL0 = 57176 , ARM64_SYSREG_PMEVCNTR25_EL0 = 57177 , ARM64_SYSREG_PMEVCNTR26_EL0 = 57178 , ARM64_SYSREG_PMEVCNTR27_EL0 = 57179 , ARM64_SYSREG_PMEVCNTR28_EL0 = 57180 , ARM64_SYSREG_PMEVCNTR29_EL0 = 57181 , ARM64_SYSREG_PMEVCNTR2_EL0 = 57154 , ARM64_SYSREG_PMEVCNTR30_EL0 = 57182 , ARM64_SYSREG_PMEVCNTR3_EL0 = 57155 , ARM64_SYSREG_PMEVCNTR4_EL0 = 57156 , ARM64_SYSREG_PMEVCNTR5_EL0 = 57157 , ARM64_SYSREG_PMEVCNTR6_EL0 = 57158 , ARM64_SYSREG_PMEVCNTR7_EL0 = 57159 , ARM64_SYSREG_PMEVCNTR8_EL0 = 57160 , ARM64_SYSREG_PMEVCNTR9_EL0 = 57161 , ARM64_SYSREG_PMEVTYPER0_EL0 = 57184 , ARM64_SYSREG_PMEVTYPER10_EL0 = 57194 , ARM64_SYSREG_PMEVTYPER11_EL0 = 57195 , ARM64_SYSREG_PMEVTYPER12_EL0 = 57196 , ARM64_SYSREG_PMEVTYPER13_EL0 = 57197 , ARM64_SYSREG_PMEVTYPER14_EL0 = 57198 , ARM64_SYSREG_PMEVTYPER15_EL0 = 57199 , ARM64_SYSREG_PMEVTYPER16_EL0 = 57200 , ARM64_SYSREG_PMEVTYPER17_EL0 = 57201 , ARM64_SYSREG_PMEVTYPER18_EL0 = 57202 , ARM64_SYSREG_PMEVTYPER19_EL0 = 57203 , ARM64_SYSREG_PMEVTYPER1_EL0 = 57185 , ARM64_SYSREG_PMEVTYPER20_EL0 = 57204 , ARM64_SYSREG_PMEVTYPER21_EL0 = 57205 , ARM64_SYSREG_PMEVTYPER22_EL0 = 57206 , ARM64_SYSREG_PMEVTYPER23_EL0 = 57207 , ARM64_SYSREG_PMEVTYPER24_EL0 = 57208 , ARM64_SYSREG_PMEVTYPER25_EL0 = 57209 , ARM64_SYSREG_PMEVTYPER26_EL0 = 57210 , ARM64_SYSREG_PMEVTYPER27_EL0 = 57211 , ARM64_SYSREG_PMEVTYPER28_EL0 = 57212 , ARM64_SYSREG_PMEVTYPER29_EL0 = 57213 , ARM64_SYSREG_PMEVTYPER2_EL0 = 57186 , ARM64_SYSREG_PMEVTYPER30_EL0 = 57214 , ARM64_SYSREG_PMEVTYPER3_EL0 = 57187 , ARM64_SYSREG_PMEVTYPER4_EL0 = 57188 , ARM64_SYSREG_PMEVTYPER5_EL0 = 57189 , ARM64_SYSREG_PMEVTYPER6_EL0 = 57190 , ARM64_SYSREG_PMEVTYPER7_EL0 = 57191 , ARM64_SYSREG_PMEVTYPER8_EL0 = 57192 , ARM64_SYSREG_PMEVTYPER9_EL0 = 57193 , ARM64_SYSREG_PMINTENCLR_EL1 = 50418 , ARM64_SYSREG_PMINTENSET_EL1 = 50417 , ARM64_SYSREG_PMMIR_EL1 = 50422 , ARM64_SYSREG_PMOVSCLR_EL0 = 56547 , ARM64_SYSREG_PMOVSSET_EL0 = 56563 , ARM64_SYSREG_PMSCR_EL1 = 50376 , ARM64_SYSREG_PMSCR_EL12 = 60616 , ARM64_SYSREG_PMSCR_EL2 = 58568 , ARM64_SYSREG_PMSELR_EL0 = 56549 , ARM64_SYSREG_PMSEVFR_EL1 = 50381 , ARM64_SYSREG_PMSFCR_EL1 = 50380 , ARM64_SYSREG_PMSICR_EL1 = 50378 , ARM64_SYSREG_PMSIDR_EL1 = 50383 , ARM64_SYSREG_PMSIRR_EL1 = 50379 , ARM64_SYSREG_PMSLATFR_EL1 = 50382 , ARM64_SYSREG_PMSNEVFR_EL1 = 50377 , ARM64_SYSREG_PMSWINC_EL0 = 56548 , ARM64_SYSREG_PMUSERENR_EL0 = 56560 , ARM64_SYSREG_PMXEVCNTR_EL0 = 56554 , ARM64_SYSREG_PMXEVTYPER_EL0 = 56553 , ARM64_SYSREG_PRBAR10_EL1 = 50024 , ARM64_SYSREG_PRBAR10_EL2 = 58216 , ARM64_SYSREG_PRBAR11_EL1 = 50028 , ARM64_SYSREG_PRBAR11_EL2 = 58220 , ARM64_SYSREG_PRBAR12_EL1 = 50032 , ARM64_SYSREG_PRBAR12_EL2 = 58224 , ARM64_SYSREG_PRBAR13_EL1 = 50036 , ARM64_SYSREG_PRBAR13_EL2 = 58228 , ARM64_SYSREG_PRBAR14_EL1 = 50040 , ARM64_SYSREG_PRBAR14_EL2 = 58232 , ARM64_SYSREG_PRBAR15_EL1 = 50044 , ARM64_SYSREG_PRBAR15_EL2 = 58236 , ARM64_SYSREG_PRBAR1_EL1 = 49988 , ARM64_SYSREG_PRBAR1_EL2 = 58180 , ARM64_SYSREG_PRBAR2_EL1 = 49992 , ARM64_SYSREG_PRBAR2_EL2 = 58184 , ARM64_SYSREG_PRBAR3_EL1 = 49996 , ARM64_SYSREG_PRBAR3_EL2 = 58188 , ARM64_SYSREG_PRBAR4_EL1 = 50000 , ARM64_SYSREG_PRBAR4_EL2 = 58192 , ARM64_SYSREG_PRBAR5_EL1 = 50004 , ARM64_SYSREG_PRBAR5_EL2 = 58196 , ARM64_SYSREG_PRBAR6_EL1 = 50008 , ARM64_SYSREG_PRBAR6_EL2 = 58200 , ARM64_SYSREG_PRBAR7_EL1 = 50012 , ARM64_SYSREG_PRBAR7_EL2 = 58204 , ARM64_SYSREG_PRBAR8_EL1 = 50016 , ARM64_SYSREG_PRBAR8_EL2 = 58208 , ARM64_SYSREG_PRBAR9_EL1 = 50020 , ARM64_SYSREG_PRBAR9_EL2 = 58212 , ARM64_SYSREG_PRBAR_EL1 = 49984 , ARM64_SYSREG_PRBAR_EL2 = 58176 , ARM64_SYSREG_PRENR_EL1 = 49929 , ARM64_SYSREG_PRENR_EL2 = 58121 , ARM64_SYSREG_PRLAR10_EL1 = 50025 , ARM64_SYSREG_PRLAR10_EL2 = 58217 , ARM64_SYSREG_PRLAR11_EL1 = 50029 , ARM64_SYSREG_PRLAR11_EL2 = 58221 , ARM64_SYSREG_PRLAR12_EL1 = 50033 , ARM64_SYSREG_PRLAR12_EL2 = 58225 , ARM64_SYSREG_PRLAR13_EL1 = 50037 , ARM64_SYSREG_PRLAR13_EL2 = 58229 , ARM64_SYSREG_PRLAR14_EL1 = 50041 , ARM64_SYSREG_PRLAR14_EL2 = 58233 , ARM64_SYSREG_PRLAR15_EL1 = 50045 , ARM64_SYSREG_PRLAR15_EL2 = 58237 , ARM64_SYSREG_PRLAR1_EL1 = 49989 , ARM64_SYSREG_PRLAR1_EL2 = 58181 , ARM64_SYSREG_PRLAR2_EL1 = 49993 , ARM64_SYSREG_PRLAR2_EL2 = 58185 , ARM64_SYSREG_PRLAR3_EL1 = 49997 , ARM64_SYSREG_PRLAR3_EL2 = 58189 , ARM64_SYSREG_PRLAR4_EL1 = 50001 , ARM64_SYSREG_PRLAR4_EL2 = 58193 , ARM64_SYSREG_PRLAR5_EL1 = 50005 , ARM64_SYSREG_PRLAR5_EL2 = 58197 , ARM64_SYSREG_PRLAR6_EL1 = 50009 , ARM64_SYSREG_PRLAR6_EL2 = 58201 , ARM64_SYSREG_PRLAR7_EL1 = 50013 , ARM64_SYSREG_PRLAR7_EL2 = 58205 , ARM64_SYSREG_PRLAR8_EL1 = 50017 , ARM64_SYSREG_PRLAR8_EL2 = 58209 , ARM64_SYSREG_PRLAR9_EL1 = 50021 , ARM64_SYSREG_PRLAR9_EL2 = 58213 , ARM64_SYSREG_PRLAR_EL1 = 49985 , ARM64_SYSREG_PRLAR_EL2 = 58177 , ARM64_SYSREG_PRSELR_EL1 = 49937 , ARM64_SYSREG_PRSELR_EL2 = 58129 , ARM64_SYSREG_REVIDR_EL1 = 49158 , ARM64_SYSREG_RGSR_EL1 = 49285 , ARM64_SYSREG_RMR_EL1 = 50690 , ARM64_SYSREG_RMR_EL2 = 58882 , ARM64_SYSREG_RMR_EL3 = 62978 , ARM64_SYSREG_RNDR = 55584 , ARM64_SYSREG_RNDRRS = 55585 , ARM64_SYSREG_RVBAR_EL1 = 50689 , ARM64_SYSREG_RVBAR_EL2 = 58881 , ARM64_SYSREG_RVBAR_EL3 = 62977 , ARM64_SYSREG_SCR_EL3 = 61576 , ARM64_SYSREG_SCTLR_EL1 = 49280 , ARM64_SYSREG_SCTLR_EL12 = 59520 , ARM64_SYSREG_SCTLR_EL2 = 57472 , ARM64_SYSREG_SCTLR_EL3 = 61568 , ARM64_SYSREG_SCXTNUM_EL0 = 56967 , ARM64_SYSREG_SCXTNUM_EL1 = 50823 , ARM64_SYSREG_SCXTNUM_EL12 = 61063 , ARM64_SYSREG_SCXTNUM_EL2 = 59015 , ARM64_SYSREG_SCXTNUM_EL3 = 63111 , ARM64_SYSREG_SDER32_EL2 = 57497 , ARM64_SYSREG_SDER32_EL3 = 61577 , ARM64_SYSREG_SMCR_EL1 = 49302 , ARM64_SYSREG_SMCR_EL12 = 59542 , ARM64_SYSREG_SMCR_EL2 = 57494 , ARM64_SYSREG_SMCR_EL3 = 61590 , ARM64_SYSREG_SMIDR_EL1 = 51206 , ARM64_SYSREG_SMPRIMAP_EL2 = 57493 , ARM64_SYSREG_SMPRI_EL1 = 49300 , ARM64_SYSREG_SPSEL = 49680 , ARM64_SYSREG_SPSR_ABT = 57881 , ARM64_SYSREG_SPSR_EL1 = 49664 , ARM64_SYSREG_SPSR_EL12 = 59904 , ARM64_SYSREG_SPSR_EL2 = 57856 , ARM64_SYSREG_SPSR_EL3 = 61952 , ARM64_SYSREG_SPSR_FIQ = 57883 , ARM64_SYSREG_SPSR_IRQ = 57880 , ARM64_SYSREG_SPSR_UND = 57882 , ARM64_SYSREG_SP_EL0 = 49672 , ARM64_SYSREG_SP_EL1 = 57864 , ARM64_SYSREG_SP_EL2 = 61960 , ARM64_SYSREG_SSBS = 55830 , ARM64_SYSREG_SVCR = 55826 , ARM64_SYSREG_TCO = 55831 , ARM64_SYSREG_TCR_EL1 = 49410 , ARM64_SYSREG_TCR_EL12 = 59650 , ARM64_SYSREG_TCR_EL2 = 57602 , ARM64_SYSREG_TCR_EL3 = 61698 , ARM64_SYSREG_TEECR32_EL1 = 36864 , ARM64_SYSREG_TEEHBR32_EL1 = 36992 , ARM64_SYSREG_TFSRE0_EL1 = 49841 , ARM64_SYSREG_TFSR_EL1 = 49840 , ARM64_SYSREG_TFSR_EL12 = 60080 , ARM64_SYSREG_TFSR_EL2 = 58032 , ARM64_SYSREG_TFSR_EL3 = 62128 , ARM64_SYSREG_TPIDR2_EL0 = 56965 , ARM64_SYSREG_TPIDRRO_EL0 = 56963 , ARM64_SYSREG_TPIDR_EL0 = 56962 , ARM64_SYSREG_TPIDR_EL1 = 50820 , ARM64_SYSREG_TPIDR_EL2 = 59010 , ARM64_SYSREG_TPIDR_EL3 = 63106 , ARM64_SYSREG_TRBBASER_EL1 = 50394 , ARM64_SYSREG_TRBIDR_EL1 = 50399 , ARM64_SYSREG_TRBLIMITR_EL1 = 50392 , ARM64_SYSREG_TRBMAR_EL1 = 50396 , ARM64_SYSREG_TRBPTR_EL1 = 50393 , ARM64_SYSREG_TRBSR_EL1 = 50395 , ARM64_SYSREG_TRBTRG_EL1 = 50398 , ARM64_SYSREG_TRCACATR0 = 35074 , ARM64_SYSREG_TRCACATR1 = 35090 , ARM64_SYSREG_TRCACATR10 = 35107 , ARM64_SYSREG_TRCACATR11 = 35123 , ARM64_SYSREG_TRCACATR12 = 35139 , ARM64_SYSREG_TRCACATR13 = 35155 , ARM64_SYSREG_TRCACATR14 = 35171 , ARM64_SYSREG_TRCACATR15 = 35187 , ARM64_SYSREG_TRCACATR2 = 35106 , ARM64_SYSREG_TRCACATR3 = 35122 , ARM64_SYSREG_TRCACATR4 = 35138 , ARM64_SYSREG_TRCACATR5 = 35154 , ARM64_SYSREG_TRCACATR6 = 35170 , ARM64_SYSREG_TRCACATR7 = 35186 , ARM64_SYSREG_TRCACATR8 = 35075 , ARM64_SYSREG_TRCACATR9 = 35091 , ARM64_SYSREG_TRCACVR0 = 35072 , ARM64_SYSREG_TRCACVR1 = 35088 , ARM64_SYSREG_TRCACVR10 = 35105 , ARM64_SYSREG_TRCACVR11 = 35121 , ARM64_SYSREG_TRCACVR12 = 35137 , ARM64_SYSREG_TRCACVR13 = 35153 , ARM64_SYSREG_TRCACVR14 = 35169 , ARM64_SYSREG_TRCACVR15 = 35185 , ARM64_SYSREG_TRCACVR2 = 35104 , ARM64_SYSREG_TRCACVR3 = 35120 , ARM64_SYSREG_TRCACVR4 = 35136 , ARM64_SYSREG_TRCACVR5 = 35152 , ARM64_SYSREG_TRCACVR6 = 35168 , ARM64_SYSREG_TRCACVR7 = 35184 , ARM64_SYSREG_TRCACVR8 = 35073 , ARM64_SYSREG_TRCACVR9 = 35089 , ARM64_SYSREG_TRCAUTHSTATUS = 35830 , ARM64_SYSREG_TRCAUXCTLR = 34864 , ARM64_SYSREG_TRCBBCTLR = 34936 , ARM64_SYSREG_TRCCCCTLR = 34928 , ARM64_SYSREG_TRCCIDCCTLR0 = 35202 , ARM64_SYSREG_TRCCIDCCTLR1 = 35210 , ARM64_SYSREG_TRCCIDCVR0 = 35200 , ARM64_SYSREG_TRCCIDCVR1 = 35216 , ARM64_SYSREG_TRCCIDCVR2 = 35232 , ARM64_SYSREG_TRCCIDCVR3 = 35248 , ARM64_SYSREG_TRCCIDCVR4 = 35264 , ARM64_SYSREG_TRCCIDCVR5 = 35280 , ARM64_SYSREG_TRCCIDCVR6 = 35296 , ARM64_SYSREG_TRCCIDCVR7 = 35312 , ARM64_SYSREG_TRCCIDR0 = 35815 , ARM64_SYSREG_TRCCIDR1 = 35823 , ARM64_SYSREG_TRCCIDR2 = 35831 , ARM64_SYSREG_TRCCIDR3 = 35839 , ARM64_SYSREG_TRCCLAIMCLR = 35790 , ARM64_SYSREG_TRCCLAIMSET = 35782 , ARM64_SYSREG_TRCCNTCTLR0 = 34853 , ARM64_SYSREG_TRCCNTCTLR1 = 34861 , ARM64_SYSREG_TRCCNTCTLR2 = 34869 , ARM64_SYSREG_TRCCNTCTLR3 = 34877 , ARM64_SYSREG_TRCCNTRLDVR0 = 34821 , ARM64_SYSREG_TRCCNTRLDVR1 = 34829 , ARM64_SYSREG_TRCCNTRLDVR2 = 34837 , ARM64_SYSREG_TRCCNTRLDVR3 = 34845 , ARM64_SYSREG_TRCCNTVR0 = 34885 , ARM64_SYSREG_TRCCNTVR1 = 34893 , ARM64_SYSREG_TRCCNTVR2 = 34901 , ARM64_SYSREG_TRCCNTVR3 = 34909 , ARM64_SYSREG_TRCCONFIGR = 34848 , ARM64_SYSREG_TRCDEVAFF0 = 35798 , ARM64_SYSREG_TRCDEVAFF1 = 35806 , ARM64_SYSREG_TRCDEVARCH = 35838 , ARM64_SYSREG_TRCDEVID = 35735 , ARM64_SYSREG_TRCDEVTYPE = 35743 , ARM64_SYSREG_TRCDVCMR0 = 35078 , ARM64_SYSREG_TRCDVCMR1 = 35110 , ARM64_SYSREG_TRCDVCMR2 = 35142 , ARM64_SYSREG_TRCDVCMR3 = 35174 , ARM64_SYSREG_TRCDVCMR4 = 35079 , ARM64_SYSREG_TRCDVCMR5 = 35111 , ARM64_SYSREG_TRCDVCMR6 = 35143 , ARM64_SYSREG_TRCDVCMR7 = 35175 , ARM64_SYSREG_TRCDVCVR0 = 35076 , ARM64_SYSREG_TRCDVCVR1 = 35108 , ARM64_SYSREG_TRCDVCVR2 = 35140 , ARM64_SYSREG_TRCDVCVR3 = 35172 , ARM64_SYSREG_TRCDVCVR4 = 35077 , ARM64_SYSREG_TRCDVCVR5 = 35109 , ARM64_SYSREG_TRCDVCVR6 = 35141 , ARM64_SYSREG_TRCDVCVR7 = 35173 , ARM64_SYSREG_TRCEVENTCTL0R = 34880 , ARM64_SYSREG_TRCEVENTCTL1R = 34888 , ARM64_SYSREG_TRCEXTINSELR = 34884 , ARM64_SYSREG_TRCEXTINSELR1 = 34892 , ARM64_SYSREG_TRCEXTINSELR2 = 34900 , ARM64_SYSREG_TRCEXTINSELR3 = 34908 , ARM64_SYSREG_TRCIDR0 = 34887 , ARM64_SYSREG_TRCIDR1 = 34895 , ARM64_SYSREG_TRCIDR10 = 34838 , ARM64_SYSREG_TRCIDR11 = 34846 , ARM64_SYSREG_TRCIDR12 = 34854 , ARM64_SYSREG_TRCIDR13 = 34862 , ARM64_SYSREG_TRCIDR2 = 34903 , ARM64_SYSREG_TRCIDR3 = 34911 , ARM64_SYSREG_TRCIDR4 = 34919 , ARM64_SYSREG_TRCIDR5 = 34927 , ARM64_SYSREG_TRCIDR6 = 34935 , ARM64_SYSREG_TRCIDR7 = 34943 , ARM64_SYSREG_TRCIDR8 = 34822 , ARM64_SYSREG_TRCIDR9 = 34830 , ARM64_SYSREG_TRCIMSPEC0 = 34823 , ARM64_SYSREG_TRCIMSPEC1 = 34831 , ARM64_SYSREG_TRCIMSPEC2 = 34839 , ARM64_SYSREG_TRCIMSPEC3 = 34847 , ARM64_SYSREG_TRCIMSPEC4 = 34855 , ARM64_SYSREG_TRCIMSPEC5 = 34863 , ARM64_SYSREG_TRCIMSPEC6 = 34871 , ARM64_SYSREG_TRCIMSPEC7 = 34879 , ARM64_SYSREG_TRCITCTRL = 35716 , ARM64_SYSREG_TRCLAR = 35814 , ARM64_SYSREG_TRCLSR = 35822 , ARM64_SYSREG_TRCOSLAR = 34948 , ARM64_SYSREG_TRCOSLSR = 34956 , ARM64_SYSREG_TRCPDCR = 34980 , ARM64_SYSREG_TRCPDSR = 34988 , ARM64_SYSREG_TRCPIDR0 = 35783 , ARM64_SYSREG_TRCPIDR1 = 35791 , ARM64_SYSREG_TRCPIDR2 = 35799 , ARM64_SYSREG_TRCPIDR3 = 35807 , ARM64_SYSREG_TRCPIDR4 = 35751 , ARM64_SYSREG_TRCPIDR5 = 35759 , ARM64_SYSREG_TRCPIDR6 = 35767 , ARM64_SYSREG_TRCPIDR7 = 35775 , ARM64_SYSREG_TRCPRGCTLR = 34824 , ARM64_SYSREG_TRCPROCSELR = 34832 , ARM64_SYSREG_TRCQCTLR = 34825 , ARM64_SYSREG_TRCRSCTLR10 = 35024 , ARM64_SYSREG_TRCRSCTLR11 = 35032 , ARM64_SYSREG_TRCRSCTLR12 = 35040 , ARM64_SYSREG_TRCRSCTLR13 = 35048 , ARM64_SYSREG_TRCRSCTLR14 = 35056 , ARM64_SYSREG_TRCRSCTLR15 = 35064 , ARM64_SYSREG_TRCRSCTLR16 = 34945 , ARM64_SYSREG_TRCRSCTLR17 = 34953 , ARM64_SYSREG_TRCRSCTLR18 = 34961 , ARM64_SYSREG_TRCRSCTLR19 = 34969 , ARM64_SYSREG_TRCRSCTLR2 = 34960 , ARM64_SYSREG_TRCRSCTLR20 = 34977 , ARM64_SYSREG_TRCRSCTLR21 = 34985 , ARM64_SYSREG_TRCRSCTLR22 = 34993 , ARM64_SYSREG_TRCRSCTLR23 = 35001 , ARM64_SYSREG_TRCRSCTLR24 = 35009 , ARM64_SYSREG_TRCRSCTLR25 = 35017 , ARM64_SYSREG_TRCRSCTLR26 = 35025 , ARM64_SYSREG_TRCRSCTLR27 = 35033 , ARM64_SYSREG_TRCRSCTLR28 = 35041 , ARM64_SYSREG_TRCRSCTLR29 = 35049 , ARM64_SYSREG_TRCRSCTLR3 = 34968 , ARM64_SYSREG_TRCRSCTLR30 = 35057 , ARM64_SYSREG_TRCRSCTLR31 = 35065 , ARM64_SYSREG_TRCRSCTLR4 = 34976 , ARM64_SYSREG_TRCRSCTLR5 = 34984 , ARM64_SYSREG_TRCRSCTLR6 = 34992 , ARM64_SYSREG_TRCRSCTLR7 = 35000 , ARM64_SYSREG_TRCRSCTLR8 = 35008 , ARM64_SYSREG_TRCRSCTLR9 = 35016 , ARM64_SYSREG_TRCRSR = 34896 , ARM64_SYSREG_TRCSEQEVR0 = 34820 , ARM64_SYSREG_TRCSEQEVR1 = 34828 , ARM64_SYSREG_TRCSEQEVR2 = 34836 , ARM64_SYSREG_TRCSEQRSTEVR = 34868 , ARM64_SYSREG_TRCSEQSTR = 34876 , ARM64_SYSREG_TRCSSCCR0 = 34946 , ARM64_SYSREG_TRCSSCCR1 = 34954 , ARM64_SYSREG_TRCSSCCR2 = 34962 , ARM64_SYSREG_TRCSSCCR3 = 34970 , ARM64_SYSREG_TRCSSCCR4 = 34978 , ARM64_SYSREG_TRCSSCCR5 = 34986 , ARM64_SYSREG_TRCSSCCR6 = 34994 , ARM64_SYSREG_TRCSSCCR7 = 35002 , ARM64_SYSREG_TRCSSCSR0 = 35010 , ARM64_SYSREG_TRCSSCSR1 = 35018 , ARM64_SYSREG_TRCSSCSR2 = 35026 , ARM64_SYSREG_TRCSSCSR3 = 35034 , ARM64_SYSREG_TRCSSCSR4 = 35042 , ARM64_SYSREG_TRCSSCSR5 = 35050 , ARM64_SYSREG_TRCSSCSR6 = 35058 , ARM64_SYSREG_TRCSSCSR7 = 35066 , ARM64_SYSREG_TRCSSPCICR0 = 34947 , ARM64_SYSREG_TRCSSPCICR1 = 34955 , ARM64_SYSREG_TRCSSPCICR2 = 34963 , ARM64_SYSREG_TRCSSPCICR3 = 34971 , ARM64_SYSREG_TRCSSPCICR4 = 34979 , ARM64_SYSREG_TRCSSPCICR5 = 34987 , ARM64_SYSREG_TRCSSPCICR6 = 34995 , ARM64_SYSREG_TRCSSPCICR7 = 35003 , ARM64_SYSREG_TRCSTALLCTLR = 34904 , ARM64_SYSREG_TRCSTATR = 34840 , ARM64_SYSREG_TRCSYNCPR = 34920 , ARM64_SYSREG_TRCTRACEIDR = 34817 , ARM64_SYSREG_TRCTSCTLR = 34912 , ARM64_SYSREG_TRCVDARCCTLR = 34898 , ARM64_SYSREG_TRCVDCTLR = 34882 , ARM64_SYSREG_TRCVDSACCTLR = 34890 , ARM64_SYSREG_TRCVICTLR = 34818 , ARM64_SYSREG_TRCVIIECTLR = 34826 , ARM64_SYSREG_TRCVIPCSSCTLR = 34842 , ARM64_SYSREG_TRCVISSCTLR = 34834 , ARM64_SYSREG_TRCVMIDCCTLR0 = 35218 , ARM64_SYSREG_TRCVMIDCCTLR1 = 35226 , ARM64_SYSREG_TRCVMIDCVR0 = 35201 , ARM64_SYSREG_TRCVMIDCVR1 = 35217 , ARM64_SYSREG_TRCVMIDCVR2 = 35233 , ARM64_SYSREG_TRCVMIDCVR3 = 35249 , ARM64_SYSREG_TRCVMIDCVR4 = 35265 , ARM64_SYSREG_TRCVMIDCVR5 = 35281 , ARM64_SYSREG_TRCVMIDCVR6 = 35297 , ARM64_SYSREG_TRCVMIDCVR7 = 35313 , ARM64_SYSREG_TRFCR_EL1 = 49297 , ARM64_SYSREG_TRFCR_EL12 = 59537 , ARM64_SYSREG_TRFCR_EL2 = 57489 , ARM64_SYSREG_TTBR0_EL1 = 49408 , ARM64_SYSREG_TTBR0_EL12 = 59648 , ARM64_SYSREG_TTBR0_EL2 = 57600 , ARM64_SYSREG_TTBR0_EL3 = 61696 , ARM64_SYSREG_TTBR1_EL1 = 49409 , ARM64_SYSREG_TTBR1_EL12 = 59649 , ARM64_SYSREG_TTBR1_EL2 = 57601 , ARM64_SYSREG_UAO = 49684 , ARM64_SYSREG_VBAR_EL1 = 50688 , ARM64_SYSREG_VBAR_EL12 = 60928 , ARM64_SYSREG_VBAR_EL2 = 58880 , ARM64_SYSREG_VBAR_EL3 = 62976 , ARM64_SYSREG_VDISR_EL2 = 58889 , ARM64_SYSREG_VMPIDR_EL2 = 57349 , ARM64_SYSREG_VNCR_EL2 = 57616 , ARM64_SYSREG_VPIDR_EL2 = 57344 , ARM64_SYSREG_VSESR_EL2 = 58003 , ARM64_SYSREG_VSTCR_EL2 = 57650 , ARM64_SYSREG_VSTTBR_EL2 = 57648 , ARM64_SYSREG_VTCR_EL2 = 57610 , ARM64_SYSREG_VTTBR_EL2 = 57608 , ARM64_SYSREG_ZCR_EL1 = 49296 , ARM64_SYSREG_ZCR_EL12 = 59536 , ARM64_SYSREG_ZCR_EL2 = 57488 , ARM64_SYSREG_ZCR_EL3 = 61584 , } # [repr (u32)] # [doc = " System PState Field (MSR instruction)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_pstate { ARM64_PSTATE_INVALID = 0 , ARM64_PSTATE_SPSEL = 5 , ARM64_PSTATE_DAIFSET = 30 , ARM64_PSTATE_DAIFCLR = 31 , ARM64_PSTATE_PAN = 4 , ARM64_PSTATE_UAO = 3 , ARM64_PSTATE_DIT = 26 , } # [repr (u32)] # [doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_vas { ARM64_VAS_INVALID = 0 , ARM64_VAS_16B = 1 , ARM64_VAS_8B = 2 , ARM64_VAS_4B = 3 , ARM64_VAS_1B = 4 , ARM64_VAS_8H = 5 , ARM64_VAS_4H = 6 , ARM64_VAS_2H = 7 , ARM64_VAS_1H = 8 , ARM64_VAS_4S = 9 , ARM64_VAS_2S = 10 , ARM64_VAS_1S = 11 , ARM64_VAS_2D = 12 , ARM64_VAS_1D = 13 , ARM64_VAS_1Q = 14 , } # [repr (u32)] # [doc = " Memory barrier operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0 , ARM64_BARRIER_OSHLD = 1 , ARM64_BARRIER_OSHST = 2 , ARM64_BARRIER_OSH = 3 , ARM64_BARRIER_NSHLD = 5 , ARM64_BARRIER_NSHST = 6 , ARM64_BARRIER_NSH = 7 , ARM64_BARRIER_ISHLD = 9 , ARM64_BARRIER_ISHST = 10 , ARM64_BARRIER_ISH = 11 , ARM64_BARRIER_LD = 13 , ARM64_BARRIER_ST = 14 , ARM64_BARRIER_SY = 15 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM64_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM64_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM64_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM64_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM64_OP_FP = 4 , # [doc = "< C-Immediate"] ARM64_OP_CIMM = 64 , # [doc = "< MRS register operand."] ARM64_OP_REG_MRS = 65 , # [doc = "< MSR register operand."] ARM64_OP_REG_MSR = 66 , # [doc = "< PState operand."] ARM64_OP_PSTATE = 67 , # [doc = "< SYS operand for IC/DC/AT/TLBI instructions."] ARM64_OP_SYS = 68 , # [doc = "< SVCR operand for MSR SVCR instructions."] ARM64_OP_SVCR = 69 , # [doc = "< Prefetch operand (PRFM)."] ARM64_OP_PREFETCH = 70 , # [doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."] ARM64_OP_BARRIER = 71 , # [doc = "< SME instruction operand with with index."] ARM64_OP_SME_INDEX = 72 , } # [repr (u32)] # [doc = " SYS operands (IC/DC/AC/TLBI)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sys_op { ARM64_SYS_INVALID = 0 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1 = 1 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1IS = 2 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1ISNXS = 3 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1NXS = 4 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OS = 5 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OSNXS = 6 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2 = 7 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2IS = 8 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2ISNXS = 9 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2NXS = 10 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OS = 11 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OSNXS = 12 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3 = 13 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3IS = 14 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3ISNXS = 15 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3NXS = 16 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OS = 17 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OSNXS = 18 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1 = 19 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1IS = 20 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1ISNXS = 21 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1NXS = 22 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OS = 23 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OSNXS = 24 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1 = 25 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1IS = 26 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1ISNXS = 27 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1NXS = 28 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OS = 29 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OSNXS = 30 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1 = 31 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1IS = 32 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1ISNXS = 33 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1NXS = 34 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OS = 35 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OSNXS = 36 , # [doc = " TLBI operations"] ARM64_TLBI_PAALL = 37 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLNXS = 38 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOS = 39 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOSNXS = 40 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1 = 41 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1IS = 42 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1ISNXS = 43 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1NXS = 44 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OS = 45 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OSNXS = 46 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1 = 47 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1IS = 48 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1ISNXS = 49 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1NXS = 50 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OS = 51 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OSNXS = 52 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOS = 53 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOSNXS = 54 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOS = 55 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOSNXS = 56 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1 = 57 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1IS = 58 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1ISNXS = 59 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1NXS = 60 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OS = 61 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OSNXS = 62 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1 = 63 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1IS = 64 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1ISNXS = 65 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1NXS = 66 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OS = 67 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OSNXS = 68 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1 = 69 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1IS = 70 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1ISNXS = 71 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1NXS = 72 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OS = 73 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OSNXS = 74 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2 = 75 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2IS = 76 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2ISNXS = 77 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2NXS = 78 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OS = 79 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OSNXS = 80 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3 = 81 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3IS = 82 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3ISNXS = 83 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3NXS = 84 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OS = 85 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OSNXS = 86 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1 = 87 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1IS = 88 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1ISNXS = 89 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1NXS = 90 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OS = 91 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OSNXS = 92 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2 = 93 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2IS = 94 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2ISNXS = 95 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2NXS = 96 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OS = 97 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OSNXS = 98 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3 = 99 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3IS = 100 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3ISNXS = 101 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3NXS = 102 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OS = 103 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OSNXS = 104 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1 = 105 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1IS = 106 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1ISNXS = 107 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1NXS = 108 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OS = 109 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OSNXS = 110 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1 = 111 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1IS = 112 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1ISNXS = 113 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1NXS = 114 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OS = 115 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OSNXS = 116 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1 = 117 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1IS = 118 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1ISNXS = 119 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1NXS = 120 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OS = 121 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OSNXS = 122 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2 = 123 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2IS = 124 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2ISNXS = 125 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2NXS = 126 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OS = 127 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OSNXS = 128 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3 = 129 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3IS = 130 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3ISNXS = 131 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3NXS = 132 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OS = 133 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OSNXS = 134 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1 = 135 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1IS = 136 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1ISNXS = 137 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1NXS = 138 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OS = 139 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OSNXS = 140 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2 = 141 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2IS = 142 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2ISNXS = 143 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2NXS = 144 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OS = 145 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OSNXS = 146 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3 = 147 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3IS = 148 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3ISNXS = 149 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3NXS = 150 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OS = 151 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OSNXS = 152 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1 = 153 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1IS = 154 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1ISNXS = 155 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1NXS = 156 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OS = 157 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OSNXS = 158 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1 = 159 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1IS = 160 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1ISNXS = 161 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1NXS = 162 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OS = 163 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OSNXS = 164 , # [doc = " AT operations"] ARM64_AT_S1E1R = 165 , # [doc = " AT operations"] ARM64_AT_S1E2R = 166 , # [doc = " AT operations"] ARM64_AT_S1E3R = 167 , # [doc = " AT operations"] ARM64_AT_S1E1W = 168 , # [doc = " AT operations"] ARM64_AT_S1E2W = 169 , # [doc = " AT operations"] ARM64_AT_S1E3W = 170 , # [doc = " AT operations"] ARM64_AT_S1E0R = 171 , # [doc = " AT operations"] ARM64_AT_S1E0W = 172 , # [doc = " AT operations"] ARM64_AT_S12E1R = 173 , # [doc = " AT operations"] ARM64_AT_S12E1W = 174 , # [doc = " AT operations"] ARM64_AT_S12E0R = 175 , # [doc = " AT operations"] ARM64_AT_S12E0W = 176 , # [doc = " AT operations"] ARM64_AT_S1E1RP = 177 , # [doc = " AT operations"] ARM64_AT_S1E1WP = 178 , # [doc = " DC operations"] ARM64_DC_CGDSW = 179 , # [doc = " DC operations"] ARM64_DC_CGDVAC = 180 , # [doc = " DC operations"] ARM64_DC_CGDVADP = 181 , # [doc = " DC operations"] ARM64_DC_CGDVAP = 182 , # [doc = " DC operations"] ARM64_DC_CGSW = 183 , # [doc = " DC operations"] ARM64_DC_CGVAC = 184 , # [doc = " DC operations"] ARM64_DC_CGVADP = 185 , # [doc = " DC operations"] ARM64_DC_CGVAP = 186 , # [doc = " DC operations"] ARM64_DC_CIGDSW = 187 , # [doc = " DC operations"] ARM64_DC_CIGDVAC = 188 , # [doc = " DC operations"] ARM64_DC_CIGSW = 189 , # [doc = " DC operations"] ARM64_DC_CIGVAC = 190 , # [doc = " DC operations"] ARM64_DC_CISW = 191 , # [doc = " DC operations"] ARM64_DC_CIVAC = 192 , # [doc = " DC operations"] ARM64_DC_CSW = 193 , # [doc = " DC operations"] ARM64_DC_CVAC = 194 , # [doc = " DC operations"] ARM64_DC_CVADP = 195 , # [doc = " DC operations"] ARM64_DC_CVAP = 196 , # [doc = " DC operations"] ARM64_DC_CVAU = 197 , # [doc = " DC operations"] ARM64_DC_GVA = 198 , # [doc = " DC operations"] ARM64_DC_GZVA = 199 , # [doc = " DC operations"] ARM64_DC_IGDSW = 200 , # [doc = " DC operations"] ARM64_DC_IGDVAC = 201 , # [doc = " DC operations"] ARM64_DC_IGSW = 202 , # [doc = " DC operations"] ARM64_DC_IGVAC = 203 , # [doc = " DC operations"] ARM64_DC_ISW = 204 , # [doc = " DC operations"] ARM64_DC_IVAC = 205 , # [doc = " DC operations"] ARM64_DC_ZVA = 206 , # [doc = " IC operations"] ARM64_IC_IALLUIS = 207 , # [doc = " IC operations"] ARM64_IC_IALLU = 208 , # [doc = " IC operations"] ARM64_IC_IVAU = 209 , } # [repr (u32)] # [doc = " SVCR operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_svcr_op { ARM64_SVCR_INVALID = 0 , ARM64_SVCR_SVCRSM = 1 , ARM64_SVCR_SVCRSMZA = 3 , ARM64_SVCR_SVCRZA = 2 , } # [repr (u32)] # [doc = " Prefetch operations (PRFM)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0 , ARM64_PRFM_PLDL1KEEP = 1 , ARM64_PRFM_PLDL1STRM = 2 , ARM64_PRFM_PLDL2KEEP = 3 , ARM64_PRFM_PLDL2STRM = 4 , ARM64_PRFM_PLDL3KEEP = 5 , ARM64_PRFM_PLDL3STRM = 6 , ARM64_PRFM_PLIL1KEEP = 9 , ARM64_PRFM_PLIL1STRM = 10 , ARM64_PRFM_PLIL2KEEP = 11 , ARM64_PRFM_PLIL2STRM = 12 , ARM64_PRFM_PLIL3KEEP = 13 , ARM64_PRFM_PLIL3STRM = 14 , ARM64_PRFM_PSTL1KEEP = 17 , ARM64_PRFM_PSTL1STRM = 18 , ARM64_PRFM_PSTL2KEEP = 19 , ARM64_PRFM_PSTL2STRM = 20 , ARM64_PRFM_PSTL3KEEP = 21 , ARM64_PRFM_PSTL3STRM = 22 , } impl arm64_reg { pub const ARM64_REG_IP0 : arm64_reg = arm64_reg :: ARM64_REG_X16 ; } impl arm64_reg { pub const ARM64_REG_IP1 : arm64_reg = arm64_reg :: ARM64_REG_X17 ; } impl arm64_reg { pub const ARM64_REG_X29 : arm64_reg = arm64_reg :: ARM64_REG_FP ; } impl arm64_reg { pub const ARM64_REG_X30 : arm64_reg = arm64_reg :: ARM64_REG_LR ; } # [repr (u32)] # [doc = " ARM64 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_reg { ARM64_REG_INVALID = 0 , ARM64_REG_FFR = 1 , ARM64_REG_FP = 2 , ARM64_REG_LR = 3 , ARM64_REG_NZCV = 4 , ARM64_REG_SP = 5 , ARM64_REG_VG = 6 , ARM64_REG_WSP = 7 , ARM64_REG_WZR = 8 , ARM64_REG_XZR = 9 , ARM64_REG_ZA = 10 , ARM64_REG_B0 = 11 , ARM64_REG_B1 = 12 , ARM64_REG_B2 = 13 , ARM64_REG_B3 = 14 , ARM64_REG_B4 = 15 , ARM64_REG_B5 = 16 , ARM64_REG_B6 = 17 , ARM64_REG_B7 = 18 , ARM64_REG_B8 = 19 , ARM64_REG_B9 = 20 , ARM64_REG_B10 = 21 , ARM64_REG_B11 = 22 , ARM64_REG_B12 = 23 , ARM64_REG_B13 = 24 , ARM64_REG_B14 = 25 , ARM64_REG_B15 = 26 , ARM64_REG_B16 = 27 , ARM64_REG_B17 = 28 , ARM64_REG_B18 = 29 , ARM64_REG_B19 = 30 , ARM64_REG_B20 = 31 , ARM64_REG_B21 = 32 , ARM64_REG_B22 = 33 , ARM64_REG_B23 = 34 , ARM64_REG_B24 = 35 , ARM64_REG_B25 = 36 , ARM64_REG_B26 = 37 , ARM64_REG_B27 = 38 , ARM64_REG_B28 = 39 , ARM64_REG_B29 = 40 , ARM64_REG_B30 = 41 , ARM64_REG_B31 = 42 , ARM64_REG_D0 = 43 , ARM64_REG_D1 = 44 , ARM64_REG_D2 = 45 , ARM64_REG_D3 = 46 , ARM64_REG_D4 = 47 , ARM64_REG_D5 = 48 , ARM64_REG_D6 = 49 , ARM64_REG_D7 = 50 , ARM64_REG_D8 = 51 , ARM64_REG_D9 = 52 , ARM64_REG_D10 = 53 , ARM64_REG_D11 = 54 , ARM64_REG_D12 = 55 , ARM64_REG_D13 = 56 , ARM64_REG_D14 = 57 , ARM64_REG_D15 = 58 , ARM64_REG_D16 = 59 , ARM64_REG_D17 = 60 , ARM64_REG_D18 = 61 , ARM64_REG_D19 = 62 , ARM64_REG_D20 = 63 , ARM64_REG_D21 = 64 , ARM64_REG_D22 = 65 , ARM64_REG_D23 = 66 , ARM64_REG_D24 = 67 , ARM64_REG_D25 = 68 , ARM64_REG_D26 = 69 , ARM64_REG_D27 = 70 , ARM64_REG_D28 = 71 , ARM64_REG_D29 = 72 , ARM64_REG_D30 = 73 , ARM64_REG_D31 = 74 , ARM64_REG_H0 = 75 , ARM64_REG_H1 = 76 , ARM64_REG_H2 = 77 , ARM64_REG_H3 = 78 , ARM64_REG_H4 = 79 , ARM64_REG_H5 = 80 , ARM64_REG_H6 = 81 , ARM64_REG_H7 = 82 , ARM64_REG_H8 = 83 , ARM64_REG_H9 = 84 , ARM64_REG_H10 = 85 , ARM64_REG_H11 = 86 , ARM64_REG_H12 = 87 , ARM64_REG_H13 = 88 , ARM64_REG_H14 = 89 , ARM64_REG_H15 = 90 , ARM64_REG_H16 = 91 , ARM64_REG_H17 = 92 , ARM64_REG_H18 = 93 , ARM64_REG_H19 = 94 , ARM64_REG_H20 = 95 , ARM64_REG_H21 = 96 , ARM64_REG_H22 = 97 , ARM64_REG_H23 = 98 , ARM64_REG_H24 = 99 , ARM64_REG_H25 = 100 , ARM64_REG_H26 = 101 , ARM64_REG_H27 = 102 , ARM64_REG_H28 = 103 , ARM64_REG_H29 = 104 , ARM64_REG_H30 = 105 , ARM64_REG_H31 = 106 , ARM64_REG_P0 = 107 , ARM64_REG_P1 = 108 , ARM64_REG_P2 = 109 , ARM64_REG_P3 = 110 , ARM64_REG_P4 = 111 , ARM64_REG_P5 = 112 , ARM64_REG_P6 = 113 , ARM64_REG_P7 = 114 , ARM64_REG_P8 = 115 , ARM64_REG_P9 = 116 , ARM64_REG_P10 = 117 , ARM64_REG_P11 = 118 , ARM64_REG_P12 = 119 , ARM64_REG_P13 = 120 , ARM64_REG_P14 = 121 , ARM64_REG_P15 = 122 , ARM64_REG_Q0 = 123 , ARM64_REG_Q1 = 124 , ARM64_REG_Q2 = 125 , ARM64_REG_Q3 = 126 , ARM64_REG_Q4 = 127 , ARM64_REG_Q5 = 128 , ARM64_REG_Q6 = 129 , ARM64_REG_Q7 = 130 , ARM64_REG_Q8 = 131 , ARM64_REG_Q9 = 132 , ARM64_REG_Q10 = 133 , ARM64_REG_Q11 = 134 , ARM64_REG_Q12 = 135 , ARM64_REG_Q13 = 136 , ARM64_REG_Q14 = 137 , ARM64_REG_Q15 = 138 , ARM64_REG_Q16 = 139 , ARM64_REG_Q17 = 140 , ARM64_REG_Q18 = 141 , ARM64_REG_Q19 = 142 , ARM64_REG_Q20 = 143 , ARM64_REG_Q21 = 144 , ARM64_REG_Q22 = 145 , ARM64_REG_Q23 = 146 , ARM64_REG_Q24 = 147 , ARM64_REG_Q25 = 148 , ARM64_REG_Q26 = 149 , ARM64_REG_Q27 = 150 , ARM64_REG_Q28 = 151 , ARM64_REG_Q29 = 152 , ARM64_REG_Q30 = 153 , ARM64_REG_Q31 = 154 , ARM64_REG_S0 = 155 , ARM64_REG_S1 = 156 , ARM64_REG_S2 = 157 , ARM64_REG_S3 = 158 , ARM64_REG_S4 = 159 , ARM64_REG_S5 = 160 , ARM64_REG_S6 = 161 , ARM64_REG_S7 = 162 , ARM64_REG_S8 = 163 , ARM64_REG_S9 = 164 , ARM64_REG_S10 = 165 , ARM64_REG_S11 = 166 , ARM64_REG_S12 = 167 , ARM64_REG_S13 = 168 , ARM64_REG_S14 = 169 , ARM64_REG_S15 = 170 , ARM64_REG_S16 = 171 , ARM64_REG_S17 = 172 , ARM64_REG_S18 = 173 , ARM64_REG_S19 = 174 , ARM64_REG_S20 = 175 , ARM64_REG_S21 = 176 , ARM64_REG_S22 = 177 , ARM64_REG_S23 = 178 , ARM64_REG_S24 = 179 , ARM64_REG_S25 = 180 , ARM64_REG_S26 = 181 , ARM64_REG_S27 = 182 , ARM64_REG_S28 = 183 , ARM64_REG_S29 = 184 , ARM64_REG_S30 = 185 , ARM64_REG_S31 = 186 , ARM64_REG_W0 = 187 , ARM64_REG_W1 = 188 , ARM64_REG_W2 = 189 , ARM64_REG_W3 = 190 , ARM64_REG_W4 = 191 , ARM64_REG_W5 = 192 , ARM64_REG_W6 = 193 , ARM64_REG_W7 = 194 , ARM64_REG_W8 = 195 , ARM64_REG_W9 = 196 , ARM64_REG_W10 = 197 , ARM64_REG_W11 = 198 , ARM64_REG_W12 = 199 , ARM64_REG_W13 = 200 , ARM64_REG_W14 = 201 , ARM64_REG_W15 = 202 , ARM64_REG_W16 = 203 , ARM64_REG_W17 = 204 , ARM64_REG_W18 = 205 , ARM64_REG_W19 = 206 , ARM64_REG_W20 = 207 , ARM64_REG_W21 = 208 , ARM64_REG_W22 = 209 , ARM64_REG_W23 = 210 , ARM64_REG_W24 = 211 , ARM64_REG_W25 = 212 , ARM64_REG_W26 = 213 , ARM64_REG_W27 = 214 , ARM64_REG_W28 = 215 , ARM64_REG_W29 = 216 , ARM64_REG_W30 = 217 , ARM64_REG_X0 = 218 , ARM64_REG_X1 = 219 , ARM64_REG_X2 = 220 , ARM64_REG_X3 = 221 , ARM64_REG_X4 = 222 , ARM64_REG_X5 = 223 , ARM64_REG_X6 = 224 , ARM64_REG_X7 = 225 , ARM64_REG_X8 = 226 , ARM64_REG_X9 = 227 , ARM64_REG_X10 = 228 , ARM64_REG_X11 = 229 , ARM64_REG_X12 = 230 , ARM64_REG_X13 = 231 , ARM64_REG_X14 = 232 , ARM64_REG_X15 = 233 , ARM64_REG_X16 = 234 , ARM64_REG_X17 = 235 , ARM64_REG_X18 = 236 , ARM64_REG_X19 = 237 , ARM64_REG_X20 = 238 , ARM64_REG_X21 = 239 , ARM64_REG_X22 = 240 , ARM64_REG_X23 = 241 , ARM64_REG_X24 = 242 , ARM64_REG_X25 = 243 , ARM64_REG_X26 = 244 , ARM64_REG_X27 = 245 , ARM64_REG_X28 = 246 , ARM64_REG_Z0 = 247 , ARM64_REG_Z1 = 248 , ARM64_REG_Z2 = 249 , ARM64_REG_Z3 = 250 , ARM64_REG_Z4 = 251 , ARM64_REG_Z5 = 252 , ARM64_REG_Z6 = 253 , ARM64_REG_Z7 = 254 , ARM64_REG_Z8 = 255 , ARM64_REG_Z9 = 256 , ARM64_REG_Z10 = 257 , ARM64_REG_Z11 = 258 , ARM64_REG_Z12 = 259 , ARM64_REG_Z13 = 260 , ARM64_REG_Z14 = 261 , ARM64_REG_Z15 = 262 , ARM64_REG_Z16 = 263 , ARM64_REG_Z17 = 264 , ARM64_REG_Z18 = 265 , ARM64_REG_Z19 = 266 , ARM64_REG_Z20 = 267 , ARM64_REG_Z21 = 268 , ARM64_REG_Z22 = 269 , ARM64_REG_Z23 = 270 , ARM64_REG_Z24 = 271 , ARM64_REG_Z25 = 272 , ARM64_REG_Z26 = 273 , ARM64_REG_Z27 = 274 , ARM64_REG_Z28 = 275 , ARM64_REG_Z29 = 276 , ARM64_REG_Z30 = 277 , ARM64_REG_Z31 = 278 , ARM64_REG_ZAB0 = 279 , ARM64_REG_ZAD0 = 280 , ARM64_REG_ZAD1 = 281 , ARM64_REG_ZAD2 = 282 , ARM64_REG_ZAD3 = 283 , ARM64_REG_ZAD4 = 284 , ARM64_REG_ZAD5 = 285 , ARM64_REG_ZAD6 = 286 , ARM64_REG_ZAD7 = 287 , ARM64_REG_ZAH0 = 288 , ARM64_REG_ZAH1 = 289 , ARM64_REG_ZAQ0 = 290 , ARM64_REG_ZAQ1 = 291 , ARM64_REG_ZAQ2 = 292 , ARM64_REG_ZAQ3 = 293 , ARM64_REG_ZAQ4 = 294 , ARM64_REG_ZAQ5 = 295 , ARM64_REG_ZAQ6 = 296 , ARM64_REG_ZAQ7 = 297 , ARM64_REG_ZAQ8 = 298 , ARM64_REG_ZAQ9 = 299 , ARM64_REG_ZAQ10 = 300 , ARM64_REG_ZAQ11 = 301 , ARM64_REG_ZAQ12 = 302 , ARM64_REG_ZAQ13 = 303 , ARM64_REG_ZAQ14 = 304 , ARM64_REG_ZAQ15 = 305 , ARM64_REG_ZAS0 = 306 , ARM64_REG_ZAS1 = 307 , ARM64_REG_ZAS2 = 308 , ARM64_REG_ZAS3 = 309 , ARM64_REG_V0 = 310 , ARM64_REG_V1 = 311 , ARM64_REG_V2 = 312 , ARM64_REG_V3 = 313 , ARM64_REG_V4 = 314 , ARM64_REG_V5 = 315 , ARM64_REG_V6 = 316 , ARM64_REG_V7 = 317 , ARM64_REG_V8 = 318 , ARM64_REG_V9 = 319 , ARM64_REG_V10 = 320 , ARM64_REG_V11 = 321 , ARM64_REG_V12 = 322 , ARM64_REG_V13 = 323 , ARM64_REG_V14 = 324 , ARM64_REG_V15 = 325 , ARM64_REG_V16 = 326 , ARM64_REG_V17 = 327 , ARM64_REG_V18 = 328 , ARM64_REG_V19 = 329 , ARM64_REG_V20 = 330 , ARM64_REG_V21 = 331 , ARM64_REG_V22 = 332 , ARM64_REG_V23 = 333 , ARM64_REG_V24 = 334 , ARM64_REG_V25 = 335 , ARM64_REG_V26 = 336 , ARM64_REG_V27 = 337 , ARM64_REG_V28 = 338 , ARM64_REG_V29 = 339 , ARM64_REG_V30 = 340 , ARM64_REG_V31 = 341 , ARM64_REG_ENDING = 342 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_mem { # [doc = "< base register"] pub base : arm64_reg , # [doc = "< index register"] pub index : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_mem"] [:: std :: mem :: size_of :: < arm64_op_mem > () - 12usize] ; ["Alignment of arm64_op_mem"] [:: std :: mem :: align_of :: < arm64_op_mem > () - 4usize] ; ["Offset of field: arm64_op_mem::base"] [:: std :: mem :: offset_of ! (arm64_op_mem , base) - 0usize] ; ["Offset of field: arm64_op_mem::index"] [:: std :: mem :: offset_of ! (arm64_op_mem , index) - 4usize] ; ["Offset of field: arm64_op_mem::disp"] [:: std :: mem :: offset_of ! (arm64_op_mem , disp) - 8usize] ; } ; # [doc = " SME Instruction's operand has index\n This is associated with ARM64_OP_SME_INDEX operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_sme_index { # [doc = "< register being indexed"] pub reg : arm64_reg , # [doc = "< base register"] pub base : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_sme_index"] [:: std :: mem :: size_of :: < arm64_op_sme_index > () - 12usize] ; ["Alignment of arm64_op_sme_index"] [:: std :: mem :: align_of :: < arm64_op_sme_index > () - 4usize] ; ["Offset of field: arm64_op_sme_index::reg"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , reg) - 0usize] ; ["Offset of field: arm64_op_sme_index::base"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , base) - 4usize] ; ["Offset of field: arm64_op_sme_index::disp"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64_op { # [doc = "< Vector Index for some vector operands (or -1 if\n< irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , # [doc = "< Vector Arrangement Specifier"] pub vas : arm64_vas , pub shift : cs_arm64_op__bindgen_ty_1 , # [doc = "< extender type of this operand"] pub ext : arm64_extender , # [doc = "< operand type"] pub type_ : arm64_op_type , # [doc = "< MSR/MRS SVCR instruction variant."] pub svcr : arm64_svcr_op , pub __bindgen_anon_1 : cs_arm64_op__bindgen_ty_2 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm64_op__bindgen_ty_1 { # [doc = "< shifter type of this operand"] pub type_ : arm64_shifter , # [doc = "< shifter value of this operand"] pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm64_op__bindgen_ty_2 { # [doc = "< register value for REG operand"] pub reg : arm64_reg , # [doc = "< immediate value, or index for C-IMM or IMM operand"] pub imm : i64 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm64_op_mem , # [doc = "< PState field of MSR instruction."] pub pstate : arm64_pstate , # [doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op,\n< arm64_dc_op, arm64_at_op, arm64_tlbi_op)"] pub sys : arm64_sys_op , # [doc = "< PRFM operation."] pub prefetch : arm64_prefetch_op , # [doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."] pub barrier : arm64_barrier_op , # [doc = "< base/disp value for matrix tile slice\n< instructions."] pub sme_index : arm64_op_sme_index , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_2 > () - 16usize] ; ["Alignment of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::pstate"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , pstate) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sys"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sys) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::prefetch"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , prefetch) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::barrier"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , barrier) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sme_index"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sme_index) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op"] [:: std :: mem :: size_of :: < cs_arm64_op > () - 56usize] ; ["Alignment of cs_arm64_op"] [:: std :: mem :: align_of :: < cs_arm64_op > () - 8usize] ; ["Offset of field: cs_arm64_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm64_op , vector_index) - 0usize] ; ["Offset of field: cs_arm64_op::vas"] [:: std :: mem :: offset_of ! (cs_arm64_op , vas) - 4usize] ; ["Offset of field: cs_arm64_op::shift"] [:: std :: mem :: offset_of ! (cs_arm64_op , shift) - 8usize] ; ["Offset of field: cs_arm64_op::ext"] [:: std :: mem :: offset_of ! (cs_arm64_op , ext) - 16usize] ; ["Offset of field: cs_arm64_op::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op , type_) - 20usize] ; ["Offset of field: cs_arm64_op::svcr"] [:: std :: mem :: offset_of ! (cs_arm64_op , svcr) - 24usize] ; ["Offset of field: cs_arm64_op::access"] [:: std :: mem :: offset_of ! (cs_arm64_op , access) - 48usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, svcr: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . svcr , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64 { # [doc = "< conditional code for this insn"] pub cc : arm64_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn request writeback? 'True' means 'yes'"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm64_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64"] [:: std :: mem :: size_of :: < cs_arm64 > () - 456usize] ; ["Alignment of cs_arm64"] [:: std :: mem :: align_of :: < cs_arm64 > () - 8usize] ; ["Offset of field: cs_arm64::cc"] [:: std :: mem :: offset_of ! (cs_arm64 , cc) - 0usize] ; ["Offset of field: cs_arm64::update_flags"] [:: std :: mem :: offset_of ! (cs_arm64 , update_flags) - 4usize] ; ["Offset of field: cs_arm64::writeback"] [:: std :: mem :: offset_of ! (cs_arm64 , writeback) - 5usize] ; ["Offset of field: cs_arm64::post_index"] [:: std :: mem :: offset_of ! (cs_arm64 , post_index) - 6usize] ; ["Offset of field: cs_arm64::op_count"] [:: std :: mem :: offset_of ! (cs_arm64 , op_count) - 7usize] ; ["Offset of field: cs_arm64::operands"] [:: std :: mem :: offset_of ! (cs_arm64 , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . post_index , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM64 instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn { ARM64_INS_INVALID = 0 , ARM64_INS_ABS = 1 , ARM64_INS_ADC = 2 , ARM64_INS_ADCLB = 3 , ARM64_INS_ADCLT = 4 , ARM64_INS_ADCS = 5 , ARM64_INS_ADD = 6 , ARM64_INS_ADDG = 7 , ARM64_INS_ADDHA = 8 , ARM64_INS_ADDHN = 9 , ARM64_INS_ADDHN2 = 10 , ARM64_INS_ADDHNB = 11 , ARM64_INS_ADDHNT = 12 , ARM64_INS_ADDP = 13 , ARM64_INS_ADDPL = 14 , ARM64_INS_ADDS = 15 , ARM64_INS_ADDV = 16 , ARM64_INS_ADDVA = 17 , ARM64_INS_ADDVL = 18 , ARM64_INS_ADR = 19 , ARM64_INS_ADRP = 20 , ARM64_INS_AESD = 21 , ARM64_INS_AESE = 22 , ARM64_INS_AESIMC = 23 , ARM64_INS_AESMC = 24 , ARM64_INS_AND = 25 , ARM64_INS_ANDS = 26 , ARM64_INS_ANDV = 27 , ARM64_INS_ASR = 28 , ARM64_INS_ASRD = 29 , ARM64_INS_ASRR = 30 , ARM64_INS_ASRV = 31 , ARM64_INS_AUTDA = 32 , ARM64_INS_AUTDB = 33 , ARM64_INS_AUTDZA = 34 , ARM64_INS_AUTDZB = 35 , ARM64_INS_AUTIA = 36 , ARM64_INS_AUTIA1716 = 37 , ARM64_INS_AUTIASP = 38 , ARM64_INS_AUTIAZ = 39 , ARM64_INS_AUTIB = 40 , ARM64_INS_AUTIB1716 = 41 , ARM64_INS_AUTIBSP = 42 , ARM64_INS_AUTIBZ = 43 , ARM64_INS_AUTIZA = 44 , ARM64_INS_AUTIZB = 45 , ARM64_INS_AXFLAG = 46 , ARM64_INS_B = 47 , ARM64_INS_BC = 48 , ARM64_INS_BCAX = 49 , ARM64_INS_BDEP = 50 , ARM64_INS_BEXT = 51 , ARM64_INS_BFCVT = 52 , ARM64_INS_BFCVTN = 53 , ARM64_INS_BFCVTN2 = 54 , ARM64_INS_BFCVTNT = 55 , ARM64_INS_BFDOT = 56 , ARM64_INS_BFM = 57 , ARM64_INS_BFMLALB = 58 , ARM64_INS_BFMLALT = 59 , ARM64_INS_BFMMLA = 60 , ARM64_INS_BFMOPA = 61 , ARM64_INS_BFMOPS = 62 , ARM64_INS_BGRP = 63 , ARM64_INS_BIC = 64 , ARM64_INS_BICS = 65 , ARM64_INS_BIF = 66 , ARM64_INS_BIT = 67 , ARM64_INS_BL = 68 , ARM64_INS_BLR = 69 , ARM64_INS_BLRAA = 70 , ARM64_INS_BLRAAZ = 71 , ARM64_INS_BLRAB = 72 , ARM64_INS_BLRABZ = 73 , ARM64_INS_BR = 74 , ARM64_INS_BRAA = 75 , ARM64_INS_BRAAZ = 76 , ARM64_INS_BRAB = 77 , ARM64_INS_BRABZ = 78 , ARM64_INS_BRB = 79 , ARM64_INS_BRK = 80 , ARM64_INS_BRKA = 81 , ARM64_INS_BRKAS = 82 , ARM64_INS_BRKB = 83 , ARM64_INS_BRKBS = 84 , ARM64_INS_BRKN = 85 , ARM64_INS_BRKNS = 86 , ARM64_INS_BRKPA = 87 , ARM64_INS_BRKPAS = 88 , ARM64_INS_BRKPB = 89 , ARM64_INS_BRKPBS = 90 , ARM64_INS_BSL = 91 , ARM64_INS_BSL1N = 92 , ARM64_INS_BSL2N = 93 , ARM64_INS_BTI = 94 , ARM64_INS_CADD = 95 , ARM64_INS_CAS = 96 , ARM64_INS_CASA = 97 , ARM64_INS_CASAB = 98 , ARM64_INS_CASAH = 99 , ARM64_INS_CASAL = 100 , ARM64_INS_CASALB = 101 , ARM64_INS_CASALH = 102 , ARM64_INS_CASB = 103 , ARM64_INS_CASH = 104 , ARM64_INS_CASL = 105 , ARM64_INS_CASLB = 106 , ARM64_INS_CASLH = 107 , ARM64_INS_CASP = 108 , ARM64_INS_CASPA = 109 , ARM64_INS_CASPAL = 110 , ARM64_INS_CASPL = 111 , ARM64_INS_CBNZ = 112 , ARM64_INS_CBZ = 113 , ARM64_INS_CCMN = 114 , ARM64_INS_CCMP = 115 , ARM64_INS_CDOT = 116 , ARM64_INS_CFINV = 117 , ARM64_INS_CINC = 118 , ARM64_INS_CINV = 119 , ARM64_INS_CLASTA = 120 , ARM64_INS_CLASTB = 121 , ARM64_INS_CLREX = 122 , ARM64_INS_CLS = 123 , ARM64_INS_CLZ = 124 , ARM64_INS_CMEQ = 125 , ARM64_INS_CMGE = 126 , ARM64_INS_CMGT = 127 , ARM64_INS_CMHI = 128 , ARM64_INS_CMHS = 129 , ARM64_INS_CMLA = 130 , ARM64_INS_CMLE = 131 , ARM64_INS_CMLO = 132 , ARM64_INS_CMLS = 133 , ARM64_INS_CMLT = 134 , ARM64_INS_CMN = 135 , ARM64_INS_CMP = 136 , ARM64_INS_CMPEQ = 137 , ARM64_INS_CMPGE = 138 , ARM64_INS_CMPGT = 139 , ARM64_INS_CMPHI = 140 , ARM64_INS_CMPHS = 141 , ARM64_INS_CMPLE = 142 , ARM64_INS_CMPLO = 143 , ARM64_INS_CMPLS = 144 , ARM64_INS_CMPLT = 145 , ARM64_INS_CMPNE = 146 , ARM64_INS_CMPP = 147 , ARM64_INS_CMTST = 148 , ARM64_INS_CNEG = 149 , ARM64_INS_CNOT = 150 , ARM64_INS_CNT = 151 , ARM64_INS_CNTB = 152 , ARM64_INS_CNTD = 153 , ARM64_INS_CNTH = 154 , ARM64_INS_CNTP = 155 , ARM64_INS_CNTW = 156 , ARM64_INS_COMPACT = 157 , ARM64_INS_CPY = 158 , ARM64_INS_CPYE = 159 , ARM64_INS_CPYEN = 160 , ARM64_INS_CPYERN = 161 , ARM64_INS_CPYERT = 162 , ARM64_INS_CPYERTN = 163 , ARM64_INS_CPYERTRN = 164 , ARM64_INS_CPYERTWN = 165 , ARM64_INS_CPYET = 166 , ARM64_INS_CPYETN = 167 , ARM64_INS_CPYETRN = 168 , ARM64_INS_CPYETWN = 169 , ARM64_INS_CPYEWN = 170 , ARM64_INS_CPYEWT = 171 , ARM64_INS_CPYEWTN = 172 , ARM64_INS_CPYEWTRN = 173 , ARM64_INS_CPYEWTWN = 174 , ARM64_INS_CPYFE = 175 , ARM64_INS_CPYFEN = 176 , ARM64_INS_CPYFERN = 177 , ARM64_INS_CPYFERT = 178 , ARM64_INS_CPYFERTN = 179 , ARM64_INS_CPYFERTRN = 180 , ARM64_INS_CPYFERTWN = 181 , ARM64_INS_CPYFET = 182 , ARM64_INS_CPYFETN = 183 , ARM64_INS_CPYFETRN = 184 , ARM64_INS_CPYFETWN = 185 , ARM64_INS_CPYFEWN = 186 , ARM64_INS_CPYFEWT = 187 , ARM64_INS_CPYFEWTN = 188 , ARM64_INS_CPYFEWTRN = 189 , ARM64_INS_CPYFEWTWN = 190 , ARM64_INS_CPYFM = 191 , ARM64_INS_CPYFMN = 192 , ARM64_INS_CPYFMRN = 193 , ARM64_INS_CPYFMRT = 194 , ARM64_INS_CPYFMRTN = 195 , ARM64_INS_CPYFMRTRN = 196 , ARM64_INS_CPYFMRTWN = 197 , ARM64_INS_CPYFMT = 198 , ARM64_INS_CPYFMTN = 199 , ARM64_INS_CPYFMTRN = 200 , ARM64_INS_CPYFMTWN = 201 , ARM64_INS_CPYFMWN = 202 , ARM64_INS_CPYFMWT = 203 , ARM64_INS_CPYFMWTN = 204 , ARM64_INS_CPYFMWTRN = 205 , ARM64_INS_CPYFMWTWN = 206 , ARM64_INS_CPYFP = 207 , ARM64_INS_CPYFPN = 208 , ARM64_INS_CPYFPRN = 209 , ARM64_INS_CPYFPRT = 210 , ARM64_INS_CPYFPRTN = 211 , ARM64_INS_CPYFPRTRN = 212 , ARM64_INS_CPYFPRTWN = 213 , ARM64_INS_CPYFPT = 214 , ARM64_INS_CPYFPTN = 215 , ARM64_INS_CPYFPTRN = 216 , ARM64_INS_CPYFPTWN = 217 , ARM64_INS_CPYFPWN = 218 , ARM64_INS_CPYFPWT = 219 , ARM64_INS_CPYFPWTN = 220 , ARM64_INS_CPYFPWTRN = 221 , ARM64_INS_CPYFPWTWN = 222 , ARM64_INS_CPYM = 223 , ARM64_INS_CPYMN = 224 , ARM64_INS_CPYMRN = 225 , ARM64_INS_CPYMRT = 226 , ARM64_INS_CPYMRTN = 227 , ARM64_INS_CPYMRTRN = 228 , ARM64_INS_CPYMRTWN = 229 , ARM64_INS_CPYMT = 230 , ARM64_INS_CPYMTN = 231 , ARM64_INS_CPYMTRN = 232 , ARM64_INS_CPYMTWN = 233 , ARM64_INS_CPYMWN = 234 , ARM64_INS_CPYMWT = 235 , ARM64_INS_CPYMWTN = 236 , ARM64_INS_CPYMWTRN = 237 , ARM64_INS_CPYMWTWN = 238 , ARM64_INS_CPYP = 239 , ARM64_INS_CPYPN = 240 , ARM64_INS_CPYPRN = 241 , ARM64_INS_CPYPRT = 242 , ARM64_INS_CPYPRTN = 243 , ARM64_INS_CPYPRTRN = 244 , ARM64_INS_CPYPRTWN = 245 , ARM64_INS_CPYPT = 246 , ARM64_INS_CPYPTN = 247 , ARM64_INS_CPYPTRN = 248 , ARM64_INS_CPYPTWN = 249 , ARM64_INS_CPYPWN = 250 , ARM64_INS_CPYPWT = 251 , ARM64_INS_CPYPWTN = 252 , ARM64_INS_CPYPWTRN = 253 , ARM64_INS_CPYPWTWN = 254 , ARM64_INS_CRC32B = 255 , ARM64_INS_CRC32CB = 256 , ARM64_INS_CRC32CH = 257 , ARM64_INS_CRC32CW = 258 , ARM64_INS_CRC32CX = 259 , ARM64_INS_CRC32H = 260 , ARM64_INS_CRC32W = 261 , ARM64_INS_CRC32X = 262 , ARM64_INS_CSDB = 263 , ARM64_INS_CSEL = 264 , ARM64_INS_CSET = 265 , ARM64_INS_CSETM = 266 , ARM64_INS_CSINC = 267 , ARM64_INS_CSINV = 268 , ARM64_INS_CSNEG = 269 , ARM64_INS_CTERMEQ = 270 , ARM64_INS_CTERMNE = 271 , ARM64_INS_DCPS1 = 272 , ARM64_INS_DCPS2 = 273 , ARM64_INS_DCPS3 = 274 , ARM64_INS_DECB = 275 , ARM64_INS_DECD = 276 , ARM64_INS_DECH = 277 , ARM64_INS_DECP = 278 , ARM64_INS_DECW = 279 , ARM64_INS_DFB = 280 , ARM64_INS_DGH = 281 , ARM64_INS_DMB = 282 , ARM64_INS_DRPS = 283 , ARM64_INS_DSB = 284 , ARM64_INS_DUP = 285 , ARM64_INS_DUPM = 286 , ARM64_INS_EON = 287 , ARM64_INS_EOR = 288 , ARM64_INS_EOR3 = 289 , ARM64_INS_EORBT = 290 , ARM64_INS_EORS = 291 , ARM64_INS_EORTB = 292 , ARM64_INS_EORV = 293 , ARM64_INS_ERET = 294 , ARM64_INS_ERETAA = 295 , ARM64_INS_ERETAB = 296 , ARM64_INS_ESB = 297 , ARM64_INS_EXT = 298 , ARM64_INS_EXTR = 299 , ARM64_INS_FABD = 300 , ARM64_INS_FABS = 301 , ARM64_INS_FACGE = 302 , ARM64_INS_FACGT = 303 , ARM64_INS_FACLE = 304 , ARM64_INS_FACLT = 305 , ARM64_INS_FADD = 306 , ARM64_INS_FADDA = 307 , ARM64_INS_FADDP = 308 , ARM64_INS_FADDV = 309 , ARM64_INS_FCADD = 310 , ARM64_INS_FCCMP = 311 , ARM64_INS_FCCMPE = 312 , ARM64_INS_FCMEQ = 313 , ARM64_INS_FCMGE = 314 , ARM64_INS_FCMGT = 315 , ARM64_INS_FCMLA = 316 , ARM64_INS_FCMLE = 317 , ARM64_INS_FCMLT = 318 , ARM64_INS_FCMNE = 319 , ARM64_INS_FCMP = 320 , ARM64_INS_FCMPE = 321 , ARM64_INS_FCMUO = 322 , ARM64_INS_FCPY = 323 , ARM64_INS_FCSEL = 324 , ARM64_INS_FCVT = 325 , ARM64_INS_FCVTAS = 326 , ARM64_INS_FCVTAU = 327 , ARM64_INS_FCVTL = 328 , ARM64_INS_FCVTL2 = 329 , ARM64_INS_FCVTLT = 330 , ARM64_INS_FCVTMS = 331 , ARM64_INS_FCVTMU = 332 , ARM64_INS_FCVTN = 333 , ARM64_INS_FCVTN2 = 334 , ARM64_INS_FCVTNS = 335 , ARM64_INS_FCVTNT = 336 , ARM64_INS_FCVTNU = 337 , ARM64_INS_FCVTPS = 338 , ARM64_INS_FCVTPU = 339 , ARM64_INS_FCVTX = 340 , ARM64_INS_FCVTXN = 341 , ARM64_INS_FCVTXN2 = 342 , ARM64_INS_FCVTXNT = 343 , ARM64_INS_FCVTZS = 344 , ARM64_INS_FCVTZU = 345 , ARM64_INS_FDIV = 346 , ARM64_INS_FDIVR = 347 , ARM64_INS_FDUP = 348 , ARM64_INS_FEXPA = 349 , ARM64_INS_FJCVTZS = 350 , ARM64_INS_FLOGB = 351 , ARM64_INS_FMAD = 352 , ARM64_INS_FMADD = 353 , ARM64_INS_FMAX = 354 , ARM64_INS_FMAXNM = 355 , ARM64_INS_FMAXNMP = 356 , ARM64_INS_FMAXNMV = 357 , ARM64_INS_FMAXP = 358 , ARM64_INS_FMAXV = 359 , ARM64_INS_FMIN = 360 , ARM64_INS_FMINNM = 361 , ARM64_INS_FMINNMP = 362 , ARM64_INS_FMINNMV = 363 , ARM64_INS_FMINP = 364 , ARM64_INS_FMINV = 365 , ARM64_INS_FMLA = 366 , ARM64_INS_FMLAL = 367 , ARM64_INS_FMLAL2 = 368 , ARM64_INS_FMLALB = 369 , ARM64_INS_FMLALT = 370 , ARM64_INS_FMLS = 371 , ARM64_INS_FMLSL = 372 , ARM64_INS_FMLSL2 = 373 , ARM64_INS_FMLSLB = 374 , ARM64_INS_FMLSLT = 375 , ARM64_INS_FMMLA = 376 , ARM64_INS_FMOPA = 377 , ARM64_INS_FMOPS = 378 , ARM64_INS_FMOV = 379 , ARM64_INS_FMSB = 380 , ARM64_INS_FMSUB = 381 , ARM64_INS_FMUL = 382 , ARM64_INS_FMULX = 383 , ARM64_INS_FNEG = 384 , ARM64_INS_FNMAD = 385 , ARM64_INS_FNMADD = 386 , ARM64_INS_FNMLA = 387 , ARM64_INS_FNMLS = 388 , ARM64_INS_FNMSB = 389 , ARM64_INS_FNMSUB = 390 , ARM64_INS_FNMUL = 391 , ARM64_INS_FRECPE = 392 , ARM64_INS_FRECPS = 393 , ARM64_INS_FRECPX = 394 , ARM64_INS_FRINT32X = 395 , ARM64_INS_FRINT32Z = 396 , ARM64_INS_FRINT64X = 397 , ARM64_INS_FRINT64Z = 398 , ARM64_INS_FRINTA = 399 , ARM64_INS_FRINTI = 400 , ARM64_INS_FRINTM = 401 , ARM64_INS_FRINTN = 402 , ARM64_INS_FRINTP = 403 , ARM64_INS_FRINTX = 404 , ARM64_INS_FRINTZ = 405 , ARM64_INS_FRSQRTE = 406 , ARM64_INS_FRSQRTS = 407 , ARM64_INS_FSCALE = 408 , ARM64_INS_FSQRT = 409 , ARM64_INS_FSUB = 410 , ARM64_INS_FSUBR = 411 , ARM64_INS_FTMAD = 412 , ARM64_INS_FTSMUL = 413 , ARM64_INS_FTSSEL = 414 , ARM64_INS_GMI = 415 , ARM64_INS_HINT = 416 , ARM64_INS_HISTCNT = 417 , ARM64_INS_HISTSEG = 418 , ARM64_INS_HLT = 419 , ARM64_INS_HVC = 420 , ARM64_INS_INCB = 421 , ARM64_INS_INCD = 422 , ARM64_INS_INCH = 423 , ARM64_INS_INCP = 424 , ARM64_INS_INCW = 425 , ARM64_INS_INDEX = 426 , ARM64_INS_INS = 427 , ARM64_INS_INSR = 428 , ARM64_INS_IRG = 429 , ARM64_INS_ISB = 430 , ARM64_INS_LASTA = 431 , ARM64_INS_LASTB = 432 , ARM64_INS_LD1 = 433 , ARM64_INS_LD1B = 434 , ARM64_INS_LD1D = 435 , ARM64_INS_LD1H = 436 , ARM64_INS_LD1Q = 437 , ARM64_INS_LD1R = 438 , ARM64_INS_LD1RB = 439 , ARM64_INS_LD1RD = 440 , ARM64_INS_LD1RH = 441 , ARM64_INS_LD1ROB = 442 , ARM64_INS_LD1ROD = 443 , ARM64_INS_LD1ROH = 444 , ARM64_INS_LD1ROW = 445 , ARM64_INS_LD1RQB = 446 , ARM64_INS_LD1RQD = 447 , ARM64_INS_LD1RQH = 448 , ARM64_INS_LD1RQW = 449 , ARM64_INS_LD1RSB = 450 , ARM64_INS_LD1RSH = 451 , ARM64_INS_LD1RSW = 452 , ARM64_INS_LD1RW = 453 , ARM64_INS_LD1SB = 454 , ARM64_INS_LD1SH = 455 , ARM64_INS_LD1SW = 456 , ARM64_INS_LD1W = 457 , ARM64_INS_LD2 = 458 , ARM64_INS_LD2B = 459 , ARM64_INS_LD2D = 460 , ARM64_INS_LD2H = 461 , ARM64_INS_LD2R = 462 , ARM64_INS_LD2W = 463 , ARM64_INS_LD3 = 464 , ARM64_INS_LD3B = 465 , ARM64_INS_LD3D = 466 , ARM64_INS_LD3H = 467 , ARM64_INS_LD3R = 468 , ARM64_INS_LD3W = 469 , ARM64_INS_LD4 = 470 , ARM64_INS_LD4B = 471 , ARM64_INS_LD4D = 472 , ARM64_INS_LD4H = 473 , ARM64_INS_LD4R = 474 , ARM64_INS_LD4W = 475 , ARM64_INS_LD64B = 476 , ARM64_INS_LDADD = 477 , ARM64_INS_LDADDA = 478 , ARM64_INS_LDADDAB = 479 , ARM64_INS_LDADDAH = 480 , ARM64_INS_LDADDAL = 481 , ARM64_INS_LDADDALB = 482 , ARM64_INS_LDADDALH = 483 , ARM64_INS_LDADDB = 484 , ARM64_INS_LDADDH = 485 , ARM64_INS_LDADDL = 486 , ARM64_INS_LDADDLB = 487 , ARM64_INS_LDADDLH = 488 , ARM64_INS_LDAPR = 489 , ARM64_INS_LDAPRB = 490 , ARM64_INS_LDAPRH = 491 , ARM64_INS_LDAPUR = 492 , ARM64_INS_LDAPURB = 493 , ARM64_INS_LDAPURH = 494 , ARM64_INS_LDAPURSB = 495 , ARM64_INS_LDAPURSH = 496 , ARM64_INS_LDAPURSW = 497 , ARM64_INS_LDAR = 498 , ARM64_INS_LDARB = 499 , ARM64_INS_LDARH = 500 , ARM64_INS_LDAXP = 501 , ARM64_INS_LDAXR = 502 , ARM64_INS_LDAXRB = 503 , ARM64_INS_LDAXRH = 504 , ARM64_INS_LDCLR = 505 , ARM64_INS_LDCLRA = 506 , ARM64_INS_LDCLRAB = 507 , ARM64_INS_LDCLRAH = 508 , ARM64_INS_LDCLRAL = 509 , ARM64_INS_LDCLRALB = 510 , ARM64_INS_LDCLRALH = 511 , ARM64_INS_LDCLRB = 512 , ARM64_INS_LDCLRH = 513 , ARM64_INS_LDCLRL = 514 , ARM64_INS_LDCLRLB = 515 , ARM64_INS_LDCLRLH = 516 , ARM64_INS_LDEOR = 517 , ARM64_INS_LDEORA = 518 , ARM64_INS_LDEORAB = 519 , ARM64_INS_LDEORAH = 520 , ARM64_INS_LDEORAL = 521 , ARM64_INS_LDEORALB = 522 , ARM64_INS_LDEORALH = 523 , ARM64_INS_LDEORB = 524 , ARM64_INS_LDEORH = 525 , ARM64_INS_LDEORL = 526 , ARM64_INS_LDEORLB = 527 , ARM64_INS_LDEORLH = 528 , ARM64_INS_LDFF1B = 529 , ARM64_INS_LDFF1D = 530 , ARM64_INS_LDFF1H = 531 , ARM64_INS_LDFF1SB = 532 , ARM64_INS_LDFF1SH = 533 , ARM64_INS_LDFF1SW = 534 , ARM64_INS_LDFF1W = 535 , ARM64_INS_LDG = 536 , ARM64_INS_LDGM = 537 , ARM64_INS_LDLAR = 538 , ARM64_INS_LDLARB = 539 , ARM64_INS_LDLARH = 540 , ARM64_INS_LDNF1B = 541 , ARM64_INS_LDNF1D = 542 , ARM64_INS_LDNF1H = 543 , ARM64_INS_LDNF1SB = 544 , ARM64_INS_LDNF1SH = 545 , ARM64_INS_LDNF1SW = 546 , ARM64_INS_LDNF1W = 547 , ARM64_INS_LDNP = 548 , ARM64_INS_LDNT1B = 549 , ARM64_INS_LDNT1D = 550 , ARM64_INS_LDNT1H = 551 , ARM64_INS_LDNT1SB = 552 , ARM64_INS_LDNT1SH = 553 , ARM64_INS_LDNT1SW = 554 , ARM64_INS_LDNT1W = 555 , ARM64_INS_LDP = 556 , ARM64_INS_LDPSW = 557 , ARM64_INS_LDR = 558 , ARM64_INS_LDRAA = 559 , ARM64_INS_LDRAB = 560 , ARM64_INS_LDRB = 561 , ARM64_INS_LDRH = 562 , ARM64_INS_LDRSB = 563 , ARM64_INS_LDRSH = 564 , ARM64_INS_LDRSW = 565 , ARM64_INS_LDSET = 566 , ARM64_INS_LDSETA = 567 , ARM64_INS_LDSETAB = 568 , ARM64_INS_LDSETAH = 569 , ARM64_INS_LDSETAL = 570 , ARM64_INS_LDSETALB = 571 , ARM64_INS_LDSETALH = 572 , ARM64_INS_LDSETB = 573 , ARM64_INS_LDSETH = 574 , ARM64_INS_LDSETL = 575 , ARM64_INS_LDSETLB = 576 , ARM64_INS_LDSETLH = 577 , ARM64_INS_LDSMAX = 578 , ARM64_INS_LDSMAXA = 579 , ARM64_INS_LDSMAXAB = 580 , ARM64_INS_LDSMAXAH = 581 , ARM64_INS_LDSMAXAL = 582 , ARM64_INS_LDSMAXALB = 583 , ARM64_INS_LDSMAXALH = 584 , ARM64_INS_LDSMAXB = 585 , ARM64_INS_LDSMAXH = 586 , ARM64_INS_LDSMAXL = 587 , ARM64_INS_LDSMAXLB = 588 , ARM64_INS_LDSMAXLH = 589 , ARM64_INS_LDSMIN = 590 , ARM64_INS_LDSMINA = 591 , ARM64_INS_LDSMINAB = 592 , ARM64_INS_LDSMINAH = 593 , ARM64_INS_LDSMINAL = 594 , ARM64_INS_LDSMINALB = 595 , ARM64_INS_LDSMINALH = 596 , ARM64_INS_LDSMINB = 597 , ARM64_INS_LDSMINH = 598 , ARM64_INS_LDSMINL = 599 , ARM64_INS_LDSMINLB = 600 , ARM64_INS_LDSMINLH = 601 , ARM64_INS_LDTR = 602 , ARM64_INS_LDTRB = 603 , ARM64_INS_LDTRH = 604 , ARM64_INS_LDTRSB = 605 , ARM64_INS_LDTRSH = 606 , ARM64_INS_LDTRSW = 607 , ARM64_INS_LDUMAX = 608 , ARM64_INS_LDUMAXA = 609 , ARM64_INS_LDUMAXAB = 610 , ARM64_INS_LDUMAXAH = 611 , ARM64_INS_LDUMAXAL = 612 , ARM64_INS_LDUMAXALB = 613 , ARM64_INS_LDUMAXALH = 614 , ARM64_INS_LDUMAXB = 615 , ARM64_INS_LDUMAXH = 616 , ARM64_INS_LDUMAXL = 617 , ARM64_INS_LDUMAXLB = 618 , ARM64_INS_LDUMAXLH = 619 , ARM64_INS_LDUMIN = 620 , ARM64_INS_LDUMINA = 621 , ARM64_INS_LDUMINAB = 622 , ARM64_INS_LDUMINAH = 623 , ARM64_INS_LDUMINAL = 624 , ARM64_INS_LDUMINALB = 625 , ARM64_INS_LDUMINALH = 626 , ARM64_INS_LDUMINB = 627 , ARM64_INS_LDUMINH = 628 , ARM64_INS_LDUMINL = 629 , ARM64_INS_LDUMINLB = 630 , ARM64_INS_LDUMINLH = 631 , ARM64_INS_LDUR = 632 , ARM64_INS_LDURB = 633 , ARM64_INS_LDURH = 634 , ARM64_INS_LDURSB = 635 , ARM64_INS_LDURSH = 636 , ARM64_INS_LDURSW = 637 , ARM64_INS_LDXP = 638 , ARM64_INS_LDXR = 639 , ARM64_INS_LDXRB = 640 , ARM64_INS_LDXRH = 641 , ARM64_INS_LSL = 642 , ARM64_INS_LSLR = 643 , ARM64_INS_LSLV = 644 , ARM64_INS_LSR = 645 , ARM64_INS_LSRR = 646 , ARM64_INS_LSRV = 647 , ARM64_INS_MAD = 648 , ARM64_INS_MADD = 649 , ARM64_INS_MATCH = 650 , ARM64_INS_MLA = 651 , ARM64_INS_MLS = 652 , ARM64_INS_MNEG = 653 , ARM64_INS_MOV = 654 , ARM64_INS_MOVA = 655 , ARM64_INS_MOVI = 656 , ARM64_INS_MOVK = 657 , ARM64_INS_MOVN = 658 , ARM64_INS_MOVPRFX = 659 , ARM64_INS_MOVS = 660 , ARM64_INS_MOVZ = 661 , ARM64_INS_MRS = 662 , ARM64_INS_MSB = 663 , ARM64_INS_MSR = 664 , ARM64_INS_MSUB = 665 , ARM64_INS_MUL = 666 , ARM64_INS_MVN = 667 , ARM64_INS_MVNI = 668 , ARM64_INS_NAND = 669 , ARM64_INS_NANDS = 670 , ARM64_INS_NBSL = 671 , ARM64_INS_NEG = 672 , ARM64_INS_NEGS = 673 , ARM64_INS_NGC = 674 , ARM64_INS_NGCS = 675 , ARM64_INS_NMATCH = 676 , ARM64_INS_NOP = 677 , ARM64_INS_NOR = 678 , ARM64_INS_NORS = 679 , ARM64_INS_NOT = 680 , ARM64_INS_NOTS = 681 , ARM64_INS_ORN = 682 , ARM64_INS_ORNS = 683 , ARM64_INS_ORR = 684 , ARM64_INS_ORRS = 685 , ARM64_INS_ORV = 686 , ARM64_INS_PACDA = 687 , ARM64_INS_PACDB = 688 , ARM64_INS_PACDZA = 689 , ARM64_INS_PACDZB = 690 , ARM64_INS_PACGA = 691 , ARM64_INS_PACIA = 692 , ARM64_INS_PACIA1716 = 693 , ARM64_INS_PACIASP = 694 , ARM64_INS_PACIAZ = 695 , ARM64_INS_PACIB = 696 , ARM64_INS_PACIB1716 = 697 , ARM64_INS_PACIBSP = 698 , ARM64_INS_PACIBZ = 699 , ARM64_INS_PACIZA = 700 , ARM64_INS_PACIZB = 701 , ARM64_INS_PFALSE = 702 , ARM64_INS_PFIRST = 703 , ARM64_INS_PMUL = 704 , ARM64_INS_PMULL = 705 , ARM64_INS_PMULL2 = 706 , ARM64_INS_PMULLB = 707 , ARM64_INS_PMULLT = 708 , ARM64_INS_PNEXT = 709 , ARM64_INS_PRFB = 710 , ARM64_INS_PRFD = 711 , ARM64_INS_PRFH = 712 , ARM64_INS_PRFM = 713 , ARM64_INS_PRFUM = 714 , ARM64_INS_PRFW = 715 , ARM64_INS_PSB = 716 , ARM64_INS_PSEL = 717 , ARM64_INS_PSSBB = 718 , ARM64_INS_PTEST = 719 , ARM64_INS_PTRUE = 720 , ARM64_INS_PTRUES = 721 , ARM64_INS_PUNPKHI = 722 , ARM64_INS_PUNPKLO = 723 , ARM64_INS_RADDHN = 724 , ARM64_INS_RADDHN2 = 725 , ARM64_INS_RADDHNB = 726 , ARM64_INS_RADDHNT = 727 , ARM64_INS_RAX1 = 728 , ARM64_INS_RBIT = 729 , ARM64_INS_RDFFR = 730 , ARM64_INS_RDFFRS = 731 , ARM64_INS_RDVL = 732 , ARM64_INS_RET = 733 , ARM64_INS_RETAA = 734 , ARM64_INS_RETAB = 735 , ARM64_INS_REV = 736 , ARM64_INS_REV16 = 737 , ARM64_INS_REV32 = 738 , ARM64_INS_REV64 = 739 , ARM64_INS_REVB = 740 , ARM64_INS_REVD = 741 , ARM64_INS_REVH = 742 , ARM64_INS_REVW = 743 , ARM64_INS_RMIF = 744 , ARM64_INS_ROR = 745 , ARM64_INS_RORV = 746 , ARM64_INS_RSHRN = 747 , ARM64_INS_RSHRN2 = 748 , ARM64_INS_RSHRNB = 749 , ARM64_INS_RSHRNT = 750 , ARM64_INS_RSUBHN = 751 , ARM64_INS_RSUBHN2 = 752 , ARM64_INS_RSUBHNB = 753 , ARM64_INS_RSUBHNT = 754 , ARM64_INS_SABA = 755 , ARM64_INS_SABAL = 756 , ARM64_INS_SABAL2 = 757 , ARM64_INS_SABALB = 758 , ARM64_INS_SABALT = 759 , ARM64_INS_SABD = 760 , ARM64_INS_SABDL = 761 , ARM64_INS_SABDL2 = 762 , ARM64_INS_SABDLB = 763 , ARM64_INS_SABDLT = 764 , ARM64_INS_SADALP = 765 , ARM64_INS_SADDL = 766 , ARM64_INS_SADDL2 = 767 , ARM64_INS_SADDLB = 768 , ARM64_INS_SADDLBT = 769 , ARM64_INS_SADDLP = 770 , ARM64_INS_SADDLT = 771 , ARM64_INS_SADDLV = 772 , ARM64_INS_SADDV = 773 , ARM64_INS_SADDW = 774 , ARM64_INS_SADDW2 = 775 , ARM64_INS_SADDWB = 776 , ARM64_INS_SADDWT = 777 , ARM64_INS_SB = 778 , ARM64_INS_SBC = 779 , ARM64_INS_SBCLB = 780 , ARM64_INS_SBCLT = 781 , ARM64_INS_SBCS = 782 , ARM64_INS_SBFM = 783 , ARM64_INS_SCLAMP = 784 , ARM64_INS_SCVTF = 785 , ARM64_INS_SDIV = 786 , ARM64_INS_SDIVR = 787 , ARM64_INS_SDOT = 788 , ARM64_INS_SEL = 789 , ARM64_INS_SETE = 790 , ARM64_INS_SETEN = 791 , ARM64_INS_SETET = 792 , ARM64_INS_SETETN = 793 , ARM64_INS_SETF16 = 794 , ARM64_INS_SETF8 = 795 , ARM64_INS_SETFFR = 796 , ARM64_INS_SETGE = 797 , ARM64_INS_SETGEN = 798 , ARM64_INS_SETGET = 799 , ARM64_INS_SETGETN = 800 , ARM64_INS_SETGM = 801 , ARM64_INS_SETGMN = 802 , ARM64_INS_SETGMT = 803 , ARM64_INS_SETGMTN = 804 , ARM64_INS_SETGP = 805 , ARM64_INS_SETGPN = 806 , ARM64_INS_SETGPT = 807 , ARM64_INS_SETGPTN = 808 , ARM64_INS_SETM = 809 , ARM64_INS_SETMN = 810 , ARM64_INS_SETMT = 811 , ARM64_INS_SETMTN = 812 , ARM64_INS_SETP = 813 , ARM64_INS_SETPN = 814 , ARM64_INS_SETPT = 815 , ARM64_INS_SETPTN = 816 , ARM64_INS_SEV = 817 , ARM64_INS_SEVL = 818 , ARM64_INS_SHA1C = 819 , ARM64_INS_SHA1H = 820 , ARM64_INS_SHA1M = 821 , ARM64_INS_SHA1P = 822 , ARM64_INS_SHA1SU0 = 823 , ARM64_INS_SHA1SU1 = 824 , ARM64_INS_SHA256H = 825 , ARM64_INS_SHA256H2 = 826 , ARM64_INS_SHA256SU0 = 827 , ARM64_INS_SHA256SU1 = 828 , ARM64_INS_SHA512H = 829 , ARM64_INS_SHA512H2 = 830 , ARM64_INS_SHA512SU0 = 831 , ARM64_INS_SHA512SU1 = 832 , ARM64_INS_SHADD = 833 , ARM64_INS_SHL = 834 , ARM64_INS_SHLL = 835 , ARM64_INS_SHLL2 = 836 , ARM64_INS_SHRN = 837 , ARM64_INS_SHRN2 = 838 , ARM64_INS_SHRNB = 839 , ARM64_INS_SHRNT = 840 , ARM64_INS_SHSUB = 841 , ARM64_INS_SHSUBR = 842 , ARM64_INS_SLI = 843 , ARM64_INS_SM3PARTW1 = 844 , ARM64_INS_SM3PARTW2 = 845 , ARM64_INS_SM3SS1 = 846 , ARM64_INS_SM3TT1A = 847 , ARM64_INS_SM3TT1B = 848 , ARM64_INS_SM3TT2A = 849 , ARM64_INS_SM3TT2B = 850 , ARM64_INS_SM4E = 851 , ARM64_INS_SM4EKEY = 852 , ARM64_INS_SMADDL = 853 , ARM64_INS_SMAX = 854 , ARM64_INS_SMAXP = 855 , ARM64_INS_SMAXV = 856 , ARM64_INS_SMC = 857 , ARM64_INS_SMIN = 858 , ARM64_INS_SMINP = 859 , ARM64_INS_SMINV = 860 , ARM64_INS_SMLAL = 861 , ARM64_INS_SMLAL2 = 862 , ARM64_INS_SMLALB = 863 , ARM64_INS_SMLALT = 864 , ARM64_INS_SMLSL = 865 , ARM64_INS_SMLSL2 = 866 , ARM64_INS_SMLSLB = 867 , ARM64_INS_SMLSLT = 868 , ARM64_INS_SMMLA = 869 , ARM64_INS_SMNEGL = 870 , ARM64_INS_SMOPA = 871 , ARM64_INS_SMOPS = 872 , ARM64_INS_SMOV = 873 , ARM64_INS_SMSTART = 874 , ARM64_INS_SMSTOP = 875 , ARM64_INS_SMSUBL = 876 , ARM64_INS_SMULH = 877 , ARM64_INS_SMULL = 878 , ARM64_INS_SMULL2 = 879 , ARM64_INS_SMULLB = 880 , ARM64_INS_SMULLT = 881 , ARM64_INS_SPLICE = 882 , ARM64_INS_SQABS = 883 , ARM64_INS_SQADD = 884 , ARM64_INS_SQCADD = 885 , ARM64_INS_SQDECB = 886 , ARM64_INS_SQDECD = 887 , ARM64_INS_SQDECH = 888 , ARM64_INS_SQDECP = 889 , ARM64_INS_SQDECW = 890 , ARM64_INS_SQDMLAL = 891 , ARM64_INS_SQDMLAL2 = 892 , ARM64_INS_SQDMLALB = 893 , ARM64_INS_SQDMLALBT = 894 , ARM64_INS_SQDMLALT = 895 , ARM64_INS_SQDMLSL = 896 , ARM64_INS_SQDMLSL2 = 897 , ARM64_INS_SQDMLSLB = 898 , ARM64_INS_SQDMLSLBT = 899 , ARM64_INS_SQDMLSLT = 900 , ARM64_INS_SQDMULH = 901 , ARM64_INS_SQDMULL = 902 , ARM64_INS_SQDMULL2 = 903 , ARM64_INS_SQDMULLB = 904 , ARM64_INS_SQDMULLT = 905 , ARM64_INS_SQINCB = 906 , ARM64_INS_SQINCD = 907 , ARM64_INS_SQINCH = 908 , ARM64_INS_SQINCP = 909 , ARM64_INS_SQINCW = 910 , ARM64_INS_SQNEG = 911 , ARM64_INS_SQRDCMLAH = 912 , ARM64_INS_SQRDMLAH = 913 , ARM64_INS_SQRDMLSH = 914 , ARM64_INS_SQRDMULH = 915 , ARM64_INS_SQRSHL = 916 , ARM64_INS_SQRSHLR = 917 , ARM64_INS_SQRSHRN = 918 , ARM64_INS_SQRSHRN2 = 919 , ARM64_INS_SQRSHRNB = 920 , ARM64_INS_SQRSHRNT = 921 , ARM64_INS_SQRSHRUN = 922 , ARM64_INS_SQRSHRUN2 = 923 , ARM64_INS_SQRSHRUNB = 924 , ARM64_INS_SQRSHRUNT = 925 , ARM64_INS_SQSHL = 926 , ARM64_INS_SQSHLR = 927 , ARM64_INS_SQSHLU = 928 , ARM64_INS_SQSHRN = 929 , ARM64_INS_SQSHRN2 = 930 , ARM64_INS_SQSHRNB = 931 , ARM64_INS_SQSHRNT = 932 , ARM64_INS_SQSHRUN = 933 , ARM64_INS_SQSHRUN2 = 934 , ARM64_INS_SQSHRUNB = 935 , ARM64_INS_SQSHRUNT = 936 , ARM64_INS_SQSUB = 937 , ARM64_INS_SQSUBR = 938 , ARM64_INS_SQXTN = 939 , ARM64_INS_SQXTN2 = 940 , ARM64_INS_SQXTNB = 941 , ARM64_INS_SQXTNT = 942 , ARM64_INS_SQXTUN = 943 , ARM64_INS_SQXTUN2 = 944 , ARM64_INS_SQXTUNB = 945 , ARM64_INS_SQXTUNT = 946 , ARM64_INS_SRHADD = 947 , ARM64_INS_SRI = 948 , ARM64_INS_SRSHL = 949 , ARM64_INS_SRSHLR = 950 , ARM64_INS_SRSHR = 951 , ARM64_INS_SRSRA = 952 , ARM64_INS_SSBB = 953 , ARM64_INS_SSHL = 954 , ARM64_INS_SSHLL = 955 , ARM64_INS_SSHLL2 = 956 , ARM64_INS_SSHLLB = 957 , ARM64_INS_SSHLLT = 958 , ARM64_INS_SSHR = 959 , ARM64_INS_SSRA = 960 , ARM64_INS_SSUBL = 961 , ARM64_INS_SSUBL2 = 962 , ARM64_INS_SSUBLB = 963 , ARM64_INS_SSUBLBT = 964 , ARM64_INS_SSUBLT = 965 , ARM64_INS_SSUBLTB = 966 , ARM64_INS_SSUBW = 967 , ARM64_INS_SSUBW2 = 968 , ARM64_INS_SSUBWB = 969 , ARM64_INS_SSUBWT = 970 , ARM64_INS_ST1 = 971 , ARM64_INS_ST1B = 972 , ARM64_INS_ST1D = 973 , ARM64_INS_ST1H = 974 , ARM64_INS_ST1Q = 975 , ARM64_INS_ST1W = 976 , ARM64_INS_ST2 = 977 , ARM64_INS_ST2B = 978 , ARM64_INS_ST2D = 979 , ARM64_INS_ST2G = 980 , ARM64_INS_ST2H = 981 , ARM64_INS_ST2W = 982 , ARM64_INS_ST3 = 983 , ARM64_INS_ST3B = 984 , ARM64_INS_ST3D = 985 , ARM64_INS_ST3H = 986 , ARM64_INS_ST3W = 987 , ARM64_INS_ST4 = 988 , ARM64_INS_ST4B = 989 , ARM64_INS_ST4D = 990 , ARM64_INS_ST4H = 991 , ARM64_INS_ST4W = 992 , ARM64_INS_ST64B = 993 , ARM64_INS_ST64BV = 994 , ARM64_INS_ST64BV0 = 995 , ARM64_INS_STADD = 996 , ARM64_INS_STADDB = 997 , ARM64_INS_STADDH = 998 , ARM64_INS_STADDL = 999 , ARM64_INS_STADDLB = 1000 , ARM64_INS_STADDLH = 1001 , ARM64_INS_STCLR = 1002 , ARM64_INS_STCLRB = 1003 , ARM64_INS_STCLRH = 1004 , ARM64_INS_STCLRL = 1005 , ARM64_INS_STCLRLB = 1006 , ARM64_INS_STCLRLH = 1007 , ARM64_INS_STEOR = 1008 , ARM64_INS_STEORB = 1009 , ARM64_INS_STEORH = 1010 , ARM64_INS_STEORL = 1011 , ARM64_INS_STEORLB = 1012 , ARM64_INS_STEORLH = 1013 , ARM64_INS_STG = 1014 , ARM64_INS_STGM = 1015 , ARM64_INS_STGP = 1016 , ARM64_INS_STLLR = 1017 , ARM64_INS_STLLRB = 1018 , ARM64_INS_STLLRH = 1019 , ARM64_INS_STLR = 1020 , ARM64_INS_STLRB = 1021 , ARM64_INS_STLRH = 1022 , ARM64_INS_STLUR = 1023 , ARM64_INS_STLURB = 1024 , ARM64_INS_STLURH = 1025 , ARM64_INS_STLXP = 1026 , ARM64_INS_STLXR = 1027 , ARM64_INS_STLXRB = 1028 , ARM64_INS_STLXRH = 1029 , ARM64_INS_STNP = 1030 , ARM64_INS_STNT1B = 1031 , ARM64_INS_STNT1D = 1032 , ARM64_INS_STNT1H = 1033 , ARM64_INS_STNT1W = 1034 , ARM64_INS_STP = 1035 , ARM64_INS_STR = 1036 , ARM64_INS_STRB = 1037 , ARM64_INS_STRH = 1038 , ARM64_INS_STSET = 1039 , ARM64_INS_STSETB = 1040 , ARM64_INS_STSETH = 1041 , ARM64_INS_STSETL = 1042 , ARM64_INS_STSETLB = 1043 , ARM64_INS_STSETLH = 1044 , ARM64_INS_STSMAX = 1045 , ARM64_INS_STSMAXB = 1046 , ARM64_INS_STSMAXH = 1047 , ARM64_INS_STSMAXL = 1048 , ARM64_INS_STSMAXLB = 1049 , ARM64_INS_STSMAXLH = 1050 , ARM64_INS_STSMIN = 1051 , ARM64_INS_STSMINB = 1052 , ARM64_INS_STSMINH = 1053 , ARM64_INS_STSMINL = 1054 , ARM64_INS_STSMINLB = 1055 , ARM64_INS_STSMINLH = 1056 , ARM64_INS_STTR = 1057 , ARM64_INS_STTRB = 1058 , ARM64_INS_STTRH = 1059 , ARM64_INS_STUMAX = 1060 , ARM64_INS_STUMAXB = 1061 , ARM64_INS_STUMAXH = 1062 , ARM64_INS_STUMAXL = 1063 , ARM64_INS_STUMAXLB = 1064 , ARM64_INS_STUMAXLH = 1065 , ARM64_INS_STUMIN = 1066 , ARM64_INS_STUMINB = 1067 , ARM64_INS_STUMINH = 1068 , ARM64_INS_STUMINL = 1069 , ARM64_INS_STUMINLB = 1070 , ARM64_INS_STUMINLH = 1071 , ARM64_INS_STUR = 1072 , ARM64_INS_STURB = 1073 , ARM64_INS_STURH = 1074 , ARM64_INS_STXP = 1075 , ARM64_INS_STXR = 1076 , ARM64_INS_STXRB = 1077 , ARM64_INS_STXRH = 1078 , ARM64_INS_STZ2G = 1079 , ARM64_INS_STZG = 1080 , ARM64_INS_STZGM = 1081 , ARM64_INS_SUB = 1082 , ARM64_INS_SUBG = 1083 , ARM64_INS_SUBHN = 1084 , ARM64_INS_SUBHN2 = 1085 , ARM64_INS_SUBHNB = 1086 , ARM64_INS_SUBHNT = 1087 , ARM64_INS_SUBP = 1088 , ARM64_INS_SUBPS = 1089 , ARM64_INS_SUBR = 1090 , ARM64_INS_SUBS = 1091 , ARM64_INS_SUDOT = 1092 , ARM64_INS_SUMOPA = 1093 , ARM64_INS_SUMOPS = 1094 , ARM64_INS_SUNPKHI = 1095 , ARM64_INS_SUNPKLO = 1096 , ARM64_INS_SUQADD = 1097 , ARM64_INS_SVC = 1098 , ARM64_INS_SWP = 1099 , ARM64_INS_SWPA = 1100 , ARM64_INS_SWPAB = 1101 , ARM64_INS_SWPAH = 1102 , ARM64_INS_SWPAL = 1103 , ARM64_INS_SWPALB = 1104 , ARM64_INS_SWPALH = 1105 , ARM64_INS_SWPB = 1106 , ARM64_INS_SWPH = 1107 , ARM64_INS_SWPL = 1108 , ARM64_INS_SWPLB = 1109 , ARM64_INS_SWPLH = 1110 , ARM64_INS_SXTB = 1111 , ARM64_INS_SXTH = 1112 , ARM64_INS_SXTL = 1113 , ARM64_INS_SXTL2 = 1114 , ARM64_INS_SXTW = 1115 , ARM64_INS_SYS = 1116 , ARM64_INS_SYSL = 1117 , ARM64_INS_TBL = 1118 , ARM64_INS_TBNZ = 1119 , ARM64_INS_TBX = 1120 , ARM64_INS_TBZ = 1121 , ARM64_INS_TCANCEL = 1122 , ARM64_INS_TCOMMIT = 1123 , ARM64_INS_TRN1 = 1124 , ARM64_INS_TRN2 = 1125 , ARM64_INS_TSB = 1126 , ARM64_INS_TST = 1127 , ARM64_INS_TSTART = 1128 , ARM64_INS_TTEST = 1129 , ARM64_INS_UABA = 1130 , ARM64_INS_UABAL = 1131 , ARM64_INS_UABAL2 = 1132 , ARM64_INS_UABALB = 1133 , ARM64_INS_UABALT = 1134 , ARM64_INS_UABD = 1135 , ARM64_INS_UABDL = 1136 , ARM64_INS_UABDL2 = 1137 , ARM64_INS_UABDLB = 1138 , ARM64_INS_UABDLT = 1139 , ARM64_INS_UADALP = 1140 , ARM64_INS_UADDL = 1141 , ARM64_INS_UADDL2 = 1142 , ARM64_INS_UADDLB = 1143 , ARM64_INS_UADDLP = 1144 , ARM64_INS_UADDLT = 1145 , ARM64_INS_UADDLV = 1146 , ARM64_INS_UADDV = 1147 , ARM64_INS_UADDW = 1148 , ARM64_INS_UADDW2 = 1149 , ARM64_INS_UADDWB = 1150 , ARM64_INS_UADDWT = 1151 , ARM64_INS_UBFM = 1152 , ARM64_INS_UCLAMP = 1153 , ARM64_INS_UCVTF = 1154 , ARM64_INS_UDF = 1155 , ARM64_INS_UDIV = 1156 , ARM64_INS_UDIVR = 1157 , ARM64_INS_UDOT = 1158 , ARM64_INS_UHADD = 1159 , ARM64_INS_UHSUB = 1160 , ARM64_INS_UHSUBR = 1161 , ARM64_INS_UMADDL = 1162 , ARM64_INS_UMAX = 1163 , ARM64_INS_UMAXP = 1164 , ARM64_INS_UMAXV = 1165 , ARM64_INS_UMIN = 1166 , ARM64_INS_UMINP = 1167 , ARM64_INS_UMINV = 1168 , ARM64_INS_UMLAL = 1169 , ARM64_INS_UMLAL2 = 1170 , ARM64_INS_UMLALB = 1171 , ARM64_INS_UMLALT = 1172 , ARM64_INS_UMLSL = 1173 , ARM64_INS_UMLSL2 = 1174 , ARM64_INS_UMLSLB = 1175 , ARM64_INS_UMLSLT = 1176 , ARM64_INS_UMMLA = 1177 , ARM64_INS_UMNEGL = 1178 , ARM64_INS_UMOPA = 1179 , ARM64_INS_UMOPS = 1180 , ARM64_INS_UMOV = 1181 , ARM64_INS_UMSUBL = 1182 , ARM64_INS_UMULH = 1183 , ARM64_INS_UMULL = 1184 , ARM64_INS_UMULL2 = 1185 , ARM64_INS_UMULLB = 1186 , ARM64_INS_UMULLT = 1187 , ARM64_INS_UQADD = 1188 , ARM64_INS_UQDECB = 1189 , ARM64_INS_UQDECD = 1190 , ARM64_INS_UQDECH = 1191 , ARM64_INS_UQDECP = 1192 , ARM64_INS_UQDECW = 1193 , ARM64_INS_UQINCB = 1194 , ARM64_INS_UQINCD = 1195 , ARM64_INS_UQINCH = 1196 , ARM64_INS_UQINCP = 1197 , ARM64_INS_UQINCW = 1198 , ARM64_INS_UQRSHL = 1199 , ARM64_INS_UQRSHLR = 1200 , ARM64_INS_UQRSHRN = 1201 , ARM64_INS_UQRSHRN2 = 1202 , ARM64_INS_UQRSHRNB = 1203 , ARM64_INS_UQRSHRNT = 1204 , ARM64_INS_UQSHL = 1205 , ARM64_INS_UQSHLR = 1206 , ARM64_INS_UQSHRN = 1207 , ARM64_INS_UQSHRN2 = 1208 , ARM64_INS_UQSHRNB = 1209 , ARM64_INS_UQSHRNT = 1210 , ARM64_INS_UQSUB = 1211 , ARM64_INS_UQSUBR = 1212 , ARM64_INS_UQXTN = 1213 , ARM64_INS_UQXTN2 = 1214 , ARM64_INS_UQXTNB = 1215 , ARM64_INS_UQXTNT = 1216 , ARM64_INS_URECPE = 1217 , ARM64_INS_URHADD = 1218 , ARM64_INS_URSHL = 1219 , ARM64_INS_URSHLR = 1220 , ARM64_INS_URSHR = 1221 , ARM64_INS_URSQRTE = 1222 , ARM64_INS_URSRA = 1223 , ARM64_INS_USDOT = 1224 , ARM64_INS_USHL = 1225 , ARM64_INS_USHLL = 1226 , ARM64_INS_USHLL2 = 1227 , ARM64_INS_USHLLB = 1228 , ARM64_INS_USHLLT = 1229 , ARM64_INS_USHR = 1230 , ARM64_INS_USMMLA = 1231 , ARM64_INS_USMOPA = 1232 , ARM64_INS_USMOPS = 1233 , ARM64_INS_USQADD = 1234 , ARM64_INS_USRA = 1235 , ARM64_INS_USUBL = 1236 , ARM64_INS_USUBL2 = 1237 , ARM64_INS_USUBLB = 1238 , ARM64_INS_USUBLT = 1239 , ARM64_INS_USUBW = 1240 , ARM64_INS_USUBW2 = 1241 , ARM64_INS_USUBWB = 1242 , ARM64_INS_USUBWT = 1243 , ARM64_INS_UUNPKHI = 1244 , ARM64_INS_UUNPKLO = 1245 , ARM64_INS_UXTB = 1246 , ARM64_INS_UXTH = 1247 , ARM64_INS_UXTL = 1248 , ARM64_INS_UXTL2 = 1249 , ARM64_INS_UXTW = 1250 , ARM64_INS_UZP1 = 1251 , ARM64_INS_UZP2 = 1252 , ARM64_INS_WFE = 1253 , ARM64_INS_WFET = 1254 , ARM64_INS_WFI = 1255 , ARM64_INS_WFIT = 1256 , ARM64_INS_WHILEGE = 1257 , ARM64_INS_WHILEGT = 1258 , ARM64_INS_WHILEHI = 1259 , ARM64_INS_WHILEHS = 1260 , ARM64_INS_WHILELE = 1261 , ARM64_INS_WHILELO = 1262 , ARM64_INS_WHILELS = 1263 , ARM64_INS_WHILELT = 1264 , ARM64_INS_WHILERW = 1265 , ARM64_INS_WHILEWR = 1266 , ARM64_INS_WRFFR = 1267 , ARM64_INS_XAFLAG = 1268 , ARM64_INS_XAR = 1269 , ARM64_INS_XPACD = 1270 , ARM64_INS_XPACI = 1271 , ARM64_INS_XPACLRI = 1272 , ARM64_INS_XTN = 1273 , ARM64_INS_XTN2 = 1274 , ARM64_INS_YIELD = 1275 , ARM64_INS_ZERO = 1276 , ARM64_INS_ZIP1 = 1277 , ARM64_INS_ZIP2 = 1278 , ARM64_INS_SBFIZ = 1279 , ARM64_INS_UBFIZ = 1280 , ARM64_INS_SBFX = 1281 , ARM64_INS_UBFX = 1282 , ARM64_INS_BFI = 1283 , ARM64_INS_BFXIL = 1284 , ARM64_INS_IC = 1285 , ARM64_INS_DC = 1286 , ARM64_INS_AT = 1287 , ARM64_INS_TLBI = 1288 , ARM64_INS_ENDING = 1289 , } # [repr (u32)] # [doc = " Group of ARM64 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM64_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM64_GRP_JUMP = 1 , ARM64_GRP_CALL = 2 , ARM64_GRP_RET = 3 , ARM64_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM64_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM64_GRP_BRANCH_RELATIVE = 7 , ARM64_GRP_PAC = 8 , ARM64_GRP_CRYPTO = 128 , ARM64_GRP_FPARMV8 = 129 , ARM64_GRP_NEON = 130 , ARM64_GRP_CRC = 131 , ARM64_GRP_AES = 132 , ARM64_GRP_DOTPROD = 133 , ARM64_GRP_FULLFP16 = 134 , ARM64_GRP_LSE = 135 , ARM64_GRP_RCPC = 136 , ARM64_GRP_RDM = 137 , ARM64_GRP_SHA2 = 138 , ARM64_GRP_SHA3 = 139 , ARM64_GRP_SM4 = 140 , ARM64_GRP_SVE = 141 , ARM64_GRP_SVE2 = 142 , ARM64_GRP_SVE2AES = 143 , ARM64_GRP_SVE2BitPerm = 144 , ARM64_GRP_SVE2SHA3 = 145 , ARM64_GRP_SVE2SM4 = 146 , ARM64_GRP_SME = 147 , ARM64_GRP_SMEF64 = 148 , ARM64_GRP_SMEI64 = 149 , ARM64_GRP_MatMulFP32 = 150 , ARM64_GRP_MatMulFP64 = 151 , ARM64_GRP_MatMulInt8 = 152 , ARM64_GRP_V8_1A = 153 , ARM64_GRP_V8_3A = 154 , ARM64_GRP_V8_4A = 155 , ARM64_GRP_ENDING = 156 , } # [repr (u32)] # [doc = " M68K registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_reg { M68K_REG_INVALID = 0 , M68K_REG_D0 = 1 , M68K_REG_D1 = 2 , M68K_REG_D2 = 3 , M68K_REG_D3 = 4 , M68K_REG_D4 = 5 , M68K_REG_D5 = 6 , M68K_REG_D6 = 7 , M68K_REG_D7 = 8 , M68K_REG_A0 = 9 , M68K_REG_A1 = 10 , M68K_REG_A2 = 11 , M68K_REG_A3 = 12 , M68K_REG_A4 = 13 , M68K_REG_A5 = 14 , M68K_REG_A6 = 15 , M68K_REG_A7 = 16 , M68K_REG_FP0 = 17 , M68K_REG_FP1 = 18 , M68K_REG_FP2 = 19 , M68K_REG_FP3 = 20 , M68K_REG_FP4 = 21 , M68K_REG_FP5 = 22 , M68K_REG_FP6 = 23 , M68K_REG_FP7 = 24 , M68K_REG_PC = 25 , M68K_REG_SR = 26 , M68K_REG_CCR = 27 , M68K_REG_SFC = 28 , M68K_REG_DFC = 29 , M68K_REG_USP = 30 , M68K_REG_VBR = 31 , M68K_REG_CACR = 32 , M68K_REG_CAAR = 33 , M68K_REG_MSP = 34 , M68K_REG_ISP = 35 , M68K_REG_TC = 36 , M68K_REG_ITT0 = 37 , M68K_REG_ITT1 = 38 , M68K_REG_DTT0 = 39 , M68K_REG_DTT1 = 40 , M68K_REG_MMUSR = 41 , M68K_REG_URP = 42 , M68K_REG_SRP = 43 , M68K_REG_FPCR = 44 , M68K_REG_FPSR = 45 , M68K_REG_FPIAR = 46 , M68K_REG_ENDING = 47 , } # [repr (u32)] # [doc = " M68K Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_address_mode { # [doc = "< No address mode."] M68K_AM_NONE = 0 , # [doc = "< Register Direct - Data"] M68K_AM_REG_DIRECT_DATA = 1 , # [doc = "< Register Direct - Address"] M68K_AM_REG_DIRECT_ADDR = 2 , # [doc = "< Register Indirect - Address"] M68K_AM_REGI_ADDR = 3 , # [doc = "< Register Indirect - Address with Postincrement"] M68K_AM_REGI_ADDR_POST_INC = 4 , # [doc = "< Register Indirect - Address with Predecrement"] M68K_AM_REGI_ADDR_PRE_DEC = 5 , # [doc = "< Register Indirect - Address with Displacement"] M68K_AM_REGI_ADDR_DISP = 6 , # [doc = "< Address Register Indirect With Index- 8-bit displacement"] M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 , # [doc = "< Address Register Indirect With Index- Base displacement"] M68K_AM_AREGI_INDEX_BASE_DISP = 8 , # [doc = "< Memory indirect - Postindex"] M68K_AM_MEMI_POST_INDEX = 9 , # [doc = "< Memory indirect - Preindex"] M68K_AM_MEMI_PRE_INDEX = 10 , # [doc = "< Program Counter Indirect - with Displacement"] M68K_AM_PCI_DISP = 11 , # [doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"] M68K_AM_PCI_INDEX_8_BIT_DISP = 12 , # [doc = "< Program Counter Indirect with Index - with Base Displacement"] M68K_AM_PCI_INDEX_BASE_DISP = 13 , # [doc = "< Program Counter Memory Indirect - Postindexed"] M68K_AM_PC_MEMI_POST_INDEX = 14 , # [doc = "< Program Counter Memory Indirect - Preindexed"] M68K_AM_PC_MEMI_PRE_INDEX = 15 , # [doc = "< Absolute Data Addressing  - Short"] M68K_AM_ABSOLUTE_DATA_SHORT = 16 , # [doc = "< Absolute Data Addressing  - Long"] M68K_AM_ABSOLUTE_DATA_LONG = 17 , # [doc = "< Immediate value"] M68K_AM_IMMEDIATE = 18 , # [doc = "< Address as displacement from (PC+2) used by branches"] M68K_AM_BRANCH_DISPLACEMENT = 19 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] M68K_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] M68K_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] M68K_OP_MEM = 3 , # [doc = "< single precision Floating-Point operand"] M68K_OP_FP_SINGLE = 4 , # [doc = "< double precision Floating-Point operand"] M68K_OP_FP_DOUBLE = 5 , # [doc = "< Register bits move"] M68K_OP_REG_BITS = 6 , # [doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"] M68K_OP_REG_PAIR = 7 , # [doc = "< Branch displacement"] M68K_OP_BR_DISP = 8 , } # [doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_mem { # [doc = "< base register (or M68K_REG_INVALID if irrelevant)"] pub base_reg : m68k_reg , # [doc = "< index register (or M68K_REG_INVALID if irrelevant)"] pub index_reg : m68k_reg , # [doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"] pub in_base_reg : m68k_reg , # [doc = "< indirect displacement"] pub in_disp : u32 , # [doc = "< other displacement"] pub out_disp : u32 , # [doc = "< displacement value"] pub disp : i16 , # [doc = "< scale for index register"] pub scale : u8 , # [doc = "< set to true if the two values below should be used"] pub bitfield : u8 , # [doc = "< used for bf* instructions"] pub width : u8 , # [doc = "< used for bf* instructions"] pub offset : u8 , # [doc = "< 0 = w, 1 = l"] pub index_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_mem"] [:: std :: mem :: size_of :: < m68k_op_mem > () - 28usize] ; ["Alignment of m68k_op_mem"] [:: std :: mem :: align_of :: < m68k_op_mem > () - 4usize] ; ["Offset of field: m68k_op_mem::base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , base_reg) - 0usize] ; ["Offset of field: m68k_op_mem::index_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_reg) - 4usize] ; ["Offset of field: m68k_op_mem::in_base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_base_reg) - 8usize] ; ["Offset of field: m68k_op_mem::in_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_disp) - 12usize] ; ["Offset of field: m68k_op_mem::out_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , out_disp) - 16usize] ; ["Offset of field: m68k_op_mem::disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , disp) - 20usize] ; ["Offset of field: m68k_op_mem::scale"] [:: std :: mem :: offset_of ! (m68k_op_mem , scale) - 22usize] ; ["Offset of field: m68k_op_mem::bitfield"] [:: std :: mem :: offset_of ! (m68k_op_mem , bitfield) - 23usize] ; ["Offset of field: m68k_op_mem::width"] [:: std :: mem :: offset_of ! (m68k_op_mem , width) - 24usize] ; ["Offset of field: m68k_op_mem::offset"] [:: std :: mem :: offset_of ! (m68k_op_mem , offset) - 25usize] ; ["Offset of field: m68k_op_mem::index_size"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_size) - 26usize] ; } ; # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_br_disp_size { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_BR_DISP_SIZE_INVALID = 0 , # [doc = "< signed 8-bit displacement"] M68K_OP_BR_DISP_SIZE_BYTE = 1 , # [doc = "< signed 16-bit displacement"] M68K_OP_BR_DISP_SIZE_WORD = 2 , # [doc = "< signed 32-bit displacement"] M68K_OP_BR_DISP_SIZE_LONG = 4 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_br_disp { # [doc = "< displacement value"] pub disp : i32 , # [doc = "< Size from m68k_op_br_disp_size type above"] pub disp_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_br_disp"] [:: std :: mem :: size_of :: < m68k_op_br_disp > () - 8usize] ; ["Alignment of m68k_op_br_disp"] [:: std :: mem :: align_of :: < m68k_op_br_disp > () - 4usize] ; ["Offset of field: m68k_op_br_disp::disp"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp) - 0usize] ; ["Offset of field: m68k_op_br_disp::disp_size"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp_size) - 4usize] ; } ; # [doc = " Register pair in one operand."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_m68k_op_reg_pair { pub reg_0 : m68k_reg , pub reg_1 : m68k_reg , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op_reg_pair"] [:: std :: mem :: size_of :: < cs_m68k_op_reg_pair > () - 8usize] ; ["Alignment of cs_m68k_op_reg_pair"] [:: std :: mem :: align_of :: < cs_m68k_op_reg_pair > () - 4usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_0"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_0) - 0usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_1"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_1) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k_op { pub __bindgen_anon_1 : cs_m68k_op__bindgen_ty_1 , # [doc = "< data when operand is targeting memory"] pub mem : m68k_op_mem , # [doc = "< data when operand is a branch displacement"] pub br_disp : m68k_op_br_disp , # [doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"] pub register_bits : u32 , pub type_ : m68k_op_type , # [doc = "< M68K addressing mode for this op"] pub address_mode : m68k_address_mode , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m68k_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< double imm"] pub dimm : f64 , # [doc = "< float imm"] pub simm : f32 , # [doc = "< register value for REG operand"] pub reg : m68k_reg , # [doc = "< register pair in one operand"] pub reg_pair : cs_m68k_op_reg_pair , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::dimm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , dimm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::simm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , simm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg_pair"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg_pair) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op"] [:: std :: mem :: size_of :: < cs_m68k_op > () - 56usize] ; ["Alignment of cs_m68k_op"] [:: std :: mem :: align_of :: < cs_m68k_op > () - 8usize] ; ["Offset of field: cs_m68k_op::mem"] [:: std :: mem :: offset_of ! (cs_m68k_op , mem) - 8usize] ; ["Offset of field: cs_m68k_op::br_disp"] [:: std :: mem :: offset_of ! (cs_m68k_op , br_disp) - 36usize] ; ["Offset of field: cs_m68k_op::register_bits"] [:: std :: mem :: offset_of ! (cs_m68k_op , register_bits) - 44usize] ; ["Offset of field: cs_m68k_op::type_"] [:: std :: mem :: offset_of ! (cs_m68k_op , type_) - 48usize] ; ["Offset of field: cs_m68k_op::address_mode"] [:: std :: mem :: offset_of ! (cs_m68k_op , address_mode) - 52usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode) } } # [repr (u32)] # [doc = " Operation size of the CPU instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_cpu_size { # [doc = "< unsized or unspecified"] M68K_CPU_SIZE_NONE = 0 , # [doc = "< 1 byte in size"] M68K_CPU_SIZE_BYTE = 1 , # [doc = "< 2 bytes in size"] M68K_CPU_SIZE_WORD = 2 , # [doc = "< 4 bytes in size"] M68K_CPU_SIZE_LONG = 4 , } # [repr (u32)] # [doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_fpu_size { # [doc = "< unsized like fsave/frestore"] M68K_FPU_SIZE_NONE = 0 , # [doc = "< 4 byte in size (single float)"] M68K_FPU_SIZE_SINGLE = 4 , # [doc = "< 8 byte in size (double)"] M68K_FPU_SIZE_DOUBLE = 8 , # [doc = "< 12 byte in size (extended real format)"] M68K_FPU_SIZE_EXTENDED = 12 , } # [repr (u32)] # [doc = " Type of size that is being used for the current instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0 , M68K_SIZE_TYPE_CPU = 1 , M68K_SIZE_TYPE_FPU = 2 , } # [doc = " Operation size of the current instruction (NOT the actually size of instruction)"] # [repr (C)] # [derive (Copy , Clone)] pub struct m68k_op_size { pub type_ : m68k_size_type , pub __bindgen_anon_1 : m68k_op_size__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union m68k_op_size__bindgen_ty_1 { pub cpu_size : m68k_cpu_size , pub fpu_size : m68k_fpu_size , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: size_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Alignment of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: align_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::cpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , cpu_size) - 0usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::fpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , fpu_size) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size"] [:: std :: mem :: size_of :: < m68k_op_size > () - 8usize] ; ["Alignment of m68k_op_size"] [:: std :: mem :: align_of :: < m68k_op_size > () - 4usize] ; ["Offset of field: m68k_op_size::type_"] [:: std :: mem :: offset_of ! (m68k_op_size , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The M68K instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k { # [doc = "< operands for this instruction."] pub operands : [cs_m68k_op ; 4usize] , # [doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"] pub op_size : m68k_op_size , # [doc = "< number of operands for the instruction"] pub op_count : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k"] [:: std :: mem :: size_of :: < cs_m68k > () - 240usize] ; ["Alignment of cs_m68k"] [:: std :: mem :: align_of :: < cs_m68k > () - 8usize] ; ["Offset of field: cs_m68k::operands"] [:: std :: mem :: offset_of ! (cs_m68k , operands) - 0usize] ; ["Offset of field: cs_m68k::op_size"] [:: std :: mem :: offset_of ! (cs_m68k , op_size) - 224usize] ; ["Offset of field: cs_m68k::op_count"] [:: std :: mem :: offset_of ! (cs_m68k , op_count) - 232usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}" , self . operands , self . op_size , self . op_count) } } # [repr (u32)] # [doc = " M68K instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_insn { M68K_INS_INVALID = 0 , M68K_INS_ABCD = 1 , M68K_INS_ADD = 2 , M68K_INS_ADDA = 3 , M68K_INS_ADDI = 4 , M68K_INS_ADDQ = 5 , M68K_INS_ADDX = 6 , M68K_INS_AND = 7 , M68K_INS_ANDI = 8 , M68K_INS_ASL = 9 , M68K_INS_ASR = 10 , M68K_INS_BHS = 11 , M68K_INS_BLO = 12 , M68K_INS_BHI = 13 , M68K_INS_BLS = 14 , M68K_INS_BCC = 15 , M68K_INS_BCS = 16 , M68K_INS_BNE = 17 , M68K_INS_BEQ = 18 , M68K_INS_BVC = 19 , M68K_INS_BVS = 20 , M68K_INS_BPL = 21 , M68K_INS_BMI = 22 , M68K_INS_BGE = 23 , M68K_INS_BLT = 24 , M68K_INS_BGT = 25 , M68K_INS_BLE = 26 , M68K_INS_BRA = 27 , M68K_INS_BSR = 28 , M68K_INS_BCHG = 29 , M68K_INS_BCLR = 30 , M68K_INS_BSET = 31 , M68K_INS_BTST = 32 , M68K_INS_BFCHG = 33 , M68K_INS_BFCLR = 34 , M68K_INS_BFEXTS = 35 , M68K_INS_BFEXTU = 36 , M68K_INS_BFFFO = 37 , M68K_INS_BFINS = 38 , M68K_INS_BFSET = 39 , M68K_INS_BFTST = 40 , M68K_INS_BKPT = 41 , M68K_INS_CALLM = 42 , M68K_INS_CAS = 43 , M68K_INS_CAS2 = 44 , M68K_INS_CHK = 45 , M68K_INS_CHK2 = 46 , M68K_INS_CLR = 47 , M68K_INS_CMP = 48 , M68K_INS_CMPA = 49 , M68K_INS_CMPI = 50 , M68K_INS_CMPM = 51 , M68K_INS_CMP2 = 52 , M68K_INS_CINVL = 53 , M68K_INS_CINVP = 54 , M68K_INS_CINVA = 55 , M68K_INS_CPUSHL = 56 , M68K_INS_CPUSHP = 57 , M68K_INS_CPUSHA = 58 , M68K_INS_DBT = 59 , M68K_INS_DBF = 60 , M68K_INS_DBHI = 61 , M68K_INS_DBLS = 62 , M68K_INS_DBCC = 63 , M68K_INS_DBCS = 64 , M68K_INS_DBNE = 65 , M68K_INS_DBEQ = 66 , M68K_INS_DBVC = 67 , M68K_INS_DBVS = 68 , M68K_INS_DBPL = 69 , M68K_INS_DBMI = 70 , M68K_INS_DBGE = 71 , M68K_INS_DBLT = 72 , M68K_INS_DBGT = 73 , M68K_INS_DBLE = 74 , M68K_INS_DBRA = 75 , M68K_INS_DIVS = 76 , M68K_INS_DIVSL = 77 , M68K_INS_DIVU = 78 , M68K_INS_DIVUL = 79 , M68K_INS_EOR = 80 , M68K_INS_EORI = 81 , M68K_INS_EXG = 82 , M68K_INS_EXT = 83 , M68K_INS_EXTB = 84 , M68K_INS_FABS = 85 , M68K_INS_FSABS = 86 , M68K_INS_FDABS = 87 , M68K_INS_FACOS = 88 , M68K_INS_FADD = 89 , M68K_INS_FSADD = 90 , M68K_INS_FDADD = 91 , M68K_INS_FASIN = 92 , M68K_INS_FATAN = 93 , M68K_INS_FATANH = 94 , M68K_INS_FBF = 95 , M68K_INS_FBEQ = 96 , M68K_INS_FBOGT = 97 , M68K_INS_FBOGE = 98 , M68K_INS_FBOLT = 99 , M68K_INS_FBOLE = 100 , M68K_INS_FBOGL = 101 , M68K_INS_FBOR = 102 , M68K_INS_FBUN = 103 , M68K_INS_FBUEQ = 104 , M68K_INS_FBUGT = 105 , M68K_INS_FBUGE = 106 , M68K_INS_FBULT = 107 , M68K_INS_FBULE = 108 , M68K_INS_FBNE = 109 , M68K_INS_FBT = 110 , M68K_INS_FBSF = 111 , M68K_INS_FBSEQ = 112 , M68K_INS_FBGT = 113 , M68K_INS_FBGE = 114 , M68K_INS_FBLT = 115 , M68K_INS_FBLE = 116 , M68K_INS_FBGL = 117 , M68K_INS_FBGLE = 118 , M68K_INS_FBNGLE = 119 , M68K_INS_FBNGL = 120 , M68K_INS_FBNLE = 121 , M68K_INS_FBNLT = 122 , M68K_INS_FBNGE = 123 , M68K_INS_FBNGT = 124 , M68K_INS_FBSNE = 125 , M68K_INS_FBST = 126 , M68K_INS_FCMP = 127 , M68K_INS_FCOS = 128 , M68K_INS_FCOSH = 129 , M68K_INS_FDBF = 130 , M68K_INS_FDBEQ = 131 , M68K_INS_FDBOGT = 132 , M68K_INS_FDBOGE = 133 , M68K_INS_FDBOLT = 134 , M68K_INS_FDBOLE = 135 , M68K_INS_FDBOGL = 136 , M68K_INS_FDBOR = 137 , M68K_INS_FDBUN = 138 , M68K_INS_FDBUEQ = 139 , M68K_INS_FDBUGT = 140 , M68K_INS_FDBUGE = 141 , M68K_INS_FDBULT = 142 , M68K_INS_FDBULE = 143 , M68K_INS_FDBNE = 144 , M68K_INS_FDBT = 145 , M68K_INS_FDBSF = 146 , M68K_INS_FDBSEQ = 147 , M68K_INS_FDBGT = 148 , M68K_INS_FDBGE = 149 , M68K_INS_FDBLT = 150 , M68K_INS_FDBLE = 151 , M68K_INS_FDBGL = 152 , M68K_INS_FDBGLE = 153 , M68K_INS_FDBNGLE = 154 , M68K_INS_FDBNGL = 155 , M68K_INS_FDBNLE = 156 , M68K_INS_FDBNLT = 157 , M68K_INS_FDBNGE = 158 , M68K_INS_FDBNGT = 159 , M68K_INS_FDBSNE = 160 , M68K_INS_FDBST = 161 , M68K_INS_FDIV = 162 , M68K_INS_FSDIV = 163 , M68K_INS_FDDIV = 164 , M68K_INS_FETOX = 165 , M68K_INS_FETOXM1 = 166 , M68K_INS_FGETEXP = 167 , M68K_INS_FGETMAN = 168 , M68K_INS_FINT = 169 , M68K_INS_FINTRZ = 170 , M68K_INS_FLOG10 = 171 , M68K_INS_FLOG2 = 172 , M68K_INS_FLOGN = 173 , M68K_INS_FLOGNP1 = 174 , M68K_INS_FMOD = 175 , M68K_INS_FMOVE = 176 , M68K_INS_FSMOVE = 177 , M68K_INS_FDMOVE = 178 , M68K_INS_FMOVECR = 179 , M68K_INS_FMOVEM = 180 , M68K_INS_FMUL = 181 , M68K_INS_FSMUL = 182 , M68K_INS_FDMUL = 183 , M68K_INS_FNEG = 184 , M68K_INS_FSNEG = 185 , M68K_INS_FDNEG = 186 , M68K_INS_FNOP = 187 , M68K_INS_FREM = 188 , M68K_INS_FRESTORE = 189 , M68K_INS_FSAVE = 190 , M68K_INS_FSCALE = 191 , M68K_INS_FSGLDIV = 192 , M68K_INS_FSGLMUL = 193 , M68K_INS_FSIN = 194 , M68K_INS_FSINCOS = 195 , M68K_INS_FSINH = 196 , M68K_INS_FSQRT = 197 , M68K_INS_FSSQRT = 198 , M68K_INS_FDSQRT = 199 , M68K_INS_FSF = 200 , M68K_INS_FSBEQ = 201 , M68K_INS_FSOGT = 202 , M68K_INS_FSOGE = 203 , M68K_INS_FSOLT = 204 , M68K_INS_FSOLE = 205 , M68K_INS_FSOGL = 206 , M68K_INS_FSOR = 207 , M68K_INS_FSUN = 208 , M68K_INS_FSUEQ = 209 , M68K_INS_FSUGT = 210 , M68K_INS_FSUGE = 211 , M68K_INS_FSULT = 212 , M68K_INS_FSULE = 213 , M68K_INS_FSNE = 214 , M68K_INS_FST = 215 , M68K_INS_FSSF = 216 , M68K_INS_FSSEQ = 217 , M68K_INS_FSGT = 218 , M68K_INS_FSGE = 219 , M68K_INS_FSLT = 220 , M68K_INS_FSLE = 221 , M68K_INS_FSGL = 222 , M68K_INS_FSGLE = 223 , M68K_INS_FSNGLE = 224 , M68K_INS_FSNGL = 225 , M68K_INS_FSNLE = 226 , M68K_INS_FSNLT = 227 , M68K_INS_FSNGE = 228 , M68K_INS_FSNGT = 229 , M68K_INS_FSSNE = 230 , M68K_INS_FSST = 231 , M68K_INS_FSUB = 232 , M68K_INS_FSSUB = 233 , M68K_INS_FDSUB = 234 , M68K_INS_FTAN = 235 , M68K_INS_FTANH = 236 , M68K_INS_FTENTOX = 237 , M68K_INS_FTRAPF = 238 , M68K_INS_FTRAPEQ = 239 , M68K_INS_FTRAPOGT = 240 , M68K_INS_FTRAPOGE = 241 , M68K_INS_FTRAPOLT = 242 , M68K_INS_FTRAPOLE = 243 , M68K_INS_FTRAPOGL = 244 , M68K_INS_FTRAPOR = 245 , M68K_INS_FTRAPUN = 246 , M68K_INS_FTRAPUEQ = 247 , M68K_INS_FTRAPUGT = 248 , M68K_INS_FTRAPUGE = 249 , M68K_INS_FTRAPULT = 250 , M68K_INS_FTRAPULE = 251 , M68K_INS_FTRAPNE = 252 , M68K_INS_FTRAPT = 253 , M68K_INS_FTRAPSF = 254 , M68K_INS_FTRAPSEQ = 255 , M68K_INS_FTRAPGT = 256 , M68K_INS_FTRAPGE = 257 , M68K_INS_FTRAPLT = 258 , M68K_INS_FTRAPLE = 259 , M68K_INS_FTRAPGL = 260 , M68K_INS_FTRAPGLE = 261 , M68K_INS_FTRAPNGLE = 262 , M68K_INS_FTRAPNGL = 263 , M68K_INS_FTRAPNLE = 264 , M68K_INS_FTRAPNLT = 265 , M68K_INS_FTRAPNGE = 266 , M68K_INS_FTRAPNGT = 267 , M68K_INS_FTRAPSNE = 268 , M68K_INS_FTRAPST = 269 , M68K_INS_FTST = 270 , M68K_INS_FTWOTOX = 271 , M68K_INS_HALT = 272 , M68K_INS_ILLEGAL = 273 , M68K_INS_JMP = 274 , M68K_INS_JSR = 275 , M68K_INS_LEA = 276 , M68K_INS_LINK = 277 , M68K_INS_LPSTOP = 278 , M68K_INS_LSL = 279 , M68K_INS_LSR = 280 , M68K_INS_MOVE = 281 , M68K_INS_MOVEA = 282 , M68K_INS_MOVEC = 283 , M68K_INS_MOVEM = 284 , M68K_INS_MOVEP = 285 , M68K_INS_MOVEQ = 286 , M68K_INS_MOVES = 287 , M68K_INS_MOVE16 = 288 , M68K_INS_MULS = 289 , M68K_INS_MULU = 290 , M68K_INS_NBCD = 291 , M68K_INS_NEG = 292 , M68K_INS_NEGX = 293 , M68K_INS_NOP = 294 , M68K_INS_NOT = 295 , M68K_INS_OR = 296 , M68K_INS_ORI = 297 , M68K_INS_PACK = 298 , M68K_INS_PEA = 299 , M68K_INS_PFLUSH = 300 , M68K_INS_PFLUSHA = 301 , M68K_INS_PFLUSHAN = 302 , M68K_INS_PFLUSHN = 303 , M68K_INS_PLOADR = 304 , M68K_INS_PLOADW = 305 , M68K_INS_PLPAR = 306 , M68K_INS_PLPAW = 307 , M68K_INS_PMOVE = 308 , M68K_INS_PMOVEFD = 309 , M68K_INS_PTESTR = 310 , M68K_INS_PTESTW = 311 , M68K_INS_PULSE = 312 , M68K_INS_REMS = 313 , M68K_INS_REMU = 314 , M68K_INS_RESET = 315 , M68K_INS_ROL = 316 , M68K_INS_ROR = 317 , M68K_INS_ROXL = 318 , M68K_INS_ROXR = 319 , M68K_INS_RTD = 320 , M68K_INS_RTE = 321 , M68K_INS_RTM = 322 , M68K_INS_RTR = 323 , M68K_INS_RTS = 324 , M68K_INS_SBCD = 325 , M68K_INS_ST = 326 , M68K_INS_SF = 327 , M68K_INS_SHI = 328 , M68K_INS_SLS = 329 , M68K_INS_SCC = 330 , M68K_INS_SHS = 331 , M68K_INS_SCS = 332 , M68K_INS_SLO = 333 , M68K_INS_SNE = 334 , M68K_INS_SEQ = 335 , M68K_INS_SVC = 336 , M68K_INS_SVS = 337 , M68K_INS_SPL = 338 , M68K_INS_SMI = 339 , M68K_INS_SGE = 340 , M68K_INS_SLT = 341 , M68K_INS_SGT = 342 , M68K_INS_SLE = 343 , M68K_INS_STOP = 344 , M68K_INS_SUB = 345 , M68K_INS_SUBA = 346 , M68K_INS_SUBI = 347 , M68K_INS_SUBQ = 348 , M68K_INS_SUBX = 349 , M68K_INS_SWAP = 350 , M68K_INS_TAS = 351 , M68K_INS_TRAP = 352 , M68K_INS_TRAPV = 353 , M68K_INS_TRAPT = 354 , M68K_INS_TRAPF = 355 , M68K_INS_TRAPHI = 356 , M68K_INS_TRAPLS = 357 , M68K_INS_TRAPCC = 358 , M68K_INS_TRAPHS = 359 , M68K_INS_TRAPCS = 360 , M68K_INS_TRAPLO = 361 , M68K_INS_TRAPNE = 362 , M68K_INS_TRAPEQ = 363 , M68K_INS_TRAPVC = 364 , M68K_INS_TRAPVS = 365 , M68K_INS_TRAPPL = 366 , M68K_INS_TRAPMI = 367 , M68K_INS_TRAPGE = 368 , M68K_INS_TRAPLT = 369 , M68K_INS_TRAPGT = 370 , M68K_INS_TRAPLE = 371 , M68K_INS_TST = 372 , M68K_INS_UNLK = 373 , M68K_INS_UNPK = 374 , M68K_INS_ENDING = 375 , } # [repr (u32)] # [doc = " Group of M68K instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_group_type { # [doc = "< CS_GRUP_INVALID"] M68K_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M68K_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] M68K_GRP_RET = 3 , # [doc = "< = CS_GRP_IRET"] M68K_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M68K_GRP_BRANCH_RELATIVE = 7 , M68K_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MIPS_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MIPS_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MIPS_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MIPS_OP_MEM = 3 , } impl mips_reg { pub const MIPS_REG_ZERO : mips_reg = mips_reg :: MIPS_REG_0 ; } impl mips_reg { pub const MIPS_REG_AT : mips_reg = mips_reg :: MIPS_REG_1 ; } impl mips_reg { pub const MIPS_REG_V0 : mips_reg = mips_reg :: MIPS_REG_2 ; } impl mips_reg { pub const MIPS_REG_V1 : mips_reg = mips_reg :: MIPS_REG_3 ; } impl mips_reg { pub const MIPS_REG_A0 : mips_reg = mips_reg :: MIPS_REG_4 ; } impl mips_reg { pub const MIPS_REG_A1 : mips_reg = mips_reg :: MIPS_REG_5 ; } impl mips_reg { pub const MIPS_REG_A2 : mips_reg = mips_reg :: MIPS_REG_6 ; } impl mips_reg { pub const MIPS_REG_A3 : mips_reg = mips_reg :: MIPS_REG_7 ; } impl mips_reg { pub const MIPS_REG_T0 : mips_reg = mips_reg :: MIPS_REG_8 ; } impl mips_reg { pub const MIPS_REG_T1 : mips_reg = mips_reg :: MIPS_REG_9 ; } impl mips_reg { pub const MIPS_REG_T2 : mips_reg = mips_reg :: MIPS_REG_10 ; } impl mips_reg { pub const MIPS_REG_T3 : mips_reg = mips_reg :: MIPS_REG_11 ; } impl mips_reg { pub const MIPS_REG_T4 : mips_reg = mips_reg :: MIPS_REG_12 ; } impl mips_reg { pub const MIPS_REG_T5 : mips_reg = mips_reg :: MIPS_REG_13 ; } impl mips_reg { pub const MIPS_REG_T6 : mips_reg = mips_reg :: MIPS_REG_14 ; } impl mips_reg { pub const MIPS_REG_T7 : mips_reg = mips_reg :: MIPS_REG_15 ; } impl mips_reg { pub const MIPS_REG_S0 : mips_reg = mips_reg :: MIPS_REG_16 ; } impl mips_reg { pub const MIPS_REG_S1 : mips_reg = mips_reg :: MIPS_REG_17 ; } impl mips_reg { pub const MIPS_REG_S2 : mips_reg = mips_reg :: MIPS_REG_18 ; } impl mips_reg { pub const MIPS_REG_S3 : mips_reg = mips_reg :: MIPS_REG_19 ; } impl mips_reg { pub const MIPS_REG_S4 : mips_reg = mips_reg :: MIPS_REG_20 ; } impl mips_reg { pub const MIPS_REG_S5 : mips_reg = mips_reg :: MIPS_REG_21 ; } impl mips_reg { pub const MIPS_REG_S6 : mips_reg = mips_reg :: MIPS_REG_22 ; } impl mips_reg { pub const MIPS_REG_S7 : mips_reg = mips_reg :: MIPS_REG_23 ; } impl mips_reg { pub const MIPS_REG_T8 : mips_reg = mips_reg :: MIPS_REG_24 ; } impl mips_reg { pub const MIPS_REG_T9 : mips_reg = mips_reg :: MIPS_REG_25 ; } impl mips_reg { pub const MIPS_REG_K0 : mips_reg = mips_reg :: MIPS_REG_26 ; } impl mips_reg { pub const MIPS_REG_K1 : mips_reg = mips_reg :: MIPS_REG_27 ; } impl mips_reg { pub const MIPS_REG_GP : mips_reg = mips_reg :: MIPS_REG_28 ; } impl mips_reg { pub const MIPS_REG_SP : mips_reg = mips_reg :: MIPS_REG_29 ; } impl mips_reg { pub const MIPS_REG_FP : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_S8 : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_RA : mips_reg = mips_reg :: MIPS_REG_31 ; } impl mips_reg { pub const MIPS_REG_HI0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_HI1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_HI2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_HI3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } impl mips_reg { pub const MIPS_REG_LO0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_LO1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_LO2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_LO3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } # [repr (u32)] # [doc = " MIPS registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_reg { MIPS_REG_INVALID = 0 , MIPS_REG_PC = 1 , MIPS_REG_0 = 2 , MIPS_REG_1 = 3 , MIPS_REG_2 = 4 , MIPS_REG_3 = 5 , MIPS_REG_4 = 6 , MIPS_REG_5 = 7 , MIPS_REG_6 = 8 , MIPS_REG_7 = 9 , MIPS_REG_8 = 10 , MIPS_REG_9 = 11 , MIPS_REG_10 = 12 , MIPS_REG_11 = 13 , MIPS_REG_12 = 14 , MIPS_REG_13 = 15 , MIPS_REG_14 = 16 , MIPS_REG_15 = 17 , MIPS_REG_16 = 18 , MIPS_REG_17 = 19 , MIPS_REG_18 = 20 , MIPS_REG_19 = 21 , MIPS_REG_20 = 22 , MIPS_REG_21 = 23 , MIPS_REG_22 = 24 , MIPS_REG_23 = 25 , MIPS_REG_24 = 26 , MIPS_REG_25 = 27 , MIPS_REG_26 = 28 , MIPS_REG_27 = 29 , MIPS_REG_28 = 30 , MIPS_REG_29 = 31 , MIPS_REG_30 = 32 , MIPS_REG_31 = 33 , MIPS_REG_DSPCCOND = 34 , MIPS_REG_DSPCARRY = 35 , MIPS_REG_DSPEFI = 36 , MIPS_REG_DSPOUTFLAG = 37 , MIPS_REG_DSPOUTFLAG16_19 = 38 , MIPS_REG_DSPOUTFLAG20 = 39 , MIPS_REG_DSPOUTFLAG21 = 40 , MIPS_REG_DSPOUTFLAG22 = 41 , MIPS_REG_DSPOUTFLAG23 = 42 , MIPS_REG_DSPPOS = 43 , MIPS_REG_DSPSCOUNT = 44 , MIPS_REG_AC0 = 45 , MIPS_REG_AC1 = 46 , MIPS_REG_AC2 = 47 , MIPS_REG_AC3 = 48 , MIPS_REG_CC0 = 49 , MIPS_REG_CC1 = 50 , MIPS_REG_CC2 = 51 , MIPS_REG_CC3 = 52 , MIPS_REG_CC4 = 53 , MIPS_REG_CC5 = 54 , MIPS_REG_CC6 = 55 , MIPS_REG_CC7 = 56 , MIPS_REG_F0 = 57 , MIPS_REG_F1 = 58 , MIPS_REG_F2 = 59 , MIPS_REG_F3 = 60 , MIPS_REG_F4 = 61 , MIPS_REG_F5 = 62 , MIPS_REG_F6 = 63 , MIPS_REG_F7 = 64 , MIPS_REG_F8 = 65 , MIPS_REG_F9 = 66 , MIPS_REG_F10 = 67 , MIPS_REG_F11 = 68 , MIPS_REG_F12 = 69 , MIPS_REG_F13 = 70 , MIPS_REG_F14 = 71 , MIPS_REG_F15 = 72 , MIPS_REG_F16 = 73 , MIPS_REG_F17 = 74 , MIPS_REG_F18 = 75 , MIPS_REG_F19 = 76 , MIPS_REG_F20 = 77 , MIPS_REG_F21 = 78 , MIPS_REG_F22 = 79 , MIPS_REG_F23 = 80 , MIPS_REG_F24 = 81 , MIPS_REG_F25 = 82 , MIPS_REG_F26 = 83 , MIPS_REG_F27 = 84 , MIPS_REG_F28 = 85 , MIPS_REG_F29 = 86 , MIPS_REG_F30 = 87 , MIPS_REG_F31 = 88 , MIPS_REG_FCC0 = 89 , MIPS_REG_FCC1 = 90 , MIPS_REG_FCC2 = 91 , MIPS_REG_FCC3 = 92 , MIPS_REG_FCC4 = 93 , MIPS_REG_FCC5 = 94 , MIPS_REG_FCC6 = 95 , MIPS_REG_FCC7 = 96 , MIPS_REG_W0 = 97 , MIPS_REG_W1 = 98 , MIPS_REG_W2 = 99 , MIPS_REG_W3 = 100 , MIPS_REG_W4 = 101 , MIPS_REG_W5 = 102 , MIPS_REG_W6 = 103 , MIPS_REG_W7 = 104 , MIPS_REG_W8 = 105 , MIPS_REG_W9 = 106 , MIPS_REG_W10 = 107 , MIPS_REG_W11 = 108 , MIPS_REG_W12 = 109 , MIPS_REG_W13 = 110 , MIPS_REG_W14 = 111 , MIPS_REG_W15 = 112 , MIPS_REG_W16 = 113 , MIPS_REG_W17 = 114 , MIPS_REG_W18 = 115 , MIPS_REG_W19 = 116 , MIPS_REG_W20 = 117 , MIPS_REG_W21 = 118 , MIPS_REG_W22 = 119 , MIPS_REG_W23 = 120 , MIPS_REG_W24 = 121 , MIPS_REG_W25 = 122 , MIPS_REG_W26 = 123 , MIPS_REG_W27 = 124 , MIPS_REG_W28 = 125 , MIPS_REG_W29 = 126 , MIPS_REG_W30 = 127 , MIPS_REG_W31 = 128 , MIPS_REG_HI = 129 , MIPS_REG_LO = 130 , MIPS_REG_P0 = 131 , MIPS_REG_P1 = 132 , MIPS_REG_P2 = 133 , MIPS_REG_MPL0 = 134 , MIPS_REG_MPL1 = 135 , MIPS_REG_MPL2 = 136 , MIPS_REG_ENDING = 137 , } # [doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct mips_op_mem { # [doc = "< base register"] pub base : mips_reg , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of mips_op_mem"] [:: std :: mem :: size_of :: < mips_op_mem > () - 16usize] ; ["Alignment of mips_op_mem"] [:: std :: mem :: align_of :: < mips_op_mem > () - 8usize] ; ["Offset of field: mips_op_mem::base"] [:: std :: mem :: offset_of ! (mips_op_mem , base) - 0usize] ; ["Offset of field: mips_op_mem::disp"] [:: std :: mem :: offset_of ! (mips_op_mem , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips_op { # [doc = "< operand type"] pub type_ : mips_op_type , pub __bindgen_anon_1 : cs_mips_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mips_op__bindgen_ty_1 { # [doc = "< register id for REG operand"] pub reg : mips_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : mips_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mips_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mips_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op"] [:: std :: mem :: size_of :: < cs_mips_op > () - 24usize] ; ["Alignment of cs_mips_op"] [:: std :: mem :: align_of :: < cs_mips_op > () - 8usize] ; ["Offset of field: cs_mips_op::type_"] [:: std :: mem :: offset_of ! (cs_mips_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mips_op ; 10usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips"] [:: std :: mem :: size_of :: < cs_mips > () - 248usize] ; ["Alignment of cs_mips"] [:: std :: mem :: align_of :: < cs_mips > () - 8usize] ; ["Offset of field: cs_mips::op_count"] [:: std :: mem :: offset_of ! (cs_mips , op_count) - 0usize] ; ["Offset of field: cs_mips::operands"] [:: std :: mem :: offset_of ! (cs_mips , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mips { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " MIPS instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn { MIPS_INS_INVALID = 0 , MIPS_INS_ABSQ_S = 1 , MIPS_INS_ADD = 2 , MIPS_INS_ADDIUPC = 3 , MIPS_INS_ADDIUR1SP = 4 , MIPS_INS_ADDIUR2 = 5 , MIPS_INS_ADDIUS5 = 6 , MIPS_INS_ADDIUSP = 7 , MIPS_INS_ADDQH = 8 , MIPS_INS_ADDQH_R = 9 , MIPS_INS_ADDQ = 10 , MIPS_INS_ADDQ_S = 11 , MIPS_INS_ADDSC = 12 , MIPS_INS_ADDS_A = 13 , MIPS_INS_ADDS_S = 14 , MIPS_INS_ADDS_U = 15 , MIPS_INS_ADDU16 = 16 , MIPS_INS_ADDUH = 17 , MIPS_INS_ADDUH_R = 18 , MIPS_INS_ADDU = 19 , MIPS_INS_ADDU_S = 20 , MIPS_INS_ADDVI = 21 , MIPS_INS_ADDV = 22 , MIPS_INS_ADDWC = 23 , MIPS_INS_ADD_A = 24 , MIPS_INS_ADDI = 25 , MIPS_INS_ADDIU = 26 , MIPS_INS_ALIGN = 27 , MIPS_INS_ALUIPC = 28 , MIPS_INS_AND = 29 , MIPS_INS_AND16 = 30 , MIPS_INS_ANDI16 = 31 , MIPS_INS_ANDI = 32 , MIPS_INS_APPEND = 33 , MIPS_INS_ASUB_S = 34 , MIPS_INS_ASUB_U = 35 , MIPS_INS_AUI = 36 , MIPS_INS_AUIPC = 37 , MIPS_INS_AVER_S = 38 , MIPS_INS_AVER_U = 39 , MIPS_INS_AVE_S = 40 , MIPS_INS_AVE_U = 41 , MIPS_INS_B16 = 42 , MIPS_INS_BADDU = 43 , MIPS_INS_BAL = 44 , MIPS_INS_BALC = 45 , MIPS_INS_BALIGN = 46 , MIPS_INS_BBIT0 = 47 , MIPS_INS_BBIT032 = 48 , MIPS_INS_BBIT1 = 49 , MIPS_INS_BBIT132 = 50 , MIPS_INS_BC = 51 , MIPS_INS_BC0F = 52 , MIPS_INS_BC0FL = 53 , MIPS_INS_BC0T = 54 , MIPS_INS_BC0TL = 55 , MIPS_INS_BC1EQZ = 56 , MIPS_INS_BC1F = 57 , MIPS_INS_BC1FL = 58 , MIPS_INS_BC1NEZ = 59 , MIPS_INS_BC1T = 60 , MIPS_INS_BC1TL = 61 , MIPS_INS_BC2EQZ = 62 , MIPS_INS_BC2F = 63 , MIPS_INS_BC2FL = 64 , MIPS_INS_BC2NEZ = 65 , MIPS_INS_BC2T = 66 , MIPS_INS_BC2TL = 67 , MIPS_INS_BC3F = 68 , MIPS_INS_BC3FL = 69 , MIPS_INS_BC3T = 70 , MIPS_INS_BC3TL = 71 , MIPS_INS_BCLRI = 72 , MIPS_INS_BCLR = 73 , MIPS_INS_BEQ = 74 , MIPS_INS_BEQC = 75 , MIPS_INS_BEQL = 76 , MIPS_INS_BEQZ16 = 77 , MIPS_INS_BEQZALC = 78 , MIPS_INS_BEQZC = 79 , MIPS_INS_BGEC = 80 , MIPS_INS_BGEUC = 81 , MIPS_INS_BGEZ = 82 , MIPS_INS_BGEZAL = 83 , MIPS_INS_BGEZALC = 84 , MIPS_INS_BGEZALL = 85 , MIPS_INS_BGEZALS = 86 , MIPS_INS_BGEZC = 87 , MIPS_INS_BGEZL = 88 , MIPS_INS_BGTZ = 89 , MIPS_INS_BGTZALC = 90 , MIPS_INS_BGTZC = 91 , MIPS_INS_BGTZL = 92 , MIPS_INS_BINSLI = 93 , MIPS_INS_BINSL = 94 , MIPS_INS_BINSRI = 95 , MIPS_INS_BINSR = 96 , MIPS_INS_BITREV = 97 , MIPS_INS_BITSWAP = 98 , MIPS_INS_BLEZ = 99 , MIPS_INS_BLEZALC = 100 , MIPS_INS_BLEZC = 101 , MIPS_INS_BLEZL = 102 , MIPS_INS_BLTC = 103 , MIPS_INS_BLTUC = 104 , MIPS_INS_BLTZ = 105 , MIPS_INS_BLTZAL = 106 , MIPS_INS_BLTZALC = 107 , MIPS_INS_BLTZALL = 108 , MIPS_INS_BLTZALS = 109 , MIPS_INS_BLTZC = 110 , MIPS_INS_BLTZL = 111 , MIPS_INS_BMNZI = 112 , MIPS_INS_BMNZ = 113 , MIPS_INS_BMZI = 114 , MIPS_INS_BMZ = 115 , MIPS_INS_BNE = 116 , MIPS_INS_BNEC = 117 , MIPS_INS_BNEGI = 118 , MIPS_INS_BNEG = 119 , MIPS_INS_BNEL = 120 , MIPS_INS_BNEZ16 = 121 , MIPS_INS_BNEZALC = 122 , MIPS_INS_BNEZC = 123 , MIPS_INS_BNVC = 124 , MIPS_INS_BNZ = 125 , MIPS_INS_BOVC = 126 , MIPS_INS_BPOSGE32 = 127 , MIPS_INS_BREAK = 128 , MIPS_INS_BREAK16 = 129 , MIPS_INS_BSELI = 130 , MIPS_INS_BSEL = 131 , MIPS_INS_BSETI = 132 , MIPS_INS_BSET = 133 , MIPS_INS_BZ = 134 , MIPS_INS_BEQZ = 135 , MIPS_INS_B = 136 , MIPS_INS_BNEZ = 137 , MIPS_INS_BTEQZ = 138 , MIPS_INS_BTNEZ = 139 , MIPS_INS_CACHE = 140 , MIPS_INS_CEIL = 141 , MIPS_INS_CEQI = 142 , MIPS_INS_CEQ = 143 , MIPS_INS_CFC1 = 144 , MIPS_INS_CFCMSA = 145 , MIPS_INS_CINS = 146 , MIPS_INS_CINS32 = 147 , MIPS_INS_CLASS = 148 , MIPS_INS_CLEI_S = 149 , MIPS_INS_CLEI_U = 150 , MIPS_INS_CLE_S = 151 , MIPS_INS_CLE_U = 152 , MIPS_INS_CLO = 153 , MIPS_INS_CLTI_S = 154 , MIPS_INS_CLTI_U = 155 , MIPS_INS_CLT_S = 156 , MIPS_INS_CLT_U = 157 , MIPS_INS_CLZ = 158 , MIPS_INS_CMPGDU = 159 , MIPS_INS_CMPGU = 160 , MIPS_INS_CMPU = 161 , MIPS_INS_CMP = 162 , MIPS_INS_COPY_S = 163 , MIPS_INS_COPY_U = 164 , MIPS_INS_CTC1 = 165 , MIPS_INS_CTCMSA = 166 , MIPS_INS_CVT = 167 , MIPS_INS_C = 168 , MIPS_INS_CMPI = 169 , MIPS_INS_DADD = 170 , MIPS_INS_DADDI = 171 , MIPS_INS_DADDIU = 172 , MIPS_INS_DADDU = 173 , MIPS_INS_DAHI = 174 , MIPS_INS_DALIGN = 175 , MIPS_INS_DATI = 176 , MIPS_INS_DAUI = 177 , MIPS_INS_DBITSWAP = 178 , MIPS_INS_DCLO = 179 , MIPS_INS_DCLZ = 180 , MIPS_INS_DDIV = 181 , MIPS_INS_DDIVU = 182 , MIPS_INS_DERET = 183 , MIPS_INS_DEXT = 184 , MIPS_INS_DEXTM = 185 , MIPS_INS_DEXTU = 186 , MIPS_INS_DI = 187 , MIPS_INS_DINS = 188 , MIPS_INS_DINSM = 189 , MIPS_INS_DINSU = 190 , MIPS_INS_DIV = 191 , MIPS_INS_DIVU = 192 , MIPS_INS_DIV_S = 193 , MIPS_INS_DIV_U = 194 , MIPS_INS_DLSA = 195 , MIPS_INS_DMFC0 = 196 , MIPS_INS_DMFC1 = 197 , MIPS_INS_DMFC2 = 198 , MIPS_INS_DMOD = 199 , MIPS_INS_DMODU = 200 , MIPS_INS_DMTC0 = 201 , MIPS_INS_DMTC1 = 202 , MIPS_INS_DMTC2 = 203 , MIPS_INS_DMUH = 204 , MIPS_INS_DMUHU = 205 , MIPS_INS_DMUL = 206 , MIPS_INS_DMULT = 207 , MIPS_INS_DMULTU = 208 , MIPS_INS_DMULU = 209 , MIPS_INS_DOTP_S = 210 , MIPS_INS_DOTP_U = 211 , MIPS_INS_DPADD_S = 212 , MIPS_INS_DPADD_U = 213 , MIPS_INS_DPAQX_SA = 214 , MIPS_INS_DPAQX_S = 215 , MIPS_INS_DPAQ_SA = 216 , MIPS_INS_DPAQ_S = 217 , MIPS_INS_DPAU = 218 , MIPS_INS_DPAX = 219 , MIPS_INS_DPA = 220 , MIPS_INS_DPOP = 221 , MIPS_INS_DPSQX_SA = 222 , MIPS_INS_DPSQX_S = 223 , MIPS_INS_DPSQ_SA = 224 , MIPS_INS_DPSQ_S = 225 , MIPS_INS_DPSUB_S = 226 , MIPS_INS_DPSUB_U = 227 , MIPS_INS_DPSU = 228 , MIPS_INS_DPSX = 229 , MIPS_INS_DPS = 230 , MIPS_INS_DROTR = 231 , MIPS_INS_DROTR32 = 232 , MIPS_INS_DROTRV = 233 , MIPS_INS_DSBH = 234 , MIPS_INS_DSHD = 235 , MIPS_INS_DSLL = 236 , MIPS_INS_DSLL32 = 237 , MIPS_INS_DSLLV = 238 , MIPS_INS_DSRA = 239 , MIPS_INS_DSRA32 = 240 , MIPS_INS_DSRAV = 241 , MIPS_INS_DSRL = 242 , MIPS_INS_DSRL32 = 243 , MIPS_INS_DSRLV = 244 , MIPS_INS_DSUB = 245 , MIPS_INS_DSUBU = 246 , MIPS_INS_EHB = 247 , MIPS_INS_EI = 248 , MIPS_INS_ERET = 249 , MIPS_INS_EXT = 250 , MIPS_INS_EXTP = 251 , MIPS_INS_EXTPDP = 252 , MIPS_INS_EXTPDPV = 253 , MIPS_INS_EXTPV = 254 , MIPS_INS_EXTRV_RS = 255 , MIPS_INS_EXTRV_R = 256 , MIPS_INS_EXTRV_S = 257 , MIPS_INS_EXTRV = 258 , MIPS_INS_EXTR_RS = 259 , MIPS_INS_EXTR_R = 260 , MIPS_INS_EXTR_S = 261 , MIPS_INS_EXTR = 262 , MIPS_INS_EXTS = 263 , MIPS_INS_EXTS32 = 264 , MIPS_INS_ABS = 265 , MIPS_INS_FADD = 266 , MIPS_INS_FCAF = 267 , MIPS_INS_FCEQ = 268 , MIPS_INS_FCLASS = 269 , MIPS_INS_FCLE = 270 , MIPS_INS_FCLT = 271 , MIPS_INS_FCNE = 272 , MIPS_INS_FCOR = 273 , MIPS_INS_FCUEQ = 274 , MIPS_INS_FCULE = 275 , MIPS_INS_FCULT = 276 , MIPS_INS_FCUNE = 277 , MIPS_INS_FCUN = 278 , MIPS_INS_FDIV = 279 , MIPS_INS_FEXDO = 280 , MIPS_INS_FEXP2 = 281 , MIPS_INS_FEXUPL = 282 , MIPS_INS_FEXUPR = 283 , MIPS_INS_FFINT_S = 284 , MIPS_INS_FFINT_U = 285 , MIPS_INS_FFQL = 286 , MIPS_INS_FFQR = 287 , MIPS_INS_FILL = 288 , MIPS_INS_FLOG2 = 289 , MIPS_INS_FLOOR = 290 , MIPS_INS_FMADD = 291 , MIPS_INS_FMAX_A = 292 , MIPS_INS_FMAX = 293 , MIPS_INS_FMIN_A = 294 , MIPS_INS_FMIN = 295 , MIPS_INS_MOV = 296 , MIPS_INS_FMSUB = 297 , MIPS_INS_FMUL = 298 , MIPS_INS_MUL = 299 , MIPS_INS_NEG = 300 , MIPS_INS_FRCP = 301 , MIPS_INS_FRINT = 302 , MIPS_INS_FRSQRT = 303 , MIPS_INS_FSAF = 304 , MIPS_INS_FSEQ = 305 , MIPS_INS_FSLE = 306 , MIPS_INS_FSLT = 307 , MIPS_INS_FSNE = 308 , MIPS_INS_FSOR = 309 , MIPS_INS_FSQRT = 310 , MIPS_INS_SQRT = 311 , MIPS_INS_FSUB = 312 , MIPS_INS_SUB = 313 , MIPS_INS_FSUEQ = 314 , MIPS_INS_FSULE = 315 , MIPS_INS_FSULT = 316 , MIPS_INS_FSUNE = 317 , MIPS_INS_FSUN = 318 , MIPS_INS_FTINT_S = 319 , MIPS_INS_FTINT_U = 320 , MIPS_INS_FTQ = 321 , MIPS_INS_FTRUNC_S = 322 , MIPS_INS_FTRUNC_U = 323 , MIPS_INS_HADD_S = 324 , MIPS_INS_HADD_U = 325 , MIPS_INS_HSUB_S = 326 , MIPS_INS_HSUB_U = 327 , MIPS_INS_ILVEV = 328 , MIPS_INS_ILVL = 329 , MIPS_INS_ILVOD = 330 , MIPS_INS_ILVR = 331 , MIPS_INS_INS = 332 , MIPS_INS_INSERT = 333 , MIPS_INS_INSV = 334 , MIPS_INS_INSVE = 335 , MIPS_INS_J = 336 , MIPS_INS_JAL = 337 , MIPS_INS_JALR = 338 , MIPS_INS_JALRS16 = 339 , MIPS_INS_JALRS = 340 , MIPS_INS_JALS = 341 , MIPS_INS_JALX = 342 , MIPS_INS_JIALC = 343 , MIPS_INS_JIC = 344 , MIPS_INS_JR = 345 , MIPS_INS_JR16 = 346 , MIPS_INS_JRADDIUSP = 347 , MIPS_INS_JRC = 348 , MIPS_INS_JALRC = 349 , MIPS_INS_LB = 350 , MIPS_INS_LBU16 = 351 , MIPS_INS_LBUX = 352 , MIPS_INS_LBU = 353 , MIPS_INS_LD = 354 , MIPS_INS_LDC1 = 355 , MIPS_INS_LDC2 = 356 , MIPS_INS_LDC3 = 357 , MIPS_INS_LDI = 358 , MIPS_INS_LDL = 359 , MIPS_INS_LDPC = 360 , MIPS_INS_LDR = 361 , MIPS_INS_LDXC1 = 362 , MIPS_INS_LH = 363 , MIPS_INS_LHU16 = 364 , MIPS_INS_LHX = 365 , MIPS_INS_LHU = 366 , MIPS_INS_LI16 = 367 , MIPS_INS_LL = 368 , MIPS_INS_LLD = 369 , MIPS_INS_LSA = 370 , MIPS_INS_LUXC1 = 371 , MIPS_INS_LUI = 372 , MIPS_INS_LW = 373 , MIPS_INS_LW16 = 374 , MIPS_INS_LWC1 = 375 , MIPS_INS_LWC2 = 376 , MIPS_INS_LWC3 = 377 , MIPS_INS_LWL = 378 , MIPS_INS_LWM16 = 379 , MIPS_INS_LWM32 = 380 , MIPS_INS_LWPC = 381 , MIPS_INS_LWP = 382 , MIPS_INS_LWR = 383 , MIPS_INS_LWUPC = 384 , MIPS_INS_LWU = 385 , MIPS_INS_LWX = 386 , MIPS_INS_LWXC1 = 387 , MIPS_INS_LWXS = 388 , MIPS_INS_LI = 389 , MIPS_INS_MADD = 390 , MIPS_INS_MADDF = 391 , MIPS_INS_MADDR_Q = 392 , MIPS_INS_MADDU = 393 , MIPS_INS_MADDV = 394 , MIPS_INS_MADD_Q = 395 , MIPS_INS_MAQ_SA = 396 , MIPS_INS_MAQ_S = 397 , MIPS_INS_MAXA = 398 , MIPS_INS_MAXI_S = 399 , MIPS_INS_MAXI_U = 400 , MIPS_INS_MAX_A = 401 , MIPS_INS_MAX = 402 , MIPS_INS_MAX_S = 403 , MIPS_INS_MAX_U = 404 , MIPS_INS_MFC0 = 405 , MIPS_INS_MFC1 = 406 , MIPS_INS_MFC2 = 407 , MIPS_INS_MFHC1 = 408 , MIPS_INS_MFHI = 409 , MIPS_INS_MFLO = 410 , MIPS_INS_MINA = 411 , MIPS_INS_MINI_S = 412 , MIPS_INS_MINI_U = 413 , MIPS_INS_MIN_A = 414 , MIPS_INS_MIN = 415 , MIPS_INS_MIN_S = 416 , MIPS_INS_MIN_U = 417 , MIPS_INS_MOD = 418 , MIPS_INS_MODSUB = 419 , MIPS_INS_MODU = 420 , MIPS_INS_MOD_S = 421 , MIPS_INS_MOD_U = 422 , MIPS_INS_MOVE = 423 , MIPS_INS_MOVEP = 424 , MIPS_INS_MOVF = 425 , MIPS_INS_MOVN = 426 , MIPS_INS_MOVT = 427 , MIPS_INS_MOVZ = 428 , MIPS_INS_MSUB = 429 , MIPS_INS_MSUBF = 430 , MIPS_INS_MSUBR_Q = 431 , MIPS_INS_MSUBU = 432 , MIPS_INS_MSUBV = 433 , MIPS_INS_MSUB_Q = 434 , MIPS_INS_MTC0 = 435 , MIPS_INS_MTC1 = 436 , MIPS_INS_MTC2 = 437 , MIPS_INS_MTHC1 = 438 , MIPS_INS_MTHI = 439 , MIPS_INS_MTHLIP = 440 , MIPS_INS_MTLO = 441 , MIPS_INS_MTM0 = 442 , MIPS_INS_MTM1 = 443 , MIPS_INS_MTM2 = 444 , MIPS_INS_MTP0 = 445 , MIPS_INS_MTP1 = 446 , MIPS_INS_MTP2 = 447 , MIPS_INS_MUH = 448 , MIPS_INS_MUHU = 449 , MIPS_INS_MULEQ_S = 450 , MIPS_INS_MULEU_S = 451 , MIPS_INS_MULQ_RS = 452 , MIPS_INS_MULQ_S = 453 , MIPS_INS_MULR_Q = 454 , MIPS_INS_MULSAQ_S = 455 , MIPS_INS_MULSA = 456 , MIPS_INS_MULT = 457 , MIPS_INS_MULTU = 458 , MIPS_INS_MULU = 459 , MIPS_INS_MULV = 460 , MIPS_INS_MUL_Q = 461 , MIPS_INS_MUL_S = 462 , MIPS_INS_NLOC = 463 , MIPS_INS_NLZC = 464 , MIPS_INS_NMADD = 465 , MIPS_INS_NMSUB = 466 , MIPS_INS_NOR = 467 , MIPS_INS_NORI = 468 , MIPS_INS_NOT16 = 469 , MIPS_INS_NOT = 470 , MIPS_INS_OR = 471 , MIPS_INS_OR16 = 472 , MIPS_INS_ORI = 473 , MIPS_INS_PACKRL = 474 , MIPS_INS_PAUSE = 475 , MIPS_INS_PCKEV = 476 , MIPS_INS_PCKOD = 477 , MIPS_INS_PCNT = 478 , MIPS_INS_PICK = 479 , MIPS_INS_POP = 480 , MIPS_INS_PRECEQU = 481 , MIPS_INS_PRECEQ = 482 , MIPS_INS_PRECEU = 483 , MIPS_INS_PRECRQU_S = 484 , MIPS_INS_PRECRQ = 485 , MIPS_INS_PRECRQ_RS = 486 , MIPS_INS_PRECR = 487 , MIPS_INS_PRECR_SRA = 488 , MIPS_INS_PRECR_SRA_R = 489 , MIPS_INS_PREF = 490 , MIPS_INS_PREPEND = 491 , MIPS_INS_RADDU = 492 , MIPS_INS_RDDSP = 493 , MIPS_INS_RDHWR = 494 , MIPS_INS_REPLV = 495 , MIPS_INS_REPL = 496 , MIPS_INS_RINT = 497 , MIPS_INS_ROTR = 498 , MIPS_INS_ROTRV = 499 , MIPS_INS_ROUND = 500 , MIPS_INS_SAT_S = 501 , MIPS_INS_SAT_U = 502 , MIPS_INS_SB = 503 , MIPS_INS_SB16 = 504 , MIPS_INS_SC = 505 , MIPS_INS_SCD = 506 , MIPS_INS_SD = 507 , MIPS_INS_SDBBP = 508 , MIPS_INS_SDBBP16 = 509 , MIPS_INS_SDC1 = 510 , MIPS_INS_SDC2 = 511 , MIPS_INS_SDC3 = 512 , MIPS_INS_SDL = 513 , MIPS_INS_SDR = 514 , MIPS_INS_SDXC1 = 515 , MIPS_INS_SEB = 516 , MIPS_INS_SEH = 517 , MIPS_INS_SELEQZ = 518 , MIPS_INS_SELNEZ = 519 , MIPS_INS_SEL = 520 , MIPS_INS_SEQ = 521 , MIPS_INS_SEQI = 522 , MIPS_INS_SH = 523 , MIPS_INS_SH16 = 524 , MIPS_INS_SHF = 525 , MIPS_INS_SHILO = 526 , MIPS_INS_SHILOV = 527 , MIPS_INS_SHLLV = 528 , MIPS_INS_SHLLV_S = 529 , MIPS_INS_SHLL = 530 , MIPS_INS_SHLL_S = 531 , MIPS_INS_SHRAV = 532 , MIPS_INS_SHRAV_R = 533 , MIPS_INS_SHRA = 534 , MIPS_INS_SHRA_R = 535 , MIPS_INS_SHRLV = 536 , MIPS_INS_SHRL = 537 , MIPS_INS_SLDI = 538 , MIPS_INS_SLD = 539 , MIPS_INS_SLL = 540 , MIPS_INS_SLL16 = 541 , MIPS_INS_SLLI = 542 , MIPS_INS_SLLV = 543 , MIPS_INS_SLT = 544 , MIPS_INS_SLTI = 545 , MIPS_INS_SLTIU = 546 , MIPS_INS_SLTU = 547 , MIPS_INS_SNE = 548 , MIPS_INS_SNEI = 549 , MIPS_INS_SPLATI = 550 , MIPS_INS_SPLAT = 551 , MIPS_INS_SRA = 552 , MIPS_INS_SRAI = 553 , MIPS_INS_SRARI = 554 , MIPS_INS_SRAR = 555 , MIPS_INS_SRAV = 556 , MIPS_INS_SRL = 557 , MIPS_INS_SRL16 = 558 , MIPS_INS_SRLI = 559 , MIPS_INS_SRLRI = 560 , MIPS_INS_SRLR = 561 , MIPS_INS_SRLV = 562 , MIPS_INS_SSNOP = 563 , MIPS_INS_ST = 564 , MIPS_INS_SUBQH = 565 , MIPS_INS_SUBQH_R = 566 , MIPS_INS_SUBQ = 567 , MIPS_INS_SUBQ_S = 568 , MIPS_INS_SUBSUS_U = 569 , MIPS_INS_SUBSUU_S = 570 , MIPS_INS_SUBS_S = 571 , MIPS_INS_SUBS_U = 572 , MIPS_INS_SUBU16 = 573 , MIPS_INS_SUBUH = 574 , MIPS_INS_SUBUH_R = 575 , MIPS_INS_SUBU = 576 , MIPS_INS_SUBU_S = 577 , MIPS_INS_SUBVI = 578 , MIPS_INS_SUBV = 579 , MIPS_INS_SUXC1 = 580 , MIPS_INS_SW = 581 , MIPS_INS_SW16 = 582 , MIPS_INS_SWC1 = 583 , MIPS_INS_SWC2 = 584 , MIPS_INS_SWC3 = 585 , MIPS_INS_SWL = 586 , MIPS_INS_SWM16 = 587 , MIPS_INS_SWM32 = 588 , MIPS_INS_SWP = 589 , MIPS_INS_SWR = 590 , MIPS_INS_SWXC1 = 591 , MIPS_INS_SYNC = 592 , MIPS_INS_SYNCI = 593 , MIPS_INS_SYSCALL = 594 , MIPS_INS_TEQ = 595 , MIPS_INS_TEQI = 596 , MIPS_INS_TGE = 597 , MIPS_INS_TGEI = 598 , MIPS_INS_TGEIU = 599 , MIPS_INS_TGEU = 600 , MIPS_INS_TLBP = 601 , MIPS_INS_TLBR = 602 , MIPS_INS_TLBWI = 603 , MIPS_INS_TLBWR = 604 , MIPS_INS_TLT = 605 , MIPS_INS_TLTI = 606 , MIPS_INS_TLTIU = 607 , MIPS_INS_TLTU = 608 , MIPS_INS_TNE = 609 , MIPS_INS_TNEI = 610 , MIPS_INS_TRUNC = 611 , MIPS_INS_V3MULU = 612 , MIPS_INS_VMM0 = 613 , MIPS_INS_VMULU = 614 , MIPS_INS_VSHF = 615 , MIPS_INS_WAIT = 616 , MIPS_INS_WRDSP = 617 , MIPS_INS_WSBH = 618 , MIPS_INS_XOR = 619 , MIPS_INS_XOR16 = 620 , MIPS_INS_XORI = 621 , MIPS_INS_NOP = 622 , MIPS_INS_NEGU = 623 , MIPS_INS_JALR_HB = 624 , MIPS_INS_JR_HB = 625 , MIPS_INS_ENDING = 626 , } # [repr (u32)] # [doc = " Group of MIPS instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn_group { # [doc = "< = CS_GRP_INVALID"] MIPS_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MIPS_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] MIPS_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MIPS_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MIPS_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MIPS_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] MIPS_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MIPS_GRP_BRANCH_RELATIVE = 7 , MIPS_GRP_BITCOUNT = 128 , MIPS_GRP_DSP = 129 , MIPS_GRP_DSPR2 = 130 , MIPS_GRP_FPIDX = 131 , MIPS_GRP_MSA = 132 , MIPS_GRP_MIPS32R2 = 133 , MIPS_GRP_MIPS64 = 134 , MIPS_GRP_MIPS64R2 = 135 , MIPS_GRP_SEINREG = 136 , MIPS_GRP_STDENC = 137 , MIPS_GRP_SWAP = 138 , MIPS_GRP_MICROMIPS = 139 , MIPS_GRP_MIPS16MODE = 140 , MIPS_GRP_FP64BIT = 141 , MIPS_GRP_NONANSFPMATH = 142 , MIPS_GRP_NOTFP64BIT = 143 , MIPS_GRP_NOTINMICROMIPS = 144 , MIPS_GRP_NOTNACL = 145 , MIPS_GRP_NOTMIPS32R6 = 146 , MIPS_GRP_NOTMIPS64R6 = 147 , MIPS_GRP_CNMIPS = 148 , MIPS_GRP_MIPS32 = 149 , MIPS_GRP_MIPS32R6 = 150 , MIPS_GRP_MIPS64R6 = 151 , MIPS_GRP_MIPS2 = 152 , MIPS_GRP_MIPS3 = 153 , MIPS_GRP_MIPS3_32 = 154 , MIPS_GRP_MIPS3_32R2 = 155 , MIPS_GRP_MIPS4_32 = 156 , MIPS_GRP_MIPS4_32R2 = 157 , MIPS_GRP_MIPS5_32R2 = 158 , MIPS_GRP_GP32BIT = 159 , MIPS_GRP_GP64BIT = 160 , MIPS_GRP_ENDING = 161 , } # [repr (u32)] # [doc = " PPC branch codes for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bc { PPC_BC_INVALID = 0 , PPC_BC_LT = 12 , PPC_BC_LE = 36 , PPC_BC_EQ = 76 , PPC_BC_GE = 4 , PPC_BC_GT = 44 , PPC_BC_NE = 68 , PPC_BC_UN = 108 , PPC_BC_NU = 100 , # [doc = "< summary overflow"] PPC_BC_SO = 140 , # [doc = "< not summary overflow"] PPC_BC_NS = 132 , } # [repr (u32)] # [doc = " PPC branch hint for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bh { # [doc = "< no hint"] PPC_BH_INVALID = 0 , # [doc = "< PLUS hint"] PPC_BH_PLUS = 1 , # [doc = "< MINUS hint"] PPC_BH_MINUS = 2 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] PPC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] PPC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] PPC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] PPC_OP_MEM = 3 , # [doc = "< Condition Register field"] PPC_OP_CRX = 64 , } # [repr (u32)] # [doc = " PPC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_reg { PPC_REG_INVALID = 0 , PPC_REG_CARRY = 2 , PPC_REG_CTR = 3 , PPC_REG_LR = 5 , PPC_REG_RM = 6 , PPC_REG_VRSAVE = 8 , PPC_REG_XER = 9 , PPC_REG_ZERO = 10 , PPC_REG_CR0 = 12 , PPC_REG_CR1 = 13 , PPC_REG_CR2 = 14 , PPC_REG_CR3 = 15 , PPC_REG_CR4 = 16 , PPC_REG_CR5 = 17 , PPC_REG_CR6 = 18 , PPC_REG_CR7 = 19 , PPC_REG_CTR8 = 20 , PPC_REG_F0 = 21 , PPC_REG_F1 = 22 , PPC_REG_F2 = 23 , PPC_REG_F3 = 24 , PPC_REG_F4 = 25 , PPC_REG_F5 = 26 , PPC_REG_F6 = 27 , PPC_REG_F7 = 28 , PPC_REG_F8 = 29 , PPC_REG_F9 = 30 , PPC_REG_F10 = 31 , PPC_REG_F11 = 32 , PPC_REG_F12 = 33 , PPC_REG_F13 = 34 , PPC_REG_F14 = 35 , PPC_REG_F15 = 36 , PPC_REG_F16 = 37 , PPC_REG_F17 = 38 , PPC_REG_F18 = 39 , PPC_REG_F19 = 40 , PPC_REG_F20 = 41 , PPC_REG_F21 = 42 , PPC_REG_F22 = 43 , PPC_REG_F23 = 44 , PPC_REG_F24 = 45 , PPC_REG_F25 = 46 , PPC_REG_F26 = 47 , PPC_REG_F27 = 48 , PPC_REG_F28 = 49 , PPC_REG_F29 = 50 , PPC_REG_F30 = 51 , PPC_REG_F31 = 52 , PPC_REG_LR8 = 54 , PPC_REG_Q0 = 55 , PPC_REG_Q1 = 56 , PPC_REG_Q2 = 57 , PPC_REG_Q3 = 58 , PPC_REG_Q4 = 59 , PPC_REG_Q5 = 60 , PPC_REG_Q6 = 61 , PPC_REG_Q7 = 62 , PPC_REG_Q8 = 63 , PPC_REG_Q9 = 64 , PPC_REG_Q10 = 65 , PPC_REG_Q11 = 66 , PPC_REG_Q12 = 67 , PPC_REG_Q13 = 68 , PPC_REG_Q14 = 69 , PPC_REG_Q15 = 70 , PPC_REG_Q16 = 71 , PPC_REG_Q17 = 72 , PPC_REG_Q18 = 73 , PPC_REG_Q19 = 74 , PPC_REG_Q20 = 75 , PPC_REG_Q21 = 76 , PPC_REG_Q22 = 77 , PPC_REG_Q23 = 78 , PPC_REG_Q24 = 79 , PPC_REG_Q25 = 80 , PPC_REG_Q26 = 81 , PPC_REG_Q27 = 82 , PPC_REG_Q28 = 83 , PPC_REG_Q29 = 84 , PPC_REG_Q30 = 85 , PPC_REG_Q31 = 86 , PPC_REG_R0 = 87 , PPC_REG_R1 = 88 , PPC_REG_R2 = 89 , PPC_REG_R3 = 90 , PPC_REG_R4 = 91 , PPC_REG_R5 = 92 , PPC_REG_R6 = 93 , PPC_REG_R7 = 94 , PPC_REG_R8 = 95 , PPC_REG_R9 = 96 , PPC_REG_R10 = 97 , PPC_REG_R11 = 98 , PPC_REG_R12 = 99 , PPC_REG_R13 = 100 , PPC_REG_R14 = 101 , PPC_REG_R15 = 102 , PPC_REG_R16 = 103 , PPC_REG_R17 = 104 , PPC_REG_R18 = 105 , PPC_REG_R19 = 106 , PPC_REG_R20 = 107 , PPC_REG_R21 = 108 , PPC_REG_R22 = 109 , PPC_REG_R23 = 110 , PPC_REG_R24 = 111 , PPC_REG_R25 = 112 , PPC_REG_R26 = 113 , PPC_REG_R27 = 114 , PPC_REG_R28 = 115 , PPC_REG_R29 = 116 , PPC_REG_R30 = 117 , PPC_REG_R31 = 118 , PPC_REG_V0 = 151 , PPC_REG_V1 = 152 , PPC_REG_V2 = 153 , PPC_REG_V3 = 154 , PPC_REG_V4 = 155 , PPC_REG_V5 = 156 , PPC_REG_V6 = 157 , PPC_REG_V7 = 158 , PPC_REG_V8 = 159 , PPC_REG_V9 = 160 , PPC_REG_V10 = 161 , PPC_REG_V11 = 162 , PPC_REG_V12 = 163 , PPC_REG_V13 = 164 , PPC_REG_V14 = 165 , PPC_REG_V15 = 166 , PPC_REG_V16 = 167 , PPC_REG_V17 = 168 , PPC_REG_V18 = 169 , PPC_REG_V19 = 170 , PPC_REG_V20 = 171 , PPC_REG_V21 = 172 , PPC_REG_V22 = 173 , PPC_REG_V23 = 174 , PPC_REG_V24 = 175 , PPC_REG_V25 = 176 , PPC_REG_V26 = 177 , PPC_REG_V27 = 178 , PPC_REG_V28 = 179 , PPC_REG_V29 = 180 , PPC_REG_V30 = 181 , PPC_REG_V31 = 182 , PPC_REG_VS0 = 215 , PPC_REG_VS1 = 216 , PPC_REG_VS2 = 217 , PPC_REG_VS3 = 218 , PPC_REG_VS4 = 219 , PPC_REG_VS5 = 220 , PPC_REG_VS6 = 221 , PPC_REG_VS7 = 222 , PPC_REG_VS8 = 223 , PPC_REG_VS9 = 224 , PPC_REG_VS10 = 225 , PPC_REG_VS11 = 226 , PPC_REG_VS12 = 227 , PPC_REG_VS13 = 228 , PPC_REG_VS14 = 229 , PPC_REG_VS15 = 230 , PPC_REG_VS16 = 231 , PPC_REG_VS17 = 232 , PPC_REG_VS18 = 233 , PPC_REG_VS19 = 234 , PPC_REG_VS20 = 235 , PPC_REG_VS21 = 236 , PPC_REG_VS22 = 237 , PPC_REG_VS23 = 238 , PPC_REG_VS24 = 239 , PPC_REG_VS25 = 240 , PPC_REG_VS26 = 241 , PPC_REG_VS27 = 242 , PPC_REG_VS28 = 243 , PPC_REG_VS29 = 244 , PPC_REG_VS30 = 245 , PPC_REG_VS31 = 246 , PPC_REG_VS32 = 247 , PPC_REG_VS33 = 248 , PPC_REG_VS34 = 249 , PPC_REG_VS35 = 250 , PPC_REG_VS36 = 251 , PPC_REG_VS37 = 252 , PPC_REG_VS38 = 253 , PPC_REG_VS39 = 254 , PPC_REG_VS40 = 255 , PPC_REG_VS41 = 256 , PPC_REG_VS42 = 257 , PPC_REG_VS43 = 258 , PPC_REG_VS44 = 259 , PPC_REG_VS45 = 260 , PPC_REG_VS46 = 261 , PPC_REG_VS47 = 262 , PPC_REG_VS48 = 263 , PPC_REG_VS49 = 264 , PPC_REG_VS50 = 265 , PPC_REG_VS51 = 266 , PPC_REG_VS52 = 267 , PPC_REG_VS53 = 268 , PPC_REG_VS54 = 269 , PPC_REG_VS55 = 270 , PPC_REG_VS56 = 271 , PPC_REG_VS57 = 272 , PPC_REG_VS58 = 273 , PPC_REG_VS59 = 274 , PPC_REG_VS60 = 275 , PPC_REG_VS61 = 276 , PPC_REG_VS62 = 277 , PPC_REG_VS63 = 278 , PPC_REG_CR0EQ = 312 , PPC_REG_CR1EQ = 313 , PPC_REG_CR2EQ = 314 , PPC_REG_CR3EQ = 315 , PPC_REG_CR4EQ = 316 , PPC_REG_CR5EQ = 317 , PPC_REG_CR6EQ = 318 , PPC_REG_CR7EQ = 319 , PPC_REG_CR0GT = 320 , PPC_REG_CR1GT = 321 , PPC_REG_CR2GT = 322 , PPC_REG_CR3GT = 323 , PPC_REG_CR4GT = 324 , PPC_REG_CR5GT = 325 , PPC_REG_CR6GT = 326 , PPC_REG_CR7GT = 327 , PPC_REG_CR0LT = 328 , PPC_REG_CR1LT = 329 , PPC_REG_CR2LT = 330 , PPC_REG_CR3LT = 331 , PPC_REG_CR4LT = 332 , PPC_REG_CR5LT = 333 , PPC_REG_CR6LT = 334 , PPC_REG_CR7LT = 335 , PPC_REG_CR0UN = 336 , PPC_REG_CR1UN = 337 , PPC_REG_CR2UN = 338 , PPC_REG_CR3UN = 339 , PPC_REG_CR4UN = 340 , PPC_REG_CR5UN = 341 , PPC_REG_CR6UN = 342 , PPC_REG_CR7UN = 343 , PPC_REG_ENDING = 344 , } # [doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_mem { # [doc = "< base register"] pub base : ppc_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_mem"] [:: std :: mem :: size_of :: < ppc_op_mem > () - 8usize] ; ["Alignment of ppc_op_mem"] [:: std :: mem :: align_of :: < ppc_op_mem > () - 4usize] ; ["Offset of field: ppc_op_mem::base"] [:: std :: mem :: offset_of ! (ppc_op_mem , base) - 0usize] ; ["Offset of field: ppc_op_mem::disp"] [:: std :: mem :: offset_of ! (ppc_op_mem , disp) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_crx { pub scale : :: std :: os :: raw :: c_uint , pub reg : ppc_reg , pub cond : ppc_bc , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_crx"] [:: std :: mem :: size_of :: < ppc_op_crx > () - 12usize] ; ["Alignment of ppc_op_crx"] [:: std :: mem :: align_of :: < ppc_op_crx > () - 4usize] ; ["Offset of field: ppc_op_crx::scale"] [:: std :: mem :: offset_of ! (ppc_op_crx , scale) - 0usize] ; ["Offset of field: ppc_op_crx::reg"] [:: std :: mem :: offset_of ! (ppc_op_crx , reg) - 4usize] ; ["Offset of field: ppc_op_crx::cond"] [:: std :: mem :: offset_of ! (ppc_op_crx , cond) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc_op { # [doc = "< operand type"] pub type_ : ppc_op_type , pub __bindgen_anon_1 : cs_ppc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_ppc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : ppc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : ppc_op_mem , # [doc = "< operand with condition register"] pub crx : ppc_op_crx , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_ppc_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_ppc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::crx"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , crx) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op"] [:: std :: mem :: size_of :: < cs_ppc_op > () - 24usize] ; ["Alignment of cs_ppc_op"] [:: std :: mem :: align_of :: < cs_ppc_op > () - 8usize] ; ["Offset of field: cs_ppc_op::type_"] [:: std :: mem :: offset_of ! (cs_ppc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc { # [doc = " branch code for branch instructions"] pub bc : ppc_bc , # [doc = " branch hint for branch instructions"] pub bh : ppc_bh , # [doc = " if update_cr0 = True, then this 'dot' insn updates CR0"] pub update_cr0 : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_ppc_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc"] [:: std :: mem :: size_of :: < cs_ppc > () - 208usize] ; ["Alignment of cs_ppc"] [:: std :: mem :: align_of :: < cs_ppc > () - 8usize] ; ["Offset of field: cs_ppc::bc"] [:: std :: mem :: offset_of ! (cs_ppc , bc) - 0usize] ; ["Offset of field: cs_ppc::bh"] [:: std :: mem :: offset_of ! (cs_ppc , bh) - 4usize] ; ["Offset of field: cs_ppc::update_cr0"] [:: std :: mem :: offset_of ! (cs_ppc , update_cr0) - 8usize] ; ["Offset of field: cs_ppc::op_count"] [:: std :: mem :: offset_of ! (cs_ppc , op_count) - 9usize] ; ["Offset of field: cs_ppc::operands"] [:: std :: mem :: offset_of ! (cs_ppc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}" , self . bc , self . bh , self . update_cr0 , self . op_count , self . operands) } } # [repr (u32)] # [doc = " PPC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn { PPC_INS_INVALID = 0 , PPC_INS_ADD = 1 , PPC_INS_ADDC = 2 , PPC_INS_ADDE = 3 , PPC_INS_ADDI = 4 , PPC_INS_ADDIC = 5 , PPC_INS_ADDIS = 6 , PPC_INS_ADDME = 7 , PPC_INS_ADDPCIS = 8 , PPC_INS_ADDZE = 9 , PPC_INS_AND = 10 , PPC_INS_ANDC = 11 , PPC_INS_ANDI = 12 , PPC_INS_ANDIS = 13 , PPC_INS_ATTN = 14 , PPC_INS_B = 15 , PPC_INS_BA = 16 , PPC_INS_BC = 17 , PPC_INS_BCA = 18 , PPC_INS_BCCTR = 19 , PPC_INS_BCCTRL = 20 , PPC_INS_BCDCFN = 21 , PPC_INS_BCDCFSQ = 22 , PPC_INS_BCDCFZ = 23 , PPC_INS_BCDCPSGN = 24 , PPC_INS_BCDCTN = 25 , PPC_INS_BCDCTSQ = 26 , PPC_INS_BCDCTZ = 27 , PPC_INS_BCDS = 28 , PPC_INS_BCDSETSGN = 29 , PPC_INS_BCDSR = 30 , PPC_INS_BCDTRUNC = 31 , PPC_INS_BCDUS = 32 , PPC_INS_BCDUTRUNC = 33 , PPC_INS_BCL = 34 , PPC_INS_BCLA = 35 , PPC_INS_BCLR = 36 , PPC_INS_BCLRL = 37 , PPC_INS_BCTR = 38 , PPC_INS_BCTRL = 39 , PPC_INS_BDNZ = 40 , PPC_INS_BDNZA = 41 , PPC_INS_BDNZF = 42 , PPC_INS_BDNZFA = 43 , PPC_INS_BDNZFL = 44 , PPC_INS_BDNZFLA = 45 , PPC_INS_BDNZFLR = 46 , PPC_INS_BDNZFLRL = 47 , PPC_INS_BDNZL = 48 , PPC_INS_BDNZLA = 49 , PPC_INS_BDNZLR = 50 , PPC_INS_BDNZLRL = 51 , PPC_INS_BDNZT = 52 , PPC_INS_BDNZTA = 53 , PPC_INS_BDNZTL = 54 , PPC_INS_BDNZTLA = 55 , PPC_INS_BDNZTLR = 56 , PPC_INS_BDNZTLRL = 57 , PPC_INS_BDZ = 58 , PPC_INS_BDZA = 59 , PPC_INS_BDZF = 60 , PPC_INS_BDZFA = 61 , PPC_INS_BDZFL = 62 , PPC_INS_BDZFLA = 63 , PPC_INS_BDZFLR = 64 , PPC_INS_BDZFLRL = 65 , PPC_INS_BDZL = 66 , PPC_INS_BDZLA = 67 , PPC_INS_BDZLR = 68 , PPC_INS_BDZLRL = 69 , PPC_INS_BDZT = 70 , PPC_INS_BDZTA = 71 , PPC_INS_BDZTL = 72 , PPC_INS_BDZTLA = 73 , PPC_INS_BDZTLR = 74 , PPC_INS_BDZTLRL = 75 , PPC_INS_BEQ = 76 , PPC_INS_BEQA = 77 , PPC_INS_BEQCTR = 78 , PPC_INS_BEQCTRL = 79 , PPC_INS_BEQL = 80 , PPC_INS_BEQLA = 81 , PPC_INS_BEQLR = 82 , PPC_INS_BEQLRL = 83 , PPC_INS_BF = 84 , PPC_INS_BFA = 85 , PPC_INS_BFCTR = 86 , PPC_INS_BFCTRL = 87 , PPC_INS_BFL = 88 , PPC_INS_BFLA = 89 , PPC_INS_BFLR = 90 , PPC_INS_BFLRL = 91 , PPC_INS_BGE = 92 , PPC_INS_BGEA = 93 , PPC_INS_BGECTR = 94 , PPC_INS_BGECTRL = 95 , PPC_INS_BGEL = 96 , PPC_INS_BGELA = 97 , PPC_INS_BGELR = 98 , PPC_INS_BGELRL = 99 , PPC_INS_BGT = 100 , PPC_INS_BGTA = 101 , PPC_INS_BGTCTR = 102 , PPC_INS_BGTCTRL = 103 , PPC_INS_BGTL = 104 , PPC_INS_BGTLA = 105 , PPC_INS_BGTLR = 106 , PPC_INS_BGTLRL = 107 , PPC_INS_BL = 108 , PPC_INS_BLA = 109 , PPC_INS_BLE = 110 , PPC_INS_BLEA = 111 , PPC_INS_BLECTR = 112 , PPC_INS_BLECTRL = 113 , PPC_INS_BLEL = 114 , PPC_INS_BLELA = 115 , PPC_INS_BLELR = 116 , PPC_INS_BLELRL = 117 , PPC_INS_BLR = 118 , PPC_INS_BLRL = 119 , PPC_INS_BLT = 120 , PPC_INS_BLTA = 121 , PPC_INS_BLTCTR = 122 , PPC_INS_BLTCTRL = 123 , PPC_INS_BLTL = 124 , PPC_INS_BLTLA = 125 , PPC_INS_BLTLR = 126 , PPC_INS_BLTLRL = 127 , PPC_INS_BNE = 128 , PPC_INS_BNEA = 129 , PPC_INS_BNECTR = 130 , PPC_INS_BNECTRL = 131 , PPC_INS_BNEL = 132 , PPC_INS_BNELA = 133 , PPC_INS_BNELR = 134 , PPC_INS_BNELRL = 135 , PPC_INS_BNG = 136 , PPC_INS_BNGA = 137 , PPC_INS_BNGCTR = 138 , PPC_INS_BNGCTRL = 139 , PPC_INS_BNGL = 140 , PPC_INS_BNGLA = 141 , PPC_INS_BNGLR = 142 , PPC_INS_BNGLRL = 143 , PPC_INS_BNL = 144 , PPC_INS_BNLA = 145 , PPC_INS_BNLCTR = 146 , PPC_INS_BNLCTRL = 147 , PPC_INS_BNLL = 148 , PPC_INS_BNLLA = 149 , PPC_INS_BNLLR = 150 , PPC_INS_BNLLRL = 151 , PPC_INS_BNS = 152 , PPC_INS_BNSA = 153 , PPC_INS_BNSCTR = 154 , PPC_INS_BNSCTRL = 155 , PPC_INS_BNSL = 156 , PPC_INS_BNSLA = 157 , PPC_INS_BNSLR = 158 , PPC_INS_BNSLRL = 159 , PPC_INS_BNU = 160 , PPC_INS_BNUA = 161 , PPC_INS_BNUCTR = 162 , PPC_INS_BNUCTRL = 163 , PPC_INS_BNUL = 164 , PPC_INS_BNULA = 165 , PPC_INS_BNULR = 166 , PPC_INS_BNULRL = 167 , PPC_INS_BPERMD = 168 , PPC_INS_BRINC = 169 , PPC_INS_BSO = 170 , PPC_INS_BSOA = 171 , PPC_INS_BSOCTR = 172 , PPC_INS_BSOCTRL = 173 , PPC_INS_BSOL = 174 , PPC_INS_BSOLA = 175 , PPC_INS_BSOLR = 176 , PPC_INS_BSOLRL = 177 , PPC_INS_BT = 178 , PPC_INS_BTA = 179 , PPC_INS_BTCTR = 180 , PPC_INS_BTCTRL = 181 , PPC_INS_BTL = 182 , PPC_INS_BTLA = 183 , PPC_INS_BTLR = 184 , PPC_INS_BTLRL = 185 , PPC_INS_BUN = 186 , PPC_INS_BUNA = 187 , PPC_INS_BUNCTR = 188 , PPC_INS_BUNCTRL = 189 , PPC_INS_BUNL = 190 , PPC_INS_BUNLA = 191 , PPC_INS_BUNLR = 192 , PPC_INS_BUNLRL = 193 , PPC_INS_CLRBHRB = 194 , PPC_INS_CLRLDI = 195 , PPC_INS_CLRLSLDI = 196 , PPC_INS_CLRLSLWI = 197 , PPC_INS_CLRLWI = 198 , PPC_INS_CLRRDI = 199 , PPC_INS_CLRRWI = 200 , PPC_INS_CMP = 201 , PPC_INS_CMPB = 202 , PPC_INS_CMPD = 203 , PPC_INS_CMPDI = 204 , PPC_INS_CMPEQB = 205 , PPC_INS_CMPI = 206 , PPC_INS_CMPL = 207 , PPC_INS_CMPLD = 208 , PPC_INS_CMPLDI = 209 , PPC_INS_CMPLI = 210 , PPC_INS_CMPLW = 211 , PPC_INS_CMPLWI = 212 , PPC_INS_CMPRB = 213 , PPC_INS_CMPW = 214 , PPC_INS_CMPWI = 215 , PPC_INS_CNTLZD = 216 , PPC_INS_CNTLZW = 217 , PPC_INS_CNTTZD = 218 , PPC_INS_CNTTZW = 219 , PPC_INS_COPY = 220 , PPC_INS_COPY_FIRST = 221 , PPC_INS_CP_ABORT = 222 , PPC_INS_CRAND = 223 , PPC_INS_CRANDC = 224 , PPC_INS_CRCLR = 225 , PPC_INS_CREQV = 226 , PPC_INS_CRMOVE = 227 , PPC_INS_CRNAND = 228 , PPC_INS_CRNOR = 229 , PPC_INS_CRNOT = 230 , PPC_INS_CROR = 231 , PPC_INS_CRORC = 232 , PPC_INS_CRSET = 233 , PPC_INS_CRXOR = 234 , PPC_INS_DARN = 235 , PPC_INS_DCBA = 236 , PPC_INS_DCBF = 237 , PPC_INS_DCBFEP = 238 , PPC_INS_DCBFL = 239 , PPC_INS_DCBFLP = 240 , PPC_INS_DCBI = 241 , PPC_INS_DCBST = 242 , PPC_INS_DCBSTEP = 243 , PPC_INS_DCBT = 244 , PPC_INS_DCBTCT = 245 , PPC_INS_DCBTDS = 246 , PPC_INS_DCBTEP = 247 , PPC_INS_DCBTST = 248 , PPC_INS_DCBTSTCT = 249 , PPC_INS_DCBTSTDS = 250 , PPC_INS_DCBTSTEP = 251 , PPC_INS_DCBTSTT = 252 , PPC_INS_DCBTT = 253 , PPC_INS_DCBZ = 254 , PPC_INS_DCBZEP = 255 , PPC_INS_DCBZL = 256 , PPC_INS_DCBZLEP = 257 , PPC_INS_DCCCI = 258 , PPC_INS_DCI = 259 , PPC_INS_DIVD = 260 , PPC_INS_DIVDE = 261 , PPC_INS_DIVDEU = 262 , PPC_INS_DIVDU = 263 , PPC_INS_DIVW = 264 , PPC_INS_DIVWE = 265 , PPC_INS_DIVWEU = 266 , PPC_INS_DIVWU = 267 , PPC_INS_DSS = 268 , PPC_INS_DSSALL = 269 , PPC_INS_DST = 270 , PPC_INS_DSTST = 271 , PPC_INS_DSTSTT = 272 , PPC_INS_DSTT = 273 , PPC_INS_EFDABS = 274 , PPC_INS_EFDADD = 275 , PPC_INS_EFDCFS = 276 , PPC_INS_EFDCFSF = 277 , PPC_INS_EFDCFSI = 278 , PPC_INS_EFDCFSID = 279 , PPC_INS_EFDCFUF = 280 , PPC_INS_EFDCFUI = 281 , PPC_INS_EFDCFUID = 282 , PPC_INS_EFDCMPEQ = 283 , PPC_INS_EFDCMPGT = 284 , PPC_INS_EFDCMPLT = 285 , PPC_INS_EFDCTSF = 286 , PPC_INS_EFDCTSI = 287 , PPC_INS_EFDCTSIDZ = 288 , PPC_INS_EFDCTSIZ = 289 , PPC_INS_EFDCTUF = 290 , PPC_INS_EFDCTUI = 291 , PPC_INS_EFDCTUIDZ = 292 , PPC_INS_EFDCTUIZ = 293 , PPC_INS_EFDDIV = 294 , PPC_INS_EFDMUL = 295 , PPC_INS_EFDNABS = 296 , PPC_INS_EFDNEG = 297 , PPC_INS_EFDSUB = 298 , PPC_INS_EFDTSTEQ = 299 , PPC_INS_EFDTSTGT = 300 , PPC_INS_EFDTSTLT = 301 , PPC_INS_EFSABS = 302 , PPC_INS_EFSADD = 303 , PPC_INS_EFSCFD = 304 , PPC_INS_EFSCFSF = 305 , PPC_INS_EFSCFSI = 306 , PPC_INS_EFSCFUF = 307 , PPC_INS_EFSCFUI = 308 , PPC_INS_EFSCMPEQ = 309 , PPC_INS_EFSCMPGT = 310 , PPC_INS_EFSCMPLT = 311 , PPC_INS_EFSCTSF = 312 , PPC_INS_EFSCTSI = 313 , PPC_INS_EFSCTSIZ = 314 , PPC_INS_EFSCTUF = 315 , PPC_INS_EFSCTUI = 316 , PPC_INS_EFSCTUIZ = 317 , PPC_INS_EFSDIV = 318 , PPC_INS_EFSMUL = 319 , PPC_INS_EFSNABS = 320 , PPC_INS_EFSNEG = 321 , PPC_INS_EFSSUB = 322 , PPC_INS_EFSTSTEQ = 323 , PPC_INS_EFSTSTGT = 324 , PPC_INS_EFSTSTLT = 325 , PPC_INS_EIEIO = 326 , PPC_INS_EQV = 327 , PPC_INS_EVABS = 328 , PPC_INS_EVADDIW = 329 , PPC_INS_EVADDSMIAAW = 330 , PPC_INS_EVADDSSIAAW = 331 , PPC_INS_EVADDUMIAAW = 332 , PPC_INS_EVADDUSIAAW = 333 , PPC_INS_EVADDW = 334 , PPC_INS_EVAND = 335 , PPC_INS_EVANDC = 336 , PPC_INS_EVCMPEQ = 337 , PPC_INS_EVCMPGTS = 338 , PPC_INS_EVCMPGTU = 339 , PPC_INS_EVCMPLTS = 340 , PPC_INS_EVCMPLTU = 341 , PPC_INS_EVCNTLSW = 342 , PPC_INS_EVCNTLZW = 343 , PPC_INS_EVDIVWS = 344 , PPC_INS_EVDIVWU = 345 , PPC_INS_EVEQV = 346 , PPC_INS_EVEXTSB = 347 , PPC_INS_EVEXTSH = 348 , PPC_INS_EVFSABS = 349 , PPC_INS_EVFSADD = 350 , PPC_INS_EVFSCFSF = 351 , PPC_INS_EVFSCFSI = 352 , PPC_INS_EVFSCFUF = 353 , PPC_INS_EVFSCFUI = 354 , PPC_INS_EVFSCMPEQ = 355 , PPC_INS_EVFSCMPGT = 356 , PPC_INS_EVFSCMPLT = 357 , PPC_INS_EVFSCTSF = 358 , PPC_INS_EVFSCTSI = 359 , PPC_INS_EVFSCTSIZ = 360 , PPC_INS_EVFSCTUI = 361 , PPC_INS_EVFSDIV = 362 , PPC_INS_EVFSMUL = 363 , PPC_INS_EVFSNABS = 364 , PPC_INS_EVFSNEG = 365 , PPC_INS_EVFSSUB = 366 , PPC_INS_EVFSTSTEQ = 367 , PPC_INS_EVFSTSTGT = 368 , PPC_INS_EVFSTSTLT = 369 , PPC_INS_EVLDD = 370 , PPC_INS_EVLDDX = 371 , PPC_INS_EVLDH = 372 , PPC_INS_EVLDHX = 373 , PPC_INS_EVLDW = 374 , PPC_INS_EVLDWX = 375 , PPC_INS_EVLHHESPLAT = 376 , PPC_INS_EVLHHESPLATX = 377 , PPC_INS_EVLHHOSSPLAT = 378 , PPC_INS_EVLHHOSSPLATX = 379 , PPC_INS_EVLHHOUSPLAT = 380 , PPC_INS_EVLHHOUSPLATX = 381 , PPC_INS_EVLWHE = 382 , PPC_INS_EVLWHEX = 383 , PPC_INS_EVLWHOS = 384 , PPC_INS_EVLWHOSX = 385 , PPC_INS_EVLWHOU = 386 , PPC_INS_EVLWHOUX = 387 , PPC_INS_EVLWHSPLAT = 388 , PPC_INS_EVLWHSPLATX = 389 , PPC_INS_EVLWWSPLAT = 390 , PPC_INS_EVLWWSPLATX = 391 , PPC_INS_EVMERGEHI = 392 , PPC_INS_EVMERGEHILO = 393 , PPC_INS_EVMERGELO = 394 , PPC_INS_EVMERGELOHI = 395 , PPC_INS_EVMHEGSMFAA = 396 , PPC_INS_EVMHEGSMFAN = 397 , PPC_INS_EVMHEGSMIAA = 398 , PPC_INS_EVMHEGSMIAN = 399 , PPC_INS_EVMHEGUMIAA = 400 , PPC_INS_EVMHEGUMIAN = 401 , PPC_INS_EVMHESMF = 402 , PPC_INS_EVMHESMFA = 403 , PPC_INS_EVMHESMFAAW = 404 , PPC_INS_EVMHESMFANW = 405 , PPC_INS_EVMHESMI = 406 , PPC_INS_EVMHESMIA = 407 , PPC_INS_EVMHESMIAAW = 408 , PPC_INS_EVMHESMIANW = 409 , PPC_INS_EVMHESSF = 410 , PPC_INS_EVMHESSFA = 411 , PPC_INS_EVMHESSFAAW = 412 , PPC_INS_EVMHESSFANW = 413 , PPC_INS_EVMHESSIAAW = 414 , PPC_INS_EVMHESSIANW = 415 , PPC_INS_EVMHEUMI = 416 , PPC_INS_EVMHEUMIA = 417 , PPC_INS_EVMHEUMIAAW = 418 , PPC_INS_EVMHEUMIANW = 419 , PPC_INS_EVMHEUSIAAW = 420 , PPC_INS_EVMHEUSIANW = 421 , PPC_INS_EVMHOGSMFAA = 422 , PPC_INS_EVMHOGSMFAN = 423 , PPC_INS_EVMHOGSMIAA = 424 , PPC_INS_EVMHOGSMIAN = 425 , PPC_INS_EVMHOGUMIAA = 426 , PPC_INS_EVMHOGUMIAN = 427 , PPC_INS_EVMHOSMF = 428 , PPC_INS_EVMHOSMFA = 429 , PPC_INS_EVMHOSMFAAW = 430 , PPC_INS_EVMHOSMFANW = 431 , PPC_INS_EVMHOSMI = 432 , PPC_INS_EVMHOSMIA = 433 , PPC_INS_EVMHOSMIAAW = 434 , PPC_INS_EVMHOSMIANW = 435 , PPC_INS_EVMHOSSF = 436 , PPC_INS_EVMHOSSFA = 437 , PPC_INS_EVMHOSSFAAW = 438 , PPC_INS_EVMHOSSFANW = 439 , PPC_INS_EVMHOSSIAAW = 440 , PPC_INS_EVMHOSSIANW = 441 , PPC_INS_EVMHOUMI = 442 , PPC_INS_EVMHOUMIA = 443 , PPC_INS_EVMHOUMIAAW = 444 , PPC_INS_EVMHOUMIANW = 445 , PPC_INS_EVMHOUSIAAW = 446 , PPC_INS_EVMHOUSIANW = 447 , PPC_INS_EVMRA = 448 , PPC_INS_EVMWHSMF = 449 , PPC_INS_EVMWHSMFA = 450 , PPC_INS_EVMWHSMI = 451 , PPC_INS_EVMWHSMIA = 452 , PPC_INS_EVMWHSSF = 453 , PPC_INS_EVMWHSSFA = 454 , PPC_INS_EVMWHUMI = 455 , PPC_INS_EVMWHUMIA = 456 , PPC_INS_EVMWLSMIAAW = 457 , PPC_INS_EVMWLSMIANW = 458 , PPC_INS_EVMWLSSIAAW = 459 , PPC_INS_EVMWLSSIANW = 460 , PPC_INS_EVMWLUMI = 461 , PPC_INS_EVMWLUMIA = 462 , PPC_INS_EVMWLUMIAAW = 463 , PPC_INS_EVMWLUMIANW = 464 , PPC_INS_EVMWLUSIAAW = 465 , PPC_INS_EVMWLUSIANW = 466 , PPC_INS_EVMWSMF = 467 , PPC_INS_EVMWSMFA = 468 , PPC_INS_EVMWSMFAA = 469 , PPC_INS_EVMWSMFAN = 470 , PPC_INS_EVMWSMI = 471 , PPC_INS_EVMWSMIA = 472 , PPC_INS_EVMWSMIAA = 473 , PPC_INS_EVMWSMIAN = 474 , PPC_INS_EVMWSSF = 475 , PPC_INS_EVMWSSFA = 476 , PPC_INS_EVMWSSFAA = 477 , PPC_INS_EVMWSSFAN = 478 , PPC_INS_EVMWUMI = 479 , PPC_INS_EVMWUMIA = 480 , PPC_INS_EVMWUMIAA = 481 , PPC_INS_EVMWUMIAN = 482 , PPC_INS_EVNAND = 483 , PPC_INS_EVNEG = 484 , PPC_INS_EVNOR = 485 , PPC_INS_EVOR = 486 , PPC_INS_EVORC = 487 , PPC_INS_EVRLW = 488 , PPC_INS_EVRLWI = 489 , PPC_INS_EVRNDW = 490 , PPC_INS_EVSEL = 491 , PPC_INS_EVSLW = 492 , PPC_INS_EVSLWI = 493 , PPC_INS_EVSPLATFI = 494 , PPC_INS_EVSPLATI = 495 , PPC_INS_EVSRWIS = 496 , PPC_INS_EVSRWIU = 497 , PPC_INS_EVSRWS = 498 , PPC_INS_EVSRWU = 499 , PPC_INS_EVSTDD = 500 , PPC_INS_EVSTDDX = 501 , PPC_INS_EVSTDH = 502 , PPC_INS_EVSTDHX = 503 , PPC_INS_EVSTDW = 504 , PPC_INS_EVSTDWX = 505 , PPC_INS_EVSTWHE = 506 , PPC_INS_EVSTWHEX = 507 , PPC_INS_EVSTWHO = 508 , PPC_INS_EVSTWHOX = 509 , PPC_INS_EVSTWWE = 510 , PPC_INS_EVSTWWEX = 511 , PPC_INS_EVSTWWO = 512 , PPC_INS_EVSTWWOX = 513 , PPC_INS_EVSUBFSMIAAW = 514 , PPC_INS_EVSUBFSSIAAW = 515 , PPC_INS_EVSUBFUMIAAW = 516 , PPC_INS_EVSUBFUSIAAW = 517 , PPC_INS_EVSUBFW = 518 , PPC_INS_EVSUBIFW = 519 , PPC_INS_EVXOR = 520 , PPC_INS_EXTLDI = 521 , PPC_INS_EXTLWI = 522 , PPC_INS_EXTRDI = 523 , PPC_INS_EXTRWI = 524 , PPC_INS_EXTSB = 525 , PPC_INS_EXTSH = 526 , PPC_INS_EXTSW = 527 , PPC_INS_EXTSWSLI = 528 , PPC_INS_FABS = 529 , PPC_INS_FADD = 530 , PPC_INS_FADDS = 531 , PPC_INS_FCFID = 532 , PPC_INS_FCFIDS = 533 , PPC_INS_FCFIDU = 534 , PPC_INS_FCFIDUS = 535 , PPC_INS_FCMPU = 536 , PPC_INS_FCPSGN = 537 , PPC_INS_FCTID = 538 , PPC_INS_FCTIDU = 539 , PPC_INS_FCTIDUZ = 540 , PPC_INS_FCTIDZ = 541 , PPC_INS_FCTIW = 542 , PPC_INS_FCTIWU = 543 , PPC_INS_FCTIWUZ = 544 , PPC_INS_FCTIWZ = 545 , PPC_INS_FDIV = 546 , PPC_INS_FDIVS = 547 , PPC_INS_FMADD = 548 , PPC_INS_FMADDS = 549 , PPC_INS_FMR = 550 , PPC_INS_FMSUB = 551 , PPC_INS_FMSUBS = 552 , PPC_INS_FMUL = 553 , PPC_INS_FMULS = 554 , PPC_INS_FNABS = 555 , PPC_INS_FNEG = 556 , PPC_INS_FNMADD = 557 , PPC_INS_FNMADDS = 558 , PPC_INS_FNMSUB = 559 , PPC_INS_FNMSUBS = 560 , PPC_INS_FRE = 561 , PPC_INS_FRES = 562 , PPC_INS_FRIM = 563 , PPC_INS_FRIN = 564 , PPC_INS_FRIP = 565 , PPC_INS_FRIZ = 566 , PPC_INS_FRSP = 567 , PPC_INS_FRSQRTE = 568 , PPC_INS_FRSQRTES = 569 , PPC_INS_FSEL = 570 , PPC_INS_FSQRT = 571 , PPC_INS_FSQRTS = 572 , PPC_INS_FSUB = 573 , PPC_INS_FSUBS = 574 , PPC_INS_FTDIV = 575 , PPC_INS_FTSQRT = 576 , PPC_INS_HRFID = 577 , PPC_INS_ICBI = 578 , PPC_INS_ICBIEP = 579 , PPC_INS_ICBLC = 580 , PPC_INS_ICBLQ = 581 , PPC_INS_ICBT = 582 , PPC_INS_ICBTLS = 583 , PPC_INS_ICCCI = 584 , PPC_INS_ICI = 585 , PPC_INS_INSLWI = 586 , PPC_INS_INSRDI = 587 , PPC_INS_INSRWI = 588 , PPC_INS_ISEL = 589 , PPC_INS_ISYNC = 590 , PPC_INS_LA = 591 , PPC_INS_LBARX = 592 , PPC_INS_LBEPX = 593 , PPC_INS_LBZ = 594 , PPC_INS_LBZCIX = 595 , PPC_INS_LBZU = 596 , PPC_INS_LBZUX = 597 , PPC_INS_LBZX = 598 , PPC_INS_LD = 599 , PPC_INS_LDARX = 600 , PPC_INS_LDAT = 601 , PPC_INS_LDBRX = 602 , PPC_INS_LDCIX = 603 , PPC_INS_LDMX = 604 , PPC_INS_LDU = 605 , PPC_INS_LDUX = 606 , PPC_INS_LDX = 607 , PPC_INS_LFD = 608 , PPC_INS_LFDEPX = 609 , PPC_INS_LFDU = 610 , PPC_INS_LFDUX = 611 , PPC_INS_LFDX = 612 , PPC_INS_LFIWAX = 613 , PPC_INS_LFIWZX = 614 , PPC_INS_LFS = 615 , PPC_INS_LFSU = 616 , PPC_INS_LFSUX = 617 , PPC_INS_LFSX = 618 , PPC_INS_LHA = 619 , PPC_INS_LHARX = 620 , PPC_INS_LHAU = 621 , PPC_INS_LHAUX = 622 , PPC_INS_LHAX = 623 , PPC_INS_LHBRX = 624 , PPC_INS_LHEPX = 625 , PPC_INS_LHZ = 626 , PPC_INS_LHZCIX = 627 , PPC_INS_LHZU = 628 , PPC_INS_LHZUX = 629 , PPC_INS_LHZX = 630 , PPC_INS_LI = 631 , PPC_INS_LIS = 632 , PPC_INS_LMW = 633 , PPC_INS_LNIA = 634 , PPC_INS_LSWI = 635 , PPC_INS_LVEBX = 636 , PPC_INS_LVEHX = 637 , PPC_INS_LVEWX = 638 , PPC_INS_LVSL = 639 , PPC_INS_LVSR = 640 , PPC_INS_LVX = 641 , PPC_INS_LVXL = 642 , PPC_INS_LWA = 643 , PPC_INS_LWARX = 644 , PPC_INS_LWAT = 645 , PPC_INS_LWAUX = 646 , PPC_INS_LWAX = 647 , PPC_INS_LWBRX = 648 , PPC_INS_LWEPX = 649 , PPC_INS_LWSYNC = 650 , PPC_INS_LWZ = 651 , PPC_INS_LWZCIX = 652 , PPC_INS_LWZU = 653 , PPC_INS_LWZUX = 654 , PPC_INS_LWZX = 655 , PPC_INS_LXSD = 656 , PPC_INS_LXSDX = 657 , PPC_INS_LXSIBZX = 658 , PPC_INS_LXSIHZX = 659 , PPC_INS_LXSIWAX = 660 , PPC_INS_LXSIWZX = 661 , PPC_INS_LXSSP = 662 , PPC_INS_LXSSPX = 663 , PPC_INS_LXV = 664 , PPC_INS_LXVB16X = 665 , PPC_INS_LXVD2X = 666 , PPC_INS_LXVDSX = 667 , PPC_INS_LXVH8X = 668 , PPC_INS_LXVL = 669 , PPC_INS_LXVLL = 670 , PPC_INS_LXVW4X = 671 , PPC_INS_LXVWSX = 672 , PPC_INS_LXVX = 673 , PPC_INS_MADDHD = 674 , PPC_INS_MADDHDU = 675 , PPC_INS_MADDLD = 676 , PPC_INS_MBAR = 677 , PPC_INS_MCRF = 678 , PPC_INS_MCRFS = 679 , PPC_INS_MCRXRX = 680 , PPC_INS_MFAMR = 681 , PPC_INS_MFASR = 682 , PPC_INS_MFBHRBE = 683 , PPC_INS_MFBR0 = 684 , PPC_INS_MFBR1 = 685 , PPC_INS_MFBR2 = 686 , PPC_INS_MFBR3 = 687 , PPC_INS_MFBR4 = 688 , PPC_INS_MFBR5 = 689 , PPC_INS_MFBR6 = 690 , PPC_INS_MFBR7 = 691 , PPC_INS_MFCFAR = 692 , PPC_INS_MFCR = 693 , PPC_INS_MFCTR = 694 , PPC_INS_MFDAR = 695 , PPC_INS_MFDBATL = 696 , PPC_INS_MFDBATU = 697 , PPC_INS_MFDCCR = 698 , PPC_INS_MFDCR = 699 , PPC_INS_MFDEAR = 700 , PPC_INS_MFDEC = 701 , PPC_INS_MFDSCR = 702 , PPC_INS_MFDSISR = 703 , PPC_INS_MFESR = 704 , PPC_INS_MFFPRD = 705 , PPC_INS_MFFS = 706 , PPC_INS_MFFSCDRN = 707 , PPC_INS_MFFSCDRNI = 708 , PPC_INS_MFFSCE = 709 , PPC_INS_MFFSCRN = 710 , PPC_INS_MFFSCRNI = 711 , PPC_INS_MFFSL = 712 , PPC_INS_MFIBATL = 713 , PPC_INS_MFIBATU = 714 , PPC_INS_MFICCR = 715 , PPC_INS_MFLR = 716 , PPC_INS_MFMSR = 717 , PPC_INS_MFOCRF = 718 , PPC_INS_MFPID = 719 , PPC_INS_MFPMR = 720 , PPC_INS_MFPVR = 721 , PPC_INS_MFRTCL = 722 , PPC_INS_MFRTCU = 723 , PPC_INS_MFSDR1 = 724 , PPC_INS_MFSPEFSCR = 725 , PPC_INS_MFSPR = 726 , PPC_INS_MFSPRG = 727 , PPC_INS_MFSPRG0 = 728 , PPC_INS_MFSPRG1 = 729 , PPC_INS_MFSPRG2 = 730 , PPC_INS_MFSPRG3 = 731 , PPC_INS_MFSPRG4 = 732 , PPC_INS_MFSPRG5 = 733 , PPC_INS_MFSPRG6 = 734 , PPC_INS_MFSPRG7 = 735 , PPC_INS_MFSR = 736 , PPC_INS_MFSRIN = 737 , PPC_INS_MFSRR0 = 738 , PPC_INS_MFSRR1 = 739 , PPC_INS_MFSRR2 = 740 , PPC_INS_MFSRR3 = 741 , PPC_INS_MFTB = 742 , PPC_INS_MFTBHI = 743 , PPC_INS_MFTBL = 744 , PPC_INS_MFTBLO = 745 , PPC_INS_MFTBU = 746 , PPC_INS_MFTCR = 747 , PPC_INS_MFVRD = 748 , PPC_INS_MFVRSAVE = 749 , PPC_INS_MFVSCR = 750 , PPC_INS_MFVSRD = 751 , PPC_INS_MFVSRLD = 752 , PPC_INS_MFVSRWZ = 753 , PPC_INS_MFXER = 754 , PPC_INS_MODSD = 755 , PPC_INS_MODSW = 756 , PPC_INS_MODUD = 757 , PPC_INS_MODUW = 758 , PPC_INS_MR = 759 , PPC_INS_MSGSYNC = 760 , PPC_INS_MSYNC = 761 , PPC_INS_MTAMR = 762 , PPC_INS_MTASR = 763 , PPC_INS_MTBR0 = 764 , PPC_INS_MTBR1 = 765 , PPC_INS_MTBR2 = 766 , PPC_INS_MTBR3 = 767 , PPC_INS_MTBR4 = 768 , PPC_INS_MTBR5 = 769 , PPC_INS_MTBR6 = 770 , PPC_INS_MTBR7 = 771 , PPC_INS_MTCFAR = 772 , PPC_INS_MTCR = 773 , PPC_INS_MTCRF = 774 , PPC_INS_MTCTR = 775 , PPC_INS_MTDAR = 776 , PPC_INS_MTDBATL = 777 , PPC_INS_MTDBATU = 778 , PPC_INS_MTDCCR = 779 , PPC_INS_MTDCR = 780 , PPC_INS_MTDEAR = 781 , PPC_INS_MTDEC = 782 , PPC_INS_MTDSCR = 783 , PPC_INS_MTDSISR = 784 , PPC_INS_MTESR = 785 , PPC_INS_MTFSB0 = 786 , PPC_INS_MTFSB1 = 787 , PPC_INS_MTFSF = 788 , PPC_INS_MTFSFI = 789 , PPC_INS_MTIBATL = 790 , PPC_INS_MTIBATU = 791 , PPC_INS_MTICCR = 792 , PPC_INS_MTLR = 793 , PPC_INS_MTMSR = 794 , PPC_INS_MTMSRD = 795 , PPC_INS_MTOCRF = 796 , PPC_INS_MTPID = 797 , PPC_INS_MTPMR = 798 , PPC_INS_MTSDR1 = 799 , PPC_INS_MTSPEFSCR = 800 , PPC_INS_MTSPR = 801 , PPC_INS_MTSPRG = 802 , PPC_INS_MTSPRG0 = 803 , PPC_INS_MTSPRG1 = 804 , PPC_INS_MTSPRG2 = 805 , PPC_INS_MTSPRG3 = 806 , PPC_INS_MTSPRG4 = 807 , PPC_INS_MTSPRG5 = 808 , PPC_INS_MTSPRG6 = 809 , PPC_INS_MTSPRG7 = 810 , PPC_INS_MTSR = 811 , PPC_INS_MTSRIN = 812 , PPC_INS_MTSRR0 = 813 , PPC_INS_MTSRR1 = 814 , PPC_INS_MTSRR2 = 815 , PPC_INS_MTSRR3 = 816 , PPC_INS_MTTBHI = 817 , PPC_INS_MTTBL = 818 , PPC_INS_MTTBLO = 819 , PPC_INS_MTTBU = 820 , PPC_INS_MTTCR = 821 , PPC_INS_MTVRSAVE = 822 , PPC_INS_MTVSCR = 823 , PPC_INS_MTVSRD = 824 , PPC_INS_MTVSRDD = 825 , PPC_INS_MTVSRWA = 826 , PPC_INS_MTVSRWS = 827 , PPC_INS_MTVSRWZ = 828 , PPC_INS_MTXER = 829 , PPC_INS_MULHD = 830 , PPC_INS_MULHDU = 831 , PPC_INS_MULHW = 832 , PPC_INS_MULHWU = 833 , PPC_INS_MULLD = 834 , PPC_INS_MULLI = 835 , PPC_INS_MULLW = 836 , PPC_INS_NAND = 837 , PPC_INS_NAP = 838 , PPC_INS_NEG = 839 , PPC_INS_NOP = 840 , PPC_INS_NOR = 841 , PPC_INS_NOT = 842 , PPC_INS_OR = 843 , PPC_INS_ORC = 844 , PPC_INS_ORI = 845 , PPC_INS_ORIS = 846 , PPC_INS_PASTE = 847 , PPC_INS_PASTE_LAST = 848 , PPC_INS_POPCNTB = 849 , PPC_INS_POPCNTD = 850 , PPC_INS_POPCNTW = 851 , PPC_INS_PTESYNC = 852 , PPC_INS_QVALIGNI = 853 , PPC_INS_QVESPLATI = 854 , PPC_INS_QVFABS = 855 , PPC_INS_QVFADD = 856 , PPC_INS_QVFADDS = 857 , PPC_INS_QVFAND = 858 , PPC_INS_QVFANDC = 859 , PPC_INS_QVFCFID = 860 , PPC_INS_QVFCFIDS = 861 , PPC_INS_QVFCFIDU = 862 , PPC_INS_QVFCFIDUS = 863 , PPC_INS_QVFCLR = 864 , PPC_INS_QVFCMPEQ = 865 , PPC_INS_QVFCMPGT = 866 , PPC_INS_QVFCMPLT = 867 , PPC_INS_QVFCPSGN = 868 , PPC_INS_QVFCTFB = 869 , PPC_INS_QVFCTID = 870 , PPC_INS_QVFCTIDU = 871 , PPC_INS_QVFCTIDUZ = 872 , PPC_INS_QVFCTIDZ = 873 , PPC_INS_QVFCTIW = 874 , PPC_INS_QVFCTIWU = 875 , PPC_INS_QVFCTIWUZ = 876 , PPC_INS_QVFCTIWZ = 877 , PPC_INS_QVFEQU = 878 , PPC_INS_QVFLOGICAL = 879 , PPC_INS_QVFMADD = 880 , PPC_INS_QVFMADDS = 881 , PPC_INS_QVFMR = 882 , PPC_INS_QVFMSUB = 883 , PPC_INS_QVFMSUBS = 884 , PPC_INS_QVFMUL = 885 , PPC_INS_QVFMULS = 886 , PPC_INS_QVFNABS = 887 , PPC_INS_QVFNAND = 888 , PPC_INS_QVFNEG = 889 , PPC_INS_QVFNMADD = 890 , PPC_INS_QVFNMADDS = 891 , PPC_INS_QVFNMSUB = 892 , PPC_INS_QVFNMSUBS = 893 , PPC_INS_QVFNOR = 894 , PPC_INS_QVFNOT = 895 , PPC_INS_QVFOR = 896 , PPC_INS_QVFORC = 897 , PPC_INS_QVFPERM = 898 , PPC_INS_QVFRE = 899 , PPC_INS_QVFRES = 900 , PPC_INS_QVFRIM = 901 , PPC_INS_QVFRIN = 902 , PPC_INS_QVFRIP = 903 , PPC_INS_QVFRIZ = 904 , PPC_INS_QVFRSP = 905 , PPC_INS_QVFRSQRTE = 906 , PPC_INS_QVFRSQRTES = 907 , PPC_INS_QVFSEL = 908 , PPC_INS_QVFSET = 909 , PPC_INS_QVFSUB = 910 , PPC_INS_QVFSUBS = 911 , PPC_INS_QVFTSTNAN = 912 , PPC_INS_QVFXMADD = 913 , PPC_INS_QVFXMADDS = 914 , PPC_INS_QVFXMUL = 915 , PPC_INS_QVFXMULS = 916 , PPC_INS_QVFXOR = 917 , PPC_INS_QVFXXCPNMADD = 918 , PPC_INS_QVFXXCPNMADDS = 919 , PPC_INS_QVFXXMADD = 920 , PPC_INS_QVFXXMADDS = 921 , PPC_INS_QVFXXNPMADD = 922 , PPC_INS_QVFXXNPMADDS = 923 , PPC_INS_QVGPCI = 924 , PPC_INS_QVLFCDUX = 925 , PPC_INS_QVLFCDUXA = 926 , PPC_INS_QVLFCDX = 927 , PPC_INS_QVLFCDXA = 928 , PPC_INS_QVLFCSUX = 929 , PPC_INS_QVLFCSUXA = 930 , PPC_INS_QVLFCSX = 931 , PPC_INS_QVLFCSXA = 932 , PPC_INS_QVLFDUX = 933 , PPC_INS_QVLFDUXA = 934 , PPC_INS_QVLFDX = 935 , PPC_INS_QVLFDXA = 936 , PPC_INS_QVLFIWAX = 937 , PPC_INS_QVLFIWAXA = 938 , PPC_INS_QVLFIWZX = 939 , PPC_INS_QVLFIWZXA = 940 , PPC_INS_QVLFSUX = 941 , PPC_INS_QVLFSUXA = 942 , PPC_INS_QVLFSX = 943 , PPC_INS_QVLFSXA = 944 , PPC_INS_QVLPCLDX = 945 , PPC_INS_QVLPCLSX = 946 , PPC_INS_QVLPCRDX = 947 , PPC_INS_QVLPCRSX = 948 , PPC_INS_QVSTFCDUX = 949 , PPC_INS_QVSTFCDUXA = 950 , PPC_INS_QVSTFCDUXI = 951 , PPC_INS_QVSTFCDUXIA = 952 , PPC_INS_QVSTFCDX = 953 , PPC_INS_QVSTFCDXA = 954 , PPC_INS_QVSTFCDXI = 955 , PPC_INS_QVSTFCDXIA = 956 , PPC_INS_QVSTFCSUX = 957 , PPC_INS_QVSTFCSUXA = 958 , PPC_INS_QVSTFCSUXI = 959 , PPC_INS_QVSTFCSUXIA = 960 , PPC_INS_QVSTFCSX = 961 , PPC_INS_QVSTFCSXA = 962 , PPC_INS_QVSTFCSXI = 963 , PPC_INS_QVSTFCSXIA = 964 , PPC_INS_QVSTFDUX = 965 , PPC_INS_QVSTFDUXA = 966 , PPC_INS_QVSTFDUXI = 967 , PPC_INS_QVSTFDUXIA = 968 , PPC_INS_QVSTFDX = 969 , PPC_INS_QVSTFDXA = 970 , PPC_INS_QVSTFDXI = 971 , PPC_INS_QVSTFDXIA = 972 , PPC_INS_QVSTFIWX = 973 , PPC_INS_QVSTFIWXA = 974 , PPC_INS_QVSTFSUX = 975 , PPC_INS_QVSTFSUXA = 976 , PPC_INS_QVSTFSUXI = 977 , PPC_INS_QVSTFSUXIA = 978 , PPC_INS_QVSTFSX = 979 , PPC_INS_QVSTFSXA = 980 , PPC_INS_QVSTFSXI = 981 , PPC_INS_QVSTFSXIA = 982 , PPC_INS_RFCI = 983 , PPC_INS_RFDI = 984 , PPC_INS_RFEBB = 985 , PPC_INS_RFI = 986 , PPC_INS_RFID = 987 , PPC_INS_RFMCI = 988 , PPC_INS_RLDCL = 989 , PPC_INS_RLDCR = 990 , PPC_INS_RLDIC = 991 , PPC_INS_RLDICL = 992 , PPC_INS_RLDICR = 993 , PPC_INS_RLDIMI = 994 , PPC_INS_RLWIMI = 995 , PPC_INS_RLWINM = 996 , PPC_INS_RLWNM = 997 , PPC_INS_ROTLD = 998 , PPC_INS_ROTLDI = 999 , PPC_INS_ROTLW = 1000 , PPC_INS_ROTLWI = 1001 , PPC_INS_ROTRDI = 1002 , PPC_INS_ROTRWI = 1003 , PPC_INS_SC = 1004 , PPC_INS_SETB = 1005 , PPC_INS_SLBIA = 1006 , PPC_INS_SLBIE = 1007 , PPC_INS_SLBIEG = 1008 , PPC_INS_SLBMFEE = 1009 , PPC_INS_SLBMFEV = 1010 , PPC_INS_SLBMTE = 1011 , PPC_INS_SLBSYNC = 1012 , PPC_INS_SLD = 1013 , PPC_INS_SLDI = 1014 , PPC_INS_SLW = 1015 , PPC_INS_SLWI = 1016 , PPC_INS_SRAD = 1017 , PPC_INS_SRADI = 1018 , PPC_INS_SRAW = 1019 , PPC_INS_SRAWI = 1020 , PPC_INS_SRD = 1021 , PPC_INS_SRDI = 1022 , PPC_INS_SRW = 1023 , PPC_INS_SRWI = 1024 , PPC_INS_STB = 1025 , PPC_INS_STBCIX = 1026 , PPC_INS_STBCX = 1027 , PPC_INS_STBEPX = 1028 , PPC_INS_STBU = 1029 , PPC_INS_STBUX = 1030 , PPC_INS_STBX = 1031 , PPC_INS_STD = 1032 , PPC_INS_STDAT = 1033 , PPC_INS_STDBRX = 1034 , PPC_INS_STDCIX = 1035 , PPC_INS_STDCX = 1036 , PPC_INS_STDU = 1037 , PPC_INS_STDUX = 1038 , PPC_INS_STDX = 1039 , PPC_INS_STFD = 1040 , PPC_INS_STFDEPX = 1041 , PPC_INS_STFDU = 1042 , PPC_INS_STFDUX = 1043 , PPC_INS_STFDX = 1044 , PPC_INS_STFIWX = 1045 , PPC_INS_STFS = 1046 , PPC_INS_STFSU = 1047 , PPC_INS_STFSUX = 1048 , PPC_INS_STFSX = 1049 , PPC_INS_STH = 1050 , PPC_INS_STHBRX = 1051 , PPC_INS_STHCIX = 1052 , PPC_INS_STHCX = 1053 , PPC_INS_STHEPX = 1054 , PPC_INS_STHU = 1055 , PPC_INS_STHUX = 1056 , PPC_INS_STHX = 1057 , PPC_INS_STMW = 1058 , PPC_INS_STOP = 1059 , PPC_INS_STSWI = 1060 , PPC_INS_STVEBX = 1061 , PPC_INS_STVEHX = 1062 , PPC_INS_STVEWX = 1063 , PPC_INS_STVX = 1064 , PPC_INS_STVXL = 1065 , PPC_INS_STW = 1066 , PPC_INS_STWAT = 1067 , PPC_INS_STWBRX = 1068 , PPC_INS_STWCIX = 1069 , PPC_INS_STWCX = 1070 , PPC_INS_STWEPX = 1071 , PPC_INS_STWU = 1072 , PPC_INS_STWUX = 1073 , PPC_INS_STWX = 1074 , PPC_INS_STXSD = 1075 , PPC_INS_STXSDX = 1076 , PPC_INS_STXSIBX = 1077 , PPC_INS_STXSIHX = 1078 , PPC_INS_STXSIWX = 1079 , PPC_INS_STXSSP = 1080 , PPC_INS_STXSSPX = 1081 , PPC_INS_STXV = 1082 , PPC_INS_STXVB16X = 1083 , PPC_INS_STXVD2X = 1084 , PPC_INS_STXVH8X = 1085 , PPC_INS_STXVL = 1086 , PPC_INS_STXVLL = 1087 , PPC_INS_STXVW4X = 1088 , PPC_INS_STXVX = 1089 , PPC_INS_SUB = 1090 , PPC_INS_SUBC = 1091 , PPC_INS_SUBF = 1092 , PPC_INS_SUBFC = 1093 , PPC_INS_SUBFE = 1094 , PPC_INS_SUBFIC = 1095 , PPC_INS_SUBFME = 1096 , PPC_INS_SUBFZE = 1097 , PPC_INS_SUBI = 1098 , PPC_INS_SUBIC = 1099 , PPC_INS_SUBIS = 1100 , PPC_INS_SUBPCIS = 1101 , PPC_INS_SYNC = 1102 , PPC_INS_TABORT = 1103 , PPC_INS_TABORTDC = 1104 , PPC_INS_TABORTDCI = 1105 , PPC_INS_TABORTWC = 1106 , PPC_INS_TABORTWCI = 1107 , PPC_INS_TBEGIN = 1108 , PPC_INS_TCHECK = 1109 , PPC_INS_TD = 1110 , PPC_INS_TDEQ = 1111 , PPC_INS_TDEQI = 1112 , PPC_INS_TDGE = 1113 , PPC_INS_TDGEI = 1114 , PPC_INS_TDGT = 1115 , PPC_INS_TDGTI = 1116 , PPC_INS_TDI = 1117 , PPC_INS_TDLE = 1118 , PPC_INS_TDLEI = 1119 , PPC_INS_TDLGE = 1120 , PPC_INS_TDLGEI = 1121 , PPC_INS_TDLGT = 1122 , PPC_INS_TDLGTI = 1123 , PPC_INS_TDLLE = 1124 , PPC_INS_TDLLEI = 1125 , PPC_INS_TDLLT = 1126 , PPC_INS_TDLLTI = 1127 , PPC_INS_TDLNG = 1128 , PPC_INS_TDLNGI = 1129 , PPC_INS_TDLNL = 1130 , PPC_INS_TDLNLI = 1131 , PPC_INS_TDLT = 1132 , PPC_INS_TDLTI = 1133 , PPC_INS_TDNE = 1134 , PPC_INS_TDNEI = 1135 , PPC_INS_TDNG = 1136 , PPC_INS_TDNGI = 1137 , PPC_INS_TDNL = 1138 , PPC_INS_TDNLI = 1139 , PPC_INS_TDU = 1140 , PPC_INS_TDUI = 1141 , PPC_INS_TEND = 1142 , PPC_INS_TLBIA = 1143 , PPC_INS_TLBIE = 1144 , PPC_INS_TLBIEL = 1145 , PPC_INS_TLBIVAX = 1146 , PPC_INS_TLBLD = 1147 , PPC_INS_TLBLI = 1148 , PPC_INS_TLBRE = 1149 , PPC_INS_TLBREHI = 1150 , PPC_INS_TLBRELO = 1151 , PPC_INS_TLBSX = 1152 , PPC_INS_TLBSYNC = 1153 , PPC_INS_TLBWE = 1154 , PPC_INS_TLBWEHI = 1155 , PPC_INS_TLBWELO = 1156 , PPC_INS_TRAP = 1157 , PPC_INS_TRECHKPT = 1158 , PPC_INS_TRECLAIM = 1159 , PPC_INS_TSR = 1160 , PPC_INS_TW = 1161 , PPC_INS_TWEQ = 1162 , PPC_INS_TWEQI = 1163 , PPC_INS_TWGE = 1164 , PPC_INS_TWGEI = 1165 , PPC_INS_TWGT = 1166 , PPC_INS_TWGTI = 1167 , PPC_INS_TWI = 1168 , PPC_INS_TWLE = 1169 , PPC_INS_TWLEI = 1170 , PPC_INS_TWLGE = 1171 , PPC_INS_TWLGEI = 1172 , PPC_INS_TWLGT = 1173 , PPC_INS_TWLGTI = 1174 , PPC_INS_TWLLE = 1175 , PPC_INS_TWLLEI = 1176 , PPC_INS_TWLLT = 1177 , PPC_INS_TWLLTI = 1178 , PPC_INS_TWLNG = 1179 , PPC_INS_TWLNGI = 1180 , PPC_INS_TWLNL = 1181 , PPC_INS_TWLNLI = 1182 , PPC_INS_TWLT = 1183 , PPC_INS_TWLTI = 1184 , PPC_INS_TWNE = 1185 , PPC_INS_TWNEI = 1186 , PPC_INS_TWNG = 1187 , PPC_INS_TWNGI = 1188 , PPC_INS_TWNL = 1189 , PPC_INS_TWNLI = 1190 , PPC_INS_TWU = 1191 , PPC_INS_TWUI = 1192 , PPC_INS_VABSDUB = 1193 , PPC_INS_VABSDUH = 1194 , PPC_INS_VABSDUW = 1195 , PPC_INS_VADDCUQ = 1196 , PPC_INS_VADDCUW = 1197 , PPC_INS_VADDECUQ = 1198 , PPC_INS_VADDEUQM = 1199 , PPC_INS_VADDFP = 1200 , PPC_INS_VADDSBS = 1201 , PPC_INS_VADDSHS = 1202 , PPC_INS_VADDSWS = 1203 , PPC_INS_VADDUBM = 1204 , PPC_INS_VADDUBS = 1205 , PPC_INS_VADDUDM = 1206 , PPC_INS_VADDUHM = 1207 , PPC_INS_VADDUHS = 1208 , PPC_INS_VADDUQM = 1209 , PPC_INS_VADDUWM = 1210 , PPC_INS_VADDUWS = 1211 , PPC_INS_VAND = 1212 , PPC_INS_VANDC = 1213 , PPC_INS_VAVGSB = 1214 , PPC_INS_VAVGSH = 1215 , PPC_INS_VAVGSW = 1216 , PPC_INS_VAVGUB = 1217 , PPC_INS_VAVGUH = 1218 , PPC_INS_VAVGUW = 1219 , PPC_INS_VBPERMD = 1220 , PPC_INS_VBPERMQ = 1221 , PPC_INS_VCFSX = 1222 , PPC_INS_VCFUX = 1223 , PPC_INS_VCIPHER = 1224 , PPC_INS_VCIPHERLAST = 1225 , PPC_INS_VCLZB = 1226 , PPC_INS_VCLZD = 1227 , PPC_INS_VCLZH = 1228 , PPC_INS_VCLZLSBB = 1229 , PPC_INS_VCLZW = 1230 , PPC_INS_VCMPBFP = 1231 , PPC_INS_VCMPEQFP = 1232 , PPC_INS_VCMPEQUB = 1233 , PPC_INS_VCMPEQUD = 1234 , PPC_INS_VCMPEQUH = 1235 , PPC_INS_VCMPEQUW = 1236 , PPC_INS_VCMPGEFP = 1237 , PPC_INS_VCMPGTFP = 1238 , PPC_INS_VCMPGTSB = 1239 , PPC_INS_VCMPGTSD = 1240 , PPC_INS_VCMPGTSH = 1241 , PPC_INS_VCMPGTSW = 1242 , PPC_INS_VCMPGTUB = 1243 , PPC_INS_VCMPGTUD = 1244 , PPC_INS_VCMPGTUH = 1245 , PPC_INS_VCMPGTUW = 1246 , PPC_INS_VCMPNEB = 1247 , PPC_INS_VCMPNEH = 1248 , PPC_INS_VCMPNEW = 1249 , PPC_INS_VCMPNEZB = 1250 , PPC_INS_VCMPNEZH = 1251 , PPC_INS_VCMPNEZW = 1252 , PPC_INS_VCTSXS = 1253 , PPC_INS_VCTUXS = 1254 , PPC_INS_VCTZB = 1255 , PPC_INS_VCTZD = 1256 , PPC_INS_VCTZH = 1257 , PPC_INS_VCTZLSBB = 1258 , PPC_INS_VCTZW = 1259 , PPC_INS_VEQV = 1260 , PPC_INS_VEXPTEFP = 1261 , PPC_INS_VEXTRACTD = 1262 , PPC_INS_VEXTRACTUB = 1263 , PPC_INS_VEXTRACTUH = 1264 , PPC_INS_VEXTRACTUW = 1265 , PPC_INS_VEXTSB2D = 1266 , PPC_INS_VEXTSB2W = 1267 , PPC_INS_VEXTSH2D = 1268 , PPC_INS_VEXTSH2W = 1269 , PPC_INS_VEXTSW2D = 1270 , PPC_INS_VEXTUBLX = 1271 , PPC_INS_VEXTUBRX = 1272 , PPC_INS_VEXTUHLX = 1273 , PPC_INS_VEXTUHRX = 1274 , PPC_INS_VEXTUWLX = 1275 , PPC_INS_VEXTUWRX = 1276 , PPC_INS_VGBBD = 1277 , PPC_INS_VINSERTB = 1278 , PPC_INS_VINSERTD = 1279 , PPC_INS_VINSERTH = 1280 , PPC_INS_VINSERTW = 1281 , PPC_INS_VLOGEFP = 1282 , PPC_INS_VMADDFP = 1283 , PPC_INS_VMAXFP = 1284 , PPC_INS_VMAXSB = 1285 , PPC_INS_VMAXSD = 1286 , PPC_INS_VMAXSH = 1287 , PPC_INS_VMAXSW = 1288 , PPC_INS_VMAXUB = 1289 , PPC_INS_VMAXUD = 1290 , PPC_INS_VMAXUH = 1291 , PPC_INS_VMAXUW = 1292 , PPC_INS_VMHADDSHS = 1293 , PPC_INS_VMHRADDSHS = 1294 , PPC_INS_VMINFP = 1295 , PPC_INS_VMINSB = 1296 , PPC_INS_VMINSD = 1297 , PPC_INS_VMINSH = 1298 , PPC_INS_VMINSW = 1299 , PPC_INS_VMINUB = 1300 , PPC_INS_VMINUD = 1301 , PPC_INS_VMINUH = 1302 , PPC_INS_VMINUW = 1303 , PPC_INS_VMLADDUHM = 1304 , PPC_INS_VMR = 1305 , PPC_INS_VMRGEW = 1306 , PPC_INS_VMRGHB = 1307 , PPC_INS_VMRGHH = 1308 , PPC_INS_VMRGHW = 1309 , PPC_INS_VMRGLB = 1310 , PPC_INS_VMRGLH = 1311 , PPC_INS_VMRGLW = 1312 , PPC_INS_VMRGOW = 1313 , PPC_INS_VMSUMMBM = 1314 , PPC_INS_VMSUMSHM = 1315 , PPC_INS_VMSUMSHS = 1316 , PPC_INS_VMSUMUBM = 1317 , PPC_INS_VMSUMUHM = 1318 , PPC_INS_VMSUMUHS = 1319 , PPC_INS_VMUL10CUQ = 1320 , PPC_INS_VMUL10ECUQ = 1321 , PPC_INS_VMUL10EUQ = 1322 , PPC_INS_VMUL10UQ = 1323 , PPC_INS_VMULESB = 1324 , PPC_INS_VMULESH = 1325 , PPC_INS_VMULESW = 1326 , PPC_INS_VMULEUB = 1327 , PPC_INS_VMULEUH = 1328 , PPC_INS_VMULEUW = 1329 , PPC_INS_VMULOSB = 1330 , PPC_INS_VMULOSH = 1331 , PPC_INS_VMULOSW = 1332 , PPC_INS_VMULOUB = 1333 , PPC_INS_VMULOUH = 1334 , PPC_INS_VMULOUW = 1335 , PPC_INS_VMULUWM = 1336 , PPC_INS_VNAND = 1337 , PPC_INS_VNCIPHER = 1338 , PPC_INS_VNCIPHERLAST = 1339 , PPC_INS_VNEGD = 1340 , PPC_INS_VNEGW = 1341 , PPC_INS_VNMSUBFP = 1342 , PPC_INS_VNOR = 1343 , PPC_INS_VNOT = 1344 , PPC_INS_VOR = 1345 , PPC_INS_VORC = 1346 , PPC_INS_VPERM = 1347 , PPC_INS_VPERMR = 1348 , PPC_INS_VPERMXOR = 1349 , PPC_INS_VPKPX = 1350 , PPC_INS_VPKSDSS = 1351 , PPC_INS_VPKSDUS = 1352 , PPC_INS_VPKSHSS = 1353 , PPC_INS_VPKSHUS = 1354 , PPC_INS_VPKSWSS = 1355 , PPC_INS_VPKSWUS = 1356 , PPC_INS_VPKUDUM = 1357 , PPC_INS_VPKUDUS = 1358 , PPC_INS_VPKUHUM = 1359 , PPC_INS_VPKUHUS = 1360 , PPC_INS_VPKUWUM = 1361 , PPC_INS_VPKUWUS = 1362 , PPC_INS_VPMSUMB = 1363 , PPC_INS_VPMSUMD = 1364 , PPC_INS_VPMSUMH = 1365 , PPC_INS_VPMSUMW = 1366 , PPC_INS_VPOPCNTB = 1367 , PPC_INS_VPOPCNTD = 1368 , PPC_INS_VPOPCNTH = 1369 , PPC_INS_VPOPCNTW = 1370 , PPC_INS_VPRTYBD = 1371 , PPC_INS_VPRTYBQ = 1372 , PPC_INS_VPRTYBW = 1373 , PPC_INS_VREFP = 1374 , PPC_INS_VRFIM = 1375 , PPC_INS_VRFIN = 1376 , PPC_INS_VRFIP = 1377 , PPC_INS_VRFIZ = 1378 , PPC_INS_VRLB = 1379 , PPC_INS_VRLD = 1380 , PPC_INS_VRLDMI = 1381 , PPC_INS_VRLDNM = 1382 , PPC_INS_VRLH = 1383 , PPC_INS_VRLW = 1384 , PPC_INS_VRLWMI = 1385 , PPC_INS_VRLWNM = 1386 , PPC_INS_VRSQRTEFP = 1387 , PPC_INS_VSBOX = 1388 , PPC_INS_VSEL = 1389 , PPC_INS_VSHASIGMAD = 1390 , PPC_INS_VSHASIGMAW = 1391 , PPC_INS_VSL = 1392 , PPC_INS_VSLB = 1393 , PPC_INS_VSLD = 1394 , PPC_INS_VSLDOI = 1395 , PPC_INS_VSLH = 1396 , PPC_INS_VSLO = 1397 , PPC_INS_VSLV = 1398 , PPC_INS_VSLW = 1399 , PPC_INS_VSPLTB = 1400 , PPC_INS_VSPLTH = 1401 , PPC_INS_VSPLTISB = 1402 , PPC_INS_VSPLTISH = 1403 , PPC_INS_VSPLTISW = 1404 , PPC_INS_VSPLTW = 1405 , PPC_INS_VSR = 1406 , PPC_INS_VSRAB = 1407 , PPC_INS_VSRAD = 1408 , PPC_INS_VSRAH = 1409 , PPC_INS_VSRAW = 1410 , PPC_INS_VSRB = 1411 , PPC_INS_VSRD = 1412 , PPC_INS_VSRH = 1413 , PPC_INS_VSRO = 1414 , PPC_INS_VSRV = 1415 , PPC_INS_VSRW = 1416 , PPC_INS_VSUBCUQ = 1417 , PPC_INS_VSUBCUW = 1418 , PPC_INS_VSUBECUQ = 1419 , PPC_INS_VSUBEUQM = 1420 , PPC_INS_VSUBFP = 1421 , PPC_INS_VSUBSBS = 1422 , PPC_INS_VSUBSHS = 1423 , PPC_INS_VSUBSWS = 1424 , PPC_INS_VSUBUBM = 1425 , PPC_INS_VSUBUBS = 1426 , PPC_INS_VSUBUDM = 1427 , PPC_INS_VSUBUHM = 1428 , PPC_INS_VSUBUHS = 1429 , PPC_INS_VSUBUQM = 1430 , PPC_INS_VSUBUWM = 1431 , PPC_INS_VSUBUWS = 1432 , PPC_INS_VSUM2SWS = 1433 , PPC_INS_VSUM4SBS = 1434 , PPC_INS_VSUM4SHS = 1435 , PPC_INS_VSUM4UBS = 1436 , PPC_INS_VSUMSWS = 1437 , PPC_INS_VUPKHPX = 1438 , PPC_INS_VUPKHSB = 1439 , PPC_INS_VUPKHSH = 1440 , PPC_INS_VUPKHSW = 1441 , PPC_INS_VUPKLPX = 1442 , PPC_INS_VUPKLSB = 1443 , PPC_INS_VUPKLSH = 1444 , PPC_INS_VUPKLSW = 1445 , PPC_INS_VXOR = 1446 , PPC_INS_WAIT = 1447 , PPC_INS_WAITIMPL = 1448 , PPC_INS_WAITRSV = 1449 , PPC_INS_WRTEE = 1450 , PPC_INS_WRTEEI = 1451 , PPC_INS_XNOP = 1452 , PPC_INS_XOR = 1453 , PPC_INS_XORI = 1454 , PPC_INS_XORIS = 1455 , PPC_INS_XSABSDP = 1456 , PPC_INS_XSABSQP = 1457 , PPC_INS_XSADDDP = 1458 , PPC_INS_XSADDQP = 1459 , PPC_INS_XSADDQPO = 1460 , PPC_INS_XSADDSP = 1461 , PPC_INS_XSCMPEQDP = 1462 , PPC_INS_XSCMPEXPDP = 1463 , PPC_INS_XSCMPEXPQP = 1464 , PPC_INS_XSCMPGEDP = 1465 , PPC_INS_XSCMPGTDP = 1466 , PPC_INS_XSCMPODP = 1467 , PPC_INS_XSCMPOQP = 1468 , PPC_INS_XSCMPUDP = 1469 , PPC_INS_XSCMPUQP = 1470 , PPC_INS_XSCPSGNDP = 1471 , PPC_INS_XSCPSGNQP = 1472 , PPC_INS_XSCVDPHP = 1473 , PPC_INS_XSCVDPQP = 1474 , PPC_INS_XSCVDPSP = 1475 , PPC_INS_XSCVDPSPN = 1476 , PPC_INS_XSCVDPSXDS = 1477 , PPC_INS_XSCVDPSXWS = 1478 , PPC_INS_XSCVDPUXDS = 1479 , PPC_INS_XSCVDPUXWS = 1480 , PPC_INS_XSCVHPDP = 1481 , PPC_INS_XSCVQPDP = 1482 , PPC_INS_XSCVQPDPO = 1483 , PPC_INS_XSCVQPSDZ = 1484 , PPC_INS_XSCVQPSWZ = 1485 , PPC_INS_XSCVQPUDZ = 1486 , PPC_INS_XSCVQPUWZ = 1487 , PPC_INS_XSCVSDQP = 1488 , PPC_INS_XSCVSPDP = 1489 , PPC_INS_XSCVSPDPN = 1490 , PPC_INS_XSCVSXDDP = 1491 , PPC_INS_XSCVSXDSP = 1492 , PPC_INS_XSCVUDQP = 1493 , PPC_INS_XSCVUXDDP = 1494 , PPC_INS_XSCVUXDSP = 1495 , PPC_INS_XSDIVDP = 1496 , PPC_INS_XSDIVQP = 1497 , PPC_INS_XSDIVQPO = 1498 , PPC_INS_XSDIVSP = 1499 , PPC_INS_XSIEXPDP = 1500 , PPC_INS_XSIEXPQP = 1501 , PPC_INS_XSMADDADP = 1502 , PPC_INS_XSMADDASP = 1503 , PPC_INS_XSMADDMDP = 1504 , PPC_INS_XSMADDMSP = 1505 , PPC_INS_XSMADDQP = 1506 , PPC_INS_XSMADDQPO = 1507 , PPC_INS_XSMAXCDP = 1508 , PPC_INS_XSMAXDP = 1509 , PPC_INS_XSMAXJDP = 1510 , PPC_INS_XSMINCDP = 1511 , PPC_INS_XSMINDP = 1512 , PPC_INS_XSMINJDP = 1513 , PPC_INS_XSMSUBADP = 1514 , PPC_INS_XSMSUBASP = 1515 , PPC_INS_XSMSUBMDP = 1516 , PPC_INS_XSMSUBMSP = 1517 , PPC_INS_XSMSUBQP = 1518 , PPC_INS_XSMSUBQPO = 1519 , PPC_INS_XSMULDP = 1520 , PPC_INS_XSMULQP = 1521 , PPC_INS_XSMULQPO = 1522 , PPC_INS_XSMULSP = 1523 , PPC_INS_XSNABSDP = 1524 , PPC_INS_XSNABSQP = 1525 , PPC_INS_XSNEGDP = 1526 , PPC_INS_XSNEGQP = 1527 , PPC_INS_XSNMADDADP = 1528 , PPC_INS_XSNMADDASP = 1529 , PPC_INS_XSNMADDMDP = 1530 , PPC_INS_XSNMADDMSP = 1531 , PPC_INS_XSNMADDQP = 1532 , PPC_INS_XSNMADDQPO = 1533 , PPC_INS_XSNMSUBADP = 1534 , PPC_INS_XSNMSUBASP = 1535 , PPC_INS_XSNMSUBMDP = 1536 , PPC_INS_XSNMSUBMSP = 1537 , PPC_INS_XSNMSUBQP = 1538 , PPC_INS_XSNMSUBQPO = 1539 , PPC_INS_XSRDPI = 1540 , PPC_INS_XSRDPIC = 1541 , PPC_INS_XSRDPIM = 1542 , PPC_INS_XSRDPIP = 1543 , PPC_INS_XSRDPIZ = 1544 , PPC_INS_XSREDP = 1545 , PPC_INS_XSRESP = 1546 , PPC_INS_XSRQPI = 1547 , PPC_INS_XSRQPIX = 1548 , PPC_INS_XSRQPXP = 1549 , PPC_INS_XSRSP = 1550 , PPC_INS_XSRSQRTEDP = 1551 , PPC_INS_XSRSQRTESP = 1552 , PPC_INS_XSSQRTDP = 1553 , PPC_INS_XSSQRTQP = 1554 , PPC_INS_XSSQRTQPO = 1555 , PPC_INS_XSSQRTSP = 1556 , PPC_INS_XSSUBDP = 1557 , PPC_INS_XSSUBQP = 1558 , PPC_INS_XSSUBQPO = 1559 , PPC_INS_XSSUBSP = 1560 , PPC_INS_XSTDIVDP = 1561 , PPC_INS_XSTSQRTDP = 1562 , PPC_INS_XSTSTDCDP = 1563 , PPC_INS_XSTSTDCQP = 1564 , PPC_INS_XSTSTDCSP = 1565 , PPC_INS_XSXEXPDP = 1566 , PPC_INS_XSXEXPQP = 1567 , PPC_INS_XSXSIGDP = 1568 , PPC_INS_XSXSIGQP = 1569 , PPC_INS_XVABSDP = 1570 , PPC_INS_XVABSSP = 1571 , PPC_INS_XVADDDP = 1572 , PPC_INS_XVADDSP = 1573 , PPC_INS_XVCMPEQDP = 1574 , PPC_INS_XVCMPEQSP = 1575 , PPC_INS_XVCMPGEDP = 1576 , PPC_INS_XVCMPGESP = 1577 , PPC_INS_XVCMPGTDP = 1578 , PPC_INS_XVCMPGTSP = 1579 , PPC_INS_XVCPSGNDP = 1580 , PPC_INS_XVCPSGNSP = 1581 , PPC_INS_XVCVDPSP = 1582 , PPC_INS_XVCVDPSXDS = 1583 , PPC_INS_XVCVDPSXWS = 1584 , PPC_INS_XVCVDPUXDS = 1585 , PPC_INS_XVCVDPUXWS = 1586 , PPC_INS_XVCVHPSP = 1587 , PPC_INS_XVCVSPDP = 1588 , PPC_INS_XVCVSPHP = 1589 , PPC_INS_XVCVSPSXDS = 1590 , PPC_INS_XVCVSPSXWS = 1591 , PPC_INS_XVCVSPUXDS = 1592 , PPC_INS_XVCVSPUXWS = 1593 , PPC_INS_XVCVSXDDP = 1594 , PPC_INS_XVCVSXDSP = 1595 , PPC_INS_XVCVSXWDP = 1596 , PPC_INS_XVCVSXWSP = 1597 , PPC_INS_XVCVUXDDP = 1598 , PPC_INS_XVCVUXDSP = 1599 , PPC_INS_XVCVUXWDP = 1600 , PPC_INS_XVCVUXWSP = 1601 , PPC_INS_XVDIVDP = 1602 , PPC_INS_XVDIVSP = 1603 , PPC_INS_XVIEXPDP = 1604 , PPC_INS_XVIEXPSP = 1605 , PPC_INS_XVMADDADP = 1606 , PPC_INS_XVMADDASP = 1607 , PPC_INS_XVMADDMDP = 1608 , PPC_INS_XVMADDMSP = 1609 , PPC_INS_XVMAXDP = 1610 , PPC_INS_XVMAXSP = 1611 , PPC_INS_XVMINDP = 1612 , PPC_INS_XVMINSP = 1613 , PPC_INS_XVMOVDP = 1614 , PPC_INS_XVMOVSP = 1615 , PPC_INS_XVMSUBADP = 1616 , PPC_INS_XVMSUBASP = 1617 , PPC_INS_XVMSUBMDP = 1618 , PPC_INS_XVMSUBMSP = 1619 , PPC_INS_XVMULDP = 1620 , PPC_INS_XVMULSP = 1621 , PPC_INS_XVNABSDP = 1622 , PPC_INS_XVNABSSP = 1623 , PPC_INS_XVNEGDP = 1624 , PPC_INS_XVNEGSP = 1625 , PPC_INS_XVNMADDADP = 1626 , PPC_INS_XVNMADDASP = 1627 , PPC_INS_XVNMADDMDP = 1628 , PPC_INS_XVNMADDMSP = 1629 , PPC_INS_XVNMSUBADP = 1630 , PPC_INS_XVNMSUBASP = 1631 , PPC_INS_XVNMSUBMDP = 1632 , PPC_INS_XVNMSUBMSP = 1633 , PPC_INS_XVRDPI = 1634 , PPC_INS_XVRDPIC = 1635 , PPC_INS_XVRDPIM = 1636 , PPC_INS_XVRDPIP = 1637 , PPC_INS_XVRDPIZ = 1638 , PPC_INS_XVREDP = 1639 , PPC_INS_XVRESP = 1640 , PPC_INS_XVRSPI = 1641 , PPC_INS_XVRSPIC = 1642 , PPC_INS_XVRSPIM = 1643 , PPC_INS_XVRSPIP = 1644 , PPC_INS_XVRSPIZ = 1645 , PPC_INS_XVRSQRTEDP = 1646 , PPC_INS_XVRSQRTESP = 1647 , PPC_INS_XVSQRTDP = 1648 , PPC_INS_XVSQRTSP = 1649 , PPC_INS_XVSUBDP = 1650 , PPC_INS_XVSUBSP = 1651 , PPC_INS_XVTDIVDP = 1652 , PPC_INS_XVTDIVSP = 1653 , PPC_INS_XVTSQRTDP = 1654 , PPC_INS_XVTSQRTSP = 1655 , PPC_INS_XVTSTDCDP = 1656 , PPC_INS_XVTSTDCSP = 1657 , PPC_INS_XVXEXPDP = 1658 , PPC_INS_XVXEXPSP = 1659 , PPC_INS_XVXSIGDP = 1660 , PPC_INS_XVXSIGSP = 1661 , PPC_INS_XXBRD = 1662 , PPC_INS_XXBRH = 1663 , PPC_INS_XXBRQ = 1664 , PPC_INS_XXBRW = 1665 , PPC_INS_XXEXTRACTUW = 1666 , PPC_INS_XXINSERTW = 1667 , PPC_INS_XXLAND = 1668 , PPC_INS_XXLANDC = 1669 , PPC_INS_XXLEQV = 1670 , PPC_INS_XXLNAND = 1671 , PPC_INS_XXLNOR = 1672 , PPC_INS_XXLOR = 1673 , PPC_INS_XXLORC = 1674 , PPC_INS_XXLXOR = 1675 , PPC_INS_XXMRGHD = 1676 , PPC_INS_XXMRGHW = 1677 , PPC_INS_XXMRGLD = 1678 , PPC_INS_XXMRGLW = 1679 , PPC_INS_XXPERM = 1680 , PPC_INS_XXPERMDI = 1681 , PPC_INS_XXPERMR = 1682 , PPC_INS_XXSEL = 1683 , PPC_INS_XXSLDWI = 1684 , PPC_INS_XXSPLTD = 1685 , PPC_INS_XXSPLTIB = 1686 , PPC_INS_XXSPLTW = 1687 , PPC_INS_XXSWAPD = 1688 , PPC_INS_DCBZ_L = 1689 , PPC_INS_PSQ_L = 1690 , PPC_INS_PSQ_LU = 1691 , PPC_INS_PSQ_LUX = 1692 , PPC_INS_PSQ_LX = 1693 , PPC_INS_PSQ_ST = 1694 , PPC_INS_PSQ_STU = 1695 , PPC_INS_PSQ_STUX = 1696 , PPC_INS_PSQ_STX = 1697 , PPC_INS_PS_ABS = 1698 , PPC_INS_PS_ADD = 1699 , PPC_INS_PS_CMPO0 = 1700 , PPC_INS_PS_CMPO1 = 1701 , PPC_INS_PS_CMPU0 = 1702 , PPC_INS_PS_CMPU1 = 1703 , PPC_INS_PS_DIV = 1704 , PPC_INS_PS_MADD = 1705 , PPC_INS_PS_MADDS0 = 1706 , PPC_INS_PS_MADDS1 = 1707 , PPC_INS_PS_MERGE00 = 1708 , PPC_INS_PS_MERGE01 = 1709 , PPC_INS_PS_MERGE10 = 1710 , PPC_INS_PS_MERGE11 = 1711 , PPC_INS_PS_MR = 1712 , PPC_INS_PS_MSUB = 1713 , PPC_INS_PS_MUL = 1714 , PPC_INS_PS_MULS0 = 1715 , PPC_INS_PS_MULS1 = 1716 , PPC_INS_PS_NABS = 1717 , PPC_INS_PS_NEG = 1718 , PPC_INS_PS_NMADD = 1719 , PPC_INS_PS_NMSUB = 1720 , PPC_INS_PS_RES = 1721 , PPC_INS_PS_RSQRTE = 1722 , PPC_INS_PS_SEL = 1723 , PPC_INS_PS_SUB = 1724 , PPC_INS_PS_SUM0 = 1725 , PPC_INS_PS_SUM1 = 1726 , PPC_INS_ENDING = 1727 , } # [repr (u32)] # [doc = " Group of PPC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn_group { # [doc = "< = CS_GRP_INVALID"] PPC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] PPC_GRP_JUMP = 1 , PPC_GRP_ALTIVEC = 128 , PPC_GRP_MODE32 = 129 , PPC_GRP_MODE64 = 130 , PPC_GRP_BOOKE = 131 , PPC_GRP_NOTBOOKE = 132 , PPC_GRP_SPE = 133 , PPC_GRP_VSX = 134 , PPC_GRP_E500 = 135 , PPC_GRP_PPC4XX = 136 , PPC_GRP_PPC6XX = 137 , PPC_GRP_ICBT = 138 , PPC_GRP_P8ALTIVEC = 139 , PPC_GRP_P8VECTOR = 140 , PPC_GRP_QPX = 141 , PPC_GRP_PS = 142 , PPC_GRP_ENDING = 143 , } # [repr (u32)] # [doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_cc { # [doc = "< invalid CC (default)"] SPARC_CC_INVALID = 0 , # [doc = "< Always"] SPARC_CC_ICC_A = 264 , # [doc = "< Never"] SPARC_CC_ICC_N = 256 , # [doc = "< Not Equal"] SPARC_CC_ICC_NE = 265 , # [doc = "< Equal"] SPARC_CC_ICC_E = 257 , # [doc = "< Greater"] SPARC_CC_ICC_G = 266 , # [doc = "< Less or Equal"] SPARC_CC_ICC_LE = 258 , # [doc = "< Greater or Equal"] SPARC_CC_ICC_GE = 267 , # [doc = "< Less"] SPARC_CC_ICC_L = 259 , # [doc = "< Greater Unsigned"] SPARC_CC_ICC_GU = 268 , # [doc = "< Less or Equal Unsigned"] SPARC_CC_ICC_LEU = 260 , # [doc = "< Carry Clear/Great or Equal Unsigned"] SPARC_CC_ICC_CC = 269 , # [doc = "< Carry Set/Less Unsigned"] SPARC_CC_ICC_CS = 261 , # [doc = "< Positive"] SPARC_CC_ICC_POS = 270 , # [doc = "< Negative"] SPARC_CC_ICC_NEG = 262 , # [doc = "< Overflow Clear"] SPARC_CC_ICC_VC = 271 , # [doc = "< Overflow Set"] SPARC_CC_ICC_VS = 263 , # [doc = "< Always"] SPARC_CC_FCC_A = 280 , # [doc = "< Never"] SPARC_CC_FCC_N = 272 , # [doc = "< Unordered"] SPARC_CC_FCC_U = 279 , # [doc = "< Greater"] SPARC_CC_FCC_G = 278 , # [doc = "< Unordered or Greater"] SPARC_CC_FCC_UG = 277 , # [doc = "< Less"] SPARC_CC_FCC_L = 276 , # [doc = "< Unordered or Less"] SPARC_CC_FCC_UL = 275 , # [doc = "< Less or Greater"] SPARC_CC_FCC_LG = 274 , # [doc = "< Not Equal"] SPARC_CC_FCC_NE = 273 , # [doc = "< Equal"] SPARC_CC_FCC_E = 281 , # [doc = "< Unordered or Equal"] SPARC_CC_FCC_UE = 282 , # [doc = "< Greater or Equal"] SPARC_CC_FCC_GE = 283 , # [doc = "< Unordered or Greater or Equal"] SPARC_CC_FCC_UGE = 284 , # [doc = "< Less or Equal"] SPARC_CC_FCC_LE = 285 , # [doc = "< Unordered or Less or Equal"] SPARC_CC_FCC_ULE = 286 , # [doc = "< Ordered"] SPARC_CC_FCC_O = 287 , } # [repr (u32)] # [doc = " Branch hint"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_hint { # [doc = "< no hint"] SPARC_HINT_INVALID = 0 , # [doc = "< annul delay slot instruction"] SPARC_HINT_A = 1 , # [doc = "< branch taken"] SPARC_HINT_PT = 2 , # [doc = "< branch NOT taken"] SPARC_HINT_PN = 4 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SPARC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SPARC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SPARC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SPARC_OP_MEM = 3 , } impl sparc_reg { pub const SPARC_REG_O6 : sparc_reg = sparc_reg :: SPARC_REG_SP ; } impl sparc_reg { pub const SPARC_REG_I6 : sparc_reg = sparc_reg :: SPARC_REG_FP ; } # [repr (u32)] # [doc = " SPARC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_reg { SPARC_REG_INVALID = 0 , SPARC_REG_F0 = 1 , SPARC_REG_F1 = 2 , SPARC_REG_F2 = 3 , SPARC_REG_F3 = 4 , SPARC_REG_F4 = 5 , SPARC_REG_F5 = 6 , SPARC_REG_F6 = 7 , SPARC_REG_F7 = 8 , SPARC_REG_F8 = 9 , SPARC_REG_F9 = 10 , SPARC_REG_F10 = 11 , SPARC_REG_F11 = 12 , SPARC_REG_F12 = 13 , SPARC_REG_F13 = 14 , SPARC_REG_F14 = 15 , SPARC_REG_F15 = 16 , SPARC_REG_F16 = 17 , SPARC_REG_F17 = 18 , SPARC_REG_F18 = 19 , SPARC_REG_F19 = 20 , SPARC_REG_F20 = 21 , SPARC_REG_F21 = 22 , SPARC_REG_F22 = 23 , SPARC_REG_F23 = 24 , SPARC_REG_F24 = 25 , SPARC_REG_F25 = 26 , SPARC_REG_F26 = 27 , SPARC_REG_F27 = 28 , SPARC_REG_F28 = 29 , SPARC_REG_F29 = 30 , SPARC_REG_F30 = 31 , SPARC_REG_F31 = 32 , SPARC_REG_F32 = 33 , SPARC_REG_F34 = 34 , SPARC_REG_F36 = 35 , SPARC_REG_F38 = 36 , SPARC_REG_F40 = 37 , SPARC_REG_F42 = 38 , SPARC_REG_F44 = 39 , SPARC_REG_F46 = 40 , SPARC_REG_F48 = 41 , SPARC_REG_F50 = 42 , SPARC_REG_F52 = 43 , SPARC_REG_F54 = 44 , SPARC_REG_F56 = 45 , SPARC_REG_F58 = 46 , SPARC_REG_F60 = 47 , SPARC_REG_F62 = 48 , SPARC_REG_FCC0 = 49 , SPARC_REG_FCC1 = 50 , SPARC_REG_FCC2 = 51 , SPARC_REG_FCC3 = 52 , SPARC_REG_FP = 53 , SPARC_REG_G0 = 54 , SPARC_REG_G1 = 55 , SPARC_REG_G2 = 56 , SPARC_REG_G3 = 57 , SPARC_REG_G4 = 58 , SPARC_REG_G5 = 59 , SPARC_REG_G6 = 60 , SPARC_REG_G7 = 61 , SPARC_REG_I0 = 62 , SPARC_REG_I1 = 63 , SPARC_REG_I2 = 64 , SPARC_REG_I3 = 65 , SPARC_REG_I4 = 66 , SPARC_REG_I5 = 67 , SPARC_REG_I7 = 68 , SPARC_REG_ICC = 69 , SPARC_REG_L0 = 70 , SPARC_REG_L1 = 71 , SPARC_REG_L2 = 72 , SPARC_REG_L3 = 73 , SPARC_REG_L4 = 74 , SPARC_REG_L5 = 75 , SPARC_REG_L6 = 76 , SPARC_REG_L7 = 77 , SPARC_REG_O0 = 78 , SPARC_REG_O1 = 79 , SPARC_REG_O2 = 80 , SPARC_REG_O3 = 81 , SPARC_REG_O4 = 82 , SPARC_REG_O5 = 83 , SPARC_REG_O7 = 84 , SPARC_REG_SP = 85 , SPARC_REG_Y = 86 , SPARC_REG_XCC = 87 , SPARC_REG_ENDING = 88 , } # [doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sparc_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sparc_op_mem"] [:: std :: mem :: size_of :: < sparc_op_mem > () - 8usize] ; ["Alignment of sparc_op_mem"] [:: std :: mem :: align_of :: < sparc_op_mem > () - 4usize] ; ["Offset of field: sparc_op_mem::base"] [:: std :: mem :: offset_of ! (sparc_op_mem , base) - 0usize] ; ["Offset of field: sparc_op_mem::index"] [:: std :: mem :: offset_of ! (sparc_op_mem , index) - 1usize] ; ["Offset of field: sparc_op_mem::disp"] [:: std :: mem :: offset_of ! (sparc_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc_op { # [doc = "< operand type"] pub type_ : sparc_op_type , pub __bindgen_anon_1 : cs_sparc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sparc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sparc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sparc_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op"] [:: std :: mem :: size_of :: < cs_sparc_op > () - 16usize] ; ["Alignment of cs_sparc_op"] [:: std :: mem :: align_of :: < cs_sparc_op > () - 8usize] ; ["Offset of field: cs_sparc_op::type_"] [:: std :: mem :: offset_of ! (cs_sparc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc { # [doc = "< code condition for this insn"] pub cc : sparc_cc , # [doc = "< branch hint: encoding as bitwise OR of sparc_hint."] pub hint : sparc_hint , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sparc_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc"] [:: std :: mem :: size_of :: < cs_sparc > () - 80usize] ; ["Alignment of cs_sparc"] [:: std :: mem :: align_of :: < cs_sparc > () - 8usize] ; ["Offset of field: cs_sparc::cc"] [:: std :: mem :: offset_of ! (cs_sparc , cc) - 0usize] ; ["Offset of field: cs_sparc::hint"] [:: std :: mem :: offset_of ! (cs_sparc , hint) - 4usize] ; ["Offset of field: cs_sparc::op_count"] [:: std :: mem :: offset_of ! (cs_sparc , op_count) - 8usize] ; ["Offset of field: cs_sparc::operands"] [:: std :: mem :: offset_of ! (cs_sparc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . hint , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SPARC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn { SPARC_INS_INVALID = 0 , SPARC_INS_ADDCC = 1 , SPARC_INS_ADDX = 2 , SPARC_INS_ADDXCC = 3 , SPARC_INS_ADDXC = 4 , SPARC_INS_ADDXCCC = 5 , SPARC_INS_ADD = 6 , SPARC_INS_ALIGNADDR = 7 , SPARC_INS_ALIGNADDRL = 8 , SPARC_INS_ANDCC = 9 , SPARC_INS_ANDNCC = 10 , SPARC_INS_ANDN = 11 , SPARC_INS_AND = 12 , SPARC_INS_ARRAY16 = 13 , SPARC_INS_ARRAY32 = 14 , SPARC_INS_ARRAY8 = 15 , SPARC_INS_B = 16 , SPARC_INS_JMP = 17 , SPARC_INS_BMASK = 18 , SPARC_INS_FB = 19 , SPARC_INS_BRGEZ = 20 , SPARC_INS_BRGZ = 21 , SPARC_INS_BRLEZ = 22 , SPARC_INS_BRLZ = 23 , SPARC_INS_BRNZ = 24 , SPARC_INS_BRZ = 25 , SPARC_INS_BSHUFFLE = 26 , SPARC_INS_CALL = 27 , SPARC_INS_CASX = 28 , SPARC_INS_CAS = 29 , SPARC_INS_CMASK16 = 30 , SPARC_INS_CMASK32 = 31 , SPARC_INS_CMASK8 = 32 , SPARC_INS_CMP = 33 , SPARC_INS_EDGE16 = 34 , SPARC_INS_EDGE16L = 35 , SPARC_INS_EDGE16LN = 36 , SPARC_INS_EDGE16N = 37 , SPARC_INS_EDGE32 = 38 , SPARC_INS_EDGE32L = 39 , SPARC_INS_EDGE32LN = 40 , SPARC_INS_EDGE32N = 41 , SPARC_INS_EDGE8 = 42 , SPARC_INS_EDGE8L = 43 , SPARC_INS_EDGE8LN = 44 , SPARC_INS_EDGE8N = 45 , SPARC_INS_FABSD = 46 , SPARC_INS_FABSQ = 47 , SPARC_INS_FABSS = 48 , SPARC_INS_FADDD = 49 , SPARC_INS_FADDQ = 50 , SPARC_INS_FADDS = 51 , SPARC_INS_FALIGNDATA = 52 , SPARC_INS_FAND = 53 , SPARC_INS_FANDNOT1 = 54 , SPARC_INS_FANDNOT1S = 55 , SPARC_INS_FANDNOT2 = 56 , SPARC_INS_FANDNOT2S = 57 , SPARC_INS_FANDS = 58 , SPARC_INS_FCHKSM16 = 59 , SPARC_INS_FCMPD = 60 , SPARC_INS_FCMPEQ16 = 61 , SPARC_INS_FCMPEQ32 = 62 , SPARC_INS_FCMPGT16 = 63 , SPARC_INS_FCMPGT32 = 64 , SPARC_INS_FCMPLE16 = 65 , SPARC_INS_FCMPLE32 = 66 , SPARC_INS_FCMPNE16 = 67 , SPARC_INS_FCMPNE32 = 68 , SPARC_INS_FCMPQ = 69 , SPARC_INS_FCMPS = 70 , SPARC_INS_FDIVD = 71 , SPARC_INS_FDIVQ = 72 , SPARC_INS_FDIVS = 73 , SPARC_INS_FDMULQ = 74 , SPARC_INS_FDTOI = 75 , SPARC_INS_FDTOQ = 76 , SPARC_INS_FDTOS = 77 , SPARC_INS_FDTOX = 78 , SPARC_INS_FEXPAND = 79 , SPARC_INS_FHADDD = 80 , SPARC_INS_FHADDS = 81 , SPARC_INS_FHSUBD = 82 , SPARC_INS_FHSUBS = 83 , SPARC_INS_FITOD = 84 , SPARC_INS_FITOQ = 85 , SPARC_INS_FITOS = 86 , SPARC_INS_FLCMPD = 87 , SPARC_INS_FLCMPS = 88 , SPARC_INS_FLUSHW = 89 , SPARC_INS_FMEAN16 = 90 , SPARC_INS_FMOVD = 91 , SPARC_INS_FMOVQ = 92 , SPARC_INS_FMOVRDGEZ = 93 , SPARC_INS_FMOVRQGEZ = 94 , SPARC_INS_FMOVRSGEZ = 95 , SPARC_INS_FMOVRDGZ = 96 , SPARC_INS_FMOVRQGZ = 97 , SPARC_INS_FMOVRSGZ = 98 , SPARC_INS_FMOVRDLEZ = 99 , SPARC_INS_FMOVRQLEZ = 100 , SPARC_INS_FMOVRSLEZ = 101 , SPARC_INS_FMOVRDLZ = 102 , SPARC_INS_FMOVRQLZ = 103 , SPARC_INS_FMOVRSLZ = 104 , SPARC_INS_FMOVRDNZ = 105 , SPARC_INS_FMOVRQNZ = 106 , SPARC_INS_FMOVRSNZ = 107 , SPARC_INS_FMOVRDZ = 108 , SPARC_INS_FMOVRQZ = 109 , SPARC_INS_FMOVRSZ = 110 , SPARC_INS_FMOVS = 111 , SPARC_INS_FMUL8SUX16 = 112 , SPARC_INS_FMUL8ULX16 = 113 , SPARC_INS_FMUL8X16 = 114 , SPARC_INS_FMUL8X16AL = 115 , SPARC_INS_FMUL8X16AU = 116 , SPARC_INS_FMULD = 117 , SPARC_INS_FMULD8SUX16 = 118 , SPARC_INS_FMULD8ULX16 = 119 , SPARC_INS_FMULQ = 120 , SPARC_INS_FMULS = 121 , SPARC_INS_FNADDD = 122 , SPARC_INS_FNADDS = 123 , SPARC_INS_FNAND = 124 , SPARC_INS_FNANDS = 125 , SPARC_INS_FNEGD = 126 , SPARC_INS_FNEGQ = 127 , SPARC_INS_FNEGS = 128 , SPARC_INS_FNHADDD = 129 , SPARC_INS_FNHADDS = 130 , SPARC_INS_FNOR = 131 , SPARC_INS_FNORS = 132 , SPARC_INS_FNOT1 = 133 , SPARC_INS_FNOT1S = 134 , SPARC_INS_FNOT2 = 135 , SPARC_INS_FNOT2S = 136 , SPARC_INS_FONE = 137 , SPARC_INS_FONES = 138 , SPARC_INS_FOR = 139 , SPARC_INS_FORNOT1 = 140 , SPARC_INS_FORNOT1S = 141 , SPARC_INS_FORNOT2 = 142 , SPARC_INS_FORNOT2S = 143 , SPARC_INS_FORS = 144 , SPARC_INS_FPACK16 = 145 , SPARC_INS_FPACK32 = 146 , SPARC_INS_FPACKFIX = 147 , SPARC_INS_FPADD16 = 148 , SPARC_INS_FPADD16S = 149 , SPARC_INS_FPADD32 = 150 , SPARC_INS_FPADD32S = 151 , SPARC_INS_FPADD64 = 152 , SPARC_INS_FPMERGE = 153 , SPARC_INS_FPSUB16 = 154 , SPARC_INS_FPSUB16S = 155 , SPARC_INS_FPSUB32 = 156 , SPARC_INS_FPSUB32S = 157 , SPARC_INS_FQTOD = 158 , SPARC_INS_FQTOI = 159 , SPARC_INS_FQTOS = 160 , SPARC_INS_FQTOX = 161 , SPARC_INS_FSLAS16 = 162 , SPARC_INS_FSLAS32 = 163 , SPARC_INS_FSLL16 = 164 , SPARC_INS_FSLL32 = 165 , SPARC_INS_FSMULD = 166 , SPARC_INS_FSQRTD = 167 , SPARC_INS_FSQRTQ = 168 , SPARC_INS_FSQRTS = 169 , SPARC_INS_FSRA16 = 170 , SPARC_INS_FSRA32 = 171 , SPARC_INS_FSRC1 = 172 , SPARC_INS_FSRC1S = 173 , SPARC_INS_FSRC2 = 174 , SPARC_INS_FSRC2S = 175 , SPARC_INS_FSRL16 = 176 , SPARC_INS_FSRL32 = 177 , SPARC_INS_FSTOD = 178 , SPARC_INS_FSTOI = 179 , SPARC_INS_FSTOQ = 180 , SPARC_INS_FSTOX = 181 , SPARC_INS_FSUBD = 182 , SPARC_INS_FSUBQ = 183 , SPARC_INS_FSUBS = 184 , SPARC_INS_FXNOR = 185 , SPARC_INS_FXNORS = 186 , SPARC_INS_FXOR = 187 , SPARC_INS_FXORS = 188 , SPARC_INS_FXTOD = 189 , SPARC_INS_FXTOQ = 190 , SPARC_INS_FXTOS = 191 , SPARC_INS_FZERO = 192 , SPARC_INS_FZEROS = 193 , SPARC_INS_JMPL = 194 , SPARC_INS_LDD = 195 , SPARC_INS_LD = 196 , SPARC_INS_LDQ = 197 , SPARC_INS_LDSB = 198 , SPARC_INS_LDSH = 199 , SPARC_INS_LDSW = 200 , SPARC_INS_LDUB = 201 , SPARC_INS_LDUH = 202 , SPARC_INS_LDX = 203 , SPARC_INS_LZCNT = 204 , SPARC_INS_MEMBAR = 205 , SPARC_INS_MOVDTOX = 206 , SPARC_INS_MOV = 207 , SPARC_INS_MOVRGEZ = 208 , SPARC_INS_MOVRGZ = 209 , SPARC_INS_MOVRLEZ = 210 , SPARC_INS_MOVRLZ = 211 , SPARC_INS_MOVRNZ = 212 , SPARC_INS_MOVRZ = 213 , SPARC_INS_MOVSTOSW = 214 , SPARC_INS_MOVSTOUW = 215 , SPARC_INS_MULX = 216 , SPARC_INS_NOP = 217 , SPARC_INS_ORCC = 218 , SPARC_INS_ORNCC = 219 , SPARC_INS_ORN = 220 , SPARC_INS_OR = 221 , SPARC_INS_PDIST = 222 , SPARC_INS_PDISTN = 223 , SPARC_INS_POPC = 224 , SPARC_INS_RD = 225 , SPARC_INS_RESTORE = 226 , SPARC_INS_RETT = 227 , SPARC_INS_SAVE = 228 , SPARC_INS_SDIVCC = 229 , SPARC_INS_SDIVX = 230 , SPARC_INS_SDIV = 231 , SPARC_INS_SETHI = 232 , SPARC_INS_SHUTDOWN = 233 , SPARC_INS_SIAM = 234 , SPARC_INS_SLLX = 235 , SPARC_INS_SLL = 236 , SPARC_INS_SMULCC = 237 , SPARC_INS_SMUL = 238 , SPARC_INS_SRAX = 239 , SPARC_INS_SRA = 240 , SPARC_INS_SRLX = 241 , SPARC_INS_SRL = 242 , SPARC_INS_STBAR = 243 , SPARC_INS_STB = 244 , SPARC_INS_STD = 245 , SPARC_INS_ST = 246 , SPARC_INS_STH = 247 , SPARC_INS_STQ = 248 , SPARC_INS_STX = 249 , SPARC_INS_SUBCC = 250 , SPARC_INS_SUBX = 251 , SPARC_INS_SUBXCC = 252 , SPARC_INS_SUB = 253 , SPARC_INS_SWAP = 254 , SPARC_INS_TADDCCTV = 255 , SPARC_INS_TADDCC = 256 , SPARC_INS_T = 257 , SPARC_INS_TSUBCCTV = 258 , SPARC_INS_TSUBCC = 259 , SPARC_INS_UDIVCC = 260 , SPARC_INS_UDIVX = 261 , SPARC_INS_UDIV = 262 , SPARC_INS_UMULCC = 263 , SPARC_INS_UMULXHI = 264 , SPARC_INS_UMUL = 265 , SPARC_INS_UNIMP = 266 , SPARC_INS_FCMPED = 267 , SPARC_INS_FCMPEQ = 268 , SPARC_INS_FCMPES = 269 , SPARC_INS_WR = 270 , SPARC_INS_XMULX = 271 , SPARC_INS_XMULXHI = 272 , SPARC_INS_XNORCC = 273 , SPARC_INS_XNOR = 274 , SPARC_INS_XORCC = 275 , SPARC_INS_XOR = 276 , SPARC_INS_RET = 277 , SPARC_INS_RETL = 278 , SPARC_INS_ENDING = 279 , } # [repr (u32)] # [doc = " Group of SPARC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn_group { # [doc = "< = CS_GRP_INVALID"] SPARC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SPARC_GRP_JUMP = 1 , SPARC_GRP_HARDQUAD = 128 , SPARC_GRP_V9 = 129 , SPARC_GRP_VIS = 130 , SPARC_GRP_VIS2 = 131 , SPARC_GRP_VIS3 = 132 , SPARC_GRP_32BIT = 133 , SPARC_GRP_64BIT = 134 , SPARC_GRP_ENDING = 135 , } # [repr (u32)] # [doc = " Enums corresponding to SystemZ condition codes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_cc { # [doc = "< invalid CC (default)"] SYSZ_CC_INVALID = 0 , SYSZ_CC_O = 1 , SYSZ_CC_H = 2 , SYSZ_CC_NLE = 3 , SYSZ_CC_L = 4 , SYSZ_CC_NHE = 5 , SYSZ_CC_LH = 6 , SYSZ_CC_NE = 7 , SYSZ_CC_E = 8 , SYSZ_CC_NLH = 9 , SYSZ_CC_HE = 10 , SYSZ_CC_NL = 11 , SYSZ_CC_LE = 12 , SYSZ_CC_NH = 13 , SYSZ_CC_NO = 14 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SYSZ_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SYSZ_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SYSZ_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SYSZ_OP_MEM = 3 , # [doc = "< Access register operand."] SYSZ_OP_ACREG = 64 , } # [repr (u32)] # [doc = " SystemZ registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_reg { SYSZ_REG_INVALID = 0 , SYSZ_REG_0 = 1 , SYSZ_REG_1 = 2 , SYSZ_REG_2 = 3 , SYSZ_REG_3 = 4 , SYSZ_REG_4 = 5 , SYSZ_REG_5 = 6 , SYSZ_REG_6 = 7 , SYSZ_REG_7 = 8 , SYSZ_REG_8 = 9 , SYSZ_REG_9 = 10 , SYSZ_REG_10 = 11 , SYSZ_REG_11 = 12 , SYSZ_REG_12 = 13 , SYSZ_REG_13 = 14 , SYSZ_REG_14 = 15 , SYSZ_REG_15 = 16 , SYSZ_REG_CC = 17 , SYSZ_REG_F0 = 18 , SYSZ_REG_F1 = 19 , SYSZ_REG_F2 = 20 , SYSZ_REG_F3 = 21 , SYSZ_REG_F4 = 22 , SYSZ_REG_F5 = 23 , SYSZ_REG_F6 = 24 , SYSZ_REG_F7 = 25 , SYSZ_REG_F8 = 26 , SYSZ_REG_F9 = 27 , SYSZ_REG_F10 = 28 , SYSZ_REG_F11 = 29 , SYSZ_REG_F12 = 30 , SYSZ_REG_F13 = 31 , SYSZ_REG_F14 = 32 , SYSZ_REG_F15 = 33 , SYSZ_REG_R0L = 34 , SYSZ_REG_A0 = 35 , SYSZ_REG_A1 = 36 , SYSZ_REG_A2 = 37 , SYSZ_REG_A3 = 38 , SYSZ_REG_A4 = 39 , SYSZ_REG_A5 = 40 , SYSZ_REG_A6 = 41 , SYSZ_REG_A7 = 42 , SYSZ_REG_A8 = 43 , SYSZ_REG_A9 = 44 , SYSZ_REG_A10 = 45 , SYSZ_REG_A11 = 46 , SYSZ_REG_A12 = 47 , SYSZ_REG_A13 = 48 , SYSZ_REG_A14 = 49 , SYSZ_REG_A15 = 50 , SYSZ_REG_C0 = 51 , SYSZ_REG_C1 = 52 , SYSZ_REG_C2 = 53 , SYSZ_REG_C3 = 54 , SYSZ_REG_C4 = 55 , SYSZ_REG_C5 = 56 , SYSZ_REG_C6 = 57 , SYSZ_REG_C7 = 58 , SYSZ_REG_C8 = 59 , SYSZ_REG_C9 = 60 , SYSZ_REG_C10 = 61 , SYSZ_REG_C11 = 62 , SYSZ_REG_C12 = 63 , SYSZ_REG_C13 = 64 , SYSZ_REG_C14 = 65 , SYSZ_REG_C15 = 66 , SYSZ_REG_V0 = 67 , SYSZ_REG_V1 = 68 , SYSZ_REG_V2 = 69 , SYSZ_REG_V3 = 70 , SYSZ_REG_V4 = 71 , SYSZ_REG_V5 = 72 , SYSZ_REG_V6 = 73 , SYSZ_REG_V7 = 74 , SYSZ_REG_V8 = 75 , SYSZ_REG_V9 = 76 , SYSZ_REG_V10 = 77 , SYSZ_REG_V11 = 78 , SYSZ_REG_V12 = 79 , SYSZ_REG_V13 = 80 , SYSZ_REG_V14 = 81 , SYSZ_REG_V15 = 82 , SYSZ_REG_V16 = 83 , SYSZ_REG_V17 = 84 , SYSZ_REG_V18 = 85 , SYSZ_REG_V19 = 86 , SYSZ_REG_V20 = 87 , SYSZ_REG_V21 = 88 , SYSZ_REG_V22 = 89 , SYSZ_REG_V23 = 90 , SYSZ_REG_V24 = 91 , SYSZ_REG_V25 = 92 , SYSZ_REG_V26 = 93 , SYSZ_REG_V27 = 94 , SYSZ_REG_V28 = 95 , SYSZ_REG_V29 = 96 , SYSZ_REG_V30 = 97 , SYSZ_REG_V31 = 98 , SYSZ_REG_F16 = 99 , SYSZ_REG_F17 = 100 , SYSZ_REG_F18 = 101 , SYSZ_REG_F19 = 102 , SYSZ_REG_F20 = 103 , SYSZ_REG_F21 = 104 , SYSZ_REG_F22 = 105 , SYSZ_REG_F23 = 106 , SYSZ_REG_F24 = 107 , SYSZ_REG_F25 = 108 , SYSZ_REG_F26 = 109 , SYSZ_REG_F27 = 110 , SYSZ_REG_F28 = 111 , SYSZ_REG_F29 = 112 , SYSZ_REG_F30 = 113 , SYSZ_REG_F31 = 114 , SYSZ_REG_F0Q = 115 , SYSZ_REG_F4Q = 116 , SYSZ_REG_ENDING = 117 , } # [doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sysz_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< BDLAddr operand"] pub length : u64 , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sysz_op_mem"] [:: std :: mem :: size_of :: < sysz_op_mem > () - 24usize] ; ["Alignment of sysz_op_mem"] [:: std :: mem :: align_of :: < sysz_op_mem > () - 8usize] ; ["Offset of field: sysz_op_mem::base"] [:: std :: mem :: offset_of ! (sysz_op_mem , base) - 0usize] ; ["Offset of field: sysz_op_mem::index"] [:: std :: mem :: offset_of ! (sysz_op_mem , index) - 1usize] ; ["Offset of field: sysz_op_mem::length"] [:: std :: mem :: offset_of ! (sysz_op_mem , length) - 8usize] ; ["Offset of field: sysz_op_mem::disp"] [:: std :: mem :: offset_of ! (sysz_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz_op { # [doc = "< operand type"] pub type_ : sysz_op_type , pub __bindgen_anon_1 : cs_sysz_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sysz_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sysz_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sysz_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sysz_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sysz_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op"] [:: std :: mem :: size_of :: < cs_sysz_op > () - 32usize] ; ["Alignment of cs_sysz_op"] [:: std :: mem :: align_of :: < cs_sysz_op > () - 8usize] ; ["Offset of field: cs_sysz_op::type_"] [:: std :: mem :: offset_of ! (cs_sysz_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz { # [doc = "< Code condition"] pub cc : sysz_cc , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sysz_op ; 6usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz"] [:: std :: mem :: size_of :: < cs_sysz > () - 200usize] ; ["Alignment of cs_sysz"] [:: std :: mem :: align_of :: < cs_sysz > () - 8usize] ; ["Offset of field: cs_sysz::cc"] [:: std :: mem :: offset_of ! (cs_sysz , cc) - 0usize] ; ["Offset of field: cs_sysz::op_count"] [:: std :: mem :: offset_of ! (cs_sysz , op_count) - 4usize] ; ["Offset of field: cs_sysz::operands"] [:: std :: mem :: offset_of ! (cs_sysz , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SystemZ instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn { SYSZ_INS_INVALID = 0 , SYSZ_INS_A = 1 , SYSZ_INS_ADB = 2 , SYSZ_INS_ADBR = 3 , SYSZ_INS_AEB = 4 , SYSZ_INS_AEBR = 5 , SYSZ_INS_AFI = 6 , SYSZ_INS_AG = 7 , SYSZ_INS_AGF = 8 , SYSZ_INS_AGFI = 9 , SYSZ_INS_AGFR = 10 , SYSZ_INS_AGHI = 11 , SYSZ_INS_AGHIK = 12 , SYSZ_INS_AGR = 13 , SYSZ_INS_AGRK = 14 , SYSZ_INS_AGSI = 15 , SYSZ_INS_AH = 16 , SYSZ_INS_AHI = 17 , SYSZ_INS_AHIK = 18 , SYSZ_INS_AHY = 19 , SYSZ_INS_AIH = 20 , SYSZ_INS_AL = 21 , SYSZ_INS_ALC = 22 , SYSZ_INS_ALCG = 23 , SYSZ_INS_ALCGR = 24 , SYSZ_INS_ALCR = 25 , SYSZ_INS_ALFI = 26 , SYSZ_INS_ALG = 27 , SYSZ_INS_ALGF = 28 , SYSZ_INS_ALGFI = 29 , SYSZ_INS_ALGFR = 30 , SYSZ_INS_ALGHSIK = 31 , SYSZ_INS_ALGR = 32 , SYSZ_INS_ALGRK = 33 , SYSZ_INS_ALHSIK = 34 , SYSZ_INS_ALR = 35 , SYSZ_INS_ALRK = 36 , SYSZ_INS_ALY = 37 , SYSZ_INS_AR = 38 , SYSZ_INS_ARK = 39 , SYSZ_INS_ASI = 40 , SYSZ_INS_AXBR = 41 , SYSZ_INS_AY = 42 , SYSZ_INS_BCR = 43 , SYSZ_INS_BRC = 44 , SYSZ_INS_BRCL = 45 , SYSZ_INS_CGIJ = 46 , SYSZ_INS_CGRJ = 47 , SYSZ_INS_CIJ = 48 , SYSZ_INS_CLGIJ = 49 , SYSZ_INS_CLGRJ = 50 , SYSZ_INS_CLIJ = 51 , SYSZ_INS_CLRJ = 52 , SYSZ_INS_CRJ = 53 , SYSZ_INS_BER = 54 , SYSZ_INS_JE = 55 , SYSZ_INS_JGE = 56 , SYSZ_INS_LOCE = 57 , SYSZ_INS_LOCGE = 58 , SYSZ_INS_LOCGRE = 59 , SYSZ_INS_LOCRE = 60 , SYSZ_INS_STOCE = 61 , SYSZ_INS_STOCGE = 62 , SYSZ_INS_BHR = 63 , SYSZ_INS_BHER = 64 , SYSZ_INS_JHE = 65 , SYSZ_INS_JGHE = 66 , SYSZ_INS_LOCHE = 67 , SYSZ_INS_LOCGHE = 68 , SYSZ_INS_LOCGRHE = 69 , SYSZ_INS_LOCRHE = 70 , SYSZ_INS_STOCHE = 71 , SYSZ_INS_STOCGHE = 72 , SYSZ_INS_JH = 73 , SYSZ_INS_JGH = 74 , SYSZ_INS_LOCH = 75 , SYSZ_INS_LOCGH = 76 , SYSZ_INS_LOCGRH = 77 , SYSZ_INS_LOCRH = 78 , SYSZ_INS_STOCH = 79 , SYSZ_INS_STOCGH = 80 , SYSZ_INS_CGIJNLH = 81 , SYSZ_INS_CGRJNLH = 82 , SYSZ_INS_CIJNLH = 83 , SYSZ_INS_CLGIJNLH = 84 , SYSZ_INS_CLGRJNLH = 85 , SYSZ_INS_CLIJNLH = 86 , SYSZ_INS_CLRJNLH = 87 , SYSZ_INS_CRJNLH = 88 , SYSZ_INS_CGIJE = 89 , SYSZ_INS_CGRJE = 90 , SYSZ_INS_CIJE = 91 , SYSZ_INS_CLGIJE = 92 , SYSZ_INS_CLGRJE = 93 , SYSZ_INS_CLIJE = 94 , SYSZ_INS_CLRJE = 95 , SYSZ_INS_CRJE = 96 , SYSZ_INS_CGIJNLE = 97 , SYSZ_INS_CGRJNLE = 98 , SYSZ_INS_CIJNLE = 99 , SYSZ_INS_CLGIJNLE = 100 , SYSZ_INS_CLGRJNLE = 101 , SYSZ_INS_CLIJNLE = 102 , SYSZ_INS_CLRJNLE = 103 , SYSZ_INS_CRJNLE = 104 , SYSZ_INS_CGIJH = 105 , SYSZ_INS_CGRJH = 106 , SYSZ_INS_CIJH = 107 , SYSZ_INS_CLGIJH = 108 , SYSZ_INS_CLGRJH = 109 , SYSZ_INS_CLIJH = 110 , SYSZ_INS_CLRJH = 111 , SYSZ_INS_CRJH = 112 , SYSZ_INS_CGIJNL = 113 , SYSZ_INS_CGRJNL = 114 , SYSZ_INS_CIJNL = 115 , SYSZ_INS_CLGIJNL = 116 , SYSZ_INS_CLGRJNL = 117 , SYSZ_INS_CLIJNL = 118 , SYSZ_INS_CLRJNL = 119 , SYSZ_INS_CRJNL = 120 , SYSZ_INS_CGIJHE = 121 , SYSZ_INS_CGRJHE = 122 , SYSZ_INS_CIJHE = 123 , SYSZ_INS_CLGIJHE = 124 , SYSZ_INS_CLGRJHE = 125 , SYSZ_INS_CLIJHE = 126 , SYSZ_INS_CLRJHE = 127 , SYSZ_INS_CRJHE = 128 , SYSZ_INS_CGIJNHE = 129 , SYSZ_INS_CGRJNHE = 130 , SYSZ_INS_CIJNHE = 131 , SYSZ_INS_CLGIJNHE = 132 , SYSZ_INS_CLGRJNHE = 133 , SYSZ_INS_CLIJNHE = 134 , SYSZ_INS_CLRJNHE = 135 , SYSZ_INS_CRJNHE = 136 , SYSZ_INS_CGIJL = 137 , SYSZ_INS_CGRJL = 138 , SYSZ_INS_CIJL = 139 , SYSZ_INS_CLGIJL = 140 , SYSZ_INS_CLGRJL = 141 , SYSZ_INS_CLIJL = 142 , SYSZ_INS_CLRJL = 143 , SYSZ_INS_CRJL = 144 , SYSZ_INS_CGIJNH = 145 , SYSZ_INS_CGRJNH = 146 , SYSZ_INS_CIJNH = 147 , SYSZ_INS_CLGIJNH = 148 , SYSZ_INS_CLGRJNH = 149 , SYSZ_INS_CLIJNH = 150 , SYSZ_INS_CLRJNH = 151 , SYSZ_INS_CRJNH = 152 , SYSZ_INS_CGIJLE = 153 , SYSZ_INS_CGRJLE = 154 , SYSZ_INS_CIJLE = 155 , SYSZ_INS_CLGIJLE = 156 , SYSZ_INS_CLGRJLE = 157 , SYSZ_INS_CLIJLE = 158 , SYSZ_INS_CLRJLE = 159 , SYSZ_INS_CRJLE = 160 , SYSZ_INS_CGIJNE = 161 , SYSZ_INS_CGRJNE = 162 , SYSZ_INS_CIJNE = 163 , SYSZ_INS_CLGIJNE = 164 , SYSZ_INS_CLGRJNE = 165 , SYSZ_INS_CLIJNE = 166 , SYSZ_INS_CLRJNE = 167 , SYSZ_INS_CRJNE = 168 , SYSZ_INS_CGIJLH = 169 , SYSZ_INS_CGRJLH = 170 , SYSZ_INS_CIJLH = 171 , SYSZ_INS_CLGIJLH = 172 , SYSZ_INS_CLGRJLH = 173 , SYSZ_INS_CLIJLH = 174 , SYSZ_INS_CLRJLH = 175 , SYSZ_INS_CRJLH = 176 , SYSZ_INS_BLR = 177 , SYSZ_INS_BLER = 178 , SYSZ_INS_JLE = 179 , SYSZ_INS_JGLE = 180 , SYSZ_INS_LOCLE = 181 , SYSZ_INS_LOCGLE = 182 , SYSZ_INS_LOCGRLE = 183 , SYSZ_INS_LOCRLE = 184 , SYSZ_INS_STOCLE = 185 , SYSZ_INS_STOCGLE = 186 , SYSZ_INS_BLHR = 187 , SYSZ_INS_JLH = 188 , SYSZ_INS_JGLH = 189 , SYSZ_INS_LOCLH = 190 , SYSZ_INS_LOCGLH = 191 , SYSZ_INS_LOCGRLH = 192 , SYSZ_INS_LOCRLH = 193 , SYSZ_INS_STOCLH = 194 , SYSZ_INS_STOCGLH = 195 , SYSZ_INS_JL = 196 , SYSZ_INS_JGL = 197 , SYSZ_INS_LOCL = 198 , SYSZ_INS_LOCGL = 199 , SYSZ_INS_LOCGRL = 200 , SYSZ_INS_LOCRL = 201 , SYSZ_INS_LOC = 202 , SYSZ_INS_LOCG = 203 , SYSZ_INS_LOCGR = 204 , SYSZ_INS_LOCR = 205 , SYSZ_INS_STOCL = 206 , SYSZ_INS_STOCGL = 207 , SYSZ_INS_BNER = 208 , SYSZ_INS_JNE = 209 , SYSZ_INS_JGNE = 210 , SYSZ_INS_LOCNE = 211 , SYSZ_INS_LOCGNE = 212 , SYSZ_INS_LOCGRNE = 213 , SYSZ_INS_LOCRNE = 214 , SYSZ_INS_STOCNE = 215 , SYSZ_INS_STOCGNE = 216 , SYSZ_INS_BNHR = 217 , SYSZ_INS_BNHER = 218 , SYSZ_INS_JNHE = 219 , SYSZ_INS_JGNHE = 220 , SYSZ_INS_LOCNHE = 221 , SYSZ_INS_LOCGNHE = 222 , SYSZ_INS_LOCGRNHE = 223 , SYSZ_INS_LOCRNHE = 224 , SYSZ_INS_STOCNHE = 225 , SYSZ_INS_STOCGNHE = 226 , SYSZ_INS_JNH = 227 , SYSZ_INS_JGNH = 228 , SYSZ_INS_LOCNH = 229 , SYSZ_INS_LOCGNH = 230 , SYSZ_INS_LOCGRNH = 231 , SYSZ_INS_LOCRNH = 232 , SYSZ_INS_STOCNH = 233 , SYSZ_INS_STOCGNH = 234 , SYSZ_INS_BNLR = 235 , SYSZ_INS_BNLER = 236 , SYSZ_INS_JNLE = 237 , SYSZ_INS_JGNLE = 238 , SYSZ_INS_LOCNLE = 239 , SYSZ_INS_LOCGNLE = 240 , SYSZ_INS_LOCGRNLE = 241 , SYSZ_INS_LOCRNLE = 242 , SYSZ_INS_STOCNLE = 243 , SYSZ_INS_STOCGNLE = 244 , SYSZ_INS_BNLHR = 245 , SYSZ_INS_JNLH = 246 , SYSZ_INS_JGNLH = 247 , SYSZ_INS_LOCNLH = 248 , SYSZ_INS_LOCGNLH = 249 , SYSZ_INS_LOCGRNLH = 250 , SYSZ_INS_LOCRNLH = 251 , SYSZ_INS_STOCNLH = 252 , SYSZ_INS_STOCGNLH = 253 , SYSZ_INS_JNL = 254 , SYSZ_INS_JGNL = 255 , SYSZ_INS_LOCNL = 256 , SYSZ_INS_LOCGNL = 257 , SYSZ_INS_LOCGRNL = 258 , SYSZ_INS_LOCRNL = 259 , SYSZ_INS_STOCNL = 260 , SYSZ_INS_STOCGNL = 261 , SYSZ_INS_BNOR = 262 , SYSZ_INS_JNO = 263 , SYSZ_INS_JGNO = 264 , SYSZ_INS_LOCNO = 265 , SYSZ_INS_LOCGNO = 266 , SYSZ_INS_LOCGRNO = 267 , SYSZ_INS_LOCRNO = 268 , SYSZ_INS_STOCNO = 269 , SYSZ_INS_STOCGNO = 270 , SYSZ_INS_BOR = 271 , SYSZ_INS_JO = 272 , SYSZ_INS_JGO = 273 , SYSZ_INS_LOCO = 274 , SYSZ_INS_LOCGO = 275 , SYSZ_INS_LOCGRO = 276 , SYSZ_INS_LOCRO = 277 , SYSZ_INS_STOCO = 278 , SYSZ_INS_STOCGO = 279 , SYSZ_INS_STOC = 280 , SYSZ_INS_STOCG = 281 , SYSZ_INS_BASR = 282 , SYSZ_INS_BR = 283 , SYSZ_INS_BRAS = 284 , SYSZ_INS_BRASL = 285 , SYSZ_INS_J = 286 , SYSZ_INS_JG = 287 , SYSZ_INS_BRCT = 288 , SYSZ_INS_BRCTG = 289 , SYSZ_INS_C = 290 , SYSZ_INS_CDB = 291 , SYSZ_INS_CDBR = 292 , SYSZ_INS_CDFBR = 293 , SYSZ_INS_CDGBR = 294 , SYSZ_INS_CDLFBR = 295 , SYSZ_INS_CDLGBR = 296 , SYSZ_INS_CEB = 297 , SYSZ_INS_CEBR = 298 , SYSZ_INS_CEFBR = 299 , SYSZ_INS_CEGBR = 300 , SYSZ_INS_CELFBR = 301 , SYSZ_INS_CELGBR = 302 , SYSZ_INS_CFDBR = 303 , SYSZ_INS_CFEBR = 304 , SYSZ_INS_CFI = 305 , SYSZ_INS_CFXBR = 306 , SYSZ_INS_CG = 307 , SYSZ_INS_CGDBR = 308 , SYSZ_INS_CGEBR = 309 , SYSZ_INS_CGF = 310 , SYSZ_INS_CGFI = 311 , SYSZ_INS_CGFR = 312 , SYSZ_INS_CGFRL = 313 , SYSZ_INS_CGH = 314 , SYSZ_INS_CGHI = 315 , SYSZ_INS_CGHRL = 316 , SYSZ_INS_CGHSI = 317 , SYSZ_INS_CGR = 318 , SYSZ_INS_CGRL = 319 , SYSZ_INS_CGXBR = 320 , SYSZ_INS_CH = 321 , SYSZ_INS_CHF = 322 , SYSZ_INS_CHHSI = 323 , SYSZ_INS_CHI = 324 , SYSZ_INS_CHRL = 325 , SYSZ_INS_CHSI = 326 , SYSZ_INS_CHY = 327 , SYSZ_INS_CIH = 328 , SYSZ_INS_CL = 329 , SYSZ_INS_CLC = 330 , SYSZ_INS_CLFDBR = 331 , SYSZ_INS_CLFEBR = 332 , SYSZ_INS_CLFHSI = 333 , SYSZ_INS_CLFI = 334 , SYSZ_INS_CLFXBR = 335 , SYSZ_INS_CLG = 336 , SYSZ_INS_CLGDBR = 337 , SYSZ_INS_CLGEBR = 338 , SYSZ_INS_CLGF = 339 , SYSZ_INS_CLGFI = 340 , SYSZ_INS_CLGFR = 341 , SYSZ_INS_CLGFRL = 342 , SYSZ_INS_CLGHRL = 343 , SYSZ_INS_CLGHSI = 344 , SYSZ_INS_CLGR = 345 , SYSZ_INS_CLGRL = 346 , SYSZ_INS_CLGXBR = 347 , SYSZ_INS_CLHF = 348 , SYSZ_INS_CLHHSI = 349 , SYSZ_INS_CLHRL = 350 , SYSZ_INS_CLI = 351 , SYSZ_INS_CLIH = 352 , SYSZ_INS_CLIY = 353 , SYSZ_INS_CLR = 354 , SYSZ_INS_CLRL = 355 , SYSZ_INS_CLST = 356 , SYSZ_INS_CLY = 357 , SYSZ_INS_CPSDR = 358 , SYSZ_INS_CR = 359 , SYSZ_INS_CRL = 360 , SYSZ_INS_CS = 361 , SYSZ_INS_CSG = 362 , SYSZ_INS_CSY = 363 , SYSZ_INS_CXBR = 364 , SYSZ_INS_CXFBR = 365 , SYSZ_INS_CXGBR = 366 , SYSZ_INS_CXLFBR = 367 , SYSZ_INS_CXLGBR = 368 , SYSZ_INS_CY = 369 , SYSZ_INS_DDB = 370 , SYSZ_INS_DDBR = 371 , SYSZ_INS_DEB = 372 , SYSZ_INS_DEBR = 373 , SYSZ_INS_DL = 374 , SYSZ_INS_DLG = 375 , SYSZ_INS_DLGR = 376 , SYSZ_INS_DLR = 377 , SYSZ_INS_DSG = 378 , SYSZ_INS_DSGF = 379 , SYSZ_INS_DSGFR = 380 , SYSZ_INS_DSGR = 381 , SYSZ_INS_DXBR = 382 , SYSZ_INS_EAR = 383 , SYSZ_INS_FIDBR = 384 , SYSZ_INS_FIDBRA = 385 , SYSZ_INS_FIEBR = 386 , SYSZ_INS_FIEBRA = 387 , SYSZ_INS_FIXBR = 388 , SYSZ_INS_FIXBRA = 389 , SYSZ_INS_FLOGR = 390 , SYSZ_INS_IC = 391 , SYSZ_INS_ICY = 392 , SYSZ_INS_IIHF = 393 , SYSZ_INS_IIHH = 394 , SYSZ_INS_IIHL = 395 , SYSZ_INS_IILF = 396 , SYSZ_INS_IILH = 397 , SYSZ_INS_IILL = 398 , SYSZ_INS_IPM = 399 , SYSZ_INS_L = 400 , SYSZ_INS_LA = 401 , SYSZ_INS_LAA = 402 , SYSZ_INS_LAAG = 403 , SYSZ_INS_LAAL = 404 , SYSZ_INS_LAALG = 405 , SYSZ_INS_LAN = 406 , SYSZ_INS_LANG = 407 , SYSZ_INS_LAO = 408 , SYSZ_INS_LAOG = 409 , SYSZ_INS_LARL = 410 , SYSZ_INS_LAX = 411 , SYSZ_INS_LAXG = 412 , SYSZ_INS_LAY = 413 , SYSZ_INS_LB = 414 , SYSZ_INS_LBH = 415 , SYSZ_INS_LBR = 416 , SYSZ_INS_LCDBR = 417 , SYSZ_INS_LCEBR = 418 , SYSZ_INS_LCGFR = 419 , SYSZ_INS_LCGR = 420 , SYSZ_INS_LCR = 421 , SYSZ_INS_LCXBR = 422 , SYSZ_INS_LD = 423 , SYSZ_INS_LDEB = 424 , SYSZ_INS_LDEBR = 425 , SYSZ_INS_LDGR = 426 , SYSZ_INS_LDR = 427 , SYSZ_INS_LDXBR = 428 , SYSZ_INS_LDXBRA = 429 , SYSZ_INS_LDY = 430 , SYSZ_INS_LE = 431 , SYSZ_INS_LEDBR = 432 , SYSZ_INS_LEDBRA = 433 , SYSZ_INS_LER = 434 , SYSZ_INS_LEXBR = 435 , SYSZ_INS_LEXBRA = 436 , SYSZ_INS_LEY = 437 , SYSZ_INS_LFH = 438 , SYSZ_INS_LG = 439 , SYSZ_INS_LGB = 440 , SYSZ_INS_LGBR = 441 , SYSZ_INS_LGDR = 442 , SYSZ_INS_LGF = 443 , SYSZ_INS_LGFI = 444 , SYSZ_INS_LGFR = 445 , SYSZ_INS_LGFRL = 446 , SYSZ_INS_LGH = 447 , SYSZ_INS_LGHI = 448 , SYSZ_INS_LGHR = 449 , SYSZ_INS_LGHRL = 450 , SYSZ_INS_LGR = 451 , SYSZ_INS_LGRL = 452 , SYSZ_INS_LH = 453 , SYSZ_INS_LHH = 454 , SYSZ_INS_LHI = 455 , SYSZ_INS_LHR = 456 , SYSZ_INS_LHRL = 457 , SYSZ_INS_LHY = 458 , SYSZ_INS_LLC = 459 , SYSZ_INS_LLCH = 460 , SYSZ_INS_LLCR = 461 , SYSZ_INS_LLGC = 462 , SYSZ_INS_LLGCR = 463 , SYSZ_INS_LLGF = 464 , SYSZ_INS_LLGFR = 465 , SYSZ_INS_LLGFRL = 466 , SYSZ_INS_LLGH = 467 , SYSZ_INS_LLGHR = 468 , SYSZ_INS_LLGHRL = 469 , SYSZ_INS_LLH = 470 , SYSZ_INS_LLHH = 471 , SYSZ_INS_LLHR = 472 , SYSZ_INS_LLHRL = 473 , SYSZ_INS_LLIHF = 474 , SYSZ_INS_LLIHH = 475 , SYSZ_INS_LLIHL = 476 , SYSZ_INS_LLILF = 477 , SYSZ_INS_LLILH = 478 , SYSZ_INS_LLILL = 479 , SYSZ_INS_LMG = 480 , SYSZ_INS_LNDBR = 481 , SYSZ_INS_LNEBR = 482 , SYSZ_INS_LNGFR = 483 , SYSZ_INS_LNGR = 484 , SYSZ_INS_LNR = 485 , SYSZ_INS_LNXBR = 486 , SYSZ_INS_LPDBR = 487 , SYSZ_INS_LPEBR = 488 , SYSZ_INS_LPGFR = 489 , SYSZ_INS_LPGR = 490 , SYSZ_INS_LPR = 491 , SYSZ_INS_LPXBR = 492 , SYSZ_INS_LR = 493 , SYSZ_INS_LRL = 494 , SYSZ_INS_LRV = 495 , SYSZ_INS_LRVG = 496 , SYSZ_INS_LRVGR = 497 , SYSZ_INS_LRVR = 498 , SYSZ_INS_LT = 499 , SYSZ_INS_LTDBR = 500 , SYSZ_INS_LTEBR = 501 , SYSZ_INS_LTG = 502 , SYSZ_INS_LTGF = 503 , SYSZ_INS_LTGFR = 504 , SYSZ_INS_LTGR = 505 , SYSZ_INS_LTR = 506 , SYSZ_INS_LTXBR = 507 , SYSZ_INS_LXDB = 508 , SYSZ_INS_LXDBR = 509 , SYSZ_INS_LXEB = 510 , SYSZ_INS_LXEBR = 511 , SYSZ_INS_LXR = 512 , SYSZ_INS_LY = 513 , SYSZ_INS_LZDR = 514 , SYSZ_INS_LZER = 515 , SYSZ_INS_LZXR = 516 , SYSZ_INS_MADB = 517 , SYSZ_INS_MADBR = 518 , SYSZ_INS_MAEB = 519 , SYSZ_INS_MAEBR = 520 , SYSZ_INS_MDB = 521 , SYSZ_INS_MDBR = 522 , SYSZ_INS_MDEB = 523 , SYSZ_INS_MDEBR = 524 , SYSZ_INS_MEEB = 525 , SYSZ_INS_MEEBR = 526 , SYSZ_INS_MGHI = 527 , SYSZ_INS_MH = 528 , SYSZ_INS_MHI = 529 , SYSZ_INS_MHY = 530 , SYSZ_INS_MLG = 531 , SYSZ_INS_MLGR = 532 , SYSZ_INS_MS = 533 , SYSZ_INS_MSDB = 534 , SYSZ_INS_MSDBR = 535 , SYSZ_INS_MSEB = 536 , SYSZ_INS_MSEBR = 537 , SYSZ_INS_MSFI = 538 , SYSZ_INS_MSG = 539 , SYSZ_INS_MSGF = 540 , SYSZ_INS_MSGFI = 541 , SYSZ_INS_MSGFR = 542 , SYSZ_INS_MSGR = 543 , SYSZ_INS_MSR = 544 , SYSZ_INS_MSY = 545 , SYSZ_INS_MVC = 546 , SYSZ_INS_MVGHI = 547 , SYSZ_INS_MVHHI = 548 , SYSZ_INS_MVHI = 549 , SYSZ_INS_MVI = 550 , SYSZ_INS_MVIY = 551 , SYSZ_INS_MVST = 552 , SYSZ_INS_MXBR = 553 , SYSZ_INS_MXDB = 554 , SYSZ_INS_MXDBR = 555 , SYSZ_INS_N = 556 , SYSZ_INS_NC = 557 , SYSZ_INS_NG = 558 , SYSZ_INS_NGR = 559 , SYSZ_INS_NGRK = 560 , SYSZ_INS_NI = 561 , SYSZ_INS_NIHF = 562 , SYSZ_INS_NIHH = 563 , SYSZ_INS_NIHL = 564 , SYSZ_INS_NILF = 565 , SYSZ_INS_NILH = 566 , SYSZ_INS_NILL = 567 , SYSZ_INS_NIY = 568 , SYSZ_INS_NR = 569 , SYSZ_INS_NRK = 570 , SYSZ_INS_NY = 571 , SYSZ_INS_O = 572 , SYSZ_INS_OC = 573 , SYSZ_INS_OG = 574 , SYSZ_INS_OGR = 575 , SYSZ_INS_OGRK = 576 , SYSZ_INS_OI = 577 , SYSZ_INS_OIHF = 578 , SYSZ_INS_OIHH = 579 , SYSZ_INS_OIHL = 580 , SYSZ_INS_OILF = 581 , SYSZ_INS_OILH = 582 , SYSZ_INS_OILL = 583 , SYSZ_INS_OIY = 584 , SYSZ_INS_OR = 585 , SYSZ_INS_ORK = 586 , SYSZ_INS_OY = 587 , SYSZ_INS_PFD = 588 , SYSZ_INS_PFDRL = 589 , SYSZ_INS_RISBG = 590 , SYSZ_INS_RISBHG = 591 , SYSZ_INS_RISBLG = 592 , SYSZ_INS_RLL = 593 , SYSZ_INS_RLLG = 594 , SYSZ_INS_RNSBG = 595 , SYSZ_INS_ROSBG = 596 , SYSZ_INS_RXSBG = 597 , SYSZ_INS_S = 598 , SYSZ_INS_SDB = 599 , SYSZ_INS_SDBR = 600 , SYSZ_INS_SEB = 601 , SYSZ_INS_SEBR = 602 , SYSZ_INS_SG = 603 , SYSZ_INS_SGF = 604 , SYSZ_INS_SGFR = 605 , SYSZ_INS_SGR = 606 , SYSZ_INS_SGRK = 607 , SYSZ_INS_SH = 608 , SYSZ_INS_SHY = 609 , SYSZ_INS_SL = 610 , SYSZ_INS_SLB = 611 , SYSZ_INS_SLBG = 612 , SYSZ_INS_SLBR = 613 , SYSZ_INS_SLFI = 614 , SYSZ_INS_SLG = 615 , SYSZ_INS_SLBGR = 616 , SYSZ_INS_SLGF = 617 , SYSZ_INS_SLGFI = 618 , SYSZ_INS_SLGFR = 619 , SYSZ_INS_SLGR = 620 , SYSZ_INS_SLGRK = 621 , SYSZ_INS_SLL = 622 , SYSZ_INS_SLLG = 623 , SYSZ_INS_SLLK = 624 , SYSZ_INS_SLR = 625 , SYSZ_INS_SLRK = 626 , SYSZ_INS_SLY = 627 , SYSZ_INS_SQDB = 628 , SYSZ_INS_SQDBR = 629 , SYSZ_INS_SQEB = 630 , SYSZ_INS_SQEBR = 631 , SYSZ_INS_SQXBR = 632 , SYSZ_INS_SR = 633 , SYSZ_INS_SRA = 634 , SYSZ_INS_SRAG = 635 , SYSZ_INS_SRAK = 636 , SYSZ_INS_SRK = 637 , SYSZ_INS_SRL = 638 , SYSZ_INS_SRLG = 639 , SYSZ_INS_SRLK = 640 , SYSZ_INS_SRST = 641 , SYSZ_INS_ST = 642 , SYSZ_INS_STC = 643 , SYSZ_INS_STCH = 644 , SYSZ_INS_STCY = 645 , SYSZ_INS_STD = 646 , SYSZ_INS_STDY = 647 , SYSZ_INS_STE = 648 , SYSZ_INS_STEY = 649 , SYSZ_INS_STFH = 650 , SYSZ_INS_STG = 651 , SYSZ_INS_STGRL = 652 , SYSZ_INS_STH = 653 , SYSZ_INS_STHH = 654 , SYSZ_INS_STHRL = 655 , SYSZ_INS_STHY = 656 , SYSZ_INS_STMG = 657 , SYSZ_INS_STRL = 658 , SYSZ_INS_STRV = 659 , SYSZ_INS_STRVG = 660 , SYSZ_INS_STY = 661 , SYSZ_INS_SXBR = 662 , SYSZ_INS_SY = 663 , SYSZ_INS_TM = 664 , SYSZ_INS_TMHH = 665 , SYSZ_INS_TMHL = 666 , SYSZ_INS_TMLH = 667 , SYSZ_INS_TMLL = 668 , SYSZ_INS_TMY = 669 , SYSZ_INS_X = 670 , SYSZ_INS_XC = 671 , SYSZ_INS_XG = 672 , SYSZ_INS_XGR = 673 , SYSZ_INS_XGRK = 674 , SYSZ_INS_XI = 675 , SYSZ_INS_XIHF = 676 , SYSZ_INS_XILF = 677 , SYSZ_INS_XIY = 678 , SYSZ_INS_XR = 679 , SYSZ_INS_XRK = 680 , SYSZ_INS_XY = 681 , SYSZ_INS_AD = 682 , SYSZ_INS_ADR = 683 , SYSZ_INS_ADTR = 684 , SYSZ_INS_ADTRA = 685 , SYSZ_INS_AE = 686 , SYSZ_INS_AER = 687 , SYSZ_INS_AGH = 688 , SYSZ_INS_AHHHR = 689 , SYSZ_INS_AHHLR = 690 , SYSZ_INS_ALGSI = 691 , SYSZ_INS_ALHHHR = 692 , SYSZ_INS_ALHHLR = 693 , SYSZ_INS_ALSI = 694 , SYSZ_INS_ALSIH = 695 , SYSZ_INS_ALSIHN = 696 , SYSZ_INS_AP = 697 , SYSZ_INS_AU = 698 , SYSZ_INS_AUR = 699 , SYSZ_INS_AW = 700 , SYSZ_INS_AWR = 701 , SYSZ_INS_AXR = 702 , SYSZ_INS_AXTR = 703 , SYSZ_INS_AXTRA = 704 , SYSZ_INS_B = 705 , SYSZ_INS_BAKR = 706 , SYSZ_INS_BAL = 707 , SYSZ_INS_BALR = 708 , SYSZ_INS_BAS = 709 , SYSZ_INS_BASSM = 710 , SYSZ_INS_BC = 711 , SYSZ_INS_BCT = 712 , SYSZ_INS_BCTG = 713 , SYSZ_INS_BCTGR = 714 , SYSZ_INS_BCTR = 715 , SYSZ_INS_BE = 716 , SYSZ_INS_BH = 717 , SYSZ_INS_BHE = 718 , SYSZ_INS_BI = 719 , SYSZ_INS_BIC = 720 , SYSZ_INS_BIE = 721 , SYSZ_INS_BIH = 722 , SYSZ_INS_BIHE = 723 , SYSZ_INS_BIL = 724 , SYSZ_INS_BILE = 725 , SYSZ_INS_BILH = 726 , SYSZ_INS_BIM = 727 , SYSZ_INS_BINE = 728 , SYSZ_INS_BINH = 729 , SYSZ_INS_BINHE = 730 , SYSZ_INS_BINL = 731 , SYSZ_INS_BINLE = 732 , SYSZ_INS_BINLH = 733 , SYSZ_INS_BINM = 734 , SYSZ_INS_BINO = 735 , SYSZ_INS_BINP = 736 , SYSZ_INS_BINZ = 737 , SYSZ_INS_BIO = 738 , SYSZ_INS_BIP = 739 , SYSZ_INS_BIZ = 740 , SYSZ_INS_BL = 741 , SYSZ_INS_BLE = 742 , SYSZ_INS_BLH = 743 , SYSZ_INS_BM = 744 , SYSZ_INS_BMR = 745 , SYSZ_INS_BNE = 746 , SYSZ_INS_BNH = 747 , SYSZ_INS_BNHE = 748 , SYSZ_INS_BNL = 749 , SYSZ_INS_BNLE = 750 , SYSZ_INS_BNLH = 751 , SYSZ_INS_BNM = 752 , SYSZ_INS_BNMR = 753 , SYSZ_INS_BNO = 754 , SYSZ_INS_BNP = 755 , SYSZ_INS_BNPR = 756 , SYSZ_INS_BNZ = 757 , SYSZ_INS_BNZR = 758 , SYSZ_INS_BO = 759 , SYSZ_INS_BP = 760 , SYSZ_INS_BPP = 761 , SYSZ_INS_BPR = 762 , SYSZ_INS_BPRP = 763 , SYSZ_INS_BRCTH = 764 , SYSZ_INS_BRXH = 765 , SYSZ_INS_BRXHG = 766 , SYSZ_INS_BRXLE = 767 , SYSZ_INS_BRXLG = 768 , SYSZ_INS_BSA = 769 , SYSZ_INS_BSG = 770 , SYSZ_INS_BSM = 771 , SYSZ_INS_BXH = 772 , SYSZ_INS_BXHG = 773 , SYSZ_INS_BXLE = 774 , SYSZ_INS_BXLEG = 775 , SYSZ_INS_BZ = 776 , SYSZ_INS_BZR = 777 , SYSZ_INS_CD = 778 , SYSZ_INS_CDFBRA = 779 , SYSZ_INS_CDFR = 780 , SYSZ_INS_CDFTR = 781 , SYSZ_INS_CDGBRA = 782 , SYSZ_INS_CDGR = 783 , SYSZ_INS_CDGTR = 784 , SYSZ_INS_CDGTRA = 785 , SYSZ_INS_CDLFTR = 786 , SYSZ_INS_CDLGTR = 787 , SYSZ_INS_CDPT = 788 , SYSZ_INS_CDR = 789 , SYSZ_INS_CDS = 790 , SYSZ_INS_CDSG = 791 , SYSZ_INS_CDSTR = 792 , SYSZ_INS_CDSY = 793 , SYSZ_INS_CDTR = 794 , SYSZ_INS_CDUTR = 795 , SYSZ_INS_CDZT = 796 , SYSZ_INS_CE = 797 , SYSZ_INS_CEDTR = 798 , SYSZ_INS_CEFBRA = 799 , SYSZ_INS_CEFR = 800 , SYSZ_INS_CEGBRA = 801 , SYSZ_INS_CEGR = 802 , SYSZ_INS_CER = 803 , SYSZ_INS_CEXTR = 804 , SYSZ_INS_CFC = 805 , SYSZ_INS_CFDBRA = 806 , SYSZ_INS_CFDR = 807 , SYSZ_INS_CFDTR = 808 , SYSZ_INS_CFEBRA = 809 , SYSZ_INS_CFER = 810 , SYSZ_INS_CFXBRA = 811 , SYSZ_INS_CFXR = 812 , SYSZ_INS_CFXTR = 813 , SYSZ_INS_CGDBRA = 814 , SYSZ_INS_CGDR = 815 , SYSZ_INS_CGDTR = 816 , SYSZ_INS_CGDTRA = 817 , SYSZ_INS_CGEBRA = 818 , SYSZ_INS_CGER = 819 , SYSZ_INS_CGIB = 820 , SYSZ_INS_CGIBE = 821 , SYSZ_INS_CGIBH = 822 , SYSZ_INS_CGIBHE = 823 , SYSZ_INS_CGIBL = 824 , SYSZ_INS_CGIBLE = 825 , SYSZ_INS_CGIBLH = 826 , SYSZ_INS_CGIBNE = 827 , SYSZ_INS_CGIBNH = 828 , SYSZ_INS_CGIBNHE = 829 , SYSZ_INS_CGIBNL = 830 , SYSZ_INS_CGIBNLE = 831 , SYSZ_INS_CGIBNLH = 832 , SYSZ_INS_CGIT = 833 , SYSZ_INS_CGITE = 834 , SYSZ_INS_CGITH = 835 , SYSZ_INS_CGITHE = 836 , SYSZ_INS_CGITL = 837 , SYSZ_INS_CGITLE = 838 , SYSZ_INS_CGITLH = 839 , SYSZ_INS_CGITNE = 840 , SYSZ_INS_CGITNH = 841 , SYSZ_INS_CGITNHE = 842 , SYSZ_INS_CGITNL = 843 , SYSZ_INS_CGITNLE = 844 , SYSZ_INS_CGITNLH = 845 , SYSZ_INS_CGRB = 846 , SYSZ_INS_CGRBE = 847 , SYSZ_INS_CGRBH = 848 , SYSZ_INS_CGRBHE = 849 , SYSZ_INS_CGRBL = 850 , SYSZ_INS_CGRBLE = 851 , SYSZ_INS_CGRBLH = 852 , SYSZ_INS_CGRBNE = 853 , SYSZ_INS_CGRBNH = 854 , SYSZ_INS_CGRBNHE = 855 , SYSZ_INS_CGRBNL = 856 , SYSZ_INS_CGRBNLE = 857 , SYSZ_INS_CGRBNLH = 858 , SYSZ_INS_CGRT = 859 , SYSZ_INS_CGRTE = 860 , SYSZ_INS_CGRTH = 861 , SYSZ_INS_CGRTHE = 862 , SYSZ_INS_CGRTL = 863 , SYSZ_INS_CGRTLE = 864 , SYSZ_INS_CGRTLH = 865 , SYSZ_INS_CGRTNE = 866 , SYSZ_INS_CGRTNH = 867 , SYSZ_INS_CGRTNHE = 868 , SYSZ_INS_CGRTNL = 869 , SYSZ_INS_CGRTNLE = 870 , SYSZ_INS_CGRTNLH = 871 , SYSZ_INS_CGXBRA = 872 , SYSZ_INS_CGXR = 873 , SYSZ_INS_CGXTR = 874 , SYSZ_INS_CGXTRA = 875 , SYSZ_INS_CHHR = 876 , SYSZ_INS_CHLR = 877 , SYSZ_INS_CIB = 878 , SYSZ_INS_CIBE = 879 , SYSZ_INS_CIBH = 880 , SYSZ_INS_CIBHE = 881 , SYSZ_INS_CIBL = 882 , SYSZ_INS_CIBLE = 883 , SYSZ_INS_CIBLH = 884 , SYSZ_INS_CIBNE = 885 , SYSZ_INS_CIBNH = 886 , SYSZ_INS_CIBNHE = 887 , SYSZ_INS_CIBNL = 888 , SYSZ_INS_CIBNLE = 889 , SYSZ_INS_CIBNLH = 890 , SYSZ_INS_CIT = 891 , SYSZ_INS_CITE = 892 , SYSZ_INS_CITH = 893 , SYSZ_INS_CITHE = 894 , SYSZ_INS_CITL = 895 , SYSZ_INS_CITLE = 896 , SYSZ_INS_CITLH = 897 , SYSZ_INS_CITNE = 898 , SYSZ_INS_CITNH = 899 , SYSZ_INS_CITNHE = 900 , SYSZ_INS_CITNL = 901 , SYSZ_INS_CITNLE = 902 , SYSZ_INS_CITNLH = 903 , SYSZ_INS_CKSM = 904 , SYSZ_INS_CLCL = 905 , SYSZ_INS_CLCLE = 906 , SYSZ_INS_CLCLU = 907 , SYSZ_INS_CLFDTR = 908 , SYSZ_INS_CLFIT = 909 , SYSZ_INS_CLFITE = 910 , SYSZ_INS_CLFITH = 911 , SYSZ_INS_CLFITHE = 912 , SYSZ_INS_CLFITL = 913 , SYSZ_INS_CLFITLE = 914 , SYSZ_INS_CLFITLH = 915 , SYSZ_INS_CLFITNE = 916 , SYSZ_INS_CLFITNH = 917 , SYSZ_INS_CLFITNHE = 918 , SYSZ_INS_CLFITNL = 919 , SYSZ_INS_CLFITNLE = 920 , SYSZ_INS_CLFITNLH = 921 , SYSZ_INS_CLFXTR = 922 , SYSZ_INS_CLGDTR = 923 , SYSZ_INS_CLGIB = 924 , SYSZ_INS_CLGIBE = 925 , SYSZ_INS_CLGIBH = 926 , SYSZ_INS_CLGIBHE = 927 , SYSZ_INS_CLGIBL = 928 , SYSZ_INS_CLGIBLE = 929 , SYSZ_INS_CLGIBLH = 930 , SYSZ_INS_CLGIBNE = 931 , SYSZ_INS_CLGIBNH = 932 , SYSZ_INS_CLGIBNHE = 933 , SYSZ_INS_CLGIBNL = 934 , SYSZ_INS_CLGIBNLE = 935 , SYSZ_INS_CLGIBNLH = 936 , SYSZ_INS_CLGIT = 937 , SYSZ_INS_CLGITE = 938 , SYSZ_INS_CLGITH = 939 , SYSZ_INS_CLGITHE = 940 , SYSZ_INS_CLGITL = 941 , SYSZ_INS_CLGITLE = 942 , SYSZ_INS_CLGITLH = 943 , SYSZ_INS_CLGITNE = 944 , SYSZ_INS_CLGITNH = 945 , SYSZ_INS_CLGITNHE = 946 , SYSZ_INS_CLGITNL = 947 , SYSZ_INS_CLGITNLE = 948 , SYSZ_INS_CLGITNLH = 949 , SYSZ_INS_CLGRB = 950 , SYSZ_INS_CLGRBE = 951 , SYSZ_INS_CLGRBH = 952 , SYSZ_INS_CLGRBHE = 953 , SYSZ_INS_CLGRBL = 954 , SYSZ_INS_CLGRBLE = 955 , SYSZ_INS_CLGRBLH = 956 , SYSZ_INS_CLGRBNE = 957 , SYSZ_INS_CLGRBNH = 958 , SYSZ_INS_CLGRBNHE = 959 , SYSZ_INS_CLGRBNL = 960 , SYSZ_INS_CLGRBNLE = 961 , SYSZ_INS_CLGRBNLH = 962 , SYSZ_INS_CLGRT = 963 , SYSZ_INS_CLGRTE = 964 , SYSZ_INS_CLGRTH = 965 , SYSZ_INS_CLGRTHE = 966 , SYSZ_INS_CLGRTL = 967 , SYSZ_INS_CLGRTLE = 968 , SYSZ_INS_CLGRTLH = 969 , SYSZ_INS_CLGRTNE = 970 , SYSZ_INS_CLGRTNH = 971 , SYSZ_INS_CLGRTNHE = 972 , SYSZ_INS_CLGRTNL = 973 , SYSZ_INS_CLGRTNLE = 974 , SYSZ_INS_CLGRTNLH = 975 , SYSZ_INS_CLGT = 976 , SYSZ_INS_CLGTE = 977 , SYSZ_INS_CLGTH = 978 , SYSZ_INS_CLGTHE = 979 , SYSZ_INS_CLGTL = 980 , SYSZ_INS_CLGTLE = 981 , SYSZ_INS_CLGTLH = 982 , SYSZ_INS_CLGTNE = 983 , SYSZ_INS_CLGTNH = 984 , SYSZ_INS_CLGTNHE = 985 , SYSZ_INS_CLGTNL = 986 , SYSZ_INS_CLGTNLE = 987 , SYSZ_INS_CLGTNLH = 988 , SYSZ_INS_CLGXTR = 989 , SYSZ_INS_CLHHR = 990 , SYSZ_INS_CLHLR = 991 , SYSZ_INS_CLIB = 992 , SYSZ_INS_CLIBE = 993 , SYSZ_INS_CLIBH = 994 , SYSZ_INS_CLIBHE = 995 , SYSZ_INS_CLIBL = 996 , SYSZ_INS_CLIBLE = 997 , SYSZ_INS_CLIBLH = 998 , SYSZ_INS_CLIBNE = 999 , SYSZ_INS_CLIBNH = 1000 , SYSZ_INS_CLIBNHE = 1001 , SYSZ_INS_CLIBNL = 1002 , SYSZ_INS_CLIBNLE = 1003 , SYSZ_INS_CLIBNLH = 1004 , SYSZ_INS_CLM = 1005 , SYSZ_INS_CLMH = 1006 , SYSZ_INS_CLMY = 1007 , SYSZ_INS_CLRB = 1008 , SYSZ_INS_CLRBE = 1009 , SYSZ_INS_CLRBH = 1010 , SYSZ_INS_CLRBHE = 1011 , SYSZ_INS_CLRBL = 1012 , SYSZ_INS_CLRBLE = 1013 , SYSZ_INS_CLRBLH = 1014 , SYSZ_INS_CLRBNE = 1015 , SYSZ_INS_CLRBNH = 1016 , SYSZ_INS_CLRBNHE = 1017 , SYSZ_INS_CLRBNL = 1018 , SYSZ_INS_CLRBNLE = 1019 , SYSZ_INS_CLRBNLH = 1020 , SYSZ_INS_CLRT = 1021 , SYSZ_INS_CLRTE = 1022 , SYSZ_INS_CLRTH = 1023 , SYSZ_INS_CLRTHE = 1024 , SYSZ_INS_CLRTL = 1025 , SYSZ_INS_CLRTLE = 1026 , SYSZ_INS_CLRTLH = 1027 , SYSZ_INS_CLRTNE = 1028 , SYSZ_INS_CLRTNH = 1029 , SYSZ_INS_CLRTNHE = 1030 , SYSZ_INS_CLRTNL = 1031 , SYSZ_INS_CLRTNLE = 1032 , SYSZ_INS_CLRTNLH = 1033 , SYSZ_INS_CLT = 1034 , SYSZ_INS_CLTE = 1035 , SYSZ_INS_CLTH = 1036 , SYSZ_INS_CLTHE = 1037 , SYSZ_INS_CLTL = 1038 , SYSZ_INS_CLTLE = 1039 , SYSZ_INS_CLTLH = 1040 , SYSZ_INS_CLTNE = 1041 , SYSZ_INS_CLTNH = 1042 , SYSZ_INS_CLTNHE = 1043 , SYSZ_INS_CLTNL = 1044 , SYSZ_INS_CLTNLE = 1045 , SYSZ_INS_CLTNLH = 1046 , SYSZ_INS_CMPSC = 1047 , SYSZ_INS_CP = 1048 , SYSZ_INS_CPDT = 1049 , SYSZ_INS_CPXT = 1050 , SYSZ_INS_CPYA = 1051 , SYSZ_INS_CRB = 1052 , SYSZ_INS_CRBE = 1053 , SYSZ_INS_CRBH = 1054 , SYSZ_INS_CRBHE = 1055 , SYSZ_INS_CRBL = 1056 , SYSZ_INS_CRBLE = 1057 , SYSZ_INS_CRBLH = 1058 , SYSZ_INS_CRBNE = 1059 , SYSZ_INS_CRBNH = 1060 , SYSZ_INS_CRBNHE = 1061 , SYSZ_INS_CRBNL = 1062 , SYSZ_INS_CRBNLE = 1063 , SYSZ_INS_CRBNLH = 1064 , SYSZ_INS_CRDTE = 1065 , SYSZ_INS_CRT = 1066 , SYSZ_INS_CRTE = 1067 , SYSZ_INS_CRTH = 1068 , SYSZ_INS_CRTHE = 1069 , SYSZ_INS_CRTL = 1070 , SYSZ_INS_CRTLE = 1071 , SYSZ_INS_CRTLH = 1072 , SYSZ_INS_CRTNE = 1073 , SYSZ_INS_CRTNH = 1074 , SYSZ_INS_CRTNHE = 1075 , SYSZ_INS_CRTNL = 1076 , SYSZ_INS_CRTNLE = 1077 , SYSZ_INS_CRTNLH = 1078 , SYSZ_INS_CSCH = 1079 , SYSZ_INS_CSDTR = 1080 , SYSZ_INS_CSP = 1081 , SYSZ_INS_CSPG = 1082 , SYSZ_INS_CSST = 1083 , SYSZ_INS_CSXTR = 1084 , SYSZ_INS_CU12 = 1085 , SYSZ_INS_CU14 = 1086 , SYSZ_INS_CU21 = 1087 , SYSZ_INS_CU24 = 1088 , SYSZ_INS_CU41 = 1089 , SYSZ_INS_CU42 = 1090 , SYSZ_INS_CUDTR = 1091 , SYSZ_INS_CUSE = 1092 , SYSZ_INS_CUTFU = 1093 , SYSZ_INS_CUUTF = 1094 , SYSZ_INS_CUXTR = 1095 , SYSZ_INS_CVB = 1096 , SYSZ_INS_CVBG = 1097 , SYSZ_INS_CVBY = 1098 , SYSZ_INS_CVD = 1099 , SYSZ_INS_CVDG = 1100 , SYSZ_INS_CVDY = 1101 , SYSZ_INS_CXFBRA = 1102 , SYSZ_INS_CXFR = 1103 , SYSZ_INS_CXFTR = 1104 , SYSZ_INS_CXGBRA = 1105 , SYSZ_INS_CXGR = 1106 , SYSZ_INS_CXGTR = 1107 , SYSZ_INS_CXGTRA = 1108 , SYSZ_INS_CXLFTR = 1109 , SYSZ_INS_CXLGTR = 1110 , SYSZ_INS_CXPT = 1111 , SYSZ_INS_CXR = 1112 , SYSZ_INS_CXSTR = 1113 , SYSZ_INS_CXTR = 1114 , SYSZ_INS_CXUTR = 1115 , SYSZ_INS_CXZT = 1116 , SYSZ_INS_CZDT = 1117 , SYSZ_INS_CZXT = 1118 , SYSZ_INS_D = 1119 , SYSZ_INS_DD = 1120 , SYSZ_INS_DDR = 1121 , SYSZ_INS_DDTR = 1122 , SYSZ_INS_DDTRA = 1123 , SYSZ_INS_DE = 1124 , SYSZ_INS_DER = 1125 , SYSZ_INS_DIAG = 1126 , SYSZ_INS_DIDBR = 1127 , SYSZ_INS_DIEBR = 1128 , SYSZ_INS_DP = 1129 , SYSZ_INS_DR = 1130 , SYSZ_INS_DXR = 1131 , SYSZ_INS_DXTR = 1132 , SYSZ_INS_DXTRA = 1133 , SYSZ_INS_ECAG = 1134 , SYSZ_INS_ECCTR = 1135 , SYSZ_INS_ECPGA = 1136 , SYSZ_INS_ECTG = 1137 , SYSZ_INS_ED = 1138 , SYSZ_INS_EDMK = 1139 , SYSZ_INS_EEDTR = 1140 , SYSZ_INS_EEXTR = 1141 , SYSZ_INS_EFPC = 1142 , SYSZ_INS_EPAIR = 1143 , SYSZ_INS_EPAR = 1144 , SYSZ_INS_EPCTR = 1145 , SYSZ_INS_EPSW = 1146 , SYSZ_INS_EREG = 1147 , SYSZ_INS_EREGG = 1148 , SYSZ_INS_ESAIR = 1149 , SYSZ_INS_ESAR = 1150 , SYSZ_INS_ESDTR = 1151 , SYSZ_INS_ESEA = 1152 , SYSZ_INS_ESTA = 1153 , SYSZ_INS_ESXTR = 1154 , SYSZ_INS_ETND = 1155 , SYSZ_INS_EX = 1156 , SYSZ_INS_EXRL = 1157 , SYSZ_INS_FIDR = 1158 , SYSZ_INS_FIDTR = 1159 , SYSZ_INS_FIER = 1160 , SYSZ_INS_FIXR = 1161 , SYSZ_INS_FIXTR = 1162 , SYSZ_INS_HDR = 1163 , SYSZ_INS_HER = 1164 , SYSZ_INS_HSCH = 1165 , SYSZ_INS_IAC = 1166 , SYSZ_INS_ICM = 1167 , SYSZ_INS_ICMH = 1168 , SYSZ_INS_ICMY = 1169 , SYSZ_INS_IDTE = 1170 , SYSZ_INS_IEDTR = 1171 , SYSZ_INS_IEXTR = 1172 , SYSZ_INS_IPK = 1173 , SYSZ_INS_IPTE = 1174 , SYSZ_INS_IRBM = 1175 , SYSZ_INS_ISKE = 1176 , SYSZ_INS_IVSK = 1177 , SYSZ_INS_JGM = 1178 , SYSZ_INS_JGNM = 1179 , SYSZ_INS_JGNP = 1180 , SYSZ_INS_JGNZ = 1181 , SYSZ_INS_JGP = 1182 , SYSZ_INS_JGZ = 1183 , SYSZ_INS_JM = 1184 , SYSZ_INS_JNM = 1185 , SYSZ_INS_JNP = 1186 , SYSZ_INS_JNZ = 1187 , SYSZ_INS_JP = 1188 , SYSZ_INS_JZ = 1189 , SYSZ_INS_KDB = 1190 , SYSZ_INS_KDBR = 1191 , SYSZ_INS_KDTR = 1192 , SYSZ_INS_KEB = 1193 , SYSZ_INS_KEBR = 1194 , SYSZ_INS_KIMD = 1195 , SYSZ_INS_KLMD = 1196 , SYSZ_INS_KM = 1197 , SYSZ_INS_KMA = 1198 , SYSZ_INS_KMAC = 1199 , SYSZ_INS_KMC = 1200 , SYSZ_INS_KMCTR = 1201 , SYSZ_INS_KMF = 1202 , SYSZ_INS_KMO = 1203 , SYSZ_INS_KXBR = 1204 , SYSZ_INS_KXTR = 1205 , SYSZ_INS_LAE = 1206 , SYSZ_INS_LAEY = 1207 , SYSZ_INS_LAM = 1208 , SYSZ_INS_LAMY = 1209 , SYSZ_INS_LASP = 1210 , SYSZ_INS_LAT = 1211 , SYSZ_INS_LCBB = 1212 , SYSZ_INS_LCCTL = 1213 , SYSZ_INS_LCDFR = 1214 , SYSZ_INS_LCDR = 1215 , SYSZ_INS_LCER = 1216 , SYSZ_INS_LCTL = 1217 , SYSZ_INS_LCTLG = 1218 , SYSZ_INS_LCXR = 1219 , SYSZ_INS_LDE = 1220 , SYSZ_INS_LDER = 1221 , SYSZ_INS_LDETR = 1222 , SYSZ_INS_LDXR = 1223 , SYSZ_INS_LDXTR = 1224 , SYSZ_INS_LEDR = 1225 , SYSZ_INS_LEDTR = 1226 , SYSZ_INS_LEXR = 1227 , SYSZ_INS_LFAS = 1228 , SYSZ_INS_LFHAT = 1229 , SYSZ_INS_LFPC = 1230 , SYSZ_INS_LGAT = 1231 , SYSZ_INS_LGG = 1232 , SYSZ_INS_LGSC = 1233 , SYSZ_INS_LLGFAT = 1234 , SYSZ_INS_LLGFSG = 1235 , SYSZ_INS_LLGT = 1236 , SYSZ_INS_LLGTAT = 1237 , SYSZ_INS_LLGTR = 1238 , SYSZ_INS_LLZRGF = 1239 , SYSZ_INS_LM = 1240 , SYSZ_INS_LMD = 1241 , SYSZ_INS_LMH = 1242 , SYSZ_INS_LMY = 1243 , SYSZ_INS_LNDFR = 1244 , SYSZ_INS_LNDR = 1245 , SYSZ_INS_LNER = 1246 , SYSZ_INS_LNXR = 1247 , SYSZ_INS_LOCFH = 1248 , SYSZ_INS_LOCFHE = 1249 , SYSZ_INS_LOCFHH = 1250 , SYSZ_INS_LOCFHHE = 1251 , SYSZ_INS_LOCFHL = 1252 , SYSZ_INS_LOCFHLE = 1253 , SYSZ_INS_LOCFHLH = 1254 , SYSZ_INS_LOCFHM = 1255 , SYSZ_INS_LOCFHNE = 1256 , SYSZ_INS_LOCFHNH = 1257 , SYSZ_INS_LOCFHNHE = 1258 , SYSZ_INS_LOCFHNL = 1259 , SYSZ_INS_LOCFHNLE = 1260 , SYSZ_INS_LOCFHNLH = 1261 , SYSZ_INS_LOCFHNM = 1262 , SYSZ_INS_LOCFHNO = 1263 , SYSZ_INS_LOCFHNP = 1264 , SYSZ_INS_LOCFHNZ = 1265 , SYSZ_INS_LOCFHO = 1266 , SYSZ_INS_LOCFHP = 1267 , SYSZ_INS_LOCFHR = 1268 , SYSZ_INS_LOCFHRE = 1269 , SYSZ_INS_LOCFHRH = 1270 , SYSZ_INS_LOCFHRHE = 1271 , SYSZ_INS_LOCFHRL = 1272 , SYSZ_INS_LOCFHRLE = 1273 , SYSZ_INS_LOCFHRLH = 1274 , SYSZ_INS_LOCFHRM = 1275 , SYSZ_INS_LOCFHRNE = 1276 , SYSZ_INS_LOCFHRNH = 1277 , SYSZ_INS_LOCFHRNHE = 1278 , SYSZ_INS_LOCFHRNL = 1279 , SYSZ_INS_LOCFHRNLE = 1280 , SYSZ_INS_LOCFHRNLH = 1281 , SYSZ_INS_LOCFHRNM = 1282 , SYSZ_INS_LOCFHRNO = 1283 , SYSZ_INS_LOCFHRNP = 1284 , SYSZ_INS_LOCFHRNZ = 1285 , SYSZ_INS_LOCFHRO = 1286 , SYSZ_INS_LOCFHRP = 1287 , SYSZ_INS_LOCFHRZ = 1288 , SYSZ_INS_LOCFHZ = 1289 , SYSZ_INS_LOCGHI = 1290 , SYSZ_INS_LOCGHIE = 1291 , SYSZ_INS_LOCGHIH = 1292 , SYSZ_INS_LOCGHIHE = 1293 , SYSZ_INS_LOCGHIL = 1294 , SYSZ_INS_LOCGHILE = 1295 , SYSZ_INS_LOCGHILH = 1296 , SYSZ_INS_LOCGHIM = 1297 , SYSZ_INS_LOCGHINE = 1298 , SYSZ_INS_LOCGHINH = 1299 , SYSZ_INS_LOCGHINHE = 1300 , SYSZ_INS_LOCGHINL = 1301 , SYSZ_INS_LOCGHINLE = 1302 , SYSZ_INS_LOCGHINLH = 1303 , SYSZ_INS_LOCGHINM = 1304 , SYSZ_INS_LOCGHINO = 1305 , SYSZ_INS_LOCGHINP = 1306 , SYSZ_INS_LOCGHINZ = 1307 , SYSZ_INS_LOCGHIO = 1308 , SYSZ_INS_LOCGHIP = 1309 , SYSZ_INS_LOCGHIZ = 1310 , SYSZ_INS_LOCGM = 1311 , SYSZ_INS_LOCGNM = 1312 , SYSZ_INS_LOCGNP = 1313 , SYSZ_INS_LOCGNZ = 1314 , SYSZ_INS_LOCGP = 1315 , SYSZ_INS_LOCGRM = 1316 , SYSZ_INS_LOCGRNM = 1317 , SYSZ_INS_LOCGRNP = 1318 , SYSZ_INS_LOCGRNZ = 1319 , SYSZ_INS_LOCGRP = 1320 , SYSZ_INS_LOCGRZ = 1321 , SYSZ_INS_LOCGZ = 1322 , SYSZ_INS_LOCHHI = 1323 , SYSZ_INS_LOCHHIE = 1324 , SYSZ_INS_LOCHHIH = 1325 , SYSZ_INS_LOCHHIHE = 1326 , SYSZ_INS_LOCHHIL = 1327 , SYSZ_INS_LOCHHILE = 1328 , SYSZ_INS_LOCHHILH = 1329 , SYSZ_INS_LOCHHIM = 1330 , SYSZ_INS_LOCHHINE = 1331 , SYSZ_INS_LOCHHINH = 1332 , SYSZ_INS_LOCHHINHE = 1333 , SYSZ_INS_LOCHHINL = 1334 , SYSZ_INS_LOCHHINLE = 1335 , SYSZ_INS_LOCHHINLH = 1336 , SYSZ_INS_LOCHHINM = 1337 , SYSZ_INS_LOCHHINO = 1338 , SYSZ_INS_LOCHHINP = 1339 , SYSZ_INS_LOCHHINZ = 1340 , SYSZ_INS_LOCHHIO = 1341 , SYSZ_INS_LOCHHIP = 1342 , SYSZ_INS_LOCHHIZ = 1343 , SYSZ_INS_LOCHI = 1344 , SYSZ_INS_LOCHIE = 1345 , SYSZ_INS_LOCHIH = 1346 , SYSZ_INS_LOCHIHE = 1347 , SYSZ_INS_LOCHIL = 1348 , SYSZ_INS_LOCHILE = 1349 , SYSZ_INS_LOCHILH = 1350 , SYSZ_INS_LOCHIM = 1351 , SYSZ_INS_LOCHINE = 1352 , SYSZ_INS_LOCHINH = 1353 , SYSZ_INS_LOCHINHE = 1354 , SYSZ_INS_LOCHINL = 1355 , SYSZ_INS_LOCHINLE = 1356 , SYSZ_INS_LOCHINLH = 1357 , SYSZ_INS_LOCHINM = 1358 , SYSZ_INS_LOCHINO = 1359 , SYSZ_INS_LOCHINP = 1360 , SYSZ_INS_LOCHINZ = 1361 , SYSZ_INS_LOCHIO = 1362 , SYSZ_INS_LOCHIP = 1363 , SYSZ_INS_LOCHIZ = 1364 , SYSZ_INS_LOCM = 1365 , SYSZ_INS_LOCNM = 1366 , SYSZ_INS_LOCNP = 1367 , SYSZ_INS_LOCNZ = 1368 , SYSZ_INS_LOCP = 1369 , SYSZ_INS_LOCRM = 1370 , SYSZ_INS_LOCRNM = 1371 , SYSZ_INS_LOCRNP = 1372 , SYSZ_INS_LOCRNZ = 1373 , SYSZ_INS_LOCRP = 1374 , SYSZ_INS_LOCRZ = 1375 , SYSZ_INS_LOCZ = 1376 , SYSZ_INS_LPCTL = 1377 , SYSZ_INS_LPD = 1378 , SYSZ_INS_LPDFR = 1379 , SYSZ_INS_LPDG = 1380 , SYSZ_INS_LPDR = 1381 , SYSZ_INS_LPER = 1382 , SYSZ_INS_LPP = 1383 , SYSZ_INS_LPQ = 1384 , SYSZ_INS_LPSW = 1385 , SYSZ_INS_LPSWE = 1386 , SYSZ_INS_LPTEA = 1387 , SYSZ_INS_LPXR = 1388 , SYSZ_INS_LRA = 1389 , SYSZ_INS_LRAG = 1390 , SYSZ_INS_LRAY = 1391 , SYSZ_INS_LRDR = 1392 , SYSZ_INS_LRER = 1393 , SYSZ_INS_LRVH = 1394 , SYSZ_INS_LSCTL = 1395 , SYSZ_INS_LTDR = 1396 , SYSZ_INS_LTDTR = 1397 , SYSZ_INS_LTER = 1398 , SYSZ_INS_LTXR = 1399 , SYSZ_INS_LTXTR = 1400 , SYSZ_INS_LURA = 1401 , SYSZ_INS_LURAG = 1402 , SYSZ_INS_LXD = 1403 , SYSZ_INS_LXDR = 1404 , SYSZ_INS_LXDTR = 1405 , SYSZ_INS_LXE = 1406 , SYSZ_INS_LXER = 1407 , SYSZ_INS_LZRF = 1408 , SYSZ_INS_LZRG = 1409 , SYSZ_INS_M = 1410 , SYSZ_INS_MAD = 1411 , SYSZ_INS_MADR = 1412 , SYSZ_INS_MAE = 1413 , SYSZ_INS_MAER = 1414 , SYSZ_INS_MAY = 1415 , SYSZ_INS_MAYH = 1416 , SYSZ_INS_MAYHR = 1417 , SYSZ_INS_MAYL = 1418 , SYSZ_INS_MAYLR = 1419 , SYSZ_INS_MAYR = 1420 , SYSZ_INS_MC = 1421 , SYSZ_INS_MD = 1422 , SYSZ_INS_MDE = 1423 , SYSZ_INS_MDER = 1424 , SYSZ_INS_MDR = 1425 , SYSZ_INS_MDTR = 1426 , SYSZ_INS_MDTRA = 1427 , SYSZ_INS_ME = 1428 , SYSZ_INS_MEE = 1429 , SYSZ_INS_MEER = 1430 , SYSZ_INS_MER = 1431 , SYSZ_INS_MFY = 1432 , SYSZ_INS_MG = 1433 , SYSZ_INS_MGH = 1434 , SYSZ_INS_MGRK = 1435 , SYSZ_INS_ML = 1436 , SYSZ_INS_MLR = 1437 , SYSZ_INS_MP = 1438 , SYSZ_INS_MR = 1439 , SYSZ_INS_MSC = 1440 , SYSZ_INS_MSCH = 1441 , SYSZ_INS_MSD = 1442 , SYSZ_INS_MSDR = 1443 , SYSZ_INS_MSE = 1444 , SYSZ_INS_MSER = 1445 , SYSZ_INS_MSGC = 1446 , SYSZ_INS_MSGRKC = 1447 , SYSZ_INS_MSRKC = 1448 , SYSZ_INS_MSTA = 1449 , SYSZ_INS_MVCDK = 1450 , SYSZ_INS_MVCIN = 1451 , SYSZ_INS_MVCK = 1452 , SYSZ_INS_MVCL = 1453 , SYSZ_INS_MVCLE = 1454 , SYSZ_INS_MVCLU = 1455 , SYSZ_INS_MVCOS = 1456 , SYSZ_INS_MVCP = 1457 , SYSZ_INS_MVCS = 1458 , SYSZ_INS_MVCSK = 1459 , SYSZ_INS_MVN = 1460 , SYSZ_INS_MVO = 1461 , SYSZ_INS_MVPG = 1462 , SYSZ_INS_MVZ = 1463 , SYSZ_INS_MXD = 1464 , SYSZ_INS_MXDR = 1465 , SYSZ_INS_MXR = 1466 , SYSZ_INS_MXTR = 1467 , SYSZ_INS_MXTRA = 1468 , SYSZ_INS_MY = 1469 , SYSZ_INS_MYH = 1470 , SYSZ_INS_MYHR = 1471 , SYSZ_INS_MYL = 1472 , SYSZ_INS_MYLR = 1473 , SYSZ_INS_MYR = 1474 , SYSZ_INS_NIAI = 1475 , SYSZ_INS_NTSTG = 1476 , SYSZ_INS_PACK = 1477 , SYSZ_INS_PALB = 1478 , SYSZ_INS_PC = 1479 , SYSZ_INS_PCC = 1480 , SYSZ_INS_PCKMO = 1481 , SYSZ_INS_PFMF = 1482 , SYSZ_INS_PFPO = 1483 , SYSZ_INS_PGIN = 1484 , SYSZ_INS_PGOUT = 1485 , SYSZ_INS_PKA = 1486 , SYSZ_INS_PKU = 1487 , SYSZ_INS_PLO = 1488 , SYSZ_INS_POPCNT = 1489 , SYSZ_INS_PPA = 1490 , SYSZ_INS_PPNO = 1491 , SYSZ_INS_PR = 1492 , SYSZ_INS_PRNO = 1493 , SYSZ_INS_PT = 1494 , SYSZ_INS_PTF = 1495 , SYSZ_INS_PTFF = 1496 , SYSZ_INS_PTI = 1497 , SYSZ_INS_PTLB = 1498 , SYSZ_INS_QADTR = 1499 , SYSZ_INS_QAXTR = 1500 , SYSZ_INS_QCTRI = 1501 , SYSZ_INS_QSI = 1502 , SYSZ_INS_RCHP = 1503 , SYSZ_INS_RISBGN = 1504 , SYSZ_INS_RP = 1505 , SYSZ_INS_RRBE = 1506 , SYSZ_INS_RRBM = 1507 , SYSZ_INS_RRDTR = 1508 , SYSZ_INS_RRXTR = 1509 , SYSZ_INS_RSCH = 1510 , SYSZ_INS_SAC = 1511 , SYSZ_INS_SACF = 1512 , SYSZ_INS_SAL = 1513 , SYSZ_INS_SAM24 = 1514 , SYSZ_INS_SAM31 = 1515 , SYSZ_INS_SAM64 = 1516 , SYSZ_INS_SAR = 1517 , SYSZ_INS_SCCTR = 1518 , SYSZ_INS_SCHM = 1519 , SYSZ_INS_SCK = 1520 , SYSZ_INS_SCKC = 1521 , SYSZ_INS_SCKPF = 1522 , SYSZ_INS_SD = 1523 , SYSZ_INS_SDR = 1524 , SYSZ_INS_SDTR = 1525 , SYSZ_INS_SDTRA = 1526 , SYSZ_INS_SE = 1527 , SYSZ_INS_SER = 1528 , SYSZ_INS_SFASR = 1529 , SYSZ_INS_SFPC = 1530 , SYSZ_INS_SGH = 1531 , SYSZ_INS_SHHHR = 1532 , SYSZ_INS_SHHLR = 1533 , SYSZ_INS_SIE = 1534 , SYSZ_INS_SIGA = 1535 , SYSZ_INS_SIGP = 1536 , SYSZ_INS_SLA = 1537 , SYSZ_INS_SLAG = 1538 , SYSZ_INS_SLAK = 1539 , SYSZ_INS_SLDA = 1540 , SYSZ_INS_SLDL = 1541 , SYSZ_INS_SLDT = 1542 , SYSZ_INS_SLHHHR = 1543 , SYSZ_INS_SLHHLR = 1544 , SYSZ_INS_SLXT = 1545 , SYSZ_INS_SP = 1546 , SYSZ_INS_SPCTR = 1547 , SYSZ_INS_SPKA = 1548 , SYSZ_INS_SPM = 1549 , SYSZ_INS_SPT = 1550 , SYSZ_INS_SPX = 1551 , SYSZ_INS_SQD = 1552 , SYSZ_INS_SQDR = 1553 , SYSZ_INS_SQE = 1554 , SYSZ_INS_SQER = 1555 , SYSZ_INS_SQXR = 1556 , SYSZ_INS_SRDA = 1557 , SYSZ_INS_SRDL = 1558 , SYSZ_INS_SRDT = 1559 , SYSZ_INS_SRNM = 1560 , SYSZ_INS_SRNMB = 1561 , SYSZ_INS_SRNMT = 1562 , SYSZ_INS_SRP = 1563 , SYSZ_INS_SRSTU = 1564 , SYSZ_INS_SRXT = 1565 , SYSZ_INS_SSAIR = 1566 , SYSZ_INS_SSAR = 1567 , SYSZ_INS_SSCH = 1568 , SYSZ_INS_SSKE = 1569 , SYSZ_INS_SSM = 1570 , SYSZ_INS_STAM = 1571 , SYSZ_INS_STAMY = 1572 , SYSZ_INS_STAP = 1573 , SYSZ_INS_STCK = 1574 , SYSZ_INS_STCKC = 1575 , SYSZ_INS_STCKE = 1576 , SYSZ_INS_STCKF = 1577 , SYSZ_INS_STCM = 1578 , SYSZ_INS_STCMH = 1579 , SYSZ_INS_STCMY = 1580 , SYSZ_INS_STCPS = 1581 , SYSZ_INS_STCRW = 1582 , SYSZ_INS_STCTG = 1583 , SYSZ_INS_STCTL = 1584 , SYSZ_INS_STFL = 1585 , SYSZ_INS_STFLE = 1586 , SYSZ_INS_STFPC = 1587 , SYSZ_INS_STGSC = 1588 , SYSZ_INS_STIDP = 1589 , SYSZ_INS_STM = 1590 , SYSZ_INS_STMH = 1591 , SYSZ_INS_STMY = 1592 , SYSZ_INS_STNSM = 1593 , SYSZ_INS_STOCFH = 1594 , SYSZ_INS_STOCFHE = 1595 , SYSZ_INS_STOCFHH = 1596 , SYSZ_INS_STOCFHHE = 1597 , SYSZ_INS_STOCFHL = 1598 , SYSZ_INS_STOCFHLE = 1599 , SYSZ_INS_STOCFHLH = 1600 , SYSZ_INS_STOCFHM = 1601 , SYSZ_INS_STOCFHNE = 1602 , SYSZ_INS_STOCFHNH = 1603 , SYSZ_INS_STOCFHNHE = 1604 , SYSZ_INS_STOCFHNL = 1605 , SYSZ_INS_STOCFHNLE = 1606 , SYSZ_INS_STOCFHNLH = 1607 , SYSZ_INS_STOCFHNM = 1608 , SYSZ_INS_STOCFHNO = 1609 , SYSZ_INS_STOCFHNP = 1610 , SYSZ_INS_STOCFHNZ = 1611 , SYSZ_INS_STOCFHO = 1612 , SYSZ_INS_STOCFHP = 1613 , SYSZ_INS_STOCFHZ = 1614 , SYSZ_INS_STOCGM = 1615 , SYSZ_INS_STOCGNM = 1616 , SYSZ_INS_STOCGNP = 1617 , SYSZ_INS_STOCGNZ = 1618 , SYSZ_INS_STOCGP = 1619 , SYSZ_INS_STOCGZ = 1620 , SYSZ_INS_STOCM = 1621 , SYSZ_INS_STOCNM = 1622 , SYSZ_INS_STOCNP = 1623 , SYSZ_INS_STOCNZ = 1624 , SYSZ_INS_STOCP = 1625 , SYSZ_INS_STOCZ = 1626 , SYSZ_INS_STOSM = 1627 , SYSZ_INS_STPQ = 1628 , SYSZ_INS_STPT = 1629 , SYSZ_INS_STPX = 1630 , SYSZ_INS_STRAG = 1631 , SYSZ_INS_STRVH = 1632 , SYSZ_INS_STSCH = 1633 , SYSZ_INS_STSI = 1634 , SYSZ_INS_STURA = 1635 , SYSZ_INS_STURG = 1636 , SYSZ_INS_SU = 1637 , SYSZ_INS_SUR = 1638 , SYSZ_INS_SVC = 1639 , SYSZ_INS_SW = 1640 , SYSZ_INS_SWR = 1641 , SYSZ_INS_SXR = 1642 , SYSZ_INS_SXTR = 1643 , SYSZ_INS_SXTRA = 1644 , SYSZ_INS_TABORT = 1645 , SYSZ_INS_TAM = 1646 , SYSZ_INS_TAR = 1647 , SYSZ_INS_TB = 1648 , SYSZ_INS_TBDR = 1649 , SYSZ_INS_TBEDR = 1650 , SYSZ_INS_TBEGIN = 1651 , SYSZ_INS_TBEGINC = 1652 , SYSZ_INS_TCDB = 1653 , SYSZ_INS_TCEB = 1654 , SYSZ_INS_TCXB = 1655 , SYSZ_INS_TDCDT = 1656 , SYSZ_INS_TDCET = 1657 , SYSZ_INS_TDCXT = 1658 , SYSZ_INS_TDGDT = 1659 , SYSZ_INS_TDGET = 1660 , SYSZ_INS_TDGXT = 1661 , SYSZ_INS_TEND = 1662 , SYSZ_INS_THDER = 1663 , SYSZ_INS_THDR = 1664 , SYSZ_INS_TP = 1665 , SYSZ_INS_TPI = 1666 , SYSZ_INS_TPROT = 1667 , SYSZ_INS_TR = 1668 , SYSZ_INS_TRACE = 1669 , SYSZ_INS_TRACG = 1670 , SYSZ_INS_TRAP2 = 1671 , SYSZ_INS_TRAP4 = 1672 , SYSZ_INS_TRE = 1673 , SYSZ_INS_TROO = 1674 , SYSZ_INS_TROT = 1675 , SYSZ_INS_TRT = 1676 , SYSZ_INS_TRTE = 1677 , SYSZ_INS_TRTO = 1678 , SYSZ_INS_TRTR = 1679 , SYSZ_INS_TRTRE = 1680 , SYSZ_INS_TRTT = 1681 , SYSZ_INS_TS = 1682 , SYSZ_INS_TSCH = 1683 , SYSZ_INS_UNPK = 1684 , SYSZ_INS_UNPKA = 1685 , SYSZ_INS_UNPKU = 1686 , SYSZ_INS_UPT = 1687 , SYSZ_INS_VA = 1688 , SYSZ_INS_VAB = 1689 , SYSZ_INS_VAC = 1690 , SYSZ_INS_VACC = 1691 , SYSZ_INS_VACCB = 1692 , SYSZ_INS_VACCC = 1693 , SYSZ_INS_VACCCQ = 1694 , SYSZ_INS_VACCF = 1695 , SYSZ_INS_VACCG = 1696 , SYSZ_INS_VACCH = 1697 , SYSZ_INS_VACCQ = 1698 , SYSZ_INS_VACQ = 1699 , SYSZ_INS_VAF = 1700 , SYSZ_INS_VAG = 1701 , SYSZ_INS_VAH = 1702 , SYSZ_INS_VAP = 1703 , SYSZ_INS_VAQ = 1704 , SYSZ_INS_VAVG = 1705 , SYSZ_INS_VAVGB = 1706 , SYSZ_INS_VAVGF = 1707 , SYSZ_INS_VAVGG = 1708 , SYSZ_INS_VAVGH = 1709 , SYSZ_INS_VAVGL = 1710 , SYSZ_INS_VAVGLB = 1711 , SYSZ_INS_VAVGLF = 1712 , SYSZ_INS_VAVGLG = 1713 , SYSZ_INS_VAVGLH = 1714 , SYSZ_INS_VBPERM = 1715 , SYSZ_INS_VCDG = 1716 , SYSZ_INS_VCDGB = 1717 , SYSZ_INS_VCDLG = 1718 , SYSZ_INS_VCDLGB = 1719 , SYSZ_INS_VCEQ = 1720 , SYSZ_INS_VCEQB = 1721 , SYSZ_INS_VCEQBS = 1722 , SYSZ_INS_VCEQF = 1723 , SYSZ_INS_VCEQFS = 1724 , SYSZ_INS_VCEQG = 1725 , SYSZ_INS_VCEQGS = 1726 , SYSZ_INS_VCEQH = 1727 , SYSZ_INS_VCEQHS = 1728 , SYSZ_INS_VCGD = 1729 , SYSZ_INS_VCGDB = 1730 , SYSZ_INS_VCH = 1731 , SYSZ_INS_VCHB = 1732 , SYSZ_INS_VCHBS = 1733 , SYSZ_INS_VCHF = 1734 , SYSZ_INS_VCHFS = 1735 , SYSZ_INS_VCHG = 1736 , SYSZ_INS_VCHGS = 1737 , SYSZ_INS_VCHH = 1738 , SYSZ_INS_VCHHS = 1739 , SYSZ_INS_VCHL = 1740 , SYSZ_INS_VCHLB = 1741 , SYSZ_INS_VCHLBS = 1742 , SYSZ_INS_VCHLF = 1743 , SYSZ_INS_VCHLFS = 1744 , SYSZ_INS_VCHLG = 1745 , SYSZ_INS_VCHLGS = 1746 , SYSZ_INS_VCHLH = 1747 , SYSZ_INS_VCHLHS = 1748 , SYSZ_INS_VCKSM = 1749 , SYSZ_INS_VCLGD = 1750 , SYSZ_INS_VCLGDB = 1751 , SYSZ_INS_VCLZ = 1752 , SYSZ_INS_VCLZB = 1753 , SYSZ_INS_VCLZF = 1754 , SYSZ_INS_VCLZG = 1755 , SYSZ_INS_VCLZH = 1756 , SYSZ_INS_VCP = 1757 , SYSZ_INS_VCTZ = 1758 , SYSZ_INS_VCTZB = 1759 , SYSZ_INS_VCTZF = 1760 , SYSZ_INS_VCTZG = 1761 , SYSZ_INS_VCTZH = 1762 , SYSZ_INS_VCVB = 1763 , SYSZ_INS_VCVBG = 1764 , SYSZ_INS_VCVD = 1765 , SYSZ_INS_VCVDG = 1766 , SYSZ_INS_VDP = 1767 , SYSZ_INS_VEC = 1768 , SYSZ_INS_VECB = 1769 , SYSZ_INS_VECF = 1770 , SYSZ_INS_VECG = 1771 , SYSZ_INS_VECH = 1772 , SYSZ_INS_VECL = 1773 , SYSZ_INS_VECLB = 1774 , SYSZ_INS_VECLF = 1775 , SYSZ_INS_VECLG = 1776 , SYSZ_INS_VECLH = 1777 , SYSZ_INS_VERIM = 1778 , SYSZ_INS_VERIMB = 1779 , SYSZ_INS_VERIMF = 1780 , SYSZ_INS_VERIMG = 1781 , SYSZ_INS_VERIMH = 1782 , SYSZ_INS_VERLL = 1783 , SYSZ_INS_VERLLB = 1784 , SYSZ_INS_VERLLF = 1785 , SYSZ_INS_VERLLG = 1786 , SYSZ_INS_VERLLH = 1787 , SYSZ_INS_VERLLV = 1788 , SYSZ_INS_VERLLVB = 1789 , SYSZ_INS_VERLLVF = 1790 , SYSZ_INS_VERLLVG = 1791 , SYSZ_INS_VERLLVH = 1792 , SYSZ_INS_VESL = 1793 , SYSZ_INS_VESLB = 1794 , SYSZ_INS_VESLF = 1795 , SYSZ_INS_VESLG = 1796 , SYSZ_INS_VESLH = 1797 , SYSZ_INS_VESLV = 1798 , SYSZ_INS_VESLVB = 1799 , SYSZ_INS_VESLVF = 1800 , SYSZ_INS_VESLVG = 1801 , SYSZ_INS_VESLVH = 1802 , SYSZ_INS_VESRA = 1803 , SYSZ_INS_VESRAB = 1804 , SYSZ_INS_VESRAF = 1805 , SYSZ_INS_VESRAG = 1806 , SYSZ_INS_VESRAH = 1807 , SYSZ_INS_VESRAV = 1808 , SYSZ_INS_VESRAVB = 1809 , SYSZ_INS_VESRAVF = 1810 , SYSZ_INS_VESRAVG = 1811 , SYSZ_INS_VESRAVH = 1812 , SYSZ_INS_VESRL = 1813 , SYSZ_INS_VESRLB = 1814 , SYSZ_INS_VESRLF = 1815 , SYSZ_INS_VESRLG = 1816 , SYSZ_INS_VESRLH = 1817 , SYSZ_INS_VESRLV = 1818 , SYSZ_INS_VESRLVB = 1819 , SYSZ_INS_VESRLVF = 1820 , SYSZ_INS_VESRLVG = 1821 , SYSZ_INS_VESRLVH = 1822 , SYSZ_INS_VFA = 1823 , SYSZ_INS_VFADB = 1824 , SYSZ_INS_VFAE = 1825 , SYSZ_INS_VFAEB = 1826 , SYSZ_INS_VFAEBS = 1827 , SYSZ_INS_VFAEF = 1828 , SYSZ_INS_VFAEFS = 1829 , SYSZ_INS_VFAEH = 1830 , SYSZ_INS_VFAEHS = 1831 , SYSZ_INS_VFAEZB = 1832 , SYSZ_INS_VFAEZBS = 1833 , SYSZ_INS_VFAEZF = 1834 , SYSZ_INS_VFAEZFS = 1835 , SYSZ_INS_VFAEZH = 1836 , SYSZ_INS_VFAEZHS = 1837 , SYSZ_INS_VFASB = 1838 , SYSZ_INS_VFCE = 1839 , SYSZ_INS_VFCEDB = 1840 , SYSZ_INS_VFCEDBS = 1841 , SYSZ_INS_VFCESB = 1842 , SYSZ_INS_VFCESBS = 1843 , SYSZ_INS_VFCH = 1844 , SYSZ_INS_VFCHDB = 1845 , SYSZ_INS_VFCHDBS = 1846 , SYSZ_INS_VFCHE = 1847 , SYSZ_INS_VFCHEDB = 1848 , SYSZ_INS_VFCHEDBS = 1849 , SYSZ_INS_VFCHESB = 1850 , SYSZ_INS_VFCHESBS = 1851 , SYSZ_INS_VFCHSB = 1852 , SYSZ_INS_VFCHSBS = 1853 , SYSZ_INS_VFD = 1854 , SYSZ_INS_VFDDB = 1855 , SYSZ_INS_VFDSB = 1856 , SYSZ_INS_VFEE = 1857 , SYSZ_INS_VFEEB = 1858 , SYSZ_INS_VFEEBS = 1859 , SYSZ_INS_VFEEF = 1860 , SYSZ_INS_VFEEFS = 1861 , SYSZ_INS_VFEEH = 1862 , SYSZ_INS_VFEEHS = 1863 , SYSZ_INS_VFEEZB = 1864 , SYSZ_INS_VFEEZBS = 1865 , SYSZ_INS_VFEEZF = 1866 , SYSZ_INS_VFEEZFS = 1867 , SYSZ_INS_VFEEZH = 1868 , SYSZ_INS_VFEEZHS = 1869 , SYSZ_INS_VFENE = 1870 , SYSZ_INS_VFENEB = 1871 , SYSZ_INS_VFENEBS = 1872 , SYSZ_INS_VFENEF = 1873 , SYSZ_INS_VFENEFS = 1874 , SYSZ_INS_VFENEH = 1875 , SYSZ_INS_VFENEHS = 1876 , SYSZ_INS_VFENEZB = 1877 , SYSZ_INS_VFENEZBS = 1878 , SYSZ_INS_VFENEZF = 1879 , SYSZ_INS_VFENEZFS = 1880 , SYSZ_INS_VFENEZH = 1881 , SYSZ_INS_VFENEZHS = 1882 , SYSZ_INS_VFI = 1883 , SYSZ_INS_VFIDB = 1884 , SYSZ_INS_VFISB = 1885 , SYSZ_INS_VFKEDB = 1886 , SYSZ_INS_VFKEDBS = 1887 , SYSZ_INS_VFKESB = 1888 , SYSZ_INS_VFKESBS = 1889 , SYSZ_INS_VFKHDB = 1890 , SYSZ_INS_VFKHDBS = 1891 , SYSZ_INS_VFKHEDB = 1892 , SYSZ_INS_VFKHEDBS = 1893 , SYSZ_INS_VFKHESB = 1894 , SYSZ_INS_VFKHESBS = 1895 , SYSZ_INS_VFKHSB = 1896 , SYSZ_INS_VFKHSBS = 1897 , SYSZ_INS_VFLCDB = 1898 , SYSZ_INS_VFLCSB = 1899 , SYSZ_INS_VFLL = 1900 , SYSZ_INS_VFLLS = 1901 , SYSZ_INS_VFLNDB = 1902 , SYSZ_INS_VFLNSB = 1903 , SYSZ_INS_VFLPDB = 1904 , SYSZ_INS_VFLPSB = 1905 , SYSZ_INS_VFLR = 1906 , SYSZ_INS_VFLRD = 1907 , SYSZ_INS_VFM = 1908 , SYSZ_INS_VFMA = 1909 , SYSZ_INS_VFMADB = 1910 , SYSZ_INS_VFMASB = 1911 , SYSZ_INS_VFMAX = 1912 , SYSZ_INS_VFMAXDB = 1913 , SYSZ_INS_VFMAXSB = 1914 , SYSZ_INS_VFMDB = 1915 , SYSZ_INS_VFMIN = 1916 , SYSZ_INS_VFMINDB = 1917 , SYSZ_INS_VFMINSB = 1918 , SYSZ_INS_VFMS = 1919 , SYSZ_INS_VFMSB = 1920 , SYSZ_INS_VFMSDB = 1921 , SYSZ_INS_VFMSSB = 1922 , SYSZ_INS_VFNMA = 1923 , SYSZ_INS_VFNMADB = 1924 , SYSZ_INS_VFNMASB = 1925 , SYSZ_INS_VFNMS = 1926 , SYSZ_INS_VFNMSDB = 1927 , SYSZ_INS_VFNMSSB = 1928 , SYSZ_INS_VFPSO = 1929 , SYSZ_INS_VFPSODB = 1930 , SYSZ_INS_VFPSOSB = 1931 , SYSZ_INS_VFS = 1932 , SYSZ_INS_VFSDB = 1933 , SYSZ_INS_VFSQ = 1934 , SYSZ_INS_VFSQDB = 1935 , SYSZ_INS_VFSQSB = 1936 , SYSZ_INS_VFSSB = 1937 , SYSZ_INS_VFTCI = 1938 , SYSZ_INS_VFTCIDB = 1939 , SYSZ_INS_VFTCISB = 1940 , SYSZ_INS_VGBM = 1941 , SYSZ_INS_VGEF = 1942 , SYSZ_INS_VGEG = 1943 , SYSZ_INS_VGFM = 1944 , SYSZ_INS_VGFMA = 1945 , SYSZ_INS_VGFMAB = 1946 , SYSZ_INS_VGFMAF = 1947 , SYSZ_INS_VGFMAG = 1948 , SYSZ_INS_VGFMAH = 1949 , SYSZ_INS_VGFMB = 1950 , SYSZ_INS_VGFMF = 1951 , SYSZ_INS_VGFMG = 1952 , SYSZ_INS_VGFMH = 1953 , SYSZ_INS_VGM = 1954 , SYSZ_INS_VGMB = 1955 , SYSZ_INS_VGMF = 1956 , SYSZ_INS_VGMG = 1957 , SYSZ_INS_VGMH = 1958 , SYSZ_INS_VISTR = 1959 , SYSZ_INS_VISTRB = 1960 , SYSZ_INS_VISTRBS = 1961 , SYSZ_INS_VISTRF = 1962 , SYSZ_INS_VISTRFS = 1963 , SYSZ_INS_VISTRH = 1964 , SYSZ_INS_VISTRHS = 1965 , SYSZ_INS_VL = 1966 , SYSZ_INS_VLBB = 1967 , SYSZ_INS_VLC = 1968 , SYSZ_INS_VLCB = 1969 , SYSZ_INS_VLCF = 1970 , SYSZ_INS_VLCG = 1971 , SYSZ_INS_VLCH = 1972 , SYSZ_INS_VLDE = 1973 , SYSZ_INS_VLDEB = 1974 , SYSZ_INS_VLEB = 1975 , SYSZ_INS_VLED = 1976 , SYSZ_INS_VLEDB = 1977 , SYSZ_INS_VLEF = 1978 , SYSZ_INS_VLEG = 1979 , SYSZ_INS_VLEH = 1980 , SYSZ_INS_VLEIB = 1981 , SYSZ_INS_VLEIF = 1982 , SYSZ_INS_VLEIG = 1983 , SYSZ_INS_VLEIH = 1984 , SYSZ_INS_VLGV = 1985 , SYSZ_INS_VLGVB = 1986 , SYSZ_INS_VLGVF = 1987 , SYSZ_INS_VLGVG = 1988 , SYSZ_INS_VLGVH = 1989 , SYSZ_INS_VLIP = 1990 , SYSZ_INS_VLL = 1991 , SYSZ_INS_VLLEZ = 1992 , SYSZ_INS_VLLEZB = 1993 , SYSZ_INS_VLLEZF = 1994 , SYSZ_INS_VLLEZG = 1995 , SYSZ_INS_VLLEZH = 1996 , SYSZ_INS_VLLEZLF = 1997 , SYSZ_INS_VLM = 1998 , SYSZ_INS_VLP = 1999 , SYSZ_INS_VLPB = 2000 , SYSZ_INS_VLPF = 2001 , SYSZ_INS_VLPG = 2002 , SYSZ_INS_VLPH = 2003 , SYSZ_INS_VLR = 2004 , SYSZ_INS_VLREP = 2005 , SYSZ_INS_VLREPB = 2006 , SYSZ_INS_VLREPF = 2007 , SYSZ_INS_VLREPG = 2008 , SYSZ_INS_VLREPH = 2009 , SYSZ_INS_VLRL = 2010 , SYSZ_INS_VLRLR = 2011 , SYSZ_INS_VLVG = 2012 , SYSZ_INS_VLVGB = 2013 , SYSZ_INS_VLVGF = 2014 , SYSZ_INS_VLVGG = 2015 , SYSZ_INS_VLVGH = 2016 , SYSZ_INS_VLVGP = 2017 , SYSZ_INS_VMAE = 2018 , SYSZ_INS_VMAEB = 2019 , SYSZ_INS_VMAEF = 2020 , SYSZ_INS_VMAEH = 2021 , SYSZ_INS_VMAH = 2022 , SYSZ_INS_VMAHB = 2023 , SYSZ_INS_VMAHF = 2024 , SYSZ_INS_VMAHH = 2025 , SYSZ_INS_VMAL = 2026 , SYSZ_INS_VMALB = 2027 , SYSZ_INS_VMALE = 2028 , SYSZ_INS_VMALEB = 2029 , SYSZ_INS_VMALEF = 2030 , SYSZ_INS_VMALEH = 2031 , SYSZ_INS_VMALF = 2032 , SYSZ_INS_VMALH = 2033 , SYSZ_INS_VMALHB = 2034 , SYSZ_INS_VMALHF = 2035 , SYSZ_INS_VMALHH = 2036 , SYSZ_INS_VMALHW = 2037 , SYSZ_INS_VMALO = 2038 , SYSZ_INS_VMALOB = 2039 , SYSZ_INS_VMALOF = 2040 , SYSZ_INS_VMALOH = 2041 , SYSZ_INS_VMAO = 2042 , SYSZ_INS_VMAOB = 2043 , SYSZ_INS_VMAOF = 2044 , SYSZ_INS_VMAOH = 2045 , SYSZ_INS_VME = 2046 , SYSZ_INS_VMEB = 2047 , SYSZ_INS_VMEF = 2048 , SYSZ_INS_VMEH = 2049 , SYSZ_INS_VMH = 2050 , SYSZ_INS_VMHB = 2051 , SYSZ_INS_VMHF = 2052 , SYSZ_INS_VMHH = 2053 , SYSZ_INS_VML = 2054 , SYSZ_INS_VMLB = 2055 , SYSZ_INS_VMLE = 2056 , SYSZ_INS_VMLEB = 2057 , SYSZ_INS_VMLEF = 2058 , SYSZ_INS_VMLEH = 2059 , SYSZ_INS_VMLF = 2060 , SYSZ_INS_VMLH = 2061 , SYSZ_INS_VMLHB = 2062 , SYSZ_INS_VMLHF = 2063 , SYSZ_INS_VMLHH = 2064 , SYSZ_INS_VMLHW = 2065 , SYSZ_INS_VMLO = 2066 , SYSZ_INS_VMLOB = 2067 , SYSZ_INS_VMLOF = 2068 , SYSZ_INS_VMLOH = 2069 , SYSZ_INS_VMN = 2070 , SYSZ_INS_VMNB = 2071 , SYSZ_INS_VMNF = 2072 , SYSZ_INS_VMNG = 2073 , SYSZ_INS_VMNH = 2074 , SYSZ_INS_VMNL = 2075 , SYSZ_INS_VMNLB = 2076 , SYSZ_INS_VMNLF = 2077 , SYSZ_INS_VMNLG = 2078 , SYSZ_INS_VMNLH = 2079 , SYSZ_INS_VMO = 2080 , SYSZ_INS_VMOB = 2081 , SYSZ_INS_VMOF = 2082 , SYSZ_INS_VMOH = 2083 , SYSZ_INS_VMP = 2084 , SYSZ_INS_VMRH = 2085 , SYSZ_INS_VMRHB = 2086 , SYSZ_INS_VMRHF = 2087 , SYSZ_INS_VMRHG = 2088 , SYSZ_INS_VMRHH = 2089 , SYSZ_INS_VMRL = 2090 , SYSZ_INS_VMRLB = 2091 , SYSZ_INS_VMRLF = 2092 , SYSZ_INS_VMRLG = 2093 , SYSZ_INS_VMRLH = 2094 , SYSZ_INS_VMSL = 2095 , SYSZ_INS_VMSLG = 2096 , SYSZ_INS_VMSP = 2097 , SYSZ_INS_VMX = 2098 , SYSZ_INS_VMXB = 2099 , SYSZ_INS_VMXF = 2100 , SYSZ_INS_VMXG = 2101 , SYSZ_INS_VMXH = 2102 , SYSZ_INS_VMXL = 2103 , SYSZ_INS_VMXLB = 2104 , SYSZ_INS_VMXLF = 2105 , SYSZ_INS_VMXLG = 2106 , SYSZ_INS_VMXLH = 2107 , SYSZ_INS_VN = 2108 , SYSZ_INS_VNC = 2109 , SYSZ_INS_VNN = 2110 , SYSZ_INS_VNO = 2111 , SYSZ_INS_VNX = 2112 , SYSZ_INS_VO = 2113 , SYSZ_INS_VOC = 2114 , SYSZ_INS_VONE = 2115 , SYSZ_INS_VPDI = 2116 , SYSZ_INS_VPERM = 2117 , SYSZ_INS_VPK = 2118 , SYSZ_INS_VPKF = 2119 , SYSZ_INS_VPKG = 2120 , SYSZ_INS_VPKH = 2121 , SYSZ_INS_VPKLS = 2122 , SYSZ_INS_VPKLSF = 2123 , SYSZ_INS_VPKLSFS = 2124 , SYSZ_INS_VPKLSG = 2125 , SYSZ_INS_VPKLSGS = 2126 , SYSZ_INS_VPKLSH = 2127 , SYSZ_INS_VPKLSHS = 2128 , SYSZ_INS_VPKS = 2129 , SYSZ_INS_VPKSF = 2130 , SYSZ_INS_VPKSFS = 2131 , SYSZ_INS_VPKSG = 2132 , SYSZ_INS_VPKSGS = 2133 , SYSZ_INS_VPKSH = 2134 , SYSZ_INS_VPKSHS = 2135 , SYSZ_INS_VPKZ = 2136 , SYSZ_INS_VPOPCT = 2137 , SYSZ_INS_VPOPCTB = 2138 , SYSZ_INS_VPOPCTF = 2139 , SYSZ_INS_VPOPCTG = 2140 , SYSZ_INS_VPOPCTH = 2141 , SYSZ_INS_VPSOP = 2142 , SYSZ_INS_VREP = 2143 , SYSZ_INS_VREPB = 2144 , SYSZ_INS_VREPF = 2145 , SYSZ_INS_VREPG = 2146 , SYSZ_INS_VREPH = 2147 , SYSZ_INS_VREPI = 2148 , SYSZ_INS_VREPIB = 2149 , SYSZ_INS_VREPIF = 2150 , SYSZ_INS_VREPIG = 2151 , SYSZ_INS_VREPIH = 2152 , SYSZ_INS_VRP = 2153 , SYSZ_INS_VS = 2154 , SYSZ_INS_VSB = 2155 , SYSZ_INS_VSBCBI = 2156 , SYSZ_INS_VSBCBIQ = 2157 , SYSZ_INS_VSBI = 2158 , SYSZ_INS_VSBIQ = 2159 , SYSZ_INS_VSCBI = 2160 , SYSZ_INS_VSCBIB = 2161 , SYSZ_INS_VSCBIF = 2162 , SYSZ_INS_VSCBIG = 2163 , SYSZ_INS_VSCBIH = 2164 , SYSZ_INS_VSCBIQ = 2165 , SYSZ_INS_VSCEF = 2166 , SYSZ_INS_VSCEG = 2167 , SYSZ_INS_VSDP = 2168 , SYSZ_INS_VSEG = 2169 , SYSZ_INS_VSEGB = 2170 , SYSZ_INS_VSEGF = 2171 , SYSZ_INS_VSEGH = 2172 , SYSZ_INS_VSEL = 2173 , SYSZ_INS_VSF = 2174 , SYSZ_INS_VSG = 2175 , SYSZ_INS_VSH = 2176 , SYSZ_INS_VSL = 2177 , SYSZ_INS_VSLB = 2178 , SYSZ_INS_VSLDB = 2179 , SYSZ_INS_VSP = 2180 , SYSZ_INS_VSQ = 2181 , SYSZ_INS_VSRA = 2182 , SYSZ_INS_VSRAB = 2183 , SYSZ_INS_VSRL = 2184 , SYSZ_INS_VSRLB = 2185 , SYSZ_INS_VSRP = 2186 , SYSZ_INS_VST = 2187 , SYSZ_INS_VSTEB = 2188 , SYSZ_INS_VSTEF = 2189 , SYSZ_INS_VSTEG = 2190 , SYSZ_INS_VSTEH = 2191 , SYSZ_INS_VSTL = 2192 , SYSZ_INS_VSTM = 2193 , SYSZ_INS_VSTRC = 2194 , SYSZ_INS_VSTRCB = 2195 , SYSZ_INS_VSTRCBS = 2196 , SYSZ_INS_VSTRCF = 2197 , SYSZ_INS_VSTRCFS = 2198 , SYSZ_INS_VSTRCH = 2199 , SYSZ_INS_VSTRCHS = 2200 , SYSZ_INS_VSTRCZB = 2201 , SYSZ_INS_VSTRCZBS = 2202 , SYSZ_INS_VSTRCZF = 2203 , SYSZ_INS_VSTRCZFS = 2204 , SYSZ_INS_VSTRCZH = 2205 , SYSZ_INS_VSTRCZHS = 2206 , SYSZ_INS_VSTRL = 2207 , SYSZ_INS_VSTRLR = 2208 , SYSZ_INS_VSUM = 2209 , SYSZ_INS_VSUMB = 2210 , SYSZ_INS_VSUMG = 2211 , SYSZ_INS_VSUMGF = 2212 , SYSZ_INS_VSUMGH = 2213 , SYSZ_INS_VSUMH = 2214 , SYSZ_INS_VSUMQ = 2215 , SYSZ_INS_VSUMQF = 2216 , SYSZ_INS_VSUMQG = 2217 , SYSZ_INS_VTM = 2218 , SYSZ_INS_VTP = 2219 , SYSZ_INS_VUPH = 2220 , SYSZ_INS_VUPHB = 2221 , SYSZ_INS_VUPHF = 2222 , SYSZ_INS_VUPHH = 2223 , SYSZ_INS_VUPKZ = 2224 , SYSZ_INS_VUPL = 2225 , SYSZ_INS_VUPLB = 2226 , SYSZ_INS_VUPLF = 2227 , SYSZ_INS_VUPLH = 2228 , SYSZ_INS_VUPLHB = 2229 , SYSZ_INS_VUPLHF = 2230 , SYSZ_INS_VUPLHH = 2231 , SYSZ_INS_VUPLHW = 2232 , SYSZ_INS_VUPLL = 2233 , SYSZ_INS_VUPLLB = 2234 , SYSZ_INS_VUPLLF = 2235 , SYSZ_INS_VUPLLH = 2236 , SYSZ_INS_VX = 2237 , SYSZ_INS_VZERO = 2238 , SYSZ_INS_WCDGB = 2239 , SYSZ_INS_WCDLGB = 2240 , SYSZ_INS_WCGDB = 2241 , SYSZ_INS_WCLGDB = 2242 , SYSZ_INS_WFADB = 2243 , SYSZ_INS_WFASB = 2244 , SYSZ_INS_WFAXB = 2245 , SYSZ_INS_WFC = 2246 , SYSZ_INS_WFCDB = 2247 , SYSZ_INS_WFCEDB = 2248 , SYSZ_INS_WFCEDBS = 2249 , SYSZ_INS_WFCESB = 2250 , SYSZ_INS_WFCESBS = 2251 , SYSZ_INS_WFCEXB = 2252 , SYSZ_INS_WFCEXBS = 2253 , SYSZ_INS_WFCHDB = 2254 , SYSZ_INS_WFCHDBS = 2255 , SYSZ_INS_WFCHEDB = 2256 , SYSZ_INS_WFCHEDBS = 2257 , SYSZ_INS_WFCHESB = 2258 , SYSZ_INS_WFCHESBS = 2259 , SYSZ_INS_WFCHEXB = 2260 , SYSZ_INS_WFCHEXBS = 2261 , SYSZ_INS_WFCHSB = 2262 , SYSZ_INS_WFCHSBS = 2263 , SYSZ_INS_WFCHXB = 2264 , SYSZ_INS_WFCHXBS = 2265 , SYSZ_INS_WFCSB = 2266 , SYSZ_INS_WFCXB = 2267 , SYSZ_INS_WFDDB = 2268 , SYSZ_INS_WFDSB = 2269 , SYSZ_INS_WFDXB = 2270 , SYSZ_INS_WFIDB = 2271 , SYSZ_INS_WFISB = 2272 , SYSZ_INS_WFIXB = 2273 , SYSZ_INS_WFK = 2274 , SYSZ_INS_WFKDB = 2275 , SYSZ_INS_WFKEDB = 2276 , SYSZ_INS_WFKEDBS = 2277 , SYSZ_INS_WFKESB = 2278 , SYSZ_INS_WFKESBS = 2279 , SYSZ_INS_WFKEXB = 2280 , SYSZ_INS_WFKEXBS = 2281 , SYSZ_INS_WFKHDB = 2282 , SYSZ_INS_WFKHDBS = 2283 , SYSZ_INS_WFKHEDB = 2284 , SYSZ_INS_WFKHEDBS = 2285 , SYSZ_INS_WFKHESB = 2286 , SYSZ_INS_WFKHESBS = 2287 , SYSZ_INS_WFKHEXB = 2288 , SYSZ_INS_WFKHEXBS = 2289 , SYSZ_INS_WFKHSB = 2290 , SYSZ_INS_WFKHSBS = 2291 , SYSZ_INS_WFKHXB = 2292 , SYSZ_INS_WFKHXBS = 2293 , SYSZ_INS_WFKSB = 2294 , SYSZ_INS_WFKXB = 2295 , SYSZ_INS_WFLCDB = 2296 , SYSZ_INS_WFLCSB = 2297 , SYSZ_INS_WFLCXB = 2298 , SYSZ_INS_WFLLD = 2299 , SYSZ_INS_WFLLS = 2300 , SYSZ_INS_WFLNDB = 2301 , SYSZ_INS_WFLNSB = 2302 , SYSZ_INS_WFLNXB = 2303 , SYSZ_INS_WFLPDB = 2304 , SYSZ_INS_WFLPSB = 2305 , SYSZ_INS_WFLPXB = 2306 , SYSZ_INS_WFLRD = 2307 , SYSZ_INS_WFLRX = 2308 , SYSZ_INS_WFMADB = 2309 , SYSZ_INS_WFMASB = 2310 , SYSZ_INS_WFMAXB = 2311 , SYSZ_INS_WFMAXDB = 2312 , SYSZ_INS_WFMAXSB = 2313 , SYSZ_INS_WFMAXXB = 2314 , SYSZ_INS_WFMDB = 2315 , SYSZ_INS_WFMINDB = 2316 , SYSZ_INS_WFMINSB = 2317 , SYSZ_INS_WFMINXB = 2318 , SYSZ_INS_WFMSB = 2319 , SYSZ_INS_WFMSDB = 2320 , SYSZ_INS_WFMSSB = 2321 , SYSZ_INS_WFMSXB = 2322 , SYSZ_INS_WFMXB = 2323 , SYSZ_INS_WFNMADB = 2324 , SYSZ_INS_WFNMASB = 2325 , SYSZ_INS_WFNMAXB = 2326 , SYSZ_INS_WFNMSDB = 2327 , SYSZ_INS_WFNMSSB = 2328 , SYSZ_INS_WFNMSXB = 2329 , SYSZ_INS_WFPSODB = 2330 , SYSZ_INS_WFPSOSB = 2331 , SYSZ_INS_WFPSOXB = 2332 , SYSZ_INS_WFSDB = 2333 , SYSZ_INS_WFSQDB = 2334 , SYSZ_INS_WFSQSB = 2335 , SYSZ_INS_WFSQXB = 2336 , SYSZ_INS_WFSSB = 2337 , SYSZ_INS_WFSXB = 2338 , SYSZ_INS_WFTCIDB = 2339 , SYSZ_INS_WFTCISB = 2340 , SYSZ_INS_WFTCIXB = 2341 , SYSZ_INS_WLDEB = 2342 , SYSZ_INS_WLEDB = 2343 , SYSZ_INS_XSCH = 2344 , SYSZ_INS_ZAP = 2345 , SYSZ_INS_ENDING = 2346 , } # [repr (u32)] # [doc = " Group of SystemZ instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn_group { # [doc = "< = CS_GRP_INVALID"] SYSZ_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SYSZ_GRP_JUMP = 1 , SYSZ_GRP_DISTINCTOPS = 128 , SYSZ_GRP_FPEXTENSION = 129 , SYSZ_GRP_HIGHWORD = 130 , SYSZ_GRP_INTERLOCKEDACCESS1 = 131 , SYSZ_GRP_LOADSTOREONCOND = 132 , SYSZ_GRP_DFPPACKEDCONVERSION = 133 , SYSZ_GRP_DFPZONEDCONVERSION = 134 , SYSZ_GRP_ENHANCEDDAT2 = 135 , SYSZ_GRP_EXECUTIONHINT = 136 , SYSZ_GRP_GUARDEDSTORAGE = 137 , SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 , SYSZ_GRP_LOADANDTRAP = 139 , SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 , SYSZ_GRP_LOADSTOREONCOND2 = 141 , SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 , SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 , SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 , SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 , SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 , SYSZ_GRP_NOVECTOR = 149 , SYSZ_GRP_POPULATIONCOUNT = 150 , SYSZ_GRP_PROCESSORASSIST = 151 , SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 , SYSZ_GRP_TRANSACTIONALEXECUTION = 153 , SYSZ_GRP_VECTOR = 154 , SYSZ_GRP_VECTORENHANCEMENTS1 = 155 , SYSZ_GRP_VECTORPACKEDDECIMAL = 156 , SYSZ_GRP_ENDING = 157 , } # [repr (u32)] # [doc = " X86 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_reg { X86_REG_INVALID = 0 , X86_REG_AH = 1 , X86_REG_AL = 2 , X86_REG_AX = 3 , X86_REG_BH = 4 , X86_REG_BL = 5 , X86_REG_BP = 6 , X86_REG_BPL = 7 , X86_REG_BX = 8 , X86_REG_CH = 9 , X86_REG_CL = 10 , X86_REG_CS = 11 , X86_REG_CX = 12 , X86_REG_DH = 13 , X86_REG_DI = 14 , X86_REG_DIL = 15 , X86_REG_DL = 16 , X86_REG_DS = 17 , X86_REG_DX = 18 , X86_REG_EAX = 19 , X86_REG_EBP = 20 , X86_REG_EBX = 21 , X86_REG_ECX = 22 , X86_REG_EDI = 23 , X86_REG_EDX = 24 , X86_REG_EFLAGS = 25 , X86_REG_EIP = 26 , X86_REG_EIZ = 27 , X86_REG_ES = 28 , X86_REG_ESI = 29 , X86_REG_ESP = 30 , X86_REG_FPSW = 31 , X86_REG_FS = 32 , X86_REG_GS = 33 , X86_REG_IP = 34 , X86_REG_RAX = 35 , X86_REG_RBP = 36 , X86_REG_RBX = 37 , X86_REG_RCX = 38 , X86_REG_RDI = 39 , X86_REG_RDX = 40 , X86_REG_RIP = 41 , X86_REG_RIZ = 42 , X86_REG_RSI = 43 , X86_REG_RSP = 44 , X86_REG_SI = 45 , X86_REG_SIL = 46 , X86_REG_SP = 47 , X86_REG_SPL = 48 , X86_REG_SS = 49 , X86_REG_CR0 = 50 , X86_REG_CR1 = 51 , X86_REG_CR2 = 52 , X86_REG_CR3 = 53 , X86_REG_CR4 = 54 , X86_REG_CR5 = 55 , X86_REG_CR6 = 56 , X86_REG_CR7 = 57 , X86_REG_CR8 = 58 , X86_REG_CR9 = 59 , X86_REG_CR10 = 60 , X86_REG_CR11 = 61 , X86_REG_CR12 = 62 , X86_REG_CR13 = 63 , X86_REG_CR14 = 64 , X86_REG_CR15 = 65 , X86_REG_DR0 = 66 , X86_REG_DR1 = 67 , X86_REG_DR2 = 68 , X86_REG_DR3 = 69 , X86_REG_DR4 = 70 , X86_REG_DR5 = 71 , X86_REG_DR6 = 72 , X86_REG_DR7 = 73 , X86_REG_DR8 = 74 , X86_REG_DR9 = 75 , X86_REG_DR10 = 76 , X86_REG_DR11 = 77 , X86_REG_DR12 = 78 , X86_REG_DR13 = 79 , X86_REG_DR14 = 80 , X86_REG_DR15 = 81 , X86_REG_FP0 = 82 , X86_REG_FP1 = 83 , X86_REG_FP2 = 84 , X86_REG_FP3 = 85 , X86_REG_FP4 = 86 , X86_REG_FP5 = 87 , X86_REG_FP6 = 88 , X86_REG_FP7 = 89 , X86_REG_K0 = 90 , X86_REG_K1 = 91 , X86_REG_K2 = 92 , X86_REG_K3 = 93 , X86_REG_K4 = 94 , X86_REG_K5 = 95 , X86_REG_K6 = 96 , X86_REG_K7 = 97 , X86_REG_MM0 = 98 , X86_REG_MM1 = 99 , X86_REG_MM2 = 100 , X86_REG_MM3 = 101 , X86_REG_MM4 = 102 , X86_REG_MM5 = 103 , X86_REG_MM6 = 104 , X86_REG_MM7 = 105 , X86_REG_R8 = 106 , X86_REG_R9 = 107 , X86_REG_R10 = 108 , X86_REG_R11 = 109 , X86_REG_R12 = 110 , X86_REG_R13 = 111 , X86_REG_R14 = 112 , X86_REG_R15 = 113 , X86_REG_ST0 = 114 , X86_REG_ST1 = 115 , X86_REG_ST2 = 116 , X86_REG_ST3 = 117 , X86_REG_ST4 = 118 , X86_REG_ST5 = 119 , X86_REG_ST6 = 120 , X86_REG_ST7 = 121 , X86_REG_XMM0 = 122 , X86_REG_XMM1 = 123 , X86_REG_XMM2 = 124 , X86_REG_XMM3 = 125 , X86_REG_XMM4 = 126 , X86_REG_XMM5 = 127 , X86_REG_XMM6 = 128 , X86_REG_XMM7 = 129 , X86_REG_XMM8 = 130 , X86_REG_XMM9 = 131 , X86_REG_XMM10 = 132 , X86_REG_XMM11 = 133 , X86_REG_XMM12 = 134 , X86_REG_XMM13 = 135 , X86_REG_XMM14 = 136 , X86_REG_XMM15 = 137 , X86_REG_XMM16 = 138 , X86_REG_XMM17 = 139 , X86_REG_XMM18 = 140 , X86_REG_XMM19 = 141 , X86_REG_XMM20 = 142 , X86_REG_XMM21 = 143 , X86_REG_XMM22 = 144 , X86_REG_XMM23 = 145 , X86_REG_XMM24 = 146 , X86_REG_XMM25 = 147 , X86_REG_XMM26 = 148 , X86_REG_XMM27 = 149 , X86_REG_XMM28 = 150 , X86_REG_XMM29 = 151 , X86_REG_XMM30 = 152 , X86_REG_XMM31 = 153 , X86_REG_YMM0 = 154 , X86_REG_YMM1 = 155 , X86_REG_YMM2 = 156 , X86_REG_YMM3 = 157 , X86_REG_YMM4 = 158 , X86_REG_YMM5 = 159 , X86_REG_YMM6 = 160 , X86_REG_YMM7 = 161 , X86_REG_YMM8 = 162 , X86_REG_YMM9 = 163 , X86_REG_YMM10 = 164 , X86_REG_YMM11 = 165 , X86_REG_YMM12 = 166 , X86_REG_YMM13 = 167 , X86_REG_YMM14 = 168 , X86_REG_YMM15 = 169 , X86_REG_YMM16 = 170 , X86_REG_YMM17 = 171 , X86_REG_YMM18 = 172 , X86_REG_YMM19 = 173 , X86_REG_YMM20 = 174 , X86_REG_YMM21 = 175 , X86_REG_YMM22 = 176 , X86_REG_YMM23 = 177 , X86_REG_YMM24 = 178 , X86_REG_YMM25 = 179 , X86_REG_YMM26 = 180 , X86_REG_YMM27 = 181 , X86_REG_YMM28 = 182 , X86_REG_YMM29 = 183 , X86_REG_YMM30 = 184 , X86_REG_YMM31 = 185 , X86_REG_ZMM0 = 186 , X86_REG_ZMM1 = 187 , X86_REG_ZMM2 = 188 , X86_REG_ZMM3 = 189 , X86_REG_ZMM4 = 190 , X86_REG_ZMM5 = 191 , X86_REG_ZMM6 = 192 , X86_REG_ZMM7 = 193 , X86_REG_ZMM8 = 194 , X86_REG_ZMM9 = 195 , X86_REG_ZMM10 = 196 , X86_REG_ZMM11 = 197 , X86_REG_ZMM12 = 198 , X86_REG_ZMM13 = 199 , X86_REG_ZMM14 = 200 , X86_REG_ZMM15 = 201 , X86_REG_ZMM16 = 202 , X86_REG_ZMM17 = 203 , X86_REG_ZMM18 = 204 , X86_REG_ZMM19 = 205 , X86_REG_ZMM20 = 206 , X86_REG_ZMM21 = 207 , X86_REG_ZMM22 = 208 , X86_REG_ZMM23 = 209 , X86_REG_ZMM24 = 210 , X86_REG_ZMM25 = 211 , X86_REG_ZMM26 = 212 , X86_REG_ZMM27 = 213 , X86_REG_ZMM28 = 214 , X86_REG_ZMM29 = 215 , X86_REG_ZMM30 = 216 , X86_REG_ZMM31 = 217 , X86_REG_R8B = 218 , X86_REG_R9B = 219 , X86_REG_R10B = 220 , X86_REG_R11B = 221 , X86_REG_R12B = 222 , X86_REG_R13B = 223 , X86_REG_R14B = 224 , X86_REG_R15B = 225 , X86_REG_R8D = 226 , X86_REG_R9D = 227 , X86_REG_R10D = 228 , X86_REG_R11D = 229 , X86_REG_R12D = 230 , X86_REG_R13D = 231 , X86_REG_R14D = 232 , X86_REG_R15D = 233 , X86_REG_R8W = 234 , X86_REG_R9W = 235 , X86_REG_R10W = 236 , X86_REG_R11W = 237 , X86_REG_R12W = 238 , X86_REG_R13W = 239 , X86_REG_R14W = 240 , X86_REG_R15W = 241 , X86_REG_BND0 = 242 , X86_REG_BND1 = 243 , X86_REG_BND2 = 244 , X86_REG_BND3 = 245 , X86_REG_ENDING = 246 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] X86_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] X86_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] X86_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] X86_OP_MEM = 3 , } # [repr (u32)] # [doc = " XOP Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_xop_cc { # [doc = "< Uninitialized."] X86_XOP_CC_INVALID = 0 , X86_XOP_CC_LT = 1 , X86_XOP_CC_LE = 2 , X86_XOP_CC_GT = 3 , X86_XOP_CC_GE = 4 , X86_XOP_CC_EQ = 5 , X86_XOP_CC_NEQ = 6 , X86_XOP_CC_FALSE = 7 , X86_XOP_CC_TRUE = 8 , } # [repr (u32)] # [doc = " AVX broadcast type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_bcast { # [doc = "< Uninitialized."] X86_AVX_BCAST_INVALID = 0 , # [doc = "< AVX512 broadcast type {1to2}"] X86_AVX_BCAST_2 = 1 , # [doc = "< AVX512 broadcast type {1to4}"] X86_AVX_BCAST_4 = 2 , # [doc = "< AVX512 broadcast type {1to8}"] X86_AVX_BCAST_8 = 3 , # [doc = "< AVX512 broadcast type {1to16}"] X86_AVX_BCAST_16 = 4 , } # [repr (u32)] # [doc = " SSE Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_sse_cc { # [doc = "< Uninitialized."] X86_SSE_CC_INVALID = 0 , X86_SSE_CC_EQ = 1 , X86_SSE_CC_LT = 2 , X86_SSE_CC_LE = 3 , X86_SSE_CC_UNORD = 4 , X86_SSE_CC_NEQ = 5 , X86_SSE_CC_NLT = 6 , X86_SSE_CC_NLE = 7 , X86_SSE_CC_ORD = 8 , } # [repr (u32)] # [doc = " AVX Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_cc { # [doc = "< Uninitialized."] X86_AVX_CC_INVALID = 0 , X86_AVX_CC_EQ = 1 , X86_AVX_CC_LT = 2 , X86_AVX_CC_LE = 3 , X86_AVX_CC_UNORD = 4 , X86_AVX_CC_NEQ = 5 , X86_AVX_CC_NLT = 6 , X86_AVX_CC_NLE = 7 , X86_AVX_CC_ORD = 8 , X86_AVX_CC_EQ_UQ = 9 , X86_AVX_CC_NGE = 10 , X86_AVX_CC_NGT = 11 , X86_AVX_CC_FALSE = 12 , X86_AVX_CC_NEQ_OQ = 13 , X86_AVX_CC_GE = 14 , X86_AVX_CC_GT = 15 , X86_AVX_CC_TRUE = 16 , X86_AVX_CC_EQ_OS = 17 , X86_AVX_CC_LT_OQ = 18 , X86_AVX_CC_LE_OQ = 19 , X86_AVX_CC_UNORD_S = 20 , X86_AVX_CC_NEQ_US = 21 , X86_AVX_CC_NLT_UQ = 22 , X86_AVX_CC_NLE_UQ = 23 , X86_AVX_CC_ORD_S = 24 , X86_AVX_CC_EQ_US = 25 , X86_AVX_CC_NGE_UQ = 26 , X86_AVX_CC_NGT_UQ = 27 , X86_AVX_CC_FALSE_OS = 28 , X86_AVX_CC_NEQ_OS = 29 , X86_AVX_CC_GE_OQ = 30 , X86_AVX_CC_GT_OQ = 31 , X86_AVX_CC_TRUE_US = 32 , } # [repr (u32)] # [doc = " AVX static rounding mode type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_rm { # [doc = "< Uninitialized."] X86_AVX_RM_INVALID = 0 , # [doc = "< Round to nearest"] X86_AVX_RM_RN = 1 , # [doc = "< Round down"] X86_AVX_RM_RD = 2 , # [doc = "< Round up"] X86_AVX_RM_RU = 3 , # [doc = "< Round toward zero"] X86_AVX_RM_RZ = 4 , } impl x86_prefix { pub const X86_PREFIX_REPE : x86_prefix = x86_prefix :: X86_PREFIX_REP ; } # [repr (u32)] # [doc = " Instruction prefixes - to be used in cs_x86.prefix[]"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_prefix { # [doc = "< lock (cs_x86.prefix[0]"] X86_PREFIX_LOCK = 240 , # [doc = "< rep (cs_x86.prefix[0]"] X86_PREFIX_REP = 243 , # [doc = "< repne/repnz (cs_x86.prefix[0]"] X86_PREFIX_REPNE = 242 , # [doc = "< segment override CS (cs_x86.prefix[1]"] X86_PREFIX_CS = 46 , # [doc = "< segment override SS (cs_x86.prefix[1]"] X86_PREFIX_SS = 54 , # [doc = "< segment override DS (cs_x86.prefix[1]"] X86_PREFIX_DS = 62 , # [doc = "< segment override ES (cs_x86.prefix[1]"] X86_PREFIX_ES = 38 , # [doc = "< segment override FS (cs_x86.prefix[1]"] X86_PREFIX_FS = 100 , # [doc = "< segment override GS (cs_x86.prefix[1]"] X86_PREFIX_GS = 101 , # [doc = "< operand-size override (cs_x86.prefix[2]"] X86_PREFIX_OPSIZE = 102 , # [doc = "< address-size override (cs_x86.prefix[3]"] X86_PREFIX_ADDRSIZE = 103 , } # [doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct x86_op_mem { # [doc = "< segment register (or X86_REG_INVALID if irrelevant)"] pub segment : x86_reg , # [doc = "< base register (or X86_REG_INVALID if irrelevant)"] pub base : x86_reg , # [doc = "< index register (or X86_REG_INVALID if irrelevant)"] pub index : x86_reg , # [doc = "< scale for index register"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of x86_op_mem"] [:: std :: mem :: size_of :: < x86_op_mem > () - 24usize] ; ["Alignment of x86_op_mem"] [:: std :: mem :: align_of :: < x86_op_mem > () - 8usize] ; ["Offset of field: x86_op_mem::segment"] [:: std :: mem :: offset_of ! (x86_op_mem , segment) - 0usize] ; ["Offset of field: x86_op_mem::base"] [:: std :: mem :: offset_of ! (x86_op_mem , base) - 4usize] ; ["Offset of field: x86_op_mem::index"] [:: std :: mem :: offset_of ! (x86_op_mem , index) - 8usize] ; ["Offset of field: x86_op_mem::scale"] [:: std :: mem :: offset_of ! (x86_op_mem , scale) - 12usize] ; ["Offset of field: x86_op_mem::disp"] [:: std :: mem :: offset_of ! (x86_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86_op { # [doc = "< operand type"] pub type_ : x86_op_type , pub __bindgen_anon_1 : cs_x86_op__bindgen_ty_1 , # [doc = " size of this operand (in bytes)."] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " AVX broadcast type, or 0 if irrelevant"] pub avx_bcast : x86_avx_bcast , # [doc = " AVX zero opmask {z}"] pub avx_zero_opmask : bool , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : x86_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : x86_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op"] [:: std :: mem :: size_of :: < cs_x86_op > () - 48usize] ; ["Alignment of cs_x86_op"] [:: std :: mem :: align_of :: < cs_x86_op > () - 8usize] ; ["Offset of field: cs_x86_op::type_"] [:: std :: mem :: offset_of ! (cs_x86_op , type_) - 0usize] ; ["Offset of field: cs_x86_op::size"] [:: std :: mem :: offset_of ! (cs_x86_op , size) - 32usize] ; ["Offset of field: cs_x86_op::access"] [:: std :: mem :: offset_of ! (cs_x86_op , access) - 33usize] ; ["Offset of field: cs_x86_op::avx_bcast"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_bcast) - 36usize] ; ["Offset of field: cs_x86_op::avx_zero_opmask"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_zero_opmask) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask) } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_x86_encoding { # [doc = " ModR/M offset, or 0 when irrelevant"] pub modrm_offset : u8 , # [doc = " Displacement offset, or 0 when irrelevant."] pub disp_offset : u8 , pub disp_size : u8 , # [doc = " Immediate offset, or 0 when irrelevant."] pub imm_offset : u8 , pub imm_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_encoding"] [:: std :: mem :: size_of :: < cs_x86_encoding > () - 5usize] ; ["Alignment of cs_x86_encoding"] [:: std :: mem :: align_of :: < cs_x86_encoding > () - 1usize] ; ["Offset of field: cs_x86_encoding::modrm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , modrm_offset) - 0usize] ; ["Offset of field: cs_x86_encoding::disp_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_offset) - 1usize] ; ["Offset of field: cs_x86_encoding::disp_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_size) - 2usize] ; ["Offset of field: cs_x86_encoding::imm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_offset) - 3usize] ; ["Offset of field: cs_x86_encoding::imm_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_size) - 4usize] ; } ; # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86 { # [doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"] pub prefix : [u8 ; 4usize] , # [doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."] pub opcode : [u8 ; 4usize] , # [doc = " REX prefix: only a non-zero value is relevant for x86_64"] pub rex : u8 , # [doc = " Address size, which can be overridden with above prefix[5]."] pub addr_size : u8 , # [doc = " ModR/M byte"] pub modrm : u8 , # [doc = " SIB value, or 0 when irrelevant."] pub sib : u8 , # [doc = " Displacement value, valid if encoding.disp_offset != 0"] pub disp : i64 , # [doc = " SIB index register, or X86_REG_INVALID when irrelevant."] pub sib_index : x86_reg , # [doc = " SIB scale, only applicable if sib_index is valid."] pub sib_scale : i8 , # [doc = " SIB base register, or X86_REG_INVALID when irrelevant."] pub sib_base : x86_reg , # [doc = " XOP Code Condition"] pub xop_cc : x86_xop_cc , # [doc = " SSE Code Condition"] pub sse_cc : x86_sse_cc , # [doc = " AVX Code Condition"] pub avx_cc : x86_avx_cc , # [doc = " AVX Suppress all Exception"] pub avx_sae : bool , # [doc = " AVX static rounding mode"] pub avx_rm : x86_avx_rm , pub __bindgen_anon_1 : cs_x86__bindgen_ty_1 , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_x86_op ; 8usize] , # [doc = "< encoding information"] pub encoding : cs_x86_encoding , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86__bindgen_ty_1 { # [doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"] pub eflags : u64 , # [doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"] pub fpu_flags : u64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_x86__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86__bindgen_ty_1::eflags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , eflags) - 0usize] ; ["Offset of field: cs_x86__bindgen_ty_1::fpu_flags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , fpu_flags) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86"] [:: std :: mem :: size_of :: < cs_x86 > () - 464usize] ; ["Alignment of cs_x86"] [:: std :: mem :: align_of :: < cs_x86 > () - 8usize] ; ["Offset of field: cs_x86::prefix"] [:: std :: mem :: offset_of ! (cs_x86 , prefix) - 0usize] ; ["Offset of field: cs_x86::opcode"] [:: std :: mem :: offset_of ! (cs_x86 , opcode) - 4usize] ; ["Offset of field: cs_x86::rex"] [:: std :: mem :: offset_of ! (cs_x86 , rex) - 8usize] ; ["Offset of field: cs_x86::addr_size"] [:: std :: mem :: offset_of ! (cs_x86 , addr_size) - 9usize] ; ["Offset of field: cs_x86::modrm"] [:: std :: mem :: offset_of ! (cs_x86 , modrm) - 10usize] ; ["Offset of field: cs_x86::sib"] [:: std :: mem :: offset_of ! (cs_x86 , sib) - 11usize] ; ["Offset of field: cs_x86::disp"] [:: std :: mem :: offset_of ! (cs_x86 , disp) - 16usize] ; ["Offset of field: cs_x86::sib_index"] [:: std :: mem :: offset_of ! (cs_x86 , sib_index) - 24usize] ; ["Offset of field: cs_x86::sib_scale"] [:: std :: mem :: offset_of ! (cs_x86 , sib_scale) - 28usize] ; ["Offset of field: cs_x86::sib_base"] [:: std :: mem :: offset_of ! (cs_x86 , sib_base) - 32usize] ; ["Offset of field: cs_x86::xop_cc"] [:: std :: mem :: offset_of ! (cs_x86 , xop_cc) - 36usize] ; ["Offset of field: cs_x86::sse_cc"] [:: std :: mem :: offset_of ! (cs_x86 , sse_cc) - 40usize] ; ["Offset of field: cs_x86::avx_cc"] [:: std :: mem :: offset_of ! (cs_x86 , avx_cc) - 44usize] ; ["Offset of field: cs_x86::avx_sae"] [:: std :: mem :: offset_of ! (cs_x86 , avx_sae) - 48usize] ; ["Offset of field: cs_x86::avx_rm"] [:: std :: mem :: offset_of ! (cs_x86 , avx_rm) - 52usize] ; ["Offset of field: cs_x86::op_count"] [:: std :: mem :: offset_of ! (cs_x86 , op_count) - 64usize] ; ["Offset of field: cs_x86::operands"] [:: std :: mem :: offset_of ! (cs_x86 , operands) - 72usize] ; ["Offset of field: cs_x86::encoding"] [:: std :: mem :: offset_of ! (cs_x86 , encoding) - 456usize] ; } ; impl :: std :: fmt :: Debug for cs_x86 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding) } } # [repr (u32)] # [doc = " X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn { X86_INS_INVALID = 0 , X86_INS_AAA = 1 , X86_INS_AAD = 2 , X86_INS_AAM = 3 , X86_INS_AAS = 4 , X86_INS_FABS = 5 , X86_INS_ADC = 6 , X86_INS_ADCX = 7 , X86_INS_ADD = 8 , X86_INS_ADDPD = 9 , X86_INS_ADDPS = 10 , X86_INS_ADDSD = 11 , X86_INS_ADDSS = 12 , X86_INS_ADDSUBPD = 13 , X86_INS_ADDSUBPS = 14 , X86_INS_FADD = 15 , X86_INS_FIADD = 16 , X86_INS_ADOX = 17 , X86_INS_AESDECLAST = 18 , X86_INS_AESDEC = 19 , X86_INS_AESENCLAST = 20 , X86_INS_AESENC = 21 , X86_INS_AESIMC = 22 , X86_INS_AESKEYGENASSIST = 23 , X86_INS_AND = 24 , X86_INS_ANDN = 25 , X86_INS_ANDNPD = 26 , X86_INS_ANDNPS = 27 , X86_INS_ANDPD = 28 , X86_INS_ANDPS = 29 , X86_INS_ARPL = 30 , X86_INS_BEXTR = 31 , X86_INS_BLCFILL = 32 , X86_INS_BLCI = 33 , X86_INS_BLCIC = 34 , X86_INS_BLCMSK = 35 , X86_INS_BLCS = 36 , X86_INS_BLENDPD = 37 , X86_INS_BLENDPS = 38 , X86_INS_BLENDVPD = 39 , X86_INS_BLENDVPS = 40 , X86_INS_BLSFILL = 41 , X86_INS_BLSI = 42 , X86_INS_BLSIC = 43 , X86_INS_BLSMSK = 44 , X86_INS_BLSR = 45 , X86_INS_BNDCL = 46 , X86_INS_BNDCN = 47 , X86_INS_BNDCU = 48 , X86_INS_BNDLDX = 49 , X86_INS_BNDMK = 50 , X86_INS_BNDMOV = 51 , X86_INS_BNDSTX = 52 , X86_INS_BOUND = 53 , X86_INS_BSF = 54 , X86_INS_BSR = 55 , X86_INS_BSWAP = 56 , X86_INS_BT = 57 , X86_INS_BTC = 58 , X86_INS_BTR = 59 , X86_INS_BTS = 60 , X86_INS_BZHI = 61 , X86_INS_CALL = 62 , X86_INS_CBW = 63 , X86_INS_CDQ = 64 , X86_INS_CDQE = 65 , X86_INS_FCHS = 66 , X86_INS_CLAC = 67 , X86_INS_CLC = 68 , X86_INS_CLD = 69 , X86_INS_CLDEMOTE = 70 , X86_INS_CLFLUSH = 71 , X86_INS_CLFLUSHOPT = 72 , X86_INS_CLGI = 73 , X86_INS_CLI = 74 , X86_INS_CLRSSBSY = 75 , X86_INS_CLTS = 76 , X86_INS_CLWB = 77 , X86_INS_CLZERO = 78 , X86_INS_CMC = 79 , X86_INS_CMOVA = 80 , X86_INS_CMOVAE = 81 , X86_INS_CMOVB = 82 , X86_INS_CMOVBE = 83 , X86_INS_FCMOVBE = 84 , X86_INS_FCMOVB = 85 , X86_INS_CMOVE = 86 , X86_INS_FCMOVE = 87 , X86_INS_CMOVG = 88 , X86_INS_CMOVGE = 89 , X86_INS_CMOVL = 90 , X86_INS_CMOVLE = 91 , X86_INS_FCMOVNBE = 92 , X86_INS_FCMOVNB = 93 , X86_INS_CMOVNE = 94 , X86_INS_FCMOVNE = 95 , X86_INS_CMOVNO = 96 , X86_INS_CMOVNP = 97 , X86_INS_FCMOVNU = 98 , X86_INS_FCMOVNP = 99 , X86_INS_CMOVNS = 100 , X86_INS_CMOVO = 101 , X86_INS_CMOVP = 102 , X86_INS_FCMOVU = 103 , X86_INS_CMOVS = 104 , X86_INS_CMP = 105 , X86_INS_CMPPD = 106 , X86_INS_CMPPS = 107 , X86_INS_CMPSB = 108 , X86_INS_CMPSD = 109 , X86_INS_CMPSQ = 110 , X86_INS_CMPSS = 111 , X86_INS_CMPSW = 112 , X86_INS_CMPXCHG16B = 113 , X86_INS_CMPXCHG = 114 , X86_INS_CMPXCHG8B = 115 , X86_INS_COMISD = 116 , X86_INS_COMISS = 117 , X86_INS_FCOMP = 118 , X86_INS_FCOMPI = 119 , X86_INS_FCOMI = 120 , X86_INS_FCOM = 121 , X86_INS_FCOS = 122 , X86_INS_CPUID = 123 , X86_INS_CQO = 124 , X86_INS_CRC32 = 125 , X86_INS_CVTDQ2PD = 126 , X86_INS_CVTDQ2PS = 127 , X86_INS_CVTPD2DQ = 128 , X86_INS_CVTPD2PS = 129 , X86_INS_CVTPS2DQ = 130 , X86_INS_CVTPS2PD = 131 , X86_INS_CVTSD2SI = 132 , X86_INS_CVTSD2SS = 133 , X86_INS_CVTSI2SD = 134 , X86_INS_CVTSI2SS = 135 , X86_INS_CVTSS2SD = 136 , X86_INS_CVTSS2SI = 137 , X86_INS_CVTTPD2DQ = 138 , X86_INS_CVTTPS2DQ = 139 , X86_INS_CVTTSD2SI = 140 , X86_INS_CVTTSS2SI = 141 , X86_INS_CWD = 142 , X86_INS_CWDE = 143 , X86_INS_DAA = 144 , X86_INS_DAS = 145 , X86_INS_DATA16 = 146 , X86_INS_DEC = 147 , X86_INS_DIV = 148 , X86_INS_DIVPD = 149 , X86_INS_DIVPS = 150 , X86_INS_FDIVR = 151 , X86_INS_FIDIVR = 152 , X86_INS_FDIVRP = 153 , X86_INS_DIVSD = 154 , X86_INS_DIVSS = 155 , X86_INS_FDIV = 156 , X86_INS_FIDIV = 157 , X86_INS_FDIVP = 158 , X86_INS_DPPD = 159 , X86_INS_DPPS = 160 , X86_INS_ENCLS = 161 , X86_INS_ENCLU = 162 , X86_INS_ENCLV = 163 , X86_INS_ENDBR32 = 164 , X86_INS_ENDBR64 = 165 , X86_INS_ENTER = 166 , X86_INS_EXTRACTPS = 167 , X86_INS_EXTRQ = 168 , X86_INS_F2XM1 = 169 , X86_INS_LCALL = 170 , X86_INS_LJMP = 171 , X86_INS_JMP = 172 , X86_INS_FBLD = 173 , X86_INS_FBSTP = 174 , X86_INS_FCOMPP = 175 , X86_INS_FDECSTP = 176 , X86_INS_FDISI8087_NOP = 177 , X86_INS_FEMMS = 178 , X86_INS_FENI8087_NOP = 179 , X86_INS_FFREE = 180 , X86_INS_FFREEP = 181 , X86_INS_FICOM = 182 , X86_INS_FICOMP = 183 , X86_INS_FINCSTP = 184 , X86_INS_FLDCW = 185 , X86_INS_FLDENV = 186 , X86_INS_FLDL2E = 187 , X86_INS_FLDL2T = 188 , X86_INS_FLDLG2 = 189 , X86_INS_FLDLN2 = 190 , X86_INS_FLDPI = 191 , X86_INS_FNCLEX = 192 , X86_INS_FNINIT = 193 , X86_INS_FNOP = 194 , X86_INS_FNSTCW = 195 , X86_INS_FNSTSW = 196 , X86_INS_FPATAN = 197 , X86_INS_FSTPNCE = 198 , X86_INS_FPREM = 199 , X86_INS_FPREM1 = 200 , X86_INS_FPTAN = 201 , X86_INS_FRNDINT = 202 , X86_INS_FRSTOR = 203 , X86_INS_FNSAVE = 204 , X86_INS_FSCALE = 205 , X86_INS_FSETPM = 206 , X86_INS_FSINCOS = 207 , X86_INS_FNSTENV = 208 , X86_INS_FXAM = 209 , X86_INS_FXRSTOR = 210 , X86_INS_FXRSTOR64 = 211 , X86_INS_FXSAVE = 212 , X86_INS_FXSAVE64 = 213 , X86_INS_FXTRACT = 214 , X86_INS_FYL2X = 215 , X86_INS_FYL2XP1 = 216 , X86_INS_GETSEC = 217 , X86_INS_GF2P8AFFINEINVQB = 218 , X86_INS_GF2P8AFFINEQB = 219 , X86_INS_GF2P8MULB = 220 , X86_INS_HADDPD = 221 , X86_INS_HADDPS = 222 , X86_INS_HLT = 223 , X86_INS_HSUBPD = 224 , X86_INS_HSUBPS = 225 , X86_INS_IDIV = 226 , X86_INS_FILD = 227 , X86_INS_IMUL = 228 , X86_INS_IN = 229 , X86_INS_INC = 230 , X86_INS_INCSSPD = 231 , X86_INS_INCSSPQ = 232 , X86_INS_INSB = 233 , X86_INS_INSERTPS = 234 , X86_INS_INSERTQ = 235 , X86_INS_INSD = 236 , X86_INS_INSW = 237 , X86_INS_INT = 238 , X86_INS_INT1 = 239 , X86_INS_INT3 = 240 , X86_INS_INTO = 241 , X86_INS_INVD = 242 , X86_INS_INVEPT = 243 , X86_INS_INVLPG = 244 , X86_INS_INVLPGA = 245 , X86_INS_INVPCID = 246 , X86_INS_INVVPID = 247 , X86_INS_IRET = 248 , X86_INS_IRETD = 249 , X86_INS_IRETQ = 250 , X86_INS_FISTTP = 251 , X86_INS_FIST = 252 , X86_INS_FISTP = 253 , X86_INS_JAE = 254 , X86_INS_JA = 255 , X86_INS_JBE = 256 , X86_INS_JB = 257 , X86_INS_JCXZ = 258 , X86_INS_JECXZ = 259 , X86_INS_JE = 260 , X86_INS_JGE = 261 , X86_INS_JG = 262 , X86_INS_JLE = 263 , X86_INS_JL = 264 , X86_INS_JNE = 265 , X86_INS_JNO = 266 , X86_INS_JNP = 267 , X86_INS_JNS = 268 , X86_INS_JO = 269 , X86_INS_JP = 270 , X86_INS_JRCXZ = 271 , X86_INS_JS = 272 , X86_INS_KADDB = 273 , X86_INS_KADDD = 274 , X86_INS_KADDQ = 275 , X86_INS_KADDW = 276 , X86_INS_KANDB = 277 , X86_INS_KANDD = 278 , X86_INS_KANDNB = 279 , X86_INS_KANDND = 280 , X86_INS_KANDNQ = 281 , X86_INS_KANDNW = 282 , X86_INS_KANDQ = 283 , X86_INS_KANDW = 284 , X86_INS_KMOVB = 285 , X86_INS_KMOVD = 286 , X86_INS_KMOVQ = 287 , X86_INS_KMOVW = 288 , X86_INS_KNOTB = 289 , X86_INS_KNOTD = 290 , X86_INS_KNOTQ = 291 , X86_INS_KNOTW = 292 , X86_INS_KORB = 293 , X86_INS_KORD = 294 , X86_INS_KORQ = 295 , X86_INS_KORTESTB = 296 , X86_INS_KORTESTD = 297 , X86_INS_KORTESTQ = 298 , X86_INS_KORTESTW = 299 , X86_INS_KORW = 300 , X86_INS_KSHIFTLB = 301 , X86_INS_KSHIFTLD = 302 , X86_INS_KSHIFTLQ = 303 , X86_INS_KSHIFTLW = 304 , X86_INS_KSHIFTRB = 305 , X86_INS_KSHIFTRD = 306 , X86_INS_KSHIFTRQ = 307 , X86_INS_KSHIFTRW = 308 , X86_INS_KTESTB = 309 , X86_INS_KTESTD = 310 , X86_INS_KTESTQ = 311 , X86_INS_KTESTW = 312 , X86_INS_KUNPCKBW = 313 , X86_INS_KUNPCKDQ = 314 , X86_INS_KUNPCKWD = 315 , X86_INS_KXNORB = 316 , X86_INS_KXNORD = 317 , X86_INS_KXNORQ = 318 , X86_INS_KXNORW = 319 , X86_INS_KXORB = 320 , X86_INS_KXORD = 321 , X86_INS_KXORQ = 322 , X86_INS_KXORW = 323 , X86_INS_LAHF = 324 , X86_INS_LAR = 325 , X86_INS_LDDQU = 326 , X86_INS_LDMXCSR = 327 , X86_INS_LDS = 328 , X86_INS_FLDZ = 329 , X86_INS_FLD1 = 330 , X86_INS_FLD = 331 , X86_INS_LEA = 332 , X86_INS_LEAVE = 333 , X86_INS_LES = 334 , X86_INS_LFENCE = 335 , X86_INS_LFS = 336 , X86_INS_LGDT = 337 , X86_INS_LGS = 338 , X86_INS_LIDT = 339 , X86_INS_LLDT = 340 , X86_INS_LLWPCB = 341 , X86_INS_LMSW = 342 , X86_INS_LOCK = 343 , X86_INS_LODSB = 344 , X86_INS_LODSD = 345 , X86_INS_LODSQ = 346 , X86_INS_LODSW = 347 , X86_INS_LOOP = 348 , X86_INS_LOOPE = 349 , X86_INS_LOOPNE = 350 , X86_INS_RETF = 351 , X86_INS_RETFQ = 352 , X86_INS_LSL = 353 , X86_INS_LSS = 354 , X86_INS_LTR = 355 , X86_INS_LWPINS = 356 , X86_INS_LWPVAL = 357 , X86_INS_LZCNT = 358 , X86_INS_MASKMOVDQU = 359 , X86_INS_MAXPD = 360 , X86_INS_MAXPS = 361 , X86_INS_MAXSD = 362 , X86_INS_MAXSS = 363 , X86_INS_MFENCE = 364 , X86_INS_MINPD = 365 , X86_INS_MINPS = 366 , X86_INS_MINSD = 367 , X86_INS_MINSS = 368 , X86_INS_CVTPD2PI = 369 , X86_INS_CVTPI2PD = 370 , X86_INS_CVTPI2PS = 371 , X86_INS_CVTPS2PI = 372 , X86_INS_CVTTPD2PI = 373 , X86_INS_CVTTPS2PI = 374 , X86_INS_EMMS = 375 , X86_INS_MASKMOVQ = 376 , X86_INS_MOVD = 377 , X86_INS_MOVQ = 378 , X86_INS_MOVDQ2Q = 379 , X86_INS_MOVNTQ = 380 , X86_INS_MOVQ2DQ = 381 , X86_INS_PABSB = 382 , X86_INS_PABSD = 383 , X86_INS_PABSW = 384 , X86_INS_PACKSSDW = 385 , X86_INS_PACKSSWB = 386 , X86_INS_PACKUSWB = 387 , X86_INS_PADDB = 388 , X86_INS_PADDD = 389 , X86_INS_PADDQ = 390 , X86_INS_PADDSB = 391 , X86_INS_PADDSW = 392 , X86_INS_PADDUSB = 393 , X86_INS_PADDUSW = 394 , X86_INS_PADDW = 395 , X86_INS_PALIGNR = 396 , X86_INS_PANDN = 397 , X86_INS_PAND = 398 , X86_INS_PAVGB = 399 , X86_INS_PAVGW = 400 , X86_INS_PCMPEQB = 401 , X86_INS_PCMPEQD = 402 , X86_INS_PCMPEQW = 403 , X86_INS_PCMPGTB = 404 , X86_INS_PCMPGTD = 405 , X86_INS_PCMPGTW = 406 , X86_INS_PEXTRW = 407 , X86_INS_PHADDD = 408 , X86_INS_PHADDSW = 409 , X86_INS_PHADDW = 410 , X86_INS_PHSUBD = 411 , X86_INS_PHSUBSW = 412 , X86_INS_PHSUBW = 413 , X86_INS_PINSRW = 414 , X86_INS_PMADDUBSW = 415 , X86_INS_PMADDWD = 416 , X86_INS_PMAXSW = 417 , X86_INS_PMAXUB = 418 , X86_INS_PMINSW = 419 , X86_INS_PMINUB = 420 , X86_INS_PMOVMSKB = 421 , X86_INS_PMULHRSW = 422 , X86_INS_PMULHUW = 423 , X86_INS_PMULHW = 424 , X86_INS_PMULLW = 425 , X86_INS_PMULUDQ = 426 , X86_INS_POR = 427 , X86_INS_PSADBW = 428 , X86_INS_PSHUFB = 429 , X86_INS_PSHUFW = 430 , X86_INS_PSIGNB = 431 , X86_INS_PSIGND = 432 , X86_INS_PSIGNW = 433 , X86_INS_PSLLD = 434 , X86_INS_PSLLQ = 435 , X86_INS_PSLLW = 436 , X86_INS_PSRAD = 437 , X86_INS_PSRAW = 438 , X86_INS_PSRLD = 439 , X86_INS_PSRLQ = 440 , X86_INS_PSRLW = 441 , X86_INS_PSUBB = 442 , X86_INS_PSUBD = 443 , X86_INS_PSUBQ = 444 , X86_INS_PSUBSB = 445 , X86_INS_PSUBSW = 446 , X86_INS_PSUBUSB = 447 , X86_INS_PSUBUSW = 448 , X86_INS_PSUBW = 449 , X86_INS_PUNPCKHBW = 450 , X86_INS_PUNPCKHDQ = 451 , X86_INS_PUNPCKHWD = 452 , X86_INS_PUNPCKLBW = 453 , X86_INS_PUNPCKLDQ = 454 , X86_INS_PUNPCKLWD = 455 , X86_INS_PXOR = 456 , X86_INS_MONITORX = 457 , X86_INS_MONITOR = 458 , X86_INS_MONTMUL = 459 , X86_INS_MOV = 460 , X86_INS_MOVABS = 461 , X86_INS_MOVAPD = 462 , X86_INS_MOVAPS = 463 , X86_INS_MOVBE = 464 , X86_INS_MOVDDUP = 465 , X86_INS_MOVDIR64B = 466 , X86_INS_MOVDIRI = 467 , X86_INS_MOVDQA = 468 , X86_INS_MOVDQU = 469 , X86_INS_MOVHLPS = 470 , X86_INS_MOVHPD = 471 , X86_INS_MOVHPS = 472 , X86_INS_MOVLHPS = 473 , X86_INS_MOVLPD = 474 , X86_INS_MOVLPS = 475 , X86_INS_MOVMSKPD = 476 , X86_INS_MOVMSKPS = 477 , X86_INS_MOVNTDQA = 478 , X86_INS_MOVNTDQ = 479 , X86_INS_MOVNTI = 480 , X86_INS_MOVNTPD = 481 , X86_INS_MOVNTPS = 482 , X86_INS_MOVNTSD = 483 , X86_INS_MOVNTSS = 484 , X86_INS_MOVSB = 485 , X86_INS_MOVSD = 486 , X86_INS_MOVSHDUP = 487 , X86_INS_MOVSLDUP = 488 , X86_INS_MOVSQ = 489 , X86_INS_MOVSS = 490 , X86_INS_MOVSW = 491 , X86_INS_MOVSX = 492 , X86_INS_MOVSXD = 493 , X86_INS_MOVUPD = 494 , X86_INS_MOVUPS = 495 , X86_INS_MOVZX = 496 , X86_INS_MPSADBW = 497 , X86_INS_MUL = 498 , X86_INS_MULPD = 499 , X86_INS_MULPS = 500 , X86_INS_MULSD = 501 , X86_INS_MULSS = 502 , X86_INS_MULX = 503 , X86_INS_FMUL = 504 , X86_INS_FIMUL = 505 , X86_INS_FMULP = 506 , X86_INS_MWAITX = 507 , X86_INS_MWAIT = 508 , X86_INS_NEG = 509 , X86_INS_NOP = 510 , X86_INS_NOT = 511 , X86_INS_OR = 512 , X86_INS_ORPD = 513 , X86_INS_ORPS = 514 , X86_INS_OUT = 515 , X86_INS_OUTSB = 516 , X86_INS_OUTSD = 517 , X86_INS_OUTSW = 518 , X86_INS_PACKUSDW = 519 , X86_INS_PAUSE = 520 , X86_INS_PAVGUSB = 521 , X86_INS_PBLENDVB = 522 , X86_INS_PBLENDW = 523 , X86_INS_PCLMULQDQ = 524 , X86_INS_PCMPEQQ = 525 , X86_INS_PCMPESTRI = 526 , X86_INS_PCMPESTRM = 527 , X86_INS_PCMPGTQ = 528 , X86_INS_PCMPISTRI = 529 , X86_INS_PCMPISTRM = 530 , X86_INS_PCONFIG = 531 , X86_INS_PDEP = 532 , X86_INS_PEXT = 533 , X86_INS_PEXTRB = 534 , X86_INS_PEXTRD = 535 , X86_INS_PEXTRQ = 536 , X86_INS_PF2ID = 537 , X86_INS_PF2IW = 538 , X86_INS_PFACC = 539 , X86_INS_PFADD = 540 , X86_INS_PFCMPEQ = 541 , X86_INS_PFCMPGE = 542 , X86_INS_PFCMPGT = 543 , X86_INS_PFMAX = 544 , X86_INS_PFMIN = 545 , X86_INS_PFMUL = 546 , X86_INS_PFNACC = 547 , X86_INS_PFPNACC = 548 , X86_INS_PFRCPIT1 = 549 , X86_INS_PFRCPIT2 = 550 , X86_INS_PFRCP = 551 , X86_INS_PFRSQIT1 = 552 , X86_INS_PFRSQRT = 553 , X86_INS_PFSUBR = 554 , X86_INS_PFSUB = 555 , X86_INS_PHMINPOSUW = 556 , X86_INS_PI2FD = 557 , X86_INS_PI2FW = 558 , X86_INS_PINSRB = 559 , X86_INS_PINSRD = 560 , X86_INS_PINSRQ = 561 , X86_INS_PMAXSB = 562 , X86_INS_PMAXSD = 563 , X86_INS_PMAXUD = 564 , X86_INS_PMAXUW = 565 , X86_INS_PMINSB = 566 , X86_INS_PMINSD = 567 , X86_INS_PMINUD = 568 , X86_INS_PMINUW = 569 , X86_INS_PMOVSXBD = 570 , X86_INS_PMOVSXBQ = 571 , X86_INS_PMOVSXBW = 572 , X86_INS_PMOVSXDQ = 573 , X86_INS_PMOVSXWD = 574 , X86_INS_PMOVSXWQ = 575 , X86_INS_PMOVZXBD = 576 , X86_INS_PMOVZXBQ = 577 , X86_INS_PMOVZXBW = 578 , X86_INS_PMOVZXDQ = 579 , X86_INS_PMOVZXWD = 580 , X86_INS_PMOVZXWQ = 581 , X86_INS_PMULDQ = 582 , X86_INS_PMULHRW = 583 , X86_INS_PMULLD = 584 , X86_INS_POP = 585 , X86_INS_POPAW = 586 , X86_INS_POPAL = 587 , X86_INS_POPCNT = 588 , X86_INS_POPF = 589 , X86_INS_POPFD = 590 , X86_INS_POPFQ = 591 , X86_INS_PREFETCH = 592 , X86_INS_PREFETCHNTA = 593 , X86_INS_PREFETCHT0 = 594 , X86_INS_PREFETCHT1 = 595 , X86_INS_PREFETCHT2 = 596 , X86_INS_PREFETCHW = 597 , X86_INS_PREFETCHWT1 = 598 , X86_INS_PSHUFD = 599 , X86_INS_PSHUFHW = 600 , X86_INS_PSHUFLW = 601 , X86_INS_PSLLDQ = 602 , X86_INS_PSRLDQ = 603 , X86_INS_PSWAPD = 604 , X86_INS_PTEST = 605 , X86_INS_PTWRITE = 606 , X86_INS_PUNPCKHQDQ = 607 , X86_INS_PUNPCKLQDQ = 608 , X86_INS_PUSH = 609 , X86_INS_PUSHAW = 610 , X86_INS_PUSHAL = 611 , X86_INS_PUSHF = 612 , X86_INS_PUSHFD = 613 , X86_INS_PUSHFQ = 614 , X86_INS_RCL = 615 , X86_INS_RCPPS = 616 , X86_INS_RCPSS = 617 , X86_INS_RCR = 618 , X86_INS_RDFSBASE = 619 , X86_INS_RDGSBASE = 620 , X86_INS_RDMSR = 621 , X86_INS_RDPID = 622 , X86_INS_RDPKRU = 623 , X86_INS_RDPMC = 624 , X86_INS_RDRAND = 625 , X86_INS_RDSEED = 626 , X86_INS_RDSSPD = 627 , X86_INS_RDSSPQ = 628 , X86_INS_RDTSC = 629 , X86_INS_RDTSCP = 630 , X86_INS_REPNE = 631 , X86_INS_REP = 632 , X86_INS_RET = 633 , X86_INS_REX64 = 634 , X86_INS_ROL = 635 , X86_INS_ROR = 636 , X86_INS_RORX = 637 , X86_INS_ROUNDPD = 638 , X86_INS_ROUNDPS = 639 , X86_INS_ROUNDSD = 640 , X86_INS_ROUNDSS = 641 , X86_INS_RSM = 642 , X86_INS_RSQRTPS = 643 , X86_INS_RSQRTSS = 644 , X86_INS_RSTORSSP = 645 , X86_INS_SAHF = 646 , X86_INS_SAL = 647 , X86_INS_SALC = 648 , X86_INS_SAR = 649 , X86_INS_SARX = 650 , X86_INS_SAVEPREVSSP = 651 , X86_INS_SBB = 652 , X86_INS_SCASB = 653 , X86_INS_SCASD = 654 , X86_INS_SCASQ = 655 , X86_INS_SCASW = 656 , X86_INS_SETAE = 657 , X86_INS_SETA = 658 , X86_INS_SETBE = 659 , X86_INS_SETB = 660 , X86_INS_SETE = 661 , X86_INS_SETGE = 662 , X86_INS_SETG = 663 , X86_INS_SETLE = 664 , X86_INS_SETL = 665 , X86_INS_SETNE = 666 , X86_INS_SETNO = 667 , X86_INS_SETNP = 668 , X86_INS_SETNS = 669 , X86_INS_SETO = 670 , X86_INS_SETP = 671 , X86_INS_SETSSBSY = 672 , X86_INS_SETS = 673 , X86_INS_SFENCE = 674 , X86_INS_SGDT = 675 , X86_INS_SHA1MSG1 = 676 , X86_INS_SHA1MSG2 = 677 , X86_INS_SHA1NEXTE = 678 , X86_INS_SHA1RNDS4 = 679 , X86_INS_SHA256MSG1 = 680 , X86_INS_SHA256MSG2 = 681 , X86_INS_SHA256RNDS2 = 682 , X86_INS_SHL = 683 , X86_INS_SHLD = 684 , X86_INS_SHLX = 685 , X86_INS_SHR = 686 , X86_INS_SHRD = 687 , X86_INS_SHRX = 688 , X86_INS_SHUFPD = 689 , X86_INS_SHUFPS = 690 , X86_INS_SIDT = 691 , X86_INS_FSIN = 692 , X86_INS_SKINIT = 693 , X86_INS_SLDT = 694 , X86_INS_SLWPCB = 695 , X86_INS_SMSW = 696 , X86_INS_SQRTPD = 697 , X86_INS_SQRTPS = 698 , X86_INS_SQRTSD = 699 , X86_INS_SQRTSS = 700 , X86_INS_FSQRT = 701 , X86_INS_STAC = 702 , X86_INS_STC = 703 , X86_INS_STD = 704 , X86_INS_STGI = 705 , X86_INS_STI = 706 , X86_INS_STMXCSR = 707 , X86_INS_STOSB = 708 , X86_INS_STOSD = 709 , X86_INS_STOSQ = 710 , X86_INS_STOSW = 711 , X86_INS_STR = 712 , X86_INS_FST = 713 , X86_INS_FSTP = 714 , X86_INS_SUB = 715 , X86_INS_SUBPD = 716 , X86_INS_SUBPS = 717 , X86_INS_FSUBR = 718 , X86_INS_FISUBR = 719 , X86_INS_FSUBRP = 720 , X86_INS_SUBSD = 721 , X86_INS_SUBSS = 722 , X86_INS_FSUB = 723 , X86_INS_FISUB = 724 , X86_INS_FSUBP = 725 , X86_INS_SWAPGS = 726 , X86_INS_SYSCALL = 727 , X86_INS_SYSENTER = 728 , X86_INS_SYSEXIT = 729 , X86_INS_SYSEXITQ = 730 , X86_INS_SYSRET = 731 , X86_INS_SYSRETQ = 732 , X86_INS_T1MSKC = 733 , X86_INS_TEST = 734 , X86_INS_TPAUSE = 735 , X86_INS_FTST = 736 , X86_INS_TZCNT = 737 , X86_INS_TZMSK = 738 , X86_INS_UCOMISD = 739 , X86_INS_UCOMISS = 740 , X86_INS_FUCOMPI = 741 , X86_INS_FUCOMI = 742 , X86_INS_FUCOMPP = 743 , X86_INS_FUCOMP = 744 , X86_INS_FUCOM = 745 , X86_INS_UD0 = 746 , X86_INS_UD1 = 747 , X86_INS_UD2 = 748 , X86_INS_UMONITOR = 749 , X86_INS_UMWAIT = 750 , X86_INS_UNPCKHPD = 751 , X86_INS_UNPCKHPS = 752 , X86_INS_UNPCKLPD = 753 , X86_INS_UNPCKLPS = 754 , X86_INS_V4FMADDPS = 755 , X86_INS_V4FMADDSS = 756 , X86_INS_V4FNMADDPS = 757 , X86_INS_V4FNMADDSS = 758 , X86_INS_VADDPD = 759 , X86_INS_VADDPS = 760 , X86_INS_VADDSD = 761 , X86_INS_VADDSS = 762 , X86_INS_VADDSUBPD = 763 , X86_INS_VADDSUBPS = 764 , X86_INS_VAESDECLAST = 765 , X86_INS_VAESDEC = 766 , X86_INS_VAESENCLAST = 767 , X86_INS_VAESENC = 768 , X86_INS_VAESIMC = 769 , X86_INS_VAESKEYGENASSIST = 770 , X86_INS_VALIGND = 771 , X86_INS_VALIGNQ = 772 , X86_INS_VANDNPD = 773 , X86_INS_VANDNPS = 774 , X86_INS_VANDPD = 775 , X86_INS_VANDPS = 776 , X86_INS_VBLENDMPD = 777 , X86_INS_VBLENDMPS = 778 , X86_INS_VBLENDPD = 779 , X86_INS_VBLENDPS = 780 , X86_INS_VBLENDVPD = 781 , X86_INS_VBLENDVPS = 782 , X86_INS_VBROADCASTF128 = 783 , X86_INS_VBROADCASTF32X2 = 784 , X86_INS_VBROADCASTF32X4 = 785 , X86_INS_VBROADCASTF32X8 = 786 , X86_INS_VBROADCASTF64X2 = 787 , X86_INS_VBROADCASTF64X4 = 788 , X86_INS_VBROADCASTI128 = 789 , X86_INS_VBROADCASTI32X2 = 790 , X86_INS_VBROADCASTI32X4 = 791 , X86_INS_VBROADCASTI32X8 = 792 , X86_INS_VBROADCASTI64X2 = 793 , X86_INS_VBROADCASTI64X4 = 794 , X86_INS_VBROADCASTSD = 795 , X86_INS_VBROADCASTSS = 796 , X86_INS_VCMP = 797 , X86_INS_VCMPPD = 798 , X86_INS_VCMPPS = 799 , X86_INS_VCMPSD = 800 , X86_INS_VCMPSS = 801 , X86_INS_VCOMISD = 802 , X86_INS_VCOMISS = 803 , X86_INS_VCOMPRESSPD = 804 , X86_INS_VCOMPRESSPS = 805 , X86_INS_VCVTDQ2PD = 806 , X86_INS_VCVTDQ2PS = 807 , X86_INS_VCVTPD2DQ = 808 , X86_INS_VCVTPD2PS = 809 , X86_INS_VCVTPD2QQ = 810 , X86_INS_VCVTPD2UDQ = 811 , X86_INS_VCVTPD2UQQ = 812 , X86_INS_VCVTPH2PS = 813 , X86_INS_VCVTPS2DQ = 814 , X86_INS_VCVTPS2PD = 815 , X86_INS_VCVTPS2PH = 816 , X86_INS_VCVTPS2QQ = 817 , X86_INS_VCVTPS2UDQ = 818 , X86_INS_VCVTPS2UQQ = 819 , X86_INS_VCVTQQ2PD = 820 , X86_INS_VCVTQQ2PS = 821 , X86_INS_VCVTSD2SI = 822 , X86_INS_VCVTSD2SS = 823 , X86_INS_VCVTSD2USI = 824 , X86_INS_VCVTSI2SD = 825 , X86_INS_VCVTSI2SS = 826 , X86_INS_VCVTSS2SD = 827 , X86_INS_VCVTSS2SI = 828 , X86_INS_VCVTSS2USI = 829 , X86_INS_VCVTTPD2DQ = 830 , X86_INS_VCVTTPD2QQ = 831 , X86_INS_VCVTTPD2UDQ = 832 , X86_INS_VCVTTPD2UQQ = 833 , X86_INS_VCVTTPS2DQ = 834 , X86_INS_VCVTTPS2QQ = 835 , X86_INS_VCVTTPS2UDQ = 836 , X86_INS_VCVTTPS2UQQ = 837 , X86_INS_VCVTTSD2SI = 838 , X86_INS_VCVTTSD2USI = 839 , X86_INS_VCVTTSS2SI = 840 , X86_INS_VCVTTSS2USI = 841 , X86_INS_VCVTUDQ2PD = 842 , X86_INS_VCVTUDQ2PS = 843 , X86_INS_VCVTUQQ2PD = 844 , X86_INS_VCVTUQQ2PS = 845 , X86_INS_VCVTUSI2SD = 846 , X86_INS_VCVTUSI2SS = 847 , X86_INS_VDBPSADBW = 848 , X86_INS_VDIVPD = 849 , X86_INS_VDIVPS = 850 , X86_INS_VDIVSD = 851 , X86_INS_VDIVSS = 852 , X86_INS_VDPPD = 853 , X86_INS_VDPPS = 854 , X86_INS_VERR = 855 , X86_INS_VERW = 856 , X86_INS_VEXP2PD = 857 , X86_INS_VEXP2PS = 858 , X86_INS_VEXPANDPD = 859 , X86_INS_VEXPANDPS = 860 , X86_INS_VEXTRACTF128 = 861 , X86_INS_VEXTRACTF32X4 = 862 , X86_INS_VEXTRACTF32X8 = 863 , X86_INS_VEXTRACTF64X2 = 864 , X86_INS_VEXTRACTF64X4 = 865 , X86_INS_VEXTRACTI128 = 866 , X86_INS_VEXTRACTI32X4 = 867 , X86_INS_VEXTRACTI32X8 = 868 , X86_INS_VEXTRACTI64X2 = 869 , X86_INS_VEXTRACTI64X4 = 870 , X86_INS_VEXTRACTPS = 871 , X86_INS_VFIXUPIMMPD = 872 , X86_INS_VFIXUPIMMPS = 873 , X86_INS_VFIXUPIMMSD = 874 , X86_INS_VFIXUPIMMSS = 875 , X86_INS_VFMADD132PD = 876 , X86_INS_VFMADD132PS = 877 , X86_INS_VFMADD132SD = 878 , X86_INS_VFMADD132SS = 879 , X86_INS_VFMADD213PD = 880 , X86_INS_VFMADD213PS = 881 , X86_INS_VFMADD213SD = 882 , X86_INS_VFMADD213SS = 883 , X86_INS_VFMADD231PD = 884 , X86_INS_VFMADD231PS = 885 , X86_INS_VFMADD231SD = 886 , X86_INS_VFMADD231SS = 887 , X86_INS_VFMADDPD = 888 , X86_INS_VFMADDPS = 889 , X86_INS_VFMADDSD = 890 , X86_INS_VFMADDSS = 891 , X86_INS_VFMADDSUB132PD = 892 , X86_INS_VFMADDSUB132PS = 893 , X86_INS_VFMADDSUB213PD = 894 , X86_INS_VFMADDSUB213PS = 895 , X86_INS_VFMADDSUB231PD = 896 , X86_INS_VFMADDSUB231PS = 897 , X86_INS_VFMADDSUBPD = 898 , X86_INS_VFMADDSUBPS = 899 , X86_INS_VFMSUB132PD = 900 , X86_INS_VFMSUB132PS = 901 , X86_INS_VFMSUB132SD = 902 , X86_INS_VFMSUB132SS = 903 , X86_INS_VFMSUB213PD = 904 , X86_INS_VFMSUB213PS = 905 , X86_INS_VFMSUB213SD = 906 , X86_INS_VFMSUB213SS = 907 , X86_INS_VFMSUB231PD = 908 , X86_INS_VFMSUB231PS = 909 , X86_INS_VFMSUB231SD = 910 , X86_INS_VFMSUB231SS = 911 , X86_INS_VFMSUBADD132PD = 912 , X86_INS_VFMSUBADD132PS = 913 , X86_INS_VFMSUBADD213PD = 914 , X86_INS_VFMSUBADD213PS = 915 , X86_INS_VFMSUBADD231PD = 916 , X86_INS_VFMSUBADD231PS = 917 , X86_INS_VFMSUBADDPD = 918 , X86_INS_VFMSUBADDPS = 919 , X86_INS_VFMSUBPD = 920 , X86_INS_VFMSUBPS = 921 , X86_INS_VFMSUBSD = 922 , X86_INS_VFMSUBSS = 923 , X86_INS_VFNMADD132PD = 924 , X86_INS_VFNMADD132PS = 925 , X86_INS_VFNMADD132SD = 926 , X86_INS_VFNMADD132SS = 927 , X86_INS_VFNMADD213PD = 928 , X86_INS_VFNMADD213PS = 929 , X86_INS_VFNMADD213SD = 930 , X86_INS_VFNMADD213SS = 931 , X86_INS_VFNMADD231PD = 932 , X86_INS_VFNMADD231PS = 933 , X86_INS_VFNMADD231SD = 934 , X86_INS_VFNMADD231SS = 935 , X86_INS_VFNMADDPD = 936 , X86_INS_VFNMADDPS = 937 , X86_INS_VFNMADDSD = 938 , X86_INS_VFNMADDSS = 939 , X86_INS_VFNMSUB132PD = 940 , X86_INS_VFNMSUB132PS = 941 , X86_INS_VFNMSUB132SD = 942 , X86_INS_VFNMSUB132SS = 943 , X86_INS_VFNMSUB213PD = 944 , X86_INS_VFNMSUB213PS = 945 , X86_INS_VFNMSUB213SD = 946 , X86_INS_VFNMSUB213SS = 947 , X86_INS_VFNMSUB231PD = 948 , X86_INS_VFNMSUB231PS = 949 , X86_INS_VFNMSUB231SD = 950 , X86_INS_VFNMSUB231SS = 951 , X86_INS_VFNMSUBPD = 952 , X86_INS_VFNMSUBPS = 953 , X86_INS_VFNMSUBSD = 954 , X86_INS_VFNMSUBSS = 955 , X86_INS_VFPCLASSPD = 956 , X86_INS_VFPCLASSPS = 957 , X86_INS_VFPCLASSSD = 958 , X86_INS_VFPCLASSSS = 959 , X86_INS_VFRCZPD = 960 , X86_INS_VFRCZPS = 961 , X86_INS_VFRCZSD = 962 , X86_INS_VFRCZSS = 963 , X86_INS_VGATHERDPD = 964 , X86_INS_VGATHERDPS = 965 , X86_INS_VGATHERPF0DPD = 966 , X86_INS_VGATHERPF0DPS = 967 , X86_INS_VGATHERPF0QPD = 968 , X86_INS_VGATHERPF0QPS = 969 , X86_INS_VGATHERPF1DPD = 970 , X86_INS_VGATHERPF1DPS = 971 , X86_INS_VGATHERPF1QPD = 972 , X86_INS_VGATHERPF1QPS = 973 , X86_INS_VGATHERQPD = 974 , X86_INS_VGATHERQPS = 975 , X86_INS_VGETEXPPD = 976 , X86_INS_VGETEXPPS = 977 , X86_INS_VGETEXPSD = 978 , X86_INS_VGETEXPSS = 979 , X86_INS_VGETMANTPD = 980 , X86_INS_VGETMANTPS = 981 , X86_INS_VGETMANTSD = 982 , X86_INS_VGETMANTSS = 983 , X86_INS_VGF2P8AFFINEINVQB = 984 , X86_INS_VGF2P8AFFINEQB = 985 , X86_INS_VGF2P8MULB = 986 , X86_INS_VHADDPD = 987 , X86_INS_VHADDPS = 988 , X86_INS_VHSUBPD = 989 , X86_INS_VHSUBPS = 990 , X86_INS_VINSERTF128 = 991 , X86_INS_VINSERTF32X4 = 992 , X86_INS_VINSERTF32X8 = 993 , X86_INS_VINSERTF64X2 = 994 , X86_INS_VINSERTF64X4 = 995 , X86_INS_VINSERTI128 = 996 , X86_INS_VINSERTI32X4 = 997 , X86_INS_VINSERTI32X8 = 998 , X86_INS_VINSERTI64X2 = 999 , X86_INS_VINSERTI64X4 = 1000 , X86_INS_VINSERTPS = 1001 , X86_INS_VLDDQU = 1002 , X86_INS_VLDMXCSR = 1003 , X86_INS_VMASKMOVDQU = 1004 , X86_INS_VMASKMOVPD = 1005 , X86_INS_VMASKMOVPS = 1006 , X86_INS_VMAXPD = 1007 , X86_INS_VMAXPS = 1008 , X86_INS_VMAXSD = 1009 , X86_INS_VMAXSS = 1010 , X86_INS_VMCALL = 1011 , X86_INS_VMCLEAR = 1012 , X86_INS_VMFUNC = 1013 , X86_INS_VMINPD = 1014 , X86_INS_VMINPS = 1015 , X86_INS_VMINSD = 1016 , X86_INS_VMINSS = 1017 , X86_INS_VMLAUNCH = 1018 , X86_INS_VMLOAD = 1019 , X86_INS_VMMCALL = 1020 , X86_INS_VMOVQ = 1021 , X86_INS_VMOVAPD = 1022 , X86_INS_VMOVAPS = 1023 , X86_INS_VMOVDDUP = 1024 , X86_INS_VMOVD = 1025 , X86_INS_VMOVDQA32 = 1026 , X86_INS_VMOVDQA64 = 1027 , X86_INS_VMOVDQA = 1028 , X86_INS_VMOVDQU16 = 1029 , X86_INS_VMOVDQU32 = 1030 , X86_INS_VMOVDQU64 = 1031 , X86_INS_VMOVDQU8 = 1032 , X86_INS_VMOVDQU = 1033 , X86_INS_VMOVHLPS = 1034 , X86_INS_VMOVHPD = 1035 , X86_INS_VMOVHPS = 1036 , X86_INS_VMOVLHPS = 1037 , X86_INS_VMOVLPD = 1038 , X86_INS_VMOVLPS = 1039 , X86_INS_VMOVMSKPD = 1040 , X86_INS_VMOVMSKPS = 1041 , X86_INS_VMOVNTDQA = 1042 , X86_INS_VMOVNTDQ = 1043 , X86_INS_VMOVNTPD = 1044 , X86_INS_VMOVNTPS = 1045 , X86_INS_VMOVSD = 1046 , X86_INS_VMOVSHDUP = 1047 , X86_INS_VMOVSLDUP = 1048 , X86_INS_VMOVSS = 1049 , X86_INS_VMOVUPD = 1050 , X86_INS_VMOVUPS = 1051 , X86_INS_VMPSADBW = 1052 , X86_INS_VMPTRLD = 1053 , X86_INS_VMPTRST = 1054 , X86_INS_VMREAD = 1055 , X86_INS_VMRESUME = 1056 , X86_INS_VMRUN = 1057 , X86_INS_VMSAVE = 1058 , X86_INS_VMULPD = 1059 , X86_INS_VMULPS = 1060 , X86_INS_VMULSD = 1061 , X86_INS_VMULSS = 1062 , X86_INS_VMWRITE = 1063 , X86_INS_VMXOFF = 1064 , X86_INS_VMXON = 1065 , X86_INS_VORPD = 1066 , X86_INS_VORPS = 1067 , X86_INS_VP4DPWSSDS = 1068 , X86_INS_VP4DPWSSD = 1069 , X86_INS_VPABSB = 1070 , X86_INS_VPABSD = 1071 , X86_INS_VPABSQ = 1072 , X86_INS_VPABSW = 1073 , X86_INS_VPACKSSDW = 1074 , X86_INS_VPACKSSWB = 1075 , X86_INS_VPACKUSDW = 1076 , X86_INS_VPACKUSWB = 1077 , X86_INS_VPADDB = 1078 , X86_INS_VPADDD = 1079 , X86_INS_VPADDQ = 1080 , X86_INS_VPADDSB = 1081 , X86_INS_VPADDSW = 1082 , X86_INS_VPADDUSB = 1083 , X86_INS_VPADDUSW = 1084 , X86_INS_VPADDW = 1085 , X86_INS_VPALIGNR = 1086 , X86_INS_VPANDD = 1087 , X86_INS_VPANDND = 1088 , X86_INS_VPANDNQ = 1089 , X86_INS_VPANDN = 1090 , X86_INS_VPANDQ = 1091 , X86_INS_VPAND = 1092 , X86_INS_VPAVGB = 1093 , X86_INS_VPAVGW = 1094 , X86_INS_VPBLENDD = 1095 , X86_INS_VPBLENDMB = 1096 , X86_INS_VPBLENDMD = 1097 , X86_INS_VPBLENDMQ = 1098 , X86_INS_VPBLENDMW = 1099 , X86_INS_VPBLENDVB = 1100 , X86_INS_VPBLENDW = 1101 , X86_INS_VPBROADCASTB = 1102 , X86_INS_VPBROADCASTD = 1103 , X86_INS_VPBROADCASTMB2Q = 1104 , X86_INS_VPBROADCASTMW2D = 1105 , X86_INS_VPBROADCASTQ = 1106 , X86_INS_VPBROADCASTW = 1107 , X86_INS_VPCLMULQDQ = 1108 , X86_INS_VPCMOV = 1109 , X86_INS_VPCMP = 1110 , X86_INS_VPCMPB = 1111 , X86_INS_VPCMPD = 1112 , X86_INS_VPCMPEQB = 1113 , X86_INS_VPCMPEQD = 1114 , X86_INS_VPCMPEQQ = 1115 , X86_INS_VPCMPEQW = 1116 , X86_INS_VPCMPESTRI = 1117 , X86_INS_VPCMPESTRM = 1118 , X86_INS_VPCMPGTB = 1119 , X86_INS_VPCMPGTD = 1120 , X86_INS_VPCMPGTQ = 1121 , X86_INS_VPCMPGTW = 1122 , X86_INS_VPCMPISTRI = 1123 , X86_INS_VPCMPISTRM = 1124 , X86_INS_VPCMPQ = 1125 , X86_INS_VPCMPUB = 1126 , X86_INS_VPCMPUD = 1127 , X86_INS_VPCMPUQ = 1128 , X86_INS_VPCMPUW = 1129 , X86_INS_VPCMPW = 1130 , X86_INS_VPCOM = 1131 , X86_INS_VPCOMB = 1132 , X86_INS_VPCOMD = 1133 , X86_INS_VPCOMPRESSB = 1134 , X86_INS_VPCOMPRESSD = 1135 , X86_INS_VPCOMPRESSQ = 1136 , X86_INS_VPCOMPRESSW = 1137 , X86_INS_VPCOMQ = 1138 , X86_INS_VPCOMUB = 1139 , X86_INS_VPCOMUD = 1140 , X86_INS_VPCOMUQ = 1141 , X86_INS_VPCOMUW = 1142 , X86_INS_VPCOMW = 1143 , X86_INS_VPCONFLICTD = 1144 , X86_INS_VPCONFLICTQ = 1145 , X86_INS_VPDPBUSDS = 1146 , X86_INS_VPDPBUSD = 1147 , X86_INS_VPDPWSSDS = 1148 , X86_INS_VPDPWSSD = 1149 , X86_INS_VPERM2F128 = 1150 , X86_INS_VPERM2I128 = 1151 , X86_INS_VPERMB = 1152 , X86_INS_VPERMD = 1153 , X86_INS_VPERMI2B = 1154 , X86_INS_VPERMI2D = 1155 , X86_INS_VPERMI2PD = 1156 , X86_INS_VPERMI2PS = 1157 , X86_INS_VPERMI2Q = 1158 , X86_INS_VPERMI2W = 1159 , X86_INS_VPERMIL2PD = 1160 , X86_INS_VPERMILPD = 1161 , X86_INS_VPERMIL2PS = 1162 , X86_INS_VPERMILPS = 1163 , X86_INS_VPERMPD = 1164 , X86_INS_VPERMPS = 1165 , X86_INS_VPERMQ = 1166 , X86_INS_VPERMT2B = 1167 , X86_INS_VPERMT2D = 1168 , X86_INS_VPERMT2PD = 1169 , X86_INS_VPERMT2PS = 1170 , X86_INS_VPERMT2Q = 1171 , X86_INS_VPERMT2W = 1172 , X86_INS_VPERMW = 1173 , X86_INS_VPEXPANDB = 1174 , X86_INS_VPEXPANDD = 1175 , X86_INS_VPEXPANDQ = 1176 , X86_INS_VPEXPANDW = 1177 , X86_INS_VPEXTRB = 1178 , X86_INS_VPEXTRD = 1179 , X86_INS_VPEXTRQ = 1180 , X86_INS_VPEXTRW = 1181 , X86_INS_VPGATHERDD = 1182 , X86_INS_VPGATHERDQ = 1183 , X86_INS_VPGATHERQD = 1184 , X86_INS_VPGATHERQQ = 1185 , X86_INS_VPHADDBD = 1186 , X86_INS_VPHADDBQ = 1187 , X86_INS_VPHADDBW = 1188 , X86_INS_VPHADDDQ = 1189 , X86_INS_VPHADDD = 1190 , X86_INS_VPHADDSW = 1191 , X86_INS_VPHADDUBD = 1192 , X86_INS_VPHADDUBQ = 1193 , X86_INS_VPHADDUBW = 1194 , X86_INS_VPHADDUDQ = 1195 , X86_INS_VPHADDUWD = 1196 , X86_INS_VPHADDUWQ = 1197 , X86_INS_VPHADDWD = 1198 , X86_INS_VPHADDWQ = 1199 , X86_INS_VPHADDW = 1200 , X86_INS_VPHMINPOSUW = 1201 , X86_INS_VPHSUBBW = 1202 , X86_INS_VPHSUBDQ = 1203 , X86_INS_VPHSUBD = 1204 , X86_INS_VPHSUBSW = 1205 , X86_INS_VPHSUBWD = 1206 , X86_INS_VPHSUBW = 1207 , X86_INS_VPINSRB = 1208 , X86_INS_VPINSRD = 1209 , X86_INS_VPINSRQ = 1210 , X86_INS_VPINSRW = 1211 , X86_INS_VPLZCNTD = 1212 , X86_INS_VPLZCNTQ = 1213 , X86_INS_VPMACSDD = 1214 , X86_INS_VPMACSDQH = 1215 , X86_INS_VPMACSDQL = 1216 , X86_INS_VPMACSSDD = 1217 , X86_INS_VPMACSSDQH = 1218 , X86_INS_VPMACSSDQL = 1219 , X86_INS_VPMACSSWD = 1220 , X86_INS_VPMACSSWW = 1221 , X86_INS_VPMACSWD = 1222 , X86_INS_VPMACSWW = 1223 , X86_INS_VPMADCSSWD = 1224 , X86_INS_VPMADCSWD = 1225 , X86_INS_VPMADD52HUQ = 1226 , X86_INS_VPMADD52LUQ = 1227 , X86_INS_VPMADDUBSW = 1228 , X86_INS_VPMADDWD = 1229 , X86_INS_VPMASKMOVD = 1230 , X86_INS_VPMASKMOVQ = 1231 , X86_INS_VPMAXSB = 1232 , X86_INS_VPMAXSD = 1233 , X86_INS_VPMAXSQ = 1234 , X86_INS_VPMAXSW = 1235 , X86_INS_VPMAXUB = 1236 , X86_INS_VPMAXUD = 1237 , X86_INS_VPMAXUQ = 1238 , X86_INS_VPMAXUW = 1239 , X86_INS_VPMINSB = 1240 , X86_INS_VPMINSD = 1241 , X86_INS_VPMINSQ = 1242 , X86_INS_VPMINSW = 1243 , X86_INS_VPMINUB = 1244 , X86_INS_VPMINUD = 1245 , X86_INS_VPMINUQ = 1246 , X86_INS_VPMINUW = 1247 , X86_INS_VPMOVB2M = 1248 , X86_INS_VPMOVD2M = 1249 , X86_INS_VPMOVDB = 1250 , X86_INS_VPMOVDW = 1251 , X86_INS_VPMOVM2B = 1252 , X86_INS_VPMOVM2D = 1253 , X86_INS_VPMOVM2Q = 1254 , X86_INS_VPMOVM2W = 1255 , X86_INS_VPMOVMSKB = 1256 , X86_INS_VPMOVQ2M = 1257 , X86_INS_VPMOVQB = 1258 , X86_INS_VPMOVQD = 1259 , X86_INS_VPMOVQW = 1260 , X86_INS_VPMOVSDB = 1261 , X86_INS_VPMOVSDW = 1262 , X86_INS_VPMOVSQB = 1263 , X86_INS_VPMOVSQD = 1264 , X86_INS_VPMOVSQW = 1265 , X86_INS_VPMOVSWB = 1266 , X86_INS_VPMOVSXBD = 1267 , X86_INS_VPMOVSXBQ = 1268 , X86_INS_VPMOVSXBW = 1269 , X86_INS_VPMOVSXDQ = 1270 , X86_INS_VPMOVSXWD = 1271 , X86_INS_VPMOVSXWQ = 1272 , X86_INS_VPMOVUSDB = 1273 , X86_INS_VPMOVUSDW = 1274 , X86_INS_VPMOVUSQB = 1275 , X86_INS_VPMOVUSQD = 1276 , X86_INS_VPMOVUSQW = 1277 , X86_INS_VPMOVUSWB = 1278 , X86_INS_VPMOVW2M = 1279 , X86_INS_VPMOVWB = 1280 , X86_INS_VPMOVZXBD = 1281 , X86_INS_VPMOVZXBQ = 1282 , X86_INS_VPMOVZXBW = 1283 , X86_INS_VPMOVZXDQ = 1284 , X86_INS_VPMOVZXWD = 1285 , X86_INS_VPMOVZXWQ = 1286 , X86_INS_VPMULDQ = 1287 , X86_INS_VPMULHRSW = 1288 , X86_INS_VPMULHUW = 1289 , X86_INS_VPMULHW = 1290 , X86_INS_VPMULLD = 1291 , X86_INS_VPMULLQ = 1292 , X86_INS_VPMULLW = 1293 , X86_INS_VPMULTISHIFTQB = 1294 , X86_INS_VPMULUDQ = 1295 , X86_INS_VPOPCNTB = 1296 , X86_INS_VPOPCNTD = 1297 , X86_INS_VPOPCNTQ = 1298 , X86_INS_VPOPCNTW = 1299 , X86_INS_VPORD = 1300 , X86_INS_VPORQ = 1301 , X86_INS_VPOR = 1302 , X86_INS_VPPERM = 1303 , X86_INS_VPROLD = 1304 , X86_INS_VPROLQ = 1305 , X86_INS_VPROLVD = 1306 , X86_INS_VPROLVQ = 1307 , X86_INS_VPRORD = 1308 , X86_INS_VPRORQ = 1309 , X86_INS_VPRORVD = 1310 , X86_INS_VPRORVQ = 1311 , X86_INS_VPROTB = 1312 , X86_INS_VPROTD = 1313 , X86_INS_VPROTQ = 1314 , X86_INS_VPROTW = 1315 , X86_INS_VPSADBW = 1316 , X86_INS_VPSCATTERDD = 1317 , X86_INS_VPSCATTERDQ = 1318 , X86_INS_VPSCATTERQD = 1319 , X86_INS_VPSCATTERQQ = 1320 , X86_INS_VPSHAB = 1321 , X86_INS_VPSHAD = 1322 , X86_INS_VPSHAQ = 1323 , X86_INS_VPSHAW = 1324 , X86_INS_VPSHLB = 1325 , X86_INS_VPSHLDD = 1326 , X86_INS_VPSHLDQ = 1327 , X86_INS_VPSHLDVD = 1328 , X86_INS_VPSHLDVQ = 1329 , X86_INS_VPSHLDVW = 1330 , X86_INS_VPSHLDW = 1331 , X86_INS_VPSHLD = 1332 , X86_INS_VPSHLQ = 1333 , X86_INS_VPSHLW = 1334 , X86_INS_VPSHRDD = 1335 , X86_INS_VPSHRDQ = 1336 , X86_INS_VPSHRDVD = 1337 , X86_INS_VPSHRDVQ = 1338 , X86_INS_VPSHRDVW = 1339 , X86_INS_VPSHRDW = 1340 , X86_INS_VPSHUFBITQMB = 1341 , X86_INS_VPSHUFB = 1342 , X86_INS_VPSHUFD = 1343 , X86_INS_VPSHUFHW = 1344 , X86_INS_VPSHUFLW = 1345 , X86_INS_VPSIGNB = 1346 , X86_INS_VPSIGND = 1347 , X86_INS_VPSIGNW = 1348 , X86_INS_VPSLLDQ = 1349 , X86_INS_VPSLLD = 1350 , X86_INS_VPSLLQ = 1351 , X86_INS_VPSLLVD = 1352 , X86_INS_VPSLLVQ = 1353 , X86_INS_VPSLLVW = 1354 , X86_INS_VPSLLW = 1355 , X86_INS_VPSRAD = 1356 , X86_INS_VPSRAQ = 1357 , X86_INS_VPSRAVD = 1358 , X86_INS_VPSRAVQ = 1359 , X86_INS_VPSRAVW = 1360 , X86_INS_VPSRAW = 1361 , X86_INS_VPSRLDQ = 1362 , X86_INS_VPSRLD = 1363 , X86_INS_VPSRLQ = 1364 , X86_INS_VPSRLVD = 1365 , X86_INS_VPSRLVQ = 1366 , X86_INS_VPSRLVW = 1367 , X86_INS_VPSRLW = 1368 , X86_INS_VPSUBB = 1369 , X86_INS_VPSUBD = 1370 , X86_INS_VPSUBQ = 1371 , X86_INS_VPSUBSB = 1372 , X86_INS_VPSUBSW = 1373 , X86_INS_VPSUBUSB = 1374 , X86_INS_VPSUBUSW = 1375 , X86_INS_VPSUBW = 1376 , X86_INS_VPTERNLOGD = 1377 , X86_INS_VPTERNLOGQ = 1378 , X86_INS_VPTESTMB = 1379 , X86_INS_VPTESTMD = 1380 , X86_INS_VPTESTMQ = 1381 , X86_INS_VPTESTMW = 1382 , X86_INS_VPTESTNMB = 1383 , X86_INS_VPTESTNMD = 1384 , X86_INS_VPTESTNMQ = 1385 , X86_INS_VPTESTNMW = 1386 , X86_INS_VPTEST = 1387 , X86_INS_VPUNPCKHBW = 1388 , X86_INS_VPUNPCKHDQ = 1389 , X86_INS_VPUNPCKHQDQ = 1390 , X86_INS_VPUNPCKHWD = 1391 , X86_INS_VPUNPCKLBW = 1392 , X86_INS_VPUNPCKLDQ = 1393 , X86_INS_VPUNPCKLQDQ = 1394 , X86_INS_VPUNPCKLWD = 1395 , X86_INS_VPXORD = 1396 , X86_INS_VPXORQ = 1397 , X86_INS_VPXOR = 1398 , X86_INS_VRANGEPD = 1399 , X86_INS_VRANGEPS = 1400 , X86_INS_VRANGESD = 1401 , X86_INS_VRANGESS = 1402 , X86_INS_VRCP14PD = 1403 , X86_INS_VRCP14PS = 1404 , X86_INS_VRCP14SD = 1405 , X86_INS_VRCP14SS = 1406 , X86_INS_VRCP28PD = 1407 , X86_INS_VRCP28PS = 1408 , X86_INS_VRCP28SD = 1409 , X86_INS_VRCP28SS = 1410 , X86_INS_VRCPPS = 1411 , X86_INS_VRCPSS = 1412 , X86_INS_VREDUCEPD = 1413 , X86_INS_VREDUCEPS = 1414 , X86_INS_VREDUCESD = 1415 , X86_INS_VREDUCESS = 1416 , X86_INS_VRNDSCALEPD = 1417 , X86_INS_VRNDSCALEPS = 1418 , X86_INS_VRNDSCALESD = 1419 , X86_INS_VRNDSCALESS = 1420 , X86_INS_VROUNDPD = 1421 , X86_INS_VROUNDPS = 1422 , X86_INS_VROUNDSD = 1423 , X86_INS_VROUNDSS = 1424 , X86_INS_VRSQRT14PD = 1425 , X86_INS_VRSQRT14PS = 1426 , X86_INS_VRSQRT14SD = 1427 , X86_INS_VRSQRT14SS = 1428 , X86_INS_VRSQRT28PD = 1429 , X86_INS_VRSQRT28PS = 1430 , X86_INS_VRSQRT28SD = 1431 , X86_INS_VRSQRT28SS = 1432 , X86_INS_VRSQRTPS = 1433 , X86_INS_VRSQRTSS = 1434 , X86_INS_VSCALEFPD = 1435 , X86_INS_VSCALEFPS = 1436 , X86_INS_VSCALEFSD = 1437 , X86_INS_VSCALEFSS = 1438 , X86_INS_VSCATTERDPD = 1439 , X86_INS_VSCATTERDPS = 1440 , X86_INS_VSCATTERPF0DPD = 1441 , X86_INS_VSCATTERPF0DPS = 1442 , X86_INS_VSCATTERPF0QPD = 1443 , X86_INS_VSCATTERPF0QPS = 1444 , X86_INS_VSCATTERPF1DPD = 1445 , X86_INS_VSCATTERPF1DPS = 1446 , X86_INS_VSCATTERPF1QPD = 1447 , X86_INS_VSCATTERPF1QPS = 1448 , X86_INS_VSCATTERQPD = 1449 , X86_INS_VSCATTERQPS = 1450 , X86_INS_VSHUFF32X4 = 1451 , X86_INS_VSHUFF64X2 = 1452 , X86_INS_VSHUFI32X4 = 1453 , X86_INS_VSHUFI64X2 = 1454 , X86_INS_VSHUFPD = 1455 , X86_INS_VSHUFPS = 1456 , X86_INS_VSQRTPD = 1457 , X86_INS_VSQRTPS = 1458 , X86_INS_VSQRTSD = 1459 , X86_INS_VSQRTSS = 1460 , X86_INS_VSTMXCSR = 1461 , X86_INS_VSUBPD = 1462 , X86_INS_VSUBPS = 1463 , X86_INS_VSUBSD = 1464 , X86_INS_VSUBSS = 1465 , X86_INS_VTESTPD = 1466 , X86_INS_VTESTPS = 1467 , X86_INS_VUCOMISD = 1468 , X86_INS_VUCOMISS = 1469 , X86_INS_VUNPCKHPD = 1470 , X86_INS_VUNPCKHPS = 1471 , X86_INS_VUNPCKLPD = 1472 , X86_INS_VUNPCKLPS = 1473 , X86_INS_VXORPD = 1474 , X86_INS_VXORPS = 1475 , X86_INS_VZEROALL = 1476 , X86_INS_VZEROUPPER = 1477 , X86_INS_WAIT = 1478 , X86_INS_WBINVD = 1479 , X86_INS_WBNOINVD = 1480 , X86_INS_WRFSBASE = 1481 , X86_INS_WRGSBASE = 1482 , X86_INS_WRMSR = 1483 , X86_INS_WRPKRU = 1484 , X86_INS_WRSSD = 1485 , X86_INS_WRSSQ = 1486 , X86_INS_WRUSSD = 1487 , X86_INS_WRUSSQ = 1488 , X86_INS_XABORT = 1489 , X86_INS_XACQUIRE = 1490 , X86_INS_XADD = 1491 , X86_INS_XBEGIN = 1492 , X86_INS_XCHG = 1493 , X86_INS_FXCH = 1494 , X86_INS_XCRYPTCBC = 1495 , X86_INS_XCRYPTCFB = 1496 , X86_INS_XCRYPTCTR = 1497 , X86_INS_XCRYPTECB = 1498 , X86_INS_XCRYPTOFB = 1499 , X86_INS_XEND = 1500 , X86_INS_XGETBV = 1501 , X86_INS_XLATB = 1502 , X86_INS_XOR = 1503 , X86_INS_XORPD = 1504 , X86_INS_XORPS = 1505 , X86_INS_XRELEASE = 1506 , X86_INS_XRSTOR = 1507 , X86_INS_XRSTOR64 = 1508 , X86_INS_XRSTORS = 1509 , X86_INS_XRSTORS64 = 1510 , X86_INS_XSAVE = 1511 , X86_INS_XSAVE64 = 1512 , X86_INS_XSAVEC = 1513 , X86_INS_XSAVEC64 = 1514 , X86_INS_XSAVEOPT = 1515 , X86_INS_XSAVEOPT64 = 1516 , X86_INS_XSAVES = 1517 , X86_INS_XSAVES64 = 1518 , X86_INS_XSETBV = 1519 , X86_INS_XSHA1 = 1520 , X86_INS_XSHA256 = 1521 , X86_INS_XSTORE = 1522 , X86_INS_XTEST = 1523 , X86_INS_ENDING = 1524 , } # [repr (u32)] # [doc = " Group of X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn_group { # [doc = "< = CS_GRP_INVALID"] X86_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] X86_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] X86_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] X86_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] X86_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] X86_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] X86_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] X86_GRP_BRANCH_RELATIVE = 7 , # [doc = "< all virtualization instructions (VT-x + AMD-V)"] X86_GRP_VM = 128 , X86_GRP_3DNOW = 129 , X86_GRP_AES = 130 , X86_GRP_ADX = 131 , X86_GRP_AVX = 132 , X86_GRP_AVX2 = 133 , X86_GRP_AVX512 = 134 , X86_GRP_BMI = 135 , X86_GRP_BMI2 = 136 , X86_GRP_CMOV = 137 , X86_GRP_F16C = 138 , X86_GRP_FMA = 139 , X86_GRP_FMA4 = 140 , X86_GRP_FSGSBASE = 141 , X86_GRP_HLE = 142 , X86_GRP_MMX = 143 , X86_GRP_MODE32 = 144 , X86_GRP_MODE64 = 145 , X86_GRP_RTM = 146 , X86_GRP_SHA = 147 , X86_GRP_SSE1 = 148 , X86_GRP_SSE2 = 149 , X86_GRP_SSE3 = 150 , X86_GRP_SSE41 = 151 , X86_GRP_SSE42 = 152 , X86_GRP_SSE4A = 153 , X86_GRP_SSSE3 = 154 , X86_GRP_PCLMUL = 155 , X86_GRP_XOP = 156 , X86_GRP_CDI = 157 , X86_GRP_ERI = 158 , X86_GRP_TBM = 159 , X86_GRP_16BITMODE = 160 , X86_GRP_NOT64BITMODE = 161 , X86_GRP_SGX = 162 , X86_GRP_DQI = 163 , X86_GRP_BWI = 164 , X86_GRP_PFI = 165 , X86_GRP_VLX = 166 , X86_GRP_SMAP = 167 , X86_GRP_NOVLX = 168 , X86_GRP_FPU = 169 , X86_GRP_ENDING = 170 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] XCORE_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] XCORE_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] XCORE_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] XCORE_OP_MEM = 3 , } # [repr (u32)] # [doc = " XCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_reg { XCORE_REG_INVALID = 0 , XCORE_REG_CP = 1 , XCORE_REG_DP = 2 , XCORE_REG_LR = 3 , XCORE_REG_SP = 4 , XCORE_REG_R0 = 5 , XCORE_REG_R1 = 6 , XCORE_REG_R2 = 7 , XCORE_REG_R3 = 8 , XCORE_REG_R4 = 9 , XCORE_REG_R5 = 10 , XCORE_REG_R6 = 11 , XCORE_REG_R7 = 12 , XCORE_REG_R8 = 13 , XCORE_REG_R9 = 14 , XCORE_REG_R10 = 15 , XCORE_REG_R11 = 16 , # [doc = "< pc"] XCORE_REG_PC = 17 , # [doc = "< save pc"] XCORE_REG_SCP = 18 , XCORE_REG_SSR = 19 , XCORE_REG_ET = 20 , XCORE_REG_ED = 21 , XCORE_REG_SED = 22 , XCORE_REG_KEP = 23 , XCORE_REG_KSP = 24 , XCORE_REG_ID = 25 , XCORE_REG_ENDING = 26 , } # [doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct xcore_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , # [doc = "< +1: forward, -1: backward"] pub direct : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of xcore_op_mem"] [:: std :: mem :: size_of :: < xcore_op_mem > () - 12usize] ; ["Alignment of xcore_op_mem"] [:: std :: mem :: align_of :: < xcore_op_mem > () - 4usize] ; ["Offset of field: xcore_op_mem::base"] [:: std :: mem :: offset_of ! (xcore_op_mem , base) - 0usize] ; ["Offset of field: xcore_op_mem::index"] [:: std :: mem :: offset_of ! (xcore_op_mem , index) - 1usize] ; ["Offset of field: xcore_op_mem::disp"] [:: std :: mem :: offset_of ! (xcore_op_mem , disp) - 4usize] ; ["Offset of field: xcore_op_mem::direct"] [:: std :: mem :: offset_of ! (xcore_op_mem , direct) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore_op { # [doc = "< operand type"] pub type_ : xcore_op_type , pub __bindgen_anon_1 : cs_xcore_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_xcore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : xcore_reg , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : xcore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_xcore_op__bindgen_ty_1 > () - 12usize] ; ["Alignment of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_xcore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op"] [:: std :: mem :: size_of :: < cs_xcore_op > () - 16usize] ; ["Alignment of cs_xcore_op"] [:: std :: mem :: align_of :: < cs_xcore_op > () - 4usize] ; ["Offset of field: cs_xcore_op::type_"] [:: std :: mem :: offset_of ! (cs_xcore_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_xcore_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore"] [:: std :: mem :: size_of :: < cs_xcore > () - 132usize] ; ["Alignment of cs_xcore"] [:: std :: mem :: align_of :: < cs_xcore > () - 4usize] ; ["Offset of field: cs_xcore::op_count"] [:: std :: mem :: offset_of ! (cs_xcore , op_count) - 0usize] ; ["Offset of field: cs_xcore::operands"] [:: std :: mem :: offset_of ! (cs_xcore , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " XCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn { XCORE_INS_INVALID = 0 , XCORE_INS_ADD = 1 , XCORE_INS_ANDNOT = 2 , XCORE_INS_AND = 3 , XCORE_INS_ASHR = 4 , XCORE_INS_BAU = 5 , XCORE_INS_BITREV = 6 , XCORE_INS_BLA = 7 , XCORE_INS_BLAT = 8 , XCORE_INS_BL = 9 , XCORE_INS_BF = 10 , XCORE_INS_BT = 11 , XCORE_INS_BU = 12 , XCORE_INS_BRU = 13 , XCORE_INS_BYTEREV = 14 , XCORE_INS_CHKCT = 15 , XCORE_INS_CLRE = 16 , XCORE_INS_CLRPT = 17 , XCORE_INS_CLRSR = 18 , XCORE_INS_CLZ = 19 , XCORE_INS_CRC8 = 20 , XCORE_INS_CRC32 = 21 , XCORE_INS_DCALL = 22 , XCORE_INS_DENTSP = 23 , XCORE_INS_DGETREG = 24 , XCORE_INS_DIVS = 25 , XCORE_INS_DIVU = 26 , XCORE_INS_DRESTSP = 27 , XCORE_INS_DRET = 28 , XCORE_INS_ECALLF = 29 , XCORE_INS_ECALLT = 30 , XCORE_INS_EDU = 31 , XCORE_INS_EEF = 32 , XCORE_INS_EET = 33 , XCORE_INS_EEU = 34 , XCORE_INS_ENDIN = 35 , XCORE_INS_ENTSP = 36 , XCORE_INS_EQ = 37 , XCORE_INS_EXTDP = 38 , XCORE_INS_EXTSP = 39 , XCORE_INS_FREER = 40 , XCORE_INS_FREET = 41 , XCORE_INS_GETD = 42 , XCORE_INS_GET = 43 , XCORE_INS_GETN = 44 , XCORE_INS_GETR = 45 , XCORE_INS_GETSR = 46 , XCORE_INS_GETST = 47 , XCORE_INS_GETTS = 48 , XCORE_INS_INCT = 49 , XCORE_INS_INIT = 50 , XCORE_INS_INPW = 51 , XCORE_INS_INSHR = 52 , XCORE_INS_INT = 53 , XCORE_INS_IN = 54 , XCORE_INS_KCALL = 55 , XCORE_INS_KENTSP = 56 , XCORE_INS_KRESTSP = 57 , XCORE_INS_KRET = 58 , XCORE_INS_LADD = 59 , XCORE_INS_LD16S = 60 , XCORE_INS_LD8U = 61 , XCORE_INS_LDA16 = 62 , XCORE_INS_LDAP = 63 , XCORE_INS_LDAW = 64 , XCORE_INS_LDC = 65 , XCORE_INS_LDW = 66 , XCORE_INS_LDIVU = 67 , XCORE_INS_LMUL = 68 , XCORE_INS_LSS = 69 , XCORE_INS_LSUB = 70 , XCORE_INS_LSU = 71 , XCORE_INS_MACCS = 72 , XCORE_INS_MACCU = 73 , XCORE_INS_MJOIN = 74 , XCORE_INS_MKMSK = 75 , XCORE_INS_MSYNC = 76 , XCORE_INS_MUL = 77 , XCORE_INS_NEG = 78 , XCORE_INS_NOT = 79 , XCORE_INS_OR = 80 , XCORE_INS_OUTCT = 81 , XCORE_INS_OUTPW = 82 , XCORE_INS_OUTSHR = 83 , XCORE_INS_OUTT = 84 , XCORE_INS_OUT = 85 , XCORE_INS_PEEK = 86 , XCORE_INS_REMS = 87 , XCORE_INS_REMU = 88 , XCORE_INS_RETSP = 89 , XCORE_INS_SETCLK = 90 , XCORE_INS_SET = 91 , XCORE_INS_SETC = 92 , XCORE_INS_SETD = 93 , XCORE_INS_SETEV = 94 , XCORE_INS_SETN = 95 , XCORE_INS_SETPSC = 96 , XCORE_INS_SETPT = 97 , XCORE_INS_SETRDY = 98 , XCORE_INS_SETSR = 99 , XCORE_INS_SETTW = 100 , XCORE_INS_SETV = 101 , XCORE_INS_SEXT = 102 , XCORE_INS_SHL = 103 , XCORE_INS_SHR = 104 , XCORE_INS_SSYNC = 105 , XCORE_INS_ST16 = 106 , XCORE_INS_ST8 = 107 , XCORE_INS_STW = 108 , XCORE_INS_SUB = 109 , XCORE_INS_SYNCR = 110 , XCORE_INS_TESTCT = 111 , XCORE_INS_TESTLCL = 112 , XCORE_INS_TESTWCT = 113 , XCORE_INS_TSETMR = 114 , XCORE_INS_START = 115 , XCORE_INS_WAITEF = 116 , XCORE_INS_WAITET = 117 , XCORE_INS_WAITEU = 118 , XCORE_INS_XOR = 119 , XCORE_INS_ZEXT = 120 , XCORE_INS_ENDING = 121 , } # [repr (u32)] # [doc = " Group of XCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn_group { # [doc = "< = CS_GRP_INVALID"] XCORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] XCORE_GRP_JUMP = 1 , XCORE_GRP_ENDING = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] TMS320C64X_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] TMS320C64X_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] TMS320C64X_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] TMS320C64X_OP_MEM = 3 , # [doc = "< Register pair for double word ops"] TMS320C64X_OP_REGPAIR = 64 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0 , TMS320C64X_MEM_DISP_CONSTANT = 1 , TMS320C64X_MEM_DISP_REGISTER = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0 , TMS320C64X_MEM_DIR_FW = 1 , TMS320C64X_MEM_DIR_BW = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0 , TMS320C64X_MEM_MOD_NO = 1 , TMS320C64X_MEM_MOD_PRE = 2 , TMS320C64X_MEM_MOD_POST = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tms320c64x_op_mem { # [doc = "< base register"] pub base : :: std :: os :: raw :: c_uint , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_uint , # [doc = "< unit of base and offset register"] pub unit : :: std :: os :: raw :: c_uint , # [doc = "< offset scaled"] pub scaled : :: std :: os :: raw :: c_uint , # [doc = "< displacement type"] pub disptype : :: std :: os :: raw :: c_uint , # [doc = "< direction"] pub direction : :: std :: os :: raw :: c_uint , # [doc = "< modification"] pub modify : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tms320c64x_op_mem"] [:: std :: mem :: size_of :: < tms320c64x_op_mem > () - 28usize] ; ["Alignment of tms320c64x_op_mem"] [:: std :: mem :: align_of :: < tms320c64x_op_mem > () - 4usize] ; ["Offset of field: tms320c64x_op_mem::base"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , base) - 0usize] ; ["Offset of field: tms320c64x_op_mem::disp"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disp) - 4usize] ; ["Offset of field: tms320c64x_op_mem::unit"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , unit) - 8usize] ; ["Offset of field: tms320c64x_op_mem::scaled"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , scaled) - 12usize] ; ["Offset of field: tms320c64x_op_mem::disptype"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disptype) - 16usize] ; ["Offset of field: tms320c64x_op_mem::direction"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , direction) - 20usize] ; ["Offset of field: tms320c64x_op_mem::modify"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , modify) - 24usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x_op { # [doc = "< operand type"] pub type_ : tms320c64x_op_type , pub __bindgen_anon_1 : cs_tms320c64x_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tms320c64x_op__bindgen_ty_1 { # [doc = "< register value for REG operand or first register for REGPAIR operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tms320c64x_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 28usize] ; ["Alignment of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op"] [:: std :: mem :: size_of :: < cs_tms320c64x_op > () - 32usize] ; ["Alignment of cs_tms320c64x_op"] [:: std :: mem :: align_of :: < cs_tms320c64x_op > () - 4usize] ; ["Offset of field: cs_tms320c64x_op::type_"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x { pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tms320c64x_op ; 8usize] , pub condition : cs_tms320c64x__bindgen_ty_1 , pub funit : cs_tms320c64x__bindgen_ty_2 , pub parallel : :: std :: os :: raw :: c_uint , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub zero : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::zero"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , zero) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_2 { pub unit : :: std :: os :: raw :: c_uint , pub side : :: std :: os :: raw :: c_uint , pub crosspath : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_2 > () - 12usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_2 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::unit"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , unit) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::side"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , side) - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::crosspath"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , crosspath) - 8usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x"] [:: std :: mem :: size_of :: < cs_tms320c64x > () - 284usize] ; ["Alignment of cs_tms320c64x"] [:: std :: mem :: align_of :: < cs_tms320c64x > () - 4usize] ; ["Offset of field: cs_tms320c64x::op_count"] [:: std :: mem :: offset_of ! (cs_tms320c64x , op_count) - 0usize] ; ["Offset of field: cs_tms320c64x::operands"] [:: std :: mem :: offset_of ! (cs_tms320c64x , operands) - 4usize] ; ["Offset of field: cs_tms320c64x::condition"] [:: std :: mem :: offset_of ! (cs_tms320c64x , condition) - 260usize] ; ["Offset of field: cs_tms320c64x::funit"] [:: std :: mem :: offset_of ! (cs_tms320c64x , funit) - 268usize] ; ["Offset of field: cs_tms320c64x::parallel"] [:: std :: mem :: offset_of ! (cs_tms320c64x , parallel) - 280usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel) } } impl tms320c64x_reg { pub const TMS320C64X_REG_EFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ECR ; } impl tms320c64x_reg { pub const TMS320C64X_REG_IFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ISR ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0 , TMS320C64X_REG_AMR = 1 , TMS320C64X_REG_CSR = 2 , TMS320C64X_REG_DIER = 3 , TMS320C64X_REG_DNUM = 4 , TMS320C64X_REG_ECR = 5 , TMS320C64X_REG_GFPGFR = 6 , TMS320C64X_REG_GPLYA = 7 , TMS320C64X_REG_GPLYB = 8 , TMS320C64X_REG_ICR = 9 , TMS320C64X_REG_IER = 10 , TMS320C64X_REG_IERR = 11 , TMS320C64X_REG_ILC = 12 , TMS320C64X_REG_IRP = 13 , TMS320C64X_REG_ISR = 14 , TMS320C64X_REG_ISTP = 15 , TMS320C64X_REG_ITSR = 16 , TMS320C64X_REG_NRP = 17 , TMS320C64X_REG_NTSR = 18 , TMS320C64X_REG_REP = 19 , TMS320C64X_REG_RILC = 20 , TMS320C64X_REG_SSR = 21 , TMS320C64X_REG_TSCH = 22 , TMS320C64X_REG_TSCL = 23 , TMS320C64X_REG_TSR = 24 , TMS320C64X_REG_A0 = 25 , TMS320C64X_REG_A1 = 26 , TMS320C64X_REG_A2 = 27 , TMS320C64X_REG_A3 = 28 , TMS320C64X_REG_A4 = 29 , TMS320C64X_REG_A5 = 30 , TMS320C64X_REG_A6 = 31 , TMS320C64X_REG_A7 = 32 , TMS320C64X_REG_A8 = 33 , TMS320C64X_REG_A9 = 34 , TMS320C64X_REG_A10 = 35 , TMS320C64X_REG_A11 = 36 , TMS320C64X_REG_A12 = 37 , TMS320C64X_REG_A13 = 38 , TMS320C64X_REG_A14 = 39 , TMS320C64X_REG_A15 = 40 , TMS320C64X_REG_A16 = 41 , TMS320C64X_REG_A17 = 42 , TMS320C64X_REG_A18 = 43 , TMS320C64X_REG_A19 = 44 , TMS320C64X_REG_A20 = 45 , TMS320C64X_REG_A21 = 46 , TMS320C64X_REG_A22 = 47 , TMS320C64X_REG_A23 = 48 , TMS320C64X_REG_A24 = 49 , TMS320C64X_REG_A25 = 50 , TMS320C64X_REG_A26 = 51 , TMS320C64X_REG_A27 = 52 , TMS320C64X_REG_A28 = 53 , TMS320C64X_REG_A29 = 54 , TMS320C64X_REG_A30 = 55 , TMS320C64X_REG_A31 = 56 , TMS320C64X_REG_B0 = 57 , TMS320C64X_REG_B1 = 58 , TMS320C64X_REG_B2 = 59 , TMS320C64X_REG_B3 = 60 , TMS320C64X_REG_B4 = 61 , TMS320C64X_REG_B5 = 62 , TMS320C64X_REG_B6 = 63 , TMS320C64X_REG_B7 = 64 , TMS320C64X_REG_B8 = 65 , TMS320C64X_REG_B9 = 66 , TMS320C64X_REG_B10 = 67 , TMS320C64X_REG_B11 = 68 , TMS320C64X_REG_B12 = 69 , TMS320C64X_REG_B13 = 70 , TMS320C64X_REG_B14 = 71 , TMS320C64X_REG_B15 = 72 , TMS320C64X_REG_B16 = 73 , TMS320C64X_REG_B17 = 74 , TMS320C64X_REG_B18 = 75 , TMS320C64X_REG_B19 = 76 , TMS320C64X_REG_B20 = 77 , TMS320C64X_REG_B21 = 78 , TMS320C64X_REG_B22 = 79 , TMS320C64X_REG_B23 = 80 , TMS320C64X_REG_B24 = 81 , TMS320C64X_REG_B25 = 82 , TMS320C64X_REG_B26 = 83 , TMS320C64X_REG_B27 = 84 , TMS320C64X_REG_B28 = 85 , TMS320C64X_REG_B29 = 86 , TMS320C64X_REG_B30 = 87 , TMS320C64X_REG_B31 = 88 , TMS320C64X_REG_PCE1 = 89 , TMS320C64X_REG_ENDING = 90 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0 , TMS320C64X_INS_ABS = 1 , TMS320C64X_INS_ABS2 = 2 , TMS320C64X_INS_ADD = 3 , TMS320C64X_INS_ADD2 = 4 , TMS320C64X_INS_ADD4 = 5 , TMS320C64X_INS_ADDAB = 6 , TMS320C64X_INS_ADDAD = 7 , TMS320C64X_INS_ADDAH = 8 , TMS320C64X_INS_ADDAW = 9 , TMS320C64X_INS_ADDK = 10 , TMS320C64X_INS_ADDKPC = 11 , TMS320C64X_INS_ADDU = 12 , TMS320C64X_INS_AND = 13 , TMS320C64X_INS_ANDN = 14 , TMS320C64X_INS_AVG2 = 15 , TMS320C64X_INS_AVGU4 = 16 , TMS320C64X_INS_B = 17 , TMS320C64X_INS_BDEC = 18 , TMS320C64X_INS_BITC4 = 19 , TMS320C64X_INS_BNOP = 20 , TMS320C64X_INS_BPOS = 21 , TMS320C64X_INS_CLR = 22 , TMS320C64X_INS_CMPEQ = 23 , TMS320C64X_INS_CMPEQ2 = 24 , TMS320C64X_INS_CMPEQ4 = 25 , TMS320C64X_INS_CMPGT = 26 , TMS320C64X_INS_CMPGT2 = 27 , TMS320C64X_INS_CMPGTU4 = 28 , TMS320C64X_INS_CMPLT = 29 , TMS320C64X_INS_CMPLTU = 30 , TMS320C64X_INS_DEAL = 31 , TMS320C64X_INS_DOTP2 = 32 , TMS320C64X_INS_DOTPN2 = 33 , TMS320C64X_INS_DOTPNRSU2 = 34 , TMS320C64X_INS_DOTPRSU2 = 35 , TMS320C64X_INS_DOTPSU4 = 36 , TMS320C64X_INS_DOTPU4 = 37 , TMS320C64X_INS_EXT = 38 , TMS320C64X_INS_EXTU = 39 , TMS320C64X_INS_GMPGTU = 40 , TMS320C64X_INS_GMPY4 = 41 , TMS320C64X_INS_LDB = 42 , TMS320C64X_INS_LDBU = 43 , TMS320C64X_INS_LDDW = 44 , TMS320C64X_INS_LDH = 45 , TMS320C64X_INS_LDHU = 46 , TMS320C64X_INS_LDNDW = 47 , TMS320C64X_INS_LDNW = 48 , TMS320C64X_INS_LDW = 49 , TMS320C64X_INS_LMBD = 50 , TMS320C64X_INS_MAX2 = 51 , TMS320C64X_INS_MAXU4 = 52 , TMS320C64X_INS_MIN2 = 53 , TMS320C64X_INS_MINU4 = 54 , TMS320C64X_INS_MPY = 55 , TMS320C64X_INS_MPY2 = 56 , TMS320C64X_INS_MPYH = 57 , TMS320C64X_INS_MPYHI = 58 , TMS320C64X_INS_MPYHIR = 59 , TMS320C64X_INS_MPYHL = 60 , TMS320C64X_INS_MPYHLU = 61 , TMS320C64X_INS_MPYHSLU = 62 , TMS320C64X_INS_MPYHSU = 63 , TMS320C64X_INS_MPYHU = 64 , TMS320C64X_INS_MPYHULS = 65 , TMS320C64X_INS_MPYHUS = 66 , TMS320C64X_INS_MPYLH = 67 , TMS320C64X_INS_MPYLHU = 68 , TMS320C64X_INS_MPYLI = 69 , TMS320C64X_INS_MPYLIR = 70 , TMS320C64X_INS_MPYLSHU = 71 , TMS320C64X_INS_MPYLUHS = 72 , TMS320C64X_INS_MPYSU = 73 , TMS320C64X_INS_MPYSU4 = 74 , TMS320C64X_INS_MPYU = 75 , TMS320C64X_INS_MPYU4 = 76 , TMS320C64X_INS_MPYUS = 77 , TMS320C64X_INS_MVC = 78 , TMS320C64X_INS_MVD = 79 , TMS320C64X_INS_MVK = 80 , TMS320C64X_INS_MVKL = 81 , TMS320C64X_INS_MVKLH = 82 , TMS320C64X_INS_NOP = 83 , TMS320C64X_INS_NORM = 84 , TMS320C64X_INS_OR = 85 , TMS320C64X_INS_PACK2 = 86 , TMS320C64X_INS_PACKH2 = 87 , TMS320C64X_INS_PACKH4 = 88 , TMS320C64X_INS_PACKHL2 = 89 , TMS320C64X_INS_PACKL4 = 90 , TMS320C64X_INS_PACKLH2 = 91 , TMS320C64X_INS_ROTL = 92 , TMS320C64X_INS_SADD = 93 , TMS320C64X_INS_SADD2 = 94 , TMS320C64X_INS_SADDU4 = 95 , TMS320C64X_INS_SADDUS2 = 96 , TMS320C64X_INS_SAT = 97 , TMS320C64X_INS_SET = 98 , TMS320C64X_INS_SHFL = 99 , TMS320C64X_INS_SHL = 100 , TMS320C64X_INS_SHLMB = 101 , TMS320C64X_INS_SHR = 102 , TMS320C64X_INS_SHR2 = 103 , TMS320C64X_INS_SHRMB = 104 , TMS320C64X_INS_SHRU = 105 , TMS320C64X_INS_SHRU2 = 106 , TMS320C64X_INS_SMPY = 107 , TMS320C64X_INS_SMPY2 = 108 , TMS320C64X_INS_SMPYH = 109 , TMS320C64X_INS_SMPYHL = 110 , TMS320C64X_INS_SMPYLH = 111 , TMS320C64X_INS_SPACK2 = 112 , TMS320C64X_INS_SPACKU4 = 113 , TMS320C64X_INS_SSHL = 114 , TMS320C64X_INS_SSHVL = 115 , TMS320C64X_INS_SSHVR = 116 , TMS320C64X_INS_SSUB = 117 , TMS320C64X_INS_STB = 118 , TMS320C64X_INS_STDW = 119 , TMS320C64X_INS_STH = 120 , TMS320C64X_INS_STNDW = 121 , TMS320C64X_INS_STNW = 122 , TMS320C64X_INS_STW = 123 , TMS320C64X_INS_SUB = 124 , TMS320C64X_INS_SUB2 = 125 , TMS320C64X_INS_SUB4 = 126 , TMS320C64X_INS_SUBAB = 127 , TMS320C64X_INS_SUBABS4 = 128 , TMS320C64X_INS_SUBAH = 129 , TMS320C64X_INS_SUBAW = 130 , TMS320C64X_INS_SUBC = 131 , TMS320C64X_INS_SUBU = 132 , TMS320C64X_INS_SWAP4 = 133 , TMS320C64X_INS_UNPKHU4 = 134 , TMS320C64X_INS_UNPKLU4 = 135 , TMS320C64X_INS_XOR = 136 , TMS320C64X_INS_XPND2 = 137 , TMS320C64X_INS_XPND4 = 138 , TMS320C64X_INS_IDLE = 139 , TMS320C64X_INS_MV = 140 , TMS320C64X_INS_NEG = 141 , TMS320C64X_INS_NOT = 142 , TMS320C64X_INS_SWAP2 = 143 , TMS320C64X_INS_ZERO = 144 , TMS320C64X_INS_ENDING = 145 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn_group { # [doc = "< = CS_GRP_INVALID"] TMS320C64X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] TMS320C64X_GRP_JUMP = 1 , TMS320C64X_GRP_FUNIT_D = 128 , TMS320C64X_GRP_FUNIT_L = 129 , TMS320C64X_GRP_FUNIT_M = 130 , TMS320C64X_GRP_FUNIT_S = 131 , TMS320C64X_GRP_FUNIT_NO = 132 , TMS320C64X_GRP_ENDING = 133 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0 , TMS320C64X_FUNIT_D = 1 , TMS320C64X_FUNIT_L = 2 , TMS320C64X_FUNIT_M = 3 , TMS320C64X_FUNIT_S = 4 , TMS320C64X_FUNIT_NO = 5 , } # [repr (u32)] # [doc = " M680X registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_reg { M680X_REG_INVALID = 0 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_A = 1 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_B = 2 , # [doc = "< HD6309"] M680X_REG_E = 3 , # [doc = "< HD6309"] M680X_REG_F = 4 , # [doc = "< HD6309"] M680X_REG_0 = 5 , # [doc = "< M6801/3/9, HD6301/9"] M680X_REG_D = 6 , # [doc = "< HD6309"] M680X_REG_W = 7 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_CC = 8 , # [doc = "< M6809/M6309"] M680X_REG_DP = 9 , # [doc = "< M6309"] M680X_REG_MD = 10 , # [doc = "< M6808"] M680X_REG_HX = 11 , # [doc = "< M6808"] M680X_REG_H = 12 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_X = 13 , # [doc = "< M6809/M6309"] M680X_REG_Y = 14 , # [doc = "< M6809/M6309"] M680X_REG_S = 15 , # [doc = "< M6809/M6309"] M680X_REG_U = 16 , # [doc = "< M6309"] M680X_REG_V = 17 , # [doc = "< M6309"] M680X_REG_Q = 18 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_PC = 19 , # [doc = "< CPU12"] M680X_REG_TMP2 = 20 , # [doc = "< CPU12"] M680X_REG_TMP3 = 21 , # [doc = "< <-- mark the end of the list of registers"] M680X_REG_ENDING = 22 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M680X_OP_INVALID = 0 , # [doc = "< = Register operand."] M680X_OP_REGISTER = 1 , # [doc = "< = Immediate operand."] M680X_OP_IMMEDIATE = 2 , # [doc = "< = Indexed addressing operand."] M680X_OP_INDEXED = 3 , # [doc = "< = Extended addressing operand."] M680X_OP_EXTENDED = 4 , # [doc = "< = Direct addressing operand."] M680X_OP_DIRECT = 5 , # [doc = "< = Relative addressing operand."] M680X_OP_RELATIVE = 6 , # [doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."] M680X_OP_CONSTANT = 7 , } # [doc = " Instruction's operand referring to indexed addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_idx { # [doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"] pub base_reg : m680x_reg , # [doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"] pub offset_reg : m680x_reg , # [doc = "< 5-,8- or 16-bit offset. See also offset_bits."] pub offset : i16 , # [doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"] pub offset_addr : u16 , # [doc = "< offset width in bits for indexed addressing"] pub offset_bits : u8 , # [doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"] pub inc_dec : i8 , # [doc = "< 8-bit flags (see above)"] pub flags : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_idx"] [:: std :: mem :: size_of :: < m680x_op_idx > () - 16usize] ; ["Alignment of m680x_op_idx"] [:: std :: mem :: align_of :: < m680x_op_idx > () - 4usize] ; ["Offset of field: m680x_op_idx::base_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , base_reg) - 0usize] ; ["Offset of field: m680x_op_idx::offset_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_reg) - 4usize] ; ["Offset of field: m680x_op_idx::offset"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset) - 8usize] ; ["Offset of field: m680x_op_idx::offset_addr"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_addr) - 10usize] ; ["Offset of field: m680x_op_idx::offset_bits"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_bits) - 12usize] ; ["Offset of field: m680x_op_idx::inc_dec"] [:: std :: mem :: offset_of ! (m680x_op_idx , inc_dec) - 13usize] ; ["Offset of field: m680x_op_idx::flags"] [:: std :: mem :: offset_of ! (m680x_op_idx , flags) - 14usize] ; } ; # [doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_rel { # [doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."] pub address : u16 , # [doc = "< the offset/displacement value"] pub offset : i16 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_rel"] [:: std :: mem :: size_of :: < m680x_op_rel > () - 4usize] ; ["Alignment of m680x_op_rel"] [:: std :: mem :: align_of :: < m680x_op_rel > () - 2usize] ; ["Offset of field: m680x_op_rel::address"] [:: std :: mem :: offset_of ! (m680x_op_rel , address) - 0usize] ; ["Offset of field: m680x_op_rel::offset"] [:: std :: mem :: offset_of ! (m680x_op_rel , offset) - 2usize] ; } ; # [doc = " Instruction's operand referring to extended addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_ext { # [doc = "< The absolute address"] pub address : u16 , # [doc = "< true if extended indirect addressing"] pub indirect : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_ext"] [:: std :: mem :: size_of :: < m680x_op_ext > () - 4usize] ; ["Alignment of m680x_op_ext"] [:: std :: mem :: align_of :: < m680x_op_ext > () - 2usize] ; ["Offset of field: m680x_op_ext::address"] [:: std :: mem :: offset_of ! (m680x_op_ext , address) - 0usize] ; ["Offset of field: m680x_op_ext::indirect"] [:: std :: mem :: offset_of ! (m680x_op_ext , indirect) - 2usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x_op { pub type_ : m680x_op_type , pub __bindgen_anon_1 : cs_m680x_op__bindgen_ty_1 , # [doc = "< size of this operand (in bytes)"] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m680x_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< register value for REG operand"] pub reg : m680x_reg , # [doc = "< Indexed addressing operand"] pub idx : m680x_op_idx , # [doc = "< Relative address. operand (Bcc/LBcc)"] pub rel : m680x_op_rel , # [doc = "< Extended address"] pub ext : m680x_op_ext , # [doc = "<</ Direct address (lower 8-bit)"] pub direct_addr : u8 , # [doc = "< constant value (bit index, page nr.)"] pub const_val : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m680x_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m680x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::idx"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , idx) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::rel"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , rel) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , ext) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::direct_addr"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , direct_addr) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::const_val"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , const_val) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op"] [:: std :: mem :: size_of :: < cs_m680x_op > () - 24usize] ; ["Alignment of cs_m680x_op"] [:: std :: mem :: align_of :: < cs_m680x_op > () - 4usize] ; ["Offset of field: cs_m680x_op::type_"] [:: std :: mem :: offset_of ! (cs_m680x_op , type_) - 0usize] ; ["Offset of field: cs_m680x_op::size"] [:: std :: mem :: offset_of ! (cs_m680x_op , size) - 20usize] ; ["Offset of field: cs_m680x_op::access"] [:: std :: mem :: offset_of ! (cs_m680x_op , access) - 21usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access) } } # [repr (u32)] # [doc = " Group of M680X instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_group_type { M680X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M680X_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] M680X_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] M680X_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] M680X_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] M680X_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEDGE; not used"] M680X_GRP_PRIV = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M680X_GRP_BRAREL = 7 , M680X_GRP_ENDING = 8 , } # [doc = " The M680X instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x { # [doc = "< See: M680X instruction flags"] pub flags : u8 , # [doc = "< number of operands for the instruction or 0"] pub op_count : u8 , # [doc = "< operands for this insn."] pub operands : [cs_m680x_op ; 9usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x"] [:: std :: mem :: size_of :: < cs_m680x > () - 220usize] ; ["Alignment of cs_m680x"] [:: std :: mem :: align_of :: < cs_m680x > () - 4usize] ; ["Offset of field: cs_m680x::flags"] [:: std :: mem :: offset_of ! (cs_m680x , flags) - 0usize] ; ["Offset of field: cs_m680x::op_count"] [:: std :: mem :: offset_of ! (cs_m680x , op_count) - 1usize] ; ["Offset of field: cs_m680x::operands"] [:: std :: mem :: offset_of ! (cs_m680x , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " M680X instruction IDs"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_insn { M680X_INS_INVLD = 0 , # [doc = "< M6800/1/2/3"] M680X_INS_ABA = 1 , M680X_INS_ABX = 2 , M680X_INS_ABY = 3 , M680X_INS_ADC = 4 , M680X_INS_ADCA = 5 , M680X_INS_ADCB = 6 , M680X_INS_ADCD = 7 , M680X_INS_ADCR = 8 , M680X_INS_ADD = 9 , M680X_INS_ADDA = 10 , M680X_INS_ADDB = 11 , M680X_INS_ADDD = 12 , M680X_INS_ADDE = 13 , M680X_INS_ADDF = 14 , M680X_INS_ADDR = 15 , M680X_INS_ADDW = 16 , M680X_INS_AIM = 17 , M680X_INS_AIS = 18 , M680X_INS_AIX = 19 , M680X_INS_AND = 20 , M680X_INS_ANDA = 21 , M680X_INS_ANDB = 22 , M680X_INS_ANDCC = 23 , M680X_INS_ANDD = 24 , M680X_INS_ANDR = 25 , M680X_INS_ASL = 26 , M680X_INS_ASLA = 27 , M680X_INS_ASLB = 28 , # [doc = "< or LSLD"] M680X_INS_ASLD = 29 , M680X_INS_ASR = 30 , M680X_INS_ASRA = 31 , M680X_INS_ASRB = 32 , M680X_INS_ASRD = 33 , M680X_INS_ASRX = 34 , M680X_INS_BAND = 35 , # [doc = "< or BHS"] M680X_INS_BCC = 36 , M680X_INS_BCLR = 37 , # [doc = "< or BLO"] M680X_INS_BCS = 38 , M680X_INS_BEOR = 39 , M680X_INS_BEQ = 40 , M680X_INS_BGE = 41 , M680X_INS_BGND = 42 , M680X_INS_BGT = 43 , M680X_INS_BHCC = 44 , M680X_INS_BHCS = 45 , M680X_INS_BHI = 46 , M680X_INS_BIAND = 47 , M680X_INS_BIEOR = 48 , M680X_INS_BIH = 49 , M680X_INS_BIL = 50 , M680X_INS_BIOR = 51 , M680X_INS_BIT = 52 , M680X_INS_BITA = 53 , M680X_INS_BITB = 54 , M680X_INS_BITD = 55 , M680X_INS_BITMD = 56 , M680X_INS_BLE = 57 , M680X_INS_BLS = 58 , M680X_INS_BLT = 59 , M680X_INS_BMC = 60 , M680X_INS_BMI = 61 , M680X_INS_BMS = 62 , M680X_INS_BNE = 63 , M680X_INS_BOR = 64 , M680X_INS_BPL = 65 , M680X_INS_BRCLR = 66 , M680X_INS_BRSET = 67 , M680X_INS_BRA = 68 , M680X_INS_BRN = 69 , M680X_INS_BSET = 70 , M680X_INS_BSR = 71 , M680X_INS_BVC = 72 , M680X_INS_BVS = 73 , M680X_INS_CALL = 74 , # [doc = "< M6800/1/2/3"] M680X_INS_CBA = 75 , M680X_INS_CBEQ = 76 , M680X_INS_CBEQA = 77 , M680X_INS_CBEQX = 78 , # [doc = "< M6800/1/2/3"] M680X_INS_CLC = 79 , # [doc = "< M6800/1/2/3"] M680X_INS_CLI = 80 , M680X_INS_CLR = 81 , M680X_INS_CLRA = 82 , M680X_INS_CLRB = 83 , M680X_INS_CLRD = 84 , M680X_INS_CLRE = 85 , M680X_INS_CLRF = 86 , M680X_INS_CLRH = 87 , M680X_INS_CLRW = 88 , M680X_INS_CLRX = 89 , # [doc = "< M6800/1/2/3"] M680X_INS_CLV = 90 , M680X_INS_CMP = 91 , M680X_INS_CMPA = 92 , M680X_INS_CMPB = 93 , M680X_INS_CMPD = 94 , M680X_INS_CMPE = 95 , M680X_INS_CMPF = 96 , M680X_INS_CMPR = 97 , M680X_INS_CMPS = 98 , M680X_INS_CMPU = 99 , M680X_INS_CMPW = 100 , M680X_INS_CMPX = 101 , M680X_INS_CMPY = 102 , M680X_INS_COM = 103 , M680X_INS_COMA = 104 , M680X_INS_COMB = 105 , M680X_INS_COMD = 106 , M680X_INS_COME = 107 , M680X_INS_COMF = 108 , M680X_INS_COMW = 109 , M680X_INS_COMX = 110 , M680X_INS_CPD = 111 , M680X_INS_CPHX = 112 , M680X_INS_CPS = 113 , # [doc = "< M6800/1/2/3"] M680X_INS_CPX = 114 , M680X_INS_CPY = 115 , M680X_INS_CWAI = 116 , M680X_INS_DAA = 117 , M680X_INS_DBEQ = 118 , M680X_INS_DBNE = 119 , M680X_INS_DBNZ = 120 , M680X_INS_DBNZA = 121 , M680X_INS_DBNZX = 122 , M680X_INS_DEC = 123 , M680X_INS_DECA = 124 , M680X_INS_DECB = 125 , M680X_INS_DECD = 126 , M680X_INS_DECE = 127 , M680X_INS_DECF = 128 , M680X_INS_DECW = 129 , M680X_INS_DECX = 130 , # [doc = "< M6800/1/2/3"] M680X_INS_DES = 131 , # [doc = "< M6800/1/2/3"] M680X_INS_DEX = 132 , M680X_INS_DEY = 133 , M680X_INS_DIV = 134 , M680X_INS_DIVD = 135 , M680X_INS_DIVQ = 136 , M680X_INS_EDIV = 137 , M680X_INS_EDIVS = 138 , M680X_INS_EIM = 139 , M680X_INS_EMACS = 140 , M680X_INS_EMAXD = 141 , M680X_INS_EMAXM = 142 , M680X_INS_EMIND = 143 , M680X_INS_EMINM = 144 , M680X_INS_EMUL = 145 , M680X_INS_EMULS = 146 , M680X_INS_EOR = 147 , M680X_INS_EORA = 148 , M680X_INS_EORB = 149 , M680X_INS_EORD = 150 , M680X_INS_EORR = 151 , M680X_INS_ETBL = 152 , M680X_INS_EXG = 153 , M680X_INS_FDIV = 154 , M680X_INS_IBEQ = 155 , M680X_INS_IBNE = 156 , M680X_INS_IDIV = 157 , M680X_INS_IDIVS = 158 , M680X_INS_ILLGL = 159 , M680X_INS_INC = 160 , M680X_INS_INCA = 161 , M680X_INS_INCB = 162 , M680X_INS_INCD = 163 , M680X_INS_INCE = 164 , M680X_INS_INCF = 165 , M680X_INS_INCW = 166 , M680X_INS_INCX = 167 , # [doc = "< M6800/1/2/3"] M680X_INS_INS = 168 , # [doc = "< M6800/1/2/3"] M680X_INS_INX = 169 , M680X_INS_INY = 170 , M680X_INS_JMP = 171 , M680X_INS_JSR = 172 , # [doc = "< or LBHS"] M680X_INS_LBCC = 173 , # [doc = "< or LBLO"] M680X_INS_LBCS = 174 , M680X_INS_LBEQ = 175 , M680X_INS_LBGE = 176 , M680X_INS_LBGT = 177 , M680X_INS_LBHI = 178 , M680X_INS_LBLE = 179 , M680X_INS_LBLS = 180 , M680X_INS_LBLT = 181 , M680X_INS_LBMI = 182 , M680X_INS_LBNE = 183 , M680X_INS_LBPL = 184 , M680X_INS_LBRA = 185 , M680X_INS_LBRN = 186 , M680X_INS_LBSR = 187 , M680X_INS_LBVC = 188 , M680X_INS_LBVS = 189 , M680X_INS_LDA = 190 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAA = 191 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAB = 192 , M680X_INS_LDB = 193 , M680X_INS_LDBT = 194 , M680X_INS_LDD = 195 , M680X_INS_LDE = 196 , M680X_INS_LDF = 197 , M680X_INS_LDHX = 198 , M680X_INS_LDMD = 199 , M680X_INS_LDQ = 200 , M680X_INS_LDS = 201 , M680X_INS_LDU = 202 , M680X_INS_LDW = 203 , M680X_INS_LDX = 204 , M680X_INS_LDY = 205 , M680X_INS_LEAS = 206 , M680X_INS_LEAU = 207 , M680X_INS_LEAX = 208 , M680X_INS_LEAY = 209 , M680X_INS_LSL = 210 , M680X_INS_LSLA = 211 , M680X_INS_LSLB = 212 , M680X_INS_LSLD = 213 , M680X_INS_LSLX = 214 , M680X_INS_LSR = 215 , M680X_INS_LSRA = 216 , M680X_INS_LSRB = 217 , # [doc = "< or ASRD"] M680X_INS_LSRD = 218 , M680X_INS_LSRW = 219 , M680X_INS_LSRX = 220 , M680X_INS_MAXA = 221 , M680X_INS_MAXM = 222 , M680X_INS_MEM = 223 , M680X_INS_MINA = 224 , M680X_INS_MINM = 225 , M680X_INS_MOV = 226 , M680X_INS_MOVB = 227 , M680X_INS_MOVW = 228 , M680X_INS_MUL = 229 , M680X_INS_MULD = 230 , M680X_INS_NEG = 231 , M680X_INS_NEGA = 232 , M680X_INS_NEGB = 233 , M680X_INS_NEGD = 234 , M680X_INS_NEGX = 235 , M680X_INS_NOP = 236 , M680X_INS_NSA = 237 , M680X_INS_OIM = 238 , M680X_INS_ORA = 239 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAA = 240 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAB = 241 , M680X_INS_ORB = 242 , M680X_INS_ORCC = 243 , M680X_INS_ORD = 244 , M680X_INS_ORR = 245 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHA = 246 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHB = 247 , M680X_INS_PSHC = 248 , M680X_INS_PSHD = 249 , M680X_INS_PSHH = 250 , M680X_INS_PSHS = 251 , M680X_INS_PSHSW = 252 , M680X_INS_PSHU = 253 , M680X_INS_PSHUW = 254 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHX = 255 , M680X_INS_PSHY = 256 , # [doc = "< M6800/1/2/3"] M680X_INS_PULA = 257 , # [doc = "< M6800/1/2/3"] M680X_INS_PULB = 258 , M680X_INS_PULC = 259 , M680X_INS_PULD = 260 , M680X_INS_PULH = 261 , M680X_INS_PULS = 262 , M680X_INS_PULSW = 263 , M680X_INS_PULU = 264 , M680X_INS_PULUW = 265 , # [doc = "< M6800/1/2/3"] M680X_INS_PULX = 266 , M680X_INS_PULY = 267 , M680X_INS_REV = 268 , M680X_INS_REVW = 269 , M680X_INS_ROL = 270 , M680X_INS_ROLA = 271 , M680X_INS_ROLB = 272 , M680X_INS_ROLD = 273 , M680X_INS_ROLW = 274 , M680X_INS_ROLX = 275 , M680X_INS_ROR = 276 , M680X_INS_RORA = 277 , M680X_INS_RORB = 278 , M680X_INS_RORD = 279 , M680X_INS_RORW = 280 , M680X_INS_RORX = 281 , M680X_INS_RSP = 282 , M680X_INS_RTC = 283 , M680X_INS_RTI = 284 , M680X_INS_RTS = 285 , # [doc = "< M6800/1/2/3"] M680X_INS_SBA = 286 , M680X_INS_SBC = 287 , M680X_INS_SBCA = 288 , M680X_INS_SBCB = 289 , M680X_INS_SBCD = 290 , M680X_INS_SBCR = 291 , M680X_INS_SEC = 292 , M680X_INS_SEI = 293 , M680X_INS_SEV = 294 , M680X_INS_SEX = 295 , M680X_INS_SEXW = 296 , M680X_INS_SLP = 297 , M680X_INS_STA = 298 , # [doc = "< M6800/1/2/3"] M680X_INS_STAA = 299 , # [doc = "< M6800/1/2/3"] M680X_INS_STAB = 300 , M680X_INS_STB = 301 , M680X_INS_STBT = 302 , M680X_INS_STD = 303 , M680X_INS_STE = 304 , M680X_INS_STF = 305 , M680X_INS_STOP = 306 , M680X_INS_STHX = 307 , M680X_INS_STQ = 308 , M680X_INS_STS = 309 , M680X_INS_STU = 310 , M680X_INS_STW = 311 , M680X_INS_STX = 312 , M680X_INS_STY = 313 , M680X_INS_SUB = 314 , M680X_INS_SUBA = 315 , M680X_INS_SUBB = 316 , M680X_INS_SUBD = 317 , M680X_INS_SUBE = 318 , M680X_INS_SUBF = 319 , M680X_INS_SUBR = 320 , M680X_INS_SUBW = 321 , M680X_INS_SWI = 322 , M680X_INS_SWI2 = 323 , M680X_INS_SWI3 = 324 , M680X_INS_SYNC = 325 , # [doc = "< M6800/1/2/3"] M680X_INS_TAB = 326 , # [doc = "< M6800/1/2/3"] M680X_INS_TAP = 327 , M680X_INS_TAX = 328 , # [doc = "< M6800/1/2/3"] M680X_INS_TBA = 329 , M680X_INS_TBEQ = 330 , M680X_INS_TBL = 331 , M680X_INS_TBNE = 332 , M680X_INS_TEST = 333 , M680X_INS_TFM = 334 , M680X_INS_TFR = 335 , M680X_INS_TIM = 336 , # [doc = "< M6800/1/2/3"] M680X_INS_TPA = 337 , M680X_INS_TST = 338 , M680X_INS_TSTA = 339 , M680X_INS_TSTB = 340 , M680X_INS_TSTD = 341 , M680X_INS_TSTE = 342 , M680X_INS_TSTF = 343 , M680X_INS_TSTW = 344 , M680X_INS_TSTX = 345 , # [doc = "< M6800/1/2/3"] M680X_INS_TSX = 346 , M680X_INS_TSY = 347 , M680X_INS_TXA = 348 , # [doc = "< M6800/1/2/3"] M680X_INS_TXS = 349 , M680X_INS_TYS = 350 , # [doc = "< M6800/1/2/3"] M680X_INS_WAI = 351 , M680X_INS_WAIT = 352 , M680X_INS_WAV = 353 , M680X_INS_WAVR = 354 , # [doc = "< HD6301"] M680X_INS_XGDX = 355 , M680X_INS_XGDY = 356 , M680X_INS_ENDING = 357 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_evm { # [doc = "< number of items popped from the stack"] pub pop : :: std :: os :: raw :: c_uchar , # [doc = "< number of items pushed into the stack"] pub push : :: std :: os :: raw :: c_uchar , # [doc = "< gas fee for the instruction"] pub fee : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_evm"] [:: std :: mem :: size_of :: < cs_evm > () - 8usize] ; ["Alignment of cs_evm"] [:: std :: mem :: align_of :: < cs_evm > () - 4usize] ; ["Offset of field: cs_evm::pop"] [:: std :: mem :: offset_of ! (cs_evm , pop) - 0usize] ; ["Offset of field: cs_evm::push"] [:: std :: mem :: offset_of ! (cs_evm , push) - 1usize] ; ["Offset of field: cs_evm::fee"] [:: std :: mem :: offset_of ! (cs_evm , fee) - 4usize] ; } ; # [repr (u32)] # [doc = " EVM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn { EVM_INS_STOP = 0 , EVM_INS_ADD = 1 , EVM_INS_MUL = 2 , EVM_INS_SUB = 3 , EVM_INS_DIV = 4 , EVM_INS_SDIV = 5 , EVM_INS_MOD = 6 , EVM_INS_SMOD = 7 , EVM_INS_ADDMOD = 8 , EVM_INS_MULMOD = 9 , EVM_INS_EXP = 10 , EVM_INS_SIGNEXTEND = 11 , EVM_INS_LT = 16 , EVM_INS_GT = 17 , EVM_INS_SLT = 18 , EVM_INS_SGT = 19 , EVM_INS_EQ = 20 , EVM_INS_ISZERO = 21 , EVM_INS_AND = 22 , EVM_INS_OR = 23 , EVM_INS_XOR = 24 , EVM_INS_NOT = 25 , EVM_INS_BYTE = 26 , EVM_INS_SHA3 = 32 , EVM_INS_ADDRESS = 48 , EVM_INS_BALANCE = 49 , EVM_INS_ORIGIN = 50 , EVM_INS_CALLER = 51 , EVM_INS_CALLVALUE = 52 , EVM_INS_CALLDATALOAD = 53 , EVM_INS_CALLDATASIZE = 54 , EVM_INS_CALLDATACOPY = 55 , EVM_INS_CODESIZE = 56 , EVM_INS_CODECOPY = 57 , EVM_INS_GASPRICE = 58 , EVM_INS_EXTCODESIZE = 59 , EVM_INS_EXTCODECOPY = 60 , EVM_INS_RETURNDATASIZE = 61 , EVM_INS_RETURNDATACOPY = 62 , EVM_INS_BLOCKHASH = 64 , EVM_INS_COINBASE = 65 , EVM_INS_TIMESTAMP = 66 , EVM_INS_NUMBER = 67 , EVM_INS_DIFFICULTY = 68 , EVM_INS_GASLIMIT = 69 , EVM_INS_POP = 80 , EVM_INS_MLOAD = 81 , EVM_INS_MSTORE = 82 , EVM_INS_MSTORE8 = 83 , EVM_INS_SLOAD = 84 , EVM_INS_SSTORE = 85 , EVM_INS_JUMP = 86 , EVM_INS_JUMPI = 87 , EVM_INS_PC = 88 , EVM_INS_MSIZE = 89 , EVM_INS_GAS = 90 , EVM_INS_JUMPDEST = 91 , EVM_INS_PUSH1 = 96 , EVM_INS_PUSH2 = 97 , EVM_INS_PUSH3 = 98 , EVM_INS_PUSH4 = 99 , EVM_INS_PUSH5 = 100 , EVM_INS_PUSH6 = 101 , EVM_INS_PUSH7 = 102 , EVM_INS_PUSH8 = 103 , EVM_INS_PUSH9 = 104 , EVM_INS_PUSH10 = 105 , EVM_INS_PUSH11 = 106 , EVM_INS_PUSH12 = 107 , EVM_INS_PUSH13 = 108 , EVM_INS_PUSH14 = 109 , EVM_INS_PUSH15 = 110 , EVM_INS_PUSH16 = 111 , EVM_INS_PUSH17 = 112 , EVM_INS_PUSH18 = 113 , EVM_INS_PUSH19 = 114 , EVM_INS_PUSH20 = 115 , EVM_INS_PUSH21 = 116 , EVM_INS_PUSH22 = 117 , EVM_INS_PUSH23 = 118 , EVM_INS_PUSH24 = 119 , EVM_INS_PUSH25 = 120 , EVM_INS_PUSH26 = 121 , EVM_INS_PUSH27 = 122 , EVM_INS_PUSH28 = 123 , EVM_INS_PUSH29 = 124 , EVM_INS_PUSH30 = 125 , EVM_INS_PUSH31 = 126 , EVM_INS_PUSH32 = 127 , EVM_INS_DUP1 = 128 , EVM_INS_DUP2 = 129 , EVM_INS_DUP3 = 130 , EVM_INS_DUP4 = 131 , EVM_INS_DUP5 = 132 , EVM_INS_DUP6 = 133 , EVM_INS_DUP7 = 134 , EVM_INS_DUP8 = 135 , EVM_INS_DUP9 = 136 , EVM_INS_DUP10 = 137 , EVM_INS_DUP11 = 138 , EVM_INS_DUP12 = 139 , EVM_INS_DUP13 = 140 , EVM_INS_DUP14 = 141 , EVM_INS_DUP15 = 142 , EVM_INS_DUP16 = 143 , EVM_INS_SWAP1 = 144 , EVM_INS_SWAP2 = 145 , EVM_INS_SWAP3 = 146 , EVM_INS_SWAP4 = 147 , EVM_INS_SWAP5 = 148 , EVM_INS_SWAP6 = 149 , EVM_INS_SWAP7 = 150 , EVM_INS_SWAP8 = 151 , EVM_INS_SWAP9 = 152 , EVM_INS_SWAP10 = 153 , EVM_INS_SWAP11 = 154 , EVM_INS_SWAP12 = 155 , EVM_INS_SWAP13 = 156 , EVM_INS_SWAP14 = 157 , EVM_INS_SWAP15 = 158 , EVM_INS_SWAP16 = 159 , EVM_INS_LOG0 = 160 , EVM_INS_LOG1 = 161 , EVM_INS_LOG2 = 162 , EVM_INS_LOG3 = 163 , EVM_INS_LOG4 = 164 , EVM_INS_CREATE = 240 , EVM_INS_CALL = 241 , EVM_INS_CALLCODE = 242 , EVM_INS_RETURN = 243 , EVM_INS_DELEGATECALL = 244 , EVM_INS_CALLBLACKBOX = 245 , EVM_INS_STATICCALL = 250 , EVM_INS_REVERT = 253 , EVM_INS_SUICIDE = 255 , EVM_INS_INVALID = 512 , EVM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of EVM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn_group { # [doc = "< = CS_GRP_INVALID"] EVM_GRP_INVALID = 0 , # [doc = "< all jump instructions"] EVM_GRP_JUMP = 1 , # [doc = "< math instructions"] EVM_GRP_MATH = 8 , # [doc = "< instructions write to stack"] EVM_GRP_STACK_WRITE = 9 , # [doc = "< instructions read from stack"] EVM_GRP_STACK_READ = 10 , # [doc = "< instructions write to memory"] EVM_GRP_MEM_WRITE = 11 , # [doc = "< instructions read from memory"] EVM_GRP_MEM_READ = 12 , # [doc = "< instructions write to storage"] EVM_GRP_STORE_WRITE = 13 , # [doc = "< instructions read from storage"] EVM_GRP_STORE_READ = 14 , # [doc = "< instructions halt execution"] EVM_GRP_HALT = 15 , # [doc = "< <-- mark the end of the list of groups"] EVM_GRP_ENDING = 16 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_op_type { RISCV_OP_INVALID = 0 , RISCV_OP_REG = 1 , RISCV_OP_IMM = 2 , RISCV_OP_MEM = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct riscv_op_mem { pub base : :: std :: os :: raw :: c_uint , pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of riscv_op_mem"] [:: std :: mem :: size_of :: < riscv_op_mem > () - 16usize] ; ["Alignment of riscv_op_mem"] [:: std :: mem :: align_of :: < riscv_op_mem > () - 8usize] ; ["Offset of field: riscv_op_mem::base"] [:: std :: mem :: offset_of ! (riscv_op_mem , base) - 0usize] ; ["Offset of field: riscv_op_mem::disp"] [:: std :: mem :: offset_of ! (riscv_op_mem , disp) - 8usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv_op { pub type_ : riscv_op_type , pub __bindgen_anon_1 : cs_riscv_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_riscv_op__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub imm : i64 , pub mem : riscv_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_riscv_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_riscv_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op"] [:: std :: mem :: size_of :: < cs_riscv_op > () - 24usize] ; ["Alignment of cs_riscv_op"] [:: std :: mem :: align_of :: < cs_riscv_op > () - 8usize] ; ["Offset of field: cs_riscv_op::type_"] [:: std :: mem :: offset_of ! (cs_riscv_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv { pub need_effective_addr : bool , pub op_count : u8 , pub operands : [cs_riscv_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv"] [:: std :: mem :: size_of :: < cs_riscv > () - 200usize] ; ["Alignment of cs_riscv"] [:: std :: mem :: align_of :: < cs_riscv > () - 8usize] ; ["Offset of field: cs_riscv::need_effective_addr"] [:: std :: mem :: offset_of ! (cs_riscv , need_effective_addr) - 0usize] ; ["Offset of field: cs_riscv::op_count"] [:: std :: mem :: offset_of ! (cs_riscv , op_count) - 1usize] ; ["Offset of field: cs_riscv::operands"] [:: std :: mem :: offset_of ! (cs_riscv , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}" , self . need_effective_addr , self . op_count , self . operands) } } impl riscv_reg { pub const RISCV_REG_ZERO : riscv_reg = riscv_reg :: RISCV_REG_X0 ; } impl riscv_reg { pub const RISCV_REG_RA : riscv_reg = riscv_reg :: RISCV_REG_X1 ; } impl riscv_reg { pub const RISCV_REG_SP : riscv_reg = riscv_reg :: RISCV_REG_X2 ; } impl riscv_reg { pub const RISCV_REG_GP : riscv_reg = riscv_reg :: RISCV_REG_X3 ; } impl riscv_reg { pub const RISCV_REG_TP : riscv_reg = riscv_reg :: RISCV_REG_X4 ; } impl riscv_reg { pub const RISCV_REG_T0 : riscv_reg = riscv_reg :: RISCV_REG_X5 ; } impl riscv_reg { pub const RISCV_REG_T1 : riscv_reg = riscv_reg :: RISCV_REG_X6 ; } impl riscv_reg { pub const RISCV_REG_T2 : riscv_reg = riscv_reg :: RISCV_REG_X7 ; } impl riscv_reg { pub const RISCV_REG_S0 : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_FP : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_S1 : riscv_reg = riscv_reg :: RISCV_REG_X9 ; } impl riscv_reg { pub const RISCV_REG_A0 : riscv_reg = riscv_reg :: RISCV_REG_X10 ; } impl riscv_reg { pub const RISCV_REG_A1 : riscv_reg = riscv_reg :: RISCV_REG_X11 ; } impl riscv_reg { pub const RISCV_REG_A2 : riscv_reg = riscv_reg :: RISCV_REG_X12 ; } impl riscv_reg { pub const RISCV_REG_A3 : riscv_reg = riscv_reg :: RISCV_REG_X13 ; } impl riscv_reg { pub const RISCV_REG_A4 : riscv_reg = riscv_reg :: RISCV_REG_X14 ; } impl riscv_reg { pub const RISCV_REG_A5 : riscv_reg = riscv_reg :: RISCV_REG_X15 ; } impl riscv_reg { pub const RISCV_REG_A6 : riscv_reg = riscv_reg :: RISCV_REG_X16 ; } impl riscv_reg { pub const RISCV_REG_A7 : riscv_reg = riscv_reg :: RISCV_REG_X17 ; } impl riscv_reg { pub const RISCV_REG_S2 : riscv_reg = riscv_reg :: RISCV_REG_X18 ; } impl riscv_reg { pub const RISCV_REG_S3 : riscv_reg = riscv_reg :: RISCV_REG_X19 ; } impl riscv_reg { pub const RISCV_REG_S4 : riscv_reg = riscv_reg :: RISCV_REG_X20 ; } impl riscv_reg { pub const RISCV_REG_S5 : riscv_reg = riscv_reg :: RISCV_REG_X21 ; } impl riscv_reg { pub const RISCV_REG_S6 : riscv_reg = riscv_reg :: RISCV_REG_X22 ; } impl riscv_reg { pub const RISCV_REG_S7 : riscv_reg = riscv_reg :: RISCV_REG_X23 ; } impl riscv_reg { pub const RISCV_REG_S8 : riscv_reg = riscv_reg :: RISCV_REG_X24 ; } impl riscv_reg { pub const RISCV_REG_S9 : riscv_reg = riscv_reg :: RISCV_REG_X25 ; } impl riscv_reg { pub const RISCV_REG_S10 : riscv_reg = riscv_reg :: RISCV_REG_X26 ; } impl riscv_reg { pub const RISCV_REG_S11 : riscv_reg = riscv_reg :: RISCV_REG_X27 ; } impl riscv_reg { pub const RISCV_REG_T3 : riscv_reg = riscv_reg :: RISCV_REG_X28 ; } impl riscv_reg { pub const RISCV_REG_T4 : riscv_reg = riscv_reg :: RISCV_REG_X29 ; } impl riscv_reg { pub const RISCV_REG_T5 : riscv_reg = riscv_reg :: RISCV_REG_X30 ; } impl riscv_reg { pub const RISCV_REG_T6 : riscv_reg = riscv_reg :: RISCV_REG_X31 ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_reg { RISCV_REG_INVALID = 0 , RISCV_REG_X0 = 1 , RISCV_REG_X1 = 2 , RISCV_REG_X2 = 3 , RISCV_REG_X3 = 4 , RISCV_REG_X4 = 5 , RISCV_REG_X5 = 6 , RISCV_REG_X6 = 7 , RISCV_REG_X7 = 8 , RISCV_REG_X8 = 9 , RISCV_REG_X9 = 10 , RISCV_REG_X10 = 11 , RISCV_REG_X11 = 12 , RISCV_REG_X12 = 13 , RISCV_REG_X13 = 14 , RISCV_REG_X14 = 15 , RISCV_REG_X15 = 16 , RISCV_REG_X16 = 17 , RISCV_REG_X17 = 18 , RISCV_REG_X18 = 19 , RISCV_REG_X19 = 20 , RISCV_REG_X20 = 21 , RISCV_REG_X21 = 22 , RISCV_REG_X22 = 23 , RISCV_REG_X23 = 24 , RISCV_REG_X24 = 25 , RISCV_REG_X25 = 26 , RISCV_REG_X26 = 27 , RISCV_REG_X27 = 28 , RISCV_REG_X28 = 29 , RISCV_REG_X29 = 30 , RISCV_REG_X30 = 31 , RISCV_REG_X31 = 32 , RISCV_REG_F0_32 = 33 , RISCV_REG_F0_64 = 34 , RISCV_REG_F1_32 = 35 , RISCV_REG_F1_64 = 36 , RISCV_REG_F2_32 = 37 , RISCV_REG_F2_64 = 38 , RISCV_REG_F3_32 = 39 , RISCV_REG_F3_64 = 40 , RISCV_REG_F4_32 = 41 , RISCV_REG_F4_64 = 42 , RISCV_REG_F5_32 = 43 , RISCV_REG_F5_64 = 44 , RISCV_REG_F6_32 = 45 , RISCV_REG_F6_64 = 46 , RISCV_REG_F7_32 = 47 , RISCV_REG_F7_64 = 48 , RISCV_REG_F8_32 = 49 , RISCV_REG_F8_64 = 50 , RISCV_REG_F9_32 = 51 , RISCV_REG_F9_64 = 52 , RISCV_REG_F10_32 = 53 , RISCV_REG_F10_64 = 54 , RISCV_REG_F11_32 = 55 , RISCV_REG_F11_64 = 56 , RISCV_REG_F12_32 = 57 , RISCV_REG_F12_64 = 58 , RISCV_REG_F13_32 = 59 , RISCV_REG_F13_64 = 60 , RISCV_REG_F14_32 = 61 , RISCV_REG_F14_64 = 62 , RISCV_REG_F15_32 = 63 , RISCV_REG_F15_64 = 64 , RISCV_REG_F16_32 = 65 , RISCV_REG_F16_64 = 66 , RISCV_REG_F17_32 = 67 , RISCV_REG_F17_64 = 68 , RISCV_REG_F18_32 = 69 , RISCV_REG_F18_64 = 70 , RISCV_REG_F19_32 = 71 , RISCV_REG_F19_64 = 72 , RISCV_REG_F20_32 = 73 , RISCV_REG_F20_64 = 74 , RISCV_REG_F21_32 = 75 , RISCV_REG_F21_64 = 76 , RISCV_REG_F22_32 = 77 , RISCV_REG_F22_64 = 78 , RISCV_REG_F23_32 = 79 , RISCV_REG_F23_64 = 80 , RISCV_REG_F24_32 = 81 , RISCV_REG_F24_64 = 82 , RISCV_REG_F25_32 = 83 , RISCV_REG_F25_64 = 84 , RISCV_REG_F26_32 = 85 , RISCV_REG_F26_64 = 86 , RISCV_REG_F27_32 = 87 , RISCV_REG_F27_64 = 88 , RISCV_REG_F28_32 = 89 , RISCV_REG_F28_64 = 90 , RISCV_REG_F29_32 = 91 , RISCV_REG_F29_64 = 92 , RISCV_REG_F30_32 = 93 , RISCV_REG_F30_64 = 94 , RISCV_REG_F31_32 = 95 , RISCV_REG_F31_64 = 96 , RISCV_REG_ENDING = 97 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn { RISCV_INS_INVALID = 0 , RISCV_INS_ADD = 1 , RISCV_INS_ADDI = 2 , RISCV_INS_ADDIW = 3 , RISCV_INS_ADDW = 4 , RISCV_INS_AMOADD_D = 5 , RISCV_INS_AMOADD_D_AQ = 6 , RISCV_INS_AMOADD_D_AQ_RL = 7 , RISCV_INS_AMOADD_D_RL = 8 , RISCV_INS_AMOADD_W = 9 , RISCV_INS_AMOADD_W_AQ = 10 , RISCV_INS_AMOADD_W_AQ_RL = 11 , RISCV_INS_AMOADD_W_RL = 12 , RISCV_INS_AMOAND_D = 13 , RISCV_INS_AMOAND_D_AQ = 14 , RISCV_INS_AMOAND_D_AQ_RL = 15 , RISCV_INS_AMOAND_D_RL = 16 , RISCV_INS_AMOAND_W = 17 , RISCV_INS_AMOAND_W_AQ = 18 , RISCV_INS_AMOAND_W_AQ_RL = 19 , RISCV_INS_AMOAND_W_RL = 20 , RISCV_INS_AMOMAXU_D = 21 , RISCV_INS_AMOMAXU_D_AQ = 22 , RISCV_INS_AMOMAXU_D_AQ_RL = 23 , RISCV_INS_AMOMAXU_D_RL = 24 , RISCV_INS_AMOMAXU_W = 25 , RISCV_INS_AMOMAXU_W_AQ = 26 , RISCV_INS_AMOMAXU_W_AQ_RL = 27 , RISCV_INS_AMOMAXU_W_RL = 28 , RISCV_INS_AMOMAX_D = 29 , RISCV_INS_AMOMAX_D_AQ = 30 , RISCV_INS_AMOMAX_D_AQ_RL = 31 , RISCV_INS_AMOMAX_D_RL = 32 , RISCV_INS_AMOMAX_W = 33 , RISCV_INS_AMOMAX_W_AQ = 34 , RISCV_INS_AMOMAX_W_AQ_RL = 35 , RISCV_INS_AMOMAX_W_RL = 36 , RISCV_INS_AMOMINU_D = 37 , RISCV_INS_AMOMINU_D_AQ = 38 , RISCV_INS_AMOMINU_D_AQ_RL = 39 , RISCV_INS_AMOMINU_D_RL = 40 , RISCV_INS_AMOMINU_W = 41 , RISCV_INS_AMOMINU_W_AQ = 42 , RISCV_INS_AMOMINU_W_AQ_RL = 43 , RISCV_INS_AMOMINU_W_RL = 44 , RISCV_INS_AMOMIN_D = 45 , RISCV_INS_AMOMIN_D_AQ = 46 , RISCV_INS_AMOMIN_D_AQ_RL = 47 , RISCV_INS_AMOMIN_D_RL = 48 , RISCV_INS_AMOMIN_W = 49 , RISCV_INS_AMOMIN_W_AQ = 50 , RISCV_INS_AMOMIN_W_AQ_RL = 51 , RISCV_INS_AMOMIN_W_RL = 52 , RISCV_INS_AMOOR_D = 53 , RISCV_INS_AMOOR_D_AQ = 54 , RISCV_INS_AMOOR_D_AQ_RL = 55 , RISCV_INS_AMOOR_D_RL = 56 , RISCV_INS_AMOOR_W = 57 , RISCV_INS_AMOOR_W_AQ = 58 , RISCV_INS_AMOOR_W_AQ_RL = 59 , RISCV_INS_AMOOR_W_RL = 60 , RISCV_INS_AMOSWAP_D = 61 , RISCV_INS_AMOSWAP_D_AQ = 62 , RISCV_INS_AMOSWAP_D_AQ_RL = 63 , RISCV_INS_AMOSWAP_D_RL = 64 , RISCV_INS_AMOSWAP_W = 65 , RISCV_INS_AMOSWAP_W_AQ = 66 , RISCV_INS_AMOSWAP_W_AQ_RL = 67 , RISCV_INS_AMOSWAP_W_RL = 68 , RISCV_INS_AMOXOR_D = 69 , RISCV_INS_AMOXOR_D_AQ = 70 , RISCV_INS_AMOXOR_D_AQ_RL = 71 , RISCV_INS_AMOXOR_D_RL = 72 , RISCV_INS_AMOXOR_W = 73 , RISCV_INS_AMOXOR_W_AQ = 74 , RISCV_INS_AMOXOR_W_AQ_RL = 75 , RISCV_INS_AMOXOR_W_RL = 76 , RISCV_INS_AND = 77 , RISCV_INS_ANDI = 78 , RISCV_INS_AUIPC = 79 , RISCV_INS_BEQ = 80 , RISCV_INS_BGE = 81 , RISCV_INS_BGEU = 82 , RISCV_INS_BLT = 83 , RISCV_INS_BLTU = 84 , RISCV_INS_BNE = 85 , RISCV_INS_CSRRC = 86 , RISCV_INS_CSRRCI = 87 , RISCV_INS_CSRRS = 88 , RISCV_INS_CSRRSI = 89 , RISCV_INS_CSRRW = 90 , RISCV_INS_CSRRWI = 91 , RISCV_INS_C_ADD = 92 , RISCV_INS_C_ADDI = 93 , RISCV_INS_C_ADDI16SP = 94 , RISCV_INS_C_ADDI4SPN = 95 , RISCV_INS_C_ADDIW = 96 , RISCV_INS_C_ADDW = 97 , RISCV_INS_C_AND = 98 , RISCV_INS_C_ANDI = 99 , RISCV_INS_C_BEQZ = 100 , RISCV_INS_C_BNEZ = 101 , RISCV_INS_C_EBREAK = 102 , RISCV_INS_C_FLD = 103 , RISCV_INS_C_FLDSP = 104 , RISCV_INS_C_FLW = 105 , RISCV_INS_C_FLWSP = 106 , RISCV_INS_C_FSD = 107 , RISCV_INS_C_FSDSP = 108 , RISCV_INS_C_FSW = 109 , RISCV_INS_C_FSWSP = 110 , RISCV_INS_C_J = 111 , RISCV_INS_C_JAL = 112 , RISCV_INS_C_JALR = 113 , RISCV_INS_C_JR = 114 , RISCV_INS_C_LD = 115 , RISCV_INS_C_LDSP = 116 , RISCV_INS_C_LI = 117 , RISCV_INS_C_LUI = 118 , RISCV_INS_C_LW = 119 , RISCV_INS_C_LWSP = 120 , RISCV_INS_C_MV = 121 , RISCV_INS_C_NOP = 122 , RISCV_INS_C_OR = 123 , RISCV_INS_C_SD = 124 , RISCV_INS_C_SDSP = 125 , RISCV_INS_C_SLLI = 126 , RISCV_INS_C_SRAI = 127 , RISCV_INS_C_SRLI = 128 , RISCV_INS_C_SUB = 129 , RISCV_INS_C_SUBW = 130 , RISCV_INS_C_SW = 131 , RISCV_INS_C_SWSP = 132 , RISCV_INS_C_UNIMP = 133 , RISCV_INS_C_XOR = 134 , RISCV_INS_DIV = 135 , RISCV_INS_DIVU = 136 , RISCV_INS_DIVUW = 137 , RISCV_INS_DIVW = 138 , RISCV_INS_EBREAK = 139 , RISCV_INS_ECALL = 140 , RISCV_INS_FADD_D = 141 , RISCV_INS_FADD_S = 142 , RISCV_INS_FCLASS_D = 143 , RISCV_INS_FCLASS_S = 144 , RISCV_INS_FCVT_D_L = 145 , RISCV_INS_FCVT_D_LU = 146 , RISCV_INS_FCVT_D_S = 147 , RISCV_INS_FCVT_D_W = 148 , RISCV_INS_FCVT_D_WU = 149 , RISCV_INS_FCVT_LU_D = 150 , RISCV_INS_FCVT_LU_S = 151 , RISCV_INS_FCVT_L_D = 152 , RISCV_INS_FCVT_L_S = 153 , RISCV_INS_FCVT_S_D = 154 , RISCV_INS_FCVT_S_L = 155 , RISCV_INS_FCVT_S_LU = 156 , RISCV_INS_FCVT_S_W = 157 , RISCV_INS_FCVT_S_WU = 158 , RISCV_INS_FCVT_WU_D = 159 , RISCV_INS_FCVT_WU_S = 160 , RISCV_INS_FCVT_W_D = 161 , RISCV_INS_FCVT_W_S = 162 , RISCV_INS_FDIV_D = 163 , RISCV_INS_FDIV_S = 164 , RISCV_INS_FENCE = 165 , RISCV_INS_FENCE_I = 166 , RISCV_INS_FENCE_TSO = 167 , RISCV_INS_FEQ_D = 168 , RISCV_INS_FEQ_S = 169 , RISCV_INS_FLD = 170 , RISCV_INS_FLE_D = 171 , RISCV_INS_FLE_S = 172 , RISCV_INS_FLT_D = 173 , RISCV_INS_FLT_S = 174 , RISCV_INS_FLW = 175 , RISCV_INS_FMADD_D = 176 , RISCV_INS_FMADD_S = 177 , RISCV_INS_FMAX_D = 178 , RISCV_INS_FMAX_S = 179 , RISCV_INS_FMIN_D = 180 , RISCV_INS_FMIN_S = 181 , RISCV_INS_FMSUB_D = 182 , RISCV_INS_FMSUB_S = 183 , RISCV_INS_FMUL_D = 184 , RISCV_INS_FMUL_S = 185 , RISCV_INS_FMV_D_X = 186 , RISCV_INS_FMV_W_X = 187 , RISCV_INS_FMV_X_D = 188 , RISCV_INS_FMV_X_W = 189 , RISCV_INS_FNMADD_D = 190 , RISCV_INS_FNMADD_S = 191 , RISCV_INS_FNMSUB_D = 192 , RISCV_INS_FNMSUB_S = 193 , RISCV_INS_FSD = 194 , RISCV_INS_FSGNJN_D = 195 , RISCV_INS_FSGNJN_S = 196 , RISCV_INS_FSGNJX_D = 197 , RISCV_INS_FSGNJX_S = 198 , RISCV_INS_FSGNJ_D = 199 , RISCV_INS_FSGNJ_S = 200 , RISCV_INS_FSQRT_D = 201 , RISCV_INS_FSQRT_S = 202 , RISCV_INS_FSUB_D = 203 , RISCV_INS_FSUB_S = 204 , RISCV_INS_FSW = 205 , RISCV_INS_JAL = 206 , RISCV_INS_JALR = 207 , RISCV_INS_LB = 208 , RISCV_INS_LBU = 209 , RISCV_INS_LD = 210 , RISCV_INS_LH = 211 , RISCV_INS_LHU = 212 , RISCV_INS_LR_D = 213 , RISCV_INS_LR_D_AQ = 214 , RISCV_INS_LR_D_AQ_RL = 215 , RISCV_INS_LR_D_RL = 216 , RISCV_INS_LR_W = 217 , RISCV_INS_LR_W_AQ = 218 , RISCV_INS_LR_W_AQ_RL = 219 , RISCV_INS_LR_W_RL = 220 , RISCV_INS_LUI = 221 , RISCV_INS_LW = 222 , RISCV_INS_LWU = 223 , RISCV_INS_MRET = 224 , RISCV_INS_MUL = 225 , RISCV_INS_MULH = 226 , RISCV_INS_MULHSU = 227 , RISCV_INS_MULHU = 228 , RISCV_INS_MULW = 229 , RISCV_INS_OR = 230 , RISCV_INS_ORI = 231 , RISCV_INS_REM = 232 , RISCV_INS_REMU = 233 , RISCV_INS_REMUW = 234 , RISCV_INS_REMW = 235 , RISCV_INS_SB = 236 , RISCV_INS_SC_D = 237 , RISCV_INS_SC_D_AQ = 238 , RISCV_INS_SC_D_AQ_RL = 239 , RISCV_INS_SC_D_RL = 240 , RISCV_INS_SC_W = 241 , RISCV_INS_SC_W_AQ = 242 , RISCV_INS_SC_W_AQ_RL = 243 , RISCV_INS_SC_W_RL = 244 , RISCV_INS_SD = 245 , RISCV_INS_SFENCE_VMA = 246 , RISCV_INS_SH = 247 , RISCV_INS_SLL = 248 , RISCV_INS_SLLI = 249 , RISCV_INS_SLLIW = 250 , RISCV_INS_SLLW = 251 , RISCV_INS_SLT = 252 , RISCV_INS_SLTI = 253 , RISCV_INS_SLTIU = 254 , RISCV_INS_SLTU = 255 , RISCV_INS_SRA = 256 , RISCV_INS_SRAI = 257 , RISCV_INS_SRAIW = 258 , RISCV_INS_SRAW = 259 , RISCV_INS_SRET = 260 , RISCV_INS_SRL = 261 , RISCV_INS_SRLI = 262 , RISCV_INS_SRLIW = 263 , RISCV_INS_SRLW = 264 , RISCV_INS_SUB = 265 , RISCV_INS_SUBW = 266 , RISCV_INS_SW = 267 , RISCV_INS_UNIMP = 268 , RISCV_INS_URET = 269 , RISCV_INS_WFI = 270 , RISCV_INS_XOR = 271 , RISCV_INS_XORI = 272 , RISCV_INS_ENDING = 273 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn_group { # [doc = "< = CS_GRP_INVALID"] RISCV_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] RISCV_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] RISCV_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] RISCV_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] RISCV_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] RISCV_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] RISCV_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] RISCV_GRP_BRANCH_RELATIVE = 7 , RISCV_GRP_ISRV32 = 128 , RISCV_GRP_ISRV64 = 129 , RISCV_GRP_HASSTDEXTA = 130 , RISCV_GRP_HASSTDEXTC = 131 , RISCV_GRP_HASSTDEXTD = 132 , RISCV_GRP_HASSTDEXTF = 133 , RISCV_GRP_HASSTDEXTM = 134 , RISCV_GRP_ENDING = 135 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_op_type { WASM_OP_INVALID = 0 , WASM_OP_NONE = 1 , WASM_OP_INT7 = 2 , WASM_OP_VARUINT32 = 3 , WASM_OP_VARUINT64 = 4 , WASM_OP_UINT32 = 5 , WASM_OP_UINT64 = 6 , WASM_OP_IMM = 7 , WASM_OP_BRTABLE = 8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_wasm_brtable { pub length : u32 , pub address : u64 , pub default_target : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_brtable"] [:: std :: mem :: size_of :: < cs_wasm_brtable > () - 24usize] ; ["Alignment of cs_wasm_brtable"] [:: std :: mem :: align_of :: < cs_wasm_brtable > () - 8usize] ; ["Offset of field: cs_wasm_brtable::length"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , length) - 0usize] ; ["Offset of field: cs_wasm_brtable::address"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , address) - 8usize] ; ["Offset of field: cs_wasm_brtable::default_target"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , default_target) - 16usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm_op { pub type_ : wasm_op_type , pub size : u32 , pub __bindgen_anon_1 : cs_wasm_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_wasm_op__bindgen_ty_1 { pub int7 : i8 , pub varuint32 : u32 , pub varuint64 : u64 , pub uint32 : u32 , pub uint64 : u64 , pub immediate : [u32 ; 2usize] , pub brtable : cs_wasm_brtable , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_wasm_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_wasm_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::int7"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , int7) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::immediate"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , immediate) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::brtable"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , brtable) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op"] [:: std :: mem :: size_of :: < cs_wasm_op > () - 32usize] ; ["Alignment of cs_wasm_op"] [:: std :: mem :: align_of :: < cs_wasm_op > () - 8usize] ; ["Offset of field: cs_wasm_op::type_"] [:: std :: mem :: offset_of ! (cs_wasm_op , type_) - 0usize] ; ["Offset of field: cs_wasm_op::size"] [:: std :: mem :: offset_of ! (cs_wasm_op , size) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . size , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm { pub op_count : u8 , pub operands : [cs_wasm_op ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm"] [:: std :: mem :: size_of :: < cs_wasm > () - 72usize] ; ["Alignment of cs_wasm"] [:: std :: mem :: align_of :: < cs_wasm > () - 8usize] ; ["Offset of field: cs_wasm::op_count"] [:: std :: mem :: offset_of ! (cs_wasm , op_count) - 0usize] ; ["Offset of field: cs_wasm::operands"] [:: std :: mem :: offset_of ! (cs_wasm , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " WASM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn { WASM_INS_UNREACHABLE = 0 , WASM_INS_NOP = 1 , WASM_INS_BLOCK = 2 , WASM_INS_LOOP = 3 , WASM_INS_IF = 4 , WASM_INS_ELSE = 5 , WASM_INS_END = 11 , WASM_INS_BR = 12 , WASM_INS_BR_IF = 13 , WASM_INS_BR_TABLE = 14 , WASM_INS_RETURN = 15 , WASM_INS_CALL = 16 , WASM_INS_CALL_INDIRECT = 17 , WASM_INS_DROP = 26 , WASM_INS_SELECT = 27 , WASM_INS_GET_LOCAL = 32 , WASM_INS_SET_LOCAL = 33 , WASM_INS_TEE_LOCAL = 34 , WASM_INS_GET_GLOBAL = 35 , WASM_INS_SET_GLOBAL = 36 , WASM_INS_I32_LOAD = 40 , WASM_INS_I64_LOAD = 41 , WASM_INS_F32_LOAD = 42 , WASM_INS_F64_LOAD = 43 , WASM_INS_I32_LOAD8_S = 44 , WASM_INS_I32_LOAD8_U = 45 , WASM_INS_I32_LOAD16_S = 46 , WASM_INS_I32_LOAD16_U = 47 , WASM_INS_I64_LOAD8_S = 48 , WASM_INS_I64_LOAD8_U = 49 , WASM_INS_I64_LOAD16_S = 50 , WASM_INS_I64_LOAD16_U = 51 , WASM_INS_I64_LOAD32_S = 52 , WASM_INS_I64_LOAD32_U = 53 , WASM_INS_I32_STORE = 54 , WASM_INS_I64_STORE = 55 , WASM_INS_F32_STORE = 56 , WASM_INS_F64_STORE = 57 , WASM_INS_I32_STORE8 = 58 , WASM_INS_I32_STORE16 = 59 , WASM_INS_I64_STORE8 = 60 , WASM_INS_I64_STORE16 = 61 , WASM_INS_I64_STORE32 = 62 , WASM_INS_CURRENT_MEMORY = 63 , WASM_INS_GROW_MEMORY = 64 , WASM_INS_I32_CONST = 65 , WASM_INS_I64_CONST = 66 , WASM_INS_F32_CONST = 67 , WASM_INS_F64_CONST = 68 , WASM_INS_I32_EQZ = 69 , WASM_INS_I32_EQ = 70 , WASM_INS_I32_NE = 71 , WASM_INS_I32_LT_S = 72 , WASM_INS_I32_LT_U = 73 , WASM_INS_I32_GT_S = 74 , WASM_INS_I32_GT_U = 75 , WASM_INS_I32_LE_S = 76 , WASM_INS_I32_LE_U = 77 , WASM_INS_I32_GE_S = 78 , WASM_INS_I32_GE_U = 79 , WASM_INS_I64_EQZ = 80 , WASM_INS_I64_EQ = 81 , WASM_INS_I64_NE = 82 , WASM_INS_I64_LT_S = 83 , WASM_INS_I64_LT_U = 84 , WASN_INS_I64_GT_S = 85 , WASM_INS_I64_GT_U = 86 , WASM_INS_I64_LE_S = 87 , WASM_INS_I64_LE_U = 88 , WASM_INS_I64_GE_S = 89 , WASM_INS_I64_GE_U = 90 , WASM_INS_F32_EQ = 91 , WASM_INS_F32_NE = 92 , WASM_INS_F32_LT = 93 , WASM_INS_F32_GT = 94 , WASM_INS_F32_LE = 95 , WASM_INS_F32_GE = 96 , WASM_INS_F64_EQ = 97 , WASM_INS_F64_NE = 98 , WASM_INS_F64_LT = 99 , WASM_INS_F64_GT = 100 , WASM_INS_F64_LE = 101 , WASM_INS_F64_GE = 102 , WASM_INS_I32_CLZ = 103 , WASM_INS_I32_CTZ = 104 , WASM_INS_I32_POPCNT = 105 , WASM_INS_I32_ADD = 106 , WASM_INS_I32_SUB = 107 , WASM_INS_I32_MUL = 108 , WASM_INS_I32_DIV_S = 109 , WASM_INS_I32_DIV_U = 110 , WASM_INS_I32_REM_S = 111 , WASM_INS_I32_REM_U = 112 , WASM_INS_I32_AND = 113 , WASM_INS_I32_OR = 114 , WASM_INS_I32_XOR = 115 , WASM_INS_I32_SHL = 116 , WASM_INS_I32_SHR_S = 117 , WASM_INS_I32_SHR_U = 118 , WASM_INS_I32_ROTL = 119 , WASM_INS_I32_ROTR = 120 , WASM_INS_I64_CLZ = 121 , WASM_INS_I64_CTZ = 122 , WASM_INS_I64_POPCNT = 123 , WASM_INS_I64_ADD = 124 , WASM_INS_I64_SUB = 125 , WASM_INS_I64_MUL = 126 , WASM_INS_I64_DIV_S = 127 , WASM_INS_I64_DIV_U = 128 , WASM_INS_I64_REM_S = 129 , WASM_INS_I64_REM_U = 130 , WASM_INS_I64_AND = 131 , WASM_INS_I64_OR = 132 , WASM_INS_I64_XOR = 133 , WASM_INS_I64_SHL = 134 , WASM_INS_I64_SHR_S = 135 , WASM_INS_I64_SHR_U = 136 , WASM_INS_I64_ROTL = 137 , WASM_INS_I64_ROTR = 138 , WASM_INS_F32_ABS = 139 , WASM_INS_F32_NEG = 140 , WASM_INS_F32_CEIL = 141 , WASM_INS_F32_FLOOR = 142 , WASM_INS_F32_TRUNC = 143 , WASM_INS_F32_NEAREST = 144 , WASM_INS_F32_SQRT = 145 , WASM_INS_F32_ADD = 146 , WASM_INS_F32_SUB = 147 , WASM_INS_F32_MUL = 148 , WASM_INS_F32_DIV = 149 , WASM_INS_F32_MIN = 150 , WASM_INS_F32_MAX = 151 , WASM_INS_F32_COPYSIGN = 152 , WASM_INS_F64_ABS = 153 , WASM_INS_F64_NEG = 154 , WASM_INS_F64_CEIL = 155 , WASM_INS_F64_FLOOR = 156 , WASM_INS_F64_TRUNC = 157 , WASM_INS_F64_NEAREST = 158 , WASM_INS_F64_SQRT = 159 , WASM_INS_F64_ADD = 160 , WASM_INS_F64_SUB = 161 , WASM_INS_F64_MUL = 162 , WASM_INS_F64_DIV = 163 , WASM_INS_F64_MIN = 164 , WASM_INS_F64_MAX = 165 , WASM_INS_F64_COPYSIGN = 166 , WASM_INS_I32_WARP_I64 = 167 , WASP_INS_I32_TRUNC_S_F32 = 168 , WASM_INS_I32_TRUNC_U_F32 = 169 , WASM_INS_I32_TRUNC_S_F64 = 170 , WASM_INS_I32_TRUNC_U_F64 = 171 , WASM_INS_I64_EXTEND_S_I32 = 172 , WASM_INS_I64_EXTEND_U_I32 = 173 , WASM_INS_I64_TRUNC_S_F32 = 174 , WASM_INS_I64_TRUNC_U_F32 = 175 , WASM_INS_I64_TRUNC_S_F64 = 176 , WASM_INS_I64_TRUNC_U_F64 = 177 , WASM_INS_F32_CONVERT_S_I32 = 178 , WASM_INS_F32_CONVERT_U_I32 = 179 , WASM_INS_F32_CONVERT_S_I64 = 180 , WASM_INS_F32_CONVERT_U_I64 = 181 , WASM_INS_F32_DEMOTE_F64 = 182 , WASM_INS_F64_CONVERT_S_I32 = 183 , WASM_INS_F64_CONVERT_U_I32 = 184 , WASM_INS_F64_CONVERT_S_I64 = 185 , WASM_INS_F64_CONVERT_U_I64 = 186 , WASM_INS_F64_PROMOTE_F32 = 187 , WASM_INS_I32_REINTERPRET_F32 = 188 , WASM_INS_I64_REINTERPRET_F64 = 189 , WASM_INS_F32_REINTERPRET_I32 = 190 , WASM_INS_F64_REINTERPRET_I64 = 191 , WASM_INS_INVALID = 512 , WASM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of WASM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn_group { # [doc = "< = CS_GRP_INVALID"] WASM_GRP_INVALID = 0 , WASM_GRP_NUMBERIC = 8 , WASM_GRP_PARAMETRIC = 9 , WASM_GRP_VARIABLE = 10 , WASM_GRP_MEMORY = 11 , WASM_GRP_CONTROL = 12 , # [doc = "< <-- mark the end of the list of groups"] WASM_GRP_ENDING = 13 , } # [repr (u32)] # [doc = " MOS65XX registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_reg { MOS65XX_REG_INVALID = 0 , # [doc = "< accumulator"] MOS65XX_REG_ACC = 1 , # [doc = "< X index register"] MOS65XX_REG_X = 2 , # [doc = "< Y index register"] MOS65XX_REG_Y = 3 , # [doc = "< status register"] MOS65XX_REG_P = 4 , # [doc = "< stack pointer register"] MOS65XX_REG_SP = 5 , # [doc = "< direct page register"] MOS65XX_REG_DP = 6 , # [doc = "< data bank register"] MOS65XX_REG_B = 7 , # [doc = "< program bank register"] MOS65XX_REG_K = 8 , MOS65XX_REG_ENDING = 9 , } # [repr (u32)] # [doc = " MOS65XX Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_address_mode { # [doc = "< No address mode."] MOS65XX_AM_NONE = 0 , # [doc = "< implied addressing (no addressing mode)"] MOS65XX_AM_IMP = 1 , # [doc = "< accumulator addressing"] MOS65XX_AM_ACC = 2 , # [doc = "< 8/16 Bit immediate value"] MOS65XX_AM_IMM = 3 , # [doc = "< relative addressing used by branches"] MOS65XX_AM_REL = 4 , # [doc = "< interrupt addressing"] MOS65XX_AM_INT = 5 , # [doc = "< memory block addressing"] MOS65XX_AM_BLOCK = 6 , # [doc = "< zeropage addressing"] MOS65XX_AM_ZP = 7 , # [doc = "< indexed zeropage addressing by the X index register"] MOS65XX_AM_ZP_X = 8 , # [doc = "< indexed zeropage addressing by the Y index register"] MOS65XX_AM_ZP_Y = 9 , # [doc = "< zero page address, branch relative address"] MOS65XX_AM_ZP_REL = 10 , # [doc = "< indirect zeropage addressing"] MOS65XX_AM_ZP_IND = 11 , # [doc = "< indexed zeropage indirect addressing by the X index register"] MOS65XX_AM_ZP_X_IND = 12 , # [doc = "< indirect zeropage indexed addressing by the Y index register"] MOS65XX_AM_ZP_IND_Y = 13 , # [doc = "< zeropage indirect long addressing"] MOS65XX_AM_ZP_IND_LONG = 14 , # [doc = "< zeropage indirect long addressing indexed by Y register"] MOS65XX_AM_ZP_IND_LONG_Y = 15 , # [doc = "< absolute addressing"] MOS65XX_AM_ABS = 16 , # [doc = "< indexed absolute addressing by the X index register"] MOS65XX_AM_ABS_X = 17 , # [doc = "< indexed absolute addressing by the Y index register"] MOS65XX_AM_ABS_Y = 18 , # [doc = "< absolute indirect addressing"] MOS65XX_AM_ABS_IND = 19 , # [doc = "< indexed absolute indirect addressing by the X index register"] MOS65XX_AM_ABS_X_IND = 20 , # [doc = "< absolute indirect long addressing"] MOS65XX_AM_ABS_IND_LONG = 21 , # [doc = "< absolute long address mode"] MOS65XX_AM_ABS_LONG = 22 , # [doc = "< absolute long address mode, indexed by X register"] MOS65XX_AM_ABS_LONG_X = 23 , # [doc = "< stack relative addressing"] MOS65XX_AM_SR = 24 , # [doc = "< indirect stack relative addressing indexed by the Y index register"] MOS65XX_AM_SR_IND_Y = 25 , } # [repr (u32)] # [doc = " MOS65XX instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_insn { MOS65XX_INS_INVALID = 0 , MOS65XX_INS_ADC = 1 , MOS65XX_INS_AND = 2 , MOS65XX_INS_ASL = 3 , MOS65XX_INS_BBR = 4 , MOS65XX_INS_BBS = 5 , MOS65XX_INS_BCC = 6 , MOS65XX_INS_BCS = 7 , MOS65XX_INS_BEQ = 8 , MOS65XX_INS_BIT = 9 , MOS65XX_INS_BMI = 10 , MOS65XX_INS_BNE = 11 , MOS65XX_INS_BPL = 12 , MOS65XX_INS_BRA = 13 , MOS65XX_INS_BRK = 14 , MOS65XX_INS_BRL = 15 , MOS65XX_INS_BVC = 16 , MOS65XX_INS_BVS = 17 , MOS65XX_INS_CLC = 18 , MOS65XX_INS_CLD = 19 , MOS65XX_INS_CLI = 20 , MOS65XX_INS_CLV = 21 , MOS65XX_INS_CMP = 22 , MOS65XX_INS_COP = 23 , MOS65XX_INS_CPX = 24 , MOS65XX_INS_CPY = 25 , MOS65XX_INS_DEC = 26 , MOS65XX_INS_DEX = 27 , MOS65XX_INS_DEY = 28 , MOS65XX_INS_EOR = 29 , MOS65XX_INS_INC = 30 , MOS65XX_INS_INX = 31 , MOS65XX_INS_INY = 32 , MOS65XX_INS_JML = 33 , MOS65XX_INS_JMP = 34 , MOS65XX_INS_JSL = 35 , MOS65XX_INS_JSR = 36 , MOS65XX_INS_LDA = 37 , MOS65XX_INS_LDX = 38 , MOS65XX_INS_LDY = 39 , MOS65XX_INS_LSR = 40 , MOS65XX_INS_MVN = 41 , MOS65XX_INS_MVP = 42 , MOS65XX_INS_NOP = 43 , MOS65XX_INS_ORA = 44 , MOS65XX_INS_PEA = 45 , MOS65XX_INS_PEI = 46 , MOS65XX_INS_PER = 47 , MOS65XX_INS_PHA = 48 , MOS65XX_INS_PHB = 49 , MOS65XX_INS_PHD = 50 , MOS65XX_INS_PHK = 51 , MOS65XX_INS_PHP = 52 , MOS65XX_INS_PHX = 53 , MOS65XX_INS_PHY = 54 , MOS65XX_INS_PLA = 55 , MOS65XX_INS_PLB = 56 , MOS65XX_INS_PLD = 57 , MOS65XX_INS_PLP = 58 , MOS65XX_INS_PLX = 59 , MOS65XX_INS_PLY = 60 , MOS65XX_INS_REP = 61 , MOS65XX_INS_RMB = 62 , MOS65XX_INS_ROL = 63 , MOS65XX_INS_ROR = 64 , MOS65XX_INS_RTI = 65 , MOS65XX_INS_RTL = 66 , MOS65XX_INS_RTS = 67 , MOS65XX_INS_SBC = 68 , MOS65XX_INS_SEC = 69 , MOS65XX_INS_SED = 70 , MOS65XX_INS_SEI = 71 , MOS65XX_INS_SEP = 72 , MOS65XX_INS_SMB = 73 , MOS65XX_INS_STA = 74 , MOS65XX_INS_STP = 75 , MOS65XX_INS_STX = 76 , MOS65XX_INS_STY = 77 , MOS65XX_INS_STZ = 78 , MOS65XX_INS_TAX = 79 , MOS65XX_INS_TAY = 80 , MOS65XX_INS_TCD = 81 , MOS65XX_INS_TCS = 82 , MOS65XX_INS_TDC = 83 , MOS65XX_INS_TRB = 84 , MOS65XX_INS_TSB = 85 , MOS65XX_INS_TSC = 86 , MOS65XX_INS_TSX = 87 , MOS65XX_INS_TXA = 88 , MOS65XX_INS_TXS = 89 , MOS65XX_INS_TXY = 90 , MOS65XX_INS_TYA = 91 , MOS65XX_INS_TYX = 92 , MOS65XX_INS_WAI = 93 , MOS65XX_INS_WDM = 94 , MOS65XX_INS_XBA = 95 , MOS65XX_INS_XCE = 96 , MOS65XX_INS_ENDING = 97 , } # [repr (u32)] # [doc = " Group of MOS65XX instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_group_type { # [doc = "< CS_GRP_INVALID"] MOS65XX_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MOS65XX_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MOS65XX_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MOS65XX_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MOS65XX_GRP_BRANCH_RELATIVE = 6 , MOS65XX_GRP_ENDING = 7 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MOS65XX_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MOS65XX_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MOS65XX_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MOS65XX_OP_MEM = 3 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx_op { # [doc = "< operand type"] pub type_ : mos65xx_op_type , pub __bindgen_anon_1 : cs_mos65xx_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mos65xx_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : mos65xx_reg , # [doc = "< immediate value for IMM operand"] pub imm : u16 , # [doc = "< address for MEM operand"] pub mem : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Alignment of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op"] [:: std :: mem :: size_of :: < cs_mos65xx_op > () - 8usize] ; ["Alignment of cs_mos65xx_op"] [:: std :: mem :: align_of :: < cs_mos65xx_op > () - 4usize] ; ["Offset of field: cs_mos65xx_op::type_"] [:: std :: mem :: offset_of ! (cs_mos65xx_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The MOS65XX address mode and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx { pub am : mos65xx_address_mode , pub modifies_flags : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mos65xx_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx"] [:: std :: mem :: size_of :: < cs_mos65xx > () - 32usize] ; ["Alignment of cs_mos65xx"] [:: std :: mem :: align_of :: < cs_mos65xx > () - 4usize] ; ["Offset of field: cs_mos65xx::am"] [:: std :: mem :: offset_of ! (cs_mos65xx , am) - 0usize] ; ["Offset of field: cs_mos65xx::modifies_flags"] [:: std :: mem :: offset_of ! (cs_mos65xx , modifies_flags) - 4usize] ; ["Offset of field: cs_mos65xx::op_count"] [:: std :: mem :: offset_of ! (cs_mos65xx , op_count) - 5usize] ; ["Offset of field: cs_mos65xx::operands"] [:: std :: mem :: offset_of ! (cs_mos65xx , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . am , self . modifies_flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_op_type { BPF_OP_INVALID = 0 , BPF_OP_REG = 1 , BPF_OP_IMM = 2 , BPF_OP_OFF = 3 , BPF_OP_MEM = 4 , # [doc = "< M[k] in cBPF"] BPF_OP_MMEM = 5 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] BPF_OP_MSH = 6 , # [doc = "< cBPF's extension (not eBPF)"] BPF_OP_EXT = 7 , } # [repr (u32)] # [doc = " BPF registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_reg { BPF_REG_INVALID = 0 , BPF_REG_A = 1 , BPF_REG_X = 2 , BPF_REG_R0 = 3 , BPF_REG_R1 = 4 , BPF_REG_R2 = 5 , BPF_REG_R3 = 6 , BPF_REG_R4 = 7 , BPF_REG_R5 = 8 , BPF_REG_R6 = 9 , BPF_REG_R7 = 10 , BPF_REG_R8 = 11 , BPF_REG_R9 = 12 , BPF_REG_R10 = 13 , BPF_REG_ENDING = 14 , } # [doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct bpf_op_mem { # [doc = "< base register"] pub base : bpf_reg , # [doc = "< offset value"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of bpf_op_mem"] [:: std :: mem :: size_of :: < bpf_op_mem > () - 8usize] ; ["Alignment of bpf_op_mem"] [:: std :: mem :: align_of :: < bpf_op_mem > () - 4usize] ; ["Offset of field: bpf_op_mem::base"] [:: std :: mem :: offset_of ! (bpf_op_mem , base) - 0usize] ; ["Offset of field: bpf_op_mem::disp"] [:: std :: mem :: offset_of ! (bpf_op_mem , disp) - 4usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_ext_type { BPF_EXT_INVALID = 0 , BPF_EXT_LEN = 1 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf_op { pub type_ : bpf_op_type , pub __bindgen_anon_1 : cs_bpf_op__bindgen_ty_1 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_bpf_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : u8 , # [doc = "< immediate value IMM operand"] pub imm : u64 , # [doc = "< offset value, used in jump & call"] pub off : u32 , # [doc = "< base/disp value for MEM operand"] pub mem : bpf_op_mem , # [doc = "< M[k] in cBPF"] pub mmem : u32 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] pub msh : u32 , # [doc = "< cBPF's extension (not eBPF)"] pub ext : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::off"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , off) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mmem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mmem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::msh"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , msh) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , ext) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op"] [:: std :: mem :: size_of :: < cs_bpf_op > () - 24usize] ; ["Alignment of cs_bpf_op"] [:: std :: mem :: align_of :: < cs_bpf_op > () - 8usize] ; ["Offset of field: cs_bpf_op::type_"] [:: std :: mem :: offset_of ! (cs_bpf_op , type_) - 0usize] ; ["Offset of field: cs_bpf_op::access"] [:: std :: mem :: offset_of ! (cs_bpf_op , access) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf { pub op_count : u8 , pub operands : [cs_bpf_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf"] [:: std :: mem :: size_of :: < cs_bpf > () - 104usize] ; ["Alignment of cs_bpf"] [:: std :: mem :: align_of :: < cs_bpf > () - 8usize] ; ["Offset of field: cs_bpf::op_count"] [:: std :: mem :: offset_of ! (cs_bpf , op_count) - 0usize] ; ["Offset of field: cs_bpf::operands"] [:: std :: mem :: offset_of ! (cs_bpf , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } impl bpf_insn { pub const BPF_INS_LD : bpf_insn = bpf_insn :: BPF_INS_LDW ; } impl bpf_insn { pub const BPF_INS_LDX : bpf_insn = bpf_insn :: BPF_INS_LDXW ; } impl bpf_insn { pub const BPF_INS_ST : bpf_insn = bpf_insn :: BPF_INS_STW ; } impl bpf_insn { pub const BPF_INS_STX : bpf_insn = bpf_insn :: BPF_INS_STXW ; } # [repr (u32)] # [doc = " BPF instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn { BPF_INS_INVALID = 0 , BPF_INS_ADD = 1 , BPF_INS_SUB = 2 , BPF_INS_MUL = 3 , BPF_INS_DIV = 4 , BPF_INS_OR = 5 , BPF_INS_AND = 6 , BPF_INS_LSH = 7 , BPF_INS_RSH = 8 , BPF_INS_NEG = 9 , BPF_INS_MOD = 10 , BPF_INS_XOR = 11 , # [doc = "< eBPF only"] BPF_INS_MOV = 12 , # [doc = "< eBPF only"] BPF_INS_ARSH = 13 , BPF_INS_ADD64 = 14 , BPF_INS_SUB64 = 15 , BPF_INS_MUL64 = 16 , BPF_INS_DIV64 = 17 , BPF_INS_OR64 = 18 , BPF_INS_AND64 = 19 , BPF_INS_LSH64 = 20 , BPF_INS_RSH64 = 21 , BPF_INS_NEG64 = 22 , BPF_INS_MOD64 = 23 , BPF_INS_XOR64 = 24 , BPF_INS_MOV64 = 25 , BPF_INS_ARSH64 = 26 , BPF_INS_LE16 = 27 , BPF_INS_LE32 = 28 , BPF_INS_LE64 = 29 , BPF_INS_BE16 = 30 , BPF_INS_BE32 = 31 , BPF_INS_BE64 = 32 , # [doc = "< eBPF only"] BPF_INS_LDW = 33 , BPF_INS_LDH = 34 , BPF_INS_LDB = 35 , # [doc = "< eBPF only: load 64-bit imm"] BPF_INS_LDDW = 36 , # [doc = "< eBPF only"] BPF_INS_LDXW = 37 , # [doc = "< eBPF only"] BPF_INS_LDXH = 38 , # [doc = "< eBPF only"] BPF_INS_LDXB = 39 , # [doc = "< eBPF only"] BPF_INS_LDXDW = 40 , # [doc = "< eBPF only"] BPF_INS_STW = 41 , # [doc = "< eBPF only"] BPF_INS_STH = 42 , # [doc = "< eBPF only"] BPF_INS_STB = 43 , # [doc = "< eBPF only"] BPF_INS_STDW = 44 , # [doc = "< eBPF only"] BPF_INS_STXW = 45 , # [doc = "< eBPF only"] BPF_INS_STXH = 46 , # [doc = "< eBPF only"] BPF_INS_STXB = 47 , # [doc = "< eBPF only"] BPF_INS_STXDW = 48 , # [doc = "< eBPF only"] BPF_INS_XADDW = 49 , # [doc = "< eBPF only"] BPF_INS_XADDDW = 50 , BPF_INS_JMP = 51 , BPF_INS_JEQ = 52 , BPF_INS_JGT = 53 , BPF_INS_JGE = 54 , BPF_INS_JSET = 55 , # [doc = "< eBPF only"] BPF_INS_JNE = 56 , # [doc = "< eBPF only"] BPF_INS_JSGT = 57 , # [doc = "< eBPF only"] BPF_INS_JSGE = 58 , # [doc = "< eBPF only"] BPF_INS_CALL = 59 , # [doc = "< eBPF only"] BPF_INS_CALLX = 60 , # [doc = "< eBPF only"] BPF_INS_EXIT = 61 , # [doc = "< eBPF only"] BPF_INS_JLT = 62 , # [doc = "< eBPF only"] BPF_INS_JLE = 63 , # [doc = "< eBPF only"] BPF_INS_JSLT = 64 , # [doc = "< eBPF only"] BPF_INS_JSLE = 65 , BPF_INS_RET = 66 , BPF_INS_TAX = 67 , BPF_INS_TXA = 68 , BPF_INS_ENDING = 69 , } # [repr (u32)] # [doc = " Group of BPF instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn_group { # [doc = "< = CS_GRP_INVALID"] BPF_GRP_INVALID = 0 , BPF_GRP_LOAD = 1 , BPF_GRP_STORE = 2 , BPF_GRP_ALU = 3 , BPF_GRP_JUMP = 4 , # [doc = "< eBPF only"] BPF_GRP_CALL = 5 , BPF_GRP_RETURN = 6 , # [doc = "< cBPF only"] BPF_GRP_MISC = 7 , BPF_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " SH registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_reg { SH_REG_INVALID = 0 , SH_REG_R0 = 1 , SH_REG_R1 = 2 , SH_REG_R2 = 3 , SH_REG_R3 = 4 , SH_REG_R4 = 5 , SH_REG_R5 = 6 , SH_REG_R6 = 7 , SH_REG_R7 = 8 , SH_REG_R8 = 9 , SH_REG_R9 = 10 , SH_REG_R10 = 11 , SH_REG_R11 = 12 , SH_REG_R12 = 13 , SH_REG_R13 = 14 , SH_REG_R14 = 15 , SH_REG_R15 = 16 , SH_REG_R0_BANK = 17 , SH_REG_R1_BANK = 18 , SH_REG_R2_BANK = 19 , SH_REG_R3_BANK = 20 , SH_REG_R4_BANK = 21 , SH_REG_R5_BANK = 22 , SH_REG_R6_BANK = 23 , SH_REG_R7_BANK = 24 , SH_REG_FR0 = 25 , SH_REG_FR1 = 26 , SH_REG_FR2 = 27 , SH_REG_FR3 = 28 , SH_REG_FR4 = 29 , SH_REG_FR5 = 30 , SH_REG_FR6 = 31 , SH_REG_FR7 = 32 , SH_REG_FR8 = 33 , SH_REG_FR9 = 34 , SH_REG_FR10 = 35 , SH_REG_FR11 = 36 , SH_REG_FR12 = 37 , SH_REG_FR13 = 38 , SH_REG_FR14 = 39 , SH_REG_FR15 = 40 , SH_REG_DR0 = 41 , SH_REG_DR2 = 42 , SH_REG_DR4 = 43 , SH_REG_DR6 = 44 , SH_REG_DR8 = 45 , SH_REG_DR10 = 46 , SH_REG_DR12 = 47 , SH_REG_DR14 = 48 , SH_REG_XD0 = 49 , SH_REG_XD2 = 50 , SH_REG_XD4 = 51 , SH_REG_XD6 = 52 , SH_REG_XD8 = 53 , SH_REG_XD10 = 54 , SH_REG_XD12 = 55 , SH_REG_XD14 = 56 , SH_REG_XF0 = 57 , SH_REG_XF1 = 58 , SH_REG_XF2 = 59 , SH_REG_XF3 = 60 , SH_REG_XF4 = 61 , SH_REG_XF5 = 62 , SH_REG_XF6 = 63 , SH_REG_XF7 = 64 , SH_REG_XF8 = 65 , SH_REG_XF9 = 66 , SH_REG_XF10 = 67 , SH_REG_XF11 = 68 , SH_REG_XF12 = 69 , SH_REG_XF13 = 70 , SH_REG_XF14 = 71 , SH_REG_XF15 = 72 , SH_REG_FV0 = 73 , SH_REG_FV4 = 74 , SH_REG_FV8 = 75 , SH_REG_FV12 = 76 , SH_REG_XMATRX = 77 , SH_REG_PC = 78 , SH_REG_PR = 79 , SH_REG_MACH = 80 , SH_REG_MACL = 81 , SH_REG_SR = 82 , SH_REG_GBR = 83 , SH_REG_SSR = 84 , SH_REG_SPC = 85 , SH_REG_SGR = 86 , SH_REG_DBR = 87 , SH_REG_VBR = 88 , SH_REG_TBR = 89 , SH_REG_RS = 90 , SH_REG_RE = 91 , SH_REG_MOD = 92 , SH_REG_FPUL = 93 , SH_REG_FPSCR = 94 , SH_REG_DSP_X0 = 95 , SH_REG_DSP_X1 = 96 , SH_REG_DSP_Y0 = 97 , SH_REG_DSP_Y1 = 98 , SH_REG_DSP_A0 = 99 , SH_REG_DSP_A1 = 100 , SH_REG_DSP_A0G = 101 , SH_REG_DSP_A1G = 102 , SH_REG_DSP_M0 = 103 , SH_REG_DSP_M1 = 104 , SH_REG_DSP_DSR = 105 , SH_REG_DSP_RSV0 = 106 , SH_REG_DSP_RSV1 = 107 , SH_REG_DSP_RSV2 = 108 , SH_REG_DSP_RSV3 = 109 , SH_REG_DSP_RSV4 = 110 , SH_REG_DSP_RSV5 = 111 , SH_REG_DSP_RSV6 = 112 , SH_REG_DSP_RSV7 = 113 , SH_REG_DSP_RSV8 = 114 , SH_REG_DSP_RSV9 = 115 , SH_REG_DSP_RSVA = 116 , SH_REG_DSP_RSVB = 117 , SH_REG_DSP_RSVC = 118 , SH_REG_DSP_RSVD = 119 , SH_REG_DSP_RSVE = 120 , SH_REG_DSP_RSVF = 121 , SH_REG_ENDING = 122 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SH_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SH_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SH_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SH_OP_MEM = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_mem_type { SH_OP_MEM_INVALID = 0 , # [doc = " <= Invalid"] SH_OP_MEM_REG_IND = 1 , # [doc = " <= Register indirect"] SH_OP_MEM_REG_POST = 2 , # [doc = " <= Register post increment"] SH_OP_MEM_REG_PRE = 3 , # [doc = " <= Register pre decrement"] SH_OP_MEM_REG_DISP = 4 , # [doc = " <= displacement"] SH_OP_MEM_REG_R0 = 5 , # [doc = " <= R0 indexed"] SH_OP_MEM_GBR_DISP = 6 , # [doc = " <= GBR based displacement"] SH_OP_MEM_GBR_R0 = 7 , # [doc = " <= GBR based R0 indexed"] SH_OP_MEM_PCR = 8 , # [doc = " <= PC relative"] SH_OP_MEM_TBR_DISP = 9 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_mem { pub address : sh_op_mem_type , # [doc = " <= memory address"] pub reg : sh_reg , # [doc = " <= base register"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_mem"] [:: std :: mem :: size_of :: < sh_op_mem > () - 12usize] ; ["Alignment of sh_op_mem"] [:: std :: mem :: align_of :: < sh_op_mem > () - 4usize] ; ["Offset of field: sh_op_mem::address"] [:: std :: mem :: offset_of ! (sh_op_mem , address) - 0usize] ; ["Offset of field: sh_op_mem::reg"] [:: std :: mem :: offset_of ! (sh_op_mem , reg) - 4usize] ; ["Offset of field: sh_op_mem::disp"] [:: std :: mem :: offset_of ! (sh_op_mem , disp) - 8usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn_type { SH_INS_DSP_INVALID = 0 , SH_INS_DSP_DOUBLE = 1 , SH_INS_DSP_SINGLE = 2 , SH_INS_DSP_PARALLEL = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn { SH_INS_DSP_NOP = 1 , SH_INS_DSP_MOV = 2 , SH_INS_DSP_PSHL = 3 , SH_INS_DSP_PSHA = 4 , SH_INS_DSP_PMULS = 5 , SH_INS_DSP_PCLR_PMULS = 6 , SH_INS_DSP_PSUB_PMULS = 7 , SH_INS_DSP_PADD_PMULS = 8 , SH_INS_DSP_PSUBC = 9 , SH_INS_DSP_PADDC = 10 , SH_INS_DSP_PCMP = 11 , SH_INS_DSP_PABS = 12 , SH_INS_DSP_PRND = 13 , SH_INS_DSP_PSUB = 14 , SH_INS_DSP_PSUBr = 15 , SH_INS_DSP_PADD = 16 , SH_INS_DSP_PAND = 17 , SH_INS_DSP_PXOR = 18 , SH_INS_DSP_POR = 19 , SH_INS_DSP_PDEC = 20 , SH_INS_DSP_PINC = 21 , SH_INS_DSP_PCLR = 22 , SH_INS_DSP_PDMSB = 23 , SH_INS_DSP_PNEG = 24 , SH_INS_DSP_PCOPY = 25 , SH_INS_DSP_PSTS = 26 , SH_INS_DSP_PLDS = 27 , SH_INS_DSP_PSWAP = 28 , SH_INS_DSP_PWAD = 29 , SH_INS_DSP_PWSB = 30 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_operand { SH_OP_DSP_INVALID = 0 , SH_OP_DSP_REG_PRE = 1 , SH_OP_DSP_REG_IND = 2 , SH_OP_DSP_REG_POST = 3 , SH_OP_DSP_REG_INDEX = 4 , SH_OP_DSP_REG = 5 , SH_OP_DSP_IMM = 6 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_cc { SH_DSP_CC_INVALID = 0 , SH_DSP_CC_NONE = 1 , SH_DSP_CC_DCT = 2 , SH_DSP_CC_DCF = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_dsp { pub insn : sh_dsp_insn , pub operand : [sh_dsp_operand ; 2usize] , pub r : [sh_reg ; 6usize] , pub cc : sh_dsp_cc , pub imm : u8 , pub size : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_dsp"] [:: std :: mem :: size_of :: < sh_op_dsp > () - 48usize] ; ["Alignment of sh_op_dsp"] [:: std :: mem :: align_of :: < sh_op_dsp > () - 4usize] ; ["Offset of field: sh_op_dsp::insn"] [:: std :: mem :: offset_of ! (sh_op_dsp , insn) - 0usize] ; ["Offset of field: sh_op_dsp::operand"] [:: std :: mem :: offset_of ! (sh_op_dsp , operand) - 4usize] ; ["Offset of field: sh_op_dsp::r"] [:: std :: mem :: offset_of ! (sh_op_dsp , r) - 12usize] ; ["Offset of field: sh_op_dsp::cc"] [:: std :: mem :: offset_of ! (sh_op_dsp , cc) - 36usize] ; ["Offset of field: sh_op_dsp::imm"] [:: std :: mem :: offset_of ! (sh_op_dsp , imm) - 40usize] ; ["Offset of field: sh_op_dsp::size"] [:: std :: mem :: offset_of ! (sh_op_dsp , size) - 44usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh_op { pub type_ : sh_op_type , pub __bindgen_anon_1 : cs_sh_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sh_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< register value for REG operand"] pub reg : sh_reg , # [doc = "< data when operand is targeting memory"] pub mem : sh_op_mem , # [doc = "< dsp instruction"] pub dsp : sh_op_dsp , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sh_op__bindgen_ty_1 > () - 48usize] ; ["Alignment of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sh_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::dsp"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , dsp) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op"] [:: std :: mem :: size_of :: < cs_sh_op > () - 56usize] ; ["Alignment of cs_sh_op"] [:: std :: mem :: align_of :: < cs_sh_op > () - 8usize] ; ["Offset of field: cs_sh_op::type_"] [:: std :: mem :: offset_of ! (cs_sh_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (u32)] # [doc = " SH instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn { SH_INS_INVALID = 0 , SH_INS_ADD_r = 1 , SH_INS_ADD = 2 , SH_INS_ADDC = 3 , SH_INS_ADDV = 4 , SH_INS_AND = 5 , SH_INS_BAND = 6 , SH_INS_BANDNOT = 7 , SH_INS_BCLR = 8 , SH_INS_BF = 9 , SH_INS_BF_S = 10 , SH_INS_BLD = 11 , SH_INS_BLDNOT = 12 , SH_INS_BOR = 13 , SH_INS_BORNOT = 14 , SH_INS_BRA = 15 , SH_INS_BRAF = 16 , SH_INS_BSET = 17 , SH_INS_BSR = 18 , SH_INS_BSRF = 19 , SH_INS_BST = 20 , SH_INS_BT = 21 , SH_INS_BT_S = 22 , SH_INS_BXOR = 23 , SH_INS_CLIPS = 24 , SH_INS_CLIPU = 25 , SH_INS_CLRDMXY = 26 , SH_INS_CLRMAC = 27 , SH_INS_CLRS = 28 , SH_INS_CLRT = 29 , SH_INS_CMP_EQ = 30 , SH_INS_CMP_GE = 31 , SH_INS_CMP_GT = 32 , SH_INS_CMP_HI = 33 , SH_INS_CMP_HS = 34 , SH_INS_CMP_PL = 35 , SH_INS_CMP_PZ = 36 , SH_INS_CMP_STR = 37 , SH_INS_DIV0S = 38 , SH_INS_DIV0U = 39 , SH_INS_DIV1 = 40 , SH_INS_DIVS = 41 , SH_INS_DIVU = 42 , SH_INS_DMULS_L = 43 , SH_INS_DMULU_L = 44 , SH_INS_DT = 45 , SH_INS_EXTS_B = 46 , SH_INS_EXTS_W = 47 , SH_INS_EXTU_B = 48 , SH_INS_EXTU_W = 49 , SH_INS_FABS = 50 , SH_INS_FADD = 51 , SH_INS_FCMP_EQ = 52 , SH_INS_FCMP_GT = 53 , SH_INS_FCNVDS = 54 , SH_INS_FCNVSD = 55 , SH_INS_FDIV = 56 , SH_INS_FIPR = 57 , SH_INS_FLDI0 = 58 , SH_INS_FLDI1 = 59 , SH_INS_FLDS = 60 , SH_INS_FLOAT = 61 , SH_INS_FMAC = 62 , SH_INS_FMOV = 63 , SH_INS_FMUL = 64 , SH_INS_FNEG = 65 , SH_INS_FPCHG = 66 , SH_INS_FRCHG = 67 , SH_INS_FSCA = 68 , SH_INS_FSCHG = 69 , SH_INS_FSQRT = 70 , SH_INS_FSRRA = 71 , SH_INS_FSTS = 72 , SH_INS_FSUB = 73 , SH_INS_FTRC = 74 , SH_INS_FTRV = 75 , SH_INS_ICBI = 76 , SH_INS_JMP = 77 , SH_INS_JSR = 78 , SH_INS_JSR_N = 79 , SH_INS_LDBANK = 80 , SH_INS_LDC = 81 , SH_INS_LDRC = 82 , SH_INS_LDRE = 83 , SH_INS_LDRS = 84 , SH_INS_LDS = 85 , SH_INS_LDTLB = 86 , SH_INS_MAC_L = 87 , SH_INS_MAC_W = 88 , SH_INS_MOV = 89 , SH_INS_MOVA = 90 , SH_INS_MOVCA = 91 , SH_INS_MOVCO = 92 , SH_INS_MOVI20 = 93 , SH_INS_MOVI20S = 94 , SH_INS_MOVLI = 95 , SH_INS_MOVML = 96 , SH_INS_MOVMU = 97 , SH_INS_MOVRT = 98 , SH_INS_MOVT = 99 , SH_INS_MOVU = 100 , SH_INS_MOVUA = 101 , SH_INS_MUL_L = 102 , SH_INS_MULR = 103 , SH_INS_MULS_W = 104 , SH_INS_MULU_W = 105 , SH_INS_NEG = 106 , SH_INS_NEGC = 107 , SH_INS_NOP = 108 , SH_INS_NOT = 109 , SH_INS_NOTT = 110 , SH_INS_OCBI = 111 , SH_INS_OCBP = 112 , SH_INS_OCBWB = 113 , SH_INS_OR = 114 , SH_INS_PREF = 115 , SH_INS_PREFI = 116 , SH_INS_RESBANK = 117 , SH_INS_ROTCL = 118 , SH_INS_ROTCR = 119 , SH_INS_ROTL = 120 , SH_INS_ROTR = 121 , SH_INS_RTE = 122 , SH_INS_RTS = 123 , SH_INS_RTS_N = 124 , SH_INS_RTV_N = 125 , SH_INS_SETDMX = 126 , SH_INS_SETDMY = 127 , SH_INS_SETRC = 128 , SH_INS_SETS = 129 , SH_INS_SETT = 130 , SH_INS_SHAD = 131 , SH_INS_SHAL = 132 , SH_INS_SHAR = 133 , SH_INS_SHLD = 134 , SH_INS_SHLL = 135 , SH_INS_SHLL16 = 136 , SH_INS_SHLL2 = 137 , SH_INS_SHLL8 = 138 , SH_INS_SHLR = 139 , SH_INS_SHLR16 = 140 , SH_INS_SHLR2 = 141 , SH_INS_SHLR8 = 142 , SH_INS_SLEEP = 143 , SH_INS_STBANK = 144 , SH_INS_STC = 145 , SH_INS_STS = 146 , SH_INS_SUB = 147 , SH_INS_SUBC = 148 , SH_INS_SUBV = 149 , SH_INS_SWAP_B = 150 , SH_INS_SWAP_W = 151 , SH_INS_SYNCO = 152 , SH_INS_TAS = 153 , SH_INS_TRAPA = 154 , SH_INS_TST = 155 , SH_INS_XOR = 156 , SH_INS_XTRCT = 157 , SH_INS_DSP = 158 , SH_INS_ENDING = 159 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh { pub insn : sh_insn , pub size : u8 , pub op_count : u8 , pub operands : [cs_sh_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh"] [:: std :: mem :: size_of :: < cs_sh > () - 176usize] ; ["Alignment of cs_sh"] [:: std :: mem :: align_of :: < cs_sh > () - 8usize] ; ["Offset of field: cs_sh::insn"] [:: std :: mem :: offset_of ! (cs_sh , insn) - 0usize] ; ["Offset of field: cs_sh::size"] [:: std :: mem :: offset_of ! (cs_sh , size) - 4usize] ; ["Offset of field: cs_sh::op_count"] [:: std :: mem :: offset_of ! (cs_sh , op_count) - 5usize] ; ["Offset of field: cs_sh::operands"] [:: std :: mem :: offset_of ! (cs_sh , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sh { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh {{ insn: {:?}, size: {:?}, op_count: {:?}, operands: {:?} }}" , self . insn , self . size , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Group of SH instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn_group { # [doc = "< CS_GRUP_INVALID"] SH_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SH_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] SH_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] SH_GRP_INT = 3 , # [doc = "< = CS_GRP_RET"] SH_GRP_RET = 4 , # [doc = "< = CS_GRP_IRET"] SH_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] SH_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] SH_GRP_BRANCH_RELATIVE = 7 , SH_GRP_SH1 = 8 , SH_GRP_SH2 = 9 , SH_GRP_SH2E = 10 , SH_GRP_SH2DSP = 11 , SH_GRP_SH2A = 12 , SH_GRP_SH2AFPU = 13 , SH_GRP_SH3 = 14 , SH_GRP_SH3DSP = 15 , SH_GRP_SH4 = 16 , SH_GRP_SH4A = 17 , SH_GRP_ENDING = 18 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_op_type { # [doc = "< CS_OP_INVALID (Uninitialized)."] TRICORE_OP_INVALID = 0 , # [doc = "< CS_OP_REG (Register operand)."] TRICORE_OP_REG = 1 , # [doc = "< CS_OP_IMM (Immediate operand)."] TRICORE_OP_IMM = 2 , # [doc = "< CS_OP_MEM (Memory operand)."] TRICORE_OP_MEM = 3 , } # [doc = " Instruction's operand referring to memory\n This is associated with TRICORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tricore_op_mem { # [doc = "< base register"] pub base : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tricore_op_mem"] [:: std :: mem :: size_of :: < tricore_op_mem > () - 8usize] ; ["Alignment of tricore_op_mem"] [:: std :: mem :: align_of :: < tricore_op_mem > () - 4usize] ; ["Offset of field: tricore_op_mem::base"] [:: std :: mem :: offset_of ! (tricore_op_mem , base) - 0usize] ; ["Offset of field: tricore_op_mem::disp"] [:: std :: mem :: offset_of ! (tricore_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore_op { # [doc = "< operand type"] pub type_ : tricore_op_type , pub __bindgen_anon_1 : cs_tricore_op__bindgen_ty_1 , # [doc = "< How is this operand accessed? (READ, WRITE or READ|WRITE)"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tricore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tricore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tricore_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tricore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op"] [:: std :: mem :: size_of :: < cs_tricore_op > () - 16usize] ; ["Alignment of cs_tricore_op"] [:: std :: mem :: align_of :: < cs_tricore_op > () - 4usize] ; ["Offset of field: cs_tricore_op::type_"] [:: std :: mem :: offset_of ! (cs_tricore_op , type_) - 0usize] ; ["Offset of field: cs_tricore_op::access"] [:: std :: mem :: offset_of ! (cs_tricore_op , access) - 12usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore { # [doc = "< number of operands of this instruction."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tricore_op ; 8usize] , # [doc = "< whether the flags register is updated."] pub update_flags : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore"] [:: std :: mem :: size_of :: < cs_tricore > () - 136usize] ; ["Alignment of cs_tricore"] [:: std :: mem :: align_of :: < cs_tricore > () - 4usize] ; ["Offset of field: cs_tricore::op_count"] [:: std :: mem :: offset_of ! (cs_tricore , op_count) - 0usize] ; ["Offset of field: cs_tricore::operands"] [:: std :: mem :: offset_of ! (cs_tricore , operands) - 4usize] ; ["Offset of field: cs_tricore::update_flags"] [:: std :: mem :: offset_of ! (cs_tricore , update_flags) - 132usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore {{ op_count: {:?}, operands: {:?}, update_flags: {:?} }}" , self . op_count , self . operands , self . update_flags) } } # [repr (u32)] # [doc = " TriCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_reg { TRICORE_REG_INVALID = 0 , TRICORE_REG_FCX = 1 , TRICORE_REG_PC = 2 , TRICORE_REG_PCXI = 3 , TRICORE_REG_PSW = 4 , TRICORE_REG_A0 = 5 , TRICORE_REG_A1 = 6 , TRICORE_REG_A2 = 7 , TRICORE_REG_A3 = 8 , TRICORE_REG_A4 = 9 , TRICORE_REG_A5 = 10 , TRICORE_REG_A6 = 11 , TRICORE_REG_A7 = 12 , TRICORE_REG_A8 = 13 , TRICORE_REG_A9 = 14 , TRICORE_REG_A10 = 15 , TRICORE_REG_A11 = 16 , TRICORE_REG_A12 = 17 , TRICORE_REG_A13 = 18 , TRICORE_REG_A14 = 19 , TRICORE_REG_A15 = 20 , TRICORE_REG_D0 = 21 , TRICORE_REG_D1 = 22 , TRICORE_REG_D2 = 23 , TRICORE_REG_D3 = 24 , TRICORE_REG_D4 = 25 , TRICORE_REG_D5 = 26 , TRICORE_REG_D6 = 27 , TRICORE_REG_D7 = 28 , TRICORE_REG_D8 = 29 , TRICORE_REG_D9 = 30 , TRICORE_REG_D10 = 31 , TRICORE_REG_D11 = 32 , TRICORE_REG_D12 = 33 , TRICORE_REG_D13 = 34 , TRICORE_REG_D14 = 35 , TRICORE_REG_D15 = 36 , TRICORE_REG_E0 = 37 , TRICORE_REG_E2 = 38 , TRICORE_REG_E4 = 39 , TRICORE_REG_E6 = 40 , TRICORE_REG_E8 = 41 , TRICORE_REG_E10 = 42 , TRICORE_REG_E12 = 43 , TRICORE_REG_E14 = 44 , TRICORE_REG_P0 = 45 , TRICORE_REG_P2 = 46 , TRICORE_REG_P4 = 47 , TRICORE_REG_P6 = 48 , TRICORE_REG_P8 = 49 , TRICORE_REG_P10 = 50 , TRICORE_REG_P12 = 51 , TRICORE_REG_P14 = 52 , TRICORE_REG_A0_A1 = 53 , TRICORE_REG_A2_A3 = 54 , TRICORE_REG_A4_A5 = 55 , TRICORE_REG_A6_A7 = 56 , TRICORE_REG_A8_A9 = 57 , TRICORE_REG_A10_A11 = 58 , TRICORE_REG_A12_A13 = 59 , TRICORE_REG_A14_A15 = 60 , TRICORE_REG_ENDING = 61 , } # [repr (u32)] # [doc = " TriCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn { TRICORE_INS_INVALID = 0 , TRICORE_INS_XOR_T = 1 , TRICORE_INS_ABSDIFS_B = 2 , TRICORE_INS_ABSDIFS_H = 3 , TRICORE_INS_ABSDIFS = 4 , TRICORE_INS_ABSDIF_B = 5 , TRICORE_INS_ABSDIF_H = 6 , TRICORE_INS_ABSDIF = 7 , TRICORE_INS_ABSS_B = 8 , TRICORE_INS_ABSS_H = 9 , TRICORE_INS_ABSS = 10 , TRICORE_INS_ABS_B = 11 , TRICORE_INS_ABS_H = 12 , TRICORE_INS_ABS = 13 , TRICORE_INS_ADDC = 14 , TRICORE_INS_ADDIH_A = 15 , TRICORE_INS_ADDIH = 16 , TRICORE_INS_ADDI = 17 , TRICORE_INS_ADDSC_AT = 18 , TRICORE_INS_ADDSC_A = 19 , TRICORE_INS_ADDS_BU = 20 , TRICORE_INS_ADDS_B = 21 , TRICORE_INS_ADDS_H = 22 , TRICORE_INS_ADDS_HU = 23 , TRICORE_INS_ADDS_U = 24 , TRICORE_INS_ADDS = 25 , TRICORE_INS_ADDX = 26 , TRICORE_INS_ADD_A = 27 , TRICORE_INS_ADD_B = 28 , TRICORE_INS_ADD_F = 29 , TRICORE_INS_ADD_H = 30 , TRICORE_INS_ADD = 31 , TRICORE_INS_ANDN_T = 32 , TRICORE_INS_ANDN = 33 , TRICORE_INS_AND_ANDN_T = 34 , TRICORE_INS_AND_AND_T = 35 , TRICORE_INS_AND_EQ = 36 , TRICORE_INS_AND_GE_U = 37 , TRICORE_INS_AND_GE = 38 , TRICORE_INS_AND_LT_U = 39 , TRICORE_INS_AND_LT = 40 , TRICORE_INS_AND_NE = 41 , TRICORE_INS_AND_NOR_T = 42 , TRICORE_INS_AND_OR_T = 43 , TRICORE_INS_AND_T = 44 , TRICORE_INS_AND = 45 , TRICORE_INS_BISR = 46 , TRICORE_INS_BMERGE = 47 , TRICORE_INS_BSPLIT = 48 , TRICORE_INS_CACHEA_I = 49 , TRICORE_INS_CACHEA_WI = 50 , TRICORE_INS_CACHEA_W = 51 , TRICORE_INS_CACHEI_I = 52 , TRICORE_INS_CACHEI_WI = 53 , TRICORE_INS_CACHEI_W = 54 , TRICORE_INS_CADDN_A = 55 , TRICORE_INS_CADDN = 56 , TRICORE_INS_CADD_A = 57 , TRICORE_INS_CADD = 58 , TRICORE_INS_CALLA = 59 , TRICORE_INS_CALLI = 60 , TRICORE_INS_CALL = 61 , TRICORE_INS_CLO_B = 62 , TRICORE_INS_CLO_H = 63 , TRICORE_INS_CLO = 64 , TRICORE_INS_CLS_B = 65 , TRICORE_INS_CLS_H = 66 , TRICORE_INS_CLS = 67 , TRICORE_INS_CLZ_B = 68 , TRICORE_INS_CLZ_H = 69 , TRICORE_INS_CLZ = 70 , TRICORE_INS_CMOVN = 71 , TRICORE_INS_CMOV = 72 , TRICORE_INS_CMPSWAP_W = 73 , TRICORE_INS_CMP_F = 74 , TRICORE_INS_CRC32B_W = 75 , TRICORE_INS_CRC32L_W = 76 , TRICORE_INS_CRC32_B = 77 , TRICORE_INS_CRCN = 78 , TRICORE_INS_CSUBN_A = 79 , TRICORE_INS_CSUBN = 80 , TRICORE_INS_CSUB_A = 81 , TRICORE_INS_CSUB = 82 , TRICORE_INS_DEBUG = 83 , TRICORE_INS_DEXTR = 84 , TRICORE_INS_DIFSC_A = 85 , TRICORE_INS_DISABLE = 86 , TRICORE_INS_DIV_F = 87 , TRICORE_INS_DIV_U = 88 , TRICORE_INS_DIV = 89 , TRICORE_INS_DSYNC = 90 , TRICORE_INS_DVADJ = 91 , TRICORE_INS_DVINIT_BU = 92 , TRICORE_INS_DVINIT_B = 93 , TRICORE_INS_DVINIT_HU = 94 , TRICORE_INS_DVINIT_H = 95 , TRICORE_INS_DVINIT_U = 96 , TRICORE_INS_DVINIT = 97 , TRICORE_INS_DVSTEP_U = 98 , TRICORE_INS_DVSTEP = 99 , TRICORE_INS_ENABLE = 100 , TRICORE_INS_EQANY_B = 101 , TRICORE_INS_EQANY_H = 102 , TRICORE_INS_EQZ_A = 103 , TRICORE_INS_EQ_A = 104 , TRICORE_INS_EQ_B = 105 , TRICORE_INS_EQ_H = 106 , TRICORE_INS_EQ_W = 107 , TRICORE_INS_EQ = 108 , TRICORE_INS_EXTR_U = 109 , TRICORE_INS_EXTR = 110 , TRICORE_INS_FCALLA = 111 , TRICORE_INS_FCALLI = 112 , TRICORE_INS_FCALL = 113 , TRICORE_INS_FRET = 114 , TRICORE_INS_FTOHP = 115 , TRICORE_INS_FTOIZ = 116 , TRICORE_INS_FTOI = 117 , TRICORE_INS_FTOQ31Z = 118 , TRICORE_INS_FTOQ31 = 119 , TRICORE_INS_FTOUZ = 120 , TRICORE_INS_FTOU = 121 , TRICORE_INS_GE_A = 122 , TRICORE_INS_GE_U = 123 , TRICORE_INS_GE = 124 , TRICORE_INS_HPTOF = 125 , TRICORE_INS_IMASK = 126 , TRICORE_INS_INSERT = 127 , TRICORE_INS_INSN_T = 128 , TRICORE_INS_INS_T = 129 , TRICORE_INS_ISYNC = 130 , TRICORE_INS_ITOF = 131 , TRICORE_INS_IXMAX_U = 132 , TRICORE_INS_IXMAX = 133 , TRICORE_INS_IXMIN_U = 134 , TRICORE_INS_IXMIN = 135 , TRICORE_INS_JA = 136 , TRICORE_INS_JEQ_A = 137 , TRICORE_INS_JEQ = 138 , TRICORE_INS_JGEZ = 139 , TRICORE_INS_JGE_U = 140 , TRICORE_INS_JGE = 141 , TRICORE_INS_JGTZ = 142 , TRICORE_INS_JI = 143 , TRICORE_INS_JLA = 144 , TRICORE_INS_JLEZ = 145 , TRICORE_INS_JLI = 146 , TRICORE_INS_JLTZ = 147 , TRICORE_INS_JLT_U = 148 , TRICORE_INS_JLT = 149 , TRICORE_INS_JL = 150 , TRICORE_INS_JNED = 151 , TRICORE_INS_JNEI = 152 , TRICORE_INS_JNE_A = 153 , TRICORE_INS_JNE = 154 , TRICORE_INS_JNZ_A = 155 , TRICORE_INS_JNZ_T = 156 , TRICORE_INS_JNZ = 157 , TRICORE_INS_JZ_A = 158 , TRICORE_INS_JZ_T = 159 , TRICORE_INS_JZ = 160 , TRICORE_INS_J = 161 , TRICORE_INS_LDLCX = 162 , TRICORE_INS_LDMST = 163 , TRICORE_INS_LDUCX = 164 , TRICORE_INS_LD_A = 165 , TRICORE_INS_LD_BU = 166 , TRICORE_INS_LD_B = 167 , TRICORE_INS_LD_DA = 168 , TRICORE_INS_LD_D = 169 , TRICORE_INS_LD_HU = 170 , TRICORE_INS_LD_H = 171 , TRICORE_INS_LD_Q = 172 , TRICORE_INS_LD_W = 173 , TRICORE_INS_LEA = 174 , TRICORE_INS_LHA = 175 , TRICORE_INS_LOOPU = 176 , TRICORE_INS_LOOP = 177 , TRICORE_INS_LT_A = 178 , TRICORE_INS_LT_B = 179 , TRICORE_INS_LT_BU = 180 , TRICORE_INS_LT_H = 181 , TRICORE_INS_LT_HU = 182 , TRICORE_INS_LT_U = 183 , TRICORE_INS_LT_W = 184 , TRICORE_INS_LT_WU = 185 , TRICORE_INS_LT = 186 , TRICORE_INS_MADDMS_H = 187 , TRICORE_INS_MADDMS_U = 188 , TRICORE_INS_MADDMS = 189 , TRICORE_INS_MADDM_H = 190 , TRICORE_INS_MADDM_Q = 191 , TRICORE_INS_MADDM_U = 192 , TRICORE_INS_MADDM = 193 , TRICORE_INS_MADDRS_H = 194 , TRICORE_INS_MADDRS_Q = 195 , TRICORE_INS_MADDR_H = 196 , TRICORE_INS_MADDR_Q = 197 , TRICORE_INS_MADDSUMS_H = 198 , TRICORE_INS_MADDSUM_H = 199 , TRICORE_INS_MADDSURS_H = 200 , TRICORE_INS_MADDSUR_H = 201 , TRICORE_INS_MADDSUS_H = 202 , TRICORE_INS_MADDSU_H = 203 , TRICORE_INS_MADDS_H = 204 , TRICORE_INS_MADDS_Q = 205 , TRICORE_INS_MADDS_U = 206 , TRICORE_INS_MADDS = 207 , TRICORE_INS_MADD_F = 208 , TRICORE_INS_MADD_H = 209 , TRICORE_INS_MADD_Q = 210 , TRICORE_INS_MADD_U = 211 , TRICORE_INS_MADD = 212 , TRICORE_INS_MAX_B = 213 , TRICORE_INS_MAX_BU = 214 , TRICORE_INS_MAX_H = 215 , TRICORE_INS_MAX_HU = 216 , TRICORE_INS_MAX_U = 217 , TRICORE_INS_MAX = 218 , TRICORE_INS_MFCR = 219 , TRICORE_INS_MIN_B = 220 , TRICORE_INS_MIN_BU = 221 , TRICORE_INS_MIN_H = 222 , TRICORE_INS_MIN_HU = 223 , TRICORE_INS_MIN_U = 224 , TRICORE_INS_MIN = 225 , TRICORE_INS_MOVH_A = 226 , TRICORE_INS_MOVH = 227 , TRICORE_INS_MOVZ_A = 228 , TRICORE_INS_MOV_AA = 229 , TRICORE_INS_MOV_A = 230 , TRICORE_INS_MOV_D = 231 , TRICORE_INS_MOV_U = 232 , TRICORE_INS_MOV = 233 , TRICORE_INS_MSUBADMS_H = 234 , TRICORE_INS_MSUBADM_H = 235 , TRICORE_INS_MSUBADRS_H = 236 , TRICORE_INS_MSUBADR_H = 237 , TRICORE_INS_MSUBADS_H = 238 , TRICORE_INS_MSUBAD_H = 239 , TRICORE_INS_MSUBMS_H = 240 , TRICORE_INS_MSUBMS_U = 241 , TRICORE_INS_MSUBMS = 242 , TRICORE_INS_MSUBM_H = 243 , TRICORE_INS_MSUBM_Q = 244 , TRICORE_INS_MSUBM_U = 245 , TRICORE_INS_MSUBM = 246 , TRICORE_INS_MSUBRS_H = 247 , TRICORE_INS_MSUBRS_Q = 248 , TRICORE_INS_MSUBR_H = 249 , TRICORE_INS_MSUBR_Q = 250 , TRICORE_INS_MSUBS_H = 251 , TRICORE_INS_MSUBS_Q = 252 , TRICORE_INS_MSUBS_U = 253 , TRICORE_INS_MSUBS = 254 , TRICORE_INS_MSUB_F = 255 , TRICORE_INS_MSUB_H = 256 , TRICORE_INS_MSUB_Q = 257 , TRICORE_INS_MSUB_U = 258 , TRICORE_INS_MSUB = 259 , TRICORE_INS_MTCR = 260 , TRICORE_INS_MULMS_H = 261 , TRICORE_INS_MULM_H = 262 , TRICORE_INS_MULM_U = 263 , TRICORE_INS_MULM = 264 , TRICORE_INS_MULR_H = 265 , TRICORE_INS_MULR_Q = 266 , TRICORE_INS_MULS_U = 267 , TRICORE_INS_MULS = 268 , TRICORE_INS_MUL_F = 269 , TRICORE_INS_MUL_H = 270 , TRICORE_INS_MUL_Q = 271 , TRICORE_INS_MUL_U = 272 , TRICORE_INS_MUL = 273 , TRICORE_INS_NAND_T = 274 , TRICORE_INS_NAND = 275 , TRICORE_INS_NEZ_A = 276 , TRICORE_INS_NE_A = 277 , TRICORE_INS_NE = 278 , TRICORE_INS_NOP = 279 , TRICORE_INS_NOR_T = 280 , TRICORE_INS_NOR = 281 , TRICORE_INS_NOT = 282 , TRICORE_INS_ORN_T = 283 , TRICORE_INS_ORN = 284 , TRICORE_INS_OR_ANDN_T = 285 , TRICORE_INS_OR_AND_T = 286 , TRICORE_INS_OR_EQ = 287 , TRICORE_INS_OR_GE_U = 288 , TRICORE_INS_OR_GE = 289 , TRICORE_INS_OR_LT_U = 290 , TRICORE_INS_OR_LT = 291 , TRICORE_INS_OR_NE = 292 , TRICORE_INS_OR_NOR_T = 293 , TRICORE_INS_OR_OR_T = 294 , TRICORE_INS_OR_T = 295 , TRICORE_INS_OR = 296 , TRICORE_INS_PACK = 297 , TRICORE_INS_PARITY = 298 , TRICORE_INS_POPCNT_W = 299 , TRICORE_INS_Q31TOF = 300 , TRICORE_INS_QSEED_F = 301 , TRICORE_INS_RESTORE = 302 , TRICORE_INS_RET = 303 , TRICORE_INS_RFE = 304 , TRICORE_INS_RFM = 305 , TRICORE_INS_RSLCX = 306 , TRICORE_INS_RSTV = 307 , TRICORE_INS_RSUBS_U = 308 , TRICORE_INS_RSUBS = 309 , TRICORE_INS_RSUB = 310 , TRICORE_INS_SAT_BU = 311 , TRICORE_INS_SAT_B = 312 , TRICORE_INS_SAT_HU = 313 , TRICORE_INS_SAT_H = 314 , TRICORE_INS_SELN_A = 315 , TRICORE_INS_SELN = 316 , TRICORE_INS_SEL_A = 317 , TRICORE_INS_SEL = 318 , TRICORE_INS_SHAS = 319 , TRICORE_INS_SHA_B = 320 , TRICORE_INS_SHA_H = 321 , TRICORE_INS_SHA = 322 , TRICORE_INS_SHUFFLE = 323 , TRICORE_INS_SH_ANDN_T = 324 , TRICORE_INS_SH_AND_T = 325 , TRICORE_INS_SH_B = 326 , TRICORE_INS_SH_EQ = 327 , TRICORE_INS_SH_GE_U = 328 , TRICORE_INS_SH_GE = 329 , TRICORE_INS_SH_H = 330 , TRICORE_INS_SH_LT_U = 331 , TRICORE_INS_SH_LT = 332 , TRICORE_INS_SH_NAND_T = 333 , TRICORE_INS_SH_NE = 334 , TRICORE_INS_SH_NOR_T = 335 , TRICORE_INS_SH_ORN_T = 336 , TRICORE_INS_SH_OR_T = 337 , TRICORE_INS_SH_XNOR_T = 338 , TRICORE_INS_SH_XOR_T = 339 , TRICORE_INS_SH = 340 , TRICORE_INS_STLCX = 341 , TRICORE_INS_STUCX = 342 , TRICORE_INS_ST_A = 343 , TRICORE_INS_ST_B = 344 , TRICORE_INS_ST_DA = 345 , TRICORE_INS_ST_D = 346 , TRICORE_INS_ST_H = 347 , TRICORE_INS_ST_Q = 348 , TRICORE_INS_ST_T = 349 , TRICORE_INS_ST_W = 350 , TRICORE_INS_SUBC = 351 , TRICORE_INS_SUBSC_A = 352 , TRICORE_INS_SUBS_BU = 353 , TRICORE_INS_SUBS_B = 354 , TRICORE_INS_SUBS_HU = 355 , TRICORE_INS_SUBS_H = 356 , TRICORE_INS_SUBS_U = 357 , TRICORE_INS_SUBS = 358 , TRICORE_INS_SUBX = 359 , TRICORE_INS_SUB_A = 360 , TRICORE_INS_SUB_B = 361 , TRICORE_INS_SUB_F = 362 , TRICORE_INS_SUB_H = 363 , TRICORE_INS_SUB = 364 , TRICORE_INS_SVLCX = 365 , TRICORE_INS_SWAPMSK_W = 366 , TRICORE_INS_SWAP_A = 367 , TRICORE_INS_SWAP_W = 368 , TRICORE_INS_SYSCALL = 369 , TRICORE_INS_TLBDEMAP = 370 , TRICORE_INS_TLBFLUSH_A = 371 , TRICORE_INS_TLBFLUSH_B = 372 , TRICORE_INS_TLBMAP = 373 , TRICORE_INS_TLBPROBE_A = 374 , TRICORE_INS_TLBPROBE_I = 375 , TRICORE_INS_TRAPSV = 376 , TRICORE_INS_TRAPV = 377 , TRICORE_INS_UNPACK = 378 , TRICORE_INS_UPDFL = 379 , TRICORE_INS_UTOF = 380 , TRICORE_INS_WAIT = 381 , TRICORE_INS_XNOR_T = 382 , TRICORE_INS_XNOR = 383 , TRICORE_INS_XOR_EQ = 384 , TRICORE_INS_XOR_GE_U = 385 , TRICORE_INS_XOR_GE = 386 , TRICORE_INS_XOR_LT_U = 387 , TRICORE_INS_XOR_LT = 388 , TRICORE_INS_XOR_NE = 389 , TRICORE_INS_XOR = 390 , TRICORE_INS_ENDING = 391 , } # [repr (u32)] # [doc = " Group of TriCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn_group { # [doc = "< = CS_GRP_INVALID"] TRICORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_CALL"] TRICORE_GRP_CALL = 1 , # [doc = "< = CS_GRP_JUMP"] TRICORE_GRP_JUMP = 2 , # [doc = "< mark the end of the list of groups"] TRICORE_GRP_ENDING = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_feature_t { TRICORE_FEATURE_INVALID = 0 , TRICORE_FEATURE_HasV110 = 128 , TRICORE_FEATURE_HasV120_UP = 129 , TRICORE_FEATURE_HasV130_UP = 130 , TRICORE_FEATURE_HasV161 = 131 , TRICORE_FEATURE_HasV160_UP = 132 , TRICORE_FEATURE_HasV131_UP = 133 , TRICORE_FEATURE_HasV161_UP = 134 , TRICORE_FEATURE_HasV162 = 135 , TRICORE_FEATURE_HasV162_UP = 136 , # [doc = "< mark the end of the list of features"] TRICORE_FEATURE_ENDING = 137 , } pub use self :: tricore_feature_t as tricore_feature ; # [doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_detail { pub regs_read : [u16 ; 20usize] , # [doc = "< number of implicit registers read by this insn"] pub regs_read_count : u8 , pub regs_write : [u16 ; 20usize] , # [doc = "< number of implicit registers modified by this insn"] pub regs_write_count : u8 , # [doc = "< list of group this instruction belong to"] pub groups : [u8 ; 8usize] , # [doc = "< number of groups this insn belongs to"] pub groups_count : u8 , # [doc = "< Instruction has writeback operands."] pub writeback : bool , pub __bindgen_anon_1 : cs_detail__bindgen_ty_1 , } # [doc = " Architecture-specific instruction info"] # [repr (C)] # [derive (Copy , Clone)] pub union cs_detail__bindgen_ty_1 { # [doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"] pub x86 : cs_x86 , # [doc = "< ARM64 architecture (aka AArch64)"] pub arm64 : cs_arm64 , # [doc = "< ARM architecture (including Thumb/Thumb2)"] pub arm : cs_arm , # [doc = "< M68K architecture"] pub m68k : cs_m68k , # [doc = "< MIPS architecture"] pub mips : cs_mips , # [doc = "< PowerPC architecture"] pub ppc : cs_ppc , # [doc = "< Sparc architecture"] pub sparc : cs_sparc , # [doc = "< SystemZ architecture"] pub sysz : cs_sysz , # [doc = "< XCore architecture"] pub xcore : cs_xcore , # [doc = "< TMS320C64x architecture"] pub tms320c64x : cs_tms320c64x , # [doc = "< M680X architecture"] pub m680x : cs_m680x , # [doc = "< Ethereum architecture"] pub evm : cs_evm , # [doc = "< MOS65XX architecture (including MOS6502)"] pub mos65xx : cs_mos65xx , # [doc = "< Web Assembly architecture"] pub wasm : cs_wasm , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] pub bpf : cs_bpf , # [doc = "< RISCV architecture"] pub riscv : cs_riscv , # [doc = "< SH architecture"] pub sh : cs_sh , # [doc = "< TriCore architecture"] pub tricore : cs_tricore , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_detail__bindgen_ty_1 > () - 1768usize] ; ["Alignment of cs_detail__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_detail__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_detail__bindgen_ty_1::x86"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , x86) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm64"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm64) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m68k"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m68k) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mips"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mips) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::ppc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , ppc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sparc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sparc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sysz"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sysz) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::xcore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , xcore) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tms320c64x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tms320c64x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m680x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m680x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::evm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , evm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mos65xx"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mos65xx) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::wasm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , wasm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::bpf"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , bpf) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::riscv"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , riscv) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sh"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sh) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tricore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tricore) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_detail__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail"] [:: std :: mem :: size_of :: < cs_detail > () - 1864usize] ; ["Alignment of cs_detail"] [:: std :: mem :: align_of :: < cs_detail > () - 8usize] ; ["Offset of field: cs_detail::regs_read"] [:: std :: mem :: offset_of ! (cs_detail , regs_read) - 0usize] ; ["Offset of field: cs_detail::regs_read_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_read_count) - 40usize] ; ["Offset of field: cs_detail::regs_write"] [:: std :: mem :: offset_of ! (cs_detail , regs_write) - 42usize] ; ["Offset of field: cs_detail::regs_write_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_write_count) - 82usize] ; ["Offset of field: cs_detail::groups"] [:: std :: mem :: offset_of ! (cs_detail , groups) - 83usize] ; ["Offset of field: cs_detail::groups_count"] [:: std :: mem :: offset_of ! (cs_detail , groups_count) - 91usize] ; ["Offset of field: cs_detail::writeback"] [:: std :: mem :: offset_of ! (cs_detail , writeback) - 92usize] ; } ; impl :: std :: fmt :: Debug for cs_detail { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, writeback: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . writeback , self . __bindgen_anon_1) } } # [doc = " Detail information of disassembled instruction"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_insn { # [doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub address : u64 , # [doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub size : u16 , # [doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub bytes : [u8 ; 24usize] , # [doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub mnemonic : [:: std :: os :: raw :: c_char ; 32usize] , # [doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub op_str : [:: std :: os :: raw :: c_char ; 160usize] , # [doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."] pub detail : * mut cs_detail , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_insn"] [:: std :: mem :: size_of :: < cs_insn > () - 248usize] ; ["Alignment of cs_insn"] [:: std :: mem :: align_of :: < cs_insn > () - 8usize] ; ["Offset of field: cs_insn::id"] [:: std :: mem :: offset_of ! (cs_insn , id) - 0usize] ; ["Offset of field: cs_insn::address"] [:: std :: mem :: offset_of ! (cs_insn , address) - 8usize] ; ["Offset of field: cs_insn::size"] [:: std :: mem :: offset_of ! (cs_insn , size) - 16usize] ; ["Offset of field: cs_insn::bytes"] [:: std :: mem :: offset_of ! (cs_insn , bytes) - 18usize] ; ["Offset of field: cs_insn::mnemonic"] [:: std :: mem :: offset_of ! (cs_insn , mnemonic) - 42usize] ; ["Offset of field: cs_insn::op_str"] [:: std :: mem :: offset_of ! (cs_insn , op_str) - 74usize] ; ["Offset of field: cs_insn::detail"] [:: std :: mem :: offset_of ! (cs_insn , detail) - 240usize] ; } ; # [repr (u32)] # [doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_err { # [doc = "< No error: everything was fine"] CS_ERR_OK = 0 , # [doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"] CS_ERR_MEM = 1 , # [doc = "< Unsupported architecture: cs_open()"] CS_ERR_ARCH = 2 , # [doc = "< Invalid handle: cs_op_count(), cs_op_index()"] CS_ERR_HANDLE = 3 , # [doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"] CS_ERR_CSH = 4 , # [doc = "< Invalid/unsupported mode: cs_open()"] CS_ERR_MODE = 5 , # [doc = "< Invalid/unsupported option: cs_option()"] CS_ERR_OPTION = 6 , # [doc = "< Information is unavailable because detail option is OFF"] CS_ERR_DETAIL = 7 , # [doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"] CS_ERR_MEMSETUP = 8 , # [doc = "< Unsupported version (bindings)"] CS_ERR_VERSION = 9 , # [doc = "< Access irrelevant data in \"diet\" engine"] CS_ERR_DIET = 10 , # [doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"] CS_ERR_SKIPDATA = 11 , # [doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_ATT = 12 , # [doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_INTEL = 13 , # [doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_MASM = 14 , } unsafe extern "C" { # [doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."] pub fn cs_version (major : * mut :: std :: os :: raw :: c_int , minor : * mut :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_uint ; } unsafe extern "C" { # [doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."] pub fn cs_support (query : :: std :: os :: raw :: c_int) -> bool ; } unsafe extern "C" { # [doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_open (arch : cs_arch , mode : cs_mode , handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_close (handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"] pub fn cs_option (handle : csh , type_ : cs_opt_type , value : usize) -> cs_err ; } unsafe extern "C" { # [doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"] pub fn cs_errno (handle : csh) -> cs_err ; } unsafe extern "C" { # [doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"] pub fn cs_strerror (code : cs_err) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm (handle : csh , code : * const u8 , code_size : usize , address : u64 , count : usize , insn : * mut * mut cs_insn) -> usize ; } unsafe extern "C" { # [doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."] pub fn cs_free (insn : * mut cs_insn , count : usize) ; } unsafe extern "C" { # [doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"] pub fn cs_malloc (handle : csh) -> * mut cs_insn ; } unsafe extern "C" { # [doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm_iter (handle : csh , code : * mut * const u8 , size : * mut usize , address : * mut u64 , insn : * mut cs_insn) -> bool ; } unsafe extern "C" { # [doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."] pub fn cs_reg_name (handle : csh , reg_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."] pub fn cs_insn_name (handle : csh , insn_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."] pub fn cs_group_name (handle : csh , group_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."] pub fn cs_insn_group (handle : csh , insn : * const cs_insn , group_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."] pub fn cs_reg_read (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."] pub fn cs_reg_write (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."] pub fn cs_op_count (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."] pub fn cs_op_index (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint , position : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } # [doc = " Type of array to keep the list of registers"] pub type cs_regs = [u16 ; 64usize] ; unsafe extern "C" { # [doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_regs_access (handle : csh , insn : * const cs_insn , regs_read : * mut u16 , regs_read_count : * mut u8 , regs_write : * mut u16 , regs_write_count : * mut u8) -> cs_err ; } pub type __builtin_va_list = [__va_list_tag ; 1usize] ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __va_list_tag { pub gp_offset : :: std :: os :: raw :: c_uint , pub fp_offset : :: std :: os :: raw :: c_uint , pub overflow_arg_area : * mut :: std :: os :: raw :: c_void , pub reg_save_area : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __va_list_tag"] [:: std :: mem :: size_of :: < __va_list_tag > () - 24usize] ; ["Alignment of __va_list_tag"] [:: std :: mem :: align_of :: < __va_list_tag > () - 8usize] ; ["Offset of field: __va_list_tag::gp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , gp_offset) - 0usize] ; ["Offset of field: __va_list_tag::fp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , fp_offset) - 4usize] ; ["Offset of field: __va_list_tag::overflow_arg_area"] [:: std :: mem :: offset_of ! (__va_list_tag , overflow_arg_area) - 8usize] ; ["Offset of field: __va_list_tag::reg_save_area"] [:: std :: mem :: offset_of ! (__va_list_tag , reg_save_area) - 16usize] ; } ;
[INFO] [stdout] 3 + # [repr (C)] # [derive (Copy , Clone , Debug , Default , Eq , Hash , Ord , PartialEq , PartialOrd)] pub struct __BindgenBitfieldUnit < Storage > { storage : Storage , } impl < Storage > __BindgenBitfieldUnit < Storage > { # [inline] pub const fn new (storage : Storage) -> Self { Self { storage } } } impl < Storage > __BindgenBitfieldUnit < Storage > where Storage : AsRef < [u8] > + AsMut < [u8] >, { # [inline] fn extract_bit (byte : u8 , index : usize) -> bool { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; byte & mask == mask } # [inline] pub fn get_bit (& self , index : usize) -> bool { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = self . storage . as_ref () [byte_index] ; Self :: extract_bit (byte , index) } # [inline] pub unsafe fn raw_get_bit (this : * const Self , index : usize) -> bool { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { * (core :: ptr :: addr_of ! ((* this) . storage) as * const u8) . offset (byte_index as isize) } ; Self :: extract_bit (byte , index) } # [inline] fn change_bit (byte : u8 , index : usize , val : bool) -> u8 { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; if val { byte | mask } else { byte & ! mask } } # [inline] pub fn set_bit (& mut self , index : usize , val : bool) { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = & mut self . storage . as_mut () [byte_index] ; * byte = Self :: change_bit (* byte , index , val) ; } # [inline] pub unsafe fn raw_set_bit (this : * mut Self , index : usize , val : bool) { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { (core :: ptr :: addr_of_mut ! ((* this) . storage) as * mut u8) . offset (byte_index as isize) } ; unsafe { * byte = Self :: change_bit (* byte , index , val) } ; } # [inline] pub fn get (& self , bit_offset : usize , bit_width : u8) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if self . get_bit (i + bit_offset) { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub unsafe fn raw_get (this : * const Self , bit_offset : usize , bit_width : u8 ,) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if unsafe { Self :: raw_get_bit (this , i + bit_offset) } { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub fn set (& mut self , bit_offset : usize , bit_width : u8 , val : u64) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; self . set_bit (index + bit_offset , val_bit_is_set) ; } } # [inline] pub unsafe fn raw_set (this : * mut Self , bit_offset : usize , bit_width : u8 , val : u64 ,) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; unsafe { Self :: raw_set_bit (this , index + bit_offset , val_bit_is_set) } ; } } } # [derive (PartialEq , Copy , Clone , Hash , Debug , Default)] # [repr (C)] pub struct __BindgenComplex < T > { pub re : T , pub im : T } pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __GLIBC_USE_ISOC2Y : u32 = 0 ; pub const __GLIBC_USE_ISOC23 : u32 = 0 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 202405 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_XOPEN2K24 : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const __TIMESIZE : u32 = 64 ; pub const __USE_TIME_BITS64 : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_GETS : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_SCANF : u32 = 0 ; pub const __GLIBC_USE_C23_STRTOL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_60559_BFP__ : u32 = 201404 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_IEC_60559_COMPLEX__ : u32 = 201404 ; pub const __STDC_ISO_10646__ : u32 = 201706 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 43 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __glibc_c99_flexarr_available : u32 = 1 ; pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI : u32 = 0 ; pub const __HAVE_GENERIC_SELECTION : u32 = 1 ; pub const __GLIBC_USE_LIB_EXT2 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_TYPES_EXT : u32 = 0 ; pub const _STDLIB_H : u32 = 1 ; pub const WNOHANG : u32 = 1 ; pub const WUNTRACED : u32 = 2 ; pub const WSTOPPED : u32 = 2 ; pub const WEXITED : u32 = 4 ; pub const WCONTINUED : u32 = 8 ; pub const WNOWAIT : u32 = 16777216 ; pub const __WNOTHREAD : u32 = 536870912 ; pub const __WALL : u32 = 1073741824 ; pub const __WCLONE : u32 = 2147483648 ; pub const __W_CONTINUED : u32 = 65535 ; pub const __WCOREFLAG : u32 = 128 ; pub const __HAVE_FLOAT128 : u32 = 1 ; pub const __HAVE_DISTINCT_FLOAT128 : u32 = 1 ; pub const __HAVE_FLOAT64X : u32 = 1 ; pub const __HAVE_FLOAT64X_LONG_DOUBLE : u32 = 1 ; pub const __HAVE_FLOAT16 : u32 = 0 ; pub const __HAVE_FLOAT32 : u32 = 1 ; pub const __HAVE_FLOAT64 : u32 = 1 ; pub const __HAVE_FLOAT32X : u32 = 1 ; pub const __HAVE_FLOAT128X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT16 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT128X : u32 = 0 ; pub const __HAVE_FLOATN_NOT_TYPEDEF : u32 = 0 ; pub const __ldiv_t_defined : u32 = 1 ; pub const __lldiv_t_defined : u32 = 1 ; pub const RAND_MAX : u32 = 2147483647 ; pub const EXIT_FAILURE : u32 = 1 ; pub const EXIT_SUCCESS : u32 = 0 ; pub const _SYS_TYPES_H : u32 = 1 ; pub const _BITS_TYPES_H : u32 = 1 ; pub const _BITS_TYPESIZES_H : u32 = 1 ; pub const __OFF_T_MATCHES_OFF64_T : u32 = 1 ; pub const __INO_T_MATCHES_INO64_T : u32 = 1 ; pub const __RLIM_T_MATCHES_RLIM64_T : u32 = 1 ; pub const __STATFS_MATCHES_STATFS64 : u32 = 1 ; pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 : u32 = 1 ; pub const __FD_SETSIZE : u32 = 1024 ; pub const _BITS_TIME64_H : u32 = 1 ; pub const __clock_t_defined : u32 = 1 ; pub const __clockid_t_defined : u32 = 1 ; pub const __time_t_defined : u32 = 1 ; pub const __timer_t_defined : u32 = 1 ; pub const _BITS_STDINT_INTN_H : u32 = 1 ; pub const __BIT_TYPES_DEFINED__ : u32 = 1 ; pub const _ENDIAN_H : u32 = 1 ; pub const _BITS_ENDIAN_H : u32 = 1 ; pub const __LITTLE_ENDIAN : u32 = 1234 ; pub const __BIG_ENDIAN : u32 = 4321 ; pub const __PDP_ENDIAN : u32 = 3412 ; pub const _BITS_ENDIANNESS_H : u32 = 1 ; pub const __BYTE_ORDER : u32 = 1234 ; pub const __FLOAT_WORD_ORDER : u32 = 1234 ; pub const LITTLE_ENDIAN : u32 = 1234 ; pub const BIG_ENDIAN : u32 = 4321 ; pub const PDP_ENDIAN : u32 = 3412 ; pub const BYTE_ORDER : u32 = 1234 ; pub const _BITS_BYTESWAP_H : u32 = 1 ; pub const _BITS_UINTN_IDENTITY_H : u32 = 1 ; pub const _SYS_SELECT_H : u32 = 1 ; pub const __sigset_t_defined : u32 = 1 ; pub const __timeval_defined : u32 = 1 ; pub const _STRUCT_TIMESPEC : u32 = 1 ; pub const FD_SETSIZE : u32 = 1024 ; pub const _BITS_PTHREADTYPES_COMMON_H : u32 = 1 ; pub const _THREAD_SHARED_TYPES_H : u32 = 1 ; pub const _BITS_PTHREADTYPES_ARCH_H : u32 = 1 ; pub const __SIZEOF_PTHREAD_MUTEX_T : u32 = 40 ; pub const __SIZEOF_PTHREAD_ATTR_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_RWLOCK_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_BARRIER_T : u32 = 32 ; pub const __SIZEOF_PTHREAD_MUTEXATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_COND_T : u32 = 48 ; pub const __SIZEOF_PTHREAD_CONDATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_RWLOCKATTR_T : u32 = 8 ; pub const __SIZEOF_PTHREAD_BARRIERATTR_T : u32 = 4 ; pub const _THREAD_MUTEX_INTERNAL_H : u32 = 1 ; pub const __PTHREAD_MUTEX_HAVE_PREV : u32 = 1 ; pub const __have_pthread_attr_t : u32 = 1 ; pub const _ALLOCA_H : u32 = 1 ; pub const _STDIO_H : u32 = 1 ; pub const _____fpos_t_defined : u32 = 1 ; pub const ____mbstate_t_defined : u32 = 1 ; pub const _____fpos64_t_defined : u32 = 1 ; pub const ____FILE_defined : u32 = 1 ; pub const __FILE_defined : u32 = 1 ; pub const __struct_FILE_defined : u32 = 1 ; pub const _IO_EOF_SEEN : u32 = 16 ; pub const _IO_ERR_SEEN : u32 = 32 ; pub const _IO_USER_LOCK : u32 = 32768 ; pub const __cookie_io_functions_t_defined : u32 = 1 ; pub const _IOFBF : u32 = 0 ; pub const _IOLBF : u32 = 1 ; pub const _IONBF : u32 = 2 ; pub const BUFSIZ : u32 = 8192 ; pub const EOF : i32 = - 1 ; pub const SEEK_SET : u32 = 0 ; pub const SEEK_CUR : u32 = 1 ; pub const SEEK_END : u32 = 2 ; pub const P_tmpdir : & [u8 ; 5] = b"/tmp\0" ; pub const L_tmpnam : u32 = 20 ; pub const TMP_MAX : u32 = 238328 ; pub const _BITS_STDIO_LIM_H : u32 = 1 ; pub const FILENAME_MAX : u32 = 4096 ; pub const L_ctermid : u32 = 9 ; pub const FOPEN_MAX : u32 = 16 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const _INTTYPES_H : u32 = 1 ; pub const _STDINT_H : u32 = 1 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const _BITS_STDINT_UINTN_H : u32 = 1 ; pub const _BITS_STDINT_LEAST_H : u32 = 1 ; pub const INT8_MIN : i32 = - 128 ; pub const INT16_MIN : i32 = - 32768 ; pub const INT32_MIN : i32 = - 2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = - 128 ; pub const INT_LEAST16_MIN : i32 = - 32768 ; pub const INT_LEAST32_MIN : i32 = - 2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = - 128 ; pub const INT_FAST16_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST32_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = - 1 ; pub const UINT_FAST32_MAX : i32 = - 1 ; pub const INTPTR_MIN : i64 = - 9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = - 1 ; pub const PTRDIFF_MIN : i64 = - 9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = - 2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = - 1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const ____gwchar_t_defined : u32 = 1 ; pub const __PRI64_PREFIX : & [u8 ; 2] = b"l\0" ; pub const __PRIPTR_PREFIX : & [u8 ; 2] = b"l\0" ; pub const PRId8 : & [u8 ; 4] = b"hhd\0" ; pub const PRId16 : & [u8 ; 3] = b"hd\0" ; pub const PRId32 : & [u8 ; 2] = b"d\0" ; pub const PRId64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const PRIdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const PRIdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIi8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIi16 : & [u8 ; 3] = b"hi\0" ; pub const PRIi32 : & [u8 ; 2] = b"i\0" ; pub const PRIi64 : & [u8 ; 3] = b"li\0" ; pub const PRIiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const PRIiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const PRIiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiFAST16 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST32 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIo8 : & [u8 ; 4] = b"hho\0" ; pub const PRIo16 : & [u8 ; 3] = b"ho\0" ; pub const PRIo32 : & [u8 ; 2] = b"o\0" ; pub const PRIo64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const PRIoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const PRIoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIu8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIu16 : & [u8 ; 3] = b"hu\0" ; pub const PRIu32 : & [u8 ; 2] = b"u\0" ; pub const PRIu64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const PRIuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const PRIuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIx8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIx16 : & [u8 ; 3] = b"hx\0" ; pub const PRIx32 : & [u8 ; 2] = b"x\0" ; pub const PRIx64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const PRIxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const PRIxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIX8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIX16 : & [u8 ; 3] = b"hX\0" ; pub const PRIX32 : & [u8 ; 2] = b"X\0" ; pub const PRIX64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXLEAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXLEAST16 : & [u8 ; 3] = b"hX\0" ; pub const PRIXLEAST32 : & [u8 ; 2] = b"X\0" ; pub const PRIXLEAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXFAST16 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST32 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIdMAX : & [u8 ; 3] = b"ld\0" ; pub const PRIiMAX : & [u8 ; 3] = b"li\0" ; pub const PRIoMAX : & [u8 ; 3] = b"lo\0" ; pub const PRIuMAX : & [u8 ; 3] = b"lu\0" ; pub const PRIxMAX : & [u8 ; 3] = b"lx\0" ; pub const PRIXMAX : & [u8 ; 3] = b"lX\0" ; pub const PRIdPTR : & [u8 ; 3] = b"ld\0" ; pub const PRIiPTR : & [u8 ; 3] = b"li\0" ; pub const PRIoPTR : & [u8 ; 3] = b"lo\0" ; pub const PRIuPTR : & [u8 ; 3] = b"lu\0" ; pub const PRIxPTR : & [u8 ; 3] = b"lx\0" ; pub const PRIXPTR : & [u8 ; 3] = b"lX\0" ; pub const SCNd8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNd16 : & [u8 ; 3] = b"hd\0" ; pub const SCNd32 : & [u8 ; 2] = b"d\0" ; pub const SCNd64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const SCNdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const SCNdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNi8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNi16 : & [u8 ; 3] = b"hi\0" ; pub const SCNi32 : & [u8 ; 2] = b"i\0" ; pub const SCNi64 : & [u8 ; 3] = b"li\0" ; pub const SCNiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const SCNiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const SCNiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiFAST16 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST32 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNu8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNu16 : & [u8 ; 3] = b"hu\0" ; pub const SCNu32 : & [u8 ; 2] = b"u\0" ; pub const SCNu64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const SCNuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const SCNuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNo8 : & [u8 ; 4] = b"hho\0" ; pub const SCNo16 : & [u8 ; 3] = b"ho\0" ; pub const SCNo32 : & [u8 ; 2] = b"o\0" ; pub const SCNo64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const SCNoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const SCNoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNx8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNx16 : & [u8 ; 3] = b"hx\0" ; pub const SCNx32 : & [u8 ; 2] = b"x\0" ; pub const SCNx64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const SCNxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const SCNxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNdMAX : & [u8 ; 3] = b"ld\0" ; pub const SCNiMAX : & [u8 ; 3] = b"li\0" ; pub const SCNoMAX : & [u8 ; 3] = b"lo\0" ; pub const SCNuMAX : & [u8 ; 3] = b"lu\0" ; pub const SCNxMAX : & [u8 ; 3] = b"lx\0" ; pub const SCNdPTR : & [u8 ; 3] = b"ld\0" ; pub const SCNiPTR : & [u8 ; 3] = b"li\0" ; pub const SCNoPTR : & [u8 ; 3] = b"lo\0" ; pub const SCNuPTR : & [u8 ; 3] = b"lu\0" ; pub const SCNxPTR : & [u8 ; 3] = b"lx\0" ; pub const CS_API_MAJOR : u32 = 5 ; pub const CS_API_MINOR : u32 = 0 ; pub const CS_NEXT_VERSION : u32 = 5 ; pub const CS_VERSION_MAJOR : u32 = 5 ; pub const CS_VERSION_MINOR : u32 = 0 ; pub const CS_VERSION_EXTRA : u32 = 7 ; pub const CS_MNEMONIC_SIZE : u32 = 32 ; pub const M68K_OPERAND_COUNT : u32 = 4 ; pub const X86_EFLAGS_MODIFY_AF : u32 = 1 ; pub const X86_EFLAGS_MODIFY_CF : u32 = 2 ; pub const X86_EFLAGS_MODIFY_SF : u32 = 4 ; pub const X86_EFLAGS_MODIFY_ZF : u32 = 8 ; pub const X86_EFLAGS_MODIFY_PF : u32 = 16 ; pub const X86_EFLAGS_MODIFY_OF : u32 = 32 ; pub const X86_EFLAGS_MODIFY_TF : u32 = 64 ; pub const X86_EFLAGS_MODIFY_IF : u32 = 128 ; pub const X86_EFLAGS_MODIFY_DF : u32 = 256 ; pub const X86_EFLAGS_MODIFY_NT : u32 = 512 ; pub const X86_EFLAGS_MODIFY_RF : u32 = 1024 ; pub const X86_EFLAGS_PRIOR_OF : u32 = 2048 ; pub const X86_EFLAGS_PRIOR_SF : u32 = 4096 ; pub const X86_EFLAGS_PRIOR_ZF : u32 = 8192 ; pub const X86_EFLAGS_PRIOR_AF : u32 = 16384 ; pub const X86_EFLAGS_PRIOR_PF : u32 = 32768 ; pub const X86_EFLAGS_PRIOR_CF : u32 = 65536 ; pub const X86_EFLAGS_PRIOR_TF : u32 = 131072 ; pub const X86_EFLAGS_PRIOR_IF : u32 = 262144 ; pub const X86_EFLAGS_PRIOR_DF : u32 = 524288 ; pub const X86_EFLAGS_PRIOR_NT : u32 = 1048576 ; pub const X86_EFLAGS_RESET_OF : u32 = 2097152 ; pub const X86_EFLAGS_RESET_CF : u32 = 4194304 ; pub const X86_EFLAGS_RESET_DF : u32 = 8388608 ; pub const X86_EFLAGS_RESET_IF : u32 = 16777216 ; pub const X86_EFLAGS_RESET_SF : u32 = 33554432 ; pub const X86_EFLAGS_RESET_AF : u32 = 67108864 ; pub const X86_EFLAGS_RESET_TF : u32 = 134217728 ; pub const X86_EFLAGS_RESET_NT : u32 = 268435456 ; pub const X86_EFLAGS_RESET_PF : u32 = 536870912 ; pub const X86_EFLAGS_SET_CF : u32 = 1073741824 ; pub const X86_EFLAGS_SET_DF : u32 = 2147483648 ; pub const X86_EFLAGS_SET_IF : u64 = 4294967296 ; pub const X86_EFLAGS_TEST_OF : u64 = 8589934592 ; pub const X86_EFLAGS_TEST_SF : u64 = 17179869184 ; pub const X86_EFLAGS_TEST_ZF : u64 = 34359738368 ; pub const X86_EFLAGS_TEST_PF : u64 = 68719476736 ; pub const X86_EFLAGS_TEST_CF : u64 = 137438953472 ; pub const X86_EFLAGS_TEST_NT : u64 = 274877906944 ; pub const X86_EFLAGS_TEST_DF : u64 = 549755813888 ; pub const X86_EFLAGS_UNDEFINED_OF : u64 = 1099511627776 ; pub const X86_EFLAGS_UNDEFINED_SF : u64 = 2199023255552 ; pub const X86_EFLAGS_UNDEFINED_ZF : u64 = 4398046511104 ; pub const X86_EFLAGS_UNDEFINED_PF : u64 = 8796093022208 ; pub const X86_EFLAGS_UNDEFINED_AF : u64 = 17592186044416 ; pub const X86_EFLAGS_UNDEFINED_CF : u64 = 35184372088832 ; pub const X86_EFLAGS_RESET_RF : u64 = 70368744177664 ; pub const X86_EFLAGS_TEST_RF : u64 = 140737488355328 ; pub const X86_EFLAGS_TEST_IF : u64 = 281474976710656 ; pub const X86_EFLAGS_TEST_TF : u64 = 562949953421312 ; pub const X86_EFLAGS_TEST_AF : u64 = 1125899906842624 ; pub const X86_EFLAGS_RESET_ZF : u64 = 2251799813685248 ; pub const X86_EFLAGS_SET_OF : u64 = 4503599627370496 ; pub const X86_EFLAGS_SET_SF : u64 = 9007199254740992 ; pub const X86_EFLAGS_SET_ZF : u64 = 18014398509481984 ; pub const X86_EFLAGS_SET_AF : u64 = 36028797018963968 ; pub const X86_EFLAGS_SET_PF : u64 = 72057594037927936 ; pub const X86_EFLAGS_RESET_0F : u64 = 144115188075855872 ; pub const X86_EFLAGS_RESET_AC : u64 = 288230376151711744 ; pub const X86_FPU_FLAGS_MODIFY_C0 : u32 = 1 ; pub const X86_FPU_FLAGS_MODIFY_C1 : u32 = 2 ; pub const X86_FPU_FLAGS_MODIFY_C2 : u32 = 4 ; pub const X86_FPU_FLAGS_MODIFY_C3 : u32 = 8 ; pub const X86_FPU_FLAGS_RESET_C0 : u32 = 16 ; pub const X86_FPU_FLAGS_RESET_C1 : u32 = 32 ; pub const X86_FPU_FLAGS_RESET_C2 : u32 = 64 ; pub const X86_FPU_FLAGS_RESET_C3 : u32 = 128 ; pub const X86_FPU_FLAGS_SET_C0 : u32 = 256 ; pub const X86_FPU_FLAGS_SET_C1 : u32 = 512 ; pub const X86_FPU_FLAGS_SET_C2 : u32 = 1024 ; pub const X86_FPU_FLAGS_SET_C3 : u32 = 2048 ; pub const X86_FPU_FLAGS_UNDEFINED_C0 : u32 = 4096 ; pub const X86_FPU_FLAGS_UNDEFINED_C1 : u32 = 8192 ; pub const X86_FPU_FLAGS_UNDEFINED_C2 : u32 = 16384 ; pub const X86_FPU_FLAGS_UNDEFINED_C3 : u32 = 32768 ; pub const X86_FPU_FLAGS_TEST_C0 : u32 = 65536 ; pub const X86_FPU_FLAGS_TEST_C1 : u32 = 131072 ; pub const X86_FPU_FLAGS_TEST_C2 : u32 = 262144 ; pub const X86_FPU_FLAGS_TEST_C3 : u32 = 524288 ; pub const M680X_OPERAND_COUNT : u32 = 9 ; pub const M680X_OFFSET_NONE : u32 = 0 ; pub const M680X_OFFSET_BITS_5 : u32 = 5 ; pub const M680X_OFFSET_BITS_8 : u32 = 8 ; pub const M680X_OFFSET_BITS_9 : u32 = 9 ; pub const M680X_OFFSET_BITS_16 : u32 = 16 ; pub const M680X_IDX_INDIRECT : u32 = 1 ; pub const M680X_IDX_NO_COMMA : u32 = 2 ; pub const M680X_IDX_POST_INC_DEC : u32 = 4 ; pub const M680X_FIRST_OP_IN_MNEM : u32 = 1 ; pub const M680X_SECOND_OP_IN_MNEM : u32 = 2 ; pub const TRICORE_OP_COUNT : u32 = 8 ; pub const MAX_IMPL_W_REGS : u32 = 20 ; pub const MAX_IMPL_R_REGS : u32 = 20 ; pub const MAX_NUM_GROUPS : u32 = 8 ; pub type __gnuc_va_list = __builtin_va_list ; pub type va_list = __builtin_va_list ; pub type wchar_t = :: std :: os :: raw :: c_int ; pub type __cfloat128 = __BindgenComplex < u128 > ; pub type _Float128 = u128 ; pub type _Float32 = f32 ; pub type _Float64 = f64 ; pub type _Float32x = f64 ; pub type _Float64x = u128 ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct div_t { pub quot : :: std :: os :: raw :: c_int , pub rem : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of div_t"] [:: std :: mem :: size_of :: < div_t > () - 8usize] ; ["Alignment of div_t"] [:: std :: mem :: align_of :: < div_t > () - 4usize] ; ["Offset of field: div_t::quot"] [:: std :: mem :: offset_of ! (div_t , quot) - 0usize] ; ["Offset of field: div_t::rem"] [:: std :: mem :: offset_of ! (div_t , rem) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ldiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ldiv_t"] [:: std :: mem :: size_of :: < ldiv_t > () - 16usize] ; ["Alignment of ldiv_t"] [:: std :: mem :: align_of :: < ldiv_t > () - 8usize] ; ["Offset of field: ldiv_t::quot"] [:: std :: mem :: offset_of ! (ldiv_t , quot) - 0usize] ; ["Offset of field: ldiv_t::rem"] [:: std :: mem :: offset_of ! (ldiv_t , rem) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct lldiv_t { pub quot : :: std :: os :: raw :: c_longlong , pub rem : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of lldiv_t"] [:: std :: mem :: size_of :: < lldiv_t > () - 16usize] ; ["Alignment of lldiv_t"] [:: std :: mem :: align_of :: < lldiv_t > () - 8usize] ; ["Offset of field: lldiv_t::quot"] [:: std :: mem :: offset_of ! (lldiv_t , quot) - 0usize] ; ["Offset of field: lldiv_t::rem"] [:: std :: mem :: offset_of ! (lldiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn __ctype_get_mb_cur_max () -> usize ; } unsafe extern "C" { pub fn atof (__nptr : * const :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn atoi (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn atol (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn atoll (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtod (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn strtof (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f32 ; } unsafe extern "C" { pub fn strtold (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> u128 ; } unsafe extern "C" { pub fn strtol (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn strtoul (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn strtoq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtouq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn strtoll (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtoull (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn l64a (__n : :: std :: os :: raw :: c_long) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn a64l (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } pub type __u_char = :: std :: os :: raw :: c_uchar ; pub type __u_short = :: std :: os :: raw :: c_ushort ; pub type __u_int = :: std :: os :: raw :: c_uint ; pub type __u_long = :: std :: os :: raw :: c_ulong ; pub type __int8_t = :: std :: os :: raw :: c_schar ; pub type __uint8_t = :: std :: os :: raw :: c_uchar ; pub type __int16_t = :: std :: os :: raw :: c_short ; pub type __uint16_t = :: std :: os :: raw :: c_ushort ; pub type __int32_t = :: std :: os :: raw :: c_int ; pub type __uint32_t = :: std :: os :: raw :: c_uint ; pub type __int64_t = :: std :: os :: raw :: c_long ; pub type __uint64_t = :: std :: os :: raw :: c_ulong ; pub type __int_least8_t = __int8_t ; pub type __uint_least8_t = __uint8_t ; pub type __int_least16_t = __int16_t ; pub type __uint_least16_t = __uint16_t ; pub type __int_least32_t = __int32_t ; pub type __uint_least32_t = __uint32_t ; pub type __int_least64_t = __int64_t ; pub type __uint_least64_t = __uint64_t ; pub type __quad_t = :: std :: os :: raw :: c_long ; pub type __u_quad_t = :: std :: os :: raw :: c_ulong ; pub type __intmax_t = :: std :: os :: raw :: c_long ; pub type __uintmax_t = :: std :: os :: raw :: c_ulong ; pub type __dev_t = :: std :: os :: raw :: c_ulong ; pub type __uid_t = :: std :: os :: raw :: c_uint ; pub type __gid_t = :: std :: os :: raw :: c_uint ; pub type __ino_t = :: std :: os :: raw :: c_ulong ; pub type __ino64_t = :: std :: os :: raw :: c_ulong ; pub type __mode_t = :: std :: os :: raw :: c_uint ; pub type __nlink_t = :: std :: os :: raw :: c_ulong ; pub type __off_t = :: std :: os :: raw :: c_long ; pub type __off64_t = :: std :: os :: raw :: c_long ; pub type __pid_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __fsid_t { pub __val : [:: std :: os :: raw :: c_int ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __fsid_t"] [:: std :: mem :: size_of :: < __fsid_t > () - 8usize] ; ["Alignment of __fsid_t"] [:: std :: mem :: align_of :: < __fsid_t > () - 4usize] ; ["Offset of field: __fsid_t::__val"] [:: std :: mem :: offset_of ! (__fsid_t , __val) - 0usize] ; } ; pub type __clock_t = :: std :: os :: raw :: c_long ; pub type __rlim_t = :: std :: os :: raw :: c_ulong ; pub type __rlim64_t = :: std :: os :: raw :: c_ulong ; pub type __id_t = :: std :: os :: raw :: c_uint ; pub type __time_t = :: std :: os :: raw :: c_long ; pub type __useconds_t = :: std :: os :: raw :: c_uint ; pub type __suseconds_t = :: std :: os :: raw :: c_long ; pub type __suseconds64_t = :: std :: os :: raw :: c_long ; pub type __daddr_t = :: std :: os :: raw :: c_int ; pub type __key_t = :: std :: os :: raw :: c_int ; pub type __clockid_t = :: std :: os :: raw :: c_int ; pub type __timer_t = * mut :: std :: os :: raw :: c_void ; pub type __blksize_t = :: std :: os :: raw :: c_long ; pub type __blkcnt_t = :: std :: os :: raw :: c_long ; pub type __blkcnt64_t = :: std :: os :: raw :: c_long ; pub type __fsblkcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsblkcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsword_t = :: std :: os :: raw :: c_long ; pub type __ssize_t = :: std :: os :: raw :: c_long ; pub type __syscall_slong_t = :: std :: os :: raw :: c_long ; pub type __syscall_ulong_t = :: std :: os :: raw :: c_ulong ; pub type __loff_t = __off64_t ; pub type __caddr_t = * mut :: std :: os :: raw :: c_char ; pub type __intptr_t = :: std :: os :: raw :: c_long ; pub type __socklen_t = :: std :: os :: raw :: c_uint ; pub type __sig_atomic_t = :: std :: os :: raw :: c_int ; pub type u_char = __u_char ; pub type u_short = __u_short ; pub type u_int = __u_int ; pub type u_long = __u_long ; pub type quad_t = __quad_t ; pub type u_quad_t = __u_quad_t ; pub type fsid_t = __fsid_t ; pub type loff_t = __loff_t ; pub type ino_t = __ino_t ; pub type dev_t = __dev_t ; pub type gid_t = __gid_t ; pub type mode_t = __mode_t ; pub type nlink_t = __nlink_t ; pub type uid_t = __uid_t ; pub type off_t = __off_t ; pub type pid_t = __pid_t ; pub type id_t = __id_t ; pub type daddr_t = __daddr_t ; pub type caddr_t = __caddr_t ; pub type key_t = __key_t ; pub type clock_t = __clock_t ; pub type clockid_t = __clockid_t ; pub type time_t = __time_t ; pub type timer_t = __timer_t ; pub type ulong = :: std :: os :: raw :: c_ulong ; pub type ushort = :: std :: os :: raw :: c_ushort ; pub type uint = :: std :: os :: raw :: c_uint ; pub type u_int8_t = __uint8_t ; pub type u_int16_t = __uint16_t ; pub type u_int32_t = __uint32_t ; pub type u_int64_t = __uint64_t ; pub type register_t = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __sigset_t { pub __val : [:: std :: os :: raw :: c_ulong ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __sigset_t"] [:: std :: mem :: size_of :: < __sigset_t > () - 128usize] ; ["Alignment of __sigset_t"] [:: std :: mem :: align_of :: < __sigset_t > () - 8usize] ; ["Offset of field: __sigset_t::__val"] [:: std :: mem :: offset_of ! (__sigset_t , __val) - 0usize] ; } ; pub type sigset_t = __sigset_t ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timeval { pub tv_sec : __time_t , pub tv_usec : __suseconds_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timeval"] [:: std :: mem :: size_of :: < timeval > () - 16usize] ; ["Alignment of timeval"] [:: std :: mem :: align_of :: < timeval > () - 8usize] ; ["Offset of field: timeval::tv_sec"] [:: std :: mem :: offset_of ! (timeval , tv_sec) - 0usize] ; ["Offset of field: timeval::tv_usec"] [:: std :: mem :: offset_of ! (timeval , tv_usec) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timespec { pub tv_sec : __time_t , pub tv_nsec : __syscall_slong_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timespec"] [:: std :: mem :: size_of :: < timespec > () - 16usize] ; ["Alignment of timespec"] [:: std :: mem :: align_of :: < timespec > () - 8usize] ; ["Offset of field: timespec::tv_sec"] [:: std :: mem :: offset_of ! (timespec , tv_sec) - 0usize] ; ["Offset of field: timespec::tv_nsec"] [:: std :: mem :: offset_of ! (timespec , tv_nsec) - 8usize] ; } ; pub type suseconds_t = __suseconds_t ; pub type __fd_mask = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct fd_set { pub __fds_bits : [__fd_mask ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of fd_set"] [:: std :: mem :: size_of :: < fd_set > () - 128usize] ; ["Alignment of fd_set"] [:: std :: mem :: align_of :: < fd_set > () - 8usize] ; ["Offset of field: fd_set::__fds_bits"] [:: std :: mem :: offset_of ! (fd_set , __fds_bits) - 0usize] ; } ; pub type fd_mask = __fd_mask ; unsafe extern "C" { pub fn select (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * mut timeval) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pselect (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * const timespec , __sigmask : * const __sigset_t) -> :: std :: os :: raw :: c_int ; } pub type blksize_t = __blksize_t ; pub type blkcnt_t = __blkcnt_t ; pub type fsblkcnt_t = __fsblkcnt_t ; pub type fsfilcnt_t = __fsfilcnt_t ; # [repr (C)] # [derive (Copy , Clone)] pub union __atomic_wide_counter { pub __value64 : :: std :: os :: raw :: c_ulonglong , pub __value32 : __atomic_wide_counter__bindgen_ty_1 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __atomic_wide_counter__bindgen_ty_1 { pub __low : :: std :: os :: raw :: c_uint , pub __high : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: size_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 8usize] ; ["Alignment of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: align_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__low"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __low) - 0usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__high"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __high) - 4usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter"] [:: std :: mem :: size_of :: < __atomic_wide_counter > () - 8usize] ; ["Alignment of __atomic_wide_counter"] [:: std :: mem :: align_of :: < __atomic_wide_counter > () - 8usize] ; ["Offset of field: __atomic_wide_counter::__value64"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value64) - 0usize] ; ["Offset of field: __atomic_wide_counter::__value32"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value32) - 0usize] ; } ; impl :: std :: fmt :: Debug for __atomic_wide_counter { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__atomic_wide_counter {{ union }}") } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_list { pub __prev : * mut __pthread_internal_list , pub __next : * mut __pthread_internal_list , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_list"] [:: std :: mem :: size_of :: < __pthread_internal_list > () - 16usize] ; ["Alignment of __pthread_internal_list"] [:: std :: mem :: align_of :: < __pthread_internal_list > () - 8usize] ; ["Offset of field: __pthread_internal_list::__prev"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __prev) - 0usize] ; ["Offset of field: __pthread_internal_list::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __next) - 8usize] ; } ; pub type __pthread_list_t = __pthread_internal_list ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_slist { pub __next : * mut __pthread_internal_slist , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_slist"] [:: std :: mem :: size_of :: < __pthread_internal_slist > () - 8usize] ; ["Alignment of __pthread_internal_slist"] [:: std :: mem :: align_of :: < __pthread_internal_slist > () - 8usize] ; ["Offset of field: __pthread_internal_slist::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_slist , __next) - 0usize] ; } ; pub type __pthread_slist_t = __pthread_internal_slist ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_mutex_s { pub __lock : :: std :: os :: raw :: c_int , pub __count : :: std :: os :: raw :: c_uint , pub __owner : :: std :: os :: raw :: c_int , pub __nusers : :: std :: os :: raw :: c_uint , pub __kind : :: std :: os :: raw :: c_int , pub __spins : :: std :: os :: raw :: c_short , pub __unused : :: std :: os :: raw :: c_short , pub __list : __pthread_list_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_mutex_s"] [:: std :: mem :: size_of :: < __pthread_mutex_s > () - 40usize] ; ["Alignment of __pthread_mutex_s"] [:: std :: mem :: align_of :: < __pthread_mutex_s > () - 8usize] ; ["Offset of field: __pthread_mutex_s::__lock"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __lock) - 0usize] ; ["Offset of field: __pthread_mutex_s::__count"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __count) - 4usize] ; ["Offset of field: __pthread_mutex_s::__owner"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __owner) - 8usize] ; ["Offset of field: __pthread_mutex_s::__nusers"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __nusers) - 12usize] ; ["Offset of field: __pthread_mutex_s::__kind"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __kind) - 16usize] ; ["Offset of field: __pthread_mutex_s::__spins"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __spins) - 20usize] ; ["Offset of field: __pthread_mutex_s::__unused"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __unused) - 22usize] ; ["Offset of field: __pthread_mutex_s::__list"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __list) - 24usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_rwlock_arch_t { pub __readers : :: std :: os :: raw :: c_uint , pub __writers : :: std :: os :: raw :: c_uint , pub __wrphase_futex : :: std :: os :: raw :: c_uint , pub __writers_futex : :: std :: os :: raw :: c_uint , pub __pad3 : :: std :: os :: raw :: c_uint , pub __pad4 : :: std :: os :: raw :: c_uint , pub __cur_writer : :: std :: os :: raw :: c_int , pub __shared : :: std :: os :: raw :: c_int , pub __pad1 : :: std :: os :: raw :: c_ulong , pub __pad2 : :: std :: os :: raw :: c_ulong , pub __flags : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_rwlock_arch_t"] [:: std :: mem :: size_of :: < __pthread_rwlock_arch_t > () - 56usize] ; ["Alignment of __pthread_rwlock_arch_t"] [:: std :: mem :: align_of :: < __pthread_rwlock_arch_t > () - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__readers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __readers) - 0usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers) - 4usize] ; ["Offset of field: __pthread_rwlock_arch_t::__wrphase_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __wrphase_futex) - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers_futex) - 12usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad3"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad3) - 16usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad4"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad4) - 20usize] ; ["Offset of field: __pthread_rwlock_arch_t::__cur_writer"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __cur_writer) - 24usize] ; ["Offset of field: __pthread_rwlock_arch_t::__shared"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __shared) - 28usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad1"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad1) - 32usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad2"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad2) - 40usize] ; ["Offset of field: __pthread_rwlock_arch_t::__flags"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __flags) - 48usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct __pthread_cond_s { pub __wseq : __atomic_wide_counter , pub __g1_start : __atomic_wide_counter , pub __g_size : [:: std :: os :: raw :: c_uint ; 2usize] , pub __g1_orig_size : :: std :: os :: raw :: c_uint , pub __wrefs : :: std :: os :: raw :: c_uint , pub __g_signals : [:: std :: os :: raw :: c_uint ; 2usize] , pub __unused_initialized_1 : :: std :: os :: raw :: c_uint , pub __unused_initialized_2 : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_cond_s"] [:: std :: mem :: size_of :: < __pthread_cond_s > () - 48usize] ; ["Alignment of __pthread_cond_s"] [:: std :: mem :: align_of :: < __pthread_cond_s > () - 8usize] ; ["Offset of field: __pthread_cond_s::__wseq"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wseq) - 0usize] ; ["Offset of field: __pthread_cond_s::__g1_start"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_start) - 8usize] ; ["Offset of field: __pthread_cond_s::__g_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_size) - 16usize] ; ["Offset of field: __pthread_cond_s::__g1_orig_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_orig_size) - 24usize] ; ["Offset of field: __pthread_cond_s::__wrefs"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wrefs) - 28usize] ; ["Offset of field: __pthread_cond_s::__g_signals"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_signals) - 32usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_1"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_1) - 40usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_2"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_2) - 44usize] ; } ; impl :: std :: fmt :: Debug for __pthread_cond_s { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__pthread_cond_s {{ __wseq: {:?}, __g1_start: {:?}, __g_size: {:?}, __g1_orig_size: {:?}, __wrefs: {:?}, __g_signals: {:?}, __unused_initialized_1: {:?}, __unused_initialized_2: {:?} }}" , self . __wseq , self . __g1_start , self . __g_size , self . __g1_orig_size , self . __wrefs , self . __g_signals , self . __unused_initialized_1 , self . __unused_initialized_2) } } pub type __tss_t = :: std :: os :: raw :: c_uint ; pub type __thrd_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __once_flag { pub __data : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __once_flag"] [:: std :: mem :: size_of :: < __once_flag > () - 4usize] ; ["Alignment of __once_flag"] [:: std :: mem :: align_of :: < __once_flag > () - 4usize] ; ["Offset of field: __once_flag::__data"] [:: std :: mem :: offset_of ! (__once_flag , __data) - 0usize] ; } ; pub type pthread_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutexattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutexattr_t"] [:: std :: mem :: size_of :: < pthread_mutexattr_t > () - 4usize] ; ["Alignment of pthread_mutexattr_t"] [:: std :: mem :: align_of :: < pthread_mutexattr_t > () - 4usize] ; ["Offset of field: pthread_mutexattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __size) - 0usize] ; ["Offset of field: pthread_mutexattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutexattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutexattr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_condattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_condattr_t"] [:: std :: mem :: size_of :: < pthread_condattr_t > () - 4usize] ; ["Alignment of pthread_condattr_t"] [:: std :: mem :: align_of :: < pthread_condattr_t > () - 4usize] ; ["Offset of field: pthread_condattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __size) - 0usize] ; ["Offset of field: pthread_condattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_condattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_condattr_t {{ union }}") } } pub type pthread_key_t = :: std :: os :: raw :: c_uint ; pub type pthread_once_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_attr_t { pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_attr_t"] [:: std :: mem :: size_of :: < pthread_attr_t > () - 56usize] ; ["Alignment of pthread_attr_t"] [:: std :: mem :: align_of :: < pthread_attr_t > () - 8usize] ; ["Offset of field: pthread_attr_t::__size"] [:: std :: mem :: offset_of ! (pthread_attr_t , __size) - 0usize] ; ["Offset of field: pthread_attr_t::__align"] [:: std :: mem :: offset_of ! (pthread_attr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_attr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_attr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutex_t { pub __data : __pthread_mutex_s , pub __size : [:: std :: os :: raw :: c_char ; 40usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutex_t"] [:: std :: mem :: size_of :: < pthread_mutex_t > () - 40usize] ; ["Alignment of pthread_mutex_t"] [:: std :: mem :: align_of :: < pthread_mutex_t > () - 8usize] ; ["Offset of field: pthread_mutex_t::__data"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __data) - 0usize] ; ["Offset of field: pthread_mutex_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __size) - 0usize] ; ["Offset of field: pthread_mutex_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutex_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutex_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_cond_t { pub __data : __pthread_cond_s , pub __size : [:: std :: os :: raw :: c_char ; 48usize] , pub __align : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_cond_t"] [:: std :: mem :: size_of :: < pthread_cond_t > () - 48usize] ; ["Alignment of pthread_cond_t"] [:: std :: mem :: align_of :: < pthread_cond_t > () - 8usize] ; ["Offset of field: pthread_cond_t::__data"] [:: std :: mem :: offset_of ! (pthread_cond_t , __data) - 0usize] ; ["Offset of field: pthread_cond_t::__size"] [:: std :: mem :: offset_of ! (pthread_cond_t , __size) - 0usize] ; ["Offset of field: pthread_cond_t::__align"] [:: std :: mem :: offset_of ! (pthread_cond_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_cond_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_cond_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlock_t { pub __data : __pthread_rwlock_arch_t , pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlock_t"] [:: std :: mem :: size_of :: < pthread_rwlock_t > () - 56usize] ; ["Alignment of pthread_rwlock_t"] [:: std :: mem :: align_of :: < pthread_rwlock_t > () - 8usize] ; ["Offset of field: pthread_rwlock_t::__data"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __data) - 0usize] ; ["Offset of field: pthread_rwlock_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __size) - 0usize] ; ["Offset of field: pthread_rwlock_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlock_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlock_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlockattr_t { pub __size : [:: std :: os :: raw :: c_char ; 8usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlockattr_t"] [:: std :: mem :: size_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Alignment of pthread_rwlockattr_t"] [:: std :: mem :: align_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Offset of field: pthread_rwlockattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __size) - 0usize] ; ["Offset of field: pthread_rwlockattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlockattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlockattr_t {{ union }}") } } pub type pthread_spinlock_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrier_t { pub __size : [:: std :: os :: raw :: c_char ; 32usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrier_t"] [:: std :: mem :: size_of :: < pthread_barrier_t > () - 32usize] ; ["Alignment of pthread_barrier_t"] [:: std :: mem :: align_of :: < pthread_barrier_t > () - 8usize] ; ["Offset of field: pthread_barrier_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __size) - 0usize] ; ["Offset of field: pthread_barrier_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrier_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrier_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrierattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrierattr_t"] [:: std :: mem :: size_of :: < pthread_barrierattr_t > () - 4usize] ; ["Alignment of pthread_barrierattr_t"] [:: std :: mem :: align_of :: < pthread_barrierattr_t > () - 4usize] ; ["Offset of field: pthread_barrierattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __size) - 0usize] ; ["Offset of field: pthread_barrierattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrierattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrierattr_t {{ union }}") } } unsafe extern "C" { pub fn random () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srandom (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn initstate (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn setstate (__statebuf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct random_data { pub fptr : * mut i32 , pub rptr : * mut i32 , pub state : * mut i32 , pub rand_type : :: std :: os :: raw :: c_int , pub rand_deg : :: std :: os :: raw :: c_int , pub rand_sep : :: std :: os :: raw :: c_int , pub end_ptr : * mut i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of random_data"] [:: std :: mem :: size_of :: < random_data > () - 48usize] ; ["Alignment of random_data"] [:: std :: mem :: align_of :: < random_data > () - 8usize] ; ["Offset of field: random_data::fptr"] [:: std :: mem :: offset_of ! (random_data , fptr) - 0usize] ; ["Offset of field: random_data::rptr"] [:: std :: mem :: offset_of ! (random_data , rptr) - 8usize] ; ["Offset of field: random_data::state"] [:: std :: mem :: offset_of ! (random_data , state) - 16usize] ; ["Offset of field: random_data::rand_type"] [:: std :: mem :: offset_of ! (random_data , rand_type) - 24usize] ; ["Offset of field: random_data::rand_deg"] [:: std :: mem :: offset_of ! (random_data , rand_deg) - 28usize] ; ["Offset of field: random_data::rand_sep"] [:: std :: mem :: offset_of ! (random_data , rand_sep) - 32usize] ; ["Offset of field: random_data::end_ptr"] [:: std :: mem :: offset_of ! (random_data , end_ptr) - 40usize] ; } ; unsafe extern "C" { pub fn random_r (__buf : * mut random_data , __result : * mut i32) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srandom_r (__seed : :: std :: os :: raw :: c_uint , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn initstate_r (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setstate_r (__statebuf : * mut :: std :: os :: raw :: c_char , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rand () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn rand_r (__seed : * mut :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn drand48 () -> f64 ; } unsafe extern "C" { pub fn erand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> f64 ; } unsafe extern "C" { pub fn lrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn nrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn mrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn jrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srand48 (__seedval : :: std :: os :: raw :: c_long) ; } unsafe extern "C" { pub fn seed48 (__seed16v : * mut :: std :: os :: raw :: c_ushort) -> * mut :: std :: os :: raw :: c_ushort ; } unsafe extern "C" { pub fn lcong48 (__param : * mut :: std :: os :: raw :: c_ushort) ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct drand48_data { pub __x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __old_x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __c : :: std :: os :: raw :: c_ushort , pub __init : :: std :: os :: raw :: c_ushort , pub __a : :: std :: os :: raw :: c_ulonglong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of drand48_data"] [:: std :: mem :: size_of :: < drand48_data > () - 24usize] ; ["Alignment of drand48_data"] [:: std :: mem :: align_of :: < drand48_data > () - 8usize] ; ["Offset of field: drand48_data::__x"] [:: std :: mem :: offset_of ! (drand48_data , __x) - 0usize] ; ["Offset of field: drand48_data::__old_x"] [:: std :: mem :: offset_of ! (drand48_data , __old_x) - 6usize] ; ["Offset of field: drand48_data::__c"] [:: std :: mem :: offset_of ! (drand48_data , __c) - 12usize] ; ["Offset of field: drand48_data::__init"] [:: std :: mem :: offset_of ! (drand48_data , __init) - 14usize] ; ["Offset of field: drand48_data::__a"] [:: std :: mem :: offset_of ! (drand48_data , __a) - 16usize] ; } ; unsafe extern "C" { pub fn drand48_r (__buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn erand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn nrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn jrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand48_r (__seedval : :: std :: os :: raw :: c_long , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn seed48_r (__seed16v : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lcong48_r (__param : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn arc4random () -> __uint32_t ; } unsafe extern "C" { pub fn arc4random_buf (__buf : * mut :: std :: os :: raw :: c_void , __size : usize) ; } unsafe extern "C" { pub fn arc4random_uniform (__upper_bound : __uint32_t) -> __uint32_t ; } unsafe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn calloc (__nmemb : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn free (__ptr : * mut :: std :: os :: raw :: c_void) ; } unsafe extern "C" { pub fn reallocarray (__ptr : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn alloca (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn valloc (__size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn posix_memalign (__memptr : * mut * mut :: std :: os :: raw :: c_void , __alignment : usize , __size : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn aligned_alloc (__alignment : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn abort () -> ! ; } unsafe extern "C" { pub fn atexit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn at_quick_exit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn on_exit (__func : :: std :: option :: Option < unsafe extern "C" fn (__status : :: std :: os :: raw :: c_int , __arg : * mut :: std :: os :: raw :: c_void) > , __arg : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn quick_exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn _Exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn getenv (__name : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn putenv (__string : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setenv (__name : * const :: std :: os :: raw :: c_char , __value : * const :: std :: os :: raw :: c_char , __replace : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn unsetenv (__name : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearenv () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mktemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn mkstemp (__template : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkstemps (__template : * mut :: std :: os :: raw :: c_char , __suffixlen : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkdtemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn system (__command : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn realpath (__name : * const :: std :: os :: raw :: c_char , __resolved : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } pub type __compar_fn_t = :: std :: option :: Option < unsafe extern "C" fn (arg1 : * const :: std :: os :: raw :: c_void , arg2 : * const :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; unsafe extern "C" { pub fn bsearch (__key : * const :: std :: os :: raw :: c_void , __base : * const :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn qsort (__base : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) ; } unsafe extern "C" { pub fn abs (__x : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn labs (__x : :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn llabs (__x : :: std :: os :: raw :: c_longlong) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn div (__numer : :: std :: os :: raw :: c_int , __denom : :: std :: os :: raw :: c_int) -> div_t ; } unsafe extern "C" { pub fn ldiv (__numer : :: std :: os :: raw :: c_long , __denom : :: std :: os :: raw :: c_long) -> ldiv_t ; } unsafe extern "C" { pub fn lldiv (__numer : :: std :: os :: raw :: c_longlong , __denom : :: std :: os :: raw :: c_longlong) -> lldiv_t ; } unsafe extern "C" { pub fn ecvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn gcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qecvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qfcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qgcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn ecvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fcvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qecvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qfcvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mblen (__s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbtowc (__pwc : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn wctomb (__s : * mut :: std :: os :: raw :: c_char , __wchar : wchar_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbstowcs (__pwcs : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> usize ; } unsafe extern "C" { pub fn wcstombs (__s : * mut :: std :: os :: raw :: c_char , __pwcs : * const wchar_t , __n : usize) -> usize ; } unsafe extern "C" { pub fn rpmatch (__response : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getsubopt (__optionp : * mut * mut :: std :: os :: raw :: c_char , __tokens : * const * mut :: std :: os :: raw :: c_char , __valuep : * mut * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getloadavg (__loadavg : * mut f64 , __nelem : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } # [repr (C)] # [derive (Copy , Clone)] pub struct __mbstate_t { pub __count : :: std :: os :: raw :: c_int , pub __value : __mbstate_t__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union __mbstate_t__bindgen_ty_1 { pub __wch : :: std :: os :: raw :: c_uint , pub __wchb : [:: std :: os :: raw :: c_char ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: size_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Alignment of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: align_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wch"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wch) - 0usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wchb"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wchb) - 0usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t"] [:: std :: mem :: size_of :: < __mbstate_t > () - 8usize] ; ["Alignment of __mbstate_t"] [:: std :: mem :: align_of :: < __mbstate_t > () - 4usize] ; ["Offset of field: __mbstate_t::__count"] [:: std :: mem :: offset_of ! (__mbstate_t , __count) - 0usize] ; ["Offset of field: __mbstate_t::__value"] [:: std :: mem :: offset_of ! (__mbstate_t , __value) - 4usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t {{ __count: {:?}, __value: {:?} }}" , self . __count , self . __value) } } # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos_t { pub __pos : __off_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos_t"] [:: std :: mem :: size_of :: < _G_fpos_t > () - 16usize] ; ["Alignment of _G_fpos_t"] [:: std :: mem :: align_of :: < _G_fpos_t > () - 8usize] ; ["Offset of field: _G_fpos_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos_t , __pos) - 0usize] ; ["Offset of field: _G_fpos_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos_t = _G_fpos_t ; # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos64_t { pub __pos : __off64_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos64_t"] [:: std :: mem :: size_of :: < _G_fpos64_t > () - 16usize] ; ["Alignment of _G_fpos64_t"] [:: std :: mem :: align_of :: < _G_fpos64_t > () - 8usize] ; ["Offset of field: _G_fpos64_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __pos) - 0usize] ; ["Offset of field: _G_fpos64_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos64_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos64_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos64_t = _G_fpos64_t ; pub type __FILE = _IO_FILE ; pub type FILE = _IO_FILE ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_marker { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_codecvt { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_wide_data { _unused : [u8 ; 0] , } pub type _IO_lock_t = :: std :: os :: raw :: c_void ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_FILE { pub _flags : :: std :: os :: raw :: c_int , pub _IO_read_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_read_end : * mut :: std :: os :: raw :: c_char , pub _IO_read_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_write_end : * mut :: std :: os :: raw :: c_char , pub _IO_buf_base : * mut :: std :: os :: raw :: c_char , pub _IO_buf_end : * mut :: std :: os :: raw :: c_char , pub _IO_save_base : * mut :: std :: os :: raw :: c_char , pub _IO_backup_base : * mut :: std :: os :: raw :: c_char , pub _IO_save_end : * mut :: std :: os :: raw :: c_char , pub _markers : * mut _IO_marker , pub _chain : * mut _IO_FILE , pub _fileno : :: std :: os :: raw :: c_int , pub _bitfield_align_1 : [u32 ; 0] , pub _bitfield_1 : __BindgenBitfieldUnit < [u8 ; 3usize] > , pub _short_backupbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _old_offset : __off_t , pub _cur_column : :: std :: os :: raw :: c_ushort , pub _vtable_offset : :: std :: os :: raw :: c_schar , pub _shortbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _lock : * mut _IO_lock_t , pub _offset : __off64_t , pub _codecvt : * mut _IO_codecvt , pub _wide_data : * mut _IO_wide_data , pub _freeres_list : * mut _IO_FILE , pub _freeres_buf : * mut :: std :: os :: raw :: c_void , pub _prevchain : * mut * mut _IO_FILE , pub _mode : :: std :: os :: raw :: c_int , pub _unused3 : :: std :: os :: raw :: c_int , pub _total_written : __uint64_t , pub _unused2 : [:: std :: os :: raw :: c_char ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_FILE"] [:: std :: mem :: size_of :: < _IO_FILE > () - 216usize] ; ["Alignment of _IO_FILE"] [:: std :: mem :: align_of :: < _IO_FILE > () - 8usize] ; ["Offset of field: _IO_FILE::_flags"] [:: std :: mem :: offset_of ! (_IO_FILE , _flags) - 0usize] ; ["Offset of field: _IO_FILE::_IO_read_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_ptr) - 8usize] ; ["Offset of field: _IO_FILE::_IO_read_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_end) - 16usize] ; ["Offset of field: _IO_FILE::_IO_read_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_base) - 24usize] ; ["Offset of field: _IO_FILE::_IO_write_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_base) - 32usize] ; ["Offset of field: _IO_FILE::_IO_write_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_ptr) - 40usize] ; ["Offset of field: _IO_FILE::_IO_write_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_end) - 48usize] ; ["Offset of field: _IO_FILE::_IO_buf_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_base) - 56usize] ; ["Offset of field: _IO_FILE::_IO_buf_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_end) - 64usize] ; ["Offset of field: _IO_FILE::_IO_save_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_base) - 72usize] ; ["Offset of field: _IO_FILE::_IO_backup_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_backup_base) - 80usize] ; ["Offset of field: _IO_FILE::_IO_save_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_end) - 88usize] ; ["Offset of field: _IO_FILE::_markers"] [:: std :: mem :: offset_of ! (_IO_FILE , _markers) - 96usize] ; ["Offset of field: _IO_FILE::_chain"] [:: std :: mem :: offset_of ! (_IO_FILE , _chain) - 104usize] ; ["Offset of field: _IO_FILE::_fileno"] [:: std :: mem :: offset_of ! (_IO_FILE , _fileno) - 112usize] ; ["Offset of field: _IO_FILE::_short_backupbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _short_backupbuf) - 119usize] ; ["Offset of field: _IO_FILE::_old_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _old_offset) - 120usize] ; ["Offset of field: _IO_FILE::_cur_column"] [:: std :: mem :: offset_of ! (_IO_FILE , _cur_column) - 128usize] ; ["Offset of field: _IO_FILE::_vtable_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _vtable_offset) - 130usize] ; ["Offset of field: _IO_FILE::_shortbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _shortbuf) - 131usize] ; ["Offset of field: _IO_FILE::_lock"] [:: std :: mem :: offset_of ! (_IO_FILE , _lock) - 136usize] ; ["Offset of field: _IO_FILE::_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _offset) - 144usize] ; ["Offset of field: _IO_FILE::_codecvt"] [:: std :: mem :: offset_of ! (_IO_FILE , _codecvt) - 152usize] ; ["Offset of field: _IO_FILE::_wide_data"] [:: std :: mem :: offset_of ! (_IO_FILE , _wide_data) - 160usize] ; ["Offset of field: _IO_FILE::_freeres_list"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_list) - 168usize] ; ["Offset of field: _IO_FILE::_freeres_buf"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_buf) - 176usize] ; ["Offset of field: _IO_FILE::_prevchain"] [:: std :: mem :: offset_of ! (_IO_FILE , _prevchain) - 184usize] ; ["Offset of field: _IO_FILE::_mode"] [:: std :: mem :: offset_of ! (_IO_FILE , _mode) - 192usize] ; ["Offset of field: _IO_FILE::_unused3"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused3) - 196usize] ; ["Offset of field: _IO_FILE::_total_written"] [:: std :: mem :: offset_of ! (_IO_FILE , _total_written) - 200usize] ; ["Offset of field: _IO_FILE::_unused2"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused2) - 208usize] ; } ; impl _IO_FILE { # [inline] pub fn _flags2 (& self) -> :: std :: os :: raw :: c_int { unsafe { u32::cast_signed (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set__flags2 (& mut self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; self . _bitfield_1 . set (0usize , 24u8 , val as u64) } } # [inline] pub unsafe fn _flags2_raw (this : * const Self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } } # [inline] pub unsafe fn set__flags2_raw (this : * mut Self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_set (:: std :: ptr :: addr_of_mut ! ((* this) . _bitfield_1) , 0usize , 24u8 , val as u64 ,) } } # [inline] pub fn new_bitfield_1 (_flags2 : :: std :: os :: raw :: c_int) -> __BindgenBitfieldUnit < [u8 ; 3usize] > { let mut __bindgen_bitfield_unit : __BindgenBitfieldUnit < [u8 ; 3usize] > = Default :: default () ; __bindgen_bitfield_unit . set (0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_unit } } pub type cookie_read_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * mut :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_write_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * const :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_seek_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __pos : * mut __off64_t , __w : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int > ; pub type cookie_close_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_cookie_io_functions_t { pub read : cookie_read_function_t , pub write : cookie_write_function_t , pub seek : cookie_seek_function_t , pub close : cookie_close_function_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_cookie_io_functions_t"] [:: std :: mem :: size_of :: < _IO_cookie_io_functions_t > () - 32usize] ; ["Alignment of _IO_cookie_io_functions_t"] [:: std :: mem :: align_of :: < _IO_cookie_io_functions_t > () - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::read"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , read) - 0usize] ; ["Offset of field: _IO_cookie_io_functions_t::write"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , write) - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::seek"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , seek) - 16usize] ; ["Offset of field: _IO_cookie_io_functions_t::close"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , close) - 24usize] ; } ; pub type cookie_io_functions_t = _IO_cookie_io_functions_t ; pub type fpos_t = __fpos_t ; unsafe extern "C" { pub static mut stdin : * mut FILE ; } unsafe extern "C" { pub static mut stdout : * mut FILE ; } unsafe extern "C" { pub static mut stderr : * mut FILE ; } unsafe extern "C" { pub fn remove (__filename : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rename (__old : * const :: std :: os :: raw :: c_char , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn renameat (__oldfd : :: std :: os :: raw :: c_int , __old : * const :: std :: os :: raw :: c_char , __newfd : :: std :: os :: raw :: c_int , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn tmpfile () -> * mut FILE ; } unsafe extern "C" { pub fn tmpnam (arg1 : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tmpnam_r (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tempnam (__dir : * const :: std :: os :: raw :: c_char , __pfx : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fflush (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fflush_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn freopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> * mut FILE ; } unsafe extern "C" { pub fn fdopen (__fd : :: std :: os :: raw :: c_int , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn fopencookie (__magic_cookie : * mut :: std :: os :: raw :: c_void , __modes : * const :: std :: os :: raw :: c_char , __io_funcs : cookie_io_functions_t) -> * mut FILE ; } unsafe extern "C" { pub fn fmemopen (__s : * mut :: std :: os :: raw :: c_void , __len : usize , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn open_memstream (__bufloc : * mut * mut :: std :: os :: raw :: c_char , __sizeloc : * mut usize) -> * mut FILE ; } unsafe extern "C" { pub fn setbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn setvbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __modes : :: std :: os :: raw :: c_int , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setbuffer (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __size : usize) ; } unsafe extern "C" { pub fn setlinebuf (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fprintf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn printf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfprintf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vprintf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn snprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsnprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vasprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __f : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vdprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn dprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fscanf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn scanf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_fscanf"] pub fn fscanf1 (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_scanf"] pub fn scanf1 (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_sscanf"] pub fn sscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfscanf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vscanf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vfscanf"] pub fn vfscanf1 (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vscanf"] pub fn vscanf1 (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vsscanf"] pub fn vsscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar_unlocked () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar_unlocked (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getw (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putw (__w : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgets (__s : * mut :: std :: os :: raw :: c_char , __n : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn __getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getline (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn fputs (__s : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn puts (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ungetc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fread (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __stream : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fwrite (__ptr : * const :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __s : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fread_unlocked (__ptr : * mut :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fwrite_unlocked (__ptr : * const :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fseek (__stream : * mut FILE , __off : :: std :: os :: raw :: c_long , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftell (__stream : * mut FILE) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn rewind (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fseeko (__stream : * mut FILE , __off : __off_t , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftello (__stream : * mut FILE) -> __off_t ; } unsafe extern "C" { pub fn fgetpos (__stream : * mut FILE , __pos : * mut fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fsetpos (__stream : * mut FILE , __pos : * const fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr_unlocked (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn perror (__s : * const :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn fileno (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fileno_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn popen (__command : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn ctermid (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn flockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn ftrylockfile (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn funlockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn __uflow (arg1 : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __overflow (arg1 : * mut FILE , arg2 : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } pub type int_least8_t = __int_least8_t ; pub type int_least16_t = __int_least16_t ; pub type int_least32_t = __int_least32_t ; pub type int_least64_t = __int_least64_t ; pub type uint_least8_t = __uint_least8_t ; pub type uint_least16_t = __uint_least16_t ; pub type uint_least32_t = __uint_least32_t ; pub type uint_least64_t = __uint_least64_t ; pub type int_fast8_t = :: std :: os :: raw :: c_schar ; pub type int_fast16_t = :: std :: os :: raw :: c_long ; pub type int_fast32_t = :: std :: os :: raw :: c_long ; pub type int_fast64_t = :: std :: os :: raw :: c_long ; pub type uint_fast8_t = :: std :: os :: raw :: c_uchar ; pub type uint_fast16_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast32_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast64_t = :: std :: os :: raw :: c_ulong ; pub type intmax_t = __intmax_t ; pub type uintmax_t = __uintmax_t ; pub type __gwchar_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct imaxdiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of imaxdiv_t"] [:: std :: mem :: size_of :: < imaxdiv_t > () - 16usize] ; ["Alignment of imaxdiv_t"] [:: std :: mem :: align_of :: < imaxdiv_t > () - 8usize] ; ["Offset of field: imaxdiv_t::quot"] [:: std :: mem :: offset_of ! (imaxdiv_t , quot) - 0usize] ; ["Offset of field: imaxdiv_t::rem"] [:: std :: mem :: offset_of ! (imaxdiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn imaxabs (__n : intmax_t) -> intmax_t ; } unsafe extern "C" { pub fn imaxdiv (__numer : intmax_t , __denom : intmax_t) -> imaxdiv_t ; } unsafe extern "C" { pub fn strtoimax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn strtoumax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } unsafe extern "C" { pub fn wcstoimax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn wcstoumax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } pub type csh = usize ; # [repr (u32)] # [doc = " Architecture type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_arch { # [doc = "< ARM architecture (including Thumb, Thumb-2)"] CS_ARCH_ARM = 0 , # [doc = "< ARM-64, also called AArch64"] CS_ARCH_ARM64 = 1 , # [doc = "< Mips architecture"] CS_ARCH_MIPS = 2 , # [doc = "< X86 architecture (including x86 & x86-64)"] CS_ARCH_X86 = 3 , # [doc = "< PowerPC architecture"] CS_ARCH_PPC = 4 , # [doc = "< Sparc architecture"] CS_ARCH_SPARC = 5 , # [doc = "< SystemZ architecture"] CS_ARCH_SYSZ = 6 , # [doc = "< XCore architecture"] CS_ARCH_XCORE = 7 , # [doc = "< 68K architecture"] CS_ARCH_M68K = 8 , # [doc = "< TMS320C64x architecture"] CS_ARCH_TMS320C64X = 9 , # [doc = "< 680X architecture"] CS_ARCH_M680X = 10 , # [doc = "< Ethereum architecture"] CS_ARCH_EVM = 11 , # [doc = "< MOS65XX architecture (including MOS6502)"] CS_ARCH_MOS65XX = 12 , # [doc = "< WebAssembly architecture"] CS_ARCH_WASM = 13 , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] CS_ARCH_BPF = 14 , # [doc = "< RISCV architecture"] CS_ARCH_RISCV = 15 , # [doc = "< SH architecture"] CS_ARCH_SH = 16 , # [doc = "< TriCore architecture"] CS_ARCH_TRICORE = 17 , CS_ARCH_MAX = 18 , CS_ARCH_ALL = 65535 , } # [doc = "< little-endian mode (default mode)"] pub const cs_mode_CS_MODE_LITTLE_ENDIAN : cs_mode = 0 ; # [doc = "< 32-bit ARM"] pub const cs_mode_CS_MODE_ARM : cs_mode = 0 ; # [doc = "< 16-bit mode (X86)"] pub const cs_mode_CS_MODE_16 : cs_mode = 2 ; # [doc = "< 32-bit mode (X86)"] pub const cs_mode_CS_MODE_32 : cs_mode = 4 ; # [doc = "< 64-bit mode (X86, PPC)"] pub const cs_mode_CS_MODE_64 : cs_mode = 8 ; # [doc = "< ARM's Thumb mode, including Thumb-2"] pub const cs_mode_CS_MODE_THUMB : cs_mode = 16 ; # [doc = "< ARM's Cortex-M series"] pub const cs_mode_CS_MODE_MCLASS : cs_mode = 32 ; # [doc = "< ARMv8 A32 encodings for ARM"] pub const cs_mode_CS_MODE_V8 : cs_mode = 64 ; # [doc = "< MicroMips mode (MIPS)"] pub const cs_mode_CS_MODE_MICRO : cs_mode = 16 ; # [doc = "< Mips III ISA"] pub const cs_mode_CS_MODE_MIPS3 : cs_mode = 32 ; # [doc = "< Mips32r6 ISA"] pub const cs_mode_CS_MODE_MIPS32R6 : cs_mode = 64 ; # [doc = "< Mips II ISA"] pub const cs_mode_CS_MODE_MIPS2 : cs_mode = 128 ; # [doc = "< SparcV9 mode (Sparc)"] pub const cs_mode_CS_MODE_V9 : cs_mode = 16 ; # [doc = "< Quad Processing eXtensions mode (PPC)"] pub const cs_mode_CS_MODE_QPX : cs_mode = 16 ; # [doc = "< Signal Processing Engine mode (PPC)"] pub const cs_mode_CS_MODE_SPE : cs_mode = 32 ; # [doc = "< Book-E mode (PPC)"] pub const cs_mode_CS_MODE_BOOKE : cs_mode = 64 ; # [doc = "< Paired-singles mode (PPC)"] pub const cs_mode_CS_MODE_PS : cs_mode = 128 ; # [doc = "< M68K 68000 mode"] pub const cs_mode_CS_MODE_M68K_000 : cs_mode = 2 ; # [doc = "< M68K 68010 mode"] pub const cs_mode_CS_MODE_M68K_010 : cs_mode = 4 ; # [doc = "< M68K 68020 mode"] pub const cs_mode_CS_MODE_M68K_020 : cs_mode = 8 ; # [doc = "< M68K 68030 mode"] pub const cs_mode_CS_MODE_M68K_030 : cs_mode = 16 ; # [doc = "< M68K 68040 mode"] pub const cs_mode_CS_MODE_M68K_040 : cs_mode = 32 ; # [doc = "< M68K 68060 mode"] pub const cs_mode_CS_MODE_M68K_060 : cs_mode = 64 ; # [doc = "< big-endian mode"] pub const cs_mode_CS_MODE_BIG_ENDIAN : cs_mode = 2147483648 ; # [doc = "< Mips32 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS32 : cs_mode = 4 ; # [doc = "< Mips64 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS64 : cs_mode = 8 ; # [doc = "< M680X Hitachi 6301,6303 mode"] pub const cs_mode_CS_MODE_M680X_6301 : cs_mode = 2 ; # [doc = "< M680X Hitachi 6309 mode"] pub const cs_mode_CS_MODE_M680X_6309 : cs_mode = 4 ; # [doc = "< M680X Motorola 6800,6802 mode"] pub const cs_mode_CS_MODE_M680X_6800 : cs_mode = 8 ; # [doc = "< M680X Motorola 6801,6803 mode"] pub const cs_mode_CS_MODE_M680X_6801 : cs_mode = 16 ; # [doc = "< M680X Motorola/Freescale 6805 mode"] pub const cs_mode_CS_MODE_M680X_6805 : cs_mode = 32 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"] pub const cs_mode_CS_MODE_M680X_6808 : cs_mode = 64 ; # [doc = "< M680X Motorola 6809 mode"] pub const cs_mode_CS_MODE_M680X_6809 : cs_mode = 128 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"] pub const cs_mode_CS_MODE_M680X_6811 : cs_mode = 256 ; # [doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"] pub const cs_mode_CS_MODE_M680X_CPU12 : cs_mode = 512 ; # [doc = "< M680X Freescale/NXP HCS08 mode"] pub const cs_mode_CS_MODE_M680X_HCS08 : cs_mode = 1024 ; # [doc = "< Classic BPF mode (default)"] pub const cs_mode_CS_MODE_BPF_CLASSIC : cs_mode = 0 ; # [doc = "< Extended BPF mode"] pub const cs_mode_CS_MODE_BPF_EXTENDED : cs_mode = 1 ; # [doc = "< RISCV RV32G"] pub const cs_mode_CS_MODE_RISCV32 : cs_mode = 1 ; # [doc = "< RISCV RV64G"] pub const cs_mode_CS_MODE_RISCV64 : cs_mode = 2 ; # [doc = "< RISCV compressed instructure mode"] pub const cs_mode_CS_MODE_RISCVC : cs_mode = 4 ; # [doc = "< MOS65XXX MOS 6502"] pub const cs_mode_CS_MODE_MOS65XX_6502 : cs_mode = 2 ; # [doc = "< MOS65XXX WDC 65c02"] pub const cs_mode_CS_MODE_MOS65XX_65C02 : cs_mode = 4 ; # [doc = "< MOS65XXX WDC W65c02"] pub const cs_mode_CS_MODE_MOS65XX_W65C02 : cs_mode = 8 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m/x"] pub const cs_mode_CS_MODE_MOS65XX_65816 : cs_mode = 16 ; # [doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_M : cs_mode = 32 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_X : cs_mode = 64 ; pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_MX : cs_mode = 96 ; # [doc = "< SH2"] pub const cs_mode_CS_MODE_SH2 : cs_mode = 2 ; # [doc = "< SH2A"] pub const cs_mode_CS_MODE_SH2A : cs_mode = 4 ; # [doc = "< SH3"] pub const cs_mode_CS_MODE_SH3 : cs_mode = 8 ; # [doc = "< SH4"] pub const cs_mode_CS_MODE_SH4 : cs_mode = 16 ; # [doc = "< SH4A"] pub const cs_mode_CS_MODE_SH4A : cs_mode = 32 ; # [doc = "< w/ FPU"] pub const cs_mode_CS_MODE_SHFPU : cs_mode = 64 ; # [doc = "< w/ DSP"] pub const cs_mode_CS_MODE_SHDSP : cs_mode = 128 ; # [doc = "< Tricore 1.1"] pub const cs_mode_CS_MODE_TRICORE_110 : cs_mode = 2 ; # [doc = "< Tricore 1.2"] pub const cs_mode_CS_MODE_TRICORE_120 : cs_mode = 4 ; # [doc = "< Tricore 1.3"] pub const cs_mode_CS_MODE_TRICORE_130 : cs_mode = 8 ; # [doc = "< Tricore 1.3.1"] pub const cs_mode_CS_MODE_TRICORE_131 : cs_mode = 16 ; # [doc = "< Tricore 1.6"] pub const cs_mode_CS_MODE_TRICORE_160 : cs_mode = 32 ; # [doc = "< Tricore 1.6.1"] pub const cs_mode_CS_MODE_TRICORE_161 : cs_mode = 64 ; # [doc = "< Tricore 1.6.2"] pub const cs_mode_CS_MODE_TRICORE_162 : cs_mode = 128 ; # [doc = " Mode type"] pub type cs_mode = :: std :: os :: raw :: c_uint ; pub type cs_malloc_t = :: std :: option :: Option < unsafe extern "C" fn (size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_calloc_t = :: std :: option :: Option < unsafe extern "C" fn (nmemb : usize , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_realloc_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_free_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void) > ; pub type cs_vsnprintf_t = :: std :: option :: Option < unsafe extern "C" fn (str_ : * mut :: std :: os :: raw :: c_char , size : usize , format : * const :: std :: os :: raw :: c_char , ap : * mut __va_list_tag) -> :: std :: os :: raw :: c_int > ; # [doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mem { pub malloc : cs_malloc_t , pub calloc : cs_calloc_t , pub realloc : cs_realloc_t , pub free : cs_free_t , pub vsnprintf : cs_vsnprintf_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mem"] [:: std :: mem :: size_of :: < cs_opt_mem > () - 40usize] ; ["Alignment of cs_opt_mem"] [:: std :: mem :: align_of :: < cs_opt_mem > () - 8usize] ; ["Offset of field: cs_opt_mem::malloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , malloc) - 0usize] ; ["Offset of field: cs_opt_mem::calloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , calloc) - 8usize] ; ["Offset of field: cs_opt_mem::realloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , realloc) - 16usize] ; ["Offset of field: cs_opt_mem::free"] [:: std :: mem :: offset_of ! (cs_opt_mem , free) - 24usize] ; ["Offset of field: cs_opt_mem::vsnprintf"] [:: std :: mem :: offset_of ! (cs_opt_mem , vsnprintf) - 32usize] ; } ; # [doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mnem { # [doc = " ID of instruction to be customized."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Customized instruction mnemonic."] pub mnemonic : * const :: std :: os :: raw :: c_char , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mnem"] [:: std :: mem :: size_of :: < cs_opt_mnem > () - 16usize] ; ["Alignment of cs_opt_mnem"] [:: std :: mem :: align_of :: < cs_opt_mnem > () - 8usize] ; ["Offset of field: cs_opt_mnem::id"] [:: std :: mem :: offset_of ! (cs_opt_mnem , id) - 0usize] ; ["Offset of field: cs_opt_mnem::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_mnem , mnemonic) - 8usize] ; } ; # [repr (u32)] # [doc = " Runtime option for the disassembled engine"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_type { # [doc = "< No option specified"] CS_OPT_INVALID = 0 , # [doc = "< Assembly output syntax"] CS_OPT_SYNTAX = 1 , # [doc = "< Break down instruction structure into details"] CS_OPT_DETAIL = 2 , # [doc = "< Change engine's mode at run-time"] CS_OPT_MODE = 3 , # [doc = "< User-defined dynamic memory related functions"] CS_OPT_MEM = 4 , # [doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."] CS_OPT_SKIPDATA = 5 , # [doc = "< Setup user-defined function for SKIPDATA option"] CS_OPT_SKIPDATA_SETUP = 6 , # [doc = "< Customize instruction mnemonic"] CS_OPT_MNEMONIC = 7 , # [doc = "< print immediate operands in unsigned form"] CS_OPT_UNSIGNED = 8 , # [doc = "< ARM, prints branch immediates without offset."] CS_OPT_NO_BRANCH_OFFSET = 9 , } impl cs_opt_value { pub const CS_OPT_SYNTAX_DEFAULT : cs_opt_value = cs_opt_value :: CS_OPT_OFF ; } impl cs_opt_value { pub const CS_OPT_SYNTAX_NOREGNAME : cs_opt_value = cs_opt_value :: CS_OPT_ON ; } # [repr (u32)] # [doc = " Runtime option value (associated with option type above)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_value { # [doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."] CS_OPT_OFF = 0 , # [doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."] CS_OPT_ON = 3 , # [doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_INTEL = 1 , # [doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_ATT = 2 , # [doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_MASM = 4 , # [doc = "< MOS65XX use $ as hex prefix"] CS_OPT_SYNTAX_MOTOROLA = 5 , } # [repr (u32)] # [doc = " Common instruction operand types - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_op_type { # [doc = "< uninitialized/invalid operand."] CS_OP_INVALID = 0 , # [doc = "< Register operand."] CS_OP_REG = 1 , # [doc = "< Immediate operand."] CS_OP_IMM = 2 , # [doc = "< Memory operand. Can be ORed with another operand type."] CS_OP_MEM = 3 , # [doc = "< Floating-Point operand."] CS_OP_FP = 4 , } # [repr (u32)] # [doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_ac_type { # [doc = "< Uninitialized/invalid access type."] CS_AC_INVALID = 0 , # [doc = "< Operand read from memory or register."] CS_AC_READ = 1 , # [doc = "< Operand write to memory or register."] CS_AC_WRITE = 2 , } # [repr (u32)] # [doc = " Common instruction groups - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_group_type { # [doc = "< uninitialized/invalid group."] CS_GRP_INVALID = 0 , # [doc = "< all jump instructions (conditional+direct+indirect jumps)"] CS_GRP_JUMP = 1 , # [doc = "< all call instructions"] CS_GRP_CALL = 2 , # [doc = "< all return instructions"] CS_GRP_RET = 3 , # [doc = "< all interrupt instructions (int+syscall)"] CS_GRP_INT = 4 , # [doc = "< all interrupt return instructions"] CS_GRP_IRET = 5 , # [doc = "< all privileged instructions"] CS_GRP_PRIVILEGE = 6 , # [doc = "< all relative branching instructions"] CS_GRP_BRANCH_RELATIVE = 7 , } # [doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."] pub type cs_skipdata_cb_t = :: std :: option :: Option < unsafe extern "C" fn (code : * const u8 , code_size : usize , offset : usize , user_data : * mut :: std :: os :: raw :: c_void) -> usize > ; # [doc = " User-customized setup for SKIPDATA option"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_skipdata { # [doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."] pub mnemonic : * const :: std :: os :: raw :: c_char , # [doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes.\n TriCore: 2 bytes."] pub callback : cs_skipdata_cb_t , # [doc = " User-defined data to be passed to @callback function pointer."] pub user_data : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_skipdata"] [:: std :: mem :: size_of :: < cs_opt_skipdata > () - 24usize] ; ["Alignment of cs_opt_skipdata"] [:: std :: mem :: align_of :: < cs_opt_skipdata > () - 8usize] ; ["Offset of field: cs_opt_skipdata::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , mnemonic) - 0usize] ; ["Offset of field: cs_opt_skipdata::callback"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , callback) - 8usize] ; ["Offset of field: cs_opt_skipdata::user_data"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , user_data) - 16usize] ; } ; # [repr (u32)] # [doc = " ARM shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_shifter { ARM_SFT_INVALID = 0 , # [doc = "< shift with immediate const"] ARM_SFT_ASR = 1 , # [doc = "< shift with immediate const"] ARM_SFT_LSL = 2 , # [doc = "< shift with immediate const"] ARM_SFT_LSR = 3 , # [doc = "< shift with immediate const"] ARM_SFT_ROR = 4 , # [doc = "< shift with immediate const"] ARM_SFT_RRX = 5 , # [doc = "< shift with register"] ARM_SFT_ASR_REG = 6 , # [doc = "< shift with register"] ARM_SFT_LSL_REG = 7 , # [doc = "< shift with register"] ARM_SFT_LSR_REG = 8 , # [doc = "< shift with register"] ARM_SFT_ROR_REG = 9 , # [doc = "< shift with register"] ARM_SFT_RRX_REG = 10 , } # [repr (u32)] # [doc = " ARM condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cc { ARM_CC_INVALID = 0 , # [doc = "< Equal                      Equal"] ARM_CC_EQ = 1 , # [doc = "< Not equal                  Not equal, or unordered"] ARM_CC_NE = 2 , # [doc = "< Carry set                  >, ==, or unordered"] ARM_CC_HS = 3 , # [doc = "< Carry clear                Less than"] ARM_CC_LO = 4 , # [doc = "< Minus, negative            Less than"] ARM_CC_MI = 5 , # [doc = "< Plus, positive or zero     >, ==, or unordered"] ARM_CC_PL = 6 , # [doc = "< Overflow                   Unordered"] ARM_CC_VS = 7 , # [doc = "< No overflow                Not unordered"] ARM_CC_VC = 8 , # [doc = "< Unsigned higher            Greater than, or unordered"] ARM_CC_HI = 9 , # [doc = "< Unsigned lower or same     Less than or equal"] ARM_CC_LS = 10 , # [doc = "< Greater than or equal      Greater than or equal"] ARM_CC_GE = 11 , # [doc = "< Less than                  Less than, or unordered"] ARM_CC_LT = 12 , # [doc = "< Greater than               Greater than"] ARM_CC_GT = 13 , # [doc = "< Less than or equal         <, ==, or unordered"] ARM_CC_LE = 14 , # [doc = "< Always (unconditional)     Always (unconditional)"] ARM_CC_AL = 15 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_sysreg { # [doc = " Special registers for MSR"] ARM_SYSREG_INVALID = 0 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_C = 1 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_X = 2 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_S = 4 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_F = 8 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_C = 16 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_X = 32 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_S = 64 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_F = 128 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR = 256 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_G = 257 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQ = 258 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQG = 259 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR = 260 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_G = 261 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQG = 262 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQ = 263 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR = 264 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_G = 265 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQG = 266 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQ = 267 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR = 268 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_G = 269 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQG = 270 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQ = 271 , # [doc = " Special registers for MSR"] ARM_SYSREG_IPSR = 272 , # [doc = " Special registers for MSR"] ARM_SYSREG_EPSR = 273 , # [doc = " Special registers for MSR"] ARM_SYSREG_IEPSR = 274 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP = 275 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP = 276 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK = 277 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI = 278 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_MAX = 279 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK = 280 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL = 281 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM = 282 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM = 283 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP_NS = 284 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP_NS = 285 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM_NS = 286 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM_NS = 287 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK_NS = 288 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_NS = 289 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK_NS = 290 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL_NS = 291 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_NS = 292 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_USR = 293 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_USR = 294 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_USR = 295 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_USR = 296 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_USR = 297 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_USR = 298 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_USR = 299 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_FIQ = 300 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_FIQ = 301 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_FIQ = 302 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_FIQ = 303 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_FIQ = 304 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_FIQ = 305 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_FIQ = 306 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_IRQ = 307 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_IRQ = 308 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_SVC = 309 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_SVC = 310 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_ABT = 311 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_ABT = 312 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_UND = 313 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_UND = 314 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_MON = 315 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_MON = 316 , # [doc = " Special registers for MSR"] ARM_SYSREG_ELR_HYP = 317 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_HYP = 318 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_FIQ = 319 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_IRQ = 320 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_SVC = 321 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_ABT = 322 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_UND = 323 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_MON = 324 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_HYP = 325 , } # [repr (u32)] # [doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_mem_barrier { ARM_MB_INVALID = 0 , ARM_MB_RESERVED_0 = 1 , ARM_MB_OSHLD = 2 , ARM_MB_OSHST = 3 , ARM_MB_OSH = 4 , ARM_MB_RESERVED_4 = 5 , ARM_MB_NSHLD = 6 , ARM_MB_NSHST = 7 , ARM_MB_NSH = 8 , ARM_MB_RESERVED_8 = 9 , ARM_MB_ISHLD = 10 , ARM_MB_ISHST = 11 , ARM_MB_ISH = 12 , ARM_MB_RESERVED_12 = 13 , ARM_MB_LD = 14 , ARM_MB_ST = 15 , ARM_MB_SY = 16 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM_OP_FP = 4 , # [doc = "< C-Immediate (coprocessor registers)"] ARM_OP_CIMM = 64 , # [doc = "< P-Immediate (coprocessor registers)"] ARM_OP_PIMM = 65 , # [doc = "< operand for SETEND instruction"] ARM_OP_SETEND = 66 , # [doc = "< MSR/MRS special register operand"] ARM_OP_SYSREG = 67 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_setend_type { # [doc = "< Uninitialized."] ARM_SETEND_INVALID = 0 , # [doc = "< BE operand."] ARM_SETEND_BE = 1 , # [doc = "< LE operand"] ARM_SETEND_LE = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0 , ARM_CPSMODE_IE = 2 , ARM_CPSMODE_ID = 3 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0 , ARM_CPSFLAG_F = 1 , ARM_CPSFLAG_I = 2 , ARM_CPSFLAG_A = 4 , # [doc = "< no flag"] ARM_CPSFLAG_NONE = 16 , } # [repr (u32)] # [doc = " Data type for elements of vector instructions."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0 , ARM_VECTORDATA_I8 = 1 , ARM_VECTORDATA_I16 = 2 , ARM_VECTORDATA_I32 = 3 , ARM_VECTORDATA_I64 = 4 , ARM_VECTORDATA_S8 = 5 , ARM_VECTORDATA_S16 = 6 , ARM_VECTORDATA_S32 = 7 , ARM_VECTORDATA_S64 = 8 , ARM_VECTORDATA_U8 = 9 , ARM_VECTORDATA_U16 = 10 , ARM_VECTORDATA_U32 = 11 , ARM_VECTORDATA_U64 = 12 , ARM_VECTORDATA_P8 = 13 , ARM_VECTORDATA_F16 = 14 , ARM_VECTORDATA_F32 = 15 , ARM_VECTORDATA_F64 = 16 , ARM_VECTORDATA_F16F64 = 17 , ARM_VECTORDATA_F64F16 = 18 , ARM_VECTORDATA_F32F16 = 19 , ARM_VECTORDATA_F16F32 = 20 , ARM_VECTORDATA_F64F32 = 21 , ARM_VECTORDATA_F32F64 = 22 , ARM_VECTORDATA_S32F32 = 23 , ARM_VECTORDATA_U32F32 = 24 , ARM_VECTORDATA_F32S32 = 25 , ARM_VECTORDATA_F32U32 = 26 , ARM_VECTORDATA_F64S16 = 27 , ARM_VECTORDATA_F32S16 = 28 , ARM_VECTORDATA_F64S32 = 29 , ARM_VECTORDATA_S16F64 = 30 , ARM_VECTORDATA_S16F32 = 31 , ARM_VECTORDATA_S32F64 = 32 , ARM_VECTORDATA_U16F64 = 33 , ARM_VECTORDATA_U16F32 = 34 , ARM_VECTORDATA_U32F64 = 35 , ARM_VECTORDATA_F64U16 = 36 , ARM_VECTORDATA_F32U16 = 37 , ARM_VECTORDATA_F64U32 = 38 , ARM_VECTORDATA_F16U16 = 39 , ARM_VECTORDATA_U16F16 = 40 , ARM_VECTORDATA_F16U32 = 41 , ARM_VECTORDATA_U32F16 = 42 , } impl arm_reg { pub const ARM_REG_R13 : arm_reg = arm_reg :: ARM_REG_SP ; } impl arm_reg { pub const ARM_REG_R14 : arm_reg = arm_reg :: ARM_REG_LR ; } impl arm_reg { pub const ARM_REG_R15 : arm_reg = arm_reg :: ARM_REG_PC ; } impl arm_reg { pub const ARM_REG_SB : arm_reg = arm_reg :: ARM_REG_R9 ; } impl arm_reg { pub const ARM_REG_SL : arm_reg = arm_reg :: ARM_REG_R10 ; } impl arm_reg { pub const ARM_REG_FP : arm_reg = arm_reg :: ARM_REG_R11 ; } impl arm_reg { pub const ARM_REG_IP : arm_reg = arm_reg :: ARM_REG_R12 ; } # [repr (u32)] # [doc = " ARM registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_reg { ARM_REG_INVALID = 0 , ARM_REG_APSR = 1 , ARM_REG_APSR_NZCV = 2 , ARM_REG_CPSR = 3 , ARM_REG_FPEXC = 4 , ARM_REG_FPINST = 5 , ARM_REG_FPSCR = 6 , ARM_REG_FPSCR_NZCV = 7 , ARM_REG_FPSID = 8 , ARM_REG_ITSTATE = 9 , ARM_REG_LR = 10 , ARM_REG_PC = 11 , ARM_REG_SP = 12 , ARM_REG_SPSR = 13 , ARM_REG_D0 = 14 , ARM_REG_D1 = 15 , ARM_REG_D2 = 16 , ARM_REG_D3 = 17 , ARM_REG_D4 = 18 , ARM_REG_D5 = 19 , ARM_REG_D6 = 20 , ARM_REG_D7 = 21 , ARM_REG_D8 = 22 , ARM_REG_D9 = 23 , ARM_REG_D10 = 24 , ARM_REG_D11 = 25 , ARM_REG_D12 = 26 , ARM_REG_D13 = 27 , ARM_REG_D14 = 28 , ARM_REG_D15 = 29 , ARM_REG_D16 = 30 , ARM_REG_D17 = 31 , ARM_REG_D18 = 32 , ARM_REG_D19 = 33 , ARM_REG_D20 = 34 , ARM_REG_D21 = 35 , ARM_REG_D22 = 36 , ARM_REG_D23 = 37 , ARM_REG_D24 = 38 , ARM_REG_D25 = 39 , ARM_REG_D26 = 40 , ARM_REG_D27 = 41 , ARM_REG_D28 = 42 , ARM_REG_D29 = 43 , ARM_REG_D30 = 44 , ARM_REG_D31 = 45 , ARM_REG_FPINST2 = 46 , ARM_REG_MVFR0 = 47 , ARM_REG_MVFR1 = 48 , ARM_REG_MVFR2 = 49 , ARM_REG_Q0 = 50 , ARM_REG_Q1 = 51 , ARM_REG_Q2 = 52 , ARM_REG_Q3 = 53 , ARM_REG_Q4 = 54 , ARM_REG_Q5 = 55 , ARM_REG_Q6 = 56 , ARM_REG_Q7 = 57 , ARM_REG_Q8 = 58 , ARM_REG_Q9 = 59 , ARM_REG_Q10 = 60 , ARM_REG_Q11 = 61 , ARM_REG_Q12 = 62 , ARM_REG_Q13 = 63 , ARM_REG_Q14 = 64 , ARM_REG_Q15 = 65 , ARM_REG_R0 = 66 , ARM_REG_R1 = 67 , ARM_REG_R2 = 68 , ARM_REG_R3 = 69 , ARM_REG_R4 = 70 , ARM_REG_R5 = 71 , ARM_REG_R6 = 72 , ARM_REG_R7 = 73 , ARM_REG_R8 = 74 , ARM_REG_R9 = 75 , ARM_REG_R10 = 76 , ARM_REG_R11 = 77 , ARM_REG_R12 = 78 , ARM_REG_S0 = 79 , ARM_REG_S1 = 80 , ARM_REG_S2 = 81 , ARM_REG_S3 = 82 , ARM_REG_S4 = 83 , ARM_REG_S5 = 84 , ARM_REG_S6 = 85 , ARM_REG_S7 = 86 , ARM_REG_S8 = 87 , ARM_REG_S9 = 88 , ARM_REG_S10 = 89 , ARM_REG_S11 = 90 , ARM_REG_S12 = 91 , ARM_REG_S13 = 92 , ARM_REG_S14 = 93 , ARM_REG_S15 = 94 , ARM_REG_S16 = 95 , ARM_REG_S17 = 96 , ARM_REG_S18 = 97 , ARM_REG_S19 = 98 , ARM_REG_S20 = 99 , ARM_REG_S21 = 100 , ARM_REG_S22 = 101 , ARM_REG_S23 = 102 , ARM_REG_S24 = 103 , ARM_REG_S25 = 104 , ARM_REG_S26 = 105 , ARM_REG_S27 = 106 , ARM_REG_S28 = 107 , ARM_REG_S29 = 108 , ARM_REG_S30 = 109 , ARM_REG_S31 = 110 , ARM_REG_ENDING = 111 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm_op_mem { # [doc = "< base register"] pub base : arm_reg , # [doc = "< index register"] pub index : arm_reg , # [doc = "< scale for index register (can be 1, or -1)"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_int , # [doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"] pub lshift : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm_op_mem"] [:: std :: mem :: size_of :: < arm_op_mem > () - 20usize] ; ["Alignment of arm_op_mem"] [:: std :: mem :: align_of :: < arm_op_mem > () - 4usize] ; ["Offset of field: arm_op_mem::base"] [:: std :: mem :: offset_of ! (arm_op_mem , base) - 0usize] ; ["Offset of field: arm_op_mem::index"] [:: std :: mem :: offset_of ! (arm_op_mem , index) - 4usize] ; ["Offset of field: arm_op_mem::scale"] [:: std :: mem :: offset_of ! (arm_op_mem , scale) - 8usize] ; ["Offset of field: arm_op_mem::disp"] [:: std :: mem :: offset_of ! (arm_op_mem , disp) - 12usize] ; ["Offset of field: arm_op_mem::lshift"] [:: std :: mem :: offset_of ! (arm_op_mem , lshift) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm_op { # [doc = "< Vector Index for some vector operands (or -1 if irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , pub shift : cs_arm_op__bindgen_ty_1 , # [doc = "< operand type"] pub type_ : arm_op_type , pub __bindgen_anon_1 : cs_arm_op__bindgen_ty_2 , # [doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."] pub subtracted : bool , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"] pub neon_lane : i8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm_op__bindgen_ty_1 { pub type_ : arm_shifter , pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm_op__bindgen_ty_2 { # [doc = "< register value for REG/SYSREG operand"] pub reg : :: std :: os :: raw :: c_int , # [doc = "< immediate value for C-IMM, P-IMM or IMM operand"] pub imm : i32 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm_op_mem , # [doc = "< SETEND instruction's operand type"] pub setend : arm_setend_type , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_2 > () - 24usize] ; ["Alignment of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::setend"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , setend) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op"] [:: std :: mem :: size_of :: < cs_arm_op > () - 48usize] ; ["Alignment of cs_arm_op"] [:: std :: mem :: align_of :: < cs_arm_op > () - 8usize] ; ["Offset of field: cs_arm_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm_op , vector_index) - 0usize] ; ["Offset of field: cs_arm_op::shift"] [:: std :: mem :: offset_of ! (cs_arm_op , shift) - 4usize] ; ["Offset of field: cs_arm_op::type_"] [:: std :: mem :: offset_of ! (cs_arm_op , type_) - 12usize] ; ["Offset of field: cs_arm_op::subtracted"] [:: std :: mem :: offset_of ! (cs_arm_op , subtracted) - 40usize] ; ["Offset of field: cs_arm_op::access"] [:: std :: mem :: offset_of ! (cs_arm_op , access) - 41usize] ; ["Offset of field: cs_arm_op::neon_lane"] [:: std :: mem :: offset_of ! (cs_arm_op , neon_lane) - 42usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm { # [doc = "< User-mode registers to be loaded (for LDM/STM instructions)"] pub usermode : bool , # [doc = "< Scalar size for vector instructions"] pub vector_size : :: std :: os :: raw :: c_int , # [doc = "< Data type for elements of vector instructions"] pub vector_data : arm_vectordata_type , # [doc = "< CPS mode for CPS instruction"] pub cps_mode : arm_cpsmode_type , # [doc = "< CPS mode for CPS instruction"] pub cps_flag : arm_cpsflag_type , # [doc = "< conditional code for this insn"] pub cc : arm_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn write-back?"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = "< Option for some memory barrier instructions"] pub mem_barrier : arm_mem_barrier , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm_op ; 36usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm"] [:: std :: mem :: size_of :: < cs_arm > () - 1768usize] ; ["Alignment of cs_arm"] [:: std :: mem :: align_of :: < cs_arm > () - 8usize] ; ["Offset of field: cs_arm::usermode"] [:: std :: mem :: offset_of ! (cs_arm , usermode) - 0usize] ; ["Offset of field: cs_arm::vector_size"] [:: std :: mem :: offset_of ! (cs_arm , vector_size) - 4usize] ; ["Offset of field: cs_arm::vector_data"] [:: std :: mem :: offset_of ! (cs_arm , vector_data) - 8usize] ; ["Offset of field: cs_arm::cps_mode"] [:: std :: mem :: offset_of ! (cs_arm , cps_mode) - 12usize] ; ["Offset of field: cs_arm::cps_flag"] [:: std :: mem :: offset_of ! (cs_arm , cps_flag) - 16usize] ; ["Offset of field: cs_arm::cc"] [:: std :: mem :: offset_of ! (cs_arm , cc) - 20usize] ; ["Offset of field: cs_arm::update_flags"] [:: std :: mem :: offset_of ! (cs_arm , update_flags) - 24usize] ; ["Offset of field: cs_arm::writeback"] [:: std :: mem :: offset_of ! (cs_arm , writeback) - 25usize] ; ["Offset of field: cs_arm::post_index"] [:: std :: mem :: offset_of ! (cs_arm , post_index) - 26usize] ; ["Offset of field: cs_arm::mem_barrier"] [:: std :: mem :: offset_of ! (cs_arm , mem_barrier) - 28usize] ; ["Offset of field: cs_arm::op_count"] [:: std :: mem :: offset_of ! (cs_arm , op_count) - 32usize] ; ["Offset of field: cs_arm::operands"] [:: std :: mem :: offset_of ! (cs_arm , operands) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_arm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . post_index , self . mem_barrier , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn { ARM_INS_INVALID = 0 , ARM_INS_ADC = 1 , ARM_INS_ADD = 2 , ARM_INS_ADDW = 3 , ARM_INS_ADR = 4 , ARM_INS_AESD = 5 , ARM_INS_AESE = 6 , ARM_INS_AESIMC = 7 , ARM_INS_AESMC = 8 , ARM_INS_AND = 9 , ARM_INS_ASR = 10 , ARM_INS_B = 11 , ARM_INS_BFC = 12 , ARM_INS_BFI = 13 , ARM_INS_BIC = 14 , ARM_INS_BKPT = 15 , ARM_INS_BL = 16 , ARM_INS_BLX = 17 , ARM_INS_BLXNS = 18 , ARM_INS_BX = 19 , ARM_INS_BXJ = 20 , ARM_INS_BXNS = 21 , ARM_INS_CBNZ = 22 , ARM_INS_CBZ = 23 , ARM_INS_CDP = 24 , ARM_INS_CDP2 = 25 , ARM_INS_CLREX = 26 , ARM_INS_CLZ = 27 , ARM_INS_CMN = 28 , ARM_INS_CMP = 29 , ARM_INS_CPS = 30 , ARM_INS_CRC32B = 31 , ARM_INS_CRC32CB = 32 , ARM_INS_CRC32CH = 33 , ARM_INS_CRC32CW = 34 , ARM_INS_CRC32H = 35 , ARM_INS_CRC32W = 36 , ARM_INS_CSDB = 37 , ARM_INS_DBG = 38 , ARM_INS_DCPS1 = 39 , ARM_INS_DCPS2 = 40 , ARM_INS_DCPS3 = 41 , ARM_INS_DFB = 42 , ARM_INS_DMB = 43 , ARM_INS_DSB = 44 , ARM_INS_EOR = 45 , ARM_INS_ERET = 46 , ARM_INS_ESB = 47 , ARM_INS_FADDD = 48 , ARM_INS_FADDS = 49 , ARM_INS_FCMPZD = 50 , ARM_INS_FCMPZS = 51 , ARM_INS_FCONSTD = 52 , ARM_INS_FCONSTS = 53 , ARM_INS_FLDMDBX = 54 , ARM_INS_FLDMIAX = 55 , ARM_INS_FMDHR = 56 , ARM_INS_FMDLR = 57 , ARM_INS_FMSTAT = 58 , ARM_INS_FSTMDBX = 59 , ARM_INS_FSTMIAX = 60 , ARM_INS_FSUBD = 61 , ARM_INS_FSUBS = 62 , ARM_INS_HINT = 63 , ARM_INS_HLT = 64 , ARM_INS_HVC = 65 , ARM_INS_ISB = 66 , ARM_INS_IT = 67 , ARM_INS_LDA = 68 , ARM_INS_LDAB = 69 , ARM_INS_LDAEX = 70 , ARM_INS_LDAEXB = 71 , ARM_INS_LDAEXD = 72 , ARM_INS_LDAEXH = 73 , ARM_INS_LDAH = 74 , ARM_INS_LDC = 75 , ARM_INS_LDC2 = 76 , ARM_INS_LDC2L = 77 , ARM_INS_LDCL = 78 , ARM_INS_LDM = 79 , ARM_INS_LDMDA = 80 , ARM_INS_LDMDB = 81 , ARM_INS_LDMIB = 82 , ARM_INS_LDR = 83 , ARM_INS_LDRB = 84 , ARM_INS_LDRBT = 85 , ARM_INS_LDRD = 86 , ARM_INS_LDREX = 87 , ARM_INS_LDREXB = 88 , ARM_INS_LDREXD = 89 , ARM_INS_LDREXH = 90 , ARM_INS_LDRH = 91 , ARM_INS_LDRHT = 92 , ARM_INS_LDRSB = 93 , ARM_INS_LDRSBT = 94 , ARM_INS_LDRSH = 95 , ARM_INS_LDRSHT = 96 , ARM_INS_LDRT = 97 , ARM_INS_LSL = 98 , ARM_INS_LSR = 99 , ARM_INS_MCR = 100 , ARM_INS_MCR2 = 101 , ARM_INS_MCRR = 102 , ARM_INS_MCRR2 = 103 , ARM_INS_MLA = 104 , ARM_INS_MLS = 105 , ARM_INS_MOV = 106 , ARM_INS_MOVS = 107 , ARM_INS_MOVT = 108 , ARM_INS_MOVW = 109 , ARM_INS_MRC = 110 , ARM_INS_MRC2 = 111 , ARM_INS_MRRC = 112 , ARM_INS_MRRC2 = 113 , ARM_INS_MRS = 114 , ARM_INS_MSR = 115 , ARM_INS_MUL = 116 , ARM_INS_MVN = 117 , ARM_INS_NEG = 118 , ARM_INS_NOP = 119 , ARM_INS_ORN = 120 , ARM_INS_ORR = 121 , ARM_INS_PKHBT = 122 , ARM_INS_PKHTB = 123 , ARM_INS_PLD = 124 , ARM_INS_PLDW = 125 , ARM_INS_PLI = 126 , ARM_INS_POP = 127 , ARM_INS_PUSH = 128 , ARM_INS_QADD = 129 , ARM_INS_QADD16 = 130 , ARM_INS_QADD8 = 131 , ARM_INS_QASX = 132 , ARM_INS_QDADD = 133 , ARM_INS_QDSUB = 134 , ARM_INS_QSAX = 135 , ARM_INS_QSUB = 136 , ARM_INS_QSUB16 = 137 , ARM_INS_QSUB8 = 138 , ARM_INS_RBIT = 139 , ARM_INS_REV = 140 , ARM_INS_REV16 = 141 , ARM_INS_REVSH = 142 , ARM_INS_RFEDA = 143 , ARM_INS_RFEDB = 144 , ARM_INS_RFEIA = 145 , ARM_INS_RFEIB = 146 , ARM_INS_ROR = 147 , ARM_INS_RRX = 148 , ARM_INS_RSB = 149 , ARM_INS_RSC = 150 , ARM_INS_SADD16 = 151 , ARM_INS_SADD8 = 152 , ARM_INS_SASX = 153 , ARM_INS_SBC = 154 , ARM_INS_SBFX = 155 , ARM_INS_SDIV = 156 , ARM_INS_SEL = 157 , ARM_INS_SETEND = 158 , ARM_INS_SETPAN = 159 , ARM_INS_SEV = 160 , ARM_INS_SEVL = 161 , ARM_INS_SG = 162 , ARM_INS_SHA1C = 163 , ARM_INS_SHA1H = 164 , ARM_INS_SHA1M = 165 , ARM_INS_SHA1P = 166 , ARM_INS_SHA1SU0 = 167 , ARM_INS_SHA1SU1 = 168 , ARM_INS_SHA256H = 169 , ARM_INS_SHA256H2 = 170 , ARM_INS_SHA256SU0 = 171 , ARM_INS_SHA256SU1 = 172 , ARM_INS_SHADD16 = 173 , ARM_INS_SHADD8 = 174 , ARM_INS_SHASX = 175 , ARM_INS_SHSAX = 176 , ARM_INS_SHSUB16 = 177 , ARM_INS_SHSUB8 = 178 , ARM_INS_SMC = 179 , ARM_INS_SMLABB = 180 , ARM_INS_SMLABT = 181 , ARM_INS_SMLAD = 182 , ARM_INS_SMLADX = 183 , ARM_INS_SMLAL = 184 , ARM_INS_SMLALBB = 185 , ARM_INS_SMLALBT = 186 , ARM_INS_SMLALD = 187 , ARM_INS_SMLALDX = 188 , ARM_INS_SMLALTB = 189 , ARM_INS_SMLALTT = 190 , ARM_INS_SMLATB = 191 , ARM_INS_SMLATT = 192 , ARM_INS_SMLAWB = 193 , ARM_INS_SMLAWT = 194 , ARM_INS_SMLSD = 195 , ARM_INS_SMLSDX = 196 , ARM_INS_SMLSLD = 197 , ARM_INS_SMLSLDX = 198 , ARM_INS_SMMLA = 199 , ARM_INS_SMMLAR = 200 , ARM_INS_SMMLS = 201 , ARM_INS_SMMLSR = 202 , ARM_INS_SMMUL = 203 , ARM_INS_SMMULR = 204 , ARM_INS_SMUAD = 205 , ARM_INS_SMUADX = 206 , ARM_INS_SMULBB = 207 , ARM_INS_SMULBT = 208 , ARM_INS_SMULL = 209 , ARM_INS_SMULTB = 210 , ARM_INS_SMULTT = 211 , ARM_INS_SMULWB = 212 , ARM_INS_SMULWT = 213 , ARM_INS_SMUSD = 214 , ARM_INS_SMUSDX = 215 , ARM_INS_SRSDA = 216 , ARM_INS_SRSDB = 217 , ARM_INS_SRSIA = 218 , ARM_INS_SRSIB = 219 , ARM_INS_SSAT = 220 , ARM_INS_SSAT16 = 221 , ARM_INS_SSAX = 222 , ARM_INS_SSUB16 = 223 , ARM_INS_SSUB8 = 224 , ARM_INS_STC = 225 , ARM_INS_STC2 = 226 , ARM_INS_STC2L = 227 , ARM_INS_STCL = 228 , ARM_INS_STL = 229 , ARM_INS_STLB = 230 , ARM_INS_STLEX = 231 , ARM_INS_STLEXB = 232 , ARM_INS_STLEXD = 233 , ARM_INS_STLEXH = 234 , ARM_INS_STLH = 235 , ARM_INS_STM = 236 , ARM_INS_STMDA = 237 , ARM_INS_STMDB = 238 , ARM_INS_STMIB = 239 , ARM_INS_STR = 240 , ARM_INS_STRB = 241 , ARM_INS_STRBT = 242 , ARM_INS_STRD = 243 , ARM_INS_STREX = 244 , ARM_INS_STREXB = 245 , ARM_INS_STREXD = 246 , ARM_INS_STREXH = 247 , ARM_INS_STRH = 248 , ARM_INS_STRHT = 249 , ARM_INS_STRT = 250 , ARM_INS_SUB = 251 , ARM_INS_SUBS = 252 , ARM_INS_SUBW = 253 , ARM_INS_SVC = 254 , ARM_INS_SWP = 255 , ARM_INS_SWPB = 256 , ARM_INS_SXTAB = 257 , ARM_INS_SXTAB16 = 258 , ARM_INS_SXTAH = 259 , ARM_INS_SXTB = 260 , ARM_INS_SXTB16 = 261 , ARM_INS_SXTH = 262 , ARM_INS_TBB = 263 , ARM_INS_TBH = 264 , ARM_INS_TEQ = 265 , ARM_INS_TRAP = 266 , ARM_INS_TSB = 267 , ARM_INS_TST = 268 , ARM_INS_TT = 269 , ARM_INS_TTA = 270 , ARM_INS_TTAT = 271 , ARM_INS_TTT = 272 , ARM_INS_UADD16 = 273 , ARM_INS_UADD8 = 274 , ARM_INS_UASX = 275 , ARM_INS_UBFX = 276 , ARM_INS_UDF = 277 , ARM_INS_UDIV = 278 , ARM_INS_UHADD16 = 279 , ARM_INS_UHADD8 = 280 , ARM_INS_UHASX = 281 , ARM_INS_UHSAX = 282 , ARM_INS_UHSUB16 = 283 , ARM_INS_UHSUB8 = 284 , ARM_INS_UMAAL = 285 , ARM_INS_UMLAL = 286 , ARM_INS_UMULL = 287 , ARM_INS_UQADD16 = 288 , ARM_INS_UQADD8 = 289 , ARM_INS_UQASX = 290 , ARM_INS_UQSAX = 291 , ARM_INS_UQSUB16 = 292 , ARM_INS_UQSUB8 = 293 , ARM_INS_USAD8 = 294 , ARM_INS_USADA8 = 295 , ARM_INS_USAT = 296 , ARM_INS_USAT16 = 297 , ARM_INS_USAX = 298 , ARM_INS_USUB16 = 299 , ARM_INS_USUB8 = 300 , ARM_INS_UXTAB = 301 , ARM_INS_UXTAB16 = 302 , ARM_INS_UXTAH = 303 , ARM_INS_UXTB = 304 , ARM_INS_UXTB16 = 305 , ARM_INS_UXTH = 306 , ARM_INS_VABA = 307 , ARM_INS_VABAL = 308 , ARM_INS_VABD = 309 , ARM_INS_VABDL = 310 , ARM_INS_VABS = 311 , ARM_INS_VACGE = 312 , ARM_INS_VACGT = 313 , ARM_INS_VACLE = 314 , ARM_INS_VACLT = 315 , ARM_INS_VADD = 316 , ARM_INS_VADDHN = 317 , ARM_INS_VADDL = 318 , ARM_INS_VADDW = 319 , ARM_INS_VAND = 320 , ARM_INS_VBIC = 321 , ARM_INS_VBIF = 322 , ARM_INS_VBIT = 323 , ARM_INS_VBSL = 324 , ARM_INS_VCADD = 325 , ARM_INS_VCEQ = 326 , ARM_INS_VCGE = 327 , ARM_INS_VCGT = 328 , ARM_INS_VCLE = 329 , ARM_INS_VCLS = 330 , ARM_INS_VCLT = 331 , ARM_INS_VCLZ = 332 , ARM_INS_VCMLA = 333 , ARM_INS_VCMP = 334 , ARM_INS_VCMPE = 335 , ARM_INS_VCNT = 336 , ARM_INS_VCVT = 337 , ARM_INS_VCVTA = 338 , ARM_INS_VCVTB = 339 , ARM_INS_VCVTM = 340 , ARM_INS_VCVTN = 341 , ARM_INS_VCVTP = 342 , ARM_INS_VCVTR = 343 , ARM_INS_VCVTT = 344 , ARM_INS_VDIV = 345 , ARM_INS_VDUP = 346 , ARM_INS_VEOR = 347 , ARM_INS_VEXT = 348 , ARM_INS_VFMA = 349 , ARM_INS_VFMS = 350 , ARM_INS_VFNMA = 351 , ARM_INS_VFNMS = 352 , ARM_INS_VHADD = 353 , ARM_INS_VHSUB = 354 , ARM_INS_VINS = 355 , ARM_INS_VJCVT = 356 , ARM_INS_VLD1 = 357 , ARM_INS_VLD2 = 358 , ARM_INS_VLD3 = 359 , ARM_INS_VLD4 = 360 , ARM_INS_VLDMDB = 361 , ARM_INS_VLDMIA = 362 , ARM_INS_VLDR = 363 , ARM_INS_VLLDM = 364 , ARM_INS_VLSTM = 365 , ARM_INS_VMAX = 366 , ARM_INS_VMAXNM = 367 , ARM_INS_VMIN = 368 , ARM_INS_VMINNM = 369 , ARM_INS_VMLA = 370 , ARM_INS_VMLAL = 371 , ARM_INS_VMLS = 372 , ARM_INS_VMLSL = 373 , ARM_INS_VMOV = 374 , ARM_INS_VMOVL = 375 , ARM_INS_VMOVN = 376 , ARM_INS_VMOVX = 377 , ARM_INS_VMRS = 378 , ARM_INS_VMSR = 379 , ARM_INS_VMUL = 380 , ARM_INS_VMULL = 381 , ARM_INS_VMVN = 382 , ARM_INS_VNEG = 383 , ARM_INS_VNMLA = 384 , ARM_INS_VNMLS = 385 , ARM_INS_VNMUL = 386 , ARM_INS_VORN = 387 , ARM_INS_VORR = 388 , ARM_INS_VPADAL = 389 , ARM_INS_VPADD = 390 , ARM_INS_VPADDL = 391 , ARM_INS_VPMAX = 392 , ARM_INS_VPMIN = 393 , ARM_INS_VPOP = 394 , ARM_INS_VPUSH = 395 , ARM_INS_VQABS = 396 , ARM_INS_VQADD = 397 , ARM_INS_VQDMLAL = 398 , ARM_INS_VQDMLSL = 399 , ARM_INS_VQDMULH = 400 , ARM_INS_VQDMULL = 401 , ARM_INS_VQMOVN = 402 , ARM_INS_VQMOVUN = 403 , ARM_INS_VQNEG = 404 , ARM_INS_VQRDMLAH = 405 , ARM_INS_VQRDMLSH = 406 , ARM_INS_VQRDMULH = 407 , ARM_INS_VQRSHL = 408 , ARM_INS_VQRSHRN = 409 , ARM_INS_VQRSHRUN = 410 , ARM_INS_VQSHL = 411 , ARM_INS_VQSHLU = 412 , ARM_INS_VQSHRN = 413 , ARM_INS_VQSHRUN = 414 , ARM_INS_VQSUB = 415 , ARM_INS_VRADDHN = 416 , ARM_INS_VRECPE = 417 , ARM_INS_VRECPS = 418 , ARM_INS_VREV16 = 419 , ARM_INS_VREV32 = 420 , ARM_INS_VREV64 = 421 , ARM_INS_VRHADD = 422 , ARM_INS_VRINTA = 423 , ARM_INS_VRINTM = 424 , ARM_INS_VRINTN = 425 , ARM_INS_VRINTP = 426 , ARM_INS_VRINTR = 427 , ARM_INS_VRINTX = 428 , ARM_INS_VRINTZ = 429 , ARM_INS_VRSHL = 430 , ARM_INS_VRSHR = 431 , ARM_INS_VRSHRN = 432 , ARM_INS_VRSQRTE = 433 , ARM_INS_VRSQRTS = 434 , ARM_INS_VRSRA = 435 , ARM_INS_VRSUBHN = 436 , ARM_INS_VSDOT = 437 , ARM_INS_VSELEQ = 438 , ARM_INS_VSELGE = 439 , ARM_INS_VSELGT = 440 , ARM_INS_VSELVS = 441 , ARM_INS_VSHL = 442 , ARM_INS_VSHLL = 443 , ARM_INS_VSHR = 444 , ARM_INS_VSHRN = 445 , ARM_INS_VSLI = 446 , ARM_INS_VSQRT = 447 , ARM_INS_VSRA = 448 , ARM_INS_VSRI = 449 , ARM_INS_VST1 = 450 , ARM_INS_VST2 = 451 , ARM_INS_VST3 = 452 , ARM_INS_VST4 = 453 , ARM_INS_VSTMDB = 454 , ARM_INS_VSTMIA = 455 , ARM_INS_VSTR = 456 , ARM_INS_VSUB = 457 , ARM_INS_VSUBHN = 458 , ARM_INS_VSUBL = 459 , ARM_INS_VSUBW = 460 , ARM_INS_VSWP = 461 , ARM_INS_VTBL = 462 , ARM_INS_VTBX = 463 , ARM_INS_VTRN = 464 , ARM_INS_VTST = 465 , ARM_INS_VUDOT = 466 , ARM_INS_VUZP = 467 , ARM_INS_VZIP = 468 , ARM_INS_WFE = 469 , ARM_INS_WFI = 470 , ARM_INS_YIELD = 471 , ARM_INS_ENDING = 472 , } # [repr (u32)] # [doc = " Group of ARM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] ARM_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] ARM_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM_GRP_BRANCH_RELATIVE = 7 , ARM_GRP_CRYPTO = 128 , ARM_GRP_DATABARRIER = 129 , ARM_GRP_DIVIDE = 130 , ARM_GRP_FPARMV8 = 131 , ARM_GRP_MULTPRO = 132 , ARM_GRP_NEON = 133 , ARM_GRP_T2EXTRACTPACK = 134 , ARM_GRP_THUMB2DSP = 135 , ARM_GRP_TRUSTZONE = 136 , ARM_GRP_V4T = 137 , ARM_GRP_V5T = 138 , ARM_GRP_V5TE = 139 , ARM_GRP_V6 = 140 , ARM_GRP_V6T2 = 141 , ARM_GRP_V7 = 142 , ARM_GRP_V8 = 143 , ARM_GRP_VFP2 = 144 , ARM_GRP_VFP3 = 145 , ARM_GRP_VFP4 = 146 , ARM_GRP_ARM = 147 , ARM_GRP_MCLASS = 148 , ARM_GRP_NOTMCLASS = 149 , ARM_GRP_THUMB = 150 , ARM_GRP_THUMB1ONLY = 151 , ARM_GRP_THUMB2 = 152 , ARM_GRP_PREV8 = 153 , ARM_GRP_FPVMLX = 154 , ARM_GRP_MULOPS = 155 , ARM_GRP_CRC = 156 , ARM_GRP_DPVFP = 157 , ARM_GRP_V6M = 158 , ARM_GRP_VIRTUALIZATION = 159 , ARM_GRP_ENDING = 160 , } # [repr (u32)] # [doc = " ARM64 shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_shifter { ARM64_SFT_INVALID = 0 , ARM64_SFT_LSL = 1 , ARM64_SFT_MSL = 2 , ARM64_SFT_LSR = 3 , ARM64_SFT_ASR = 4 , ARM64_SFT_ROR = 5 , } # [repr (u32)] # [doc = " ARM64 extender type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_extender { ARM64_EXT_INVALID = 0 , ARM64_EXT_UXTB = 1 , ARM64_EXT_UXTH = 2 , ARM64_EXT_UXTW = 3 , ARM64_EXT_UXTX = 4 , ARM64_EXT_SXTB = 5 , ARM64_EXT_SXTH = 6 , ARM64_EXT_SXTW = 7 , ARM64_EXT_SXTX = 8 , } # [repr (u32)] # [doc = " ARM64 condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_cc { ARM64_CC_INVALID = 0 , # [doc = "< Equal"] ARM64_CC_EQ = 1 , # [doc = "< Not equal:                 Not equal, or unordered"] ARM64_CC_NE = 2 , # [doc = "< Unsigned higher or same:   >, ==, or unordered"] ARM64_CC_HS = 3 , # [doc = "< Unsigned lower or same:    Less than"] ARM64_CC_LO = 4 , # [doc = "< Minus, negative:           Less than"] ARM64_CC_MI = 5 , # [doc = "< Plus, positive or zero:    >, ==, or unordered"] ARM64_CC_PL = 6 , # [doc = "< Overflow:                  Unordered"] ARM64_CC_VS = 7 , # [doc = "< No overflow:               Ordered"] ARM64_CC_VC = 8 , # [doc = "< Unsigned higher:           Greater than, or unordered"] ARM64_CC_HI = 9 , # [doc = "< Unsigned lower or same:    Less than or equal"] ARM64_CC_LS = 10 , # [doc = "< Greater than or equal:     Greater than or equal"] ARM64_CC_GE = 11 , # [doc = "< Less than:                 Less than, or unordered"] ARM64_CC_LT = 12 , # [doc = "< Signed greater than:       Greater than"] ARM64_CC_GT = 13 , # [doc = "< Signed less than or equal: <, ==, or unordered"] ARM64_CC_LE = 14 , # [doc = "< Always (unconditional):    Always (unconditional)"] ARM64_CC_AL = 15 , # [doc = "< Always (unconditional):   Always (unconditional)"] ARM64_CC_NV = 16 , } impl arm64_sysreg { pub const ARM64_SYSREG_DBGDTRTX_EL0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_DBGDTRRX_EL0 ; } impl arm64_sysreg { pub const ARM64_SYSREG_TRCEXTINSELR0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TRCEXTINSELR ; } impl arm64_sysreg { pub const ARM64_SYSREG_VSCTLR_EL2 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TTBR0_EL2 ; } # [repr (u32)] # [doc = " System registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sysreg { ARM64_SYSREG_INVALID = 0 , ARM64_SYSREG_ACCDATA_EL1 = 50821 , ARM64_SYSREG_ACTLR_EL1 = 49281 , ARM64_SYSREG_ACTLR_EL2 = 57473 , ARM64_SYSREG_ACTLR_EL3 = 61569 , ARM64_SYSREG_AFSR0_EL1 = 49800 , ARM64_SYSREG_AFSR0_EL12 = 60040 , ARM64_SYSREG_AFSR0_EL2 = 57992 , ARM64_SYSREG_AFSR0_EL3 = 62088 , ARM64_SYSREG_AFSR1_EL1 = 49801 , ARM64_SYSREG_AFSR1_EL12 = 60041 , ARM64_SYSREG_AFSR1_EL2 = 57993 , ARM64_SYSREG_AFSR1_EL3 = 62089 , ARM64_SYSREG_AIDR_EL1 = 51207 , ARM64_SYSREG_AMAIR_EL1 = 50456 , ARM64_SYSREG_AMAIR_EL12 = 60696 , ARM64_SYSREG_AMAIR_EL2 = 58648 , ARM64_SYSREG_AMAIR_EL3 = 62744 , ARM64_SYSREG_AMCFGR_EL0 = 56977 , ARM64_SYSREG_AMCGCR_EL0 = 56978 , ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980 , ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984 , ARM64_SYSREG_AMCNTENSET0_EL0 = 56981 , ARM64_SYSREG_AMCNTENSET1_EL0 = 56985 , ARM64_SYSREG_AMCR_EL0 = 56976 , ARM64_SYSREG_AMEVCNTR00_EL0 = 56992 , ARM64_SYSREG_AMEVCNTR01_EL0 = 56993 , ARM64_SYSREG_AMEVCNTR02_EL0 = 56994 , ARM64_SYSREG_AMEVCNTR03_EL0 = 56995 , ARM64_SYSREG_AMEVCNTR10_EL0 = 57056 , ARM64_SYSREG_AMEVCNTR110_EL0 = 57066 , ARM64_SYSREG_AMEVCNTR111_EL0 = 57067 , ARM64_SYSREG_AMEVCNTR112_EL0 = 57068 , ARM64_SYSREG_AMEVCNTR113_EL0 = 57069 , ARM64_SYSREG_AMEVCNTR114_EL0 = 57070 , ARM64_SYSREG_AMEVCNTR115_EL0 = 57071 , ARM64_SYSREG_AMEVCNTR11_EL0 = 57057 , ARM64_SYSREG_AMEVCNTR12_EL0 = 57058 , ARM64_SYSREG_AMEVCNTR13_EL0 = 57059 , ARM64_SYSREG_AMEVCNTR14_EL0 = 57060 , ARM64_SYSREG_AMEVCNTR15_EL0 = 57061 , ARM64_SYSREG_AMEVCNTR16_EL0 = 57062 , ARM64_SYSREG_AMEVCNTR17_EL0 = 57063 , ARM64_SYSREG_AMEVCNTR18_EL0 = 57064 , ARM64_SYSREG_AMEVCNTR19_EL0 = 57065 , ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 59072 , ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 59082 , ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 59083 , ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 59084 , ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 59085 , ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 59086 , ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 59087 , ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 59073 , ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 59074 , ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 59075 , ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 59076 , ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 59077 , ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 59078 , ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 59079 , ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 59080 , ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 59081 , ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 59088 , ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 59098 , ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 59099 , ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 59100 , ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 59101 , ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 59102 , ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 59103 , ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 59089 , ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 59090 , ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 59091 , ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 59092 , ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 59093 , ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 59094 , ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 59095 , ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 59096 , ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 59097 , ARM64_SYSREG_AMEVTYPER00_EL0 = 57008 , ARM64_SYSREG_AMEVTYPER01_EL0 = 57009 , ARM64_SYSREG_AMEVTYPER02_EL0 = 57010 , ARM64_SYSREG_AMEVTYPER03_EL0 = 57011 , ARM64_SYSREG_AMEVTYPER10_EL0 = 57072 , ARM64_SYSREG_AMEVTYPER110_EL0 = 57082 , ARM64_SYSREG_AMEVTYPER111_EL0 = 57083 , ARM64_SYSREG_AMEVTYPER112_EL0 = 57084 , ARM64_SYSREG_AMEVTYPER113_EL0 = 57085 , ARM64_SYSREG_AMEVTYPER114_EL0 = 57086 , ARM64_SYSREG_AMEVTYPER115_EL0 = 57087 , ARM64_SYSREG_AMEVTYPER11_EL0 = 57073 , ARM64_SYSREG_AMEVTYPER12_EL0 = 57074 , ARM64_SYSREG_AMEVTYPER13_EL0 = 57075 , ARM64_SYSREG_AMEVTYPER14_EL0 = 57076 , ARM64_SYSREG_AMEVTYPER15_EL0 = 57077 , ARM64_SYSREG_AMEVTYPER16_EL0 = 57078 , ARM64_SYSREG_AMEVTYPER17_EL0 = 57079 , ARM64_SYSREG_AMEVTYPER18_EL0 = 57080 , ARM64_SYSREG_AMEVTYPER19_EL0 = 57081 , ARM64_SYSREG_AMUSERENR_EL0 = 56979 , ARM64_SYSREG_APDAKEYHI_EL1 = 49425 , ARM64_SYSREG_APDAKEYLO_EL1 = 49424 , ARM64_SYSREG_APDBKEYHI_EL1 = 49427 , ARM64_SYSREG_APDBKEYLO_EL1 = 49426 , ARM64_SYSREG_APGAKEYHI_EL1 = 49433 , ARM64_SYSREG_APGAKEYLO_EL1 = 49432 , ARM64_SYSREG_APIAKEYHI_EL1 = 49417 , ARM64_SYSREG_APIAKEYLO_EL1 = 49416 , ARM64_SYSREG_APIBKEYHI_EL1 = 49419 , ARM64_SYSREG_APIBKEYLO_EL1 = 49418 , ARM64_SYSREG_BRBCR_EL1 = 35968 , ARM64_SYSREG_BRBCR_EL12 = 44160 , ARM64_SYSREG_BRBCR_EL2 = 42112 , ARM64_SYSREG_BRBFCR_EL1 = 35969 , ARM64_SYSREG_BRBIDR0_EL1 = 35984 , ARM64_SYSREG_BRBINF0_EL1 = 35840 , ARM64_SYSREG_BRBINF10_EL1 = 35920 , ARM64_SYSREG_BRBINF11_EL1 = 35928 , ARM64_SYSREG_BRBINF12_EL1 = 35936 , ARM64_SYSREG_BRBINF13_EL1 = 35944 , ARM64_SYSREG_BRBINF14_EL1 = 35952 , ARM64_SYSREG_BRBINF15_EL1 = 35960 , ARM64_SYSREG_BRBINF16_EL1 = 35844 , ARM64_SYSREG_BRBINF17_EL1 = 35852 , ARM64_SYSREG_BRBINF18_EL1 = 35860 , ARM64_SYSREG_BRBINF19_EL1 = 35868 , ARM64_SYSREG_BRBINF1_EL1 = 35848 , ARM64_SYSREG_BRBINF20_EL1 = 35876 , ARM64_SYSREG_BRBINF21_EL1 = 35884 , ARM64_SYSREG_BRBINF22_EL1 = 35892 , ARM64_SYSREG_BRBINF23_EL1 = 35900 , ARM64_SYSREG_BRBINF24_EL1 = 35908 , ARM64_SYSREG_BRBINF25_EL1 = 35916 , ARM64_SYSREG_BRBINF26_EL1 = 35924 , ARM64_SYSREG_BRBINF27_EL1 = 35932 , ARM64_SYSREG_BRBINF28_EL1 = 35940 , ARM64_SYSREG_BRBINF29_EL1 = 35948 , ARM64_SYSREG_BRBINF2_EL1 = 35856 , ARM64_SYSREG_BRBINF30_EL1 = 35956 , ARM64_SYSREG_BRBINF31_EL1 = 35964 , ARM64_SYSREG_BRBINF3_EL1 = 35864 , ARM64_SYSREG_BRBINF4_EL1 = 35872 , ARM64_SYSREG_BRBINF5_EL1 = 35880 , ARM64_SYSREG_BRBINF6_EL1 = 35888 , ARM64_SYSREG_BRBINF7_EL1 = 35896 , ARM64_SYSREG_BRBINF8_EL1 = 35904 , ARM64_SYSREG_BRBINF9_EL1 = 35912 , ARM64_SYSREG_BRBINFINJ_EL1 = 35976 , ARM64_SYSREG_BRBSRC0_EL1 = 35841 , ARM64_SYSREG_BRBSRC10_EL1 = 35921 , ARM64_SYSREG_BRBSRC11_EL1 = 35929 , ARM64_SYSREG_BRBSRC12_EL1 = 35937 , ARM64_SYSREG_BRBSRC13_EL1 = 35945 , ARM64_SYSREG_BRBSRC14_EL1 = 35953 , ARM64_SYSREG_BRBSRC15_EL1 = 35961 , ARM64_SYSREG_BRBSRC16_EL1 = 35845 , ARM64_SYSREG_BRBSRC17_EL1 = 35853 , ARM64_SYSREG_BRBSRC18_EL1 = 35861 , ARM64_SYSREG_BRBSRC19_EL1 = 35869 , ARM64_SYSREG_BRBSRC1_EL1 = 35849 , ARM64_SYSREG_BRBSRC20_EL1 = 35877 , ARM64_SYSREG_BRBSRC21_EL1 = 35885 , ARM64_SYSREG_BRBSRC22_EL1 = 35893 , ARM64_SYSREG_BRBSRC23_EL1 = 35901 , ARM64_SYSREG_BRBSRC24_EL1 = 35909 , ARM64_SYSREG_BRBSRC25_EL1 = 35917 , ARM64_SYSREG_BRBSRC26_EL1 = 35925 , ARM64_SYSREG_BRBSRC27_EL1 = 35933 , ARM64_SYSREG_BRBSRC28_EL1 = 35941 , ARM64_SYSREG_BRBSRC29_EL1 = 35949 , ARM64_SYSREG_BRBSRC2_EL1 = 35857 , ARM64_SYSREG_BRBSRC30_EL1 = 35957 , ARM64_SYSREG_BRBSRC31_EL1 = 35965 , ARM64_SYSREG_BRBSRC3_EL1 = 35865 , ARM64_SYSREG_BRBSRC4_EL1 = 35873 , ARM64_SYSREG_BRBSRC5_EL1 = 35881 , ARM64_SYSREG_BRBSRC6_EL1 = 35889 , ARM64_SYSREG_BRBSRC7_EL1 = 35897 , ARM64_SYSREG_BRBSRC8_EL1 = 35905 , ARM64_SYSREG_BRBSRC9_EL1 = 35913 , ARM64_SYSREG_BRBSRCINJ_EL1 = 35977 , ARM64_SYSREG_BRBTGT0_EL1 = 35842 , ARM64_SYSREG_BRBTGT10_EL1 = 35922 , ARM64_SYSREG_BRBTGT11_EL1 = 35930 , ARM64_SYSREG_BRBTGT12_EL1 = 35938 , ARM64_SYSREG_BRBTGT13_EL1 = 35946 , ARM64_SYSREG_BRBTGT14_EL1 = 35954 , ARM64_SYSREG_BRBTGT15_EL1 = 35962 , ARM64_SYSREG_BRBTGT16_EL1 = 35846 , ARM64_SYSREG_BRBTGT17_EL1 = 35854 , ARM64_SYSREG_BRBTGT18_EL1 = 35862 , ARM64_SYSREG_BRBTGT19_EL1 = 35870 , ARM64_SYSREG_BRBTGT1_EL1 = 35850 , ARM64_SYSREG_BRBTGT20_EL1 = 35878 , ARM64_SYSREG_BRBTGT21_EL1 = 35886 , ARM64_SYSREG_BRBTGT22_EL1 = 35894 , ARM64_SYSREG_BRBTGT23_EL1 = 35902 , ARM64_SYSREG_BRBTGT24_EL1 = 35910 , ARM64_SYSREG_BRBTGT25_EL1 = 35918 , ARM64_SYSREG_BRBTGT26_EL1 = 35926 , ARM64_SYSREG_BRBTGT27_EL1 = 35934 , ARM64_SYSREG_BRBTGT28_EL1 = 35942 , ARM64_SYSREG_BRBTGT29_EL1 = 35950 , ARM64_SYSREG_BRBTGT2_EL1 = 35858 , ARM64_SYSREG_BRBTGT30_EL1 = 35958 , ARM64_SYSREG_BRBTGT31_EL1 = 35966 , ARM64_SYSREG_BRBTGT3_EL1 = 35866 , ARM64_SYSREG_BRBTGT4_EL1 = 35874 , ARM64_SYSREG_BRBTGT5_EL1 = 35882 , ARM64_SYSREG_BRBTGT6_EL1 = 35890 , ARM64_SYSREG_BRBTGT7_EL1 = 35898 , ARM64_SYSREG_BRBTGT8_EL1 = 35906 , ARM64_SYSREG_BRBTGT9_EL1 = 35914 , ARM64_SYSREG_BRBTGTINJ_EL1 = 35978 , ARM64_SYSREG_BRBTS_EL1 = 35970 , ARM64_SYSREG_CCSIDR2_EL1 = 51202 , ARM64_SYSREG_CCSIDR_EL1 = 51200 , ARM64_SYSREG_CLIDR_EL1 = 51201 , ARM64_SYSREG_CNTFRQ_EL0 = 57088 , ARM64_SYSREG_CNTHCTL_EL2 = 59144 , ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177 , ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178 , ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176 , ARM64_SYSREG_CNTHP_CTL_EL2 = 59153 , ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154 , ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152 , ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169 , ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170 , ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168 , ARM64_SYSREG_CNTHV_CTL_EL2 = 59161 , ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162 , ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160 , ARM64_SYSREG_CNTISCALE_EL2 = 59141 , ARM64_SYSREG_CNTKCTL_EL1 = 50952 , ARM64_SYSREG_CNTKCTL_EL12 = 61192 , ARM64_SYSREG_CNTPCTSS_EL0 = 57093 , ARM64_SYSREG_CNTPCT_EL0 = 57089 , ARM64_SYSREG_CNTPOFF_EL2 = 59142 , ARM64_SYSREG_CNTPS_CTL_EL1 = 65297 , ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298 , ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296 , ARM64_SYSREG_CNTP_CTL_EL0 = 57105 , ARM64_SYSREG_CNTP_CTL_EL02 = 61201 , ARM64_SYSREG_CNTP_CVAL_EL0 = 57106 , ARM64_SYSREG_CNTP_CVAL_EL02 = 61202 , ARM64_SYSREG_CNTP_TVAL_EL0 = 57104 , ARM64_SYSREG_CNTP_TVAL_EL02 = 61200 , ARM64_SYSREG_CNTSCALE_EL2 = 59140 , ARM64_SYSREG_CNTVCTSS_EL0 = 57094 , ARM64_SYSREG_CNTVCT_EL0 = 57090 , ARM64_SYSREG_CNTVFRQ_EL2 = 59143 , ARM64_SYSREG_CNTVOFF_EL2 = 59139 , ARM64_SYSREG_CNTV_CTL_EL0 = 57113 , ARM64_SYSREG_CNTV_CTL_EL02 = 61209 , ARM64_SYSREG_CNTV_CVAL_EL0 = 57114 , ARM64_SYSREG_CNTV_CVAL_EL02 = 61210 , ARM64_SYSREG_CNTV_TVAL_EL0 = 57112 , ARM64_SYSREG_CNTV_TVAL_EL02 = 61208 , ARM64_SYSREG_CONTEXTIDR_EL1 = 50817 , ARM64_SYSREG_CONTEXTIDR_EL12 = 61057 , ARM64_SYSREG_CONTEXTIDR_EL2 = 59009 , ARM64_SYSREG_CPACR_EL1 = 49282 , ARM64_SYSREG_CPACR_EL12 = 59522 , ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424 , ARM64_SYSREG_CPTR_EL2 = 57482 , ARM64_SYSREG_CPTR_EL3 = 61578 , ARM64_SYSREG_CSSELR_EL1 = 53248 , ARM64_SYSREG_CTR_EL0 = 55297 , ARM64_SYSREG_CURRENTEL = 49682 , ARM64_SYSREG_DACR32_EL2 = 57728 , ARM64_SYSREG_DAIF = 55825 , ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782 , ARM64_SYSREG_DBGBCR0_EL1 = 32773 , ARM64_SYSREG_DBGBCR10_EL1 = 32853 , ARM64_SYSREG_DBGBCR11_EL1 = 32861 , ARM64_SYSREG_DBGBCR12_EL1 = 32869 , ARM64_SYSREG_DBGBCR13_EL1 = 32877 , ARM64_SYSREG_DBGBCR14_EL1 = 32885 , ARM64_SYSREG_DBGBCR15_EL1 = 32893 , ARM64_SYSREG_DBGBCR1_EL1 = 32781 , ARM64_SYSREG_DBGBCR2_EL1 = 32789 , ARM64_SYSREG_DBGBCR3_EL1 = 32797 , ARM64_SYSREG_DBGBCR4_EL1 = 32805 , ARM64_SYSREG_DBGBCR5_EL1 = 32813 , ARM64_SYSREG_DBGBCR6_EL1 = 32821 , ARM64_SYSREG_DBGBCR7_EL1 = 32829 , ARM64_SYSREG_DBGBCR8_EL1 = 32837 , ARM64_SYSREG_DBGBCR9_EL1 = 32845 , ARM64_SYSREG_DBGBVR0_EL1 = 32772 , ARM64_SYSREG_DBGBVR10_EL1 = 32852 , ARM64_SYSREG_DBGBVR11_EL1 = 32860 , ARM64_SYSREG_DBGBVR12_EL1 = 32868 , ARM64_SYSREG_DBGBVR13_EL1 = 32876 , ARM64_SYSREG_DBGBVR14_EL1 = 32884 , ARM64_SYSREG_DBGBVR15_EL1 = 32892 , ARM64_SYSREG_DBGBVR1_EL1 = 32780 , ARM64_SYSREG_DBGBVR2_EL1 = 32788 , ARM64_SYSREG_DBGBVR3_EL1 = 32796 , ARM64_SYSREG_DBGBVR4_EL1 = 32804 , ARM64_SYSREG_DBGBVR5_EL1 = 32812 , ARM64_SYSREG_DBGBVR6_EL1 = 32820 , ARM64_SYSREG_DBGBVR7_EL1 = 32828 , ARM64_SYSREG_DBGBVR8_EL1 = 32836 , ARM64_SYSREG_DBGBVR9_EL1 = 32844 , ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742 , ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734 , ARM64_SYSREG_DBGDTRRX_EL0 = 38952 , ARM64_SYSREG_DBGDTR_EL0 = 38944 , ARM64_SYSREG_DBGPRCR_EL1 = 32932 , ARM64_SYSREG_DBGVCR32_EL2 = 41016 , ARM64_SYSREG_DBGWCR0_EL1 = 32775 , ARM64_SYSREG_DBGWCR10_EL1 = 32855 , ARM64_SYSREG_DBGWCR11_EL1 = 32863 , ARM64_SYSREG_DBGWCR12_EL1 = 32871 , ARM64_SYSREG_DBGWCR13_EL1 = 32879 , ARM64_SYSREG_DBGWCR14_EL1 = 32887 , ARM64_SYSREG_DBGWCR15_EL1 = 32895 , ARM64_SYSREG_DBGWCR1_EL1 = 32783 , ARM64_SYSREG_DBGWCR2_EL1 = 32791 , ARM64_SYSREG_DBGWCR3_EL1 = 32799 , ARM64_SYSREG_DBGWCR4_EL1 = 32807 , ARM64_SYSREG_DBGWCR5_EL1 = 32815 , ARM64_SYSREG_DBGWCR6_EL1 = 32823 , ARM64_SYSREG_DBGWCR7_EL1 = 32831 , ARM64_SYSREG_DBGWCR8_EL1 = 32839 , ARM64_SYSREG_DBGWCR9_EL1 = 32847 , ARM64_SYSREG_DBGWVR0_EL1 = 32774 , ARM64_SYSREG_DBGWVR10_EL1 = 32854 , ARM64_SYSREG_DBGWVR11_EL1 = 32862 , ARM64_SYSREG_DBGWVR12_EL1 = 32870 , ARM64_SYSREG_DBGWVR13_EL1 = 32878 , ARM64_SYSREG_DBGWVR14_EL1 = 32886 , ARM64_SYSREG_DBGWVR15_EL1 = 32894 , ARM64_SYSREG_DBGWVR1_EL1 = 32782 , ARM64_SYSREG_DBGWVR2_EL1 = 32790 , ARM64_SYSREG_DBGWVR3_EL1 = 32798 , ARM64_SYSREG_DBGWVR4_EL1 = 32806 , ARM64_SYSREG_DBGWVR5_EL1 = 32814 , ARM64_SYSREG_DBGWVR6_EL1 = 32822 , ARM64_SYSREG_DBGWVR7_EL1 = 32830 , ARM64_SYSREG_DBGWVR8_EL1 = 32838 , ARM64_SYSREG_DBGWVR9_EL1 = 32846 , ARM64_SYSREG_DCZID_EL0 = 55303 , ARM64_SYSREG_DISR_EL1 = 50697 , ARM64_SYSREG_DIT = 55829 , ARM64_SYSREG_DLR_EL0 = 55849 , ARM64_SYSREG_DSPSR_EL0 = 55848 , ARM64_SYSREG_ELR_EL1 = 49665 , ARM64_SYSREG_ELR_EL12 = 59905 , ARM64_SYSREG_ELR_EL2 = 57857 , ARM64_SYSREG_ELR_EL3 = 61953 , ARM64_SYSREG_ERRIDR_EL1 = 49816 , ARM64_SYSREG_ERRSELR_EL1 = 49817 , ARM64_SYSREG_ERXADDR_EL1 = 49827 , ARM64_SYSREG_ERXCTLR_EL1 = 49825 , ARM64_SYSREG_ERXFR_EL1 = 49824 , ARM64_SYSREG_ERXMISC0_EL1 = 49832 , ARM64_SYSREG_ERXMISC1_EL1 = 49833 , ARM64_SYSREG_ERXMISC2_EL1 = 49834 , ARM64_SYSREG_ERXMISC3_EL1 = 49835 , ARM64_SYSREG_ERXPFGCDN_EL1 = 49830 , ARM64_SYSREG_ERXPFGCTL_EL1 = 49829 , ARM64_SYSREG_ERXPFGF_EL1 = 49828 , ARM64_SYSREG_ERXSTATUS_EL1 = 49826 , ARM64_SYSREG_ESR_EL1 = 49808 , ARM64_SYSREG_ESR_EL12 = 60048 , ARM64_SYSREG_ESR_EL2 = 58000 , ARM64_SYSREG_ESR_EL3 = 62096 , ARM64_SYSREG_FAR_EL1 = 49920 , ARM64_SYSREG_FAR_EL12 = 60160 , ARM64_SYSREG_FAR_EL2 = 58112 , ARM64_SYSREG_FAR_EL3 = 62208 , ARM64_SYSREG_FPCR = 55840 , ARM64_SYSREG_FPEXC32_EL2 = 58008 , ARM64_SYSREG_FPSR = 55841 , ARM64_SYSREG_GCR_EL1 = 49286 , ARM64_SYSREG_GMID_EL1 = 51204 , ARM64_SYSREG_GPCCR_EL3 = 61710 , ARM64_SYSREG_GPTBR_EL3 = 61708 , ARM64_SYSREG_HACR_EL2 = 57487 , ARM64_SYSREG_HCRX_EL2 = 57490 , ARM64_SYSREG_HCR_EL2 = 57480 , ARM64_SYSREG_HDFGRTR_EL2 = 57740 , ARM64_SYSREG_HDFGWTR_EL2 = 57741 , ARM64_SYSREG_HFGITR_EL2 = 57486 , ARM64_SYSREG_HFGRTR_EL2 = 57484 , ARM64_SYSREG_HFGWTR_EL2 = 57485 , ARM64_SYSREG_HPFAR_EL2 = 58116 , ARM64_SYSREG_HSTR_EL2 = 57483 , ARM64_SYSREG_ICC_AP0R0_EL1 = 50756 , ARM64_SYSREG_ICC_AP0R1_EL1 = 50757 , ARM64_SYSREG_ICC_AP0R2_EL1 = 50758 , ARM64_SYSREG_ICC_AP0R3_EL1 = 50759 , ARM64_SYSREG_ICC_AP1R0_EL1 = 50760 , ARM64_SYSREG_ICC_AP1R1_EL1 = 50761 , ARM64_SYSREG_ICC_AP1R2_EL1 = 50762 , ARM64_SYSREG_ICC_AP1R3_EL1 = 50763 , ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782 , ARM64_SYSREG_ICC_BPR0_EL1 = 50755 , ARM64_SYSREG_ICC_BPR1_EL1 = 50787 , ARM64_SYSREG_ICC_CTLR_EL1 = 50788 , ARM64_SYSREG_ICC_CTLR_EL3 = 63076 , ARM64_SYSREG_ICC_DIR_EL1 = 50777 , ARM64_SYSREG_ICC_EOIR0_EL1 = 50753 , ARM64_SYSREG_ICC_EOIR1_EL1 = 50785 , ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754 , ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786 , ARM64_SYSREG_ICC_IAR0_EL1 = 50752 , ARM64_SYSREG_ICC_IAR1_EL1 = 50784 , ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790 , ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791 , ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079 , ARM64_SYSREG_ICC_PMR_EL1 = 49712 , ARM64_SYSREG_ICC_RPR_EL1 = 50779 , ARM64_SYSREG_ICC_SGI0R_EL1 = 50783 , ARM64_SYSREG_ICC_SGI1R_EL1 = 50781 , ARM64_SYSREG_ICC_SRE_EL1 = 50789 , ARM64_SYSREG_ICC_SRE_EL2 = 58957 , ARM64_SYSREG_ICC_SRE_EL3 = 63077 , ARM64_SYSREG_ICH_AP0R0_EL2 = 58944 , ARM64_SYSREG_ICH_AP0R1_EL2 = 58945 , ARM64_SYSREG_ICH_AP0R2_EL2 = 58946 , ARM64_SYSREG_ICH_AP0R3_EL2 = 58947 , ARM64_SYSREG_ICH_AP1R0_EL2 = 58952 , ARM64_SYSREG_ICH_AP1R1_EL2 = 58953 , ARM64_SYSREG_ICH_AP1R2_EL2 = 58954 , ARM64_SYSREG_ICH_AP1R3_EL2 = 58955 , ARM64_SYSREG_ICH_EISR_EL2 = 58971 , ARM64_SYSREG_ICH_ELRSR_EL2 = 58973 , ARM64_SYSREG_ICH_HCR_EL2 = 58968 , ARM64_SYSREG_ICH_LR0_EL2 = 58976 , ARM64_SYSREG_ICH_LR10_EL2 = 58986 , ARM64_SYSREG_ICH_LR11_EL2 = 58987 , ARM64_SYSREG_ICH_LR12_EL2 = 58988 , ARM64_SYSREG_ICH_LR13_EL2 = 58989 , ARM64_SYSREG_ICH_LR14_EL2 = 58990 , ARM64_SYSREG_ICH_LR15_EL2 = 58991 , ARM64_SYSREG_ICH_LR1_EL2 = 58977 , ARM64_SYSREG_ICH_LR2_EL2 = 58978 , ARM64_SYSREG_ICH_LR3_EL2 = 58979 , ARM64_SYSREG_ICH_LR4_EL2 = 58980 , ARM64_SYSREG_ICH_LR5_EL2 = 58981 , ARM64_SYSREG_ICH_LR6_EL2 = 58982 , ARM64_SYSREG_ICH_LR7_EL2 = 58983 , ARM64_SYSREG_ICH_LR8_EL2 = 58984 , ARM64_SYSREG_ICH_LR9_EL2 = 58985 , ARM64_SYSREG_ICH_MISR_EL2 = 58970 , ARM64_SYSREG_ICH_VMCR_EL2 = 58975 , ARM64_SYSREG_ICH_VTR_EL2 = 58969 , ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196 , ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197 , ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192 , ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193 , ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200 , ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201 , ARM64_SYSREG_ID_AA64ISAR2_EL1 = 49202 , ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208 , ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209 , ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210 , ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184 , ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185 , ARM64_SYSREG_ID_AA64SMFR0_EL1 = 49189 , ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188 , ARM64_SYSREG_ID_AFR0_EL1 = 49163 , ARM64_SYSREG_ID_DFR0_EL1 = 49162 , ARM64_SYSREG_ID_ISAR0_EL1 = 49168 , ARM64_SYSREG_ID_ISAR1_EL1 = 49169 , ARM64_SYSREG_ID_ISAR2_EL1 = 49170 , ARM64_SYSREG_ID_ISAR3_EL1 = 49171 , ARM64_SYSREG_ID_ISAR4_EL1 = 49172 , ARM64_SYSREG_ID_ISAR5_EL1 = 49173 , ARM64_SYSREG_ID_ISAR6_EL1 = 49175 , ARM64_SYSREG_ID_MMFR0_EL1 = 49164 , ARM64_SYSREG_ID_MMFR1_EL1 = 49165 , ARM64_SYSREG_ID_MMFR2_EL1 = 49166 , ARM64_SYSREG_ID_MMFR3_EL1 = 49167 , ARM64_SYSREG_ID_MMFR4_EL1 = 49174 , ARM64_SYSREG_ID_MMFR5_EL1 = 49182 , ARM64_SYSREG_ID_PFR0_EL1 = 49160 , ARM64_SYSREG_ID_PFR1_EL1 = 49161 , ARM64_SYSREG_ID_PFR2_EL1 = 49180 , ARM64_SYSREG_IFSR32_EL2 = 57985 , ARM64_SYSREG_ISR_EL1 = 50696 , ARM64_SYSREG_LORC_EL1 = 50467 , ARM64_SYSREG_LOREA_EL1 = 50465 , ARM64_SYSREG_LORID_EL1 = 50471 , ARM64_SYSREG_LORN_EL1 = 50466 , ARM64_SYSREG_LORSA_EL1 = 50464 , ARM64_SYSREG_MAIR_EL1 = 50448 , ARM64_SYSREG_MAIR_EL12 = 60688 , ARM64_SYSREG_MAIR_EL2 = 58640 , ARM64_SYSREG_MAIR_EL3 = 62736 , ARM64_SYSREG_MDCCINT_EL1 = 32784 , ARM64_SYSREG_MDCCSR_EL0 = 38920 , ARM64_SYSREG_MDCR_EL2 = 57481 , ARM64_SYSREG_MDCR_EL3 = 61593 , ARM64_SYSREG_MDRAR_EL1 = 32896 , ARM64_SYSREG_MDSCR_EL1 = 32786 , ARM64_SYSREG_MFAR_EL3 = 62213 , ARM64_SYSREG_MIDR_EL1 = 49152 , ARM64_SYSREG_MPAM0_EL1 = 50473 , ARM64_SYSREG_MPAM1_EL1 = 50472 , ARM64_SYSREG_MPAM1_EL12 = 60712 , ARM64_SYSREG_MPAM2_EL2 = 58664 , ARM64_SYSREG_MPAM3_EL3 = 62760 , ARM64_SYSREG_MPAMHCR_EL2 = 58656 , ARM64_SYSREG_MPAMIDR_EL1 = 50468 , ARM64_SYSREG_MPAMSM_EL1 = 50475 , ARM64_SYSREG_MPAMVPM0_EL2 = 58672 , ARM64_SYSREG_MPAMVPM1_EL2 = 58673 , ARM64_SYSREG_MPAMVPM2_EL2 = 58674 , ARM64_SYSREG_MPAMVPM3_EL2 = 58675 , ARM64_SYSREG_MPAMVPM4_EL2 = 58676 , ARM64_SYSREG_MPAMVPM5_EL2 = 58677 , ARM64_SYSREG_MPAMVPM6_EL2 = 58678 , ARM64_SYSREG_MPAMVPM7_EL2 = 58679 , ARM64_SYSREG_MPAMVPMV_EL2 = 58657 , ARM64_SYSREG_MPIDR_EL1 = 49157 , ARM64_SYSREG_MPUIR_EL1 = 49156 , ARM64_SYSREG_MPUIR_EL2 = 57348 , ARM64_SYSREG_MVFR0_EL1 = 49176 , ARM64_SYSREG_MVFR1_EL1 = 49177 , ARM64_SYSREG_MVFR2_EL1 = 49178 , ARM64_SYSREG_NZCV = 55824 , ARM64_SYSREG_OSDLR_EL1 = 32924 , ARM64_SYSREG_OSDTRRX_EL1 = 32770 , ARM64_SYSREG_OSDTRTX_EL1 = 32794 , ARM64_SYSREG_OSECCR_EL1 = 32818 , ARM64_SYSREG_OSLAR_EL1 = 32900 , ARM64_SYSREG_OSLSR_EL1 = 32908 , ARM64_SYSREG_PAN = 49683 , ARM64_SYSREG_PAR_EL1 = 50080 , ARM64_SYSREG_PMBIDR_EL1 = 50391 , ARM64_SYSREG_PMBLIMITR_EL1 = 50384 , ARM64_SYSREG_PMBPTR_EL1 = 50385 , ARM64_SYSREG_PMBSR_EL1 = 50387 , ARM64_SYSREG_PMCCFILTR_EL0 = 57215 , ARM64_SYSREG_PMCCNTR_EL0 = 56552 , ARM64_SYSREG_PMCEID0_EL0 = 56550 , ARM64_SYSREG_PMCEID1_EL0 = 56551 , ARM64_SYSREG_PMCNTENCLR_EL0 = 56546 , ARM64_SYSREG_PMCNTENSET_EL0 = 56545 , ARM64_SYSREG_PMCR_EL0 = 56544 , ARM64_SYSREG_PMEVCNTR0_EL0 = 57152 , ARM64_SYSREG_PMEVCNTR10_EL0 = 57162 , ARM64_SYSREG_PMEVCNTR11_EL0 = 57163 , ARM64_SYSREG_PMEVCNTR12_EL0 = 57164 , ARM64_SYSREG_PMEVCNTR13_EL0 = 57165 , ARM64_SYSREG_PMEVCNTR14_EL0 = 57166 , ARM64_SYSREG_PMEVCNTR15_EL0 = 57167 , ARM64_SYSREG_PMEVCNTR16_EL0 = 57168 , ARM64_SYSREG_PMEVCNTR17_EL0 = 57169 , ARM64_SYSREG_PMEVCNTR18_EL0 = 57170 , ARM64_SYSREG_PMEVCNTR19_EL0 = 57171 , ARM64_SYSREG_PMEVCNTR1_EL0 = 57153 , ARM64_SYSREG_PMEVCNTR20_EL0 = 57172 , ARM64_SYSREG_PMEVCNTR21_EL0 = 57173 , ARM64_SYSREG_PMEVCNTR22_EL0 = 57174 , ARM64_SYSREG_PMEVCNTR23_EL0 = 57175 , ARM64_SYSREG_PMEVCNTR24_EL0 = 57176 , ARM64_SYSREG_PMEVCNTR25_EL0 = 57177 , ARM64_SYSREG_PMEVCNTR26_EL0 = 57178 , ARM64_SYSREG_PMEVCNTR27_EL0 = 57179 , ARM64_SYSREG_PMEVCNTR28_EL0 = 57180 , ARM64_SYSREG_PMEVCNTR29_EL0 = 57181 , ARM64_SYSREG_PMEVCNTR2_EL0 = 57154 , ARM64_SYSREG_PMEVCNTR30_EL0 = 57182 , ARM64_SYSREG_PMEVCNTR3_EL0 = 57155 , ARM64_SYSREG_PMEVCNTR4_EL0 = 57156 , ARM64_SYSREG_PMEVCNTR5_EL0 = 57157 , ARM64_SYSREG_PMEVCNTR6_EL0 = 57158 , ARM64_SYSREG_PMEVCNTR7_EL0 = 57159 , ARM64_SYSREG_PMEVCNTR8_EL0 = 57160 , ARM64_SYSREG_PMEVCNTR9_EL0 = 57161 , ARM64_SYSREG_PMEVTYPER0_EL0 = 57184 , ARM64_SYSREG_PMEVTYPER10_EL0 = 57194 , ARM64_SYSREG_PMEVTYPER11_EL0 = 57195 , ARM64_SYSREG_PMEVTYPER12_EL0 = 57196 , ARM64_SYSREG_PMEVTYPER13_EL0 = 57197 , ARM64_SYSREG_PMEVTYPER14_EL0 = 57198 , ARM64_SYSREG_PMEVTYPER15_EL0 = 57199 , ARM64_SYSREG_PMEVTYPER16_EL0 = 57200 , ARM64_SYSREG_PMEVTYPER17_EL0 = 57201 , ARM64_SYSREG_PMEVTYPER18_EL0 = 57202 , ARM64_SYSREG_PMEVTYPER19_EL0 = 57203 , ARM64_SYSREG_PMEVTYPER1_EL0 = 57185 , ARM64_SYSREG_PMEVTYPER20_EL0 = 57204 , ARM64_SYSREG_PMEVTYPER21_EL0 = 57205 , ARM64_SYSREG_PMEVTYPER22_EL0 = 57206 , ARM64_SYSREG_PMEVTYPER23_EL0 = 57207 , ARM64_SYSREG_PMEVTYPER24_EL0 = 57208 , ARM64_SYSREG_PMEVTYPER25_EL0 = 57209 , ARM64_SYSREG_PMEVTYPER26_EL0 = 57210 , ARM64_SYSREG_PMEVTYPER27_EL0 = 57211 , ARM64_SYSREG_PMEVTYPER28_EL0 = 57212 , ARM64_SYSREG_PMEVTYPER29_EL0 = 57213 , ARM64_SYSREG_PMEVTYPER2_EL0 = 57186 , ARM64_SYSREG_PMEVTYPER30_EL0 = 57214 , ARM64_SYSREG_PMEVTYPER3_EL0 = 57187 , ARM64_SYSREG_PMEVTYPER4_EL0 = 57188 , ARM64_SYSREG_PMEVTYPER5_EL0 = 57189 , ARM64_SYSREG_PMEVTYPER6_EL0 = 57190 , ARM64_SYSREG_PMEVTYPER7_EL0 = 57191 , ARM64_SYSREG_PMEVTYPER8_EL0 = 57192 , ARM64_SYSREG_PMEVTYPER9_EL0 = 57193 , ARM64_SYSREG_PMINTENCLR_EL1 = 50418 , ARM64_SYSREG_PMINTENSET_EL1 = 50417 , ARM64_SYSREG_PMMIR_EL1 = 50422 , ARM64_SYSREG_PMOVSCLR_EL0 = 56547 , ARM64_SYSREG_PMOVSSET_EL0 = 56563 , ARM64_SYSREG_PMSCR_EL1 = 50376 , ARM64_SYSREG_PMSCR_EL12 = 60616 , ARM64_SYSREG_PMSCR_EL2 = 58568 , ARM64_SYSREG_PMSELR_EL0 = 56549 , ARM64_SYSREG_PMSEVFR_EL1 = 50381 , ARM64_SYSREG_PMSFCR_EL1 = 50380 , ARM64_SYSREG_PMSICR_EL1 = 50378 , ARM64_SYSREG_PMSIDR_EL1 = 50383 , ARM64_SYSREG_PMSIRR_EL1 = 50379 , ARM64_SYSREG_PMSLATFR_EL1 = 50382 , ARM64_SYSREG_PMSNEVFR_EL1 = 50377 , ARM64_SYSREG_PMSWINC_EL0 = 56548 , ARM64_SYSREG_PMUSERENR_EL0 = 56560 , ARM64_SYSREG_PMXEVCNTR_EL0 = 56554 , ARM64_SYSREG_PMXEVTYPER_EL0 = 56553 , ARM64_SYSREG_PRBAR10_EL1 = 50024 , ARM64_SYSREG_PRBAR10_EL2 = 58216 , ARM64_SYSREG_PRBAR11_EL1 = 50028 , ARM64_SYSREG_PRBAR11_EL2 = 58220 , ARM64_SYSREG_PRBAR12_EL1 = 50032 , ARM64_SYSREG_PRBAR12_EL2 = 58224 , ARM64_SYSREG_PRBAR13_EL1 = 50036 , ARM64_SYSREG_PRBAR13_EL2 = 58228 , ARM64_SYSREG_PRBAR14_EL1 = 50040 , ARM64_SYSREG_PRBAR14_EL2 = 58232 , ARM64_SYSREG_PRBAR15_EL1 = 50044 , ARM64_SYSREG_PRBAR15_EL2 = 58236 , ARM64_SYSREG_PRBAR1_EL1 = 49988 , ARM64_SYSREG_PRBAR1_EL2 = 58180 , ARM64_SYSREG_PRBAR2_EL1 = 49992 , ARM64_SYSREG_PRBAR2_EL2 = 58184 , ARM64_SYSREG_PRBAR3_EL1 = 49996 , ARM64_SYSREG_PRBAR3_EL2 = 58188 , ARM64_SYSREG_PRBAR4_EL1 = 50000 , ARM64_SYSREG_PRBAR4_EL2 = 58192 , ARM64_SYSREG_PRBAR5_EL1 = 50004 , ARM64_SYSREG_PRBAR5_EL2 = 58196 , ARM64_SYSREG_PRBAR6_EL1 = 50008 , ARM64_SYSREG_PRBAR6_EL2 = 58200 , ARM64_SYSREG_PRBAR7_EL1 = 50012 , ARM64_SYSREG_PRBAR7_EL2 = 58204 , ARM64_SYSREG_PRBAR8_EL1 = 50016 , ARM64_SYSREG_PRBAR8_EL2 = 58208 , ARM64_SYSREG_PRBAR9_EL1 = 50020 , ARM64_SYSREG_PRBAR9_EL2 = 58212 , ARM64_SYSREG_PRBAR_EL1 = 49984 , ARM64_SYSREG_PRBAR_EL2 = 58176 , ARM64_SYSREG_PRENR_EL1 = 49929 , ARM64_SYSREG_PRENR_EL2 = 58121 , ARM64_SYSREG_PRLAR10_EL1 = 50025 , ARM64_SYSREG_PRLAR10_EL2 = 58217 , ARM64_SYSREG_PRLAR11_EL1 = 50029 , ARM64_SYSREG_PRLAR11_EL2 = 58221 , ARM64_SYSREG_PRLAR12_EL1 = 50033 , ARM64_SYSREG_PRLAR12_EL2 = 58225 , ARM64_SYSREG_PRLAR13_EL1 = 50037 , ARM64_SYSREG_PRLAR13_EL2 = 58229 , ARM64_SYSREG_PRLAR14_EL1 = 50041 , ARM64_SYSREG_PRLAR14_EL2 = 58233 , ARM64_SYSREG_PRLAR15_EL1 = 50045 , ARM64_SYSREG_PRLAR15_EL2 = 58237 , ARM64_SYSREG_PRLAR1_EL1 = 49989 , ARM64_SYSREG_PRLAR1_EL2 = 58181 , ARM64_SYSREG_PRLAR2_EL1 = 49993 , ARM64_SYSREG_PRLAR2_EL2 = 58185 , ARM64_SYSREG_PRLAR3_EL1 = 49997 , ARM64_SYSREG_PRLAR3_EL2 = 58189 , ARM64_SYSREG_PRLAR4_EL1 = 50001 , ARM64_SYSREG_PRLAR4_EL2 = 58193 , ARM64_SYSREG_PRLAR5_EL1 = 50005 , ARM64_SYSREG_PRLAR5_EL2 = 58197 , ARM64_SYSREG_PRLAR6_EL1 = 50009 , ARM64_SYSREG_PRLAR6_EL2 = 58201 , ARM64_SYSREG_PRLAR7_EL1 = 50013 , ARM64_SYSREG_PRLAR7_EL2 = 58205 , ARM64_SYSREG_PRLAR8_EL1 = 50017 , ARM64_SYSREG_PRLAR8_EL2 = 58209 , ARM64_SYSREG_PRLAR9_EL1 = 50021 , ARM64_SYSREG_PRLAR9_EL2 = 58213 , ARM64_SYSREG_PRLAR_EL1 = 49985 , ARM64_SYSREG_PRLAR_EL2 = 58177 , ARM64_SYSREG_PRSELR_EL1 = 49937 , ARM64_SYSREG_PRSELR_EL2 = 58129 , ARM64_SYSREG_REVIDR_EL1 = 49158 , ARM64_SYSREG_RGSR_EL1 = 49285 , ARM64_SYSREG_RMR_EL1 = 50690 , ARM64_SYSREG_RMR_EL2 = 58882 , ARM64_SYSREG_RMR_EL3 = 62978 , ARM64_SYSREG_RNDR = 55584 , ARM64_SYSREG_RNDRRS = 55585 , ARM64_SYSREG_RVBAR_EL1 = 50689 , ARM64_SYSREG_RVBAR_EL2 = 58881 , ARM64_SYSREG_RVBAR_EL3 = 62977 , ARM64_SYSREG_SCR_EL3 = 61576 , ARM64_SYSREG_SCTLR_EL1 = 49280 , ARM64_SYSREG_SCTLR_EL12 = 59520 , ARM64_SYSREG_SCTLR_EL2 = 57472 , ARM64_SYSREG_SCTLR_EL3 = 61568 , ARM64_SYSREG_SCXTNUM_EL0 = 56967 , ARM64_SYSREG_SCXTNUM_EL1 = 50823 , ARM64_SYSREG_SCXTNUM_EL12 = 61063 , ARM64_SYSREG_SCXTNUM_EL2 = 59015 , ARM64_SYSREG_SCXTNUM_EL3 = 63111 , ARM64_SYSREG_SDER32_EL2 = 57497 , ARM64_SYSREG_SDER32_EL3 = 61577 , ARM64_SYSREG_SMCR_EL1 = 49302 , ARM64_SYSREG_SMCR_EL12 = 59542 , ARM64_SYSREG_SMCR_EL2 = 57494 , ARM64_SYSREG_SMCR_EL3 = 61590 , ARM64_SYSREG_SMIDR_EL1 = 51206 , ARM64_SYSREG_SMPRIMAP_EL2 = 57493 , ARM64_SYSREG_SMPRI_EL1 = 49300 , ARM64_SYSREG_SPSEL = 49680 , ARM64_SYSREG_SPSR_ABT = 57881 , ARM64_SYSREG_SPSR_EL1 = 49664 , ARM64_SYSREG_SPSR_EL12 = 59904 , ARM64_SYSREG_SPSR_EL2 = 57856 , ARM64_SYSREG_SPSR_EL3 = 61952 , ARM64_SYSREG_SPSR_FIQ = 57883 , ARM64_SYSREG_SPSR_IRQ = 57880 , ARM64_SYSREG_SPSR_UND = 57882 , ARM64_SYSREG_SP_EL0 = 49672 , ARM64_SYSREG_SP_EL1 = 57864 , ARM64_SYSREG_SP_EL2 = 61960 , ARM64_SYSREG_SSBS = 55830 , ARM64_SYSREG_SVCR = 55826 , ARM64_SYSREG_TCO = 55831 , ARM64_SYSREG_TCR_EL1 = 49410 , ARM64_SYSREG_TCR_EL12 = 59650 , ARM64_SYSREG_TCR_EL2 = 57602 , ARM64_SYSREG_TCR_EL3 = 61698 , ARM64_SYSREG_TEECR32_EL1 = 36864 , ARM64_SYSREG_TEEHBR32_EL1 = 36992 , ARM64_SYSREG_TFSRE0_EL1 = 49841 , ARM64_SYSREG_TFSR_EL1 = 49840 , ARM64_SYSREG_TFSR_EL12 = 60080 , ARM64_SYSREG_TFSR_EL2 = 58032 , ARM64_SYSREG_TFSR_EL3 = 62128 , ARM64_SYSREG_TPIDR2_EL0 = 56965 , ARM64_SYSREG_TPIDRRO_EL0 = 56963 , ARM64_SYSREG_TPIDR_EL0 = 56962 , ARM64_SYSREG_TPIDR_EL1 = 50820 , ARM64_SYSREG_TPIDR_EL2 = 59010 , ARM64_SYSREG_TPIDR_EL3 = 63106 , ARM64_SYSREG_TRBBASER_EL1 = 50394 , ARM64_SYSREG_TRBIDR_EL1 = 50399 , ARM64_SYSREG_TRBLIMITR_EL1 = 50392 , ARM64_SYSREG_TRBMAR_EL1 = 50396 , ARM64_SYSREG_TRBPTR_EL1 = 50393 , ARM64_SYSREG_TRBSR_EL1 = 50395 , ARM64_SYSREG_TRBTRG_EL1 = 50398 , ARM64_SYSREG_TRCACATR0 = 35074 , ARM64_SYSREG_TRCACATR1 = 35090 , ARM64_SYSREG_TRCACATR10 = 35107 , ARM64_SYSREG_TRCACATR11 = 35123 , ARM64_SYSREG_TRCACATR12 = 35139 , ARM64_SYSREG_TRCACATR13 = 35155 , ARM64_SYSREG_TRCACATR14 = 35171 , ARM64_SYSREG_TRCACATR15 = 35187 , ARM64_SYSREG_TRCACATR2 = 35106 , ARM64_SYSREG_TRCACATR3 = 35122 , ARM64_SYSREG_TRCACATR4 = 35138 , ARM64_SYSREG_TRCACATR5 = 35154 , ARM64_SYSREG_TRCACATR6 = 35170 , ARM64_SYSREG_TRCACATR7 = 35186 , ARM64_SYSREG_TRCACATR8 = 35075 , ARM64_SYSREG_TRCACATR9 = 35091 , ARM64_SYSREG_TRCACVR0 = 35072 , ARM64_SYSREG_TRCACVR1 = 35088 , ARM64_SYSREG_TRCACVR10 = 35105 , ARM64_SYSREG_TRCACVR11 = 35121 , ARM64_SYSREG_TRCACVR12 = 35137 , ARM64_SYSREG_TRCACVR13 = 35153 , ARM64_SYSREG_TRCACVR14 = 35169 , ARM64_SYSREG_TRCACVR15 = 35185 , ARM64_SYSREG_TRCACVR2 = 35104 , ARM64_SYSREG_TRCACVR3 = 35120 , ARM64_SYSREG_TRCACVR4 = 35136 , ARM64_SYSREG_TRCACVR5 = 35152 , ARM64_SYSREG_TRCACVR6 = 35168 , ARM64_SYSREG_TRCACVR7 = 35184 , ARM64_SYSREG_TRCACVR8 = 35073 , ARM64_SYSREG_TRCACVR9 = 35089 , ARM64_SYSREG_TRCAUTHSTATUS = 35830 , ARM64_SYSREG_TRCAUXCTLR = 34864 , ARM64_SYSREG_TRCBBCTLR = 34936 , ARM64_SYSREG_TRCCCCTLR = 34928 , ARM64_SYSREG_TRCCIDCCTLR0 = 35202 , ARM64_SYSREG_TRCCIDCCTLR1 = 35210 , ARM64_SYSREG_TRCCIDCVR0 = 35200 , ARM64_SYSREG_TRCCIDCVR1 = 35216 , ARM64_SYSREG_TRCCIDCVR2 = 35232 , ARM64_SYSREG_TRCCIDCVR3 = 35248 , ARM64_SYSREG_TRCCIDCVR4 = 35264 , ARM64_SYSREG_TRCCIDCVR5 = 35280 , ARM64_SYSREG_TRCCIDCVR6 = 35296 , ARM64_SYSREG_TRCCIDCVR7 = 35312 , ARM64_SYSREG_TRCCIDR0 = 35815 , ARM64_SYSREG_TRCCIDR1 = 35823 , ARM64_SYSREG_TRCCIDR2 = 35831 , ARM64_SYSREG_TRCCIDR3 = 35839 , ARM64_SYSREG_TRCCLAIMCLR = 35790 , ARM64_SYSREG_TRCCLAIMSET = 35782 , ARM64_SYSREG_TRCCNTCTLR0 = 34853 , ARM64_SYSREG_TRCCNTCTLR1 = 34861 , ARM64_SYSREG_TRCCNTCTLR2 = 34869 , ARM64_SYSREG_TRCCNTCTLR3 = 34877 , ARM64_SYSREG_TRCCNTRLDVR0 = 34821 , ARM64_SYSREG_TRCCNTRLDVR1 = 34829 , ARM64_SYSREG_TRCCNTRLDVR2 = 34837 , ARM64_SYSREG_TRCCNTRLDVR3 = 34845 , ARM64_SYSREG_TRCCNTVR0 = 34885 , ARM64_SYSREG_TRCCNTVR1 = 34893 , ARM64_SYSREG_TRCCNTVR2 = 34901 , ARM64_SYSREG_TRCCNTVR3 = 34909 , ARM64_SYSREG_TRCCONFIGR = 34848 , ARM64_SYSREG_TRCDEVAFF0 = 35798 , ARM64_SYSREG_TRCDEVAFF1 = 35806 , ARM64_SYSREG_TRCDEVARCH = 35838 , ARM64_SYSREG_TRCDEVID = 35735 , ARM64_SYSREG_TRCDEVTYPE = 35743 , ARM64_SYSREG_TRCDVCMR0 = 35078 , ARM64_SYSREG_TRCDVCMR1 = 35110 , ARM64_SYSREG_TRCDVCMR2 = 35142 , ARM64_SYSREG_TRCDVCMR3 = 35174 , ARM64_SYSREG_TRCDVCMR4 = 35079 , ARM64_SYSREG_TRCDVCMR5 = 35111 , ARM64_SYSREG_TRCDVCMR6 = 35143 , ARM64_SYSREG_TRCDVCMR7 = 35175 , ARM64_SYSREG_TRCDVCVR0 = 35076 , ARM64_SYSREG_TRCDVCVR1 = 35108 , ARM64_SYSREG_TRCDVCVR2 = 35140 , ARM64_SYSREG_TRCDVCVR3 = 35172 , ARM64_SYSREG_TRCDVCVR4 = 35077 , ARM64_SYSREG_TRCDVCVR5 = 35109 , ARM64_SYSREG_TRCDVCVR6 = 35141 , ARM64_SYSREG_TRCDVCVR7 = 35173 , ARM64_SYSREG_TRCEVENTCTL0R = 34880 , ARM64_SYSREG_TRCEVENTCTL1R = 34888 , ARM64_SYSREG_TRCEXTINSELR = 34884 , ARM64_SYSREG_TRCEXTINSELR1 = 34892 , ARM64_SYSREG_TRCEXTINSELR2 = 34900 , ARM64_SYSREG_TRCEXTINSELR3 = 34908 , ARM64_SYSREG_TRCIDR0 = 34887 , ARM64_SYSREG_TRCIDR1 = 34895 , ARM64_SYSREG_TRCIDR10 = 34838 , ARM64_SYSREG_TRCIDR11 = 34846 , ARM64_SYSREG_TRCIDR12 = 34854 , ARM64_SYSREG_TRCIDR13 = 34862 , ARM64_SYSREG_TRCIDR2 = 34903 , ARM64_SYSREG_TRCIDR3 = 34911 , ARM64_SYSREG_TRCIDR4 = 34919 , ARM64_SYSREG_TRCIDR5 = 34927 , ARM64_SYSREG_TRCIDR6 = 34935 , ARM64_SYSREG_TRCIDR7 = 34943 , ARM64_SYSREG_TRCIDR8 = 34822 , ARM64_SYSREG_TRCIDR9 = 34830 , ARM64_SYSREG_TRCIMSPEC0 = 34823 , ARM64_SYSREG_TRCIMSPEC1 = 34831 , ARM64_SYSREG_TRCIMSPEC2 = 34839 , ARM64_SYSREG_TRCIMSPEC3 = 34847 , ARM64_SYSREG_TRCIMSPEC4 = 34855 , ARM64_SYSREG_TRCIMSPEC5 = 34863 , ARM64_SYSREG_TRCIMSPEC6 = 34871 , ARM64_SYSREG_TRCIMSPEC7 = 34879 , ARM64_SYSREG_TRCITCTRL = 35716 , ARM64_SYSREG_TRCLAR = 35814 , ARM64_SYSREG_TRCLSR = 35822 , ARM64_SYSREG_TRCOSLAR = 34948 , ARM64_SYSREG_TRCOSLSR = 34956 , ARM64_SYSREG_TRCPDCR = 34980 , ARM64_SYSREG_TRCPDSR = 34988 , ARM64_SYSREG_TRCPIDR0 = 35783 , ARM64_SYSREG_TRCPIDR1 = 35791 , ARM64_SYSREG_TRCPIDR2 = 35799 , ARM64_SYSREG_TRCPIDR3 = 35807 , ARM64_SYSREG_TRCPIDR4 = 35751 , ARM64_SYSREG_TRCPIDR5 = 35759 , ARM64_SYSREG_TRCPIDR6 = 35767 , ARM64_SYSREG_TRCPIDR7 = 35775 , ARM64_SYSREG_TRCPRGCTLR = 34824 , ARM64_SYSREG_TRCPROCSELR = 34832 , ARM64_SYSREG_TRCQCTLR = 34825 , ARM64_SYSREG_TRCRSCTLR10 = 35024 , ARM64_SYSREG_TRCRSCTLR11 = 35032 , ARM64_SYSREG_TRCRSCTLR12 = 35040 , ARM64_SYSREG_TRCRSCTLR13 = 35048 , ARM64_SYSREG_TRCRSCTLR14 = 35056 , ARM64_SYSREG_TRCRSCTLR15 = 35064 , ARM64_SYSREG_TRCRSCTLR16 = 34945 , ARM64_SYSREG_TRCRSCTLR17 = 34953 , ARM64_SYSREG_TRCRSCTLR18 = 34961 , ARM64_SYSREG_TRCRSCTLR19 = 34969 , ARM64_SYSREG_TRCRSCTLR2 = 34960 , ARM64_SYSREG_TRCRSCTLR20 = 34977 , ARM64_SYSREG_TRCRSCTLR21 = 34985 , ARM64_SYSREG_TRCRSCTLR22 = 34993 , ARM64_SYSREG_TRCRSCTLR23 = 35001 , ARM64_SYSREG_TRCRSCTLR24 = 35009 , ARM64_SYSREG_TRCRSCTLR25 = 35017 , ARM64_SYSREG_TRCRSCTLR26 = 35025 , ARM64_SYSREG_TRCRSCTLR27 = 35033 , ARM64_SYSREG_TRCRSCTLR28 = 35041 , ARM64_SYSREG_TRCRSCTLR29 = 35049 , ARM64_SYSREG_TRCRSCTLR3 = 34968 , ARM64_SYSREG_TRCRSCTLR30 = 35057 , ARM64_SYSREG_TRCRSCTLR31 = 35065 , ARM64_SYSREG_TRCRSCTLR4 = 34976 , ARM64_SYSREG_TRCRSCTLR5 = 34984 , ARM64_SYSREG_TRCRSCTLR6 = 34992 , ARM64_SYSREG_TRCRSCTLR7 = 35000 , ARM64_SYSREG_TRCRSCTLR8 = 35008 , ARM64_SYSREG_TRCRSCTLR9 = 35016 , ARM64_SYSREG_TRCRSR = 34896 , ARM64_SYSREG_TRCSEQEVR0 = 34820 , ARM64_SYSREG_TRCSEQEVR1 = 34828 , ARM64_SYSREG_TRCSEQEVR2 = 34836 , ARM64_SYSREG_TRCSEQRSTEVR = 34868 , ARM64_SYSREG_TRCSEQSTR = 34876 , ARM64_SYSREG_TRCSSCCR0 = 34946 , ARM64_SYSREG_TRCSSCCR1 = 34954 , ARM64_SYSREG_TRCSSCCR2 = 34962 , ARM64_SYSREG_TRCSSCCR3 = 34970 , ARM64_SYSREG_TRCSSCCR4 = 34978 , ARM64_SYSREG_TRCSSCCR5 = 34986 , ARM64_SYSREG_TRCSSCCR6 = 34994 , ARM64_SYSREG_TRCSSCCR7 = 35002 , ARM64_SYSREG_TRCSSCSR0 = 35010 , ARM64_SYSREG_TRCSSCSR1 = 35018 , ARM64_SYSREG_TRCSSCSR2 = 35026 , ARM64_SYSREG_TRCSSCSR3 = 35034 , ARM64_SYSREG_TRCSSCSR4 = 35042 , ARM64_SYSREG_TRCSSCSR5 = 35050 , ARM64_SYSREG_TRCSSCSR6 = 35058 , ARM64_SYSREG_TRCSSCSR7 = 35066 , ARM64_SYSREG_TRCSSPCICR0 = 34947 , ARM64_SYSREG_TRCSSPCICR1 = 34955 , ARM64_SYSREG_TRCSSPCICR2 = 34963 , ARM64_SYSREG_TRCSSPCICR3 = 34971 , ARM64_SYSREG_TRCSSPCICR4 = 34979 , ARM64_SYSREG_TRCSSPCICR5 = 34987 , ARM64_SYSREG_TRCSSPCICR6 = 34995 , ARM64_SYSREG_TRCSSPCICR7 = 35003 , ARM64_SYSREG_TRCSTALLCTLR = 34904 , ARM64_SYSREG_TRCSTATR = 34840 , ARM64_SYSREG_TRCSYNCPR = 34920 , ARM64_SYSREG_TRCTRACEIDR = 34817 , ARM64_SYSREG_TRCTSCTLR = 34912 , ARM64_SYSREG_TRCVDARCCTLR = 34898 , ARM64_SYSREG_TRCVDCTLR = 34882 , ARM64_SYSREG_TRCVDSACCTLR = 34890 , ARM64_SYSREG_TRCVICTLR = 34818 , ARM64_SYSREG_TRCVIIECTLR = 34826 , ARM64_SYSREG_TRCVIPCSSCTLR = 34842 , ARM64_SYSREG_TRCVISSCTLR = 34834 , ARM64_SYSREG_TRCVMIDCCTLR0 = 35218 , ARM64_SYSREG_TRCVMIDCCTLR1 = 35226 , ARM64_SYSREG_TRCVMIDCVR0 = 35201 , ARM64_SYSREG_TRCVMIDCVR1 = 35217 , ARM64_SYSREG_TRCVMIDCVR2 = 35233 , ARM64_SYSREG_TRCVMIDCVR3 = 35249 , ARM64_SYSREG_TRCVMIDCVR4 = 35265 , ARM64_SYSREG_TRCVMIDCVR5 = 35281 , ARM64_SYSREG_TRCVMIDCVR6 = 35297 , ARM64_SYSREG_TRCVMIDCVR7 = 35313 , ARM64_SYSREG_TRFCR_EL1 = 49297 , ARM64_SYSREG_TRFCR_EL12 = 59537 , ARM64_SYSREG_TRFCR_EL2 = 57489 , ARM64_SYSREG_TTBR0_EL1 = 49408 , ARM64_SYSREG_TTBR0_EL12 = 59648 , ARM64_SYSREG_TTBR0_EL2 = 57600 , ARM64_SYSREG_TTBR0_EL3 = 61696 , ARM64_SYSREG_TTBR1_EL1 = 49409 , ARM64_SYSREG_TTBR1_EL12 = 59649 , ARM64_SYSREG_TTBR1_EL2 = 57601 , ARM64_SYSREG_UAO = 49684 , ARM64_SYSREG_VBAR_EL1 = 50688 , ARM64_SYSREG_VBAR_EL12 = 60928 , ARM64_SYSREG_VBAR_EL2 = 58880 , ARM64_SYSREG_VBAR_EL3 = 62976 , ARM64_SYSREG_VDISR_EL2 = 58889 , ARM64_SYSREG_VMPIDR_EL2 = 57349 , ARM64_SYSREG_VNCR_EL2 = 57616 , ARM64_SYSREG_VPIDR_EL2 = 57344 , ARM64_SYSREG_VSESR_EL2 = 58003 , ARM64_SYSREG_VSTCR_EL2 = 57650 , ARM64_SYSREG_VSTTBR_EL2 = 57648 , ARM64_SYSREG_VTCR_EL2 = 57610 , ARM64_SYSREG_VTTBR_EL2 = 57608 , ARM64_SYSREG_ZCR_EL1 = 49296 , ARM64_SYSREG_ZCR_EL12 = 59536 , ARM64_SYSREG_ZCR_EL2 = 57488 , ARM64_SYSREG_ZCR_EL3 = 61584 , } # [repr (u32)] # [doc = " System PState Field (MSR instruction)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_pstate { ARM64_PSTATE_INVALID = 0 , ARM64_PSTATE_SPSEL = 5 , ARM64_PSTATE_DAIFSET = 30 , ARM64_PSTATE_DAIFCLR = 31 , ARM64_PSTATE_PAN = 4 , ARM64_PSTATE_UAO = 3 , ARM64_PSTATE_DIT = 26 , } # [repr (u32)] # [doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_vas { ARM64_VAS_INVALID = 0 , ARM64_VAS_16B = 1 , ARM64_VAS_8B = 2 , ARM64_VAS_4B = 3 , ARM64_VAS_1B = 4 , ARM64_VAS_8H = 5 , ARM64_VAS_4H = 6 , ARM64_VAS_2H = 7 , ARM64_VAS_1H = 8 , ARM64_VAS_4S = 9 , ARM64_VAS_2S = 10 , ARM64_VAS_1S = 11 , ARM64_VAS_2D = 12 , ARM64_VAS_1D = 13 , ARM64_VAS_1Q = 14 , } # [repr (u32)] # [doc = " Memory barrier operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0 , ARM64_BARRIER_OSHLD = 1 , ARM64_BARRIER_OSHST = 2 , ARM64_BARRIER_OSH = 3 , ARM64_BARRIER_NSHLD = 5 , ARM64_BARRIER_NSHST = 6 , ARM64_BARRIER_NSH = 7 , ARM64_BARRIER_ISHLD = 9 , ARM64_BARRIER_ISHST = 10 , ARM64_BARRIER_ISH = 11 , ARM64_BARRIER_LD = 13 , ARM64_BARRIER_ST = 14 , ARM64_BARRIER_SY = 15 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM64_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM64_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM64_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM64_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM64_OP_FP = 4 , # [doc = "< C-Immediate"] ARM64_OP_CIMM = 64 , # [doc = "< MRS register operand."] ARM64_OP_REG_MRS = 65 , # [doc = "< MSR register operand."] ARM64_OP_REG_MSR = 66 , # [doc = "< PState operand."] ARM64_OP_PSTATE = 67 , # [doc = "< SYS operand for IC/DC/AT/TLBI instructions."] ARM64_OP_SYS = 68 , # [doc = "< SVCR operand for MSR SVCR instructions."] ARM64_OP_SVCR = 69 , # [doc = "< Prefetch operand (PRFM)."] ARM64_OP_PREFETCH = 70 , # [doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."] ARM64_OP_BARRIER = 71 , # [doc = "< SME instruction operand with with index."] ARM64_OP_SME_INDEX = 72 , } # [repr (u32)] # [doc = " SYS operands (IC/DC/AC/TLBI)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sys_op { ARM64_SYS_INVALID = 0 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1 = 1 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1IS = 2 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1ISNXS = 3 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1NXS = 4 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OS = 5 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OSNXS = 6 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2 = 7 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2IS = 8 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2ISNXS = 9 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2NXS = 10 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OS = 11 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OSNXS = 12 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3 = 13 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3IS = 14 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3ISNXS = 15 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3NXS = 16 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OS = 17 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OSNXS = 18 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1 = 19 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1IS = 20 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1ISNXS = 21 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1NXS = 22 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OS = 23 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OSNXS = 24 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1 = 25 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1IS = 26 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1ISNXS = 27 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1NXS = 28 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OS = 29 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OSNXS = 30 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1 = 31 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1IS = 32 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1ISNXS = 33 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1NXS = 34 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OS = 35 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OSNXS = 36 , # [doc = " TLBI operations"] ARM64_TLBI_PAALL = 37 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLNXS = 38 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOS = 39 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOSNXS = 40 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1 = 41 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1IS = 42 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1ISNXS = 43 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1NXS = 44 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OS = 45 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OSNXS = 46 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1 = 47 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1IS = 48 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1ISNXS = 49 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1NXS = 50 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OS = 51 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OSNXS = 52 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOS = 53 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOSNXS = 54 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOS = 55 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOSNXS = 56 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1 = 57 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1IS = 58 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1ISNXS = 59 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1NXS = 60 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OS = 61 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OSNXS = 62 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1 = 63 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1IS = 64 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1ISNXS = 65 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1NXS = 66 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OS = 67 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OSNXS = 68 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1 = 69 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1IS = 70 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1ISNXS = 71 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1NXS = 72 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OS = 73 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OSNXS = 74 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2 = 75 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2IS = 76 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2ISNXS = 77 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2NXS = 78 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OS = 79 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OSNXS = 80 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3 = 81 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3IS = 82 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3ISNXS = 83 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3NXS = 84 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OS = 85 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OSNXS = 86 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1 = 87 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1IS = 88 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1ISNXS = 89 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1NXS = 90 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OS = 91 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OSNXS = 92 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2 = 93 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2IS = 94 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2ISNXS = 95 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2NXS = 96 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OS = 97 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OSNXS = 98 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3 = 99 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3IS = 100 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3ISNXS = 101 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3NXS = 102 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OS = 103 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OSNXS = 104 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1 = 105 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1IS = 106 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1ISNXS = 107 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1NXS = 108 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OS = 109 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OSNXS = 110 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1 = 111 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1IS = 112 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1ISNXS = 113 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1NXS = 114 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OS = 115 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OSNXS = 116 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1 = 117 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1IS = 118 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1ISNXS = 119 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1NXS = 120 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OS = 121 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OSNXS = 122 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2 = 123 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2IS = 124 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2ISNXS = 125 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2NXS = 126 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OS = 127 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OSNXS = 128 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3 = 129 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3IS = 130 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3ISNXS = 131 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3NXS = 132 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OS = 133 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OSNXS = 134 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1 = 135 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1IS = 136 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1ISNXS = 137 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1NXS = 138 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OS = 139 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OSNXS = 140 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2 = 141 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2IS = 142 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2ISNXS = 143 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2NXS = 144 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OS = 145 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OSNXS = 146 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3 = 147 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3IS = 148 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3ISNXS = 149 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3NXS = 150 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OS = 151 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OSNXS = 152 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1 = 153 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1IS = 154 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1ISNXS = 155 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1NXS = 156 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OS = 157 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OSNXS = 158 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1 = 159 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1IS = 160 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1ISNXS = 161 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1NXS = 162 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OS = 163 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OSNXS = 164 , # [doc = " AT operations"] ARM64_AT_S1E1R = 165 , # [doc = " AT operations"] ARM64_AT_S1E2R = 166 , # [doc = " AT operations"] ARM64_AT_S1E3R = 167 , # [doc = " AT operations"] ARM64_AT_S1E1W = 168 , # [doc = " AT operations"] ARM64_AT_S1E2W = 169 , # [doc = " AT operations"] ARM64_AT_S1E3W = 170 , # [doc = " AT operations"] ARM64_AT_S1E0R = 171 , # [doc = " AT operations"] ARM64_AT_S1E0W = 172 , # [doc = " AT operations"] ARM64_AT_S12E1R = 173 , # [doc = " AT operations"] ARM64_AT_S12E1W = 174 , # [doc = " AT operations"] ARM64_AT_S12E0R = 175 , # [doc = " AT operations"] ARM64_AT_S12E0W = 176 , # [doc = " AT operations"] ARM64_AT_S1E1RP = 177 , # [doc = " AT operations"] ARM64_AT_S1E1WP = 178 , # [doc = " DC operations"] ARM64_DC_CGDSW = 179 , # [doc = " DC operations"] ARM64_DC_CGDVAC = 180 , # [doc = " DC operations"] ARM64_DC_CGDVADP = 181 , # [doc = " DC operations"] ARM64_DC_CGDVAP = 182 , # [doc = " DC operations"] ARM64_DC_CGSW = 183 , # [doc = " DC operations"] ARM64_DC_CGVAC = 184 , # [doc = " DC operations"] ARM64_DC_CGVADP = 185 , # [doc = " DC operations"] ARM64_DC_CGVAP = 186 , # [doc = " DC operations"] ARM64_DC_CIGDSW = 187 , # [doc = " DC operations"] ARM64_DC_CIGDVAC = 188 , # [doc = " DC operations"] ARM64_DC_CIGSW = 189 , # [doc = " DC operations"] ARM64_DC_CIGVAC = 190 , # [doc = " DC operations"] ARM64_DC_CISW = 191 , # [doc = " DC operations"] ARM64_DC_CIVAC = 192 , # [doc = " DC operations"] ARM64_DC_CSW = 193 , # [doc = " DC operations"] ARM64_DC_CVAC = 194 , # [doc = " DC operations"] ARM64_DC_CVADP = 195 , # [doc = " DC operations"] ARM64_DC_CVAP = 196 , # [doc = " DC operations"] ARM64_DC_CVAU = 197 , # [doc = " DC operations"] ARM64_DC_GVA = 198 , # [doc = " DC operations"] ARM64_DC_GZVA = 199 , # [doc = " DC operations"] ARM64_DC_IGDSW = 200 , # [doc = " DC operations"] ARM64_DC_IGDVAC = 201 , # [doc = " DC operations"] ARM64_DC_IGSW = 202 , # [doc = " DC operations"] ARM64_DC_IGVAC = 203 , # [doc = " DC operations"] ARM64_DC_ISW = 204 , # [doc = " DC operations"] ARM64_DC_IVAC = 205 , # [doc = " DC operations"] ARM64_DC_ZVA = 206 , # [doc = " IC operations"] ARM64_IC_IALLUIS = 207 , # [doc = " IC operations"] ARM64_IC_IALLU = 208 , # [doc = " IC operations"] ARM64_IC_IVAU = 209 , } # [repr (u32)] # [doc = " SVCR operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_svcr_op { ARM64_SVCR_INVALID = 0 , ARM64_SVCR_SVCRSM = 1 , ARM64_SVCR_SVCRSMZA = 3 , ARM64_SVCR_SVCRZA = 2 , } # [repr (u32)] # [doc = " Prefetch operations (PRFM)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0 , ARM64_PRFM_PLDL1KEEP = 1 , ARM64_PRFM_PLDL1STRM = 2 , ARM64_PRFM_PLDL2KEEP = 3 , ARM64_PRFM_PLDL2STRM = 4 , ARM64_PRFM_PLDL3KEEP = 5 , ARM64_PRFM_PLDL3STRM = 6 , ARM64_PRFM_PLIL1KEEP = 9 , ARM64_PRFM_PLIL1STRM = 10 , ARM64_PRFM_PLIL2KEEP = 11 , ARM64_PRFM_PLIL2STRM = 12 , ARM64_PRFM_PLIL3KEEP = 13 , ARM64_PRFM_PLIL3STRM = 14 , ARM64_PRFM_PSTL1KEEP = 17 , ARM64_PRFM_PSTL1STRM = 18 , ARM64_PRFM_PSTL2KEEP = 19 , ARM64_PRFM_PSTL2STRM = 20 , ARM64_PRFM_PSTL3KEEP = 21 , ARM64_PRFM_PSTL3STRM = 22 , } impl arm64_reg { pub const ARM64_REG_IP0 : arm64_reg = arm64_reg :: ARM64_REG_X16 ; } impl arm64_reg { pub const ARM64_REG_IP1 : arm64_reg = arm64_reg :: ARM64_REG_X17 ; } impl arm64_reg { pub const ARM64_REG_X29 : arm64_reg = arm64_reg :: ARM64_REG_FP ; } impl arm64_reg { pub const ARM64_REG_X30 : arm64_reg = arm64_reg :: ARM64_REG_LR ; } # [repr (u32)] # [doc = " ARM64 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_reg { ARM64_REG_INVALID = 0 , ARM64_REG_FFR = 1 , ARM64_REG_FP = 2 , ARM64_REG_LR = 3 , ARM64_REG_NZCV = 4 , ARM64_REG_SP = 5 , ARM64_REG_VG = 6 , ARM64_REG_WSP = 7 , ARM64_REG_WZR = 8 , ARM64_REG_XZR = 9 , ARM64_REG_ZA = 10 , ARM64_REG_B0 = 11 , ARM64_REG_B1 = 12 , ARM64_REG_B2 = 13 , ARM64_REG_B3 = 14 , ARM64_REG_B4 = 15 , ARM64_REG_B5 = 16 , ARM64_REG_B6 = 17 , ARM64_REG_B7 = 18 , ARM64_REG_B8 = 19 , ARM64_REG_B9 = 20 , ARM64_REG_B10 = 21 , ARM64_REG_B11 = 22 , ARM64_REG_B12 = 23 , ARM64_REG_B13 = 24 , ARM64_REG_B14 = 25 , ARM64_REG_B15 = 26 , ARM64_REG_B16 = 27 , ARM64_REG_B17 = 28 , ARM64_REG_B18 = 29 , ARM64_REG_B19 = 30 , ARM64_REG_B20 = 31 , ARM64_REG_B21 = 32 , ARM64_REG_B22 = 33 , ARM64_REG_B23 = 34 , ARM64_REG_B24 = 35 , ARM64_REG_B25 = 36 , ARM64_REG_B26 = 37 , ARM64_REG_B27 = 38 , ARM64_REG_B28 = 39 , ARM64_REG_B29 = 40 , ARM64_REG_B30 = 41 , ARM64_REG_B31 = 42 , ARM64_REG_D0 = 43 , ARM64_REG_D1 = 44 , ARM64_REG_D2 = 45 , ARM64_REG_D3 = 46 , ARM64_REG_D4 = 47 , ARM64_REG_D5 = 48 , ARM64_REG_D6 = 49 , ARM64_REG_D7 = 50 , ARM64_REG_D8 = 51 , ARM64_REG_D9 = 52 , ARM64_REG_D10 = 53 , ARM64_REG_D11 = 54 , ARM64_REG_D12 = 55 , ARM64_REG_D13 = 56 , ARM64_REG_D14 = 57 , ARM64_REG_D15 = 58 , ARM64_REG_D16 = 59 , ARM64_REG_D17 = 60 , ARM64_REG_D18 = 61 , ARM64_REG_D19 = 62 , ARM64_REG_D20 = 63 , ARM64_REG_D21 = 64 , ARM64_REG_D22 = 65 , ARM64_REG_D23 = 66 , ARM64_REG_D24 = 67 , ARM64_REG_D25 = 68 , ARM64_REG_D26 = 69 , ARM64_REG_D27 = 70 , ARM64_REG_D28 = 71 , ARM64_REG_D29 = 72 , ARM64_REG_D30 = 73 , ARM64_REG_D31 = 74 , ARM64_REG_H0 = 75 , ARM64_REG_H1 = 76 , ARM64_REG_H2 = 77 , ARM64_REG_H3 = 78 , ARM64_REG_H4 = 79 , ARM64_REG_H5 = 80 , ARM64_REG_H6 = 81 , ARM64_REG_H7 = 82 , ARM64_REG_H8 = 83 , ARM64_REG_H9 = 84 , ARM64_REG_H10 = 85 , ARM64_REG_H11 = 86 , ARM64_REG_H12 = 87 , ARM64_REG_H13 = 88 , ARM64_REG_H14 = 89 , ARM64_REG_H15 = 90 , ARM64_REG_H16 = 91 , ARM64_REG_H17 = 92 , ARM64_REG_H18 = 93 , ARM64_REG_H19 = 94 , ARM64_REG_H20 = 95 , ARM64_REG_H21 = 96 , ARM64_REG_H22 = 97 , ARM64_REG_H23 = 98 , ARM64_REG_H24 = 99 , ARM64_REG_H25 = 100 , ARM64_REG_H26 = 101 , ARM64_REG_H27 = 102 , ARM64_REG_H28 = 103 , ARM64_REG_H29 = 104 , ARM64_REG_H30 = 105 , ARM64_REG_H31 = 106 , ARM64_REG_P0 = 107 , ARM64_REG_P1 = 108 , ARM64_REG_P2 = 109 , ARM64_REG_P3 = 110 , ARM64_REG_P4 = 111 , ARM64_REG_P5 = 112 , ARM64_REG_P6 = 113 , ARM64_REG_P7 = 114 , ARM64_REG_P8 = 115 , ARM64_REG_P9 = 116 , ARM64_REG_P10 = 117 , ARM64_REG_P11 = 118 , ARM64_REG_P12 = 119 , ARM64_REG_P13 = 120 , ARM64_REG_P14 = 121 , ARM64_REG_P15 = 122 , ARM64_REG_Q0 = 123 , ARM64_REG_Q1 = 124 , ARM64_REG_Q2 = 125 , ARM64_REG_Q3 = 126 , ARM64_REG_Q4 = 127 , ARM64_REG_Q5 = 128 , ARM64_REG_Q6 = 129 , ARM64_REG_Q7 = 130 , ARM64_REG_Q8 = 131 , ARM64_REG_Q9 = 132 , ARM64_REG_Q10 = 133 , ARM64_REG_Q11 = 134 , ARM64_REG_Q12 = 135 , ARM64_REG_Q13 = 136 , ARM64_REG_Q14 = 137 , ARM64_REG_Q15 = 138 , ARM64_REG_Q16 = 139 , ARM64_REG_Q17 = 140 , ARM64_REG_Q18 = 141 , ARM64_REG_Q19 = 142 , ARM64_REG_Q20 = 143 , ARM64_REG_Q21 = 144 , ARM64_REG_Q22 = 145 , ARM64_REG_Q23 = 146 , ARM64_REG_Q24 = 147 , ARM64_REG_Q25 = 148 , ARM64_REG_Q26 = 149 , ARM64_REG_Q27 = 150 , ARM64_REG_Q28 = 151 , ARM64_REG_Q29 = 152 , ARM64_REG_Q30 = 153 , ARM64_REG_Q31 = 154 , ARM64_REG_S0 = 155 , ARM64_REG_S1 = 156 , ARM64_REG_S2 = 157 , ARM64_REG_S3 = 158 , ARM64_REG_S4 = 159 , ARM64_REG_S5 = 160 , ARM64_REG_S6 = 161 , ARM64_REG_S7 = 162 , ARM64_REG_S8 = 163 , ARM64_REG_S9 = 164 , ARM64_REG_S10 = 165 , ARM64_REG_S11 = 166 , ARM64_REG_S12 = 167 , ARM64_REG_S13 = 168 , ARM64_REG_S14 = 169 , ARM64_REG_S15 = 170 , ARM64_REG_S16 = 171 , ARM64_REG_S17 = 172 , ARM64_REG_S18 = 173 , ARM64_REG_S19 = 174 , ARM64_REG_S20 = 175 , ARM64_REG_S21 = 176 , ARM64_REG_S22 = 177 , ARM64_REG_S23 = 178 , ARM64_REG_S24 = 179 , ARM64_REG_S25 = 180 , ARM64_REG_S26 = 181 , ARM64_REG_S27 = 182 , ARM64_REG_S28 = 183 , ARM64_REG_S29 = 184 , ARM64_REG_S30 = 185 , ARM64_REG_S31 = 186 , ARM64_REG_W0 = 187 , ARM64_REG_W1 = 188 , ARM64_REG_W2 = 189 , ARM64_REG_W3 = 190 , ARM64_REG_W4 = 191 , ARM64_REG_W5 = 192 , ARM64_REG_W6 = 193 , ARM64_REG_W7 = 194 , ARM64_REG_W8 = 195 , ARM64_REG_W9 = 196 , ARM64_REG_W10 = 197 , ARM64_REG_W11 = 198 , ARM64_REG_W12 = 199 , ARM64_REG_W13 = 200 , ARM64_REG_W14 = 201 , ARM64_REG_W15 = 202 , ARM64_REG_W16 = 203 , ARM64_REG_W17 = 204 , ARM64_REG_W18 = 205 , ARM64_REG_W19 = 206 , ARM64_REG_W20 = 207 , ARM64_REG_W21 = 208 , ARM64_REG_W22 = 209 , ARM64_REG_W23 = 210 , ARM64_REG_W24 = 211 , ARM64_REG_W25 = 212 , ARM64_REG_W26 = 213 , ARM64_REG_W27 = 214 , ARM64_REG_W28 = 215 , ARM64_REG_W29 = 216 , ARM64_REG_W30 = 217 , ARM64_REG_X0 = 218 , ARM64_REG_X1 = 219 , ARM64_REG_X2 = 220 , ARM64_REG_X3 = 221 , ARM64_REG_X4 = 222 , ARM64_REG_X5 = 223 , ARM64_REG_X6 = 224 , ARM64_REG_X7 = 225 , ARM64_REG_X8 = 226 , ARM64_REG_X9 = 227 , ARM64_REG_X10 = 228 , ARM64_REG_X11 = 229 , ARM64_REG_X12 = 230 , ARM64_REG_X13 = 231 , ARM64_REG_X14 = 232 , ARM64_REG_X15 = 233 , ARM64_REG_X16 = 234 , ARM64_REG_X17 = 235 , ARM64_REG_X18 = 236 , ARM64_REG_X19 = 237 , ARM64_REG_X20 = 238 , ARM64_REG_X21 = 239 , ARM64_REG_X22 = 240 , ARM64_REG_X23 = 241 , ARM64_REG_X24 = 242 , ARM64_REG_X25 = 243 , ARM64_REG_X26 = 244 , ARM64_REG_X27 = 245 , ARM64_REG_X28 = 246 , ARM64_REG_Z0 = 247 , ARM64_REG_Z1 = 248 , ARM64_REG_Z2 = 249 , ARM64_REG_Z3 = 250 , ARM64_REG_Z4 = 251 , ARM64_REG_Z5 = 252 , ARM64_REG_Z6 = 253 , ARM64_REG_Z7 = 254 , ARM64_REG_Z8 = 255 , ARM64_REG_Z9 = 256 , ARM64_REG_Z10 = 257 , ARM64_REG_Z11 = 258 , ARM64_REG_Z12 = 259 , ARM64_REG_Z13 = 260 , ARM64_REG_Z14 = 261 , ARM64_REG_Z15 = 262 , ARM64_REG_Z16 = 263 , ARM64_REG_Z17 = 264 , ARM64_REG_Z18 = 265 , ARM64_REG_Z19 = 266 , ARM64_REG_Z20 = 267 , ARM64_REG_Z21 = 268 , ARM64_REG_Z22 = 269 , ARM64_REG_Z23 = 270 , ARM64_REG_Z24 = 271 , ARM64_REG_Z25 = 272 , ARM64_REG_Z26 = 273 , ARM64_REG_Z27 = 274 , ARM64_REG_Z28 = 275 , ARM64_REG_Z29 = 276 , ARM64_REG_Z30 = 277 , ARM64_REG_Z31 = 278 , ARM64_REG_ZAB0 = 279 , ARM64_REG_ZAD0 = 280 , ARM64_REG_ZAD1 = 281 , ARM64_REG_ZAD2 = 282 , ARM64_REG_ZAD3 = 283 , ARM64_REG_ZAD4 = 284 , ARM64_REG_ZAD5 = 285 , ARM64_REG_ZAD6 = 286 , ARM64_REG_ZAD7 = 287 , ARM64_REG_ZAH0 = 288 , ARM64_REG_ZAH1 = 289 , ARM64_REG_ZAQ0 = 290 , ARM64_REG_ZAQ1 = 291 , ARM64_REG_ZAQ2 = 292 , ARM64_REG_ZAQ3 = 293 , ARM64_REG_ZAQ4 = 294 , ARM64_REG_ZAQ5 = 295 , ARM64_REG_ZAQ6 = 296 , ARM64_REG_ZAQ7 = 297 , ARM64_REG_ZAQ8 = 298 , ARM64_REG_ZAQ9 = 299 , ARM64_REG_ZAQ10 = 300 , ARM64_REG_ZAQ11 = 301 , ARM64_REG_ZAQ12 = 302 , ARM64_REG_ZAQ13 = 303 , ARM64_REG_ZAQ14 = 304 , ARM64_REG_ZAQ15 = 305 , ARM64_REG_ZAS0 = 306 , ARM64_REG_ZAS1 = 307 , ARM64_REG_ZAS2 = 308 , ARM64_REG_ZAS3 = 309 , ARM64_REG_V0 = 310 , ARM64_REG_V1 = 311 , ARM64_REG_V2 = 312 , ARM64_REG_V3 = 313 , ARM64_REG_V4 = 314 , ARM64_REG_V5 = 315 , ARM64_REG_V6 = 316 , ARM64_REG_V7 = 317 , ARM64_REG_V8 = 318 , ARM64_REG_V9 = 319 , ARM64_REG_V10 = 320 , ARM64_REG_V11 = 321 , ARM64_REG_V12 = 322 , ARM64_REG_V13 = 323 , ARM64_REG_V14 = 324 , ARM64_REG_V15 = 325 , ARM64_REG_V16 = 326 , ARM64_REG_V17 = 327 , ARM64_REG_V18 = 328 , ARM64_REG_V19 = 329 , ARM64_REG_V20 = 330 , ARM64_REG_V21 = 331 , ARM64_REG_V22 = 332 , ARM64_REG_V23 = 333 , ARM64_REG_V24 = 334 , ARM64_REG_V25 = 335 , ARM64_REG_V26 = 336 , ARM64_REG_V27 = 337 , ARM64_REG_V28 = 338 , ARM64_REG_V29 = 339 , ARM64_REG_V30 = 340 , ARM64_REG_V31 = 341 , ARM64_REG_ENDING = 342 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_mem { # [doc = "< base register"] pub base : arm64_reg , # [doc = "< index register"] pub index : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_mem"] [:: std :: mem :: size_of :: < arm64_op_mem > () - 12usize] ; ["Alignment of arm64_op_mem"] [:: std :: mem :: align_of :: < arm64_op_mem > () - 4usize] ; ["Offset of field: arm64_op_mem::base"] [:: std :: mem :: offset_of ! (arm64_op_mem , base) - 0usize] ; ["Offset of field: arm64_op_mem::index"] [:: std :: mem :: offset_of ! (arm64_op_mem , index) - 4usize] ; ["Offset of field: arm64_op_mem::disp"] [:: std :: mem :: offset_of ! (arm64_op_mem , disp) - 8usize] ; } ; # [doc = " SME Instruction's operand has index\n This is associated with ARM64_OP_SME_INDEX operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_sme_index { # [doc = "< register being indexed"] pub reg : arm64_reg , # [doc = "< base register"] pub base : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_sme_index"] [:: std :: mem :: size_of :: < arm64_op_sme_index > () - 12usize] ; ["Alignment of arm64_op_sme_index"] [:: std :: mem :: align_of :: < arm64_op_sme_index > () - 4usize] ; ["Offset of field: arm64_op_sme_index::reg"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , reg) - 0usize] ; ["Offset of field: arm64_op_sme_index::base"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , base) - 4usize] ; ["Offset of field: arm64_op_sme_index::disp"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64_op { # [doc = "< Vector Index for some vector operands (or -1 if\n< irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , # [doc = "< Vector Arrangement Specifier"] pub vas : arm64_vas , pub shift : cs_arm64_op__bindgen_ty_1 , # [doc = "< extender type of this operand"] pub ext : arm64_extender , # [doc = "< operand type"] pub type_ : arm64_op_type , # [doc = "< MSR/MRS SVCR instruction variant."] pub svcr : arm64_svcr_op , pub __bindgen_anon_1 : cs_arm64_op__bindgen_ty_2 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm64_op__bindgen_ty_1 { # [doc = "< shifter type of this operand"] pub type_ : arm64_shifter , # [doc = "< shifter value of this operand"] pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm64_op__bindgen_ty_2 { # [doc = "< register value for REG operand"] pub reg : arm64_reg , # [doc = "< immediate value, or index for C-IMM or IMM operand"] pub imm : i64 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm64_op_mem , # [doc = "< PState field of MSR instruction."] pub pstate : arm64_pstate , # [doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op,\n< arm64_dc_op, arm64_at_op, arm64_tlbi_op)"] pub sys : arm64_sys_op , # [doc = "< PRFM operation."] pub prefetch : arm64_prefetch_op , # [doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."] pub barrier : arm64_barrier_op , # [doc = "< base/disp value for matrix tile slice\n< instructions."] pub sme_index : arm64_op_sme_index , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_2 > () - 16usize] ; ["Alignment of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::pstate"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , pstate) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sys"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sys) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::prefetch"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , prefetch) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::barrier"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , barrier) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sme_index"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sme_index) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op"] [:: std :: mem :: size_of :: < cs_arm64_op > () - 56usize] ; ["Alignment of cs_arm64_op"] [:: std :: mem :: align_of :: < cs_arm64_op > () - 8usize] ; ["Offset of field: cs_arm64_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm64_op , vector_index) - 0usize] ; ["Offset of field: cs_arm64_op::vas"] [:: std :: mem :: offset_of ! (cs_arm64_op , vas) - 4usize] ; ["Offset of field: cs_arm64_op::shift"] [:: std :: mem :: offset_of ! (cs_arm64_op , shift) - 8usize] ; ["Offset of field: cs_arm64_op::ext"] [:: std :: mem :: offset_of ! (cs_arm64_op , ext) - 16usize] ; ["Offset of field: cs_arm64_op::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op , type_) - 20usize] ; ["Offset of field: cs_arm64_op::svcr"] [:: std :: mem :: offset_of ! (cs_arm64_op , svcr) - 24usize] ; ["Offset of field: cs_arm64_op::access"] [:: std :: mem :: offset_of ! (cs_arm64_op , access) - 48usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, svcr: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . svcr , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64 { # [doc = "< conditional code for this insn"] pub cc : arm64_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn request writeback? 'True' means 'yes'"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm64_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64"] [:: std :: mem :: size_of :: < cs_arm64 > () - 456usize] ; ["Alignment of cs_arm64"] [:: std :: mem :: align_of :: < cs_arm64 > () - 8usize] ; ["Offset of field: cs_arm64::cc"] [:: std :: mem :: offset_of ! (cs_arm64 , cc) - 0usize] ; ["Offset of field: cs_arm64::update_flags"] [:: std :: mem :: offset_of ! (cs_arm64 , update_flags) - 4usize] ; ["Offset of field: cs_arm64::writeback"] [:: std :: mem :: offset_of ! (cs_arm64 , writeback) - 5usize] ; ["Offset of field: cs_arm64::post_index"] [:: std :: mem :: offset_of ! (cs_arm64 , post_index) - 6usize] ; ["Offset of field: cs_arm64::op_count"] [:: std :: mem :: offset_of ! (cs_arm64 , op_count) - 7usize] ; ["Offset of field: cs_arm64::operands"] [:: std :: mem :: offset_of ! (cs_arm64 , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . post_index , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM64 instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn { ARM64_INS_INVALID = 0 , ARM64_INS_ABS = 1 , ARM64_INS_ADC = 2 , ARM64_INS_ADCLB = 3 , ARM64_INS_ADCLT = 4 , ARM64_INS_ADCS = 5 , ARM64_INS_ADD = 6 , ARM64_INS_ADDG = 7 , ARM64_INS_ADDHA = 8 , ARM64_INS_ADDHN = 9 , ARM64_INS_ADDHN2 = 10 , ARM64_INS_ADDHNB = 11 , ARM64_INS_ADDHNT = 12 , ARM64_INS_ADDP = 13 , ARM64_INS_ADDPL = 14 , ARM64_INS_ADDS = 15 , ARM64_INS_ADDV = 16 , ARM64_INS_ADDVA = 17 , ARM64_INS_ADDVL = 18 , ARM64_INS_ADR = 19 , ARM64_INS_ADRP = 20 , ARM64_INS_AESD = 21 , ARM64_INS_AESE = 22 , ARM64_INS_AESIMC = 23 , ARM64_INS_AESMC = 24 , ARM64_INS_AND = 25 , ARM64_INS_ANDS = 26 , ARM64_INS_ANDV = 27 , ARM64_INS_ASR = 28 , ARM64_INS_ASRD = 29 , ARM64_INS_ASRR = 30 , ARM64_INS_ASRV = 31 , ARM64_INS_AUTDA = 32 , ARM64_INS_AUTDB = 33 , ARM64_INS_AUTDZA = 34 , ARM64_INS_AUTDZB = 35 , ARM64_INS_AUTIA = 36 , ARM64_INS_AUTIA1716 = 37 , ARM64_INS_AUTIASP = 38 , ARM64_INS_AUTIAZ = 39 , ARM64_INS_AUTIB = 40 , ARM64_INS_AUTIB1716 = 41 , ARM64_INS_AUTIBSP = 42 , ARM64_INS_AUTIBZ = 43 , ARM64_INS_AUTIZA = 44 , ARM64_INS_AUTIZB = 45 , ARM64_INS_AXFLAG = 46 , ARM64_INS_B = 47 , ARM64_INS_BC = 48 , ARM64_INS_BCAX = 49 , ARM64_INS_BDEP = 50 , ARM64_INS_BEXT = 51 , ARM64_INS_BFCVT = 52 , ARM64_INS_BFCVTN = 53 , ARM64_INS_BFCVTN2 = 54 , ARM64_INS_BFCVTNT = 55 , ARM64_INS_BFDOT = 56 , ARM64_INS_BFM = 57 , ARM64_INS_BFMLALB = 58 , ARM64_INS_BFMLALT = 59 , ARM64_INS_BFMMLA = 60 , ARM64_INS_BFMOPA = 61 , ARM64_INS_BFMOPS = 62 , ARM64_INS_BGRP = 63 , ARM64_INS_BIC = 64 , ARM64_INS_BICS = 65 , ARM64_INS_BIF = 66 , ARM64_INS_BIT = 67 , ARM64_INS_BL = 68 , ARM64_INS_BLR = 69 , ARM64_INS_BLRAA = 70 , ARM64_INS_BLRAAZ = 71 , ARM64_INS_BLRAB = 72 , ARM64_INS_BLRABZ = 73 , ARM64_INS_BR = 74 , ARM64_INS_BRAA = 75 , ARM64_INS_BRAAZ = 76 , ARM64_INS_BRAB = 77 , ARM64_INS_BRABZ = 78 , ARM64_INS_BRB = 79 , ARM64_INS_BRK = 80 , ARM64_INS_BRKA = 81 , ARM64_INS_BRKAS = 82 , ARM64_INS_BRKB = 83 , ARM64_INS_BRKBS = 84 , ARM64_INS_BRKN = 85 , ARM64_INS_BRKNS = 86 , ARM64_INS_BRKPA = 87 , ARM64_INS_BRKPAS = 88 , ARM64_INS_BRKPB = 89 , ARM64_INS_BRKPBS = 90 , ARM64_INS_BSL = 91 , ARM64_INS_BSL1N = 92 , ARM64_INS_BSL2N = 93 , ARM64_INS_BTI = 94 , ARM64_INS_CADD = 95 , ARM64_INS_CAS = 96 , ARM64_INS_CASA = 97 , ARM64_INS_CASAB = 98 , ARM64_INS_CASAH = 99 , ARM64_INS_CASAL = 100 , ARM64_INS_CASALB = 101 , ARM64_INS_CASALH = 102 , ARM64_INS_CASB = 103 , ARM64_INS_CASH = 104 , ARM64_INS_CASL = 105 , ARM64_INS_CASLB = 106 , ARM64_INS_CASLH = 107 , ARM64_INS_CASP = 108 , ARM64_INS_CASPA = 109 , ARM64_INS_CASPAL = 110 , ARM64_INS_CASPL = 111 , ARM64_INS_CBNZ = 112 , ARM64_INS_CBZ = 113 , ARM64_INS_CCMN = 114 , ARM64_INS_CCMP = 115 , ARM64_INS_CDOT = 116 , ARM64_INS_CFINV = 117 , ARM64_INS_CINC = 118 , ARM64_INS_CINV = 119 , ARM64_INS_CLASTA = 120 , ARM64_INS_CLASTB = 121 , ARM64_INS_CLREX = 122 , ARM64_INS_CLS = 123 , ARM64_INS_CLZ = 124 , ARM64_INS_CMEQ = 125 , ARM64_INS_CMGE = 126 , ARM64_INS_CMGT = 127 , ARM64_INS_CMHI = 128 , ARM64_INS_CMHS = 129 , ARM64_INS_CMLA = 130 , ARM64_INS_CMLE = 131 , ARM64_INS_CMLO = 132 , ARM64_INS_CMLS = 133 , ARM64_INS_CMLT = 134 , ARM64_INS_CMN = 135 , ARM64_INS_CMP = 136 , ARM64_INS_CMPEQ = 137 , ARM64_INS_CMPGE = 138 , ARM64_INS_CMPGT = 139 , ARM64_INS_CMPHI = 140 , ARM64_INS_CMPHS = 141 , ARM64_INS_CMPLE = 142 , ARM64_INS_CMPLO = 143 , ARM64_INS_CMPLS = 144 , ARM64_INS_CMPLT = 145 , ARM64_INS_CMPNE = 146 , ARM64_INS_CMPP = 147 , ARM64_INS_CMTST = 148 , ARM64_INS_CNEG = 149 , ARM64_INS_CNOT = 150 , ARM64_INS_CNT = 151 , ARM64_INS_CNTB = 152 , ARM64_INS_CNTD = 153 , ARM64_INS_CNTH = 154 , ARM64_INS_CNTP = 155 , ARM64_INS_CNTW = 156 , ARM64_INS_COMPACT = 157 , ARM64_INS_CPY = 158 , ARM64_INS_CPYE = 159 , ARM64_INS_CPYEN = 160 , ARM64_INS_CPYERN = 161 , ARM64_INS_CPYERT = 162 , ARM64_INS_CPYERTN = 163 , ARM64_INS_CPYERTRN = 164 , ARM64_INS_CPYERTWN = 165 , ARM64_INS_CPYET = 166 , ARM64_INS_CPYETN = 167 , ARM64_INS_CPYETRN = 168 , ARM64_INS_CPYETWN = 169 , ARM64_INS_CPYEWN = 170 , ARM64_INS_CPYEWT = 171 , ARM64_INS_CPYEWTN = 172 , ARM64_INS_CPYEWTRN = 173 , ARM64_INS_CPYEWTWN = 174 , ARM64_INS_CPYFE = 175 , ARM64_INS_CPYFEN = 176 , ARM64_INS_CPYFERN = 177 , ARM64_INS_CPYFERT = 178 , ARM64_INS_CPYFERTN = 179 , ARM64_INS_CPYFERTRN = 180 , ARM64_INS_CPYFERTWN = 181 , ARM64_INS_CPYFET = 182 , ARM64_INS_CPYFETN = 183 , ARM64_INS_CPYFETRN = 184 , ARM64_INS_CPYFETWN = 185 , ARM64_INS_CPYFEWN = 186 , ARM64_INS_CPYFEWT = 187 , ARM64_INS_CPYFEWTN = 188 , ARM64_INS_CPYFEWTRN = 189 , ARM64_INS_CPYFEWTWN = 190 , ARM64_INS_CPYFM = 191 , ARM64_INS_CPYFMN = 192 , ARM64_INS_CPYFMRN = 193 , ARM64_INS_CPYFMRT = 194 , ARM64_INS_CPYFMRTN = 195 , ARM64_INS_CPYFMRTRN = 196 , ARM64_INS_CPYFMRTWN = 197 , ARM64_INS_CPYFMT = 198 , ARM64_INS_CPYFMTN = 199 , ARM64_INS_CPYFMTRN = 200 , ARM64_INS_CPYFMTWN = 201 , ARM64_INS_CPYFMWN = 202 , ARM64_INS_CPYFMWT = 203 , ARM64_INS_CPYFMWTN = 204 , ARM64_INS_CPYFMWTRN = 205 , ARM64_INS_CPYFMWTWN = 206 , ARM64_INS_CPYFP = 207 , ARM64_INS_CPYFPN = 208 , ARM64_INS_CPYFPRN = 209 , ARM64_INS_CPYFPRT = 210 , ARM64_INS_CPYFPRTN = 211 , ARM64_INS_CPYFPRTRN = 212 , ARM64_INS_CPYFPRTWN = 213 , ARM64_INS_CPYFPT = 214 , ARM64_INS_CPYFPTN = 215 , ARM64_INS_CPYFPTRN = 216 , ARM64_INS_CPYFPTWN = 217 , ARM64_INS_CPYFPWN = 218 , ARM64_INS_CPYFPWT = 219 , ARM64_INS_CPYFPWTN = 220 , ARM64_INS_CPYFPWTRN = 221 , ARM64_INS_CPYFPWTWN = 222 , ARM64_INS_CPYM = 223 , ARM64_INS_CPYMN = 224 , ARM64_INS_CPYMRN = 225 , ARM64_INS_CPYMRT = 226 , ARM64_INS_CPYMRTN = 227 , ARM64_INS_CPYMRTRN = 228 , ARM64_INS_CPYMRTWN = 229 , ARM64_INS_CPYMT = 230 , ARM64_INS_CPYMTN = 231 , ARM64_INS_CPYMTRN = 232 , ARM64_INS_CPYMTWN = 233 , ARM64_INS_CPYMWN = 234 , ARM64_INS_CPYMWT = 235 , ARM64_INS_CPYMWTN = 236 , ARM64_INS_CPYMWTRN = 237 , ARM64_INS_CPYMWTWN = 238 , ARM64_INS_CPYP = 239 , ARM64_INS_CPYPN = 240 , ARM64_INS_CPYPRN = 241 , ARM64_INS_CPYPRT = 242 , ARM64_INS_CPYPRTN = 243 , ARM64_INS_CPYPRTRN = 244 , ARM64_INS_CPYPRTWN = 245 , ARM64_INS_CPYPT = 246 , ARM64_INS_CPYPTN = 247 , ARM64_INS_CPYPTRN = 248 , ARM64_INS_CPYPTWN = 249 , ARM64_INS_CPYPWN = 250 , ARM64_INS_CPYPWT = 251 , ARM64_INS_CPYPWTN = 252 , ARM64_INS_CPYPWTRN = 253 , ARM64_INS_CPYPWTWN = 254 , ARM64_INS_CRC32B = 255 , ARM64_INS_CRC32CB = 256 , ARM64_INS_CRC32CH = 257 , ARM64_INS_CRC32CW = 258 , ARM64_INS_CRC32CX = 259 , ARM64_INS_CRC32H = 260 , ARM64_INS_CRC32W = 261 , ARM64_INS_CRC32X = 262 , ARM64_INS_CSDB = 263 , ARM64_INS_CSEL = 264 , ARM64_INS_CSET = 265 , ARM64_INS_CSETM = 266 , ARM64_INS_CSINC = 267 , ARM64_INS_CSINV = 268 , ARM64_INS_CSNEG = 269 , ARM64_INS_CTERMEQ = 270 , ARM64_INS_CTERMNE = 271 , ARM64_INS_DCPS1 = 272 , ARM64_INS_DCPS2 = 273 , ARM64_INS_DCPS3 = 274 , ARM64_INS_DECB = 275 , ARM64_INS_DECD = 276 , ARM64_INS_DECH = 277 , ARM64_INS_DECP = 278 , ARM64_INS_DECW = 279 , ARM64_INS_DFB = 280 , ARM64_INS_DGH = 281 , ARM64_INS_DMB = 282 , ARM64_INS_DRPS = 283 , ARM64_INS_DSB = 284 , ARM64_INS_DUP = 285 , ARM64_INS_DUPM = 286 , ARM64_INS_EON = 287 , ARM64_INS_EOR = 288 , ARM64_INS_EOR3 = 289 , ARM64_INS_EORBT = 290 , ARM64_INS_EORS = 291 , ARM64_INS_EORTB = 292 , ARM64_INS_EORV = 293 , ARM64_INS_ERET = 294 , ARM64_INS_ERETAA = 295 , ARM64_INS_ERETAB = 296 , ARM64_INS_ESB = 297 , ARM64_INS_EXT = 298 , ARM64_INS_EXTR = 299 , ARM64_INS_FABD = 300 , ARM64_INS_FABS = 301 , ARM64_INS_FACGE = 302 , ARM64_INS_FACGT = 303 , ARM64_INS_FACLE = 304 , ARM64_INS_FACLT = 305 , ARM64_INS_FADD = 306 , ARM64_INS_FADDA = 307 , ARM64_INS_FADDP = 308 , ARM64_INS_FADDV = 309 , ARM64_INS_FCADD = 310 , ARM64_INS_FCCMP = 311 , ARM64_INS_FCCMPE = 312 , ARM64_INS_FCMEQ = 313 , ARM64_INS_FCMGE = 314 , ARM64_INS_FCMGT = 315 , ARM64_INS_FCMLA = 316 , ARM64_INS_FCMLE = 317 , ARM64_INS_FCMLT = 318 , ARM64_INS_FCMNE = 319 , ARM64_INS_FCMP = 320 , ARM64_INS_FCMPE = 321 , ARM64_INS_FCMUO = 322 , ARM64_INS_FCPY = 323 , ARM64_INS_FCSEL = 324 , ARM64_INS_FCVT = 325 , ARM64_INS_FCVTAS = 326 , ARM64_INS_FCVTAU = 327 , ARM64_INS_FCVTL = 328 , ARM64_INS_FCVTL2 = 329 , ARM64_INS_FCVTLT = 330 , ARM64_INS_FCVTMS = 331 , ARM64_INS_FCVTMU = 332 , ARM64_INS_FCVTN = 333 , ARM64_INS_FCVTN2 = 334 , ARM64_INS_FCVTNS = 335 , ARM64_INS_FCVTNT = 336 , ARM64_INS_FCVTNU = 337 , ARM64_INS_FCVTPS = 338 , ARM64_INS_FCVTPU = 339 , ARM64_INS_FCVTX = 340 , ARM64_INS_FCVTXN = 341 , ARM64_INS_FCVTXN2 = 342 , ARM64_INS_FCVTXNT = 343 , ARM64_INS_FCVTZS = 344 , ARM64_INS_FCVTZU = 345 , ARM64_INS_FDIV = 346 , ARM64_INS_FDIVR = 347 , ARM64_INS_FDUP = 348 , ARM64_INS_FEXPA = 349 , ARM64_INS_FJCVTZS = 350 , ARM64_INS_FLOGB = 351 , ARM64_INS_FMAD = 352 , ARM64_INS_FMADD = 353 , ARM64_INS_FMAX = 354 , ARM64_INS_FMAXNM = 355 , ARM64_INS_FMAXNMP = 356 , ARM64_INS_FMAXNMV = 357 , ARM64_INS_FMAXP = 358 , ARM64_INS_FMAXV = 359 , ARM64_INS_FMIN = 360 , ARM64_INS_FMINNM = 361 , ARM64_INS_FMINNMP = 362 , ARM64_INS_FMINNMV = 363 , ARM64_INS_FMINP = 364 , ARM64_INS_FMINV = 365 , ARM64_INS_FMLA = 366 , ARM64_INS_FMLAL = 367 , ARM64_INS_FMLAL2 = 368 , ARM64_INS_FMLALB = 369 , ARM64_INS_FMLALT = 370 , ARM64_INS_FMLS = 371 , ARM64_INS_FMLSL = 372 , ARM64_INS_FMLSL2 = 373 , ARM64_INS_FMLSLB = 374 , ARM64_INS_FMLSLT = 375 , ARM64_INS_FMMLA = 376 , ARM64_INS_FMOPA = 377 , ARM64_INS_FMOPS = 378 , ARM64_INS_FMOV = 379 , ARM64_INS_FMSB = 380 , ARM64_INS_FMSUB = 381 , ARM64_INS_FMUL = 382 , ARM64_INS_FMULX = 383 , ARM64_INS_FNEG = 384 , ARM64_INS_FNMAD = 385 , ARM64_INS_FNMADD = 386 , ARM64_INS_FNMLA = 387 , ARM64_INS_FNMLS = 388 , ARM64_INS_FNMSB = 389 , ARM64_INS_FNMSUB = 390 , ARM64_INS_FNMUL = 391 , ARM64_INS_FRECPE = 392 , ARM64_INS_FRECPS = 393 , ARM64_INS_FRECPX = 394 , ARM64_INS_FRINT32X = 395 , ARM64_INS_FRINT32Z = 396 , ARM64_INS_FRINT64X = 397 , ARM64_INS_FRINT64Z = 398 , ARM64_INS_FRINTA = 399 , ARM64_INS_FRINTI = 400 , ARM64_INS_FRINTM = 401 , ARM64_INS_FRINTN = 402 , ARM64_INS_FRINTP = 403 , ARM64_INS_FRINTX = 404 , ARM64_INS_FRINTZ = 405 , ARM64_INS_FRSQRTE = 406 , ARM64_INS_FRSQRTS = 407 , ARM64_INS_FSCALE = 408 , ARM64_INS_FSQRT = 409 , ARM64_INS_FSUB = 410 , ARM64_INS_FSUBR = 411 , ARM64_INS_FTMAD = 412 , ARM64_INS_FTSMUL = 413 , ARM64_INS_FTSSEL = 414 , ARM64_INS_GMI = 415 , ARM64_INS_HINT = 416 , ARM64_INS_HISTCNT = 417 , ARM64_INS_HISTSEG = 418 , ARM64_INS_HLT = 419 , ARM64_INS_HVC = 420 , ARM64_INS_INCB = 421 , ARM64_INS_INCD = 422 , ARM64_INS_INCH = 423 , ARM64_INS_INCP = 424 , ARM64_INS_INCW = 425 , ARM64_INS_INDEX = 426 , ARM64_INS_INS = 427 , ARM64_INS_INSR = 428 , ARM64_INS_IRG = 429 , ARM64_INS_ISB = 430 , ARM64_INS_LASTA = 431 , ARM64_INS_LASTB = 432 , ARM64_INS_LD1 = 433 , ARM64_INS_LD1B = 434 , ARM64_INS_LD1D = 435 , ARM64_INS_LD1H = 436 , ARM64_INS_LD1Q = 437 , ARM64_INS_LD1R = 438 , ARM64_INS_LD1RB = 439 , ARM64_INS_LD1RD = 440 , ARM64_INS_LD1RH = 441 , ARM64_INS_LD1ROB = 442 , ARM64_INS_LD1ROD = 443 , ARM64_INS_LD1ROH = 444 , ARM64_INS_LD1ROW = 445 , ARM64_INS_LD1RQB = 446 , ARM64_INS_LD1RQD = 447 , ARM64_INS_LD1RQH = 448 , ARM64_INS_LD1RQW = 449 , ARM64_INS_LD1RSB = 450 , ARM64_INS_LD1RSH = 451 , ARM64_INS_LD1RSW = 452 , ARM64_INS_LD1RW = 453 , ARM64_INS_LD1SB = 454 , ARM64_INS_LD1SH = 455 , ARM64_INS_LD1SW = 456 , ARM64_INS_LD1W = 457 , ARM64_INS_LD2 = 458 , ARM64_INS_LD2B = 459 , ARM64_INS_LD2D = 460 , ARM64_INS_LD2H = 461 , ARM64_INS_LD2R = 462 , ARM64_INS_LD2W = 463 , ARM64_INS_LD3 = 464 , ARM64_INS_LD3B = 465 , ARM64_INS_LD3D = 466 , ARM64_INS_LD3H = 467 , ARM64_INS_LD3R = 468 , ARM64_INS_LD3W = 469 , ARM64_INS_LD4 = 470 , ARM64_INS_LD4B = 471 , ARM64_INS_LD4D = 472 , ARM64_INS_LD4H = 473 , ARM64_INS_LD4R = 474 , ARM64_INS_LD4W = 475 , ARM64_INS_LD64B = 476 , ARM64_INS_LDADD = 477 , ARM64_INS_LDADDA = 478 , ARM64_INS_LDADDAB = 479 , ARM64_INS_LDADDAH = 480 , ARM64_INS_LDADDAL = 481 , ARM64_INS_LDADDALB = 482 , ARM64_INS_LDADDALH = 483 , ARM64_INS_LDADDB = 484 , ARM64_INS_LDADDH = 485 , ARM64_INS_LDADDL = 486 , ARM64_INS_LDADDLB = 487 , ARM64_INS_LDADDLH = 488 , ARM64_INS_LDAPR = 489 , ARM64_INS_LDAPRB = 490 , ARM64_INS_LDAPRH = 491 , ARM64_INS_LDAPUR = 492 , ARM64_INS_LDAPURB = 493 , ARM64_INS_LDAPURH = 494 , ARM64_INS_LDAPURSB = 495 , ARM64_INS_LDAPURSH = 496 , ARM64_INS_LDAPURSW = 497 , ARM64_INS_LDAR = 498 , ARM64_INS_LDARB = 499 , ARM64_INS_LDARH = 500 , ARM64_INS_LDAXP = 501 , ARM64_INS_LDAXR = 502 , ARM64_INS_LDAXRB = 503 , ARM64_INS_LDAXRH = 504 , ARM64_INS_LDCLR = 505 , ARM64_INS_LDCLRA = 506 , ARM64_INS_LDCLRAB = 507 , ARM64_INS_LDCLRAH = 508 , ARM64_INS_LDCLRAL = 509 , ARM64_INS_LDCLRALB = 510 , ARM64_INS_LDCLRALH = 511 , ARM64_INS_LDCLRB = 512 , ARM64_INS_LDCLRH = 513 , ARM64_INS_LDCLRL = 514 , ARM64_INS_LDCLRLB = 515 , ARM64_INS_LDCLRLH = 516 , ARM64_INS_LDEOR = 517 , ARM64_INS_LDEORA = 518 , ARM64_INS_LDEORAB = 519 , ARM64_INS_LDEORAH = 520 , ARM64_INS_LDEORAL = 521 , ARM64_INS_LDEORALB = 522 , ARM64_INS_LDEORALH = 523 , ARM64_INS_LDEORB = 524 , ARM64_INS_LDEORH = 525 , ARM64_INS_LDEORL = 526 , ARM64_INS_LDEORLB = 527 , ARM64_INS_LDEORLH = 528 , ARM64_INS_LDFF1B = 529 , ARM64_INS_LDFF1D = 530 , ARM64_INS_LDFF1H = 531 , ARM64_INS_LDFF1SB = 532 , ARM64_INS_LDFF1SH = 533 , ARM64_INS_LDFF1SW = 534 , ARM64_INS_LDFF1W = 535 , ARM64_INS_LDG = 536 , ARM64_INS_LDGM = 537 , ARM64_INS_LDLAR = 538 , ARM64_INS_LDLARB = 539 , ARM64_INS_LDLARH = 540 , ARM64_INS_LDNF1B = 541 , ARM64_INS_LDNF1D = 542 , ARM64_INS_LDNF1H = 543 , ARM64_INS_LDNF1SB = 544 , ARM64_INS_LDNF1SH = 545 , ARM64_INS_LDNF1SW = 546 , ARM64_INS_LDNF1W = 547 , ARM64_INS_LDNP = 548 , ARM64_INS_LDNT1B = 549 , ARM64_INS_LDNT1D = 550 , ARM64_INS_LDNT1H = 551 , ARM64_INS_LDNT1SB = 552 , ARM64_INS_LDNT1SH = 553 , ARM64_INS_LDNT1SW = 554 , ARM64_INS_LDNT1W = 555 , ARM64_INS_LDP = 556 , ARM64_INS_LDPSW = 557 , ARM64_INS_LDR = 558 , ARM64_INS_LDRAA = 559 , ARM64_INS_LDRAB = 560 , ARM64_INS_LDRB = 561 , ARM64_INS_LDRH = 562 , ARM64_INS_LDRSB = 563 , ARM64_INS_LDRSH = 564 , ARM64_INS_LDRSW = 565 , ARM64_INS_LDSET = 566 , ARM64_INS_LDSETA = 567 , ARM64_INS_LDSETAB = 568 , ARM64_INS_LDSETAH = 569 , ARM64_INS_LDSETAL = 570 , ARM64_INS_LDSETALB = 571 , ARM64_INS_LDSETALH = 572 , ARM64_INS_LDSETB = 573 , ARM64_INS_LDSETH = 574 , ARM64_INS_LDSETL = 575 , ARM64_INS_LDSETLB = 576 , ARM64_INS_LDSETLH = 577 , ARM64_INS_LDSMAX = 578 , ARM64_INS_LDSMAXA = 579 , ARM64_INS_LDSMAXAB = 580 , ARM64_INS_LDSMAXAH = 581 , ARM64_INS_LDSMAXAL = 582 , ARM64_INS_LDSMAXALB = 583 , ARM64_INS_LDSMAXALH = 584 , ARM64_INS_LDSMAXB = 585 , ARM64_INS_LDSMAXH = 586 , ARM64_INS_LDSMAXL = 587 , ARM64_INS_LDSMAXLB = 588 , ARM64_INS_LDSMAXLH = 589 , ARM64_INS_LDSMIN = 590 , ARM64_INS_LDSMINA = 591 , ARM64_INS_LDSMINAB = 592 , ARM64_INS_LDSMINAH = 593 , ARM64_INS_LDSMINAL = 594 , ARM64_INS_LDSMINALB = 595 , ARM64_INS_LDSMINALH = 596 , ARM64_INS_LDSMINB = 597 , ARM64_INS_LDSMINH = 598 , ARM64_INS_LDSMINL = 599 , ARM64_INS_LDSMINLB = 600 , ARM64_INS_LDSMINLH = 601 , ARM64_INS_LDTR = 602 , ARM64_INS_LDTRB = 603 , ARM64_INS_LDTRH = 604 , ARM64_INS_LDTRSB = 605 , ARM64_INS_LDTRSH = 606 , ARM64_INS_LDTRSW = 607 , ARM64_INS_LDUMAX = 608 , ARM64_INS_LDUMAXA = 609 , ARM64_INS_LDUMAXAB = 610 , ARM64_INS_LDUMAXAH = 611 , ARM64_INS_LDUMAXAL = 612 , ARM64_INS_LDUMAXALB = 613 , ARM64_INS_LDUMAXALH = 614 , ARM64_INS_LDUMAXB = 615 , ARM64_INS_LDUMAXH = 616 , ARM64_INS_LDUMAXL = 617 , ARM64_INS_LDUMAXLB = 618 , ARM64_INS_LDUMAXLH = 619 , ARM64_INS_LDUMIN = 620 , ARM64_INS_LDUMINA = 621 , ARM64_INS_LDUMINAB = 622 , ARM64_INS_LDUMINAH = 623 , ARM64_INS_LDUMINAL = 624 , ARM64_INS_LDUMINALB = 625 , ARM64_INS_LDUMINALH = 626 , ARM64_INS_LDUMINB = 627 , ARM64_INS_LDUMINH = 628 , ARM64_INS_LDUMINL = 629 , ARM64_INS_LDUMINLB = 630 , ARM64_INS_LDUMINLH = 631 , ARM64_INS_LDUR = 632 , ARM64_INS_LDURB = 633 , ARM64_INS_LDURH = 634 , ARM64_INS_LDURSB = 635 , ARM64_INS_LDURSH = 636 , ARM64_INS_LDURSW = 637 , ARM64_INS_LDXP = 638 , ARM64_INS_LDXR = 639 , ARM64_INS_LDXRB = 640 , ARM64_INS_LDXRH = 641 , ARM64_INS_LSL = 642 , ARM64_INS_LSLR = 643 , ARM64_INS_LSLV = 644 , ARM64_INS_LSR = 645 , ARM64_INS_LSRR = 646 , ARM64_INS_LSRV = 647 , ARM64_INS_MAD = 648 , ARM64_INS_MADD = 649 , ARM64_INS_MATCH = 650 , ARM64_INS_MLA = 651 , ARM64_INS_MLS = 652 , ARM64_INS_MNEG = 653 , ARM64_INS_MOV = 654 , ARM64_INS_MOVA = 655 , ARM64_INS_MOVI = 656 , ARM64_INS_MOVK = 657 , ARM64_INS_MOVN = 658 , ARM64_INS_MOVPRFX = 659 , ARM64_INS_MOVS = 660 , ARM64_INS_MOVZ = 661 , ARM64_INS_MRS = 662 , ARM64_INS_MSB = 663 , ARM64_INS_MSR = 664 , ARM64_INS_MSUB = 665 , ARM64_INS_MUL = 666 , ARM64_INS_MVN = 667 , ARM64_INS_MVNI = 668 , ARM64_INS_NAND = 669 , ARM64_INS_NANDS = 670 , ARM64_INS_NBSL = 671 , ARM64_INS_NEG = 672 , ARM64_INS_NEGS = 673 , ARM64_INS_NGC = 674 , ARM64_INS_NGCS = 675 , ARM64_INS_NMATCH = 676 , ARM64_INS_NOP = 677 , ARM64_INS_NOR = 678 , ARM64_INS_NORS = 679 , ARM64_INS_NOT = 680 , ARM64_INS_NOTS = 681 , ARM64_INS_ORN = 682 , ARM64_INS_ORNS = 683 , ARM64_INS_ORR = 684 , ARM64_INS_ORRS = 685 , ARM64_INS_ORV = 686 , ARM64_INS_PACDA = 687 , ARM64_INS_PACDB = 688 , ARM64_INS_PACDZA = 689 , ARM64_INS_PACDZB = 690 , ARM64_INS_PACGA = 691 , ARM64_INS_PACIA = 692 , ARM64_INS_PACIA1716 = 693 , ARM64_INS_PACIASP = 694 , ARM64_INS_PACIAZ = 695 , ARM64_INS_PACIB = 696 , ARM64_INS_PACIB1716 = 697 , ARM64_INS_PACIBSP = 698 , ARM64_INS_PACIBZ = 699 , ARM64_INS_PACIZA = 700 , ARM64_INS_PACIZB = 701 , ARM64_INS_PFALSE = 702 , ARM64_INS_PFIRST = 703 , ARM64_INS_PMUL = 704 , ARM64_INS_PMULL = 705 , ARM64_INS_PMULL2 = 706 , ARM64_INS_PMULLB = 707 , ARM64_INS_PMULLT = 708 , ARM64_INS_PNEXT = 709 , ARM64_INS_PRFB = 710 , ARM64_INS_PRFD = 711 , ARM64_INS_PRFH = 712 , ARM64_INS_PRFM = 713 , ARM64_INS_PRFUM = 714 , ARM64_INS_PRFW = 715 , ARM64_INS_PSB = 716 , ARM64_INS_PSEL = 717 , ARM64_INS_PSSBB = 718 , ARM64_INS_PTEST = 719 , ARM64_INS_PTRUE = 720 , ARM64_INS_PTRUES = 721 , ARM64_INS_PUNPKHI = 722 , ARM64_INS_PUNPKLO = 723 , ARM64_INS_RADDHN = 724 , ARM64_INS_RADDHN2 = 725 , ARM64_INS_RADDHNB = 726 , ARM64_INS_RADDHNT = 727 , ARM64_INS_RAX1 = 728 , ARM64_INS_RBIT = 729 , ARM64_INS_RDFFR = 730 , ARM64_INS_RDFFRS = 731 , ARM64_INS_RDVL = 732 , ARM64_INS_RET = 733 , ARM64_INS_RETAA = 734 , ARM64_INS_RETAB = 735 , ARM64_INS_REV = 736 , ARM64_INS_REV16 = 737 , ARM64_INS_REV32 = 738 , ARM64_INS_REV64 = 739 , ARM64_INS_REVB = 740 , ARM64_INS_REVD = 741 , ARM64_INS_REVH = 742 , ARM64_INS_REVW = 743 , ARM64_INS_RMIF = 744 , ARM64_INS_ROR = 745 , ARM64_INS_RORV = 746 , ARM64_INS_RSHRN = 747 , ARM64_INS_RSHRN2 = 748 , ARM64_INS_RSHRNB = 749 , ARM64_INS_RSHRNT = 750 , ARM64_INS_RSUBHN = 751 , ARM64_INS_RSUBHN2 = 752 , ARM64_INS_RSUBHNB = 753 , ARM64_INS_RSUBHNT = 754 , ARM64_INS_SABA = 755 , ARM64_INS_SABAL = 756 , ARM64_INS_SABAL2 = 757 , ARM64_INS_SABALB = 758 , ARM64_INS_SABALT = 759 , ARM64_INS_SABD = 760 , ARM64_INS_SABDL = 761 , ARM64_INS_SABDL2 = 762 , ARM64_INS_SABDLB = 763 , ARM64_INS_SABDLT = 764 , ARM64_INS_SADALP = 765 , ARM64_INS_SADDL = 766 , ARM64_INS_SADDL2 = 767 , ARM64_INS_SADDLB = 768 , ARM64_INS_SADDLBT = 769 , ARM64_INS_SADDLP = 770 , ARM64_INS_SADDLT = 771 , ARM64_INS_SADDLV = 772 , ARM64_INS_SADDV = 773 , ARM64_INS_SADDW = 774 , ARM64_INS_SADDW2 = 775 , ARM64_INS_SADDWB = 776 , ARM64_INS_SADDWT = 777 , ARM64_INS_SB = 778 , ARM64_INS_SBC = 779 , ARM64_INS_SBCLB = 780 , ARM64_INS_SBCLT = 781 , ARM64_INS_SBCS = 782 , ARM64_INS_SBFM = 783 , ARM64_INS_SCLAMP = 784 , ARM64_INS_SCVTF = 785 , ARM64_INS_SDIV = 786 , ARM64_INS_SDIVR = 787 , ARM64_INS_SDOT = 788 , ARM64_INS_SEL = 789 , ARM64_INS_SETE = 790 , ARM64_INS_SETEN = 791 , ARM64_INS_SETET = 792 , ARM64_INS_SETETN = 793 , ARM64_INS_SETF16 = 794 , ARM64_INS_SETF8 = 795 , ARM64_INS_SETFFR = 796 , ARM64_INS_SETGE = 797 , ARM64_INS_SETGEN = 798 , ARM64_INS_SETGET = 799 , ARM64_INS_SETGETN = 800 , ARM64_INS_SETGM = 801 , ARM64_INS_SETGMN = 802 , ARM64_INS_SETGMT = 803 , ARM64_INS_SETGMTN = 804 , ARM64_INS_SETGP = 805 , ARM64_INS_SETGPN = 806 , ARM64_INS_SETGPT = 807 , ARM64_INS_SETGPTN = 808 , ARM64_INS_SETM = 809 , ARM64_INS_SETMN = 810 , ARM64_INS_SETMT = 811 , ARM64_INS_SETMTN = 812 , ARM64_INS_SETP = 813 , ARM64_INS_SETPN = 814 , ARM64_INS_SETPT = 815 , ARM64_INS_SETPTN = 816 , ARM64_INS_SEV = 817 , ARM64_INS_SEVL = 818 , ARM64_INS_SHA1C = 819 , ARM64_INS_SHA1H = 820 , ARM64_INS_SHA1M = 821 , ARM64_INS_SHA1P = 822 , ARM64_INS_SHA1SU0 = 823 , ARM64_INS_SHA1SU1 = 824 , ARM64_INS_SHA256H = 825 , ARM64_INS_SHA256H2 = 826 , ARM64_INS_SHA256SU0 = 827 , ARM64_INS_SHA256SU1 = 828 , ARM64_INS_SHA512H = 829 , ARM64_INS_SHA512H2 = 830 , ARM64_INS_SHA512SU0 = 831 , ARM64_INS_SHA512SU1 = 832 , ARM64_INS_SHADD = 833 , ARM64_INS_SHL = 834 , ARM64_INS_SHLL = 835 , ARM64_INS_SHLL2 = 836 , ARM64_INS_SHRN = 837 , ARM64_INS_SHRN2 = 838 , ARM64_INS_SHRNB = 839 , ARM64_INS_SHRNT = 840 , ARM64_INS_SHSUB = 841 , ARM64_INS_SHSUBR = 842 , ARM64_INS_SLI = 843 , ARM64_INS_SM3PARTW1 = 844 , ARM64_INS_SM3PARTW2 = 845 , ARM64_INS_SM3SS1 = 846 , ARM64_INS_SM3TT1A = 847 , ARM64_INS_SM3TT1B = 848 , ARM64_INS_SM3TT2A = 849 , ARM64_INS_SM3TT2B = 850 , ARM64_INS_SM4E = 851 , ARM64_INS_SM4EKEY = 852 , ARM64_INS_SMADDL = 853 , ARM64_INS_SMAX = 854 , ARM64_INS_SMAXP = 855 , ARM64_INS_SMAXV = 856 , ARM64_INS_SMC = 857 , ARM64_INS_SMIN = 858 , ARM64_INS_SMINP = 859 , ARM64_INS_SMINV = 860 , ARM64_INS_SMLAL = 861 , ARM64_INS_SMLAL2 = 862 , ARM64_INS_SMLALB = 863 , ARM64_INS_SMLALT = 864 , ARM64_INS_SMLSL = 865 , ARM64_INS_SMLSL2 = 866 , ARM64_INS_SMLSLB = 867 , ARM64_INS_SMLSLT = 868 , ARM64_INS_SMMLA = 869 , ARM64_INS_SMNEGL = 870 , ARM64_INS_SMOPA = 871 , ARM64_INS_SMOPS = 872 , ARM64_INS_SMOV = 873 , ARM64_INS_SMSTART = 874 , ARM64_INS_SMSTOP = 875 , ARM64_INS_SMSUBL = 876 , ARM64_INS_SMULH = 877 , ARM64_INS_SMULL = 878 , ARM64_INS_SMULL2 = 879 , ARM64_INS_SMULLB = 880 , ARM64_INS_SMULLT = 881 , ARM64_INS_SPLICE = 882 , ARM64_INS_SQABS = 883 , ARM64_INS_SQADD = 884 , ARM64_INS_SQCADD = 885 , ARM64_INS_SQDECB = 886 , ARM64_INS_SQDECD = 887 , ARM64_INS_SQDECH = 888 , ARM64_INS_SQDECP = 889 , ARM64_INS_SQDECW = 890 , ARM64_INS_SQDMLAL = 891 , ARM64_INS_SQDMLAL2 = 892 , ARM64_INS_SQDMLALB = 893 , ARM64_INS_SQDMLALBT = 894 , ARM64_INS_SQDMLALT = 895 , ARM64_INS_SQDMLSL = 896 , ARM64_INS_SQDMLSL2 = 897 , ARM64_INS_SQDMLSLB = 898 , ARM64_INS_SQDMLSLBT = 899 , ARM64_INS_SQDMLSLT = 900 , ARM64_INS_SQDMULH = 901 , ARM64_INS_SQDMULL = 902 , ARM64_INS_SQDMULL2 = 903 , ARM64_INS_SQDMULLB = 904 , ARM64_INS_SQDMULLT = 905 , ARM64_INS_SQINCB = 906 , ARM64_INS_SQINCD = 907 , ARM64_INS_SQINCH = 908 , ARM64_INS_SQINCP = 909 , ARM64_INS_SQINCW = 910 , ARM64_INS_SQNEG = 911 , ARM64_INS_SQRDCMLAH = 912 , ARM64_INS_SQRDMLAH = 913 , ARM64_INS_SQRDMLSH = 914 , ARM64_INS_SQRDMULH = 915 , ARM64_INS_SQRSHL = 916 , ARM64_INS_SQRSHLR = 917 , ARM64_INS_SQRSHRN = 918 , ARM64_INS_SQRSHRN2 = 919 , ARM64_INS_SQRSHRNB = 920 , ARM64_INS_SQRSHRNT = 921 , ARM64_INS_SQRSHRUN = 922 , ARM64_INS_SQRSHRUN2 = 923 , ARM64_INS_SQRSHRUNB = 924 , ARM64_INS_SQRSHRUNT = 925 , ARM64_INS_SQSHL = 926 , ARM64_INS_SQSHLR = 927 , ARM64_INS_SQSHLU = 928 , ARM64_INS_SQSHRN = 929 , ARM64_INS_SQSHRN2 = 930 , ARM64_INS_SQSHRNB = 931 , ARM64_INS_SQSHRNT = 932 , ARM64_INS_SQSHRUN = 933 , ARM64_INS_SQSHRUN2 = 934 , ARM64_INS_SQSHRUNB = 935 , ARM64_INS_SQSHRUNT = 936 , ARM64_INS_SQSUB = 937 , ARM64_INS_SQSUBR = 938 , ARM64_INS_SQXTN = 939 , ARM64_INS_SQXTN2 = 940 , ARM64_INS_SQXTNB = 941 , ARM64_INS_SQXTNT = 942 , ARM64_INS_SQXTUN = 943 , ARM64_INS_SQXTUN2 = 944 , ARM64_INS_SQXTUNB = 945 , ARM64_INS_SQXTUNT = 946 , ARM64_INS_SRHADD = 947 , ARM64_INS_SRI = 948 , ARM64_INS_SRSHL = 949 , ARM64_INS_SRSHLR = 950 , ARM64_INS_SRSHR = 951 , ARM64_INS_SRSRA = 952 , ARM64_INS_SSBB = 953 , ARM64_INS_SSHL = 954 , ARM64_INS_SSHLL = 955 , ARM64_INS_SSHLL2 = 956 , ARM64_INS_SSHLLB = 957 , ARM64_INS_SSHLLT = 958 , ARM64_INS_SSHR = 959 , ARM64_INS_SSRA = 960 , ARM64_INS_SSUBL = 961 , ARM64_INS_SSUBL2 = 962 , ARM64_INS_SSUBLB = 963 , ARM64_INS_SSUBLBT = 964 , ARM64_INS_SSUBLT = 965 , ARM64_INS_SSUBLTB = 966 , ARM64_INS_SSUBW = 967 , ARM64_INS_SSUBW2 = 968 , ARM64_INS_SSUBWB = 969 , ARM64_INS_SSUBWT = 970 , ARM64_INS_ST1 = 971 , ARM64_INS_ST1B = 972 , ARM64_INS_ST1D = 973 , ARM64_INS_ST1H = 974 , ARM64_INS_ST1Q = 975 , ARM64_INS_ST1W = 976 , ARM64_INS_ST2 = 977 , ARM64_INS_ST2B = 978 , ARM64_INS_ST2D = 979 , ARM64_INS_ST2G = 980 , ARM64_INS_ST2H = 981 , ARM64_INS_ST2W = 982 , ARM64_INS_ST3 = 983 , ARM64_INS_ST3B = 984 , ARM64_INS_ST3D = 985 , ARM64_INS_ST3H = 986 , ARM64_INS_ST3W = 987 , ARM64_INS_ST4 = 988 , ARM64_INS_ST4B = 989 , ARM64_INS_ST4D = 990 , ARM64_INS_ST4H = 991 , ARM64_INS_ST4W = 992 , ARM64_INS_ST64B = 993 , ARM64_INS_ST64BV = 994 , ARM64_INS_ST64BV0 = 995 , ARM64_INS_STADD = 996 , ARM64_INS_STADDB = 997 , ARM64_INS_STADDH = 998 , ARM64_INS_STADDL = 999 , ARM64_INS_STADDLB = 1000 , ARM64_INS_STADDLH = 1001 , ARM64_INS_STCLR = 1002 , ARM64_INS_STCLRB = 1003 , ARM64_INS_STCLRH = 1004 , ARM64_INS_STCLRL = 1005 , ARM64_INS_STCLRLB = 1006 , ARM64_INS_STCLRLH = 1007 , ARM64_INS_STEOR = 1008 , ARM64_INS_STEORB = 1009 , ARM64_INS_STEORH = 1010 , ARM64_INS_STEORL = 1011 , ARM64_INS_STEORLB = 1012 , ARM64_INS_STEORLH = 1013 , ARM64_INS_STG = 1014 , ARM64_INS_STGM = 1015 , ARM64_INS_STGP = 1016 , ARM64_INS_STLLR = 1017 , ARM64_INS_STLLRB = 1018 , ARM64_INS_STLLRH = 1019 , ARM64_INS_STLR = 1020 , ARM64_INS_STLRB = 1021 , ARM64_INS_STLRH = 1022 , ARM64_INS_STLUR = 1023 , ARM64_INS_STLURB = 1024 , ARM64_INS_STLURH = 1025 , ARM64_INS_STLXP = 1026 , ARM64_INS_STLXR = 1027 , ARM64_INS_STLXRB = 1028 , ARM64_INS_STLXRH = 1029 , ARM64_INS_STNP = 1030 , ARM64_INS_STNT1B = 1031 , ARM64_INS_STNT1D = 1032 , ARM64_INS_STNT1H = 1033 , ARM64_INS_STNT1W = 1034 , ARM64_INS_STP = 1035 , ARM64_INS_STR = 1036 , ARM64_INS_STRB = 1037 , ARM64_INS_STRH = 1038 , ARM64_INS_STSET = 1039 , ARM64_INS_STSETB = 1040 , ARM64_INS_STSETH = 1041 , ARM64_INS_STSETL = 1042 , ARM64_INS_STSETLB = 1043 , ARM64_INS_STSETLH = 1044 , ARM64_INS_STSMAX = 1045 , ARM64_INS_STSMAXB = 1046 , ARM64_INS_STSMAXH = 1047 , ARM64_INS_STSMAXL = 1048 , ARM64_INS_STSMAXLB = 1049 , ARM64_INS_STSMAXLH = 1050 , ARM64_INS_STSMIN = 1051 , ARM64_INS_STSMINB = 1052 , ARM64_INS_STSMINH = 1053 , ARM64_INS_STSMINL = 1054 , ARM64_INS_STSMINLB = 1055 , ARM64_INS_STSMINLH = 1056 , ARM64_INS_STTR = 1057 , ARM64_INS_STTRB = 1058 , ARM64_INS_STTRH = 1059 , ARM64_INS_STUMAX = 1060 , ARM64_INS_STUMAXB = 1061 , ARM64_INS_STUMAXH = 1062 , ARM64_INS_STUMAXL = 1063 , ARM64_INS_STUMAXLB = 1064 , ARM64_INS_STUMAXLH = 1065 , ARM64_INS_STUMIN = 1066 , ARM64_INS_STUMINB = 1067 , ARM64_INS_STUMINH = 1068 , ARM64_INS_STUMINL = 1069 , ARM64_INS_STUMINLB = 1070 , ARM64_INS_STUMINLH = 1071 , ARM64_INS_STUR = 1072 , ARM64_INS_STURB = 1073 , ARM64_INS_STURH = 1074 , ARM64_INS_STXP = 1075 , ARM64_INS_STXR = 1076 , ARM64_INS_STXRB = 1077 , ARM64_INS_STXRH = 1078 , ARM64_INS_STZ2G = 1079 , ARM64_INS_STZG = 1080 , ARM64_INS_STZGM = 1081 , ARM64_INS_SUB = 1082 , ARM64_INS_SUBG = 1083 , ARM64_INS_SUBHN = 1084 , ARM64_INS_SUBHN2 = 1085 , ARM64_INS_SUBHNB = 1086 , ARM64_INS_SUBHNT = 1087 , ARM64_INS_SUBP = 1088 , ARM64_INS_SUBPS = 1089 , ARM64_INS_SUBR = 1090 , ARM64_INS_SUBS = 1091 , ARM64_INS_SUDOT = 1092 , ARM64_INS_SUMOPA = 1093 , ARM64_INS_SUMOPS = 1094 , ARM64_INS_SUNPKHI = 1095 , ARM64_INS_SUNPKLO = 1096 , ARM64_INS_SUQADD = 1097 , ARM64_INS_SVC = 1098 , ARM64_INS_SWP = 1099 , ARM64_INS_SWPA = 1100 , ARM64_INS_SWPAB = 1101 , ARM64_INS_SWPAH = 1102 , ARM64_INS_SWPAL = 1103 , ARM64_INS_SWPALB = 1104 , ARM64_INS_SWPALH = 1105 , ARM64_INS_SWPB = 1106 , ARM64_INS_SWPH = 1107 , ARM64_INS_SWPL = 1108 , ARM64_INS_SWPLB = 1109 , ARM64_INS_SWPLH = 1110 , ARM64_INS_SXTB = 1111 , ARM64_INS_SXTH = 1112 , ARM64_INS_SXTL = 1113 , ARM64_INS_SXTL2 = 1114 , ARM64_INS_SXTW = 1115 , ARM64_INS_SYS = 1116 , ARM64_INS_SYSL = 1117 , ARM64_INS_TBL = 1118 , ARM64_INS_TBNZ = 1119 , ARM64_INS_TBX = 1120 , ARM64_INS_TBZ = 1121 , ARM64_INS_TCANCEL = 1122 , ARM64_INS_TCOMMIT = 1123 , ARM64_INS_TRN1 = 1124 , ARM64_INS_TRN2 = 1125 , ARM64_INS_TSB = 1126 , ARM64_INS_TST = 1127 , ARM64_INS_TSTART = 1128 , ARM64_INS_TTEST = 1129 , ARM64_INS_UABA = 1130 , ARM64_INS_UABAL = 1131 , ARM64_INS_UABAL2 = 1132 , ARM64_INS_UABALB = 1133 , ARM64_INS_UABALT = 1134 , ARM64_INS_UABD = 1135 , ARM64_INS_UABDL = 1136 , ARM64_INS_UABDL2 = 1137 , ARM64_INS_UABDLB = 1138 , ARM64_INS_UABDLT = 1139 , ARM64_INS_UADALP = 1140 , ARM64_INS_UADDL = 1141 , ARM64_INS_UADDL2 = 1142 , ARM64_INS_UADDLB = 1143 , ARM64_INS_UADDLP = 1144 , ARM64_INS_UADDLT = 1145 , ARM64_INS_UADDLV = 1146 , ARM64_INS_UADDV = 1147 , ARM64_INS_UADDW = 1148 , ARM64_INS_UADDW2 = 1149 , ARM64_INS_UADDWB = 1150 , ARM64_INS_UADDWT = 1151 , ARM64_INS_UBFM = 1152 , ARM64_INS_UCLAMP = 1153 , ARM64_INS_UCVTF = 1154 , ARM64_INS_UDF = 1155 , ARM64_INS_UDIV = 1156 , ARM64_INS_UDIVR = 1157 , ARM64_INS_UDOT = 1158 , ARM64_INS_UHADD = 1159 , ARM64_INS_UHSUB = 1160 , ARM64_INS_UHSUBR = 1161 , ARM64_INS_UMADDL = 1162 , ARM64_INS_UMAX = 1163 , ARM64_INS_UMAXP = 1164 , ARM64_INS_UMAXV = 1165 , ARM64_INS_UMIN = 1166 , ARM64_INS_UMINP = 1167 , ARM64_INS_UMINV = 1168 , ARM64_INS_UMLAL = 1169 , ARM64_INS_UMLAL2 = 1170 , ARM64_INS_UMLALB = 1171 , ARM64_INS_UMLALT = 1172 , ARM64_INS_UMLSL = 1173 , ARM64_INS_UMLSL2 = 1174 , ARM64_INS_UMLSLB = 1175 , ARM64_INS_UMLSLT = 1176 , ARM64_INS_UMMLA = 1177 , ARM64_INS_UMNEGL = 1178 , ARM64_INS_UMOPA = 1179 , ARM64_INS_UMOPS = 1180 , ARM64_INS_UMOV = 1181 , ARM64_INS_UMSUBL = 1182 , ARM64_INS_UMULH = 1183 , ARM64_INS_UMULL = 1184 , ARM64_INS_UMULL2 = 1185 , ARM64_INS_UMULLB = 1186 , ARM64_INS_UMULLT = 1187 , ARM64_INS_UQADD = 1188 , ARM64_INS_UQDECB = 1189 , ARM64_INS_UQDECD = 1190 , ARM64_INS_UQDECH = 1191 , ARM64_INS_UQDECP = 1192 , ARM64_INS_UQDECW = 1193 , ARM64_INS_UQINCB = 1194 , ARM64_INS_UQINCD = 1195 , ARM64_INS_UQINCH = 1196 , ARM64_INS_UQINCP = 1197 , ARM64_INS_UQINCW = 1198 , ARM64_INS_UQRSHL = 1199 , ARM64_INS_UQRSHLR = 1200 , ARM64_INS_UQRSHRN = 1201 , ARM64_INS_UQRSHRN2 = 1202 , ARM64_INS_UQRSHRNB = 1203 , ARM64_INS_UQRSHRNT = 1204 , ARM64_INS_UQSHL = 1205 , ARM64_INS_UQSHLR = 1206 , ARM64_INS_UQSHRN = 1207 , ARM64_INS_UQSHRN2 = 1208 , ARM64_INS_UQSHRNB = 1209 , ARM64_INS_UQSHRNT = 1210 , ARM64_INS_UQSUB = 1211 , ARM64_INS_UQSUBR = 1212 , ARM64_INS_UQXTN = 1213 , ARM64_INS_UQXTN2 = 1214 , ARM64_INS_UQXTNB = 1215 , ARM64_INS_UQXTNT = 1216 , ARM64_INS_URECPE = 1217 , ARM64_INS_URHADD = 1218 , ARM64_INS_URSHL = 1219 , ARM64_INS_URSHLR = 1220 , ARM64_INS_URSHR = 1221 , ARM64_INS_URSQRTE = 1222 , ARM64_INS_URSRA = 1223 , ARM64_INS_USDOT = 1224 , ARM64_INS_USHL = 1225 , ARM64_INS_USHLL = 1226 , ARM64_INS_USHLL2 = 1227 , ARM64_INS_USHLLB = 1228 , ARM64_INS_USHLLT = 1229 , ARM64_INS_USHR = 1230 , ARM64_INS_USMMLA = 1231 , ARM64_INS_USMOPA = 1232 , ARM64_INS_USMOPS = 1233 , ARM64_INS_USQADD = 1234 , ARM64_INS_USRA = 1235 , ARM64_INS_USUBL = 1236 , ARM64_INS_USUBL2 = 1237 , ARM64_INS_USUBLB = 1238 , ARM64_INS_USUBLT = 1239 , ARM64_INS_USUBW = 1240 , ARM64_INS_USUBW2 = 1241 , ARM64_INS_USUBWB = 1242 , ARM64_INS_USUBWT = 1243 , ARM64_INS_UUNPKHI = 1244 , ARM64_INS_UUNPKLO = 1245 , ARM64_INS_UXTB = 1246 , ARM64_INS_UXTH = 1247 , ARM64_INS_UXTL = 1248 , ARM64_INS_UXTL2 = 1249 , ARM64_INS_UXTW = 1250 , ARM64_INS_UZP1 = 1251 , ARM64_INS_UZP2 = 1252 , ARM64_INS_WFE = 1253 , ARM64_INS_WFET = 1254 , ARM64_INS_WFI = 1255 , ARM64_INS_WFIT = 1256 , ARM64_INS_WHILEGE = 1257 , ARM64_INS_WHILEGT = 1258 , ARM64_INS_WHILEHI = 1259 , ARM64_INS_WHILEHS = 1260 , ARM64_INS_WHILELE = 1261 , ARM64_INS_WHILELO = 1262 , ARM64_INS_WHILELS = 1263 , ARM64_INS_WHILELT = 1264 , ARM64_INS_WHILERW = 1265 , ARM64_INS_WHILEWR = 1266 , ARM64_INS_WRFFR = 1267 , ARM64_INS_XAFLAG = 1268 , ARM64_INS_XAR = 1269 , ARM64_INS_XPACD = 1270 , ARM64_INS_XPACI = 1271 , ARM64_INS_XPACLRI = 1272 , ARM64_INS_XTN = 1273 , ARM64_INS_XTN2 = 1274 , ARM64_INS_YIELD = 1275 , ARM64_INS_ZERO = 1276 , ARM64_INS_ZIP1 = 1277 , ARM64_INS_ZIP2 = 1278 , ARM64_INS_SBFIZ = 1279 , ARM64_INS_UBFIZ = 1280 , ARM64_INS_SBFX = 1281 , ARM64_INS_UBFX = 1282 , ARM64_INS_BFI = 1283 , ARM64_INS_BFXIL = 1284 , ARM64_INS_IC = 1285 , ARM64_INS_DC = 1286 , ARM64_INS_AT = 1287 , ARM64_INS_TLBI = 1288 , ARM64_INS_ENDING = 1289 , } # [repr (u32)] # [doc = " Group of ARM64 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM64_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM64_GRP_JUMP = 1 , ARM64_GRP_CALL = 2 , ARM64_GRP_RET = 3 , ARM64_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM64_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM64_GRP_BRANCH_RELATIVE = 7 , ARM64_GRP_PAC = 8 , ARM64_GRP_CRYPTO = 128 , ARM64_GRP_FPARMV8 = 129 , ARM64_GRP_NEON = 130 , ARM64_GRP_CRC = 131 , ARM64_GRP_AES = 132 , ARM64_GRP_DOTPROD = 133 , ARM64_GRP_FULLFP16 = 134 , ARM64_GRP_LSE = 135 , ARM64_GRP_RCPC = 136 , ARM64_GRP_RDM = 137 , ARM64_GRP_SHA2 = 138 , ARM64_GRP_SHA3 = 139 , ARM64_GRP_SM4 = 140 , ARM64_GRP_SVE = 141 , ARM64_GRP_SVE2 = 142 , ARM64_GRP_SVE2AES = 143 , ARM64_GRP_SVE2BitPerm = 144 , ARM64_GRP_SVE2SHA3 = 145 , ARM64_GRP_SVE2SM4 = 146 , ARM64_GRP_SME = 147 , ARM64_GRP_SMEF64 = 148 , ARM64_GRP_SMEI64 = 149 , ARM64_GRP_MatMulFP32 = 150 , ARM64_GRP_MatMulFP64 = 151 , ARM64_GRP_MatMulInt8 = 152 , ARM64_GRP_V8_1A = 153 , ARM64_GRP_V8_3A = 154 , ARM64_GRP_V8_4A = 155 , ARM64_GRP_ENDING = 156 , } # [repr (u32)] # [doc = " M68K registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_reg { M68K_REG_INVALID = 0 , M68K_REG_D0 = 1 , M68K_REG_D1 = 2 , M68K_REG_D2 = 3 , M68K_REG_D3 = 4 , M68K_REG_D4 = 5 , M68K_REG_D5 = 6 , M68K_REG_D6 = 7 , M68K_REG_D7 = 8 , M68K_REG_A0 = 9 , M68K_REG_A1 = 10 , M68K_REG_A2 = 11 , M68K_REG_A3 = 12 , M68K_REG_A4 = 13 , M68K_REG_A5 = 14 , M68K_REG_A6 = 15 , M68K_REG_A7 = 16 , M68K_REG_FP0 = 17 , M68K_REG_FP1 = 18 , M68K_REG_FP2 = 19 , M68K_REG_FP3 = 20 , M68K_REG_FP4 = 21 , M68K_REG_FP5 = 22 , M68K_REG_FP6 = 23 , M68K_REG_FP7 = 24 , M68K_REG_PC = 25 , M68K_REG_SR = 26 , M68K_REG_CCR = 27 , M68K_REG_SFC = 28 , M68K_REG_DFC = 29 , M68K_REG_USP = 30 , M68K_REG_VBR = 31 , M68K_REG_CACR = 32 , M68K_REG_CAAR = 33 , M68K_REG_MSP = 34 , M68K_REG_ISP = 35 , M68K_REG_TC = 36 , M68K_REG_ITT0 = 37 , M68K_REG_ITT1 = 38 , M68K_REG_DTT0 = 39 , M68K_REG_DTT1 = 40 , M68K_REG_MMUSR = 41 , M68K_REG_URP = 42 , M68K_REG_SRP = 43 , M68K_REG_FPCR = 44 , M68K_REG_FPSR = 45 , M68K_REG_FPIAR = 46 , M68K_REG_ENDING = 47 , } # [repr (u32)] # [doc = " M68K Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_address_mode { # [doc = "< No address mode."] M68K_AM_NONE = 0 , # [doc = "< Register Direct - Data"] M68K_AM_REG_DIRECT_DATA = 1 , # [doc = "< Register Direct - Address"] M68K_AM_REG_DIRECT_ADDR = 2 , # [doc = "< Register Indirect - Address"] M68K_AM_REGI_ADDR = 3 , # [doc = "< Register Indirect - Address with Postincrement"] M68K_AM_REGI_ADDR_POST_INC = 4 , # [doc = "< Register Indirect - Address with Predecrement"] M68K_AM_REGI_ADDR_PRE_DEC = 5 , # [doc = "< Register Indirect - Address with Displacement"] M68K_AM_REGI_ADDR_DISP = 6 , # [doc = "< Address Register Indirect With Index- 8-bit displacement"] M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 , # [doc = "< Address Register Indirect With Index- Base displacement"] M68K_AM_AREGI_INDEX_BASE_DISP = 8 , # [doc = "< Memory indirect - Postindex"] M68K_AM_MEMI_POST_INDEX = 9 , # [doc = "< Memory indirect - Preindex"] M68K_AM_MEMI_PRE_INDEX = 10 , # [doc = "< Program Counter Indirect - with Displacement"] M68K_AM_PCI_DISP = 11 , # [doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"] M68K_AM_PCI_INDEX_8_BIT_DISP = 12 , # [doc = "< Program Counter Indirect with Index - with Base Displacement"] M68K_AM_PCI_INDEX_BASE_DISP = 13 , # [doc = "< Program Counter Memory Indirect - Postindexed"] M68K_AM_PC_MEMI_POST_INDEX = 14 , # [doc = "< Program Counter Memory Indirect - Preindexed"] M68K_AM_PC_MEMI_PRE_INDEX = 15 , # [doc = "< Absolute Data Addressing  - Short"] M68K_AM_ABSOLUTE_DATA_SHORT = 16 , # [doc = "< Absolute Data Addressing  - Long"] M68K_AM_ABSOLUTE_DATA_LONG = 17 , # [doc = "< Immediate value"] M68K_AM_IMMEDIATE = 18 , # [doc = "< Address as displacement from (PC+2) used by branches"] M68K_AM_BRANCH_DISPLACEMENT = 19 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] M68K_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] M68K_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] M68K_OP_MEM = 3 , # [doc = "< single precision Floating-Point operand"] M68K_OP_FP_SINGLE = 4 , # [doc = "< double precision Floating-Point operand"] M68K_OP_FP_DOUBLE = 5 , # [doc = "< Register bits move"] M68K_OP_REG_BITS = 6 , # [doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"] M68K_OP_REG_PAIR = 7 , # [doc = "< Branch displacement"] M68K_OP_BR_DISP = 8 , } # [doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_mem { # [doc = "< base register (or M68K_REG_INVALID if irrelevant)"] pub base_reg : m68k_reg , # [doc = "< index register (or M68K_REG_INVALID if irrelevant)"] pub index_reg : m68k_reg , # [doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"] pub in_base_reg : m68k_reg , # [doc = "< indirect displacement"] pub in_disp : u32 , # [doc = "< other displacement"] pub out_disp : u32 , # [doc = "< displacement value"] pub disp : i16 , # [doc = "< scale for index register"] pub scale : u8 , # [doc = "< set to true if the two values below should be used"] pub bitfield : u8 , # [doc = "< used for bf* instructions"] pub width : u8 , # [doc = "< used for bf* instructions"] pub offset : u8 , # [doc = "< 0 = w, 1 = l"] pub index_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_mem"] [:: std :: mem :: size_of :: < m68k_op_mem > () - 28usize] ; ["Alignment of m68k_op_mem"] [:: std :: mem :: align_of :: < m68k_op_mem > () - 4usize] ; ["Offset of field: m68k_op_mem::base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , base_reg) - 0usize] ; ["Offset of field: m68k_op_mem::index_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_reg) - 4usize] ; ["Offset of field: m68k_op_mem::in_base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_base_reg) - 8usize] ; ["Offset of field: m68k_op_mem::in_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_disp) - 12usize] ; ["Offset of field: m68k_op_mem::out_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , out_disp) - 16usize] ; ["Offset of field: m68k_op_mem::disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , disp) - 20usize] ; ["Offset of field: m68k_op_mem::scale"] [:: std :: mem :: offset_of ! (m68k_op_mem , scale) - 22usize] ; ["Offset of field: m68k_op_mem::bitfield"] [:: std :: mem :: offset_of ! (m68k_op_mem , bitfield) - 23usize] ; ["Offset of field: m68k_op_mem::width"] [:: std :: mem :: offset_of ! (m68k_op_mem , width) - 24usize] ; ["Offset of field: m68k_op_mem::offset"] [:: std :: mem :: offset_of ! (m68k_op_mem , offset) - 25usize] ; ["Offset of field: m68k_op_mem::index_size"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_size) - 26usize] ; } ; # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_br_disp_size { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_BR_DISP_SIZE_INVALID = 0 , # [doc = "< signed 8-bit displacement"] M68K_OP_BR_DISP_SIZE_BYTE = 1 , # [doc = "< signed 16-bit displacement"] M68K_OP_BR_DISP_SIZE_WORD = 2 , # [doc = "< signed 32-bit displacement"] M68K_OP_BR_DISP_SIZE_LONG = 4 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_br_disp { # [doc = "< displacement value"] pub disp : i32 , # [doc = "< Size from m68k_op_br_disp_size type above"] pub disp_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_br_disp"] [:: std :: mem :: size_of :: < m68k_op_br_disp > () - 8usize] ; ["Alignment of m68k_op_br_disp"] [:: std :: mem :: align_of :: < m68k_op_br_disp > () - 4usize] ; ["Offset of field: m68k_op_br_disp::disp"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp) - 0usize] ; ["Offset of field: m68k_op_br_disp::disp_size"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp_size) - 4usize] ; } ; # [doc = " Register pair in one operand."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_m68k_op_reg_pair { pub reg_0 : m68k_reg , pub reg_1 : m68k_reg , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op_reg_pair"] [:: std :: mem :: size_of :: < cs_m68k_op_reg_pair > () - 8usize] ; ["Alignment of cs_m68k_op_reg_pair"] [:: std :: mem :: align_of :: < cs_m68k_op_reg_pair > () - 4usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_0"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_0) - 0usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_1"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_1) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k_op { pub __bindgen_anon_1 : cs_m68k_op__bindgen_ty_1 , # [doc = "< data when operand is targeting memory"] pub mem : m68k_op_mem , # [doc = "< data when operand is a branch displacement"] pub br_disp : m68k_op_br_disp , # [doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"] pub register_bits : u32 , pub type_ : m68k_op_type , # [doc = "< M68K addressing mode for this op"] pub address_mode : m68k_address_mode , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m68k_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< double imm"] pub dimm : f64 , # [doc = "< float imm"] pub simm : f32 , # [doc = "< register value for REG operand"] pub reg : m68k_reg , # [doc = "< register pair in one operand"] pub reg_pair : cs_m68k_op_reg_pair , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::dimm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , dimm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::simm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , simm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg_pair"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg_pair) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op"] [:: std :: mem :: size_of :: < cs_m68k_op > () - 56usize] ; ["Alignment of cs_m68k_op"] [:: std :: mem :: align_of :: < cs_m68k_op > () - 8usize] ; ["Offset of field: cs_m68k_op::mem"] [:: std :: mem :: offset_of ! (cs_m68k_op , mem) - 8usize] ; ["Offset of field: cs_m68k_op::br_disp"] [:: std :: mem :: offset_of ! (cs_m68k_op , br_disp) - 36usize] ; ["Offset of field: cs_m68k_op::register_bits"] [:: std :: mem :: offset_of ! (cs_m68k_op , register_bits) - 44usize] ; ["Offset of field: cs_m68k_op::type_"] [:: std :: mem :: offset_of ! (cs_m68k_op , type_) - 48usize] ; ["Offset of field: cs_m68k_op::address_mode"] [:: std :: mem :: offset_of ! (cs_m68k_op , address_mode) - 52usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode) } } # [repr (u32)] # [doc = " Operation size of the CPU instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_cpu_size { # [doc = "< unsized or unspecified"] M68K_CPU_SIZE_NONE = 0 , # [doc = "< 1 byte in size"] M68K_CPU_SIZE_BYTE = 1 , # [doc = "< 2 bytes in size"] M68K_CPU_SIZE_WORD = 2 , # [doc = "< 4 bytes in size"] M68K_CPU_SIZE_LONG = 4 , } # [repr (u32)] # [doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_fpu_size { # [doc = "< unsized like fsave/frestore"] M68K_FPU_SIZE_NONE = 0 , # [doc = "< 4 byte in size (single float)"] M68K_FPU_SIZE_SINGLE = 4 , # [doc = "< 8 byte in size (double)"] M68K_FPU_SIZE_DOUBLE = 8 , # [doc = "< 12 byte in size (extended real format)"] M68K_FPU_SIZE_EXTENDED = 12 , } # [repr (u32)] # [doc = " Type of size that is being used for the current instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0 , M68K_SIZE_TYPE_CPU = 1 , M68K_SIZE_TYPE_FPU = 2 , } # [doc = " Operation size of the current instruction (NOT the actually size of instruction)"] # [repr (C)] # [derive (Copy , Clone)] pub struct m68k_op_size { pub type_ : m68k_size_type , pub __bindgen_anon_1 : m68k_op_size__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union m68k_op_size__bindgen_ty_1 { pub cpu_size : m68k_cpu_size , pub fpu_size : m68k_fpu_size , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: size_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Alignment of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: align_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::cpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , cpu_size) - 0usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::fpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , fpu_size) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size"] [:: std :: mem :: size_of :: < m68k_op_size > () - 8usize] ; ["Alignment of m68k_op_size"] [:: std :: mem :: align_of :: < m68k_op_size > () - 4usize] ; ["Offset of field: m68k_op_size::type_"] [:: std :: mem :: offset_of ! (m68k_op_size , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The M68K instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k { # [doc = "< operands for this instruction."] pub operands : [cs_m68k_op ; 4usize] , # [doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"] pub op_size : m68k_op_size , # [doc = "< number of operands for the instruction"] pub op_count : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k"] [:: std :: mem :: size_of :: < cs_m68k > () - 240usize] ; ["Alignment of cs_m68k"] [:: std :: mem :: align_of :: < cs_m68k > () - 8usize] ; ["Offset of field: cs_m68k::operands"] [:: std :: mem :: offset_of ! (cs_m68k , operands) - 0usize] ; ["Offset of field: cs_m68k::op_size"] [:: std :: mem :: offset_of ! (cs_m68k , op_size) - 224usize] ; ["Offset of field: cs_m68k::op_count"] [:: std :: mem :: offset_of ! (cs_m68k , op_count) - 232usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}" , self . operands , self . op_size , self . op_count) } } # [repr (u32)] # [doc = " M68K instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_insn { M68K_INS_INVALID = 0 , M68K_INS_ABCD = 1 , M68K_INS_ADD = 2 , M68K_INS_ADDA = 3 , M68K_INS_ADDI = 4 , M68K_INS_ADDQ = 5 , M68K_INS_ADDX = 6 , M68K_INS_AND = 7 , M68K_INS_ANDI = 8 , M68K_INS_ASL = 9 , M68K_INS_ASR = 10 , M68K_INS_BHS = 11 , M68K_INS_BLO = 12 , M68K_INS_BHI = 13 , M68K_INS_BLS = 14 , M68K_INS_BCC = 15 , M68K_INS_BCS = 16 , M68K_INS_BNE = 17 , M68K_INS_BEQ = 18 , M68K_INS_BVC = 19 , M68K_INS_BVS = 20 , M68K_INS_BPL = 21 , M68K_INS_BMI = 22 , M68K_INS_BGE = 23 , M68K_INS_BLT = 24 , M68K_INS_BGT = 25 , M68K_INS_BLE = 26 , M68K_INS_BRA = 27 , M68K_INS_BSR = 28 , M68K_INS_BCHG = 29 , M68K_INS_BCLR = 30 , M68K_INS_BSET = 31 , M68K_INS_BTST = 32 , M68K_INS_BFCHG = 33 , M68K_INS_BFCLR = 34 , M68K_INS_BFEXTS = 35 , M68K_INS_BFEXTU = 36 , M68K_INS_BFFFO = 37 , M68K_INS_BFINS = 38 , M68K_INS_BFSET = 39 , M68K_INS_BFTST = 40 , M68K_INS_BKPT = 41 , M68K_INS_CALLM = 42 , M68K_INS_CAS = 43 , M68K_INS_CAS2 = 44 , M68K_INS_CHK = 45 , M68K_INS_CHK2 = 46 , M68K_INS_CLR = 47 , M68K_INS_CMP = 48 , M68K_INS_CMPA = 49 , M68K_INS_CMPI = 50 , M68K_INS_CMPM = 51 , M68K_INS_CMP2 = 52 , M68K_INS_CINVL = 53 , M68K_INS_CINVP = 54 , M68K_INS_CINVA = 55 , M68K_INS_CPUSHL = 56 , M68K_INS_CPUSHP = 57 , M68K_INS_CPUSHA = 58 , M68K_INS_DBT = 59 , M68K_INS_DBF = 60 , M68K_INS_DBHI = 61 , M68K_INS_DBLS = 62 , M68K_INS_DBCC = 63 , M68K_INS_DBCS = 64 , M68K_INS_DBNE = 65 , M68K_INS_DBEQ = 66 , M68K_INS_DBVC = 67 , M68K_INS_DBVS = 68 , M68K_INS_DBPL = 69 , M68K_INS_DBMI = 70 , M68K_INS_DBGE = 71 , M68K_INS_DBLT = 72 , M68K_INS_DBGT = 73 , M68K_INS_DBLE = 74 , M68K_INS_DBRA = 75 , M68K_INS_DIVS = 76 , M68K_INS_DIVSL = 77 , M68K_INS_DIVU = 78 , M68K_INS_DIVUL = 79 , M68K_INS_EOR = 80 , M68K_INS_EORI = 81 , M68K_INS_EXG = 82 , M68K_INS_EXT = 83 , M68K_INS_EXTB = 84 , M68K_INS_FABS = 85 , M68K_INS_FSABS = 86 , M68K_INS_FDABS = 87 , M68K_INS_FACOS = 88 , M68K_INS_FADD = 89 , M68K_INS_FSADD = 90 , M68K_INS_FDADD = 91 , M68K_INS_FASIN = 92 , M68K_INS_FATAN = 93 , M68K_INS_FATANH = 94 , M68K_INS_FBF = 95 , M68K_INS_FBEQ = 96 , M68K_INS_FBOGT = 97 , M68K_INS_FBOGE = 98 , M68K_INS_FBOLT = 99 , M68K_INS_FBOLE = 100 , M68K_INS_FBOGL = 101 , M68K_INS_FBOR = 102 , M68K_INS_FBUN = 103 , M68K_INS_FBUEQ = 104 , M68K_INS_FBUGT = 105 , M68K_INS_FBUGE = 106 , M68K_INS_FBULT = 107 , M68K_INS_FBULE = 108 , M68K_INS_FBNE = 109 , M68K_INS_FBT = 110 , M68K_INS_FBSF = 111 , M68K_INS_FBSEQ = 112 , M68K_INS_FBGT = 113 , M68K_INS_FBGE = 114 , M68K_INS_FBLT = 115 , M68K_INS_FBLE = 116 , M68K_INS_FBGL = 117 , M68K_INS_FBGLE = 118 , M68K_INS_FBNGLE = 119 , M68K_INS_FBNGL = 120 , M68K_INS_FBNLE = 121 , M68K_INS_FBNLT = 122 , M68K_INS_FBNGE = 123 , M68K_INS_FBNGT = 124 , M68K_INS_FBSNE = 125 , M68K_INS_FBST = 126 , M68K_INS_FCMP = 127 , M68K_INS_FCOS = 128 , M68K_INS_FCOSH = 129 , M68K_INS_FDBF = 130 , M68K_INS_FDBEQ = 131 , M68K_INS_FDBOGT = 132 , M68K_INS_FDBOGE = 133 , M68K_INS_FDBOLT = 134 , M68K_INS_FDBOLE = 135 , M68K_INS_FDBOGL = 136 , M68K_INS_FDBOR = 137 , M68K_INS_FDBUN = 138 , M68K_INS_FDBUEQ = 139 , M68K_INS_FDBUGT = 140 , M68K_INS_FDBUGE = 141 , M68K_INS_FDBULT = 142 , M68K_INS_FDBULE = 143 , M68K_INS_FDBNE = 144 , M68K_INS_FDBT = 145 , M68K_INS_FDBSF = 146 , M68K_INS_FDBSEQ = 147 , M68K_INS_FDBGT = 148 , M68K_INS_FDBGE = 149 , M68K_INS_FDBLT = 150 , M68K_INS_FDBLE = 151 , M68K_INS_FDBGL = 152 , M68K_INS_FDBGLE = 153 , M68K_INS_FDBNGLE = 154 , M68K_INS_FDBNGL = 155 , M68K_INS_FDBNLE = 156 , M68K_INS_FDBNLT = 157 , M68K_INS_FDBNGE = 158 , M68K_INS_FDBNGT = 159 , M68K_INS_FDBSNE = 160 , M68K_INS_FDBST = 161 , M68K_INS_FDIV = 162 , M68K_INS_FSDIV = 163 , M68K_INS_FDDIV = 164 , M68K_INS_FETOX = 165 , M68K_INS_FETOXM1 = 166 , M68K_INS_FGETEXP = 167 , M68K_INS_FGETMAN = 168 , M68K_INS_FINT = 169 , M68K_INS_FINTRZ = 170 , M68K_INS_FLOG10 = 171 , M68K_INS_FLOG2 = 172 , M68K_INS_FLOGN = 173 , M68K_INS_FLOGNP1 = 174 , M68K_INS_FMOD = 175 , M68K_INS_FMOVE = 176 , M68K_INS_FSMOVE = 177 , M68K_INS_FDMOVE = 178 , M68K_INS_FMOVECR = 179 , M68K_INS_FMOVEM = 180 , M68K_INS_FMUL = 181 , M68K_INS_FSMUL = 182 , M68K_INS_FDMUL = 183 , M68K_INS_FNEG = 184 , M68K_INS_FSNEG = 185 , M68K_INS_FDNEG = 186 , M68K_INS_FNOP = 187 , M68K_INS_FREM = 188 , M68K_INS_FRESTORE = 189 , M68K_INS_FSAVE = 190 , M68K_INS_FSCALE = 191 , M68K_INS_FSGLDIV = 192 , M68K_INS_FSGLMUL = 193 , M68K_INS_FSIN = 194 , M68K_INS_FSINCOS = 195 , M68K_INS_FSINH = 196 , M68K_INS_FSQRT = 197 , M68K_INS_FSSQRT = 198 , M68K_INS_FDSQRT = 199 , M68K_INS_FSF = 200 , M68K_INS_FSBEQ = 201 , M68K_INS_FSOGT = 202 , M68K_INS_FSOGE = 203 , M68K_INS_FSOLT = 204 , M68K_INS_FSOLE = 205 , M68K_INS_FSOGL = 206 , M68K_INS_FSOR = 207 , M68K_INS_FSUN = 208 , M68K_INS_FSUEQ = 209 , M68K_INS_FSUGT = 210 , M68K_INS_FSUGE = 211 , M68K_INS_FSULT = 212 , M68K_INS_FSULE = 213 , M68K_INS_FSNE = 214 , M68K_INS_FST = 215 , M68K_INS_FSSF = 216 , M68K_INS_FSSEQ = 217 , M68K_INS_FSGT = 218 , M68K_INS_FSGE = 219 , M68K_INS_FSLT = 220 , M68K_INS_FSLE = 221 , M68K_INS_FSGL = 222 , M68K_INS_FSGLE = 223 , M68K_INS_FSNGLE = 224 , M68K_INS_FSNGL = 225 , M68K_INS_FSNLE = 226 , M68K_INS_FSNLT = 227 , M68K_INS_FSNGE = 228 , M68K_INS_FSNGT = 229 , M68K_INS_FSSNE = 230 , M68K_INS_FSST = 231 , M68K_INS_FSUB = 232 , M68K_INS_FSSUB = 233 , M68K_INS_FDSUB = 234 , M68K_INS_FTAN = 235 , M68K_INS_FTANH = 236 , M68K_INS_FTENTOX = 237 , M68K_INS_FTRAPF = 238 , M68K_INS_FTRAPEQ = 239 , M68K_INS_FTRAPOGT = 240 , M68K_INS_FTRAPOGE = 241 , M68K_INS_FTRAPOLT = 242 , M68K_INS_FTRAPOLE = 243 , M68K_INS_FTRAPOGL = 244 , M68K_INS_FTRAPOR = 245 , M68K_INS_FTRAPUN = 246 , M68K_INS_FTRAPUEQ = 247 , M68K_INS_FTRAPUGT = 248 , M68K_INS_FTRAPUGE = 249 , M68K_INS_FTRAPULT = 250 , M68K_INS_FTRAPULE = 251 , M68K_INS_FTRAPNE = 252 , M68K_INS_FTRAPT = 253 , M68K_INS_FTRAPSF = 254 , M68K_INS_FTRAPSEQ = 255 , M68K_INS_FTRAPGT = 256 , M68K_INS_FTRAPGE = 257 , M68K_INS_FTRAPLT = 258 , M68K_INS_FTRAPLE = 259 , M68K_INS_FTRAPGL = 260 , M68K_INS_FTRAPGLE = 261 , M68K_INS_FTRAPNGLE = 262 , M68K_INS_FTRAPNGL = 263 , M68K_INS_FTRAPNLE = 264 , M68K_INS_FTRAPNLT = 265 , M68K_INS_FTRAPNGE = 266 , M68K_INS_FTRAPNGT = 267 , M68K_INS_FTRAPSNE = 268 , M68K_INS_FTRAPST = 269 , M68K_INS_FTST = 270 , M68K_INS_FTWOTOX = 271 , M68K_INS_HALT = 272 , M68K_INS_ILLEGAL = 273 , M68K_INS_JMP = 274 , M68K_INS_JSR = 275 , M68K_INS_LEA = 276 , M68K_INS_LINK = 277 , M68K_INS_LPSTOP = 278 , M68K_INS_LSL = 279 , M68K_INS_LSR = 280 , M68K_INS_MOVE = 281 , M68K_INS_MOVEA = 282 , M68K_INS_MOVEC = 283 , M68K_INS_MOVEM = 284 , M68K_INS_MOVEP = 285 , M68K_INS_MOVEQ = 286 , M68K_INS_MOVES = 287 , M68K_INS_MOVE16 = 288 , M68K_INS_MULS = 289 , M68K_INS_MULU = 290 , M68K_INS_NBCD = 291 , M68K_INS_NEG = 292 , M68K_INS_NEGX = 293 , M68K_INS_NOP = 294 , M68K_INS_NOT = 295 , M68K_INS_OR = 296 , M68K_INS_ORI = 297 , M68K_INS_PACK = 298 , M68K_INS_PEA = 299 , M68K_INS_PFLUSH = 300 , M68K_INS_PFLUSHA = 301 , M68K_INS_PFLUSHAN = 302 , M68K_INS_PFLUSHN = 303 , M68K_INS_PLOADR = 304 , M68K_INS_PLOADW = 305 , M68K_INS_PLPAR = 306 , M68K_INS_PLPAW = 307 , M68K_INS_PMOVE = 308 , M68K_INS_PMOVEFD = 309 , M68K_INS_PTESTR = 310 , M68K_INS_PTESTW = 311 , M68K_INS_PULSE = 312 , M68K_INS_REMS = 313 , M68K_INS_REMU = 314 , M68K_INS_RESET = 315 , M68K_INS_ROL = 316 , M68K_INS_ROR = 317 , M68K_INS_ROXL = 318 , M68K_INS_ROXR = 319 , M68K_INS_RTD = 320 , M68K_INS_RTE = 321 , M68K_INS_RTM = 322 , M68K_INS_RTR = 323 , M68K_INS_RTS = 324 , M68K_INS_SBCD = 325 , M68K_INS_ST = 326 , M68K_INS_SF = 327 , M68K_INS_SHI = 328 , M68K_INS_SLS = 329 , M68K_INS_SCC = 330 , M68K_INS_SHS = 331 , M68K_INS_SCS = 332 , M68K_INS_SLO = 333 , M68K_INS_SNE = 334 , M68K_INS_SEQ = 335 , M68K_INS_SVC = 336 , M68K_INS_SVS = 337 , M68K_INS_SPL = 338 , M68K_INS_SMI = 339 , M68K_INS_SGE = 340 , M68K_INS_SLT = 341 , M68K_INS_SGT = 342 , M68K_INS_SLE = 343 , M68K_INS_STOP = 344 , M68K_INS_SUB = 345 , M68K_INS_SUBA = 346 , M68K_INS_SUBI = 347 , M68K_INS_SUBQ = 348 , M68K_INS_SUBX = 349 , M68K_INS_SWAP = 350 , M68K_INS_TAS = 351 , M68K_INS_TRAP = 352 , M68K_INS_TRAPV = 353 , M68K_INS_TRAPT = 354 , M68K_INS_TRAPF = 355 , M68K_INS_TRAPHI = 356 , M68K_INS_TRAPLS = 357 , M68K_INS_TRAPCC = 358 , M68K_INS_TRAPHS = 359 , M68K_INS_TRAPCS = 360 , M68K_INS_TRAPLO = 361 , M68K_INS_TRAPNE = 362 , M68K_INS_TRAPEQ = 363 , M68K_INS_TRAPVC = 364 , M68K_INS_TRAPVS = 365 , M68K_INS_TRAPPL = 366 , M68K_INS_TRAPMI = 367 , M68K_INS_TRAPGE = 368 , M68K_INS_TRAPLT = 369 , M68K_INS_TRAPGT = 370 , M68K_INS_TRAPLE = 371 , M68K_INS_TST = 372 , M68K_INS_UNLK = 373 , M68K_INS_UNPK = 374 , M68K_INS_ENDING = 375 , } # [repr (u32)] # [doc = " Group of M68K instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_group_type { # [doc = "< CS_GRUP_INVALID"] M68K_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M68K_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] M68K_GRP_RET = 3 , # [doc = "< = CS_GRP_IRET"] M68K_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M68K_GRP_BRANCH_RELATIVE = 7 , M68K_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MIPS_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MIPS_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MIPS_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MIPS_OP_MEM = 3 , } impl mips_reg { pub const MIPS_REG_ZERO : mips_reg = mips_reg :: MIPS_REG_0 ; } impl mips_reg { pub const MIPS_REG_AT : mips_reg = mips_reg :: MIPS_REG_1 ; } impl mips_reg { pub const MIPS_REG_V0 : mips_reg = mips_reg :: MIPS_REG_2 ; } impl mips_reg { pub const MIPS_REG_V1 : mips_reg = mips_reg :: MIPS_REG_3 ; } impl mips_reg { pub const MIPS_REG_A0 : mips_reg = mips_reg :: MIPS_REG_4 ; } impl mips_reg { pub const MIPS_REG_A1 : mips_reg = mips_reg :: MIPS_REG_5 ; } impl mips_reg { pub const MIPS_REG_A2 : mips_reg = mips_reg :: MIPS_REG_6 ; } impl mips_reg { pub const MIPS_REG_A3 : mips_reg = mips_reg :: MIPS_REG_7 ; } impl mips_reg { pub const MIPS_REG_T0 : mips_reg = mips_reg :: MIPS_REG_8 ; } impl mips_reg { pub const MIPS_REG_T1 : mips_reg = mips_reg :: MIPS_REG_9 ; } impl mips_reg { pub const MIPS_REG_T2 : mips_reg = mips_reg :: MIPS_REG_10 ; } impl mips_reg { pub const MIPS_REG_T3 : mips_reg = mips_reg :: MIPS_REG_11 ; } impl mips_reg { pub const MIPS_REG_T4 : mips_reg = mips_reg :: MIPS_REG_12 ; } impl mips_reg { pub const MIPS_REG_T5 : mips_reg = mips_reg :: MIPS_REG_13 ; } impl mips_reg { pub const MIPS_REG_T6 : mips_reg = mips_reg :: MIPS_REG_14 ; } impl mips_reg { pub const MIPS_REG_T7 : mips_reg = mips_reg :: MIPS_REG_15 ; } impl mips_reg { pub const MIPS_REG_S0 : mips_reg = mips_reg :: MIPS_REG_16 ; } impl mips_reg { pub const MIPS_REG_S1 : mips_reg = mips_reg :: MIPS_REG_17 ; } impl mips_reg { pub const MIPS_REG_S2 : mips_reg = mips_reg :: MIPS_REG_18 ; } impl mips_reg { pub const MIPS_REG_S3 : mips_reg = mips_reg :: MIPS_REG_19 ; } impl mips_reg { pub const MIPS_REG_S4 : mips_reg = mips_reg :: MIPS_REG_20 ; } impl mips_reg { pub const MIPS_REG_S5 : mips_reg = mips_reg :: MIPS_REG_21 ; } impl mips_reg { pub const MIPS_REG_S6 : mips_reg = mips_reg :: MIPS_REG_22 ; } impl mips_reg { pub const MIPS_REG_S7 : mips_reg = mips_reg :: MIPS_REG_23 ; } impl mips_reg { pub const MIPS_REG_T8 : mips_reg = mips_reg :: MIPS_REG_24 ; } impl mips_reg { pub const MIPS_REG_T9 : mips_reg = mips_reg :: MIPS_REG_25 ; } impl mips_reg { pub const MIPS_REG_K0 : mips_reg = mips_reg :: MIPS_REG_26 ; } impl mips_reg { pub const MIPS_REG_K1 : mips_reg = mips_reg :: MIPS_REG_27 ; } impl mips_reg { pub const MIPS_REG_GP : mips_reg = mips_reg :: MIPS_REG_28 ; } impl mips_reg { pub const MIPS_REG_SP : mips_reg = mips_reg :: MIPS_REG_29 ; } impl mips_reg { pub const MIPS_REG_FP : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_S8 : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_RA : mips_reg = mips_reg :: MIPS_REG_31 ; } impl mips_reg { pub const MIPS_REG_HI0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_HI1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_HI2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_HI3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } impl mips_reg { pub const MIPS_REG_LO0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_LO1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_LO2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_LO3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } # [repr (u32)] # [doc = " MIPS registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_reg { MIPS_REG_INVALID = 0 , MIPS_REG_PC = 1 , MIPS_REG_0 = 2 , MIPS_REG_1 = 3 , MIPS_REG_2 = 4 , MIPS_REG_3 = 5 , MIPS_REG_4 = 6 , MIPS_REG_5 = 7 , MIPS_REG_6 = 8 , MIPS_REG_7 = 9 , MIPS_REG_8 = 10 , MIPS_REG_9 = 11 , MIPS_REG_10 = 12 , MIPS_REG_11 = 13 , MIPS_REG_12 = 14 , MIPS_REG_13 = 15 , MIPS_REG_14 = 16 , MIPS_REG_15 = 17 , MIPS_REG_16 = 18 , MIPS_REG_17 = 19 , MIPS_REG_18 = 20 , MIPS_REG_19 = 21 , MIPS_REG_20 = 22 , MIPS_REG_21 = 23 , MIPS_REG_22 = 24 , MIPS_REG_23 = 25 , MIPS_REG_24 = 26 , MIPS_REG_25 = 27 , MIPS_REG_26 = 28 , MIPS_REG_27 = 29 , MIPS_REG_28 = 30 , MIPS_REG_29 = 31 , MIPS_REG_30 = 32 , MIPS_REG_31 = 33 , MIPS_REG_DSPCCOND = 34 , MIPS_REG_DSPCARRY = 35 , MIPS_REG_DSPEFI = 36 , MIPS_REG_DSPOUTFLAG = 37 , MIPS_REG_DSPOUTFLAG16_19 = 38 , MIPS_REG_DSPOUTFLAG20 = 39 , MIPS_REG_DSPOUTFLAG21 = 40 , MIPS_REG_DSPOUTFLAG22 = 41 , MIPS_REG_DSPOUTFLAG23 = 42 , MIPS_REG_DSPPOS = 43 , MIPS_REG_DSPSCOUNT = 44 , MIPS_REG_AC0 = 45 , MIPS_REG_AC1 = 46 , MIPS_REG_AC2 = 47 , MIPS_REG_AC3 = 48 , MIPS_REG_CC0 = 49 , MIPS_REG_CC1 = 50 , MIPS_REG_CC2 = 51 , MIPS_REG_CC3 = 52 , MIPS_REG_CC4 = 53 , MIPS_REG_CC5 = 54 , MIPS_REG_CC6 = 55 , MIPS_REG_CC7 = 56 , MIPS_REG_F0 = 57 , MIPS_REG_F1 = 58 , MIPS_REG_F2 = 59 , MIPS_REG_F3 = 60 , MIPS_REG_F4 = 61 , MIPS_REG_F5 = 62 , MIPS_REG_F6 = 63 , MIPS_REG_F7 = 64 , MIPS_REG_F8 = 65 , MIPS_REG_F9 = 66 , MIPS_REG_F10 = 67 , MIPS_REG_F11 = 68 , MIPS_REG_F12 = 69 , MIPS_REG_F13 = 70 , MIPS_REG_F14 = 71 , MIPS_REG_F15 = 72 , MIPS_REG_F16 = 73 , MIPS_REG_F17 = 74 , MIPS_REG_F18 = 75 , MIPS_REG_F19 = 76 , MIPS_REG_F20 = 77 , MIPS_REG_F21 = 78 , MIPS_REG_F22 = 79 , MIPS_REG_F23 = 80 , MIPS_REG_F24 = 81 , MIPS_REG_F25 = 82 , MIPS_REG_F26 = 83 , MIPS_REG_F27 = 84 , MIPS_REG_F28 = 85 , MIPS_REG_F29 = 86 , MIPS_REG_F30 = 87 , MIPS_REG_F31 = 88 , MIPS_REG_FCC0 = 89 , MIPS_REG_FCC1 = 90 , MIPS_REG_FCC2 = 91 , MIPS_REG_FCC3 = 92 , MIPS_REG_FCC4 = 93 , MIPS_REG_FCC5 = 94 , MIPS_REG_FCC6 = 95 , MIPS_REG_FCC7 = 96 , MIPS_REG_W0 = 97 , MIPS_REG_W1 = 98 , MIPS_REG_W2 = 99 , MIPS_REG_W3 = 100 , MIPS_REG_W4 = 101 , MIPS_REG_W5 = 102 , MIPS_REG_W6 = 103 , MIPS_REG_W7 = 104 , MIPS_REG_W8 = 105 , MIPS_REG_W9 = 106 , MIPS_REG_W10 = 107 , MIPS_REG_W11 = 108 , MIPS_REG_W12 = 109 , MIPS_REG_W13 = 110 , MIPS_REG_W14 = 111 , MIPS_REG_W15 = 112 , MIPS_REG_W16 = 113 , MIPS_REG_W17 = 114 , MIPS_REG_W18 = 115 , MIPS_REG_W19 = 116 , MIPS_REG_W20 = 117 , MIPS_REG_W21 = 118 , MIPS_REG_W22 = 119 , MIPS_REG_W23 = 120 , MIPS_REG_W24 = 121 , MIPS_REG_W25 = 122 , MIPS_REG_W26 = 123 , MIPS_REG_W27 = 124 , MIPS_REG_W28 = 125 , MIPS_REG_W29 = 126 , MIPS_REG_W30 = 127 , MIPS_REG_W31 = 128 , MIPS_REG_HI = 129 , MIPS_REG_LO = 130 , MIPS_REG_P0 = 131 , MIPS_REG_P1 = 132 , MIPS_REG_P2 = 133 , MIPS_REG_MPL0 = 134 , MIPS_REG_MPL1 = 135 , MIPS_REG_MPL2 = 136 , MIPS_REG_ENDING = 137 , } # [doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct mips_op_mem { # [doc = "< base register"] pub base : mips_reg , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of mips_op_mem"] [:: std :: mem :: size_of :: < mips_op_mem > () - 16usize] ; ["Alignment of mips_op_mem"] [:: std :: mem :: align_of :: < mips_op_mem > () - 8usize] ; ["Offset of field: mips_op_mem::base"] [:: std :: mem :: offset_of ! (mips_op_mem , base) - 0usize] ; ["Offset of field: mips_op_mem::disp"] [:: std :: mem :: offset_of ! (mips_op_mem , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips_op { # [doc = "< operand type"] pub type_ : mips_op_type , pub __bindgen_anon_1 : cs_mips_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mips_op__bindgen_ty_1 { # [doc = "< register id for REG operand"] pub reg : mips_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : mips_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mips_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mips_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op"] [:: std :: mem :: size_of :: < cs_mips_op > () - 24usize] ; ["Alignment of cs_mips_op"] [:: std :: mem :: align_of :: < cs_mips_op > () - 8usize] ; ["Offset of field: cs_mips_op::type_"] [:: std :: mem :: offset_of ! (cs_mips_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mips_op ; 10usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips"] [:: std :: mem :: size_of :: < cs_mips > () - 248usize] ; ["Alignment of cs_mips"] [:: std :: mem :: align_of :: < cs_mips > () - 8usize] ; ["Offset of field: cs_mips::op_count"] [:: std :: mem :: offset_of ! (cs_mips , op_count) - 0usize] ; ["Offset of field: cs_mips::operands"] [:: std :: mem :: offset_of ! (cs_mips , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mips { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " MIPS instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn { MIPS_INS_INVALID = 0 , MIPS_INS_ABSQ_S = 1 , MIPS_INS_ADD = 2 , MIPS_INS_ADDIUPC = 3 , MIPS_INS_ADDIUR1SP = 4 , MIPS_INS_ADDIUR2 = 5 , MIPS_INS_ADDIUS5 = 6 , MIPS_INS_ADDIUSP = 7 , MIPS_INS_ADDQH = 8 , MIPS_INS_ADDQH_R = 9 , MIPS_INS_ADDQ = 10 , MIPS_INS_ADDQ_S = 11 , MIPS_INS_ADDSC = 12 , MIPS_INS_ADDS_A = 13 , MIPS_INS_ADDS_S = 14 , MIPS_INS_ADDS_U = 15 , MIPS_INS_ADDU16 = 16 , MIPS_INS_ADDUH = 17 , MIPS_INS_ADDUH_R = 18 , MIPS_INS_ADDU = 19 , MIPS_INS_ADDU_S = 20 , MIPS_INS_ADDVI = 21 , MIPS_INS_ADDV = 22 , MIPS_INS_ADDWC = 23 , MIPS_INS_ADD_A = 24 , MIPS_INS_ADDI = 25 , MIPS_INS_ADDIU = 26 , MIPS_INS_ALIGN = 27 , MIPS_INS_ALUIPC = 28 , MIPS_INS_AND = 29 , MIPS_INS_AND16 = 30 , MIPS_INS_ANDI16 = 31 , MIPS_INS_ANDI = 32 , MIPS_INS_APPEND = 33 , MIPS_INS_ASUB_S = 34 , MIPS_INS_ASUB_U = 35 , MIPS_INS_AUI = 36 , MIPS_INS_AUIPC = 37 , MIPS_INS_AVER_S = 38 , MIPS_INS_AVER_U = 39 , MIPS_INS_AVE_S = 40 , MIPS_INS_AVE_U = 41 , MIPS_INS_B16 = 42 , MIPS_INS_BADDU = 43 , MIPS_INS_BAL = 44 , MIPS_INS_BALC = 45 , MIPS_INS_BALIGN = 46 , MIPS_INS_BBIT0 = 47 , MIPS_INS_BBIT032 = 48 , MIPS_INS_BBIT1 = 49 , MIPS_INS_BBIT132 = 50 , MIPS_INS_BC = 51 , MIPS_INS_BC0F = 52 , MIPS_INS_BC0FL = 53 , MIPS_INS_BC0T = 54 , MIPS_INS_BC0TL = 55 , MIPS_INS_BC1EQZ = 56 , MIPS_INS_BC1F = 57 , MIPS_INS_BC1FL = 58 , MIPS_INS_BC1NEZ = 59 , MIPS_INS_BC1T = 60 , MIPS_INS_BC1TL = 61 , MIPS_INS_BC2EQZ = 62 , MIPS_INS_BC2F = 63 , MIPS_INS_BC2FL = 64 , MIPS_INS_BC2NEZ = 65 , MIPS_INS_BC2T = 66 , MIPS_INS_BC2TL = 67 , MIPS_INS_BC3F = 68 , MIPS_INS_BC3FL = 69 , MIPS_INS_BC3T = 70 , MIPS_INS_BC3TL = 71 , MIPS_INS_BCLRI = 72 , MIPS_INS_BCLR = 73 , MIPS_INS_BEQ = 74 , MIPS_INS_BEQC = 75 , MIPS_INS_BEQL = 76 , MIPS_INS_BEQZ16 = 77 , MIPS_INS_BEQZALC = 78 , MIPS_INS_BEQZC = 79 , MIPS_INS_BGEC = 80 , MIPS_INS_BGEUC = 81 , MIPS_INS_BGEZ = 82 , MIPS_INS_BGEZAL = 83 , MIPS_INS_BGEZALC = 84 , MIPS_INS_BGEZALL = 85 , MIPS_INS_BGEZALS = 86 , MIPS_INS_BGEZC = 87 , MIPS_INS_BGEZL = 88 , MIPS_INS_BGTZ = 89 , MIPS_INS_BGTZALC = 90 , MIPS_INS_BGTZC = 91 , MIPS_INS_BGTZL = 92 , MIPS_INS_BINSLI = 93 , MIPS_INS_BINSL = 94 , MIPS_INS_BINSRI = 95 , MIPS_INS_BINSR = 96 , MIPS_INS_BITREV = 97 , MIPS_INS_BITSWAP = 98 , MIPS_INS_BLEZ = 99 , MIPS_INS_BLEZALC = 100 , MIPS_INS_BLEZC = 101 , MIPS_INS_BLEZL = 102 , MIPS_INS_BLTC = 103 , MIPS_INS_BLTUC = 104 , MIPS_INS_BLTZ = 105 , MIPS_INS_BLTZAL = 106 , MIPS_INS_BLTZALC = 107 , MIPS_INS_BLTZALL = 108 , MIPS_INS_BLTZALS = 109 , MIPS_INS_BLTZC = 110 , MIPS_INS_BLTZL = 111 , MIPS_INS_BMNZI = 112 , MIPS_INS_BMNZ = 113 , MIPS_INS_BMZI = 114 , MIPS_INS_BMZ = 115 , MIPS_INS_BNE = 116 , MIPS_INS_BNEC = 117 , MIPS_INS_BNEGI = 118 , MIPS_INS_BNEG = 119 , MIPS_INS_BNEL = 120 , MIPS_INS_BNEZ16 = 121 , MIPS_INS_BNEZALC = 122 , MIPS_INS_BNEZC = 123 , MIPS_INS_BNVC = 124 , MIPS_INS_BNZ = 125 , MIPS_INS_BOVC = 126 , MIPS_INS_BPOSGE32 = 127 , MIPS_INS_BREAK = 128 , MIPS_INS_BREAK16 = 129 , MIPS_INS_BSELI = 130 , MIPS_INS_BSEL = 131 , MIPS_INS_BSETI = 132 , MIPS_INS_BSET = 133 , MIPS_INS_BZ = 134 , MIPS_INS_BEQZ = 135 , MIPS_INS_B = 136 , MIPS_INS_BNEZ = 137 , MIPS_INS_BTEQZ = 138 , MIPS_INS_BTNEZ = 139 , MIPS_INS_CACHE = 140 , MIPS_INS_CEIL = 141 , MIPS_INS_CEQI = 142 , MIPS_INS_CEQ = 143 , MIPS_INS_CFC1 = 144 , MIPS_INS_CFCMSA = 145 , MIPS_INS_CINS = 146 , MIPS_INS_CINS32 = 147 , MIPS_INS_CLASS = 148 , MIPS_INS_CLEI_S = 149 , MIPS_INS_CLEI_U = 150 , MIPS_INS_CLE_S = 151 , MIPS_INS_CLE_U = 152 , MIPS_INS_CLO = 153 , MIPS_INS_CLTI_S = 154 , MIPS_INS_CLTI_U = 155 , MIPS_INS_CLT_S = 156 , MIPS_INS_CLT_U = 157 , MIPS_INS_CLZ = 158 , MIPS_INS_CMPGDU = 159 , MIPS_INS_CMPGU = 160 , MIPS_INS_CMPU = 161 , MIPS_INS_CMP = 162 , MIPS_INS_COPY_S = 163 , MIPS_INS_COPY_U = 164 , MIPS_INS_CTC1 = 165 , MIPS_INS_CTCMSA = 166 , MIPS_INS_CVT = 167 , MIPS_INS_C = 168 , MIPS_INS_CMPI = 169 , MIPS_INS_DADD = 170 , MIPS_INS_DADDI = 171 , MIPS_INS_DADDIU = 172 , MIPS_INS_DADDU = 173 , MIPS_INS_DAHI = 174 , MIPS_INS_DALIGN = 175 , MIPS_INS_DATI = 176 , MIPS_INS_DAUI = 177 , MIPS_INS_DBITSWAP = 178 , MIPS_INS_DCLO = 179 , MIPS_INS_DCLZ = 180 , MIPS_INS_DDIV = 181 , MIPS_INS_DDIVU = 182 , MIPS_INS_DERET = 183 , MIPS_INS_DEXT = 184 , MIPS_INS_DEXTM = 185 , MIPS_INS_DEXTU = 186 , MIPS_INS_DI = 187 , MIPS_INS_DINS = 188 , MIPS_INS_DINSM = 189 , MIPS_INS_DINSU = 190 , MIPS_INS_DIV = 191 , MIPS_INS_DIVU = 192 , MIPS_INS_DIV_S = 193 , MIPS_INS_DIV_U = 194 , MIPS_INS_DLSA = 195 , MIPS_INS_DMFC0 = 196 , MIPS_INS_DMFC1 = 197 , MIPS_INS_DMFC2 = 198 , MIPS_INS_DMOD = 199 , MIPS_INS_DMODU = 200 , MIPS_INS_DMTC0 = 201 , MIPS_INS_DMTC1 = 202 , MIPS_INS_DMTC2 = 203 , MIPS_INS_DMUH = 204 , MIPS_INS_DMUHU = 205 , MIPS_INS_DMUL = 206 , MIPS_INS_DMULT = 207 , MIPS_INS_DMULTU = 208 , MIPS_INS_DMULU = 209 , MIPS_INS_DOTP_S = 210 , MIPS_INS_DOTP_U = 211 , MIPS_INS_DPADD_S = 212 , MIPS_INS_DPADD_U = 213 , MIPS_INS_DPAQX_SA = 214 , MIPS_INS_DPAQX_S = 215 , MIPS_INS_DPAQ_SA = 216 , MIPS_INS_DPAQ_S = 217 , MIPS_INS_DPAU = 218 , MIPS_INS_DPAX = 219 , MIPS_INS_DPA = 220 , MIPS_INS_DPOP = 221 , MIPS_INS_DPSQX_SA = 222 , MIPS_INS_DPSQX_S = 223 , MIPS_INS_DPSQ_SA = 224 , MIPS_INS_DPSQ_S = 225 , MIPS_INS_DPSUB_S = 226 , MIPS_INS_DPSUB_U = 227 , MIPS_INS_DPSU = 228 , MIPS_INS_DPSX = 229 , MIPS_INS_DPS = 230 , MIPS_INS_DROTR = 231 , MIPS_INS_DROTR32 = 232 , MIPS_INS_DROTRV = 233 , MIPS_INS_DSBH = 234 , MIPS_INS_DSHD = 235 , MIPS_INS_DSLL = 236 , MIPS_INS_DSLL32 = 237 , MIPS_INS_DSLLV = 238 , MIPS_INS_DSRA = 239 , MIPS_INS_DSRA32 = 240 , MIPS_INS_DSRAV = 241 , MIPS_INS_DSRL = 242 , MIPS_INS_DSRL32 = 243 , MIPS_INS_DSRLV = 244 , MIPS_INS_DSUB = 245 , MIPS_INS_DSUBU = 246 , MIPS_INS_EHB = 247 , MIPS_INS_EI = 248 , MIPS_INS_ERET = 249 , MIPS_INS_EXT = 250 , MIPS_INS_EXTP = 251 , MIPS_INS_EXTPDP = 252 , MIPS_INS_EXTPDPV = 253 , MIPS_INS_EXTPV = 254 , MIPS_INS_EXTRV_RS = 255 , MIPS_INS_EXTRV_R = 256 , MIPS_INS_EXTRV_S = 257 , MIPS_INS_EXTRV = 258 , MIPS_INS_EXTR_RS = 259 , MIPS_INS_EXTR_R = 260 , MIPS_INS_EXTR_S = 261 , MIPS_INS_EXTR = 262 , MIPS_INS_EXTS = 263 , MIPS_INS_EXTS32 = 264 , MIPS_INS_ABS = 265 , MIPS_INS_FADD = 266 , MIPS_INS_FCAF = 267 , MIPS_INS_FCEQ = 268 , MIPS_INS_FCLASS = 269 , MIPS_INS_FCLE = 270 , MIPS_INS_FCLT = 271 , MIPS_INS_FCNE = 272 , MIPS_INS_FCOR = 273 , MIPS_INS_FCUEQ = 274 , MIPS_INS_FCULE = 275 , MIPS_INS_FCULT = 276 , MIPS_INS_FCUNE = 277 , MIPS_INS_FCUN = 278 , MIPS_INS_FDIV = 279 , MIPS_INS_FEXDO = 280 , MIPS_INS_FEXP2 = 281 , MIPS_INS_FEXUPL = 282 , MIPS_INS_FEXUPR = 283 , MIPS_INS_FFINT_S = 284 , MIPS_INS_FFINT_U = 285 , MIPS_INS_FFQL = 286 , MIPS_INS_FFQR = 287 , MIPS_INS_FILL = 288 , MIPS_INS_FLOG2 = 289 , MIPS_INS_FLOOR = 290 , MIPS_INS_FMADD = 291 , MIPS_INS_FMAX_A = 292 , MIPS_INS_FMAX = 293 , MIPS_INS_FMIN_A = 294 , MIPS_INS_FMIN = 295 , MIPS_INS_MOV = 296 , MIPS_INS_FMSUB = 297 , MIPS_INS_FMUL = 298 , MIPS_INS_MUL = 299 , MIPS_INS_NEG = 300 , MIPS_INS_FRCP = 301 , MIPS_INS_FRINT = 302 , MIPS_INS_FRSQRT = 303 , MIPS_INS_FSAF = 304 , MIPS_INS_FSEQ = 305 , MIPS_INS_FSLE = 306 , MIPS_INS_FSLT = 307 , MIPS_INS_FSNE = 308 , MIPS_INS_FSOR = 309 , MIPS_INS_FSQRT = 310 , MIPS_INS_SQRT = 311 , MIPS_INS_FSUB = 312 , MIPS_INS_SUB = 313 , MIPS_INS_FSUEQ = 314 , MIPS_INS_FSULE = 315 , MIPS_INS_FSULT = 316 , MIPS_INS_FSUNE = 317 , MIPS_INS_FSUN = 318 , MIPS_INS_FTINT_S = 319 , MIPS_INS_FTINT_U = 320 , MIPS_INS_FTQ = 321 , MIPS_INS_FTRUNC_S = 322 , MIPS_INS_FTRUNC_U = 323 , MIPS_INS_HADD_S = 324 , MIPS_INS_HADD_U = 325 , MIPS_INS_HSUB_S = 326 , MIPS_INS_HSUB_U = 327 , MIPS_INS_ILVEV = 328 , MIPS_INS_ILVL = 329 , MIPS_INS_ILVOD = 330 , MIPS_INS_ILVR = 331 , MIPS_INS_INS = 332 , MIPS_INS_INSERT = 333 , MIPS_INS_INSV = 334 , MIPS_INS_INSVE = 335 , MIPS_INS_J = 336 , MIPS_INS_JAL = 337 , MIPS_INS_JALR = 338 , MIPS_INS_JALRS16 = 339 , MIPS_INS_JALRS = 340 , MIPS_INS_JALS = 341 , MIPS_INS_JALX = 342 , MIPS_INS_JIALC = 343 , MIPS_INS_JIC = 344 , MIPS_INS_JR = 345 , MIPS_INS_JR16 = 346 , MIPS_INS_JRADDIUSP = 347 , MIPS_INS_JRC = 348 , MIPS_INS_JALRC = 349 , MIPS_INS_LB = 350 , MIPS_INS_LBU16 = 351 , MIPS_INS_LBUX = 352 , MIPS_INS_LBU = 353 , MIPS_INS_LD = 354 , MIPS_INS_LDC1 = 355 , MIPS_INS_LDC2 = 356 , MIPS_INS_LDC3 = 357 , MIPS_INS_LDI = 358 , MIPS_INS_LDL = 359 , MIPS_INS_LDPC = 360 , MIPS_INS_LDR = 361 , MIPS_INS_LDXC1 = 362 , MIPS_INS_LH = 363 , MIPS_INS_LHU16 = 364 , MIPS_INS_LHX = 365 , MIPS_INS_LHU = 366 , MIPS_INS_LI16 = 367 , MIPS_INS_LL = 368 , MIPS_INS_LLD = 369 , MIPS_INS_LSA = 370 , MIPS_INS_LUXC1 = 371 , MIPS_INS_LUI = 372 , MIPS_INS_LW = 373 , MIPS_INS_LW16 = 374 , MIPS_INS_LWC1 = 375 , MIPS_INS_LWC2 = 376 , MIPS_INS_LWC3 = 377 , MIPS_INS_LWL = 378 , MIPS_INS_LWM16 = 379 , MIPS_INS_LWM32 = 380 , MIPS_INS_LWPC = 381 , MIPS_INS_LWP = 382 , MIPS_INS_LWR = 383 , MIPS_INS_LWUPC = 384 , MIPS_INS_LWU = 385 , MIPS_INS_LWX = 386 , MIPS_INS_LWXC1 = 387 , MIPS_INS_LWXS = 388 , MIPS_INS_LI = 389 , MIPS_INS_MADD = 390 , MIPS_INS_MADDF = 391 , MIPS_INS_MADDR_Q = 392 , MIPS_INS_MADDU = 393 , MIPS_INS_MADDV = 394 , MIPS_INS_MADD_Q = 395 , MIPS_INS_MAQ_SA = 396 , MIPS_INS_MAQ_S = 397 , MIPS_INS_MAXA = 398 , MIPS_INS_MAXI_S = 399 , MIPS_INS_MAXI_U = 400 , MIPS_INS_MAX_A = 401 , MIPS_INS_MAX = 402 , MIPS_INS_MAX_S = 403 , MIPS_INS_MAX_U = 404 , MIPS_INS_MFC0 = 405 , MIPS_INS_MFC1 = 406 , MIPS_INS_MFC2 = 407 , MIPS_INS_MFHC1 = 408 , MIPS_INS_MFHI = 409 , MIPS_INS_MFLO = 410 , MIPS_INS_MINA = 411 , MIPS_INS_MINI_S = 412 , MIPS_INS_MINI_U = 413 , MIPS_INS_MIN_A = 414 , MIPS_INS_MIN = 415 , MIPS_INS_MIN_S = 416 , MIPS_INS_MIN_U = 417 , MIPS_INS_MOD = 418 , MIPS_INS_MODSUB = 419 , MIPS_INS_MODU = 420 , MIPS_INS_MOD_S = 421 , MIPS_INS_MOD_U = 422 , MIPS_INS_MOVE = 423 , MIPS_INS_MOVEP = 424 , MIPS_INS_MOVF = 425 , MIPS_INS_MOVN = 426 , MIPS_INS_MOVT = 427 , MIPS_INS_MOVZ = 428 , MIPS_INS_MSUB = 429 , MIPS_INS_MSUBF = 430 , MIPS_INS_MSUBR_Q = 431 , MIPS_INS_MSUBU = 432 , MIPS_INS_MSUBV = 433 , MIPS_INS_MSUB_Q = 434 , MIPS_INS_MTC0 = 435 , MIPS_INS_MTC1 = 436 , MIPS_INS_MTC2 = 437 , MIPS_INS_MTHC1 = 438 , MIPS_INS_MTHI = 439 , MIPS_INS_MTHLIP = 440 , MIPS_INS_MTLO = 441 , MIPS_INS_MTM0 = 442 , MIPS_INS_MTM1 = 443 , MIPS_INS_MTM2 = 444 , MIPS_INS_MTP0 = 445 , MIPS_INS_MTP1 = 446 , MIPS_INS_MTP2 = 447 , MIPS_INS_MUH = 448 , MIPS_INS_MUHU = 449 , MIPS_INS_MULEQ_S = 450 , MIPS_INS_MULEU_S = 451 , MIPS_INS_MULQ_RS = 452 , MIPS_INS_MULQ_S = 453 , MIPS_INS_MULR_Q = 454 , MIPS_INS_MULSAQ_S = 455 , MIPS_INS_MULSA = 456 , MIPS_INS_MULT = 457 , MIPS_INS_MULTU = 458 , MIPS_INS_MULU = 459 , MIPS_INS_MULV = 460 , MIPS_INS_MUL_Q = 461 , MIPS_INS_MUL_S = 462 , MIPS_INS_NLOC = 463 , MIPS_INS_NLZC = 464 , MIPS_INS_NMADD = 465 , MIPS_INS_NMSUB = 466 , MIPS_INS_NOR = 467 , MIPS_INS_NORI = 468 , MIPS_INS_NOT16 = 469 , MIPS_INS_NOT = 470 , MIPS_INS_OR = 471 , MIPS_INS_OR16 = 472 , MIPS_INS_ORI = 473 , MIPS_INS_PACKRL = 474 , MIPS_INS_PAUSE = 475 , MIPS_INS_PCKEV = 476 , MIPS_INS_PCKOD = 477 , MIPS_INS_PCNT = 478 , MIPS_INS_PICK = 479 , MIPS_INS_POP = 480 , MIPS_INS_PRECEQU = 481 , MIPS_INS_PRECEQ = 482 , MIPS_INS_PRECEU = 483 , MIPS_INS_PRECRQU_S = 484 , MIPS_INS_PRECRQ = 485 , MIPS_INS_PRECRQ_RS = 486 , MIPS_INS_PRECR = 487 , MIPS_INS_PRECR_SRA = 488 , MIPS_INS_PRECR_SRA_R = 489 , MIPS_INS_PREF = 490 , MIPS_INS_PREPEND = 491 , MIPS_INS_RADDU = 492 , MIPS_INS_RDDSP = 493 , MIPS_INS_RDHWR = 494 , MIPS_INS_REPLV = 495 , MIPS_INS_REPL = 496 , MIPS_INS_RINT = 497 , MIPS_INS_ROTR = 498 , MIPS_INS_ROTRV = 499 , MIPS_INS_ROUND = 500 , MIPS_INS_SAT_S = 501 , MIPS_INS_SAT_U = 502 , MIPS_INS_SB = 503 , MIPS_INS_SB16 = 504 , MIPS_INS_SC = 505 , MIPS_INS_SCD = 506 , MIPS_INS_SD = 507 , MIPS_INS_SDBBP = 508 , MIPS_INS_SDBBP16 = 509 , MIPS_INS_SDC1 = 510 , MIPS_INS_SDC2 = 511 , MIPS_INS_SDC3 = 512 , MIPS_INS_SDL = 513 , MIPS_INS_SDR = 514 , MIPS_INS_SDXC1 = 515 , MIPS_INS_SEB = 516 , MIPS_INS_SEH = 517 , MIPS_INS_SELEQZ = 518 , MIPS_INS_SELNEZ = 519 , MIPS_INS_SEL = 520 , MIPS_INS_SEQ = 521 , MIPS_INS_SEQI = 522 , MIPS_INS_SH = 523 , MIPS_INS_SH16 = 524 , MIPS_INS_SHF = 525 , MIPS_INS_SHILO = 526 , MIPS_INS_SHILOV = 527 , MIPS_INS_SHLLV = 528 , MIPS_INS_SHLLV_S = 529 , MIPS_INS_SHLL = 530 , MIPS_INS_SHLL_S = 531 , MIPS_INS_SHRAV = 532 , MIPS_INS_SHRAV_R = 533 , MIPS_INS_SHRA = 534 , MIPS_INS_SHRA_R = 535 , MIPS_INS_SHRLV = 536 , MIPS_INS_SHRL = 537 , MIPS_INS_SLDI = 538 , MIPS_INS_SLD = 539 , MIPS_INS_SLL = 540 , MIPS_INS_SLL16 = 541 , MIPS_INS_SLLI = 542 , MIPS_INS_SLLV = 543 , MIPS_INS_SLT = 544 , MIPS_INS_SLTI = 545 , MIPS_INS_SLTIU = 546 , MIPS_INS_SLTU = 547 , MIPS_INS_SNE = 548 , MIPS_INS_SNEI = 549 , MIPS_INS_SPLATI = 550 , MIPS_INS_SPLAT = 551 , MIPS_INS_SRA = 552 , MIPS_INS_SRAI = 553 , MIPS_INS_SRARI = 554 , MIPS_INS_SRAR = 555 , MIPS_INS_SRAV = 556 , MIPS_INS_SRL = 557 , MIPS_INS_SRL16 = 558 , MIPS_INS_SRLI = 559 , MIPS_INS_SRLRI = 560 , MIPS_INS_SRLR = 561 , MIPS_INS_SRLV = 562 , MIPS_INS_SSNOP = 563 , MIPS_INS_ST = 564 , MIPS_INS_SUBQH = 565 , MIPS_INS_SUBQH_R = 566 , MIPS_INS_SUBQ = 567 , MIPS_INS_SUBQ_S = 568 , MIPS_INS_SUBSUS_U = 569 , MIPS_INS_SUBSUU_S = 570 , MIPS_INS_SUBS_S = 571 , MIPS_INS_SUBS_U = 572 , MIPS_INS_SUBU16 = 573 , MIPS_INS_SUBUH = 574 , MIPS_INS_SUBUH_R = 575 , MIPS_INS_SUBU = 576 , MIPS_INS_SUBU_S = 577 , MIPS_INS_SUBVI = 578 , MIPS_INS_SUBV = 579 , MIPS_INS_SUXC1 = 580 , MIPS_INS_SW = 581 , MIPS_INS_SW16 = 582 , MIPS_INS_SWC1 = 583 , MIPS_INS_SWC2 = 584 , MIPS_INS_SWC3 = 585 , MIPS_INS_SWL = 586 , MIPS_INS_SWM16 = 587 , MIPS_INS_SWM32 = 588 , MIPS_INS_SWP = 589 , MIPS_INS_SWR = 590 , MIPS_INS_SWXC1 = 591 , MIPS_INS_SYNC = 592 , MIPS_INS_SYNCI = 593 , MIPS_INS_SYSCALL = 594 , MIPS_INS_TEQ = 595 , MIPS_INS_TEQI = 596 , MIPS_INS_TGE = 597 , MIPS_INS_TGEI = 598 , MIPS_INS_TGEIU = 599 , MIPS_INS_TGEU = 600 , MIPS_INS_TLBP = 601 , MIPS_INS_TLBR = 602 , MIPS_INS_TLBWI = 603 , MIPS_INS_TLBWR = 604 , MIPS_INS_TLT = 605 , MIPS_INS_TLTI = 606 , MIPS_INS_TLTIU = 607 , MIPS_INS_TLTU = 608 , MIPS_INS_TNE = 609 , MIPS_INS_TNEI = 610 , MIPS_INS_TRUNC = 611 , MIPS_INS_V3MULU = 612 , MIPS_INS_VMM0 = 613 , MIPS_INS_VMULU = 614 , MIPS_INS_VSHF = 615 , MIPS_INS_WAIT = 616 , MIPS_INS_WRDSP = 617 , MIPS_INS_WSBH = 618 , MIPS_INS_XOR = 619 , MIPS_INS_XOR16 = 620 , MIPS_INS_XORI = 621 , MIPS_INS_NOP = 622 , MIPS_INS_NEGU = 623 , MIPS_INS_JALR_HB = 624 , MIPS_INS_JR_HB = 625 , MIPS_INS_ENDING = 626 , } # [repr (u32)] # [doc = " Group of MIPS instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn_group { # [doc = "< = CS_GRP_INVALID"] MIPS_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MIPS_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] MIPS_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MIPS_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MIPS_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MIPS_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] MIPS_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MIPS_GRP_BRANCH_RELATIVE = 7 , MIPS_GRP_BITCOUNT = 128 , MIPS_GRP_DSP = 129 , MIPS_GRP_DSPR2 = 130 , MIPS_GRP_FPIDX = 131 , MIPS_GRP_MSA = 132 , MIPS_GRP_MIPS32R2 = 133 , MIPS_GRP_MIPS64 = 134 , MIPS_GRP_MIPS64R2 = 135 , MIPS_GRP_SEINREG = 136 , MIPS_GRP_STDENC = 137 , MIPS_GRP_SWAP = 138 , MIPS_GRP_MICROMIPS = 139 , MIPS_GRP_MIPS16MODE = 140 , MIPS_GRP_FP64BIT = 141 , MIPS_GRP_NONANSFPMATH = 142 , MIPS_GRP_NOTFP64BIT = 143 , MIPS_GRP_NOTINMICROMIPS = 144 , MIPS_GRP_NOTNACL = 145 , MIPS_GRP_NOTMIPS32R6 = 146 , MIPS_GRP_NOTMIPS64R6 = 147 , MIPS_GRP_CNMIPS = 148 , MIPS_GRP_MIPS32 = 149 , MIPS_GRP_MIPS32R6 = 150 , MIPS_GRP_MIPS64R6 = 151 , MIPS_GRP_MIPS2 = 152 , MIPS_GRP_MIPS3 = 153 , MIPS_GRP_MIPS3_32 = 154 , MIPS_GRP_MIPS3_32R2 = 155 , MIPS_GRP_MIPS4_32 = 156 , MIPS_GRP_MIPS4_32R2 = 157 , MIPS_GRP_MIPS5_32R2 = 158 , MIPS_GRP_GP32BIT = 159 , MIPS_GRP_GP64BIT = 160 , MIPS_GRP_ENDING = 161 , } # [repr (u32)] # [doc = " PPC branch codes for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bc { PPC_BC_INVALID = 0 , PPC_BC_LT = 12 , PPC_BC_LE = 36 , PPC_BC_EQ = 76 , PPC_BC_GE = 4 , PPC_BC_GT = 44 , PPC_BC_NE = 68 , PPC_BC_UN = 108 , PPC_BC_NU = 100 , # [doc = "< summary overflow"] PPC_BC_SO = 140 , # [doc = "< not summary overflow"] PPC_BC_NS = 132 , } # [repr (u32)] # [doc = " PPC branch hint for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bh { # [doc = "< no hint"] PPC_BH_INVALID = 0 , # [doc = "< PLUS hint"] PPC_BH_PLUS = 1 , # [doc = "< MINUS hint"] PPC_BH_MINUS = 2 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] PPC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] PPC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] PPC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] PPC_OP_MEM = 3 , # [doc = "< Condition Register field"] PPC_OP_CRX = 64 , } # [repr (u32)] # [doc = " PPC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_reg { PPC_REG_INVALID = 0 , PPC_REG_CARRY = 2 , PPC_REG_CTR = 3 , PPC_REG_LR = 5 , PPC_REG_RM = 6 , PPC_REG_VRSAVE = 8 , PPC_REG_XER = 9 , PPC_REG_ZERO = 10 , PPC_REG_CR0 = 12 , PPC_REG_CR1 = 13 , PPC_REG_CR2 = 14 , PPC_REG_CR3 = 15 , PPC_REG_CR4 = 16 , PPC_REG_CR5 = 17 , PPC_REG_CR6 = 18 , PPC_REG_CR7 = 19 , PPC_REG_CTR8 = 20 , PPC_REG_F0 = 21 , PPC_REG_F1 = 22 , PPC_REG_F2 = 23 , PPC_REG_F3 = 24 , PPC_REG_F4 = 25 , PPC_REG_F5 = 26 , PPC_REG_F6 = 27 , PPC_REG_F7 = 28 , PPC_REG_F8 = 29 , PPC_REG_F9 = 30 , PPC_REG_F10 = 31 , PPC_REG_F11 = 32 , PPC_REG_F12 = 33 , PPC_REG_F13 = 34 , PPC_REG_F14 = 35 , PPC_REG_F15 = 36 , PPC_REG_F16 = 37 , PPC_REG_F17 = 38 , PPC_REG_F18 = 39 , PPC_REG_F19 = 40 , PPC_REG_F20 = 41 , PPC_REG_F21 = 42 , PPC_REG_F22 = 43 , PPC_REG_F23 = 44 , PPC_REG_F24 = 45 , PPC_REG_F25 = 46 , PPC_REG_F26 = 47 , PPC_REG_F27 = 48 , PPC_REG_F28 = 49 , PPC_REG_F29 = 50 , PPC_REG_F30 = 51 , PPC_REG_F31 = 52 , PPC_REG_LR8 = 54 , PPC_REG_Q0 = 55 , PPC_REG_Q1 = 56 , PPC_REG_Q2 = 57 , PPC_REG_Q3 = 58 , PPC_REG_Q4 = 59 , PPC_REG_Q5 = 60 , PPC_REG_Q6 = 61 , PPC_REG_Q7 = 62 , PPC_REG_Q8 = 63 , PPC_REG_Q9 = 64 , PPC_REG_Q10 = 65 , PPC_REG_Q11 = 66 , PPC_REG_Q12 = 67 , PPC_REG_Q13 = 68 , PPC_REG_Q14 = 69 , PPC_REG_Q15 = 70 , PPC_REG_Q16 = 71 , PPC_REG_Q17 = 72 , PPC_REG_Q18 = 73 , PPC_REG_Q19 = 74 , PPC_REG_Q20 = 75 , PPC_REG_Q21 = 76 , PPC_REG_Q22 = 77 , PPC_REG_Q23 = 78 , PPC_REG_Q24 = 79 , PPC_REG_Q25 = 80 , PPC_REG_Q26 = 81 , PPC_REG_Q27 = 82 , PPC_REG_Q28 = 83 , PPC_REG_Q29 = 84 , PPC_REG_Q30 = 85 , PPC_REG_Q31 = 86 , PPC_REG_R0 = 87 , PPC_REG_R1 = 88 , PPC_REG_R2 = 89 , PPC_REG_R3 = 90 , PPC_REG_R4 = 91 , PPC_REG_R5 = 92 , PPC_REG_R6 = 93 , PPC_REG_R7 = 94 , PPC_REG_R8 = 95 , PPC_REG_R9 = 96 , PPC_REG_R10 = 97 , PPC_REG_R11 = 98 , PPC_REG_R12 = 99 , PPC_REG_R13 = 100 , PPC_REG_R14 = 101 , PPC_REG_R15 = 102 , PPC_REG_R16 = 103 , PPC_REG_R17 = 104 , PPC_REG_R18 = 105 , PPC_REG_R19 = 106 , PPC_REG_R20 = 107 , PPC_REG_R21 = 108 , PPC_REG_R22 = 109 , PPC_REG_R23 = 110 , PPC_REG_R24 = 111 , PPC_REG_R25 = 112 , PPC_REG_R26 = 113 , PPC_REG_R27 = 114 , PPC_REG_R28 = 115 , PPC_REG_R29 = 116 , PPC_REG_R30 = 117 , PPC_REG_R31 = 118 , PPC_REG_V0 = 151 , PPC_REG_V1 = 152 , PPC_REG_V2 = 153 , PPC_REG_V3 = 154 , PPC_REG_V4 = 155 , PPC_REG_V5 = 156 , PPC_REG_V6 = 157 , PPC_REG_V7 = 158 , PPC_REG_V8 = 159 , PPC_REG_V9 = 160 , PPC_REG_V10 = 161 , PPC_REG_V11 = 162 , PPC_REG_V12 = 163 , PPC_REG_V13 = 164 , PPC_REG_V14 = 165 , PPC_REG_V15 = 166 , PPC_REG_V16 = 167 , PPC_REG_V17 = 168 , PPC_REG_V18 = 169 , PPC_REG_V19 = 170 , PPC_REG_V20 = 171 , PPC_REG_V21 = 172 , PPC_REG_V22 = 173 , PPC_REG_V23 = 174 , PPC_REG_V24 = 175 , PPC_REG_V25 = 176 , PPC_REG_V26 = 177 , PPC_REG_V27 = 178 , PPC_REG_V28 = 179 , PPC_REG_V29 = 180 , PPC_REG_V30 = 181 , PPC_REG_V31 = 182 , PPC_REG_VS0 = 215 , PPC_REG_VS1 = 216 , PPC_REG_VS2 = 217 , PPC_REG_VS3 = 218 , PPC_REG_VS4 = 219 , PPC_REG_VS5 = 220 , PPC_REG_VS6 = 221 , PPC_REG_VS7 = 222 , PPC_REG_VS8 = 223 , PPC_REG_VS9 = 224 , PPC_REG_VS10 = 225 , PPC_REG_VS11 = 226 , PPC_REG_VS12 = 227 , PPC_REG_VS13 = 228 , PPC_REG_VS14 = 229 , PPC_REG_VS15 = 230 , PPC_REG_VS16 = 231 , PPC_REG_VS17 = 232 , PPC_REG_VS18 = 233 , PPC_REG_VS19 = 234 , PPC_REG_VS20 = 235 , PPC_REG_VS21 = 236 , PPC_REG_VS22 = 237 , PPC_REG_VS23 = 238 , PPC_REG_VS24 = 239 , PPC_REG_VS25 = 240 , PPC_REG_VS26 = 241 , PPC_REG_VS27 = 242 , PPC_REG_VS28 = 243 , PPC_REG_VS29 = 244 , PPC_REG_VS30 = 245 , PPC_REG_VS31 = 246 , PPC_REG_VS32 = 247 , PPC_REG_VS33 = 248 , PPC_REG_VS34 = 249 , PPC_REG_VS35 = 250 , PPC_REG_VS36 = 251 , PPC_REG_VS37 = 252 , PPC_REG_VS38 = 253 , PPC_REG_VS39 = 254 , PPC_REG_VS40 = 255 , PPC_REG_VS41 = 256 , PPC_REG_VS42 = 257 , PPC_REG_VS43 = 258 , PPC_REG_VS44 = 259 , PPC_REG_VS45 = 260 , PPC_REG_VS46 = 261 , PPC_REG_VS47 = 262 , PPC_REG_VS48 = 263 , PPC_REG_VS49 = 264 , PPC_REG_VS50 = 265 , PPC_REG_VS51 = 266 , PPC_REG_VS52 = 267 , PPC_REG_VS53 = 268 , PPC_REG_VS54 = 269 , PPC_REG_VS55 = 270 , PPC_REG_VS56 = 271 , PPC_REG_VS57 = 272 , PPC_REG_VS58 = 273 , PPC_REG_VS59 = 274 , PPC_REG_VS60 = 275 , PPC_REG_VS61 = 276 , PPC_REG_VS62 = 277 , PPC_REG_VS63 = 278 , PPC_REG_CR0EQ = 312 , PPC_REG_CR1EQ = 313 , PPC_REG_CR2EQ = 314 , PPC_REG_CR3EQ = 315 , PPC_REG_CR4EQ = 316 , PPC_REG_CR5EQ = 317 , PPC_REG_CR6EQ = 318 , PPC_REG_CR7EQ = 319 , PPC_REG_CR0GT = 320 , PPC_REG_CR1GT = 321 , PPC_REG_CR2GT = 322 , PPC_REG_CR3GT = 323 , PPC_REG_CR4GT = 324 , PPC_REG_CR5GT = 325 , PPC_REG_CR6GT = 326 , PPC_REG_CR7GT = 327 , PPC_REG_CR0LT = 328 , PPC_REG_CR1LT = 329 , PPC_REG_CR2LT = 330 , PPC_REG_CR3LT = 331 , PPC_REG_CR4LT = 332 , PPC_REG_CR5LT = 333 , PPC_REG_CR6LT = 334 , PPC_REG_CR7LT = 335 , PPC_REG_CR0UN = 336 , PPC_REG_CR1UN = 337 , PPC_REG_CR2UN = 338 , PPC_REG_CR3UN = 339 , PPC_REG_CR4UN = 340 , PPC_REG_CR5UN = 341 , PPC_REG_CR6UN = 342 , PPC_REG_CR7UN = 343 , PPC_REG_ENDING = 344 , } # [doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_mem { # [doc = "< base register"] pub base : ppc_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_mem"] [:: std :: mem :: size_of :: < ppc_op_mem > () - 8usize] ; ["Alignment of ppc_op_mem"] [:: std :: mem :: align_of :: < ppc_op_mem > () - 4usize] ; ["Offset of field: ppc_op_mem::base"] [:: std :: mem :: offset_of ! (ppc_op_mem , base) - 0usize] ; ["Offset of field: ppc_op_mem::disp"] [:: std :: mem :: offset_of ! (ppc_op_mem , disp) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_crx { pub scale : :: std :: os :: raw :: c_uint , pub reg : ppc_reg , pub cond : ppc_bc , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_crx"] [:: std :: mem :: size_of :: < ppc_op_crx > () - 12usize] ; ["Alignment of ppc_op_crx"] [:: std :: mem :: align_of :: < ppc_op_crx > () - 4usize] ; ["Offset of field: ppc_op_crx::scale"] [:: std :: mem :: offset_of ! (ppc_op_crx , scale) - 0usize] ; ["Offset of field: ppc_op_crx::reg"] [:: std :: mem :: offset_of ! (ppc_op_crx , reg) - 4usize] ; ["Offset of field: ppc_op_crx::cond"] [:: std :: mem :: offset_of ! (ppc_op_crx , cond) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc_op { # [doc = "< operand type"] pub type_ : ppc_op_type , pub __bindgen_anon_1 : cs_ppc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_ppc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : ppc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : ppc_op_mem , # [doc = "< operand with condition register"] pub crx : ppc_op_crx , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_ppc_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_ppc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::crx"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , crx) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op"] [:: std :: mem :: size_of :: < cs_ppc_op > () - 24usize] ; ["Alignment of cs_ppc_op"] [:: std :: mem :: align_of :: < cs_ppc_op > () - 8usize] ; ["Offset of field: cs_ppc_op::type_"] [:: std :: mem :: offset_of ! (cs_ppc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc { # [doc = " branch code for branch instructions"] pub bc : ppc_bc , # [doc = " branch hint for branch instructions"] pub bh : ppc_bh , # [doc = " if update_cr0 = True, then this 'dot' insn updates CR0"] pub update_cr0 : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_ppc_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc"] [:: std :: mem :: size_of :: < cs_ppc > () - 208usize] ; ["Alignment of cs_ppc"] [:: std :: mem :: align_of :: < cs_ppc > () - 8usize] ; ["Offset of field: cs_ppc::bc"] [:: std :: mem :: offset_of ! (cs_ppc , bc) - 0usize] ; ["Offset of field: cs_ppc::bh"] [:: std :: mem :: offset_of ! (cs_ppc , bh) - 4usize] ; ["Offset of field: cs_ppc::update_cr0"] [:: std :: mem :: offset_of ! (cs_ppc , update_cr0) - 8usize] ; ["Offset of field: cs_ppc::op_count"] [:: std :: mem :: offset_of ! (cs_ppc , op_count) - 9usize] ; ["Offset of field: cs_ppc::operands"] [:: std :: mem :: offset_of ! (cs_ppc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}" , self . bc , self . bh , self . update_cr0 , self . op_count , self . operands) } } # [repr (u32)] # [doc = " PPC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn { PPC_INS_INVALID = 0 , PPC_INS_ADD = 1 , PPC_INS_ADDC = 2 , PPC_INS_ADDE = 3 , PPC_INS_ADDI = 4 , PPC_INS_ADDIC = 5 , PPC_INS_ADDIS = 6 , PPC_INS_ADDME = 7 , PPC_INS_ADDPCIS = 8 , PPC_INS_ADDZE = 9 , PPC_INS_AND = 10 , PPC_INS_ANDC = 11 , PPC_INS_ANDI = 12 , PPC_INS_ANDIS = 13 , PPC_INS_ATTN = 14 , PPC_INS_B = 15 , PPC_INS_BA = 16 , PPC_INS_BC = 17 , PPC_INS_BCA = 18 , PPC_INS_BCCTR = 19 , PPC_INS_BCCTRL = 20 , PPC_INS_BCDCFN = 21 , PPC_INS_BCDCFSQ = 22 , PPC_INS_BCDCFZ = 23 , PPC_INS_BCDCPSGN = 24 , PPC_INS_BCDCTN = 25 , PPC_INS_BCDCTSQ = 26 , PPC_INS_BCDCTZ = 27 , PPC_INS_BCDS = 28 , PPC_INS_BCDSETSGN = 29 , PPC_INS_BCDSR = 30 , PPC_INS_BCDTRUNC = 31 , PPC_INS_BCDUS = 32 , PPC_INS_BCDUTRUNC = 33 , PPC_INS_BCL = 34 , PPC_INS_BCLA = 35 , PPC_INS_BCLR = 36 , PPC_INS_BCLRL = 37 , PPC_INS_BCTR = 38 , PPC_INS_BCTRL = 39 , PPC_INS_BDNZ = 40 , PPC_INS_BDNZA = 41 , PPC_INS_BDNZF = 42 , PPC_INS_BDNZFA = 43 , PPC_INS_BDNZFL = 44 , PPC_INS_BDNZFLA = 45 , PPC_INS_BDNZFLR = 46 , PPC_INS_BDNZFLRL = 47 , PPC_INS_BDNZL = 48 , PPC_INS_BDNZLA = 49 , PPC_INS_BDNZLR = 50 , PPC_INS_BDNZLRL = 51 , PPC_INS_BDNZT = 52 , PPC_INS_BDNZTA = 53 , PPC_INS_BDNZTL = 54 , PPC_INS_BDNZTLA = 55 , PPC_INS_BDNZTLR = 56 , PPC_INS_BDNZTLRL = 57 , PPC_INS_BDZ = 58 , PPC_INS_BDZA = 59 , PPC_INS_BDZF = 60 , PPC_INS_BDZFA = 61 , PPC_INS_BDZFL = 62 , PPC_INS_BDZFLA = 63 , PPC_INS_BDZFLR = 64 , PPC_INS_BDZFLRL = 65 , PPC_INS_BDZL = 66 , PPC_INS_BDZLA = 67 , PPC_INS_BDZLR = 68 , PPC_INS_BDZLRL = 69 , PPC_INS_BDZT = 70 , PPC_INS_BDZTA = 71 , PPC_INS_BDZTL = 72 , PPC_INS_BDZTLA = 73 , PPC_INS_BDZTLR = 74 , PPC_INS_BDZTLRL = 75 , PPC_INS_BEQ = 76 , PPC_INS_BEQA = 77 , PPC_INS_BEQCTR = 78 , PPC_INS_BEQCTRL = 79 , PPC_INS_BEQL = 80 , PPC_INS_BEQLA = 81 , PPC_INS_BEQLR = 82 , PPC_INS_BEQLRL = 83 , PPC_INS_BF = 84 , PPC_INS_BFA = 85 , PPC_INS_BFCTR = 86 , PPC_INS_BFCTRL = 87 , PPC_INS_BFL = 88 , PPC_INS_BFLA = 89 , PPC_INS_BFLR = 90 , PPC_INS_BFLRL = 91 , PPC_INS_BGE = 92 , PPC_INS_BGEA = 93 , PPC_INS_BGECTR = 94 , PPC_INS_BGECTRL = 95 , PPC_INS_BGEL = 96 , PPC_INS_BGELA = 97 , PPC_INS_BGELR = 98 , PPC_INS_BGELRL = 99 , PPC_INS_BGT = 100 , PPC_INS_BGTA = 101 , PPC_INS_BGTCTR = 102 , PPC_INS_BGTCTRL = 103 , PPC_INS_BGTL = 104 , PPC_INS_BGTLA = 105 , PPC_INS_BGTLR = 106 , PPC_INS_BGTLRL = 107 , PPC_INS_BL = 108 , PPC_INS_BLA = 109 , PPC_INS_BLE = 110 , PPC_INS_BLEA = 111 , PPC_INS_BLECTR = 112 , PPC_INS_BLECTRL = 113 , PPC_INS_BLEL = 114 , PPC_INS_BLELA = 115 , PPC_INS_BLELR = 116 , PPC_INS_BLELRL = 117 , PPC_INS_BLR = 118 , PPC_INS_BLRL = 119 , PPC_INS_BLT = 120 , PPC_INS_BLTA = 121 , PPC_INS_BLTCTR = 122 , PPC_INS_BLTCTRL = 123 , PPC_INS_BLTL = 124 , PPC_INS_BLTLA = 125 , PPC_INS_BLTLR = 126 , PPC_INS_BLTLRL = 127 , PPC_INS_BNE = 128 , PPC_INS_BNEA = 129 , PPC_INS_BNECTR = 130 , PPC_INS_BNECTRL = 131 , PPC_INS_BNEL = 132 , PPC_INS_BNELA = 133 , PPC_INS_BNELR = 134 , PPC_INS_BNELRL = 135 , PPC_INS_BNG = 136 , PPC_INS_BNGA = 137 , PPC_INS_BNGCTR = 138 , PPC_INS_BNGCTRL = 139 , PPC_INS_BNGL = 140 , PPC_INS_BNGLA = 141 , PPC_INS_BNGLR = 142 , PPC_INS_BNGLRL = 143 , PPC_INS_BNL = 144 , PPC_INS_BNLA = 145 , PPC_INS_BNLCTR = 146 , PPC_INS_BNLCTRL = 147 , PPC_INS_BNLL = 148 , PPC_INS_BNLLA = 149 , PPC_INS_BNLLR = 150 , PPC_INS_BNLLRL = 151 , PPC_INS_BNS = 152 , PPC_INS_BNSA = 153 , PPC_INS_BNSCTR = 154 , PPC_INS_BNSCTRL = 155 , PPC_INS_BNSL = 156 , PPC_INS_BNSLA = 157 , PPC_INS_BNSLR = 158 , PPC_INS_BNSLRL = 159 , PPC_INS_BNU = 160 , PPC_INS_BNUA = 161 , PPC_INS_BNUCTR = 162 , PPC_INS_BNUCTRL = 163 , PPC_INS_BNUL = 164 , PPC_INS_BNULA = 165 , PPC_INS_BNULR = 166 , PPC_INS_BNULRL = 167 , PPC_INS_BPERMD = 168 , PPC_INS_BRINC = 169 , PPC_INS_BSO = 170 , PPC_INS_BSOA = 171 , PPC_INS_BSOCTR = 172 , PPC_INS_BSOCTRL = 173 , PPC_INS_BSOL = 174 , PPC_INS_BSOLA = 175 , PPC_INS_BSOLR = 176 , PPC_INS_BSOLRL = 177 , PPC_INS_BT = 178 , PPC_INS_BTA = 179 , PPC_INS_BTCTR = 180 , PPC_INS_BTCTRL = 181 , PPC_INS_BTL = 182 , PPC_INS_BTLA = 183 , PPC_INS_BTLR = 184 , PPC_INS_BTLRL = 185 , PPC_INS_BUN = 186 , PPC_INS_BUNA = 187 , PPC_INS_BUNCTR = 188 , PPC_INS_BUNCTRL = 189 , PPC_INS_BUNL = 190 , PPC_INS_BUNLA = 191 , PPC_INS_BUNLR = 192 , PPC_INS_BUNLRL = 193 , PPC_INS_CLRBHRB = 194 , PPC_INS_CLRLDI = 195 , PPC_INS_CLRLSLDI = 196 , PPC_INS_CLRLSLWI = 197 , PPC_INS_CLRLWI = 198 , PPC_INS_CLRRDI = 199 , PPC_INS_CLRRWI = 200 , PPC_INS_CMP = 201 , PPC_INS_CMPB = 202 , PPC_INS_CMPD = 203 , PPC_INS_CMPDI = 204 , PPC_INS_CMPEQB = 205 , PPC_INS_CMPI = 206 , PPC_INS_CMPL = 207 , PPC_INS_CMPLD = 208 , PPC_INS_CMPLDI = 209 , PPC_INS_CMPLI = 210 , PPC_INS_CMPLW = 211 , PPC_INS_CMPLWI = 212 , PPC_INS_CMPRB = 213 , PPC_INS_CMPW = 214 , PPC_INS_CMPWI = 215 , PPC_INS_CNTLZD = 216 , PPC_INS_CNTLZW = 217 , PPC_INS_CNTTZD = 218 , PPC_INS_CNTTZW = 219 , PPC_INS_COPY = 220 , PPC_INS_COPY_FIRST = 221 , PPC_INS_CP_ABORT = 222 , PPC_INS_CRAND = 223 , PPC_INS_CRANDC = 224 , PPC_INS_CRCLR = 225 , PPC_INS_CREQV = 226 , PPC_INS_CRMOVE = 227 , PPC_INS_CRNAND = 228 , PPC_INS_CRNOR = 229 , PPC_INS_CRNOT = 230 , PPC_INS_CROR = 231 , PPC_INS_CRORC = 232 , PPC_INS_CRSET = 233 , PPC_INS_CRXOR = 234 , PPC_INS_DARN = 235 , PPC_INS_DCBA = 236 , PPC_INS_DCBF = 237 , PPC_INS_DCBFEP = 238 , PPC_INS_DCBFL = 239 , PPC_INS_DCBFLP = 240 , PPC_INS_DCBI = 241 , PPC_INS_DCBST = 242 , PPC_INS_DCBSTEP = 243 , PPC_INS_DCBT = 244 , PPC_INS_DCBTCT = 245 , PPC_INS_DCBTDS = 246 , PPC_INS_DCBTEP = 247 , PPC_INS_DCBTST = 248 , PPC_INS_DCBTSTCT = 249 , PPC_INS_DCBTSTDS = 250 , PPC_INS_DCBTSTEP = 251 , PPC_INS_DCBTSTT = 252 , PPC_INS_DCBTT = 253 , PPC_INS_DCBZ = 254 , PPC_INS_DCBZEP = 255 , PPC_INS_DCBZL = 256 , PPC_INS_DCBZLEP = 257 , PPC_INS_DCCCI = 258 , PPC_INS_DCI = 259 , PPC_INS_DIVD = 260 , PPC_INS_DIVDE = 261 , PPC_INS_DIVDEU = 262 , PPC_INS_DIVDU = 263 , PPC_INS_DIVW = 264 , PPC_INS_DIVWE = 265 , PPC_INS_DIVWEU = 266 , PPC_INS_DIVWU = 267 , PPC_INS_DSS = 268 , PPC_INS_DSSALL = 269 , PPC_INS_DST = 270 , PPC_INS_DSTST = 271 , PPC_INS_DSTSTT = 272 , PPC_INS_DSTT = 273 , PPC_INS_EFDABS = 274 , PPC_INS_EFDADD = 275 , PPC_INS_EFDCFS = 276 , PPC_INS_EFDCFSF = 277 , PPC_INS_EFDCFSI = 278 , PPC_INS_EFDCFSID = 279 , PPC_INS_EFDCFUF = 280 , PPC_INS_EFDCFUI = 281 , PPC_INS_EFDCFUID = 282 , PPC_INS_EFDCMPEQ = 283 , PPC_INS_EFDCMPGT = 284 , PPC_INS_EFDCMPLT = 285 , PPC_INS_EFDCTSF = 286 , PPC_INS_EFDCTSI = 287 , PPC_INS_EFDCTSIDZ = 288 , PPC_INS_EFDCTSIZ = 289 , PPC_INS_EFDCTUF = 290 , PPC_INS_EFDCTUI = 291 , PPC_INS_EFDCTUIDZ = 292 , PPC_INS_EFDCTUIZ = 293 , PPC_INS_EFDDIV = 294 , PPC_INS_EFDMUL = 295 , PPC_INS_EFDNABS = 296 , PPC_INS_EFDNEG = 297 , PPC_INS_EFDSUB = 298 , PPC_INS_EFDTSTEQ = 299 , PPC_INS_EFDTSTGT = 300 , PPC_INS_EFDTSTLT = 301 , PPC_INS_EFSABS = 302 , PPC_INS_EFSADD = 303 , PPC_INS_EFSCFD = 304 , PPC_INS_EFSCFSF = 305 , PPC_INS_EFSCFSI = 306 , PPC_INS_EFSCFUF = 307 , PPC_INS_EFSCFUI = 308 , PPC_INS_EFSCMPEQ = 309 , PPC_INS_EFSCMPGT = 310 , PPC_INS_EFSCMPLT = 311 , PPC_INS_EFSCTSF = 312 , PPC_INS_EFSCTSI = 313 , PPC_INS_EFSCTSIZ = 314 , PPC_INS_EFSCTUF = 315 , PPC_INS_EFSCTUI = 316 , PPC_INS_EFSCTUIZ = 317 , PPC_INS_EFSDIV = 318 , PPC_INS_EFSMUL = 319 , PPC_INS_EFSNABS = 320 , PPC_INS_EFSNEG = 321 , PPC_INS_EFSSUB = 322 , PPC_INS_EFSTSTEQ = 323 , PPC_INS_EFSTSTGT = 324 , PPC_INS_EFSTSTLT = 325 , PPC_INS_EIEIO = 326 , PPC_INS_EQV = 327 , PPC_INS_EVABS = 328 , PPC_INS_EVADDIW = 329 , PPC_INS_EVADDSMIAAW = 330 , PPC_INS_EVADDSSIAAW = 331 , PPC_INS_EVADDUMIAAW = 332 , PPC_INS_EVADDUSIAAW = 333 , PPC_INS_EVADDW = 334 , PPC_INS_EVAND = 335 , PPC_INS_EVANDC = 336 , PPC_INS_EVCMPEQ = 337 , PPC_INS_EVCMPGTS = 338 , PPC_INS_EVCMPGTU = 339 , PPC_INS_EVCMPLTS = 340 , PPC_INS_EVCMPLTU = 341 , PPC_INS_EVCNTLSW = 342 , PPC_INS_EVCNTLZW = 343 , PPC_INS_EVDIVWS = 344 , PPC_INS_EVDIVWU = 345 , PPC_INS_EVEQV = 346 , PPC_INS_EVEXTSB = 347 , PPC_INS_EVEXTSH = 348 , PPC_INS_EVFSABS = 349 , PPC_INS_EVFSADD = 350 , PPC_INS_EVFSCFSF = 351 , PPC_INS_EVFSCFSI = 352 , PPC_INS_EVFSCFUF = 353 , PPC_INS_EVFSCFUI = 354 , PPC_INS_EVFSCMPEQ = 355 , PPC_INS_EVFSCMPGT = 356 , PPC_INS_EVFSCMPLT = 357 , PPC_INS_EVFSCTSF = 358 , PPC_INS_EVFSCTSI = 359 , PPC_INS_EVFSCTSIZ = 360 , PPC_INS_EVFSCTUI = 361 , PPC_INS_EVFSDIV = 362 , PPC_INS_EVFSMUL = 363 , PPC_INS_EVFSNABS = 364 , PPC_INS_EVFSNEG = 365 , PPC_INS_EVFSSUB = 366 , PPC_INS_EVFSTSTEQ = 367 , PPC_INS_EVFSTSTGT = 368 , PPC_INS_EVFSTSTLT = 369 , PPC_INS_EVLDD = 370 , PPC_INS_EVLDDX = 371 , PPC_INS_EVLDH = 372 , PPC_INS_EVLDHX = 373 , PPC_INS_EVLDW = 374 , PPC_INS_EVLDWX = 375 , PPC_INS_EVLHHESPLAT = 376 , PPC_INS_EVLHHESPLATX = 377 , PPC_INS_EVLHHOSSPLAT = 378 , PPC_INS_EVLHHOSSPLATX = 379 , PPC_INS_EVLHHOUSPLAT = 380 , PPC_INS_EVLHHOUSPLATX = 381 , PPC_INS_EVLWHE = 382 , PPC_INS_EVLWHEX = 383 , PPC_INS_EVLWHOS = 384 , PPC_INS_EVLWHOSX = 385 , PPC_INS_EVLWHOU = 386 , PPC_INS_EVLWHOUX = 387 , PPC_INS_EVLWHSPLAT = 388 , PPC_INS_EVLWHSPLATX = 389 , PPC_INS_EVLWWSPLAT = 390 , PPC_INS_EVLWWSPLATX = 391 , PPC_INS_EVMERGEHI = 392 , PPC_INS_EVMERGEHILO = 393 , PPC_INS_EVMERGELO = 394 , PPC_INS_EVMERGELOHI = 395 , PPC_INS_EVMHEGSMFAA = 396 , PPC_INS_EVMHEGSMFAN = 397 , PPC_INS_EVMHEGSMIAA = 398 , PPC_INS_EVMHEGSMIAN = 399 , PPC_INS_EVMHEGUMIAA = 400 , PPC_INS_EVMHEGUMIAN = 401 , PPC_INS_EVMHESMF = 402 , PPC_INS_EVMHESMFA = 403 , PPC_INS_EVMHESMFAAW = 404 , PPC_INS_EVMHESMFANW = 405 , PPC_INS_EVMHESMI = 406 , PPC_INS_EVMHESMIA = 407 , PPC_INS_EVMHESMIAAW = 408 , PPC_INS_EVMHESMIANW = 409 , PPC_INS_EVMHESSF = 410 , PPC_INS_EVMHESSFA = 411 , PPC_INS_EVMHESSFAAW = 412 , PPC_INS_EVMHESSFANW = 413 , PPC_INS_EVMHESSIAAW = 414 , PPC_INS_EVMHESSIANW = 415 , PPC_INS_EVMHEUMI = 416 , PPC_INS_EVMHEUMIA = 417 , PPC_INS_EVMHEUMIAAW = 418 , PPC_INS_EVMHEUMIANW = 419 , PPC_INS_EVMHEUSIAAW = 420 , PPC_INS_EVMHEUSIANW = 421 , PPC_INS_EVMHOGSMFAA = 422 , PPC_INS_EVMHOGSMFAN = 423 , PPC_INS_EVMHOGSMIAA = 424 , PPC_INS_EVMHOGSMIAN = 425 , PPC_INS_EVMHOGUMIAA = 426 , PPC_INS_EVMHOGUMIAN = 427 , PPC_INS_EVMHOSMF = 428 , PPC_INS_EVMHOSMFA = 429 , PPC_INS_EVMHOSMFAAW = 430 , PPC_INS_EVMHOSMFANW = 431 , PPC_INS_EVMHOSMI = 432 , PPC_INS_EVMHOSMIA = 433 , PPC_INS_EVMHOSMIAAW = 434 , PPC_INS_EVMHOSMIANW = 435 , PPC_INS_EVMHOSSF = 436 , PPC_INS_EVMHOSSFA = 437 , PPC_INS_EVMHOSSFAAW = 438 , PPC_INS_EVMHOSSFANW = 439 , PPC_INS_EVMHOSSIAAW = 440 , PPC_INS_EVMHOSSIANW = 441 , PPC_INS_EVMHOUMI = 442 , PPC_INS_EVMHOUMIA = 443 , PPC_INS_EVMHOUMIAAW = 444 , PPC_INS_EVMHOUMIANW = 445 , PPC_INS_EVMHOUSIAAW = 446 , PPC_INS_EVMHOUSIANW = 447 , PPC_INS_EVMRA = 448 , PPC_INS_EVMWHSMF = 449 , PPC_INS_EVMWHSMFA = 450 , PPC_INS_EVMWHSMI = 451 , PPC_INS_EVMWHSMIA = 452 , PPC_INS_EVMWHSSF = 453 , PPC_INS_EVMWHSSFA = 454 , PPC_INS_EVMWHUMI = 455 , PPC_INS_EVMWHUMIA = 456 , PPC_INS_EVMWLSMIAAW = 457 , PPC_INS_EVMWLSMIANW = 458 , PPC_INS_EVMWLSSIAAW = 459 , PPC_INS_EVMWLSSIANW = 460 , PPC_INS_EVMWLUMI = 461 , PPC_INS_EVMWLUMIA = 462 , PPC_INS_EVMWLUMIAAW = 463 , PPC_INS_EVMWLUMIANW = 464 , PPC_INS_EVMWLUSIAAW = 465 , PPC_INS_EVMWLUSIANW = 466 , PPC_INS_EVMWSMF = 467 , PPC_INS_EVMWSMFA = 468 , PPC_INS_EVMWSMFAA = 469 , PPC_INS_EVMWSMFAN = 470 , PPC_INS_EVMWSMI = 471 , PPC_INS_EVMWSMIA = 472 , PPC_INS_EVMWSMIAA = 473 , PPC_INS_EVMWSMIAN = 474 , PPC_INS_EVMWSSF = 475 , PPC_INS_EVMWSSFA = 476 , PPC_INS_EVMWSSFAA = 477 , PPC_INS_EVMWSSFAN = 478 , PPC_INS_EVMWUMI = 479 , PPC_INS_EVMWUMIA = 480 , PPC_INS_EVMWUMIAA = 481 , PPC_INS_EVMWUMIAN = 482 , PPC_INS_EVNAND = 483 , PPC_INS_EVNEG = 484 , PPC_INS_EVNOR = 485 , PPC_INS_EVOR = 486 , PPC_INS_EVORC = 487 , PPC_INS_EVRLW = 488 , PPC_INS_EVRLWI = 489 , PPC_INS_EVRNDW = 490 , PPC_INS_EVSEL = 491 , PPC_INS_EVSLW = 492 , PPC_INS_EVSLWI = 493 , PPC_INS_EVSPLATFI = 494 , PPC_INS_EVSPLATI = 495 , PPC_INS_EVSRWIS = 496 , PPC_INS_EVSRWIU = 497 , PPC_INS_EVSRWS = 498 , PPC_INS_EVSRWU = 499 , PPC_INS_EVSTDD = 500 , PPC_INS_EVSTDDX = 501 , PPC_INS_EVSTDH = 502 , PPC_INS_EVSTDHX = 503 , PPC_INS_EVSTDW = 504 , PPC_INS_EVSTDWX = 505 , PPC_INS_EVSTWHE = 506 , PPC_INS_EVSTWHEX = 507 , PPC_INS_EVSTWHO = 508 , PPC_INS_EVSTWHOX = 509 , PPC_INS_EVSTWWE = 510 , PPC_INS_EVSTWWEX = 511 , PPC_INS_EVSTWWO = 512 , PPC_INS_EVSTWWOX = 513 , PPC_INS_EVSUBFSMIAAW = 514 , PPC_INS_EVSUBFSSIAAW = 515 , PPC_INS_EVSUBFUMIAAW = 516 , PPC_INS_EVSUBFUSIAAW = 517 , PPC_INS_EVSUBFW = 518 , PPC_INS_EVSUBIFW = 519 , PPC_INS_EVXOR = 520 , PPC_INS_EXTLDI = 521 , PPC_INS_EXTLWI = 522 , PPC_INS_EXTRDI = 523 , PPC_INS_EXTRWI = 524 , PPC_INS_EXTSB = 525 , PPC_INS_EXTSH = 526 , PPC_INS_EXTSW = 527 , PPC_INS_EXTSWSLI = 528 , PPC_INS_FABS = 529 , PPC_INS_FADD = 530 , PPC_INS_FADDS = 531 , PPC_INS_FCFID = 532 , PPC_INS_FCFIDS = 533 , PPC_INS_FCFIDU = 534 , PPC_INS_FCFIDUS = 535 , PPC_INS_FCMPU = 536 , PPC_INS_FCPSGN = 537 , PPC_INS_FCTID = 538 , PPC_INS_FCTIDU = 539 , PPC_INS_FCTIDUZ = 540 , PPC_INS_FCTIDZ = 541 , PPC_INS_FCTIW = 542 , PPC_INS_FCTIWU = 543 , PPC_INS_FCTIWUZ = 544 , PPC_INS_FCTIWZ = 545 , PPC_INS_FDIV = 546 , PPC_INS_FDIVS = 547 , PPC_INS_FMADD = 548 , PPC_INS_FMADDS = 549 , PPC_INS_FMR = 550 , PPC_INS_FMSUB = 551 , PPC_INS_FMSUBS = 552 , PPC_INS_FMUL = 553 , PPC_INS_FMULS = 554 , PPC_INS_FNABS = 555 , PPC_INS_FNEG = 556 , PPC_INS_FNMADD = 557 , PPC_INS_FNMADDS = 558 , PPC_INS_FNMSUB = 559 , PPC_INS_FNMSUBS = 560 , PPC_INS_FRE = 561 , PPC_INS_FRES = 562 , PPC_INS_FRIM = 563 , PPC_INS_FRIN = 564 , PPC_INS_FRIP = 565 , PPC_INS_FRIZ = 566 , PPC_INS_FRSP = 567 , PPC_INS_FRSQRTE = 568 , PPC_INS_FRSQRTES = 569 , PPC_INS_FSEL = 570 , PPC_INS_FSQRT = 571 , PPC_INS_FSQRTS = 572 , PPC_INS_FSUB = 573 , PPC_INS_FSUBS = 574 , PPC_INS_FTDIV = 575 , PPC_INS_FTSQRT = 576 , PPC_INS_HRFID = 577 , PPC_INS_ICBI = 578 , PPC_INS_ICBIEP = 579 , PPC_INS_ICBLC = 580 , PPC_INS_ICBLQ = 581 , PPC_INS_ICBT = 582 , PPC_INS_ICBTLS = 583 , PPC_INS_ICCCI = 584 , PPC_INS_ICI = 585 , PPC_INS_INSLWI = 586 , PPC_INS_INSRDI = 587 , PPC_INS_INSRWI = 588 , PPC_INS_ISEL = 589 , PPC_INS_ISYNC = 590 , PPC_INS_LA = 591 , PPC_INS_LBARX = 592 , PPC_INS_LBEPX = 593 , PPC_INS_LBZ = 594 , PPC_INS_LBZCIX = 595 , PPC_INS_LBZU = 596 , PPC_INS_LBZUX = 597 , PPC_INS_LBZX = 598 , PPC_INS_LD = 599 , PPC_INS_LDARX = 600 , PPC_INS_LDAT = 601 , PPC_INS_LDBRX = 602 , PPC_INS_LDCIX = 603 , PPC_INS_LDMX = 604 , PPC_INS_LDU = 605 , PPC_INS_LDUX = 606 , PPC_INS_LDX = 607 , PPC_INS_LFD = 608 , PPC_INS_LFDEPX = 609 , PPC_INS_LFDU = 610 , PPC_INS_LFDUX = 611 , PPC_INS_LFDX = 612 , PPC_INS_LFIWAX = 613 , PPC_INS_LFIWZX = 614 , PPC_INS_LFS = 615 , PPC_INS_LFSU = 616 , PPC_INS_LFSUX = 617 , PPC_INS_LFSX = 618 , PPC_INS_LHA = 619 , PPC_INS_LHARX = 620 , PPC_INS_LHAU = 621 , PPC_INS_LHAUX = 622 , PPC_INS_LHAX = 623 , PPC_INS_LHBRX = 624 , PPC_INS_LHEPX = 625 , PPC_INS_LHZ = 626 , PPC_INS_LHZCIX = 627 , PPC_INS_LHZU = 628 , PPC_INS_LHZUX = 629 , PPC_INS_LHZX = 630 , PPC_INS_LI = 631 , PPC_INS_LIS = 632 , PPC_INS_LMW = 633 , PPC_INS_LNIA = 634 , PPC_INS_LSWI = 635 , PPC_INS_LVEBX = 636 , PPC_INS_LVEHX = 637 , PPC_INS_LVEWX = 638 , PPC_INS_LVSL = 639 , PPC_INS_LVSR = 640 , PPC_INS_LVX = 641 , PPC_INS_LVXL = 642 , PPC_INS_LWA = 643 , PPC_INS_LWARX = 644 , PPC_INS_LWAT = 645 , PPC_INS_LWAUX = 646 , PPC_INS_LWAX = 647 , PPC_INS_LWBRX = 648 , PPC_INS_LWEPX = 649 , PPC_INS_LWSYNC = 650 , PPC_INS_LWZ = 651 , PPC_INS_LWZCIX = 652 , PPC_INS_LWZU = 653 , PPC_INS_LWZUX = 654 , PPC_INS_LWZX = 655 , PPC_INS_LXSD = 656 , PPC_INS_LXSDX = 657 , PPC_INS_LXSIBZX = 658 , PPC_INS_LXSIHZX = 659 , PPC_INS_LXSIWAX = 660 , PPC_INS_LXSIWZX = 661 , PPC_INS_LXSSP = 662 , PPC_INS_LXSSPX = 663 , PPC_INS_LXV = 664 , PPC_INS_LXVB16X = 665 , PPC_INS_LXVD2X = 666 , PPC_INS_LXVDSX = 667 , PPC_INS_LXVH8X = 668 , PPC_INS_LXVL = 669 , PPC_INS_LXVLL = 670 , PPC_INS_LXVW4X = 671 , PPC_INS_LXVWSX = 672 , PPC_INS_LXVX = 673 , PPC_INS_MADDHD = 674 , PPC_INS_MADDHDU = 675 , PPC_INS_MADDLD = 676 , PPC_INS_MBAR = 677 , PPC_INS_MCRF = 678 , PPC_INS_MCRFS = 679 , PPC_INS_MCRXRX = 680 , PPC_INS_MFAMR = 681 , PPC_INS_MFASR = 682 , PPC_INS_MFBHRBE = 683 , PPC_INS_MFBR0 = 684 , PPC_INS_MFBR1 = 685 , PPC_INS_MFBR2 = 686 , PPC_INS_MFBR3 = 687 , PPC_INS_MFBR4 = 688 , PPC_INS_MFBR5 = 689 , PPC_INS_MFBR6 = 690 , PPC_INS_MFBR7 = 691 , PPC_INS_MFCFAR = 692 , PPC_INS_MFCR = 693 , PPC_INS_MFCTR = 694 , PPC_INS_MFDAR = 695 , PPC_INS_MFDBATL = 696 , PPC_INS_MFDBATU = 697 , PPC_INS_MFDCCR = 698 , PPC_INS_MFDCR = 699 , PPC_INS_MFDEAR = 700 , PPC_INS_MFDEC = 701 , PPC_INS_MFDSCR = 702 , PPC_INS_MFDSISR = 703 , PPC_INS_MFESR = 704 , PPC_INS_MFFPRD = 705 , PPC_INS_MFFS = 706 , PPC_INS_MFFSCDRN = 707 , PPC_INS_MFFSCDRNI = 708 , PPC_INS_MFFSCE = 709 , PPC_INS_MFFSCRN = 710 , PPC_INS_MFFSCRNI = 711 , PPC_INS_MFFSL = 712 , PPC_INS_MFIBATL = 713 , PPC_INS_MFIBATU = 714 , PPC_INS_MFICCR = 715 , PPC_INS_MFLR = 716 , PPC_INS_MFMSR = 717 , PPC_INS_MFOCRF = 718 , PPC_INS_MFPID = 719 , PPC_INS_MFPMR = 720 , PPC_INS_MFPVR = 721 , PPC_INS_MFRTCL = 722 , PPC_INS_MFRTCU = 723 , PPC_INS_MFSDR1 = 724 , PPC_INS_MFSPEFSCR = 725 , PPC_INS_MFSPR = 726 , PPC_INS_MFSPRG = 727 , PPC_INS_MFSPRG0 = 728 , PPC_INS_MFSPRG1 = 729 , PPC_INS_MFSPRG2 = 730 , PPC_INS_MFSPRG3 = 731 , PPC_INS_MFSPRG4 = 732 , PPC_INS_MFSPRG5 = 733 , PPC_INS_MFSPRG6 = 734 , PPC_INS_MFSPRG7 = 735 , PPC_INS_MFSR = 736 , PPC_INS_MFSRIN = 737 , PPC_INS_MFSRR0 = 738 , PPC_INS_MFSRR1 = 739 , PPC_INS_MFSRR2 = 740 , PPC_INS_MFSRR3 = 741 , PPC_INS_MFTB = 742 , PPC_INS_MFTBHI = 743 , PPC_INS_MFTBL = 744 , PPC_INS_MFTBLO = 745 , PPC_INS_MFTBU = 746 , PPC_INS_MFTCR = 747 , PPC_INS_MFVRD = 748 , PPC_INS_MFVRSAVE = 749 , PPC_INS_MFVSCR = 750 , PPC_INS_MFVSRD = 751 , PPC_INS_MFVSRLD = 752 , PPC_INS_MFVSRWZ = 753 , PPC_INS_MFXER = 754 , PPC_INS_MODSD = 755 , PPC_INS_MODSW = 756 , PPC_INS_MODUD = 757 , PPC_INS_MODUW = 758 , PPC_INS_MR = 759 , PPC_INS_MSGSYNC = 760 , PPC_INS_MSYNC = 761 , PPC_INS_MTAMR = 762 , PPC_INS_MTASR = 763 , PPC_INS_MTBR0 = 764 , PPC_INS_MTBR1 = 765 , PPC_INS_MTBR2 = 766 , PPC_INS_MTBR3 = 767 , PPC_INS_MTBR4 = 768 , PPC_INS_MTBR5 = 769 , PPC_INS_MTBR6 = 770 , PPC_INS_MTBR7 = 771 , PPC_INS_MTCFAR = 772 , PPC_INS_MTCR = 773 , PPC_INS_MTCRF = 774 , PPC_INS_MTCTR = 775 , PPC_INS_MTDAR = 776 , PPC_INS_MTDBATL = 777 , PPC_INS_MTDBATU = 778 , PPC_INS_MTDCCR = 779 , PPC_INS_MTDCR = 780 , PPC_INS_MTDEAR = 781 , PPC_INS_MTDEC = 782 , PPC_INS_MTDSCR = 783 , PPC_INS_MTDSISR = 784 , PPC_INS_MTESR = 785 , PPC_INS_MTFSB0 = 786 , PPC_INS_MTFSB1 = 787 , PPC_INS_MTFSF = 788 , PPC_INS_MTFSFI = 789 , PPC_INS_MTIBATL = 790 , PPC_INS_MTIBATU = 791 , PPC_INS_MTICCR = 792 , PPC_INS_MTLR = 793 , PPC_INS_MTMSR = 794 , PPC_INS_MTMSRD = 795 , PPC_INS_MTOCRF = 796 , PPC_INS_MTPID = 797 , PPC_INS_MTPMR = 798 , PPC_INS_MTSDR1 = 799 , PPC_INS_MTSPEFSCR = 800 , PPC_INS_MTSPR = 801 , PPC_INS_MTSPRG = 802 , PPC_INS_MTSPRG0 = 803 , PPC_INS_MTSPRG1 = 804 , PPC_INS_MTSPRG2 = 805 , PPC_INS_MTSPRG3 = 806 , PPC_INS_MTSPRG4 = 807 , PPC_INS_MTSPRG5 = 808 , PPC_INS_MTSPRG6 = 809 , PPC_INS_MTSPRG7 = 810 , PPC_INS_MTSR = 811 , PPC_INS_MTSRIN = 812 , PPC_INS_MTSRR0 = 813 , PPC_INS_MTSRR1 = 814 , PPC_INS_MTSRR2 = 815 , PPC_INS_MTSRR3 = 816 , PPC_INS_MTTBHI = 817 , PPC_INS_MTTBL = 818 , PPC_INS_MTTBLO = 819 , PPC_INS_MTTBU = 820 , PPC_INS_MTTCR = 821 , PPC_INS_MTVRSAVE = 822 , PPC_INS_MTVSCR = 823 , PPC_INS_MTVSRD = 824 , PPC_INS_MTVSRDD = 825 , PPC_INS_MTVSRWA = 826 , PPC_INS_MTVSRWS = 827 , PPC_INS_MTVSRWZ = 828 , PPC_INS_MTXER = 829 , PPC_INS_MULHD = 830 , PPC_INS_MULHDU = 831 , PPC_INS_MULHW = 832 , PPC_INS_MULHWU = 833 , PPC_INS_MULLD = 834 , PPC_INS_MULLI = 835 , PPC_INS_MULLW = 836 , PPC_INS_NAND = 837 , PPC_INS_NAP = 838 , PPC_INS_NEG = 839 , PPC_INS_NOP = 840 , PPC_INS_NOR = 841 , PPC_INS_NOT = 842 , PPC_INS_OR = 843 , PPC_INS_ORC = 844 , PPC_INS_ORI = 845 , PPC_INS_ORIS = 846 , PPC_INS_PASTE = 847 , PPC_INS_PASTE_LAST = 848 , PPC_INS_POPCNTB = 849 , PPC_INS_POPCNTD = 850 , PPC_INS_POPCNTW = 851 , PPC_INS_PTESYNC = 852 , PPC_INS_QVALIGNI = 853 , PPC_INS_QVESPLATI = 854 , PPC_INS_QVFABS = 855 , PPC_INS_QVFADD = 856 , PPC_INS_QVFADDS = 857 , PPC_INS_QVFAND = 858 , PPC_INS_QVFANDC = 859 , PPC_INS_QVFCFID = 860 , PPC_INS_QVFCFIDS = 861 , PPC_INS_QVFCFIDU = 862 , PPC_INS_QVFCFIDUS = 863 , PPC_INS_QVFCLR = 864 , PPC_INS_QVFCMPEQ = 865 , PPC_INS_QVFCMPGT = 866 , PPC_INS_QVFCMPLT = 867 , PPC_INS_QVFCPSGN = 868 , PPC_INS_QVFCTFB = 869 , PPC_INS_QVFCTID = 870 , PPC_INS_QVFCTIDU = 871 , PPC_INS_QVFCTIDUZ = 872 , PPC_INS_QVFCTIDZ = 873 , PPC_INS_QVFCTIW = 874 , PPC_INS_QVFCTIWU = 875 , PPC_INS_QVFCTIWUZ = 876 , PPC_INS_QVFCTIWZ = 877 , PPC_INS_QVFEQU = 878 , PPC_INS_QVFLOGICAL = 879 , PPC_INS_QVFMADD = 880 , PPC_INS_QVFMADDS = 881 , PPC_INS_QVFMR = 882 , PPC_INS_QVFMSUB = 883 , PPC_INS_QVFMSUBS = 884 , PPC_INS_QVFMUL = 885 , PPC_INS_QVFMULS = 886 , PPC_INS_QVFNABS = 887 , PPC_INS_QVFNAND = 888 , PPC_INS_QVFNEG = 889 , PPC_INS_QVFNMADD = 890 , PPC_INS_QVFNMADDS = 891 , PPC_INS_QVFNMSUB = 892 , PPC_INS_QVFNMSUBS = 893 , PPC_INS_QVFNOR = 894 , PPC_INS_QVFNOT = 895 , PPC_INS_QVFOR = 896 , PPC_INS_QVFORC = 897 , PPC_INS_QVFPERM = 898 , PPC_INS_QVFRE = 899 , PPC_INS_QVFRES = 900 , PPC_INS_QVFRIM = 901 , PPC_INS_QVFRIN = 902 , PPC_INS_QVFRIP = 903 , PPC_INS_QVFRIZ = 904 , PPC_INS_QVFRSP = 905 , PPC_INS_QVFRSQRTE = 906 , PPC_INS_QVFRSQRTES = 907 , PPC_INS_QVFSEL = 908 , PPC_INS_QVFSET = 909 , PPC_INS_QVFSUB = 910 , PPC_INS_QVFSUBS = 911 , PPC_INS_QVFTSTNAN = 912 , PPC_INS_QVFXMADD = 913 , PPC_INS_QVFXMADDS = 914 , PPC_INS_QVFXMUL = 915 , PPC_INS_QVFXMULS = 916 , PPC_INS_QVFXOR = 917 , PPC_INS_QVFXXCPNMADD = 918 , PPC_INS_QVFXXCPNMADDS = 919 , PPC_INS_QVFXXMADD = 920 , PPC_INS_QVFXXMADDS = 921 , PPC_INS_QVFXXNPMADD = 922 , PPC_INS_QVFXXNPMADDS = 923 , PPC_INS_QVGPCI = 924 , PPC_INS_QVLFCDUX = 925 , PPC_INS_QVLFCDUXA = 926 , PPC_INS_QVLFCDX = 927 , PPC_INS_QVLFCDXA = 928 , PPC_INS_QVLFCSUX = 929 , PPC_INS_QVLFCSUXA = 930 , PPC_INS_QVLFCSX = 931 , PPC_INS_QVLFCSXA = 932 , PPC_INS_QVLFDUX = 933 , PPC_INS_QVLFDUXA = 934 , PPC_INS_QVLFDX = 935 , PPC_INS_QVLFDXA = 936 , PPC_INS_QVLFIWAX = 937 , PPC_INS_QVLFIWAXA = 938 , PPC_INS_QVLFIWZX = 939 , PPC_INS_QVLFIWZXA = 940 , PPC_INS_QVLFSUX = 941 , PPC_INS_QVLFSUXA = 942 , PPC_INS_QVLFSX = 943 , PPC_INS_QVLFSXA = 944 , PPC_INS_QVLPCLDX = 945 , PPC_INS_QVLPCLSX = 946 , PPC_INS_QVLPCRDX = 947 , PPC_INS_QVLPCRSX = 948 , PPC_INS_QVSTFCDUX = 949 , PPC_INS_QVSTFCDUXA = 950 , PPC_INS_QVSTFCDUXI = 951 , PPC_INS_QVSTFCDUXIA = 952 , PPC_INS_QVSTFCDX = 953 , PPC_INS_QVSTFCDXA = 954 , PPC_INS_QVSTFCDXI = 955 , PPC_INS_QVSTFCDXIA = 956 , PPC_INS_QVSTFCSUX = 957 , PPC_INS_QVSTFCSUXA = 958 , PPC_INS_QVSTFCSUXI = 959 , PPC_INS_QVSTFCSUXIA = 960 , PPC_INS_QVSTFCSX = 961 , PPC_INS_QVSTFCSXA = 962 , PPC_INS_QVSTFCSXI = 963 , PPC_INS_QVSTFCSXIA = 964 , PPC_INS_QVSTFDUX = 965 , PPC_INS_QVSTFDUXA = 966 , PPC_INS_QVSTFDUXI = 967 , PPC_INS_QVSTFDUXIA = 968 , PPC_INS_QVSTFDX = 969 , PPC_INS_QVSTFDXA = 970 , PPC_INS_QVSTFDXI = 971 , PPC_INS_QVSTFDXIA = 972 , PPC_INS_QVSTFIWX = 973 , PPC_INS_QVSTFIWXA = 974 , PPC_INS_QVSTFSUX = 975 , PPC_INS_QVSTFSUXA = 976 , PPC_INS_QVSTFSUXI = 977 , PPC_INS_QVSTFSUXIA = 978 , PPC_INS_QVSTFSX = 979 , PPC_INS_QVSTFSXA = 980 , PPC_INS_QVSTFSXI = 981 , PPC_INS_QVSTFSXIA = 982 , PPC_INS_RFCI = 983 , PPC_INS_RFDI = 984 , PPC_INS_RFEBB = 985 , PPC_INS_RFI = 986 , PPC_INS_RFID = 987 , PPC_INS_RFMCI = 988 , PPC_INS_RLDCL = 989 , PPC_INS_RLDCR = 990 , PPC_INS_RLDIC = 991 , PPC_INS_RLDICL = 992 , PPC_INS_RLDICR = 993 , PPC_INS_RLDIMI = 994 , PPC_INS_RLWIMI = 995 , PPC_INS_RLWINM = 996 , PPC_INS_RLWNM = 997 , PPC_INS_ROTLD = 998 , PPC_INS_ROTLDI = 999 , PPC_INS_ROTLW = 1000 , PPC_INS_ROTLWI = 1001 , PPC_INS_ROTRDI = 1002 , PPC_INS_ROTRWI = 1003 , PPC_INS_SC = 1004 , PPC_INS_SETB = 1005 , PPC_INS_SLBIA = 1006 , PPC_INS_SLBIE = 1007 , PPC_INS_SLBIEG = 1008 , PPC_INS_SLBMFEE = 1009 , PPC_INS_SLBMFEV = 1010 , PPC_INS_SLBMTE = 1011 , PPC_INS_SLBSYNC = 1012 , PPC_INS_SLD = 1013 , PPC_INS_SLDI = 1014 , PPC_INS_SLW = 1015 , PPC_INS_SLWI = 1016 , PPC_INS_SRAD = 1017 , PPC_INS_SRADI = 1018 , PPC_INS_SRAW = 1019 , PPC_INS_SRAWI = 1020 , PPC_INS_SRD = 1021 , PPC_INS_SRDI = 1022 , PPC_INS_SRW = 1023 , PPC_INS_SRWI = 1024 , PPC_INS_STB = 1025 , PPC_INS_STBCIX = 1026 , PPC_INS_STBCX = 1027 , PPC_INS_STBEPX = 1028 , PPC_INS_STBU = 1029 , PPC_INS_STBUX = 1030 , PPC_INS_STBX = 1031 , PPC_INS_STD = 1032 , PPC_INS_STDAT = 1033 , PPC_INS_STDBRX = 1034 , PPC_INS_STDCIX = 1035 , PPC_INS_STDCX = 1036 , PPC_INS_STDU = 1037 , PPC_INS_STDUX = 1038 , PPC_INS_STDX = 1039 , PPC_INS_STFD = 1040 , PPC_INS_STFDEPX = 1041 , PPC_INS_STFDU = 1042 , PPC_INS_STFDUX = 1043 , PPC_INS_STFDX = 1044 , PPC_INS_STFIWX = 1045 , PPC_INS_STFS = 1046 , PPC_INS_STFSU = 1047 , PPC_INS_STFSUX = 1048 , PPC_INS_STFSX = 1049 , PPC_INS_STH = 1050 , PPC_INS_STHBRX = 1051 , PPC_INS_STHCIX = 1052 , PPC_INS_STHCX = 1053 , PPC_INS_STHEPX = 1054 , PPC_INS_STHU = 1055 , PPC_INS_STHUX = 1056 , PPC_INS_STHX = 1057 , PPC_INS_STMW = 1058 , PPC_INS_STOP = 1059 , PPC_INS_STSWI = 1060 , PPC_INS_STVEBX = 1061 , PPC_INS_STVEHX = 1062 , PPC_INS_STVEWX = 1063 , PPC_INS_STVX = 1064 , PPC_INS_STVXL = 1065 , PPC_INS_STW = 1066 , PPC_INS_STWAT = 1067 , PPC_INS_STWBRX = 1068 , PPC_INS_STWCIX = 1069 , PPC_INS_STWCX = 1070 , PPC_INS_STWEPX = 1071 , PPC_INS_STWU = 1072 , PPC_INS_STWUX = 1073 , PPC_INS_STWX = 1074 , PPC_INS_STXSD = 1075 , PPC_INS_STXSDX = 1076 , PPC_INS_STXSIBX = 1077 , PPC_INS_STXSIHX = 1078 , PPC_INS_STXSIWX = 1079 , PPC_INS_STXSSP = 1080 , PPC_INS_STXSSPX = 1081 , PPC_INS_STXV = 1082 , PPC_INS_STXVB16X = 1083 , PPC_INS_STXVD2X = 1084 , PPC_INS_STXVH8X = 1085 , PPC_INS_STXVL = 1086 , PPC_INS_STXVLL = 1087 , PPC_INS_STXVW4X = 1088 , PPC_INS_STXVX = 1089 , PPC_INS_SUB = 1090 , PPC_INS_SUBC = 1091 , PPC_INS_SUBF = 1092 , PPC_INS_SUBFC = 1093 , PPC_INS_SUBFE = 1094 , PPC_INS_SUBFIC = 1095 , PPC_INS_SUBFME = 1096 , PPC_INS_SUBFZE = 1097 , PPC_INS_SUBI = 1098 , PPC_INS_SUBIC = 1099 , PPC_INS_SUBIS = 1100 , PPC_INS_SUBPCIS = 1101 , PPC_INS_SYNC = 1102 , PPC_INS_TABORT = 1103 , PPC_INS_TABORTDC = 1104 , PPC_INS_TABORTDCI = 1105 , PPC_INS_TABORTWC = 1106 , PPC_INS_TABORTWCI = 1107 , PPC_INS_TBEGIN = 1108 , PPC_INS_TCHECK = 1109 , PPC_INS_TD = 1110 , PPC_INS_TDEQ = 1111 , PPC_INS_TDEQI = 1112 , PPC_INS_TDGE = 1113 , PPC_INS_TDGEI = 1114 , PPC_INS_TDGT = 1115 , PPC_INS_TDGTI = 1116 , PPC_INS_TDI = 1117 , PPC_INS_TDLE = 1118 , PPC_INS_TDLEI = 1119 , PPC_INS_TDLGE = 1120 , PPC_INS_TDLGEI = 1121 , PPC_INS_TDLGT = 1122 , PPC_INS_TDLGTI = 1123 , PPC_INS_TDLLE = 1124 , PPC_INS_TDLLEI = 1125 , PPC_INS_TDLLT = 1126 , PPC_INS_TDLLTI = 1127 , PPC_INS_TDLNG = 1128 , PPC_INS_TDLNGI = 1129 , PPC_INS_TDLNL = 1130 , PPC_INS_TDLNLI = 1131 , PPC_INS_TDLT = 1132 , PPC_INS_TDLTI = 1133 , PPC_INS_TDNE = 1134 , PPC_INS_TDNEI = 1135 , PPC_INS_TDNG = 1136 , PPC_INS_TDNGI = 1137 , PPC_INS_TDNL = 1138 , PPC_INS_TDNLI = 1139 , PPC_INS_TDU = 1140 , PPC_INS_TDUI = 1141 , PPC_INS_TEND = 1142 , PPC_INS_TLBIA = 1143 , PPC_INS_TLBIE = 1144 , PPC_INS_TLBIEL = 1145 , PPC_INS_TLBIVAX = 1146 , PPC_INS_TLBLD = 1147 , PPC_INS_TLBLI = 1148 , PPC_INS_TLBRE = 1149 , PPC_INS_TLBREHI = 1150 , PPC_INS_TLBRELO = 1151 , PPC_INS_TLBSX = 1152 , PPC_INS_TLBSYNC = 1153 , PPC_INS_TLBWE = 1154 , PPC_INS_TLBWEHI = 1155 , PPC_INS_TLBWELO = 1156 , PPC_INS_TRAP = 1157 , PPC_INS_TRECHKPT = 1158 , PPC_INS_TRECLAIM = 1159 , PPC_INS_TSR = 1160 , PPC_INS_TW = 1161 , PPC_INS_TWEQ = 1162 , PPC_INS_TWEQI = 1163 , PPC_INS_TWGE = 1164 , PPC_INS_TWGEI = 1165 , PPC_INS_TWGT = 1166 , PPC_INS_TWGTI = 1167 , PPC_INS_TWI = 1168 , PPC_INS_TWLE = 1169 , PPC_INS_TWLEI = 1170 , PPC_INS_TWLGE = 1171 , PPC_INS_TWLGEI = 1172 , PPC_INS_TWLGT = 1173 , PPC_INS_TWLGTI = 1174 , PPC_INS_TWLLE = 1175 , PPC_INS_TWLLEI = 1176 , PPC_INS_TWLLT = 1177 , PPC_INS_TWLLTI = 1178 , PPC_INS_TWLNG = 1179 , PPC_INS_TWLNGI = 1180 , PPC_INS_TWLNL = 1181 , PPC_INS_TWLNLI = 1182 , PPC_INS_TWLT = 1183 , PPC_INS_TWLTI = 1184 , PPC_INS_TWNE = 1185 , PPC_INS_TWNEI = 1186 , PPC_INS_TWNG = 1187 , PPC_INS_TWNGI = 1188 , PPC_INS_TWNL = 1189 , PPC_INS_TWNLI = 1190 , PPC_INS_TWU = 1191 , PPC_INS_TWUI = 1192 , PPC_INS_VABSDUB = 1193 , PPC_INS_VABSDUH = 1194 , PPC_INS_VABSDUW = 1195 , PPC_INS_VADDCUQ = 1196 , PPC_INS_VADDCUW = 1197 , PPC_INS_VADDECUQ = 1198 , PPC_INS_VADDEUQM = 1199 , PPC_INS_VADDFP = 1200 , PPC_INS_VADDSBS = 1201 , PPC_INS_VADDSHS = 1202 , PPC_INS_VADDSWS = 1203 , PPC_INS_VADDUBM = 1204 , PPC_INS_VADDUBS = 1205 , PPC_INS_VADDUDM = 1206 , PPC_INS_VADDUHM = 1207 , PPC_INS_VADDUHS = 1208 , PPC_INS_VADDUQM = 1209 , PPC_INS_VADDUWM = 1210 , PPC_INS_VADDUWS = 1211 , PPC_INS_VAND = 1212 , PPC_INS_VANDC = 1213 , PPC_INS_VAVGSB = 1214 , PPC_INS_VAVGSH = 1215 , PPC_INS_VAVGSW = 1216 , PPC_INS_VAVGUB = 1217 , PPC_INS_VAVGUH = 1218 , PPC_INS_VAVGUW = 1219 , PPC_INS_VBPERMD = 1220 , PPC_INS_VBPERMQ = 1221 , PPC_INS_VCFSX = 1222 , PPC_INS_VCFUX = 1223 , PPC_INS_VCIPHER = 1224 , PPC_INS_VCIPHERLAST = 1225 , PPC_INS_VCLZB = 1226 , PPC_INS_VCLZD = 1227 , PPC_INS_VCLZH = 1228 , PPC_INS_VCLZLSBB = 1229 , PPC_INS_VCLZW = 1230 , PPC_INS_VCMPBFP = 1231 , PPC_INS_VCMPEQFP = 1232 , PPC_INS_VCMPEQUB = 1233 , PPC_INS_VCMPEQUD = 1234 , PPC_INS_VCMPEQUH = 1235 , PPC_INS_VCMPEQUW = 1236 , PPC_INS_VCMPGEFP = 1237 , PPC_INS_VCMPGTFP = 1238 , PPC_INS_VCMPGTSB = 1239 , PPC_INS_VCMPGTSD = 1240 , PPC_INS_VCMPGTSH = 1241 , PPC_INS_VCMPGTSW = 1242 , PPC_INS_VCMPGTUB = 1243 , PPC_INS_VCMPGTUD = 1244 , PPC_INS_VCMPGTUH = 1245 , PPC_INS_VCMPGTUW = 1246 , PPC_INS_VCMPNEB = 1247 , PPC_INS_VCMPNEH = 1248 , PPC_INS_VCMPNEW = 1249 , PPC_INS_VCMPNEZB = 1250 , PPC_INS_VCMPNEZH = 1251 , PPC_INS_VCMPNEZW = 1252 , PPC_INS_VCTSXS = 1253 , PPC_INS_VCTUXS = 1254 , PPC_INS_VCTZB = 1255 , PPC_INS_VCTZD = 1256 , PPC_INS_VCTZH = 1257 , PPC_INS_VCTZLSBB = 1258 , PPC_INS_VCTZW = 1259 , PPC_INS_VEQV = 1260 , PPC_INS_VEXPTEFP = 1261 , PPC_INS_VEXTRACTD = 1262 , PPC_INS_VEXTRACTUB = 1263 , PPC_INS_VEXTRACTUH = 1264 , PPC_INS_VEXTRACTUW = 1265 , PPC_INS_VEXTSB2D = 1266 , PPC_INS_VEXTSB2W = 1267 , PPC_INS_VEXTSH2D = 1268 , PPC_INS_VEXTSH2W = 1269 , PPC_INS_VEXTSW2D = 1270 , PPC_INS_VEXTUBLX = 1271 , PPC_INS_VEXTUBRX = 1272 , PPC_INS_VEXTUHLX = 1273 , PPC_INS_VEXTUHRX = 1274 , PPC_INS_VEXTUWLX = 1275 , PPC_INS_VEXTUWRX = 1276 , PPC_INS_VGBBD = 1277 , PPC_INS_VINSERTB = 1278 , PPC_INS_VINSERTD = 1279 , PPC_INS_VINSERTH = 1280 , PPC_INS_VINSERTW = 1281 , PPC_INS_VLOGEFP = 1282 , PPC_INS_VMADDFP = 1283 , PPC_INS_VMAXFP = 1284 , PPC_INS_VMAXSB = 1285 , PPC_INS_VMAXSD = 1286 , PPC_INS_VMAXSH = 1287 , PPC_INS_VMAXSW = 1288 , PPC_INS_VMAXUB = 1289 , PPC_INS_VMAXUD = 1290 , PPC_INS_VMAXUH = 1291 , PPC_INS_VMAXUW = 1292 , PPC_INS_VMHADDSHS = 1293 , PPC_INS_VMHRADDSHS = 1294 , PPC_INS_VMINFP = 1295 , PPC_INS_VMINSB = 1296 , PPC_INS_VMINSD = 1297 , PPC_INS_VMINSH = 1298 , PPC_INS_VMINSW = 1299 , PPC_INS_VMINUB = 1300 , PPC_INS_VMINUD = 1301 , PPC_INS_VMINUH = 1302 , PPC_INS_VMINUW = 1303 , PPC_INS_VMLADDUHM = 1304 , PPC_INS_VMR = 1305 , PPC_INS_VMRGEW = 1306 , PPC_INS_VMRGHB = 1307 , PPC_INS_VMRGHH = 1308 , PPC_INS_VMRGHW = 1309 , PPC_INS_VMRGLB = 1310 , PPC_INS_VMRGLH = 1311 , PPC_INS_VMRGLW = 1312 , PPC_INS_VMRGOW = 1313 , PPC_INS_VMSUMMBM = 1314 , PPC_INS_VMSUMSHM = 1315 , PPC_INS_VMSUMSHS = 1316 , PPC_INS_VMSUMUBM = 1317 , PPC_INS_VMSUMUHM = 1318 , PPC_INS_VMSUMUHS = 1319 , PPC_INS_VMUL10CUQ = 1320 , PPC_INS_VMUL10ECUQ = 1321 , PPC_INS_VMUL10EUQ = 1322 , PPC_INS_VMUL10UQ = 1323 , PPC_INS_VMULESB = 1324 , PPC_INS_VMULESH = 1325 , PPC_INS_VMULESW = 1326 , PPC_INS_VMULEUB = 1327 , PPC_INS_VMULEUH = 1328 , PPC_INS_VMULEUW = 1329 , PPC_INS_VMULOSB = 1330 , PPC_INS_VMULOSH = 1331 , PPC_INS_VMULOSW = 1332 , PPC_INS_VMULOUB = 1333 , PPC_INS_VMULOUH = 1334 , PPC_INS_VMULOUW = 1335 , PPC_INS_VMULUWM = 1336 , PPC_INS_VNAND = 1337 , PPC_INS_VNCIPHER = 1338 , PPC_INS_VNCIPHERLAST = 1339 , PPC_INS_VNEGD = 1340 , PPC_INS_VNEGW = 1341 , PPC_INS_VNMSUBFP = 1342 , PPC_INS_VNOR = 1343 , PPC_INS_VNOT = 1344 , PPC_INS_VOR = 1345 , PPC_INS_VORC = 1346 , PPC_INS_VPERM = 1347 , PPC_INS_VPERMR = 1348 , PPC_INS_VPERMXOR = 1349 , PPC_INS_VPKPX = 1350 , PPC_INS_VPKSDSS = 1351 , PPC_INS_VPKSDUS = 1352 , PPC_INS_VPKSHSS = 1353 , PPC_INS_VPKSHUS = 1354 , PPC_INS_VPKSWSS = 1355 , PPC_INS_VPKSWUS = 1356 , PPC_INS_VPKUDUM = 1357 , PPC_INS_VPKUDUS = 1358 , PPC_INS_VPKUHUM = 1359 , PPC_INS_VPKUHUS = 1360 , PPC_INS_VPKUWUM = 1361 , PPC_INS_VPKUWUS = 1362 , PPC_INS_VPMSUMB = 1363 , PPC_INS_VPMSUMD = 1364 , PPC_INS_VPMSUMH = 1365 , PPC_INS_VPMSUMW = 1366 , PPC_INS_VPOPCNTB = 1367 , PPC_INS_VPOPCNTD = 1368 , PPC_INS_VPOPCNTH = 1369 , PPC_INS_VPOPCNTW = 1370 , PPC_INS_VPRTYBD = 1371 , PPC_INS_VPRTYBQ = 1372 , PPC_INS_VPRTYBW = 1373 , PPC_INS_VREFP = 1374 , PPC_INS_VRFIM = 1375 , PPC_INS_VRFIN = 1376 , PPC_INS_VRFIP = 1377 , PPC_INS_VRFIZ = 1378 , PPC_INS_VRLB = 1379 , PPC_INS_VRLD = 1380 , PPC_INS_VRLDMI = 1381 , PPC_INS_VRLDNM = 1382 , PPC_INS_VRLH = 1383 , PPC_INS_VRLW = 1384 , PPC_INS_VRLWMI = 1385 , PPC_INS_VRLWNM = 1386 , PPC_INS_VRSQRTEFP = 1387 , PPC_INS_VSBOX = 1388 , PPC_INS_VSEL = 1389 , PPC_INS_VSHASIGMAD = 1390 , PPC_INS_VSHASIGMAW = 1391 , PPC_INS_VSL = 1392 , PPC_INS_VSLB = 1393 , PPC_INS_VSLD = 1394 , PPC_INS_VSLDOI = 1395 , PPC_INS_VSLH = 1396 , PPC_INS_VSLO = 1397 , PPC_INS_VSLV = 1398 , PPC_INS_VSLW = 1399 , PPC_INS_VSPLTB = 1400 , PPC_INS_VSPLTH = 1401 , PPC_INS_VSPLTISB = 1402 , PPC_INS_VSPLTISH = 1403 , PPC_INS_VSPLTISW = 1404 , PPC_INS_VSPLTW = 1405 , PPC_INS_VSR = 1406 , PPC_INS_VSRAB = 1407 , PPC_INS_VSRAD = 1408 , PPC_INS_VSRAH = 1409 , PPC_INS_VSRAW = 1410 , PPC_INS_VSRB = 1411 , PPC_INS_VSRD = 1412 , PPC_INS_VSRH = 1413 , PPC_INS_VSRO = 1414 , PPC_INS_VSRV = 1415 , PPC_INS_VSRW = 1416 , PPC_INS_VSUBCUQ = 1417 , PPC_INS_VSUBCUW = 1418 , PPC_INS_VSUBECUQ = 1419 , PPC_INS_VSUBEUQM = 1420 , PPC_INS_VSUBFP = 1421 , PPC_INS_VSUBSBS = 1422 , PPC_INS_VSUBSHS = 1423 , PPC_INS_VSUBSWS = 1424 , PPC_INS_VSUBUBM = 1425 , PPC_INS_VSUBUBS = 1426 , PPC_INS_VSUBUDM = 1427 , PPC_INS_VSUBUHM = 1428 , PPC_INS_VSUBUHS = 1429 , PPC_INS_VSUBUQM = 1430 , PPC_INS_VSUBUWM = 1431 , PPC_INS_VSUBUWS = 1432 , PPC_INS_VSUM2SWS = 1433 , PPC_INS_VSUM4SBS = 1434 , PPC_INS_VSUM4SHS = 1435 , PPC_INS_VSUM4UBS = 1436 , PPC_INS_VSUMSWS = 1437 , PPC_INS_VUPKHPX = 1438 , PPC_INS_VUPKHSB = 1439 , PPC_INS_VUPKHSH = 1440 , PPC_INS_VUPKHSW = 1441 , PPC_INS_VUPKLPX = 1442 , PPC_INS_VUPKLSB = 1443 , PPC_INS_VUPKLSH = 1444 , PPC_INS_VUPKLSW = 1445 , PPC_INS_VXOR = 1446 , PPC_INS_WAIT = 1447 , PPC_INS_WAITIMPL = 1448 , PPC_INS_WAITRSV = 1449 , PPC_INS_WRTEE = 1450 , PPC_INS_WRTEEI = 1451 , PPC_INS_XNOP = 1452 , PPC_INS_XOR = 1453 , PPC_INS_XORI = 1454 , PPC_INS_XORIS = 1455 , PPC_INS_XSABSDP = 1456 , PPC_INS_XSABSQP = 1457 , PPC_INS_XSADDDP = 1458 , PPC_INS_XSADDQP = 1459 , PPC_INS_XSADDQPO = 1460 , PPC_INS_XSADDSP = 1461 , PPC_INS_XSCMPEQDP = 1462 , PPC_INS_XSCMPEXPDP = 1463 , PPC_INS_XSCMPEXPQP = 1464 , PPC_INS_XSCMPGEDP = 1465 , PPC_INS_XSCMPGTDP = 1466 , PPC_INS_XSCMPODP = 1467 , PPC_INS_XSCMPOQP = 1468 , PPC_INS_XSCMPUDP = 1469 , PPC_INS_XSCMPUQP = 1470 , PPC_INS_XSCPSGNDP = 1471 , PPC_INS_XSCPSGNQP = 1472 , PPC_INS_XSCVDPHP = 1473 , PPC_INS_XSCVDPQP = 1474 , PPC_INS_XSCVDPSP = 1475 , PPC_INS_XSCVDPSPN = 1476 , PPC_INS_XSCVDPSXDS = 1477 , PPC_INS_XSCVDPSXWS = 1478 , PPC_INS_XSCVDPUXDS = 1479 , PPC_INS_XSCVDPUXWS = 1480 , PPC_INS_XSCVHPDP = 1481 , PPC_INS_XSCVQPDP = 1482 , PPC_INS_XSCVQPDPO = 1483 , PPC_INS_XSCVQPSDZ = 1484 , PPC_INS_XSCVQPSWZ = 1485 , PPC_INS_XSCVQPUDZ = 1486 , PPC_INS_XSCVQPUWZ = 1487 , PPC_INS_XSCVSDQP = 1488 , PPC_INS_XSCVSPDP = 1489 , PPC_INS_XSCVSPDPN = 1490 , PPC_INS_XSCVSXDDP = 1491 , PPC_INS_XSCVSXDSP = 1492 , PPC_INS_XSCVUDQP = 1493 , PPC_INS_XSCVUXDDP = 1494 , PPC_INS_XSCVUXDSP = 1495 , PPC_INS_XSDIVDP = 1496 , PPC_INS_XSDIVQP = 1497 , PPC_INS_XSDIVQPO = 1498 , PPC_INS_XSDIVSP = 1499 , PPC_INS_XSIEXPDP = 1500 , PPC_INS_XSIEXPQP = 1501 , PPC_INS_XSMADDADP = 1502 , PPC_INS_XSMADDASP = 1503 , PPC_INS_XSMADDMDP = 1504 , PPC_INS_XSMADDMSP = 1505 , PPC_INS_XSMADDQP = 1506 , PPC_INS_XSMADDQPO = 1507 , PPC_INS_XSMAXCDP = 1508 , PPC_INS_XSMAXDP = 1509 , PPC_INS_XSMAXJDP = 1510 , PPC_INS_XSMINCDP = 1511 , PPC_INS_XSMINDP = 1512 , PPC_INS_XSMINJDP = 1513 , PPC_INS_XSMSUBADP = 1514 , PPC_INS_XSMSUBASP = 1515 , PPC_INS_XSMSUBMDP = 1516 , PPC_INS_XSMSUBMSP = 1517 , PPC_INS_XSMSUBQP = 1518 , PPC_INS_XSMSUBQPO = 1519 , PPC_INS_XSMULDP = 1520 , PPC_INS_XSMULQP = 1521 , PPC_INS_XSMULQPO = 1522 , PPC_INS_XSMULSP = 1523 , PPC_INS_XSNABSDP = 1524 , PPC_INS_XSNABSQP = 1525 , PPC_INS_XSNEGDP = 1526 , PPC_INS_XSNEGQP = 1527 , PPC_INS_XSNMADDADP = 1528 , PPC_INS_XSNMADDASP = 1529 , PPC_INS_XSNMADDMDP = 1530 , PPC_INS_XSNMADDMSP = 1531 , PPC_INS_XSNMADDQP = 1532 , PPC_INS_XSNMADDQPO = 1533 , PPC_INS_XSNMSUBADP = 1534 , PPC_INS_XSNMSUBASP = 1535 , PPC_INS_XSNMSUBMDP = 1536 , PPC_INS_XSNMSUBMSP = 1537 , PPC_INS_XSNMSUBQP = 1538 , PPC_INS_XSNMSUBQPO = 1539 , PPC_INS_XSRDPI = 1540 , PPC_INS_XSRDPIC = 1541 , PPC_INS_XSRDPIM = 1542 , PPC_INS_XSRDPIP = 1543 , PPC_INS_XSRDPIZ = 1544 , PPC_INS_XSREDP = 1545 , PPC_INS_XSRESP = 1546 , PPC_INS_XSRQPI = 1547 , PPC_INS_XSRQPIX = 1548 , PPC_INS_XSRQPXP = 1549 , PPC_INS_XSRSP = 1550 , PPC_INS_XSRSQRTEDP = 1551 , PPC_INS_XSRSQRTESP = 1552 , PPC_INS_XSSQRTDP = 1553 , PPC_INS_XSSQRTQP = 1554 , PPC_INS_XSSQRTQPO = 1555 , PPC_INS_XSSQRTSP = 1556 , PPC_INS_XSSUBDP = 1557 , PPC_INS_XSSUBQP = 1558 , PPC_INS_XSSUBQPO = 1559 , PPC_INS_XSSUBSP = 1560 , PPC_INS_XSTDIVDP = 1561 , PPC_INS_XSTSQRTDP = 1562 , PPC_INS_XSTSTDCDP = 1563 , PPC_INS_XSTSTDCQP = 1564 , PPC_INS_XSTSTDCSP = 1565 , PPC_INS_XSXEXPDP = 1566 , PPC_INS_XSXEXPQP = 1567 , PPC_INS_XSXSIGDP = 1568 , PPC_INS_XSXSIGQP = 1569 , PPC_INS_XVABSDP = 1570 , PPC_INS_XVABSSP = 1571 , PPC_INS_XVADDDP = 1572 , PPC_INS_XVADDSP = 1573 , PPC_INS_XVCMPEQDP = 1574 , PPC_INS_XVCMPEQSP = 1575 , PPC_INS_XVCMPGEDP = 1576 , PPC_INS_XVCMPGESP = 1577 , PPC_INS_XVCMPGTDP = 1578 , PPC_INS_XVCMPGTSP = 1579 , PPC_INS_XVCPSGNDP = 1580 , PPC_INS_XVCPSGNSP = 1581 , PPC_INS_XVCVDPSP = 1582 , PPC_INS_XVCVDPSXDS = 1583 , PPC_INS_XVCVDPSXWS = 1584 , PPC_INS_XVCVDPUXDS = 1585 , PPC_INS_XVCVDPUXWS = 1586 , PPC_INS_XVCVHPSP = 1587 , PPC_INS_XVCVSPDP = 1588 , PPC_INS_XVCVSPHP = 1589 , PPC_INS_XVCVSPSXDS = 1590 , PPC_INS_XVCVSPSXWS = 1591 , PPC_INS_XVCVSPUXDS = 1592 , PPC_INS_XVCVSPUXWS = 1593 , PPC_INS_XVCVSXDDP = 1594 , PPC_INS_XVCVSXDSP = 1595 , PPC_INS_XVCVSXWDP = 1596 , PPC_INS_XVCVSXWSP = 1597 , PPC_INS_XVCVUXDDP = 1598 , PPC_INS_XVCVUXDSP = 1599 , PPC_INS_XVCVUXWDP = 1600 , PPC_INS_XVCVUXWSP = 1601 , PPC_INS_XVDIVDP = 1602 , PPC_INS_XVDIVSP = 1603 , PPC_INS_XVIEXPDP = 1604 , PPC_INS_XVIEXPSP = 1605 , PPC_INS_XVMADDADP = 1606 , PPC_INS_XVMADDASP = 1607 , PPC_INS_XVMADDMDP = 1608 , PPC_INS_XVMADDMSP = 1609 , PPC_INS_XVMAXDP = 1610 , PPC_INS_XVMAXSP = 1611 , PPC_INS_XVMINDP = 1612 , PPC_INS_XVMINSP = 1613 , PPC_INS_XVMOVDP = 1614 , PPC_INS_XVMOVSP = 1615 , PPC_INS_XVMSUBADP = 1616 , PPC_INS_XVMSUBASP = 1617 , PPC_INS_XVMSUBMDP = 1618 , PPC_INS_XVMSUBMSP = 1619 , PPC_INS_XVMULDP = 1620 , PPC_INS_XVMULSP = 1621 , PPC_INS_XVNABSDP = 1622 , PPC_INS_XVNABSSP = 1623 , PPC_INS_XVNEGDP = 1624 , PPC_INS_XVNEGSP = 1625 , PPC_INS_XVNMADDADP = 1626 , PPC_INS_XVNMADDASP = 1627 , PPC_INS_XVNMADDMDP = 1628 , PPC_INS_XVNMADDMSP = 1629 , PPC_INS_XVNMSUBADP = 1630 , PPC_INS_XVNMSUBASP = 1631 , PPC_INS_XVNMSUBMDP = 1632 , PPC_INS_XVNMSUBMSP = 1633 , PPC_INS_XVRDPI = 1634 , PPC_INS_XVRDPIC = 1635 , PPC_INS_XVRDPIM = 1636 , PPC_INS_XVRDPIP = 1637 , PPC_INS_XVRDPIZ = 1638 , PPC_INS_XVREDP = 1639 , PPC_INS_XVRESP = 1640 , PPC_INS_XVRSPI = 1641 , PPC_INS_XVRSPIC = 1642 , PPC_INS_XVRSPIM = 1643 , PPC_INS_XVRSPIP = 1644 , PPC_INS_XVRSPIZ = 1645 , PPC_INS_XVRSQRTEDP = 1646 , PPC_INS_XVRSQRTESP = 1647 , PPC_INS_XVSQRTDP = 1648 , PPC_INS_XVSQRTSP = 1649 , PPC_INS_XVSUBDP = 1650 , PPC_INS_XVSUBSP = 1651 , PPC_INS_XVTDIVDP = 1652 , PPC_INS_XVTDIVSP = 1653 , PPC_INS_XVTSQRTDP = 1654 , PPC_INS_XVTSQRTSP = 1655 , PPC_INS_XVTSTDCDP = 1656 , PPC_INS_XVTSTDCSP = 1657 , PPC_INS_XVXEXPDP = 1658 , PPC_INS_XVXEXPSP = 1659 , PPC_INS_XVXSIGDP = 1660 , PPC_INS_XVXSIGSP = 1661 , PPC_INS_XXBRD = 1662 , PPC_INS_XXBRH = 1663 , PPC_INS_XXBRQ = 1664 , PPC_INS_XXBRW = 1665 , PPC_INS_XXEXTRACTUW = 1666 , PPC_INS_XXINSERTW = 1667 , PPC_INS_XXLAND = 1668 , PPC_INS_XXLANDC = 1669 , PPC_INS_XXLEQV = 1670 , PPC_INS_XXLNAND = 1671 , PPC_INS_XXLNOR = 1672 , PPC_INS_XXLOR = 1673 , PPC_INS_XXLORC = 1674 , PPC_INS_XXLXOR = 1675 , PPC_INS_XXMRGHD = 1676 , PPC_INS_XXMRGHW = 1677 , PPC_INS_XXMRGLD = 1678 , PPC_INS_XXMRGLW = 1679 , PPC_INS_XXPERM = 1680 , PPC_INS_XXPERMDI = 1681 , PPC_INS_XXPERMR = 1682 , PPC_INS_XXSEL = 1683 , PPC_INS_XXSLDWI = 1684 , PPC_INS_XXSPLTD = 1685 , PPC_INS_XXSPLTIB = 1686 , PPC_INS_XXSPLTW = 1687 , PPC_INS_XXSWAPD = 1688 , PPC_INS_DCBZ_L = 1689 , PPC_INS_PSQ_L = 1690 , PPC_INS_PSQ_LU = 1691 , PPC_INS_PSQ_LUX = 1692 , PPC_INS_PSQ_LX = 1693 , PPC_INS_PSQ_ST = 1694 , PPC_INS_PSQ_STU = 1695 , PPC_INS_PSQ_STUX = 1696 , PPC_INS_PSQ_STX = 1697 , PPC_INS_PS_ABS = 1698 , PPC_INS_PS_ADD = 1699 , PPC_INS_PS_CMPO0 = 1700 , PPC_INS_PS_CMPO1 = 1701 , PPC_INS_PS_CMPU0 = 1702 , PPC_INS_PS_CMPU1 = 1703 , PPC_INS_PS_DIV = 1704 , PPC_INS_PS_MADD = 1705 , PPC_INS_PS_MADDS0 = 1706 , PPC_INS_PS_MADDS1 = 1707 , PPC_INS_PS_MERGE00 = 1708 , PPC_INS_PS_MERGE01 = 1709 , PPC_INS_PS_MERGE10 = 1710 , PPC_INS_PS_MERGE11 = 1711 , PPC_INS_PS_MR = 1712 , PPC_INS_PS_MSUB = 1713 , PPC_INS_PS_MUL = 1714 , PPC_INS_PS_MULS0 = 1715 , PPC_INS_PS_MULS1 = 1716 , PPC_INS_PS_NABS = 1717 , PPC_INS_PS_NEG = 1718 , PPC_INS_PS_NMADD = 1719 , PPC_INS_PS_NMSUB = 1720 , PPC_INS_PS_RES = 1721 , PPC_INS_PS_RSQRTE = 1722 , PPC_INS_PS_SEL = 1723 , PPC_INS_PS_SUB = 1724 , PPC_INS_PS_SUM0 = 1725 , PPC_INS_PS_SUM1 = 1726 , PPC_INS_ENDING = 1727 , } # [repr (u32)] # [doc = " Group of PPC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn_group { # [doc = "< = CS_GRP_INVALID"] PPC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] PPC_GRP_JUMP = 1 , PPC_GRP_ALTIVEC = 128 , PPC_GRP_MODE32 = 129 , PPC_GRP_MODE64 = 130 , PPC_GRP_BOOKE = 131 , PPC_GRP_NOTBOOKE = 132 , PPC_GRP_SPE = 133 , PPC_GRP_VSX = 134 , PPC_GRP_E500 = 135 , PPC_GRP_PPC4XX = 136 , PPC_GRP_PPC6XX = 137 , PPC_GRP_ICBT = 138 , PPC_GRP_P8ALTIVEC = 139 , PPC_GRP_P8VECTOR = 140 , PPC_GRP_QPX = 141 , PPC_GRP_PS = 142 , PPC_GRP_ENDING = 143 , } # [repr (u32)] # [doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_cc { # [doc = "< invalid CC (default)"] SPARC_CC_INVALID = 0 , # [doc = "< Always"] SPARC_CC_ICC_A = 264 , # [doc = "< Never"] SPARC_CC_ICC_N = 256 , # [doc = "< Not Equal"] SPARC_CC_ICC_NE = 265 , # [doc = "< Equal"] SPARC_CC_ICC_E = 257 , # [doc = "< Greater"] SPARC_CC_ICC_G = 266 , # [doc = "< Less or Equal"] SPARC_CC_ICC_LE = 258 , # [doc = "< Greater or Equal"] SPARC_CC_ICC_GE = 267 , # [doc = "< Less"] SPARC_CC_ICC_L = 259 , # [doc = "< Greater Unsigned"] SPARC_CC_ICC_GU = 268 , # [doc = "< Less or Equal Unsigned"] SPARC_CC_ICC_LEU = 260 , # [doc = "< Carry Clear/Great or Equal Unsigned"] SPARC_CC_ICC_CC = 269 , # [doc = "< Carry Set/Less Unsigned"] SPARC_CC_ICC_CS = 261 , # [doc = "< Positive"] SPARC_CC_ICC_POS = 270 , # [doc = "< Negative"] SPARC_CC_ICC_NEG = 262 , # [doc = "< Overflow Clear"] SPARC_CC_ICC_VC = 271 , # [doc = "< Overflow Set"] SPARC_CC_ICC_VS = 263 , # [doc = "< Always"] SPARC_CC_FCC_A = 280 , # [doc = "< Never"] SPARC_CC_FCC_N = 272 , # [doc = "< Unordered"] SPARC_CC_FCC_U = 279 , # [doc = "< Greater"] SPARC_CC_FCC_G = 278 , # [doc = "< Unordered or Greater"] SPARC_CC_FCC_UG = 277 , # [doc = "< Less"] SPARC_CC_FCC_L = 276 , # [doc = "< Unordered or Less"] SPARC_CC_FCC_UL = 275 , # [doc = "< Less or Greater"] SPARC_CC_FCC_LG = 274 , # [doc = "< Not Equal"] SPARC_CC_FCC_NE = 273 , # [doc = "< Equal"] SPARC_CC_FCC_E = 281 , # [doc = "< Unordered or Equal"] SPARC_CC_FCC_UE = 282 , # [doc = "< Greater or Equal"] SPARC_CC_FCC_GE = 283 , # [doc = "< Unordered or Greater or Equal"] SPARC_CC_FCC_UGE = 284 , # [doc = "< Less or Equal"] SPARC_CC_FCC_LE = 285 , # [doc = "< Unordered or Less or Equal"] SPARC_CC_FCC_ULE = 286 , # [doc = "< Ordered"] SPARC_CC_FCC_O = 287 , } # [repr (u32)] # [doc = " Branch hint"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_hint { # [doc = "< no hint"] SPARC_HINT_INVALID = 0 , # [doc = "< annul delay slot instruction"] SPARC_HINT_A = 1 , # [doc = "< branch taken"] SPARC_HINT_PT = 2 , # [doc = "< branch NOT taken"] SPARC_HINT_PN = 4 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SPARC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SPARC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SPARC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SPARC_OP_MEM = 3 , } impl sparc_reg { pub const SPARC_REG_O6 : sparc_reg = sparc_reg :: SPARC_REG_SP ; } impl sparc_reg { pub const SPARC_REG_I6 : sparc_reg = sparc_reg :: SPARC_REG_FP ; } # [repr (u32)] # [doc = " SPARC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_reg { SPARC_REG_INVALID = 0 , SPARC_REG_F0 = 1 , SPARC_REG_F1 = 2 , SPARC_REG_F2 = 3 , SPARC_REG_F3 = 4 , SPARC_REG_F4 = 5 , SPARC_REG_F5 = 6 , SPARC_REG_F6 = 7 , SPARC_REG_F7 = 8 , SPARC_REG_F8 = 9 , SPARC_REG_F9 = 10 , SPARC_REG_F10 = 11 , SPARC_REG_F11 = 12 , SPARC_REG_F12 = 13 , SPARC_REG_F13 = 14 , SPARC_REG_F14 = 15 , SPARC_REG_F15 = 16 , SPARC_REG_F16 = 17 , SPARC_REG_F17 = 18 , SPARC_REG_F18 = 19 , SPARC_REG_F19 = 20 , SPARC_REG_F20 = 21 , SPARC_REG_F21 = 22 , SPARC_REG_F22 = 23 , SPARC_REG_F23 = 24 , SPARC_REG_F24 = 25 , SPARC_REG_F25 = 26 , SPARC_REG_F26 = 27 , SPARC_REG_F27 = 28 , SPARC_REG_F28 = 29 , SPARC_REG_F29 = 30 , SPARC_REG_F30 = 31 , SPARC_REG_F31 = 32 , SPARC_REG_F32 = 33 , SPARC_REG_F34 = 34 , SPARC_REG_F36 = 35 , SPARC_REG_F38 = 36 , SPARC_REG_F40 = 37 , SPARC_REG_F42 = 38 , SPARC_REG_F44 = 39 , SPARC_REG_F46 = 40 , SPARC_REG_F48 = 41 , SPARC_REG_F50 = 42 , SPARC_REG_F52 = 43 , SPARC_REG_F54 = 44 , SPARC_REG_F56 = 45 , SPARC_REG_F58 = 46 , SPARC_REG_F60 = 47 , SPARC_REG_F62 = 48 , SPARC_REG_FCC0 = 49 , SPARC_REG_FCC1 = 50 , SPARC_REG_FCC2 = 51 , SPARC_REG_FCC3 = 52 , SPARC_REG_FP = 53 , SPARC_REG_G0 = 54 , SPARC_REG_G1 = 55 , SPARC_REG_G2 = 56 , SPARC_REG_G3 = 57 , SPARC_REG_G4 = 58 , SPARC_REG_G5 = 59 , SPARC_REG_G6 = 60 , SPARC_REG_G7 = 61 , SPARC_REG_I0 = 62 , SPARC_REG_I1 = 63 , SPARC_REG_I2 = 64 , SPARC_REG_I3 = 65 , SPARC_REG_I4 = 66 , SPARC_REG_I5 = 67 , SPARC_REG_I7 = 68 , SPARC_REG_ICC = 69 , SPARC_REG_L0 = 70 , SPARC_REG_L1 = 71 , SPARC_REG_L2 = 72 , SPARC_REG_L3 = 73 , SPARC_REG_L4 = 74 , SPARC_REG_L5 = 75 , SPARC_REG_L6 = 76 , SPARC_REG_L7 = 77 , SPARC_REG_O0 = 78 , SPARC_REG_O1 = 79 , SPARC_REG_O2 = 80 , SPARC_REG_O3 = 81 , SPARC_REG_O4 = 82 , SPARC_REG_O5 = 83 , SPARC_REG_O7 = 84 , SPARC_REG_SP = 85 , SPARC_REG_Y = 86 , SPARC_REG_XCC = 87 , SPARC_REG_ENDING = 88 , } # [doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sparc_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sparc_op_mem"] [:: std :: mem :: size_of :: < sparc_op_mem > () - 8usize] ; ["Alignment of sparc_op_mem"] [:: std :: mem :: align_of :: < sparc_op_mem > () - 4usize] ; ["Offset of field: sparc_op_mem::base"] [:: std :: mem :: offset_of ! (sparc_op_mem , base) - 0usize] ; ["Offset of field: sparc_op_mem::index"] [:: std :: mem :: offset_of ! (sparc_op_mem , index) - 1usize] ; ["Offset of field: sparc_op_mem::disp"] [:: std :: mem :: offset_of ! (sparc_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc_op { # [doc = "< operand type"] pub type_ : sparc_op_type , pub __bindgen_anon_1 : cs_sparc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sparc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sparc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sparc_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op"] [:: std :: mem :: size_of :: < cs_sparc_op > () - 16usize] ; ["Alignment of cs_sparc_op"] [:: std :: mem :: align_of :: < cs_sparc_op > () - 8usize] ; ["Offset of field: cs_sparc_op::type_"] [:: std :: mem :: offset_of ! (cs_sparc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc { # [doc = "< code condition for this insn"] pub cc : sparc_cc , # [doc = "< branch hint: encoding as bitwise OR of sparc_hint."] pub hint : sparc_hint , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sparc_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc"] [:: std :: mem :: size_of :: < cs_sparc > () - 80usize] ; ["Alignment of cs_sparc"] [:: std :: mem :: align_of :: < cs_sparc > () - 8usize] ; ["Offset of field: cs_sparc::cc"] [:: std :: mem :: offset_of ! (cs_sparc , cc) - 0usize] ; ["Offset of field: cs_sparc::hint"] [:: std :: mem :: offset_of ! (cs_sparc , hint) - 4usize] ; ["Offset of field: cs_sparc::op_count"] [:: std :: mem :: offset_of ! (cs_sparc , op_count) - 8usize] ; ["Offset of field: cs_sparc::operands"] [:: std :: mem :: offset_of ! (cs_sparc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . hint , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SPARC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn { SPARC_INS_INVALID = 0 , SPARC_INS_ADDCC = 1 , SPARC_INS_ADDX = 2 , SPARC_INS_ADDXCC = 3 , SPARC_INS_ADDXC = 4 , SPARC_INS_ADDXCCC = 5 , SPARC_INS_ADD = 6 , SPARC_INS_ALIGNADDR = 7 , SPARC_INS_ALIGNADDRL = 8 , SPARC_INS_ANDCC = 9 , SPARC_INS_ANDNCC = 10 , SPARC_INS_ANDN = 11 , SPARC_INS_AND = 12 , SPARC_INS_ARRAY16 = 13 , SPARC_INS_ARRAY32 = 14 , SPARC_INS_ARRAY8 = 15 , SPARC_INS_B = 16 , SPARC_INS_JMP = 17 , SPARC_INS_BMASK = 18 , SPARC_INS_FB = 19 , SPARC_INS_BRGEZ = 20 , SPARC_INS_BRGZ = 21 , SPARC_INS_BRLEZ = 22 , SPARC_INS_BRLZ = 23 , SPARC_INS_BRNZ = 24 , SPARC_INS_BRZ = 25 , SPARC_INS_BSHUFFLE = 26 , SPARC_INS_CALL = 27 , SPARC_INS_CASX = 28 , SPARC_INS_CAS = 29 , SPARC_INS_CMASK16 = 30 , SPARC_INS_CMASK32 = 31 , SPARC_INS_CMASK8 = 32 , SPARC_INS_CMP = 33 , SPARC_INS_EDGE16 = 34 , SPARC_INS_EDGE16L = 35 , SPARC_INS_EDGE16LN = 36 , SPARC_INS_EDGE16N = 37 , SPARC_INS_EDGE32 = 38 , SPARC_INS_EDGE32L = 39 , SPARC_INS_EDGE32LN = 40 , SPARC_INS_EDGE32N = 41 , SPARC_INS_EDGE8 = 42 , SPARC_INS_EDGE8L = 43 , SPARC_INS_EDGE8LN = 44 , SPARC_INS_EDGE8N = 45 , SPARC_INS_FABSD = 46 , SPARC_INS_FABSQ = 47 , SPARC_INS_FABSS = 48 , SPARC_INS_FADDD = 49 , SPARC_INS_FADDQ = 50 , SPARC_INS_FADDS = 51 , SPARC_INS_FALIGNDATA = 52 , SPARC_INS_FAND = 53 , SPARC_INS_FANDNOT1 = 54 , SPARC_INS_FANDNOT1S = 55 , SPARC_INS_FANDNOT2 = 56 , SPARC_INS_FANDNOT2S = 57 , SPARC_INS_FANDS = 58 , SPARC_INS_FCHKSM16 = 59 , SPARC_INS_FCMPD = 60 , SPARC_INS_FCMPEQ16 = 61 , SPARC_INS_FCMPEQ32 = 62 , SPARC_INS_FCMPGT16 = 63 , SPARC_INS_FCMPGT32 = 64 , SPARC_INS_FCMPLE16 = 65 , SPARC_INS_FCMPLE32 = 66 , SPARC_INS_FCMPNE16 = 67 , SPARC_INS_FCMPNE32 = 68 , SPARC_INS_FCMPQ = 69 , SPARC_INS_FCMPS = 70 , SPARC_INS_FDIVD = 71 , SPARC_INS_FDIVQ = 72 , SPARC_INS_FDIVS = 73 , SPARC_INS_FDMULQ = 74 , SPARC_INS_FDTOI = 75 , SPARC_INS_FDTOQ = 76 , SPARC_INS_FDTOS = 77 , SPARC_INS_FDTOX = 78 , SPARC_INS_FEXPAND = 79 , SPARC_INS_FHADDD = 80 , SPARC_INS_FHADDS = 81 , SPARC_INS_FHSUBD = 82 , SPARC_INS_FHSUBS = 83 , SPARC_INS_FITOD = 84 , SPARC_INS_FITOQ = 85 , SPARC_INS_FITOS = 86 , SPARC_INS_FLCMPD = 87 , SPARC_INS_FLCMPS = 88 , SPARC_INS_FLUSHW = 89 , SPARC_INS_FMEAN16 = 90 , SPARC_INS_FMOVD = 91 , SPARC_INS_FMOVQ = 92 , SPARC_INS_FMOVRDGEZ = 93 , SPARC_INS_FMOVRQGEZ = 94 , SPARC_INS_FMOVRSGEZ = 95 , SPARC_INS_FMOVRDGZ = 96 , SPARC_INS_FMOVRQGZ = 97 , SPARC_INS_FMOVRSGZ = 98 , SPARC_INS_FMOVRDLEZ = 99 , SPARC_INS_FMOVRQLEZ = 100 , SPARC_INS_FMOVRSLEZ = 101 , SPARC_INS_FMOVRDLZ = 102 , SPARC_INS_FMOVRQLZ = 103 , SPARC_INS_FMOVRSLZ = 104 , SPARC_INS_FMOVRDNZ = 105 , SPARC_INS_FMOVRQNZ = 106 , SPARC_INS_FMOVRSNZ = 107 , SPARC_INS_FMOVRDZ = 108 , SPARC_INS_FMOVRQZ = 109 , SPARC_INS_FMOVRSZ = 110 , SPARC_INS_FMOVS = 111 , SPARC_INS_FMUL8SUX16 = 112 , SPARC_INS_FMUL8ULX16 = 113 , SPARC_INS_FMUL8X16 = 114 , SPARC_INS_FMUL8X16AL = 115 , SPARC_INS_FMUL8X16AU = 116 , SPARC_INS_FMULD = 117 , SPARC_INS_FMULD8SUX16 = 118 , SPARC_INS_FMULD8ULX16 = 119 , SPARC_INS_FMULQ = 120 , SPARC_INS_FMULS = 121 , SPARC_INS_FNADDD = 122 , SPARC_INS_FNADDS = 123 , SPARC_INS_FNAND = 124 , SPARC_INS_FNANDS = 125 , SPARC_INS_FNEGD = 126 , SPARC_INS_FNEGQ = 127 , SPARC_INS_FNEGS = 128 , SPARC_INS_FNHADDD = 129 , SPARC_INS_FNHADDS = 130 , SPARC_INS_FNOR = 131 , SPARC_INS_FNORS = 132 , SPARC_INS_FNOT1 = 133 , SPARC_INS_FNOT1S = 134 , SPARC_INS_FNOT2 = 135 , SPARC_INS_FNOT2S = 136 , SPARC_INS_FONE = 137 , SPARC_INS_FONES = 138 , SPARC_INS_FOR = 139 , SPARC_INS_FORNOT1 = 140 , SPARC_INS_FORNOT1S = 141 , SPARC_INS_FORNOT2 = 142 , SPARC_INS_FORNOT2S = 143 , SPARC_INS_FORS = 144 , SPARC_INS_FPACK16 = 145 , SPARC_INS_FPACK32 = 146 , SPARC_INS_FPACKFIX = 147 , SPARC_INS_FPADD16 = 148 , SPARC_INS_FPADD16S = 149 , SPARC_INS_FPADD32 = 150 , SPARC_INS_FPADD32S = 151 , SPARC_INS_FPADD64 = 152 , SPARC_INS_FPMERGE = 153 , SPARC_INS_FPSUB16 = 154 , SPARC_INS_FPSUB16S = 155 , SPARC_INS_FPSUB32 = 156 , SPARC_INS_FPSUB32S = 157 , SPARC_INS_FQTOD = 158 , SPARC_INS_FQTOI = 159 , SPARC_INS_FQTOS = 160 , SPARC_INS_FQTOX = 161 , SPARC_INS_FSLAS16 = 162 , SPARC_INS_FSLAS32 = 163 , SPARC_INS_FSLL16 = 164 , SPARC_INS_FSLL32 = 165 , SPARC_INS_FSMULD = 166 , SPARC_INS_FSQRTD = 167 , SPARC_INS_FSQRTQ = 168 , SPARC_INS_FSQRTS = 169 , SPARC_INS_FSRA16 = 170 , SPARC_INS_FSRA32 = 171 , SPARC_INS_FSRC1 = 172 , SPARC_INS_FSRC1S = 173 , SPARC_INS_FSRC2 = 174 , SPARC_INS_FSRC2S = 175 , SPARC_INS_FSRL16 = 176 , SPARC_INS_FSRL32 = 177 , SPARC_INS_FSTOD = 178 , SPARC_INS_FSTOI = 179 , SPARC_INS_FSTOQ = 180 , SPARC_INS_FSTOX = 181 , SPARC_INS_FSUBD = 182 , SPARC_INS_FSUBQ = 183 , SPARC_INS_FSUBS = 184 , SPARC_INS_FXNOR = 185 , SPARC_INS_FXNORS = 186 , SPARC_INS_FXOR = 187 , SPARC_INS_FXORS = 188 , SPARC_INS_FXTOD = 189 , SPARC_INS_FXTOQ = 190 , SPARC_INS_FXTOS = 191 , SPARC_INS_FZERO = 192 , SPARC_INS_FZEROS = 193 , SPARC_INS_JMPL = 194 , SPARC_INS_LDD = 195 , SPARC_INS_LD = 196 , SPARC_INS_LDQ = 197 , SPARC_INS_LDSB = 198 , SPARC_INS_LDSH = 199 , SPARC_INS_LDSW = 200 , SPARC_INS_LDUB = 201 , SPARC_INS_LDUH = 202 , SPARC_INS_LDX = 203 , SPARC_INS_LZCNT = 204 , SPARC_INS_MEMBAR = 205 , SPARC_INS_MOVDTOX = 206 , SPARC_INS_MOV = 207 , SPARC_INS_MOVRGEZ = 208 , SPARC_INS_MOVRGZ = 209 , SPARC_INS_MOVRLEZ = 210 , SPARC_INS_MOVRLZ = 211 , SPARC_INS_MOVRNZ = 212 , SPARC_INS_MOVRZ = 213 , SPARC_INS_MOVSTOSW = 214 , SPARC_INS_MOVSTOUW = 215 , SPARC_INS_MULX = 216 , SPARC_INS_NOP = 217 , SPARC_INS_ORCC = 218 , SPARC_INS_ORNCC = 219 , SPARC_INS_ORN = 220 , SPARC_INS_OR = 221 , SPARC_INS_PDIST = 222 , SPARC_INS_PDISTN = 223 , SPARC_INS_POPC = 224 , SPARC_INS_RD = 225 , SPARC_INS_RESTORE = 226 , SPARC_INS_RETT = 227 , SPARC_INS_SAVE = 228 , SPARC_INS_SDIVCC = 229 , SPARC_INS_SDIVX = 230 , SPARC_INS_SDIV = 231 , SPARC_INS_SETHI = 232 , SPARC_INS_SHUTDOWN = 233 , SPARC_INS_SIAM = 234 , SPARC_INS_SLLX = 235 , SPARC_INS_SLL = 236 , SPARC_INS_SMULCC = 237 , SPARC_INS_SMUL = 238 , SPARC_INS_SRAX = 239 , SPARC_INS_SRA = 240 , SPARC_INS_SRLX = 241 , SPARC_INS_SRL = 242 , SPARC_INS_STBAR = 243 , SPARC_INS_STB = 244 , SPARC_INS_STD = 245 , SPARC_INS_ST = 246 , SPARC_INS_STH = 247 , SPARC_INS_STQ = 248 , SPARC_INS_STX = 249 , SPARC_INS_SUBCC = 250 , SPARC_INS_SUBX = 251 , SPARC_INS_SUBXCC = 252 , SPARC_INS_SUB = 253 , SPARC_INS_SWAP = 254 , SPARC_INS_TADDCCTV = 255 , SPARC_INS_TADDCC = 256 , SPARC_INS_T = 257 , SPARC_INS_TSUBCCTV = 258 , SPARC_INS_TSUBCC = 259 , SPARC_INS_UDIVCC = 260 , SPARC_INS_UDIVX = 261 , SPARC_INS_UDIV = 262 , SPARC_INS_UMULCC = 263 , SPARC_INS_UMULXHI = 264 , SPARC_INS_UMUL = 265 , SPARC_INS_UNIMP = 266 , SPARC_INS_FCMPED = 267 , SPARC_INS_FCMPEQ = 268 , SPARC_INS_FCMPES = 269 , SPARC_INS_WR = 270 , SPARC_INS_XMULX = 271 , SPARC_INS_XMULXHI = 272 , SPARC_INS_XNORCC = 273 , SPARC_INS_XNOR = 274 , SPARC_INS_XORCC = 275 , SPARC_INS_XOR = 276 , SPARC_INS_RET = 277 , SPARC_INS_RETL = 278 , SPARC_INS_ENDING = 279 , } # [repr (u32)] # [doc = " Group of SPARC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn_group { # [doc = "< = CS_GRP_INVALID"] SPARC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SPARC_GRP_JUMP = 1 , SPARC_GRP_HARDQUAD = 128 , SPARC_GRP_V9 = 129 , SPARC_GRP_VIS = 130 , SPARC_GRP_VIS2 = 131 , SPARC_GRP_VIS3 = 132 , SPARC_GRP_32BIT = 133 , SPARC_GRP_64BIT = 134 , SPARC_GRP_ENDING = 135 , } # [repr (u32)] # [doc = " Enums corresponding to SystemZ condition codes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_cc { # [doc = "< invalid CC (default)"] SYSZ_CC_INVALID = 0 , SYSZ_CC_O = 1 , SYSZ_CC_H = 2 , SYSZ_CC_NLE = 3 , SYSZ_CC_L = 4 , SYSZ_CC_NHE = 5 , SYSZ_CC_LH = 6 , SYSZ_CC_NE = 7 , SYSZ_CC_E = 8 , SYSZ_CC_NLH = 9 , SYSZ_CC_HE = 10 , SYSZ_CC_NL = 11 , SYSZ_CC_LE = 12 , SYSZ_CC_NH = 13 , SYSZ_CC_NO = 14 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SYSZ_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SYSZ_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SYSZ_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SYSZ_OP_MEM = 3 , # [doc = "< Access register operand."] SYSZ_OP_ACREG = 64 , } # [repr (u32)] # [doc = " SystemZ registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_reg { SYSZ_REG_INVALID = 0 , SYSZ_REG_0 = 1 , SYSZ_REG_1 = 2 , SYSZ_REG_2 = 3 , SYSZ_REG_3 = 4 , SYSZ_REG_4 = 5 , SYSZ_REG_5 = 6 , SYSZ_REG_6 = 7 , SYSZ_REG_7 = 8 , SYSZ_REG_8 = 9 , SYSZ_REG_9 = 10 , SYSZ_REG_10 = 11 , SYSZ_REG_11 = 12 , SYSZ_REG_12 = 13 , SYSZ_REG_13 = 14 , SYSZ_REG_14 = 15 , SYSZ_REG_15 = 16 , SYSZ_REG_CC = 17 , SYSZ_REG_F0 = 18 , SYSZ_REG_F1 = 19 , SYSZ_REG_F2 = 20 , SYSZ_REG_F3 = 21 , SYSZ_REG_F4 = 22 , SYSZ_REG_F5 = 23 , SYSZ_REG_F6 = 24 , SYSZ_REG_F7 = 25 , SYSZ_REG_F8 = 26 , SYSZ_REG_F9 = 27 , SYSZ_REG_F10 = 28 , SYSZ_REG_F11 = 29 , SYSZ_REG_F12 = 30 , SYSZ_REG_F13 = 31 , SYSZ_REG_F14 = 32 , SYSZ_REG_F15 = 33 , SYSZ_REG_R0L = 34 , SYSZ_REG_A0 = 35 , SYSZ_REG_A1 = 36 , SYSZ_REG_A2 = 37 , SYSZ_REG_A3 = 38 , SYSZ_REG_A4 = 39 , SYSZ_REG_A5 = 40 , SYSZ_REG_A6 = 41 , SYSZ_REG_A7 = 42 , SYSZ_REG_A8 = 43 , SYSZ_REG_A9 = 44 , SYSZ_REG_A10 = 45 , SYSZ_REG_A11 = 46 , SYSZ_REG_A12 = 47 , SYSZ_REG_A13 = 48 , SYSZ_REG_A14 = 49 , SYSZ_REG_A15 = 50 , SYSZ_REG_C0 = 51 , SYSZ_REG_C1 = 52 , SYSZ_REG_C2 = 53 , SYSZ_REG_C3 = 54 , SYSZ_REG_C4 = 55 , SYSZ_REG_C5 = 56 , SYSZ_REG_C6 = 57 , SYSZ_REG_C7 = 58 , SYSZ_REG_C8 = 59 , SYSZ_REG_C9 = 60 , SYSZ_REG_C10 = 61 , SYSZ_REG_C11 = 62 , SYSZ_REG_C12 = 63 , SYSZ_REG_C13 = 64 , SYSZ_REG_C14 = 65 , SYSZ_REG_C15 = 66 , SYSZ_REG_V0 = 67 , SYSZ_REG_V1 = 68 , SYSZ_REG_V2 = 69 , SYSZ_REG_V3 = 70 , SYSZ_REG_V4 = 71 , SYSZ_REG_V5 = 72 , SYSZ_REG_V6 = 73 , SYSZ_REG_V7 = 74 , SYSZ_REG_V8 = 75 , SYSZ_REG_V9 = 76 , SYSZ_REG_V10 = 77 , SYSZ_REG_V11 = 78 , SYSZ_REG_V12 = 79 , SYSZ_REG_V13 = 80 , SYSZ_REG_V14 = 81 , SYSZ_REG_V15 = 82 , SYSZ_REG_V16 = 83 , SYSZ_REG_V17 = 84 , SYSZ_REG_V18 = 85 , SYSZ_REG_V19 = 86 , SYSZ_REG_V20 = 87 , SYSZ_REG_V21 = 88 , SYSZ_REG_V22 = 89 , SYSZ_REG_V23 = 90 , SYSZ_REG_V24 = 91 , SYSZ_REG_V25 = 92 , SYSZ_REG_V26 = 93 , SYSZ_REG_V27 = 94 , SYSZ_REG_V28 = 95 , SYSZ_REG_V29 = 96 , SYSZ_REG_V30 = 97 , SYSZ_REG_V31 = 98 , SYSZ_REG_F16 = 99 , SYSZ_REG_F17 = 100 , SYSZ_REG_F18 = 101 , SYSZ_REG_F19 = 102 , SYSZ_REG_F20 = 103 , SYSZ_REG_F21 = 104 , SYSZ_REG_F22 = 105 , SYSZ_REG_F23 = 106 , SYSZ_REG_F24 = 107 , SYSZ_REG_F25 = 108 , SYSZ_REG_F26 = 109 , SYSZ_REG_F27 = 110 , SYSZ_REG_F28 = 111 , SYSZ_REG_F29 = 112 , SYSZ_REG_F30 = 113 , SYSZ_REG_F31 = 114 , SYSZ_REG_F0Q = 115 , SYSZ_REG_F4Q = 116 , SYSZ_REG_ENDING = 117 , } # [doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sysz_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< BDLAddr operand"] pub length : u64 , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sysz_op_mem"] [:: std :: mem :: size_of :: < sysz_op_mem > () - 24usize] ; ["Alignment of sysz_op_mem"] [:: std :: mem :: align_of :: < sysz_op_mem > () - 8usize] ; ["Offset of field: sysz_op_mem::base"] [:: std :: mem :: offset_of ! (sysz_op_mem , base) - 0usize] ; ["Offset of field: sysz_op_mem::index"] [:: std :: mem :: offset_of ! (sysz_op_mem , index) - 1usize] ; ["Offset of field: sysz_op_mem::length"] [:: std :: mem :: offset_of ! (sysz_op_mem , length) - 8usize] ; ["Offset of field: sysz_op_mem::disp"] [:: std :: mem :: offset_of ! (sysz_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz_op { # [doc = "< operand type"] pub type_ : sysz_op_type , pub __bindgen_anon_1 : cs_sysz_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sysz_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sysz_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sysz_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sysz_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sysz_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op"] [:: std :: mem :: size_of :: < cs_sysz_op > () - 32usize] ; ["Alignment of cs_sysz_op"] [:: std :: mem :: align_of :: < cs_sysz_op > () - 8usize] ; ["Offset of field: cs_sysz_op::type_"] [:: std :: mem :: offset_of ! (cs_sysz_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz { # [doc = "< Code condition"] pub cc : sysz_cc , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sysz_op ; 6usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz"] [:: std :: mem :: size_of :: < cs_sysz > () - 200usize] ; ["Alignment of cs_sysz"] [:: std :: mem :: align_of :: < cs_sysz > () - 8usize] ; ["Offset of field: cs_sysz::cc"] [:: std :: mem :: offset_of ! (cs_sysz , cc) - 0usize] ; ["Offset of field: cs_sysz::op_count"] [:: std :: mem :: offset_of ! (cs_sysz , op_count) - 4usize] ; ["Offset of field: cs_sysz::operands"] [:: std :: mem :: offset_of ! (cs_sysz , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SystemZ instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn { SYSZ_INS_INVALID = 0 , SYSZ_INS_A = 1 , SYSZ_INS_ADB = 2 , SYSZ_INS_ADBR = 3 , SYSZ_INS_AEB = 4 , SYSZ_INS_AEBR = 5 , SYSZ_INS_AFI = 6 , SYSZ_INS_AG = 7 , SYSZ_INS_AGF = 8 , SYSZ_INS_AGFI = 9 , SYSZ_INS_AGFR = 10 , SYSZ_INS_AGHI = 11 , SYSZ_INS_AGHIK = 12 , SYSZ_INS_AGR = 13 , SYSZ_INS_AGRK = 14 , SYSZ_INS_AGSI = 15 , SYSZ_INS_AH = 16 , SYSZ_INS_AHI = 17 , SYSZ_INS_AHIK = 18 , SYSZ_INS_AHY = 19 , SYSZ_INS_AIH = 20 , SYSZ_INS_AL = 21 , SYSZ_INS_ALC = 22 , SYSZ_INS_ALCG = 23 , SYSZ_INS_ALCGR = 24 , SYSZ_INS_ALCR = 25 , SYSZ_INS_ALFI = 26 , SYSZ_INS_ALG = 27 , SYSZ_INS_ALGF = 28 , SYSZ_INS_ALGFI = 29 , SYSZ_INS_ALGFR = 30 , SYSZ_INS_ALGHSIK = 31 , SYSZ_INS_ALGR = 32 , SYSZ_INS_ALGRK = 33 , SYSZ_INS_ALHSIK = 34 , SYSZ_INS_ALR = 35 , SYSZ_INS_ALRK = 36 , SYSZ_INS_ALY = 37 , SYSZ_INS_AR = 38 , SYSZ_INS_ARK = 39 , SYSZ_INS_ASI = 40 , SYSZ_INS_AXBR = 41 , SYSZ_INS_AY = 42 , SYSZ_INS_BCR = 43 , SYSZ_INS_BRC = 44 , SYSZ_INS_BRCL = 45 , SYSZ_INS_CGIJ = 46 , SYSZ_INS_CGRJ = 47 , SYSZ_INS_CIJ = 48 , SYSZ_INS_CLGIJ = 49 , SYSZ_INS_CLGRJ = 50 , SYSZ_INS_CLIJ = 51 , SYSZ_INS_CLRJ = 52 , SYSZ_INS_CRJ = 53 , SYSZ_INS_BER = 54 , SYSZ_INS_JE = 55 , SYSZ_INS_JGE = 56 , SYSZ_INS_LOCE = 57 , SYSZ_INS_LOCGE = 58 , SYSZ_INS_LOCGRE = 59 , SYSZ_INS_LOCRE = 60 , SYSZ_INS_STOCE = 61 , SYSZ_INS_STOCGE = 62 , SYSZ_INS_BHR = 63 , SYSZ_INS_BHER = 64 , SYSZ_INS_JHE = 65 , SYSZ_INS_JGHE = 66 , SYSZ_INS_LOCHE = 67 , SYSZ_INS_LOCGHE = 68 , SYSZ_INS_LOCGRHE = 69 , SYSZ_INS_LOCRHE = 70 , SYSZ_INS_STOCHE = 71 , SYSZ_INS_STOCGHE = 72 , SYSZ_INS_JH = 73 , SYSZ_INS_JGH = 74 , SYSZ_INS_LOCH = 75 , SYSZ_INS_LOCGH = 76 , SYSZ_INS_LOCGRH = 77 , SYSZ_INS_LOCRH = 78 , SYSZ_INS_STOCH = 79 , SYSZ_INS_STOCGH = 80 , SYSZ_INS_CGIJNLH = 81 , SYSZ_INS_CGRJNLH = 82 , SYSZ_INS_CIJNLH = 83 , SYSZ_INS_CLGIJNLH = 84 , SYSZ_INS_CLGRJNLH = 85 , SYSZ_INS_CLIJNLH = 86 , SYSZ_INS_CLRJNLH = 87 , SYSZ_INS_CRJNLH = 88 , SYSZ_INS_CGIJE = 89 , SYSZ_INS_CGRJE = 90 , SYSZ_INS_CIJE = 91 , SYSZ_INS_CLGIJE = 92 , SYSZ_INS_CLGRJE = 93 , SYSZ_INS_CLIJE = 94 , SYSZ_INS_CLRJE = 95 , SYSZ_INS_CRJE = 96 , SYSZ_INS_CGIJNLE = 97 , SYSZ_INS_CGRJNLE = 98 , SYSZ_INS_CIJNLE = 99 , SYSZ_INS_CLGIJNLE = 100 , SYSZ_INS_CLGRJNLE = 101 , SYSZ_INS_CLIJNLE = 102 , SYSZ_INS_CLRJNLE = 103 , SYSZ_INS_CRJNLE = 104 , SYSZ_INS_CGIJH = 105 , SYSZ_INS_CGRJH = 106 , SYSZ_INS_CIJH = 107 , SYSZ_INS_CLGIJH = 108 , SYSZ_INS_CLGRJH = 109 , SYSZ_INS_CLIJH = 110 , SYSZ_INS_CLRJH = 111 , SYSZ_INS_CRJH = 112 , SYSZ_INS_CGIJNL = 113 , SYSZ_INS_CGRJNL = 114 , SYSZ_INS_CIJNL = 115 , SYSZ_INS_CLGIJNL = 116 , SYSZ_INS_CLGRJNL = 117 , SYSZ_INS_CLIJNL = 118 , SYSZ_INS_CLRJNL = 119 , SYSZ_INS_CRJNL = 120 , SYSZ_INS_CGIJHE = 121 , SYSZ_INS_CGRJHE = 122 , SYSZ_INS_CIJHE = 123 , SYSZ_INS_CLGIJHE = 124 , SYSZ_INS_CLGRJHE = 125 , SYSZ_INS_CLIJHE = 126 , SYSZ_INS_CLRJHE = 127 , SYSZ_INS_CRJHE = 128 , SYSZ_INS_CGIJNHE = 129 , SYSZ_INS_CGRJNHE = 130 , SYSZ_INS_CIJNHE = 131 , SYSZ_INS_CLGIJNHE = 132 , SYSZ_INS_CLGRJNHE = 133 , SYSZ_INS_CLIJNHE = 134 , SYSZ_INS_CLRJNHE = 135 , SYSZ_INS_CRJNHE = 136 , SYSZ_INS_CGIJL = 137 , SYSZ_INS_CGRJL = 138 , SYSZ_INS_CIJL = 139 , SYSZ_INS_CLGIJL = 140 , SYSZ_INS_CLGRJL = 141 , SYSZ_INS_CLIJL = 142 , SYSZ_INS_CLRJL = 143 , SYSZ_INS_CRJL = 144 , SYSZ_INS_CGIJNH = 145 , SYSZ_INS_CGRJNH = 146 , SYSZ_INS_CIJNH = 147 , SYSZ_INS_CLGIJNH = 148 , SYSZ_INS_CLGRJNH = 149 , SYSZ_INS_CLIJNH = 150 , SYSZ_INS_CLRJNH = 151 , SYSZ_INS_CRJNH = 152 , SYSZ_INS_CGIJLE = 153 , SYSZ_INS_CGRJLE = 154 , SYSZ_INS_CIJLE = 155 , SYSZ_INS_CLGIJLE = 156 , SYSZ_INS_CLGRJLE = 157 , SYSZ_INS_CLIJLE = 158 , SYSZ_INS_CLRJLE = 159 , SYSZ_INS_CRJLE = 160 , SYSZ_INS_CGIJNE = 161 , SYSZ_INS_CGRJNE = 162 , SYSZ_INS_CIJNE = 163 , SYSZ_INS_CLGIJNE = 164 , SYSZ_INS_CLGRJNE = 165 , SYSZ_INS_CLIJNE = 166 , SYSZ_INS_CLRJNE = 167 , SYSZ_INS_CRJNE = 168 , SYSZ_INS_CGIJLH = 169 , SYSZ_INS_CGRJLH = 170 , SYSZ_INS_CIJLH = 171 , SYSZ_INS_CLGIJLH = 172 , SYSZ_INS_CLGRJLH = 173 , SYSZ_INS_CLIJLH = 174 , SYSZ_INS_CLRJLH = 175 , SYSZ_INS_CRJLH = 176 , SYSZ_INS_BLR = 177 , SYSZ_INS_BLER = 178 , SYSZ_INS_JLE = 179 , SYSZ_INS_JGLE = 180 , SYSZ_INS_LOCLE = 181 , SYSZ_INS_LOCGLE = 182 , SYSZ_INS_LOCGRLE = 183 , SYSZ_INS_LOCRLE = 184 , SYSZ_INS_STOCLE = 185 , SYSZ_INS_STOCGLE = 186 , SYSZ_INS_BLHR = 187 , SYSZ_INS_JLH = 188 , SYSZ_INS_JGLH = 189 , SYSZ_INS_LOCLH = 190 , SYSZ_INS_LOCGLH = 191 , SYSZ_INS_LOCGRLH = 192 , SYSZ_INS_LOCRLH = 193 , SYSZ_INS_STOCLH = 194 , SYSZ_INS_STOCGLH = 195 , SYSZ_INS_JL = 196 , SYSZ_INS_JGL = 197 , SYSZ_INS_LOCL = 198 , SYSZ_INS_LOCGL = 199 , SYSZ_INS_LOCGRL = 200 , SYSZ_INS_LOCRL = 201 , SYSZ_INS_LOC = 202 , SYSZ_INS_LOCG = 203 , SYSZ_INS_LOCGR = 204 , SYSZ_INS_LOCR = 205 , SYSZ_INS_STOCL = 206 , SYSZ_INS_STOCGL = 207 , SYSZ_INS_BNER = 208 , SYSZ_INS_JNE = 209 , SYSZ_INS_JGNE = 210 , SYSZ_INS_LOCNE = 211 , SYSZ_INS_LOCGNE = 212 , SYSZ_INS_LOCGRNE = 213 , SYSZ_INS_LOCRNE = 214 , SYSZ_INS_STOCNE = 215 , SYSZ_INS_STOCGNE = 216 , SYSZ_INS_BNHR = 217 , SYSZ_INS_BNHER = 218 , SYSZ_INS_JNHE = 219 , SYSZ_INS_JGNHE = 220 , SYSZ_INS_LOCNHE = 221 , SYSZ_INS_LOCGNHE = 222 , SYSZ_INS_LOCGRNHE = 223 , SYSZ_INS_LOCRNHE = 224 , SYSZ_INS_STOCNHE = 225 , SYSZ_INS_STOCGNHE = 226 , SYSZ_INS_JNH = 227 , SYSZ_INS_JGNH = 228 , SYSZ_INS_LOCNH = 229 , SYSZ_INS_LOCGNH = 230 , SYSZ_INS_LOCGRNH = 231 , SYSZ_INS_LOCRNH = 232 , SYSZ_INS_STOCNH = 233 , SYSZ_INS_STOCGNH = 234 , SYSZ_INS_BNLR = 235 , SYSZ_INS_BNLER = 236 , SYSZ_INS_JNLE = 237 , SYSZ_INS_JGNLE = 238 , SYSZ_INS_LOCNLE = 239 , SYSZ_INS_LOCGNLE = 240 , SYSZ_INS_LOCGRNLE = 241 , SYSZ_INS_LOCRNLE = 242 , SYSZ_INS_STOCNLE = 243 , SYSZ_INS_STOCGNLE = 244 , SYSZ_INS_BNLHR = 245 , SYSZ_INS_JNLH = 246 , SYSZ_INS_JGNLH = 247 , SYSZ_INS_LOCNLH = 248 , SYSZ_INS_LOCGNLH = 249 , SYSZ_INS_LOCGRNLH = 250 , SYSZ_INS_LOCRNLH = 251 , SYSZ_INS_STOCNLH = 252 , SYSZ_INS_STOCGNLH = 253 , SYSZ_INS_JNL = 254 , SYSZ_INS_JGNL = 255 , SYSZ_INS_LOCNL = 256 , SYSZ_INS_LOCGNL = 257 , SYSZ_INS_LOCGRNL = 258 , SYSZ_INS_LOCRNL = 259 , SYSZ_INS_STOCNL = 260 , SYSZ_INS_STOCGNL = 261 , SYSZ_INS_BNOR = 262 , SYSZ_INS_JNO = 263 , SYSZ_INS_JGNO = 264 , SYSZ_INS_LOCNO = 265 , SYSZ_INS_LOCGNO = 266 , SYSZ_INS_LOCGRNO = 267 , SYSZ_INS_LOCRNO = 268 , SYSZ_INS_STOCNO = 269 , SYSZ_INS_STOCGNO = 270 , SYSZ_INS_BOR = 271 , SYSZ_INS_JO = 272 , SYSZ_INS_JGO = 273 , SYSZ_INS_LOCO = 274 , SYSZ_INS_LOCGO = 275 , SYSZ_INS_LOCGRO = 276 , SYSZ_INS_LOCRO = 277 , SYSZ_INS_STOCO = 278 , SYSZ_INS_STOCGO = 279 , SYSZ_INS_STOC = 280 , SYSZ_INS_STOCG = 281 , SYSZ_INS_BASR = 282 , SYSZ_INS_BR = 283 , SYSZ_INS_BRAS = 284 , SYSZ_INS_BRASL = 285 , SYSZ_INS_J = 286 , SYSZ_INS_JG = 287 , SYSZ_INS_BRCT = 288 , SYSZ_INS_BRCTG = 289 , SYSZ_INS_C = 290 , SYSZ_INS_CDB = 291 , SYSZ_INS_CDBR = 292 , SYSZ_INS_CDFBR = 293 , SYSZ_INS_CDGBR = 294 , SYSZ_INS_CDLFBR = 295 , SYSZ_INS_CDLGBR = 296 , SYSZ_INS_CEB = 297 , SYSZ_INS_CEBR = 298 , SYSZ_INS_CEFBR = 299 , SYSZ_INS_CEGBR = 300 , SYSZ_INS_CELFBR = 301 , SYSZ_INS_CELGBR = 302 , SYSZ_INS_CFDBR = 303 , SYSZ_INS_CFEBR = 304 , SYSZ_INS_CFI = 305 , SYSZ_INS_CFXBR = 306 , SYSZ_INS_CG = 307 , SYSZ_INS_CGDBR = 308 , SYSZ_INS_CGEBR = 309 , SYSZ_INS_CGF = 310 , SYSZ_INS_CGFI = 311 , SYSZ_INS_CGFR = 312 , SYSZ_INS_CGFRL = 313 , SYSZ_INS_CGH = 314 , SYSZ_INS_CGHI = 315 , SYSZ_INS_CGHRL = 316 , SYSZ_INS_CGHSI = 317 , SYSZ_INS_CGR = 318 , SYSZ_INS_CGRL = 319 , SYSZ_INS_CGXBR = 320 , SYSZ_INS_CH = 321 , SYSZ_INS_CHF = 322 , SYSZ_INS_CHHSI = 323 , SYSZ_INS_CHI = 324 , SYSZ_INS_CHRL = 325 , SYSZ_INS_CHSI = 326 , SYSZ_INS_CHY = 327 , SYSZ_INS_CIH = 328 , SYSZ_INS_CL = 329 , SYSZ_INS_CLC = 330 , SYSZ_INS_CLFDBR = 331 , SYSZ_INS_CLFEBR = 332 , SYSZ_INS_CLFHSI = 333 , SYSZ_INS_CLFI = 334 , SYSZ_INS_CLFXBR = 335 , SYSZ_INS_CLG = 336 , SYSZ_INS_CLGDBR = 337 , SYSZ_INS_CLGEBR = 338 , SYSZ_INS_CLGF = 339 , SYSZ_INS_CLGFI = 340 , SYSZ_INS_CLGFR = 341 , SYSZ_INS_CLGFRL = 342 , SYSZ_INS_CLGHRL = 343 , SYSZ_INS_CLGHSI = 344 , SYSZ_INS_CLGR = 345 , SYSZ_INS_CLGRL = 346 , SYSZ_INS_CLGXBR = 347 , SYSZ_INS_CLHF = 348 , SYSZ_INS_CLHHSI = 349 , SYSZ_INS_CLHRL = 350 , SYSZ_INS_CLI = 351 , SYSZ_INS_CLIH = 352 , SYSZ_INS_CLIY = 353 , SYSZ_INS_CLR = 354 , SYSZ_INS_CLRL = 355 , SYSZ_INS_CLST = 356 , SYSZ_INS_CLY = 357 , SYSZ_INS_CPSDR = 358 , SYSZ_INS_CR = 359 , SYSZ_INS_CRL = 360 , SYSZ_INS_CS = 361 , SYSZ_INS_CSG = 362 , SYSZ_INS_CSY = 363 , SYSZ_INS_CXBR = 364 , SYSZ_INS_CXFBR = 365 , SYSZ_INS_CXGBR = 366 , SYSZ_INS_CXLFBR = 367 , SYSZ_INS_CXLGBR = 368 , SYSZ_INS_CY = 369 , SYSZ_INS_DDB = 370 , SYSZ_INS_DDBR = 371 , SYSZ_INS_DEB = 372 , SYSZ_INS_DEBR = 373 , SYSZ_INS_DL = 374 , SYSZ_INS_DLG = 375 , SYSZ_INS_DLGR = 376 , SYSZ_INS_DLR = 377 , SYSZ_INS_DSG = 378 , SYSZ_INS_DSGF = 379 , SYSZ_INS_DSGFR = 380 , SYSZ_INS_DSGR = 381 , SYSZ_INS_DXBR = 382 , SYSZ_INS_EAR = 383 , SYSZ_INS_FIDBR = 384 , SYSZ_INS_FIDBRA = 385 , SYSZ_INS_FIEBR = 386 , SYSZ_INS_FIEBRA = 387 , SYSZ_INS_FIXBR = 388 , SYSZ_INS_FIXBRA = 389 , SYSZ_INS_FLOGR = 390 , SYSZ_INS_IC = 391 , SYSZ_INS_ICY = 392 , SYSZ_INS_IIHF = 393 , SYSZ_INS_IIHH = 394 , SYSZ_INS_IIHL = 395 , SYSZ_INS_IILF = 396 , SYSZ_INS_IILH = 397 , SYSZ_INS_IILL = 398 , SYSZ_INS_IPM = 399 , SYSZ_INS_L = 400 , SYSZ_INS_LA = 401 , SYSZ_INS_LAA = 402 , SYSZ_INS_LAAG = 403 , SYSZ_INS_LAAL = 404 , SYSZ_INS_LAALG = 405 , SYSZ_INS_LAN = 406 , SYSZ_INS_LANG = 407 , SYSZ_INS_LAO = 408 , SYSZ_INS_LAOG = 409 , SYSZ_INS_LARL = 410 , SYSZ_INS_LAX = 411 , SYSZ_INS_LAXG = 412 , SYSZ_INS_LAY = 413 , SYSZ_INS_LB = 414 , SYSZ_INS_LBH = 415 , SYSZ_INS_LBR = 416 , SYSZ_INS_LCDBR = 417 , SYSZ_INS_LCEBR = 418 , SYSZ_INS_LCGFR = 419 , SYSZ_INS_LCGR = 420 , SYSZ_INS_LCR = 421 , SYSZ_INS_LCXBR = 422 , SYSZ_INS_LD = 423 , SYSZ_INS_LDEB = 424 , SYSZ_INS_LDEBR = 425 , SYSZ_INS_LDGR = 426 , SYSZ_INS_LDR = 427 , SYSZ_INS_LDXBR = 428 , SYSZ_INS_LDXBRA = 429 , SYSZ_INS_LDY = 430 , SYSZ_INS_LE = 431 , SYSZ_INS_LEDBR = 432 , SYSZ_INS_LEDBRA = 433 , SYSZ_INS_LER = 434 , SYSZ_INS_LEXBR = 435 , SYSZ_INS_LEXBRA = 436 , SYSZ_INS_LEY = 437 , SYSZ_INS_LFH = 438 , SYSZ_INS_LG = 439 , SYSZ_INS_LGB = 440 , SYSZ_INS_LGBR = 441 , SYSZ_INS_LGDR = 442 , SYSZ_INS_LGF = 443 , SYSZ_INS_LGFI = 444 , SYSZ_INS_LGFR = 445 , SYSZ_INS_LGFRL = 446 , SYSZ_INS_LGH = 447 , SYSZ_INS_LGHI = 448 , SYSZ_INS_LGHR = 449 , SYSZ_INS_LGHRL = 450 , SYSZ_INS_LGR = 451 , SYSZ_INS_LGRL = 452 , SYSZ_INS_LH = 453 , SYSZ_INS_LHH = 454 , SYSZ_INS_LHI = 455 , SYSZ_INS_LHR = 456 , SYSZ_INS_LHRL = 457 , SYSZ_INS_LHY = 458 , SYSZ_INS_LLC = 459 , SYSZ_INS_LLCH = 460 , SYSZ_INS_LLCR = 461 , SYSZ_INS_LLGC = 462 , SYSZ_INS_LLGCR = 463 , SYSZ_INS_LLGF = 464 , SYSZ_INS_LLGFR = 465 , SYSZ_INS_LLGFRL = 466 , SYSZ_INS_LLGH = 467 , SYSZ_INS_LLGHR = 468 , SYSZ_INS_LLGHRL = 469 , SYSZ_INS_LLH = 470 , SYSZ_INS_LLHH = 471 , SYSZ_INS_LLHR = 472 , SYSZ_INS_LLHRL = 473 , SYSZ_INS_LLIHF = 474 , SYSZ_INS_LLIHH = 475 , SYSZ_INS_LLIHL = 476 , SYSZ_INS_LLILF = 477 , SYSZ_INS_LLILH = 478 , SYSZ_INS_LLILL = 479 , SYSZ_INS_LMG = 480 , SYSZ_INS_LNDBR = 481 , SYSZ_INS_LNEBR = 482 , SYSZ_INS_LNGFR = 483 , SYSZ_INS_LNGR = 484 , SYSZ_INS_LNR = 485 , SYSZ_INS_LNXBR = 486 , SYSZ_INS_LPDBR = 487 , SYSZ_INS_LPEBR = 488 , SYSZ_INS_LPGFR = 489 , SYSZ_INS_LPGR = 490 , SYSZ_INS_LPR = 491 , SYSZ_INS_LPXBR = 492 , SYSZ_INS_LR = 493 , SYSZ_INS_LRL = 494 , SYSZ_INS_LRV = 495 , SYSZ_INS_LRVG = 496 , SYSZ_INS_LRVGR = 497 , SYSZ_INS_LRVR = 498 , SYSZ_INS_LT = 499 , SYSZ_INS_LTDBR = 500 , SYSZ_INS_LTEBR = 501 , SYSZ_INS_LTG = 502 , SYSZ_INS_LTGF = 503 , SYSZ_INS_LTGFR = 504 , SYSZ_INS_LTGR = 505 , SYSZ_INS_LTR = 506 , SYSZ_INS_LTXBR = 507 , SYSZ_INS_LXDB = 508 , SYSZ_INS_LXDBR = 509 , SYSZ_INS_LXEB = 510 , SYSZ_INS_LXEBR = 511 , SYSZ_INS_LXR = 512 , SYSZ_INS_LY = 513 , SYSZ_INS_LZDR = 514 , SYSZ_INS_LZER = 515 , SYSZ_INS_LZXR = 516 , SYSZ_INS_MADB = 517 , SYSZ_INS_MADBR = 518 , SYSZ_INS_MAEB = 519 , SYSZ_INS_MAEBR = 520 , SYSZ_INS_MDB = 521 , SYSZ_INS_MDBR = 522 , SYSZ_INS_MDEB = 523 , SYSZ_INS_MDEBR = 524 , SYSZ_INS_MEEB = 525 , SYSZ_INS_MEEBR = 526 , SYSZ_INS_MGHI = 527 , SYSZ_INS_MH = 528 , SYSZ_INS_MHI = 529 , SYSZ_INS_MHY = 530 , SYSZ_INS_MLG = 531 , SYSZ_INS_MLGR = 532 , SYSZ_INS_MS = 533 , SYSZ_INS_MSDB = 534 , SYSZ_INS_MSDBR = 535 , SYSZ_INS_MSEB = 536 , SYSZ_INS_MSEBR = 537 , SYSZ_INS_MSFI = 538 , SYSZ_INS_MSG = 539 , SYSZ_INS_MSGF = 540 , SYSZ_INS_MSGFI = 541 , SYSZ_INS_MSGFR = 542 , SYSZ_INS_MSGR = 543 , SYSZ_INS_MSR = 544 , SYSZ_INS_MSY = 545 , SYSZ_INS_MVC = 546 , SYSZ_INS_MVGHI = 547 , SYSZ_INS_MVHHI = 548 , SYSZ_INS_MVHI = 549 , SYSZ_INS_MVI = 550 , SYSZ_INS_MVIY = 551 , SYSZ_INS_MVST = 552 , SYSZ_INS_MXBR = 553 , SYSZ_INS_MXDB = 554 , SYSZ_INS_MXDBR = 555 , SYSZ_INS_N = 556 , SYSZ_INS_NC = 557 , SYSZ_INS_NG = 558 , SYSZ_INS_NGR = 559 , SYSZ_INS_NGRK = 560 , SYSZ_INS_NI = 561 , SYSZ_INS_NIHF = 562 , SYSZ_INS_NIHH = 563 , SYSZ_INS_NIHL = 564 , SYSZ_INS_NILF = 565 , SYSZ_INS_NILH = 566 , SYSZ_INS_NILL = 567 , SYSZ_INS_NIY = 568 , SYSZ_INS_NR = 569 , SYSZ_INS_NRK = 570 , SYSZ_INS_NY = 571 , SYSZ_INS_O = 572 , SYSZ_INS_OC = 573 , SYSZ_INS_OG = 574 , SYSZ_INS_OGR = 575 , SYSZ_INS_OGRK = 576 , SYSZ_INS_OI = 577 , SYSZ_INS_OIHF = 578 , SYSZ_INS_OIHH = 579 , SYSZ_INS_OIHL = 580 , SYSZ_INS_OILF = 581 , SYSZ_INS_OILH = 582 , SYSZ_INS_OILL = 583 , SYSZ_INS_OIY = 584 , SYSZ_INS_OR = 585 , SYSZ_INS_ORK = 586 , SYSZ_INS_OY = 587 , SYSZ_INS_PFD = 588 , SYSZ_INS_PFDRL = 589 , SYSZ_INS_RISBG = 590 , SYSZ_INS_RISBHG = 591 , SYSZ_INS_RISBLG = 592 , SYSZ_INS_RLL = 593 , SYSZ_INS_RLLG = 594 , SYSZ_INS_RNSBG = 595 , SYSZ_INS_ROSBG = 596 , SYSZ_INS_RXSBG = 597 , SYSZ_INS_S = 598 , SYSZ_INS_SDB = 599 , SYSZ_INS_SDBR = 600 , SYSZ_INS_SEB = 601 , SYSZ_INS_SEBR = 602 , SYSZ_INS_SG = 603 , SYSZ_INS_SGF = 604 , SYSZ_INS_SGFR = 605 , SYSZ_INS_SGR = 606 , SYSZ_INS_SGRK = 607 , SYSZ_INS_SH = 608 , SYSZ_INS_SHY = 609 , SYSZ_INS_SL = 610 , SYSZ_INS_SLB = 611 , SYSZ_INS_SLBG = 612 , SYSZ_INS_SLBR = 613 , SYSZ_INS_SLFI = 614 , SYSZ_INS_SLG = 615 , SYSZ_INS_SLBGR = 616 , SYSZ_INS_SLGF = 617 , SYSZ_INS_SLGFI = 618 , SYSZ_INS_SLGFR = 619 , SYSZ_INS_SLGR = 620 , SYSZ_INS_SLGRK = 621 , SYSZ_INS_SLL = 622 , SYSZ_INS_SLLG = 623 , SYSZ_INS_SLLK = 624 , SYSZ_INS_SLR = 625 , SYSZ_INS_SLRK = 626 , SYSZ_INS_SLY = 627 , SYSZ_INS_SQDB = 628 , SYSZ_INS_SQDBR = 629 , SYSZ_INS_SQEB = 630 , SYSZ_INS_SQEBR = 631 , SYSZ_INS_SQXBR = 632 , SYSZ_INS_SR = 633 , SYSZ_INS_SRA = 634 , SYSZ_INS_SRAG = 635 , SYSZ_INS_SRAK = 636 , SYSZ_INS_SRK = 637 , SYSZ_INS_SRL = 638 , SYSZ_INS_SRLG = 639 , SYSZ_INS_SRLK = 640 , SYSZ_INS_SRST = 641 , SYSZ_INS_ST = 642 , SYSZ_INS_STC = 643 , SYSZ_INS_STCH = 644 , SYSZ_INS_STCY = 645 , SYSZ_INS_STD = 646 , SYSZ_INS_STDY = 647 , SYSZ_INS_STE = 648 , SYSZ_INS_STEY = 649 , SYSZ_INS_STFH = 650 , SYSZ_INS_STG = 651 , SYSZ_INS_STGRL = 652 , SYSZ_INS_STH = 653 , SYSZ_INS_STHH = 654 , SYSZ_INS_STHRL = 655 , SYSZ_INS_STHY = 656 , SYSZ_INS_STMG = 657 , SYSZ_INS_STRL = 658 , SYSZ_INS_STRV = 659 , SYSZ_INS_STRVG = 660 , SYSZ_INS_STY = 661 , SYSZ_INS_SXBR = 662 , SYSZ_INS_SY = 663 , SYSZ_INS_TM = 664 , SYSZ_INS_TMHH = 665 , SYSZ_INS_TMHL = 666 , SYSZ_INS_TMLH = 667 , SYSZ_INS_TMLL = 668 , SYSZ_INS_TMY = 669 , SYSZ_INS_X = 670 , SYSZ_INS_XC = 671 , SYSZ_INS_XG = 672 , SYSZ_INS_XGR = 673 , SYSZ_INS_XGRK = 674 , SYSZ_INS_XI = 675 , SYSZ_INS_XIHF = 676 , SYSZ_INS_XILF = 677 , SYSZ_INS_XIY = 678 , SYSZ_INS_XR = 679 , SYSZ_INS_XRK = 680 , SYSZ_INS_XY = 681 , SYSZ_INS_AD = 682 , SYSZ_INS_ADR = 683 , SYSZ_INS_ADTR = 684 , SYSZ_INS_ADTRA = 685 , SYSZ_INS_AE = 686 , SYSZ_INS_AER = 687 , SYSZ_INS_AGH = 688 , SYSZ_INS_AHHHR = 689 , SYSZ_INS_AHHLR = 690 , SYSZ_INS_ALGSI = 691 , SYSZ_INS_ALHHHR = 692 , SYSZ_INS_ALHHLR = 693 , SYSZ_INS_ALSI = 694 , SYSZ_INS_ALSIH = 695 , SYSZ_INS_ALSIHN = 696 , SYSZ_INS_AP = 697 , SYSZ_INS_AU = 698 , SYSZ_INS_AUR = 699 , SYSZ_INS_AW = 700 , SYSZ_INS_AWR = 701 , SYSZ_INS_AXR = 702 , SYSZ_INS_AXTR = 703 , SYSZ_INS_AXTRA = 704 , SYSZ_INS_B = 705 , SYSZ_INS_BAKR = 706 , SYSZ_INS_BAL = 707 , SYSZ_INS_BALR = 708 , SYSZ_INS_BAS = 709 , SYSZ_INS_BASSM = 710 , SYSZ_INS_BC = 711 , SYSZ_INS_BCT = 712 , SYSZ_INS_BCTG = 713 , SYSZ_INS_BCTGR = 714 , SYSZ_INS_BCTR = 715 , SYSZ_INS_BE = 716 , SYSZ_INS_BH = 717 , SYSZ_INS_BHE = 718 , SYSZ_INS_BI = 719 , SYSZ_INS_BIC = 720 , SYSZ_INS_BIE = 721 , SYSZ_INS_BIH = 722 , SYSZ_INS_BIHE = 723 , SYSZ_INS_BIL = 724 , SYSZ_INS_BILE = 725 , SYSZ_INS_BILH = 726 , SYSZ_INS_BIM = 727 , SYSZ_INS_BINE = 728 , SYSZ_INS_BINH = 729 , SYSZ_INS_BINHE = 730 , SYSZ_INS_BINL = 731 , SYSZ_INS_BINLE = 732 , SYSZ_INS_BINLH = 733 , SYSZ_INS_BINM = 734 , SYSZ_INS_BINO = 735 , SYSZ_INS_BINP = 736 , SYSZ_INS_BINZ = 737 , SYSZ_INS_BIO = 738 , SYSZ_INS_BIP = 739 , SYSZ_INS_BIZ = 740 , SYSZ_INS_BL = 741 , SYSZ_INS_BLE = 742 , SYSZ_INS_BLH = 743 , SYSZ_INS_BM = 744 , SYSZ_INS_BMR = 745 , SYSZ_INS_BNE = 746 , SYSZ_INS_BNH = 747 , SYSZ_INS_BNHE = 748 , SYSZ_INS_BNL = 749 , SYSZ_INS_BNLE = 750 , SYSZ_INS_BNLH = 751 , SYSZ_INS_BNM = 752 , SYSZ_INS_BNMR = 753 , SYSZ_INS_BNO = 754 , SYSZ_INS_BNP = 755 , SYSZ_INS_BNPR = 756 , SYSZ_INS_BNZ = 757 , SYSZ_INS_BNZR = 758 , SYSZ_INS_BO = 759 , SYSZ_INS_BP = 760 , SYSZ_INS_BPP = 761 , SYSZ_INS_BPR = 762 , SYSZ_INS_BPRP = 763 , SYSZ_INS_BRCTH = 764 , SYSZ_INS_BRXH = 765 , SYSZ_INS_BRXHG = 766 , SYSZ_INS_BRXLE = 767 , SYSZ_INS_BRXLG = 768 , SYSZ_INS_BSA = 769 , SYSZ_INS_BSG = 770 , SYSZ_INS_BSM = 771 , SYSZ_INS_BXH = 772 , SYSZ_INS_BXHG = 773 , SYSZ_INS_BXLE = 774 , SYSZ_INS_BXLEG = 775 , SYSZ_INS_BZ = 776 , SYSZ_INS_BZR = 777 , SYSZ_INS_CD = 778 , SYSZ_INS_CDFBRA = 779 , SYSZ_INS_CDFR = 780 , SYSZ_INS_CDFTR = 781 , SYSZ_INS_CDGBRA = 782 , SYSZ_INS_CDGR = 783 , SYSZ_INS_CDGTR = 784 , SYSZ_INS_CDGTRA = 785 , SYSZ_INS_CDLFTR = 786 , SYSZ_INS_CDLGTR = 787 , SYSZ_INS_CDPT = 788 , SYSZ_INS_CDR = 789 , SYSZ_INS_CDS = 790 , SYSZ_INS_CDSG = 791 , SYSZ_INS_CDSTR = 792 , SYSZ_INS_CDSY = 793 , SYSZ_INS_CDTR = 794 , SYSZ_INS_CDUTR = 795 , SYSZ_INS_CDZT = 796 , SYSZ_INS_CE = 797 , SYSZ_INS_CEDTR = 798 , SYSZ_INS_CEFBRA = 799 , SYSZ_INS_CEFR = 800 , SYSZ_INS_CEGBRA = 801 , SYSZ_INS_CEGR = 802 , SYSZ_INS_CER = 803 , SYSZ_INS_CEXTR = 804 , SYSZ_INS_CFC = 805 , SYSZ_INS_CFDBRA = 806 , SYSZ_INS_CFDR = 807 , SYSZ_INS_CFDTR = 808 , SYSZ_INS_CFEBRA = 809 , SYSZ_INS_CFER = 810 , SYSZ_INS_CFXBRA = 811 , SYSZ_INS_CFXR = 812 , SYSZ_INS_CFXTR = 813 , SYSZ_INS_CGDBRA = 814 , SYSZ_INS_CGDR = 815 , SYSZ_INS_CGDTR = 816 , SYSZ_INS_CGDTRA = 817 , SYSZ_INS_CGEBRA = 818 , SYSZ_INS_CGER = 819 , SYSZ_INS_CGIB = 820 , SYSZ_INS_CGIBE = 821 , SYSZ_INS_CGIBH = 822 , SYSZ_INS_CGIBHE = 823 , SYSZ_INS_CGIBL = 824 , SYSZ_INS_CGIBLE = 825 , SYSZ_INS_CGIBLH = 826 , SYSZ_INS_CGIBNE = 827 , SYSZ_INS_CGIBNH = 828 , SYSZ_INS_CGIBNHE = 829 , SYSZ_INS_CGIBNL = 830 , SYSZ_INS_CGIBNLE = 831 , SYSZ_INS_CGIBNLH = 832 , SYSZ_INS_CGIT = 833 , SYSZ_INS_CGITE = 834 , SYSZ_INS_CGITH = 835 , SYSZ_INS_CGITHE = 836 , SYSZ_INS_CGITL = 837 , SYSZ_INS_CGITLE = 838 , SYSZ_INS_CGITLH = 839 , SYSZ_INS_CGITNE = 840 , SYSZ_INS_CGITNH = 841 , SYSZ_INS_CGITNHE = 842 , SYSZ_INS_CGITNL = 843 , SYSZ_INS_CGITNLE = 844 , SYSZ_INS_CGITNLH = 845 , SYSZ_INS_CGRB = 846 , SYSZ_INS_CGRBE = 847 , SYSZ_INS_CGRBH = 848 , SYSZ_INS_CGRBHE = 849 , SYSZ_INS_CGRBL = 850 , SYSZ_INS_CGRBLE = 851 , SYSZ_INS_CGRBLH = 852 , SYSZ_INS_CGRBNE = 853 , SYSZ_INS_CGRBNH = 854 , SYSZ_INS_CGRBNHE = 855 , SYSZ_INS_CGRBNL = 856 , SYSZ_INS_CGRBNLE = 857 , SYSZ_INS_CGRBNLH = 858 , SYSZ_INS_CGRT = 859 , SYSZ_INS_CGRTE = 860 , SYSZ_INS_CGRTH = 861 , SYSZ_INS_CGRTHE = 862 , SYSZ_INS_CGRTL = 863 , SYSZ_INS_CGRTLE = 864 , SYSZ_INS_CGRTLH = 865 , SYSZ_INS_CGRTNE = 866 , SYSZ_INS_CGRTNH = 867 , SYSZ_INS_CGRTNHE = 868 , SYSZ_INS_CGRTNL = 869 , SYSZ_INS_CGRTNLE = 870 , SYSZ_INS_CGRTNLH = 871 , SYSZ_INS_CGXBRA = 872 , SYSZ_INS_CGXR = 873 , SYSZ_INS_CGXTR = 874 , SYSZ_INS_CGXTRA = 875 , SYSZ_INS_CHHR = 876 , SYSZ_INS_CHLR = 877 , SYSZ_INS_CIB = 878 , SYSZ_INS_CIBE = 879 , SYSZ_INS_CIBH = 880 , SYSZ_INS_CIBHE = 881 , SYSZ_INS_CIBL = 882 , SYSZ_INS_CIBLE = 883 , SYSZ_INS_CIBLH = 884 , SYSZ_INS_CIBNE = 885 , SYSZ_INS_CIBNH = 886 , SYSZ_INS_CIBNHE = 887 , SYSZ_INS_CIBNL = 888 , SYSZ_INS_CIBNLE = 889 , SYSZ_INS_CIBNLH = 890 , SYSZ_INS_CIT = 891 , SYSZ_INS_CITE = 892 , SYSZ_INS_CITH = 893 , SYSZ_INS_CITHE = 894 , SYSZ_INS_CITL = 895 , SYSZ_INS_CITLE = 896 , SYSZ_INS_CITLH = 897 , SYSZ_INS_CITNE = 898 , SYSZ_INS_CITNH = 899 , SYSZ_INS_CITNHE = 900 , SYSZ_INS_CITNL = 901 , SYSZ_INS_CITNLE = 902 , SYSZ_INS_CITNLH = 903 , SYSZ_INS_CKSM = 904 , SYSZ_INS_CLCL = 905 , SYSZ_INS_CLCLE = 906 , SYSZ_INS_CLCLU = 907 , SYSZ_INS_CLFDTR = 908 , SYSZ_INS_CLFIT = 909 , SYSZ_INS_CLFITE = 910 , SYSZ_INS_CLFITH = 911 , SYSZ_INS_CLFITHE = 912 , SYSZ_INS_CLFITL = 913 , SYSZ_INS_CLFITLE = 914 , SYSZ_INS_CLFITLH = 915 , SYSZ_INS_CLFITNE = 916 , SYSZ_INS_CLFITNH = 917 , SYSZ_INS_CLFITNHE = 918 , SYSZ_INS_CLFITNL = 919 , SYSZ_INS_CLFITNLE = 920 , SYSZ_INS_CLFITNLH = 921 , SYSZ_INS_CLFXTR = 922 , SYSZ_INS_CLGDTR = 923 , SYSZ_INS_CLGIB = 924 , SYSZ_INS_CLGIBE = 925 , SYSZ_INS_CLGIBH = 926 , SYSZ_INS_CLGIBHE = 927 , SYSZ_INS_CLGIBL = 928 , SYSZ_INS_CLGIBLE = 929 , SYSZ_INS_CLGIBLH = 930 , SYSZ_INS_CLGIBNE = 931 , SYSZ_INS_CLGIBNH = 932 , SYSZ_INS_CLGIBNHE = 933 , SYSZ_INS_CLGIBNL = 934 , SYSZ_INS_CLGIBNLE = 935 , SYSZ_INS_CLGIBNLH = 936 , SYSZ_INS_CLGIT = 937 , SYSZ_INS_CLGITE = 938 , SYSZ_INS_CLGITH = 939 , SYSZ_INS_CLGITHE = 940 , SYSZ_INS_CLGITL = 941 , SYSZ_INS_CLGITLE = 942 , SYSZ_INS_CLGITLH = 943 , SYSZ_INS_CLGITNE = 944 , SYSZ_INS_CLGITNH = 945 , SYSZ_INS_CLGITNHE = 946 , SYSZ_INS_CLGITNL = 947 , SYSZ_INS_CLGITNLE = 948 , SYSZ_INS_CLGITNLH = 949 , SYSZ_INS_CLGRB = 950 , SYSZ_INS_CLGRBE = 951 , SYSZ_INS_CLGRBH = 952 , SYSZ_INS_CLGRBHE = 953 , SYSZ_INS_CLGRBL = 954 , SYSZ_INS_CLGRBLE = 955 , SYSZ_INS_CLGRBLH = 956 , SYSZ_INS_CLGRBNE = 957 , SYSZ_INS_CLGRBNH = 958 , SYSZ_INS_CLGRBNHE = 959 , SYSZ_INS_CLGRBNL = 960 , SYSZ_INS_CLGRBNLE = 961 , SYSZ_INS_CLGRBNLH = 962 , SYSZ_INS_CLGRT = 963 , SYSZ_INS_CLGRTE = 964 , SYSZ_INS_CLGRTH = 965 , SYSZ_INS_CLGRTHE = 966 , SYSZ_INS_CLGRTL = 967 , SYSZ_INS_CLGRTLE = 968 , SYSZ_INS_CLGRTLH = 969 , SYSZ_INS_CLGRTNE = 970 , SYSZ_INS_CLGRTNH = 971 , SYSZ_INS_CLGRTNHE = 972 , SYSZ_INS_CLGRTNL = 973 , SYSZ_INS_CLGRTNLE = 974 , SYSZ_INS_CLGRTNLH = 975 , SYSZ_INS_CLGT = 976 , SYSZ_INS_CLGTE = 977 , SYSZ_INS_CLGTH = 978 , SYSZ_INS_CLGTHE = 979 , SYSZ_INS_CLGTL = 980 , SYSZ_INS_CLGTLE = 981 , SYSZ_INS_CLGTLH = 982 , SYSZ_INS_CLGTNE = 983 , SYSZ_INS_CLGTNH = 984 , SYSZ_INS_CLGTNHE = 985 , SYSZ_INS_CLGTNL = 986 , SYSZ_INS_CLGTNLE = 987 , SYSZ_INS_CLGTNLH = 988 , SYSZ_INS_CLGXTR = 989 , SYSZ_INS_CLHHR = 990 , SYSZ_INS_CLHLR = 991 , SYSZ_INS_CLIB = 992 , SYSZ_INS_CLIBE = 993 , SYSZ_INS_CLIBH = 994 , SYSZ_INS_CLIBHE = 995 , SYSZ_INS_CLIBL = 996 , SYSZ_INS_CLIBLE = 997 , SYSZ_INS_CLIBLH = 998 , SYSZ_INS_CLIBNE = 999 , SYSZ_INS_CLIBNH = 1000 , SYSZ_INS_CLIBNHE = 1001 , SYSZ_INS_CLIBNL = 1002 , SYSZ_INS_CLIBNLE = 1003 , SYSZ_INS_CLIBNLH = 1004 , SYSZ_INS_CLM = 1005 , SYSZ_INS_CLMH = 1006 , SYSZ_INS_CLMY = 1007 , SYSZ_INS_CLRB = 1008 , SYSZ_INS_CLRBE = 1009 , SYSZ_INS_CLRBH = 1010 , SYSZ_INS_CLRBHE = 1011 , SYSZ_INS_CLRBL = 1012 , SYSZ_INS_CLRBLE = 1013 , SYSZ_INS_CLRBLH = 1014 , SYSZ_INS_CLRBNE = 1015 , SYSZ_INS_CLRBNH = 1016 , SYSZ_INS_CLRBNHE = 1017 , SYSZ_INS_CLRBNL = 1018 , SYSZ_INS_CLRBNLE = 1019 , SYSZ_INS_CLRBNLH = 1020 , SYSZ_INS_CLRT = 1021 , SYSZ_INS_CLRTE = 1022 , SYSZ_INS_CLRTH = 1023 , SYSZ_INS_CLRTHE = 1024 , SYSZ_INS_CLRTL = 1025 , SYSZ_INS_CLRTLE = 1026 , SYSZ_INS_CLRTLH = 1027 , SYSZ_INS_CLRTNE = 1028 , SYSZ_INS_CLRTNH = 1029 , SYSZ_INS_CLRTNHE = 1030 , SYSZ_INS_CLRTNL = 1031 , SYSZ_INS_CLRTNLE = 1032 , SYSZ_INS_CLRTNLH = 1033 , SYSZ_INS_CLT = 1034 , SYSZ_INS_CLTE = 1035 , SYSZ_INS_CLTH = 1036 , SYSZ_INS_CLTHE = 1037 , SYSZ_INS_CLTL = 1038 , SYSZ_INS_CLTLE = 1039 , SYSZ_INS_CLTLH = 1040 , SYSZ_INS_CLTNE = 1041 , SYSZ_INS_CLTNH = 1042 , SYSZ_INS_CLTNHE = 1043 , SYSZ_INS_CLTNL = 1044 , SYSZ_INS_CLTNLE = 1045 , SYSZ_INS_CLTNLH = 1046 , SYSZ_INS_CMPSC = 1047 , SYSZ_INS_CP = 1048 , SYSZ_INS_CPDT = 1049 , SYSZ_INS_CPXT = 1050 , SYSZ_INS_CPYA = 1051 , SYSZ_INS_CRB = 1052 , SYSZ_INS_CRBE = 1053 , SYSZ_INS_CRBH = 1054 , SYSZ_INS_CRBHE = 1055 , SYSZ_INS_CRBL = 1056 , SYSZ_INS_CRBLE = 1057 , SYSZ_INS_CRBLH = 1058 , SYSZ_INS_CRBNE = 1059 , SYSZ_INS_CRBNH = 1060 , SYSZ_INS_CRBNHE = 1061 , SYSZ_INS_CRBNL = 1062 , SYSZ_INS_CRBNLE = 1063 , SYSZ_INS_CRBNLH = 1064 , SYSZ_INS_CRDTE = 1065 , SYSZ_INS_CRT = 1066 , SYSZ_INS_CRTE = 1067 , SYSZ_INS_CRTH = 1068 , SYSZ_INS_CRTHE = 1069 , SYSZ_INS_CRTL = 1070 , SYSZ_INS_CRTLE = 1071 , SYSZ_INS_CRTLH = 1072 , SYSZ_INS_CRTNE = 1073 , SYSZ_INS_CRTNH = 1074 , SYSZ_INS_CRTNHE = 1075 , SYSZ_INS_CRTNL = 1076 , SYSZ_INS_CRTNLE = 1077 , SYSZ_INS_CRTNLH = 1078 , SYSZ_INS_CSCH = 1079 , SYSZ_INS_CSDTR = 1080 , SYSZ_INS_CSP = 1081 , SYSZ_INS_CSPG = 1082 , SYSZ_INS_CSST = 1083 , SYSZ_INS_CSXTR = 1084 , SYSZ_INS_CU12 = 1085 , SYSZ_INS_CU14 = 1086 , SYSZ_INS_CU21 = 1087 , SYSZ_INS_CU24 = 1088 , SYSZ_INS_CU41 = 1089 , SYSZ_INS_CU42 = 1090 , SYSZ_INS_CUDTR = 1091 , SYSZ_INS_CUSE = 1092 , SYSZ_INS_CUTFU = 1093 , SYSZ_INS_CUUTF = 1094 , SYSZ_INS_CUXTR = 1095 , SYSZ_INS_CVB = 1096 , SYSZ_INS_CVBG = 1097 , SYSZ_INS_CVBY = 1098 , SYSZ_INS_CVD = 1099 , SYSZ_INS_CVDG = 1100 , SYSZ_INS_CVDY = 1101 , SYSZ_INS_CXFBRA = 1102 , SYSZ_INS_CXFR = 1103 , SYSZ_INS_CXFTR = 1104 , SYSZ_INS_CXGBRA = 1105 , SYSZ_INS_CXGR = 1106 , SYSZ_INS_CXGTR = 1107 , SYSZ_INS_CXGTRA = 1108 , SYSZ_INS_CXLFTR = 1109 , SYSZ_INS_CXLGTR = 1110 , SYSZ_INS_CXPT = 1111 , SYSZ_INS_CXR = 1112 , SYSZ_INS_CXSTR = 1113 , SYSZ_INS_CXTR = 1114 , SYSZ_INS_CXUTR = 1115 , SYSZ_INS_CXZT = 1116 , SYSZ_INS_CZDT = 1117 , SYSZ_INS_CZXT = 1118 , SYSZ_INS_D = 1119 , SYSZ_INS_DD = 1120 , SYSZ_INS_DDR = 1121 , SYSZ_INS_DDTR = 1122 , SYSZ_INS_DDTRA = 1123 , SYSZ_INS_DE = 1124 , SYSZ_INS_DER = 1125 , SYSZ_INS_DIAG = 1126 , SYSZ_INS_DIDBR = 1127 , SYSZ_INS_DIEBR = 1128 , SYSZ_INS_DP = 1129 , SYSZ_INS_DR = 1130 , SYSZ_INS_DXR = 1131 , SYSZ_INS_DXTR = 1132 , SYSZ_INS_DXTRA = 1133 , SYSZ_INS_ECAG = 1134 , SYSZ_INS_ECCTR = 1135 , SYSZ_INS_ECPGA = 1136 , SYSZ_INS_ECTG = 1137 , SYSZ_INS_ED = 1138 , SYSZ_INS_EDMK = 1139 , SYSZ_INS_EEDTR = 1140 , SYSZ_INS_EEXTR = 1141 , SYSZ_INS_EFPC = 1142 , SYSZ_INS_EPAIR = 1143 , SYSZ_INS_EPAR = 1144 , SYSZ_INS_EPCTR = 1145 , SYSZ_INS_EPSW = 1146 , SYSZ_INS_EREG = 1147 , SYSZ_INS_EREGG = 1148 , SYSZ_INS_ESAIR = 1149 , SYSZ_INS_ESAR = 1150 , SYSZ_INS_ESDTR = 1151 , SYSZ_INS_ESEA = 1152 , SYSZ_INS_ESTA = 1153 , SYSZ_INS_ESXTR = 1154 , SYSZ_INS_ETND = 1155 , SYSZ_INS_EX = 1156 , SYSZ_INS_EXRL = 1157 , SYSZ_INS_FIDR = 1158 , SYSZ_INS_FIDTR = 1159 , SYSZ_INS_FIER = 1160 , SYSZ_INS_FIXR = 1161 , SYSZ_INS_FIXTR = 1162 , SYSZ_INS_HDR = 1163 , SYSZ_INS_HER = 1164 , SYSZ_INS_HSCH = 1165 , SYSZ_INS_IAC = 1166 , SYSZ_INS_ICM = 1167 , SYSZ_INS_ICMH = 1168 , SYSZ_INS_ICMY = 1169 , SYSZ_INS_IDTE = 1170 , SYSZ_INS_IEDTR = 1171 , SYSZ_INS_IEXTR = 1172 , SYSZ_INS_IPK = 1173 , SYSZ_INS_IPTE = 1174 , SYSZ_INS_IRBM = 1175 , SYSZ_INS_ISKE = 1176 , SYSZ_INS_IVSK = 1177 , SYSZ_INS_JGM = 1178 , SYSZ_INS_JGNM = 1179 , SYSZ_INS_JGNP = 1180 , SYSZ_INS_JGNZ = 1181 , SYSZ_INS_JGP = 1182 , SYSZ_INS_JGZ = 1183 , SYSZ_INS_JM = 1184 , SYSZ_INS_JNM = 1185 , SYSZ_INS_JNP = 1186 , SYSZ_INS_JNZ = 1187 , SYSZ_INS_JP = 1188 , SYSZ_INS_JZ = 1189 , SYSZ_INS_KDB = 1190 , SYSZ_INS_KDBR = 1191 , SYSZ_INS_KDTR = 1192 , SYSZ_INS_KEB = 1193 , SYSZ_INS_KEBR = 1194 , SYSZ_INS_KIMD = 1195 , SYSZ_INS_KLMD = 1196 , SYSZ_INS_KM = 1197 , SYSZ_INS_KMA = 1198 , SYSZ_INS_KMAC = 1199 , SYSZ_INS_KMC = 1200 , SYSZ_INS_KMCTR = 1201 , SYSZ_INS_KMF = 1202 , SYSZ_INS_KMO = 1203 , SYSZ_INS_KXBR = 1204 , SYSZ_INS_KXTR = 1205 , SYSZ_INS_LAE = 1206 , SYSZ_INS_LAEY = 1207 , SYSZ_INS_LAM = 1208 , SYSZ_INS_LAMY = 1209 , SYSZ_INS_LASP = 1210 , SYSZ_INS_LAT = 1211 , SYSZ_INS_LCBB = 1212 , SYSZ_INS_LCCTL = 1213 , SYSZ_INS_LCDFR = 1214 , SYSZ_INS_LCDR = 1215 , SYSZ_INS_LCER = 1216 , SYSZ_INS_LCTL = 1217 , SYSZ_INS_LCTLG = 1218 , SYSZ_INS_LCXR = 1219 , SYSZ_INS_LDE = 1220 , SYSZ_INS_LDER = 1221 , SYSZ_INS_LDETR = 1222 , SYSZ_INS_LDXR = 1223 , SYSZ_INS_LDXTR = 1224 , SYSZ_INS_LEDR = 1225 , SYSZ_INS_LEDTR = 1226 , SYSZ_INS_LEXR = 1227 , SYSZ_INS_LFAS = 1228 , SYSZ_INS_LFHAT = 1229 , SYSZ_INS_LFPC = 1230 , SYSZ_INS_LGAT = 1231 , SYSZ_INS_LGG = 1232 , SYSZ_INS_LGSC = 1233 , SYSZ_INS_LLGFAT = 1234 , SYSZ_INS_LLGFSG = 1235 , SYSZ_INS_LLGT = 1236 , SYSZ_INS_LLGTAT = 1237 , SYSZ_INS_LLGTR = 1238 , SYSZ_INS_LLZRGF = 1239 , SYSZ_INS_LM = 1240 , SYSZ_INS_LMD = 1241 , SYSZ_INS_LMH = 1242 , SYSZ_INS_LMY = 1243 , SYSZ_INS_LNDFR = 1244 , SYSZ_INS_LNDR = 1245 , SYSZ_INS_LNER = 1246 , SYSZ_INS_LNXR = 1247 , SYSZ_INS_LOCFH = 1248 , SYSZ_INS_LOCFHE = 1249 , SYSZ_INS_LOCFHH = 1250 , SYSZ_INS_LOCFHHE = 1251 , SYSZ_INS_LOCFHL = 1252 , SYSZ_INS_LOCFHLE = 1253 , SYSZ_INS_LOCFHLH = 1254 , SYSZ_INS_LOCFHM = 1255 , SYSZ_INS_LOCFHNE = 1256 , SYSZ_INS_LOCFHNH = 1257 , SYSZ_INS_LOCFHNHE = 1258 , SYSZ_INS_LOCFHNL = 1259 , SYSZ_INS_LOCFHNLE = 1260 , SYSZ_INS_LOCFHNLH = 1261 , SYSZ_INS_LOCFHNM = 1262 , SYSZ_INS_LOCFHNO = 1263 , SYSZ_INS_LOCFHNP = 1264 , SYSZ_INS_LOCFHNZ = 1265 , SYSZ_INS_LOCFHO = 1266 , SYSZ_INS_LOCFHP = 1267 , SYSZ_INS_LOCFHR = 1268 , SYSZ_INS_LOCFHRE = 1269 , SYSZ_INS_LOCFHRH = 1270 , SYSZ_INS_LOCFHRHE = 1271 , SYSZ_INS_LOCFHRL = 1272 , SYSZ_INS_LOCFHRLE = 1273 , SYSZ_INS_LOCFHRLH = 1274 , SYSZ_INS_LOCFHRM = 1275 , SYSZ_INS_LOCFHRNE = 1276 , SYSZ_INS_LOCFHRNH = 1277 , SYSZ_INS_LOCFHRNHE = 1278 , SYSZ_INS_LOCFHRNL = 1279 , SYSZ_INS_LOCFHRNLE = 1280 , SYSZ_INS_LOCFHRNLH = 1281 , SYSZ_INS_LOCFHRNM = 1282 , SYSZ_INS_LOCFHRNO = 1283 , SYSZ_INS_LOCFHRNP = 1284 , SYSZ_INS_LOCFHRNZ = 1285 , SYSZ_INS_LOCFHRO = 1286 , SYSZ_INS_LOCFHRP = 1287 , SYSZ_INS_LOCFHRZ = 1288 , SYSZ_INS_LOCFHZ = 1289 , SYSZ_INS_LOCGHI = 1290 , SYSZ_INS_LOCGHIE = 1291 , SYSZ_INS_LOCGHIH = 1292 , SYSZ_INS_LOCGHIHE = 1293 , SYSZ_INS_LOCGHIL = 1294 , SYSZ_INS_LOCGHILE = 1295 , SYSZ_INS_LOCGHILH = 1296 , SYSZ_INS_LOCGHIM = 1297 , SYSZ_INS_LOCGHINE = 1298 , SYSZ_INS_LOCGHINH = 1299 , SYSZ_INS_LOCGHINHE = 1300 , SYSZ_INS_LOCGHINL = 1301 , SYSZ_INS_LOCGHINLE = 1302 , SYSZ_INS_LOCGHINLH = 1303 , SYSZ_INS_LOCGHINM = 1304 , SYSZ_INS_LOCGHINO = 1305 , SYSZ_INS_LOCGHINP = 1306 , SYSZ_INS_LOCGHINZ = 1307 , SYSZ_INS_LOCGHIO = 1308 , SYSZ_INS_LOCGHIP = 1309 , SYSZ_INS_LOCGHIZ = 1310 , SYSZ_INS_LOCGM = 1311 , SYSZ_INS_LOCGNM = 1312 , SYSZ_INS_LOCGNP = 1313 , SYSZ_INS_LOCGNZ = 1314 , SYSZ_INS_LOCGP = 1315 , SYSZ_INS_LOCGRM = 1316 , SYSZ_INS_LOCGRNM = 1317 , SYSZ_INS_LOCGRNP = 1318 , SYSZ_INS_LOCGRNZ = 1319 , SYSZ_INS_LOCGRP = 1320 , SYSZ_INS_LOCGRZ = 1321 , SYSZ_INS_LOCGZ = 1322 , SYSZ_INS_LOCHHI = 1323 , SYSZ_INS_LOCHHIE = 1324 , SYSZ_INS_LOCHHIH = 1325 , SYSZ_INS_LOCHHIHE = 1326 , SYSZ_INS_LOCHHIL = 1327 , SYSZ_INS_LOCHHILE = 1328 , SYSZ_INS_LOCHHILH = 1329 , SYSZ_INS_LOCHHIM = 1330 , SYSZ_INS_LOCHHINE = 1331 , SYSZ_INS_LOCHHINH = 1332 , SYSZ_INS_LOCHHINHE = 1333 , SYSZ_INS_LOCHHINL = 1334 , SYSZ_INS_LOCHHINLE = 1335 , SYSZ_INS_LOCHHINLH = 1336 , SYSZ_INS_LOCHHINM = 1337 , SYSZ_INS_LOCHHINO = 1338 , SYSZ_INS_LOCHHINP = 1339 , SYSZ_INS_LOCHHINZ = 1340 , SYSZ_INS_LOCHHIO = 1341 , SYSZ_INS_LOCHHIP = 1342 , SYSZ_INS_LOCHHIZ = 1343 , SYSZ_INS_LOCHI = 1344 , SYSZ_INS_LOCHIE = 1345 , SYSZ_INS_LOCHIH = 1346 , SYSZ_INS_LOCHIHE = 1347 , SYSZ_INS_LOCHIL = 1348 , SYSZ_INS_LOCHILE = 1349 , SYSZ_INS_LOCHILH = 1350 , SYSZ_INS_LOCHIM = 1351 , SYSZ_INS_LOCHINE = 1352 , SYSZ_INS_LOCHINH = 1353 , SYSZ_INS_LOCHINHE = 1354 , SYSZ_INS_LOCHINL = 1355 , SYSZ_INS_LOCHINLE = 1356 , SYSZ_INS_LOCHINLH = 1357 , SYSZ_INS_LOCHINM = 1358 , SYSZ_INS_LOCHINO = 1359 , SYSZ_INS_LOCHINP = 1360 , SYSZ_INS_LOCHINZ = 1361 , SYSZ_INS_LOCHIO = 1362 , SYSZ_INS_LOCHIP = 1363 , SYSZ_INS_LOCHIZ = 1364 , SYSZ_INS_LOCM = 1365 , SYSZ_INS_LOCNM = 1366 , SYSZ_INS_LOCNP = 1367 , SYSZ_INS_LOCNZ = 1368 , SYSZ_INS_LOCP = 1369 , SYSZ_INS_LOCRM = 1370 , SYSZ_INS_LOCRNM = 1371 , SYSZ_INS_LOCRNP = 1372 , SYSZ_INS_LOCRNZ = 1373 , SYSZ_INS_LOCRP = 1374 , SYSZ_INS_LOCRZ = 1375 , SYSZ_INS_LOCZ = 1376 , SYSZ_INS_LPCTL = 1377 , SYSZ_INS_LPD = 1378 , SYSZ_INS_LPDFR = 1379 , SYSZ_INS_LPDG = 1380 , SYSZ_INS_LPDR = 1381 , SYSZ_INS_LPER = 1382 , SYSZ_INS_LPP = 1383 , SYSZ_INS_LPQ = 1384 , SYSZ_INS_LPSW = 1385 , SYSZ_INS_LPSWE = 1386 , SYSZ_INS_LPTEA = 1387 , SYSZ_INS_LPXR = 1388 , SYSZ_INS_LRA = 1389 , SYSZ_INS_LRAG = 1390 , SYSZ_INS_LRAY = 1391 , SYSZ_INS_LRDR = 1392 , SYSZ_INS_LRER = 1393 , SYSZ_INS_LRVH = 1394 , SYSZ_INS_LSCTL = 1395 , SYSZ_INS_LTDR = 1396 , SYSZ_INS_LTDTR = 1397 , SYSZ_INS_LTER = 1398 , SYSZ_INS_LTXR = 1399 , SYSZ_INS_LTXTR = 1400 , SYSZ_INS_LURA = 1401 , SYSZ_INS_LURAG = 1402 , SYSZ_INS_LXD = 1403 , SYSZ_INS_LXDR = 1404 , SYSZ_INS_LXDTR = 1405 , SYSZ_INS_LXE = 1406 , SYSZ_INS_LXER = 1407 , SYSZ_INS_LZRF = 1408 , SYSZ_INS_LZRG = 1409 , SYSZ_INS_M = 1410 , SYSZ_INS_MAD = 1411 , SYSZ_INS_MADR = 1412 , SYSZ_INS_MAE = 1413 , SYSZ_INS_MAER = 1414 , SYSZ_INS_MAY = 1415 , SYSZ_INS_MAYH = 1416 , SYSZ_INS_MAYHR = 1417 , SYSZ_INS_MAYL = 1418 , SYSZ_INS_MAYLR = 1419 , SYSZ_INS_MAYR = 1420 , SYSZ_INS_MC = 1421 , SYSZ_INS_MD = 1422 , SYSZ_INS_MDE = 1423 , SYSZ_INS_MDER = 1424 , SYSZ_INS_MDR = 1425 , SYSZ_INS_MDTR = 1426 , SYSZ_INS_MDTRA = 1427 , SYSZ_INS_ME = 1428 , SYSZ_INS_MEE = 1429 , SYSZ_INS_MEER = 1430 , SYSZ_INS_MER = 1431 , SYSZ_INS_MFY = 1432 , SYSZ_INS_MG = 1433 , SYSZ_INS_MGH = 1434 , SYSZ_INS_MGRK = 1435 , SYSZ_INS_ML = 1436 , SYSZ_INS_MLR = 1437 , SYSZ_INS_MP = 1438 , SYSZ_INS_MR = 1439 , SYSZ_INS_MSC = 1440 , SYSZ_INS_MSCH = 1441 , SYSZ_INS_MSD = 1442 , SYSZ_INS_MSDR = 1443 , SYSZ_INS_MSE = 1444 , SYSZ_INS_MSER = 1445 , SYSZ_INS_MSGC = 1446 , SYSZ_INS_MSGRKC = 1447 , SYSZ_INS_MSRKC = 1448 , SYSZ_INS_MSTA = 1449 , SYSZ_INS_MVCDK = 1450 , SYSZ_INS_MVCIN = 1451 , SYSZ_INS_MVCK = 1452 , SYSZ_INS_MVCL = 1453 , SYSZ_INS_MVCLE = 1454 , SYSZ_INS_MVCLU = 1455 , SYSZ_INS_MVCOS = 1456 , SYSZ_INS_MVCP = 1457 , SYSZ_INS_MVCS = 1458 , SYSZ_INS_MVCSK = 1459 , SYSZ_INS_MVN = 1460 , SYSZ_INS_MVO = 1461 , SYSZ_INS_MVPG = 1462 , SYSZ_INS_MVZ = 1463 , SYSZ_INS_MXD = 1464 , SYSZ_INS_MXDR = 1465 , SYSZ_INS_MXR = 1466 , SYSZ_INS_MXTR = 1467 , SYSZ_INS_MXTRA = 1468 , SYSZ_INS_MY = 1469 , SYSZ_INS_MYH = 1470 , SYSZ_INS_MYHR = 1471 , SYSZ_INS_MYL = 1472 , SYSZ_INS_MYLR = 1473 , SYSZ_INS_MYR = 1474 , SYSZ_INS_NIAI = 1475 , SYSZ_INS_NTSTG = 1476 , SYSZ_INS_PACK = 1477 , SYSZ_INS_PALB = 1478 , SYSZ_INS_PC = 1479 , SYSZ_INS_PCC = 1480 , SYSZ_INS_PCKMO = 1481 , SYSZ_INS_PFMF = 1482 , SYSZ_INS_PFPO = 1483 , SYSZ_INS_PGIN = 1484 , SYSZ_INS_PGOUT = 1485 , SYSZ_INS_PKA = 1486 , SYSZ_INS_PKU = 1487 , SYSZ_INS_PLO = 1488 , SYSZ_INS_POPCNT = 1489 , SYSZ_INS_PPA = 1490 , SYSZ_INS_PPNO = 1491 , SYSZ_INS_PR = 1492 , SYSZ_INS_PRNO = 1493 , SYSZ_INS_PT = 1494 , SYSZ_INS_PTF = 1495 , SYSZ_INS_PTFF = 1496 , SYSZ_INS_PTI = 1497 , SYSZ_INS_PTLB = 1498 , SYSZ_INS_QADTR = 1499 , SYSZ_INS_QAXTR = 1500 , SYSZ_INS_QCTRI = 1501 , SYSZ_INS_QSI = 1502 , SYSZ_INS_RCHP = 1503 , SYSZ_INS_RISBGN = 1504 , SYSZ_INS_RP = 1505 , SYSZ_INS_RRBE = 1506 , SYSZ_INS_RRBM = 1507 , SYSZ_INS_RRDTR = 1508 , SYSZ_INS_RRXTR = 1509 , SYSZ_INS_RSCH = 1510 , SYSZ_INS_SAC = 1511 , SYSZ_INS_SACF = 1512 , SYSZ_INS_SAL = 1513 , SYSZ_INS_SAM24 = 1514 , SYSZ_INS_SAM31 = 1515 , SYSZ_INS_SAM64 = 1516 , SYSZ_INS_SAR = 1517 , SYSZ_INS_SCCTR = 1518 , SYSZ_INS_SCHM = 1519 , SYSZ_INS_SCK = 1520 , SYSZ_INS_SCKC = 1521 , SYSZ_INS_SCKPF = 1522 , SYSZ_INS_SD = 1523 , SYSZ_INS_SDR = 1524 , SYSZ_INS_SDTR = 1525 , SYSZ_INS_SDTRA = 1526 , SYSZ_INS_SE = 1527 , SYSZ_INS_SER = 1528 , SYSZ_INS_SFASR = 1529 , SYSZ_INS_SFPC = 1530 , SYSZ_INS_SGH = 1531 , SYSZ_INS_SHHHR = 1532 , SYSZ_INS_SHHLR = 1533 , SYSZ_INS_SIE = 1534 , SYSZ_INS_SIGA = 1535 , SYSZ_INS_SIGP = 1536 , SYSZ_INS_SLA = 1537 , SYSZ_INS_SLAG = 1538 , SYSZ_INS_SLAK = 1539 , SYSZ_INS_SLDA = 1540 , SYSZ_INS_SLDL = 1541 , SYSZ_INS_SLDT = 1542 , SYSZ_INS_SLHHHR = 1543 , SYSZ_INS_SLHHLR = 1544 , SYSZ_INS_SLXT = 1545 , SYSZ_INS_SP = 1546 , SYSZ_INS_SPCTR = 1547 , SYSZ_INS_SPKA = 1548 , SYSZ_INS_SPM = 1549 , SYSZ_INS_SPT = 1550 , SYSZ_INS_SPX = 1551 , SYSZ_INS_SQD = 1552 , SYSZ_INS_SQDR = 1553 , SYSZ_INS_SQE = 1554 , SYSZ_INS_SQER = 1555 , SYSZ_INS_SQXR = 1556 , SYSZ_INS_SRDA = 1557 , SYSZ_INS_SRDL = 1558 , SYSZ_INS_SRDT = 1559 , SYSZ_INS_SRNM = 1560 , SYSZ_INS_SRNMB = 1561 , SYSZ_INS_SRNMT = 1562 , SYSZ_INS_SRP = 1563 , SYSZ_INS_SRSTU = 1564 , SYSZ_INS_SRXT = 1565 , SYSZ_INS_SSAIR = 1566 , SYSZ_INS_SSAR = 1567 , SYSZ_INS_SSCH = 1568 , SYSZ_INS_SSKE = 1569 , SYSZ_INS_SSM = 1570 , SYSZ_INS_STAM = 1571 , SYSZ_INS_STAMY = 1572 , SYSZ_INS_STAP = 1573 , SYSZ_INS_STCK = 1574 , SYSZ_INS_STCKC = 1575 , SYSZ_INS_STCKE = 1576 , SYSZ_INS_STCKF = 1577 , SYSZ_INS_STCM = 1578 , SYSZ_INS_STCMH = 1579 , SYSZ_INS_STCMY = 1580 , SYSZ_INS_STCPS = 1581 , SYSZ_INS_STCRW = 1582 , SYSZ_INS_STCTG = 1583 , SYSZ_INS_STCTL = 1584 , SYSZ_INS_STFL = 1585 , SYSZ_INS_STFLE = 1586 , SYSZ_INS_STFPC = 1587 , SYSZ_INS_STGSC = 1588 , SYSZ_INS_STIDP = 1589 , SYSZ_INS_STM = 1590 , SYSZ_INS_STMH = 1591 , SYSZ_INS_STMY = 1592 , SYSZ_INS_STNSM = 1593 , SYSZ_INS_STOCFH = 1594 , SYSZ_INS_STOCFHE = 1595 , SYSZ_INS_STOCFHH = 1596 , SYSZ_INS_STOCFHHE = 1597 , SYSZ_INS_STOCFHL = 1598 , SYSZ_INS_STOCFHLE = 1599 , SYSZ_INS_STOCFHLH = 1600 , SYSZ_INS_STOCFHM = 1601 , SYSZ_INS_STOCFHNE = 1602 , SYSZ_INS_STOCFHNH = 1603 , SYSZ_INS_STOCFHNHE = 1604 , SYSZ_INS_STOCFHNL = 1605 , SYSZ_INS_STOCFHNLE = 1606 , SYSZ_INS_STOCFHNLH = 1607 , SYSZ_INS_STOCFHNM = 1608 , SYSZ_INS_STOCFHNO = 1609 , SYSZ_INS_STOCFHNP = 1610 , SYSZ_INS_STOCFHNZ = 1611 , SYSZ_INS_STOCFHO = 1612 , SYSZ_INS_STOCFHP = 1613 , SYSZ_INS_STOCFHZ = 1614 , SYSZ_INS_STOCGM = 1615 , SYSZ_INS_STOCGNM = 1616 , SYSZ_INS_STOCGNP = 1617 , SYSZ_INS_STOCGNZ = 1618 , SYSZ_INS_STOCGP = 1619 , SYSZ_INS_STOCGZ = 1620 , SYSZ_INS_STOCM = 1621 , SYSZ_INS_STOCNM = 1622 , SYSZ_INS_STOCNP = 1623 , SYSZ_INS_STOCNZ = 1624 , SYSZ_INS_STOCP = 1625 , SYSZ_INS_STOCZ = 1626 , SYSZ_INS_STOSM = 1627 , SYSZ_INS_STPQ = 1628 , SYSZ_INS_STPT = 1629 , SYSZ_INS_STPX = 1630 , SYSZ_INS_STRAG = 1631 , SYSZ_INS_STRVH = 1632 , SYSZ_INS_STSCH = 1633 , SYSZ_INS_STSI = 1634 , SYSZ_INS_STURA = 1635 , SYSZ_INS_STURG = 1636 , SYSZ_INS_SU = 1637 , SYSZ_INS_SUR = 1638 , SYSZ_INS_SVC = 1639 , SYSZ_INS_SW = 1640 , SYSZ_INS_SWR = 1641 , SYSZ_INS_SXR = 1642 , SYSZ_INS_SXTR = 1643 , SYSZ_INS_SXTRA = 1644 , SYSZ_INS_TABORT = 1645 , SYSZ_INS_TAM = 1646 , SYSZ_INS_TAR = 1647 , SYSZ_INS_TB = 1648 , SYSZ_INS_TBDR = 1649 , SYSZ_INS_TBEDR = 1650 , SYSZ_INS_TBEGIN = 1651 , SYSZ_INS_TBEGINC = 1652 , SYSZ_INS_TCDB = 1653 , SYSZ_INS_TCEB = 1654 , SYSZ_INS_TCXB = 1655 , SYSZ_INS_TDCDT = 1656 , SYSZ_INS_TDCET = 1657 , SYSZ_INS_TDCXT = 1658 , SYSZ_INS_TDGDT = 1659 , SYSZ_INS_TDGET = 1660 , SYSZ_INS_TDGXT = 1661 , SYSZ_INS_TEND = 1662 , SYSZ_INS_THDER = 1663 , SYSZ_INS_THDR = 1664 , SYSZ_INS_TP = 1665 , SYSZ_INS_TPI = 1666 , SYSZ_INS_TPROT = 1667 , SYSZ_INS_TR = 1668 , SYSZ_INS_TRACE = 1669 , SYSZ_INS_TRACG = 1670 , SYSZ_INS_TRAP2 = 1671 , SYSZ_INS_TRAP4 = 1672 , SYSZ_INS_TRE = 1673 , SYSZ_INS_TROO = 1674 , SYSZ_INS_TROT = 1675 , SYSZ_INS_TRT = 1676 , SYSZ_INS_TRTE = 1677 , SYSZ_INS_TRTO = 1678 , SYSZ_INS_TRTR = 1679 , SYSZ_INS_TRTRE = 1680 , SYSZ_INS_TRTT = 1681 , SYSZ_INS_TS = 1682 , SYSZ_INS_TSCH = 1683 , SYSZ_INS_UNPK = 1684 , SYSZ_INS_UNPKA = 1685 , SYSZ_INS_UNPKU = 1686 , SYSZ_INS_UPT = 1687 , SYSZ_INS_VA = 1688 , SYSZ_INS_VAB = 1689 , SYSZ_INS_VAC = 1690 , SYSZ_INS_VACC = 1691 , SYSZ_INS_VACCB = 1692 , SYSZ_INS_VACCC = 1693 , SYSZ_INS_VACCCQ = 1694 , SYSZ_INS_VACCF = 1695 , SYSZ_INS_VACCG = 1696 , SYSZ_INS_VACCH = 1697 , SYSZ_INS_VACCQ = 1698 , SYSZ_INS_VACQ = 1699 , SYSZ_INS_VAF = 1700 , SYSZ_INS_VAG = 1701 , SYSZ_INS_VAH = 1702 , SYSZ_INS_VAP = 1703 , SYSZ_INS_VAQ = 1704 , SYSZ_INS_VAVG = 1705 , SYSZ_INS_VAVGB = 1706 , SYSZ_INS_VAVGF = 1707 , SYSZ_INS_VAVGG = 1708 , SYSZ_INS_VAVGH = 1709 , SYSZ_INS_VAVGL = 1710 , SYSZ_INS_VAVGLB = 1711 , SYSZ_INS_VAVGLF = 1712 , SYSZ_INS_VAVGLG = 1713 , SYSZ_INS_VAVGLH = 1714 , SYSZ_INS_VBPERM = 1715 , SYSZ_INS_VCDG = 1716 , SYSZ_INS_VCDGB = 1717 , SYSZ_INS_VCDLG = 1718 , SYSZ_INS_VCDLGB = 1719 , SYSZ_INS_VCEQ = 1720 , SYSZ_INS_VCEQB = 1721 , SYSZ_INS_VCEQBS = 1722 , SYSZ_INS_VCEQF = 1723 , SYSZ_INS_VCEQFS = 1724 , SYSZ_INS_VCEQG = 1725 , SYSZ_INS_VCEQGS = 1726 , SYSZ_INS_VCEQH = 1727 , SYSZ_INS_VCEQHS = 1728 , SYSZ_INS_VCGD = 1729 , SYSZ_INS_VCGDB = 1730 , SYSZ_INS_VCH = 1731 , SYSZ_INS_VCHB = 1732 , SYSZ_INS_VCHBS = 1733 , SYSZ_INS_VCHF = 1734 , SYSZ_INS_VCHFS = 1735 , SYSZ_INS_VCHG = 1736 , SYSZ_INS_VCHGS = 1737 , SYSZ_INS_VCHH = 1738 , SYSZ_INS_VCHHS = 1739 , SYSZ_INS_VCHL = 1740 , SYSZ_INS_VCHLB = 1741 , SYSZ_INS_VCHLBS = 1742 , SYSZ_INS_VCHLF = 1743 , SYSZ_INS_VCHLFS = 1744 , SYSZ_INS_VCHLG = 1745 , SYSZ_INS_VCHLGS = 1746 , SYSZ_INS_VCHLH = 1747 , SYSZ_INS_VCHLHS = 1748 , SYSZ_INS_VCKSM = 1749 , SYSZ_INS_VCLGD = 1750 , SYSZ_INS_VCLGDB = 1751 , SYSZ_INS_VCLZ = 1752 , SYSZ_INS_VCLZB = 1753 , SYSZ_INS_VCLZF = 1754 , SYSZ_INS_VCLZG = 1755 , SYSZ_INS_VCLZH = 1756 , SYSZ_INS_VCP = 1757 , SYSZ_INS_VCTZ = 1758 , SYSZ_INS_VCTZB = 1759 , SYSZ_INS_VCTZF = 1760 , SYSZ_INS_VCTZG = 1761 , SYSZ_INS_VCTZH = 1762 , SYSZ_INS_VCVB = 1763 , SYSZ_INS_VCVBG = 1764 , SYSZ_INS_VCVD = 1765 , SYSZ_INS_VCVDG = 1766 , SYSZ_INS_VDP = 1767 , SYSZ_INS_VEC = 1768 , SYSZ_INS_VECB = 1769 , SYSZ_INS_VECF = 1770 , SYSZ_INS_VECG = 1771 , SYSZ_INS_VECH = 1772 , SYSZ_INS_VECL = 1773 , SYSZ_INS_VECLB = 1774 , SYSZ_INS_VECLF = 1775 , SYSZ_INS_VECLG = 1776 , SYSZ_INS_VECLH = 1777 , SYSZ_INS_VERIM = 1778 , SYSZ_INS_VERIMB = 1779 , SYSZ_INS_VERIMF = 1780 , SYSZ_INS_VERIMG = 1781 , SYSZ_INS_VERIMH = 1782 , SYSZ_INS_VERLL = 1783 , SYSZ_INS_VERLLB = 1784 , SYSZ_INS_VERLLF = 1785 , SYSZ_INS_VERLLG = 1786 , SYSZ_INS_VERLLH = 1787 , SYSZ_INS_VERLLV = 1788 , SYSZ_INS_VERLLVB = 1789 , SYSZ_INS_VERLLVF = 1790 , SYSZ_INS_VERLLVG = 1791 , SYSZ_INS_VERLLVH = 1792 , SYSZ_INS_VESL = 1793 , SYSZ_INS_VESLB = 1794 , SYSZ_INS_VESLF = 1795 , SYSZ_INS_VESLG = 1796 , SYSZ_INS_VESLH = 1797 , SYSZ_INS_VESLV = 1798 , SYSZ_INS_VESLVB = 1799 , SYSZ_INS_VESLVF = 1800 , SYSZ_INS_VESLVG = 1801 , SYSZ_INS_VESLVH = 1802 , SYSZ_INS_VESRA = 1803 , SYSZ_INS_VESRAB = 1804 , SYSZ_INS_VESRAF = 1805 , SYSZ_INS_VESRAG = 1806 , SYSZ_INS_VESRAH = 1807 , SYSZ_INS_VESRAV = 1808 , SYSZ_INS_VESRAVB = 1809 , SYSZ_INS_VESRAVF = 1810 , SYSZ_INS_VESRAVG = 1811 , SYSZ_INS_VESRAVH = 1812 , SYSZ_INS_VESRL = 1813 , SYSZ_INS_VESRLB = 1814 , SYSZ_INS_VESRLF = 1815 , SYSZ_INS_VESRLG = 1816 , SYSZ_INS_VESRLH = 1817 , SYSZ_INS_VESRLV = 1818 , SYSZ_INS_VESRLVB = 1819 , SYSZ_INS_VESRLVF = 1820 , SYSZ_INS_VESRLVG = 1821 , SYSZ_INS_VESRLVH = 1822 , SYSZ_INS_VFA = 1823 , SYSZ_INS_VFADB = 1824 , SYSZ_INS_VFAE = 1825 , SYSZ_INS_VFAEB = 1826 , SYSZ_INS_VFAEBS = 1827 , SYSZ_INS_VFAEF = 1828 , SYSZ_INS_VFAEFS = 1829 , SYSZ_INS_VFAEH = 1830 , SYSZ_INS_VFAEHS = 1831 , SYSZ_INS_VFAEZB = 1832 , SYSZ_INS_VFAEZBS = 1833 , SYSZ_INS_VFAEZF = 1834 , SYSZ_INS_VFAEZFS = 1835 , SYSZ_INS_VFAEZH = 1836 , SYSZ_INS_VFAEZHS = 1837 , SYSZ_INS_VFASB = 1838 , SYSZ_INS_VFCE = 1839 , SYSZ_INS_VFCEDB = 1840 , SYSZ_INS_VFCEDBS = 1841 , SYSZ_INS_VFCESB = 1842 , SYSZ_INS_VFCESBS = 1843 , SYSZ_INS_VFCH = 1844 , SYSZ_INS_VFCHDB = 1845 , SYSZ_INS_VFCHDBS = 1846 , SYSZ_INS_VFCHE = 1847 , SYSZ_INS_VFCHEDB = 1848 , SYSZ_INS_VFCHEDBS = 1849 , SYSZ_INS_VFCHESB = 1850 , SYSZ_INS_VFCHESBS = 1851 , SYSZ_INS_VFCHSB = 1852 , SYSZ_INS_VFCHSBS = 1853 , SYSZ_INS_VFD = 1854 , SYSZ_INS_VFDDB = 1855 , SYSZ_INS_VFDSB = 1856 , SYSZ_INS_VFEE = 1857 , SYSZ_INS_VFEEB = 1858 , SYSZ_INS_VFEEBS = 1859 , SYSZ_INS_VFEEF = 1860 , SYSZ_INS_VFEEFS = 1861 , SYSZ_INS_VFEEH = 1862 , SYSZ_INS_VFEEHS = 1863 , SYSZ_INS_VFEEZB = 1864 , SYSZ_INS_VFEEZBS = 1865 , SYSZ_INS_VFEEZF = 1866 , SYSZ_INS_VFEEZFS = 1867 , SYSZ_INS_VFEEZH = 1868 , SYSZ_INS_VFEEZHS = 1869 , SYSZ_INS_VFENE = 1870 , SYSZ_INS_VFENEB = 1871 , SYSZ_INS_VFENEBS = 1872 , SYSZ_INS_VFENEF = 1873 , SYSZ_INS_VFENEFS = 1874 , SYSZ_INS_VFENEH = 1875 , SYSZ_INS_VFENEHS = 1876 , SYSZ_INS_VFENEZB = 1877 , SYSZ_INS_VFENEZBS = 1878 , SYSZ_INS_VFENEZF = 1879 , SYSZ_INS_VFENEZFS = 1880 , SYSZ_INS_VFENEZH = 1881 , SYSZ_INS_VFENEZHS = 1882 , SYSZ_INS_VFI = 1883 , SYSZ_INS_VFIDB = 1884 , SYSZ_INS_VFISB = 1885 , SYSZ_INS_VFKEDB = 1886 , SYSZ_INS_VFKEDBS = 1887 , SYSZ_INS_VFKESB = 1888 , SYSZ_INS_VFKESBS = 1889 , SYSZ_INS_VFKHDB = 1890 , SYSZ_INS_VFKHDBS = 1891 , SYSZ_INS_VFKHEDB = 1892 , SYSZ_INS_VFKHEDBS = 1893 , SYSZ_INS_VFKHESB = 1894 , SYSZ_INS_VFKHESBS = 1895 , SYSZ_INS_VFKHSB = 1896 , SYSZ_INS_VFKHSBS = 1897 , SYSZ_INS_VFLCDB = 1898 , SYSZ_INS_VFLCSB = 1899 , SYSZ_INS_VFLL = 1900 , SYSZ_INS_VFLLS = 1901 , SYSZ_INS_VFLNDB = 1902 , SYSZ_INS_VFLNSB = 1903 , SYSZ_INS_VFLPDB = 1904 , SYSZ_INS_VFLPSB = 1905 , SYSZ_INS_VFLR = 1906 , SYSZ_INS_VFLRD = 1907 , SYSZ_INS_VFM = 1908 , SYSZ_INS_VFMA = 1909 , SYSZ_INS_VFMADB = 1910 , SYSZ_INS_VFMASB = 1911 , SYSZ_INS_VFMAX = 1912 , SYSZ_INS_VFMAXDB = 1913 , SYSZ_INS_VFMAXSB = 1914 , SYSZ_INS_VFMDB = 1915 , SYSZ_INS_VFMIN = 1916 , SYSZ_INS_VFMINDB = 1917 , SYSZ_INS_VFMINSB = 1918 , SYSZ_INS_VFMS = 1919 , SYSZ_INS_VFMSB = 1920 , SYSZ_INS_VFMSDB = 1921 , SYSZ_INS_VFMSSB = 1922 , SYSZ_INS_VFNMA = 1923 , SYSZ_INS_VFNMADB = 1924 , SYSZ_INS_VFNMASB = 1925 , SYSZ_INS_VFNMS = 1926 , SYSZ_INS_VFNMSDB = 1927 , SYSZ_INS_VFNMSSB = 1928 , SYSZ_INS_VFPSO = 1929 , SYSZ_INS_VFPSODB = 1930 , SYSZ_INS_VFPSOSB = 1931 , SYSZ_INS_VFS = 1932 , SYSZ_INS_VFSDB = 1933 , SYSZ_INS_VFSQ = 1934 , SYSZ_INS_VFSQDB = 1935 , SYSZ_INS_VFSQSB = 1936 , SYSZ_INS_VFSSB = 1937 , SYSZ_INS_VFTCI = 1938 , SYSZ_INS_VFTCIDB = 1939 , SYSZ_INS_VFTCISB = 1940 , SYSZ_INS_VGBM = 1941 , SYSZ_INS_VGEF = 1942 , SYSZ_INS_VGEG = 1943 , SYSZ_INS_VGFM = 1944 , SYSZ_INS_VGFMA = 1945 , SYSZ_INS_VGFMAB = 1946 , SYSZ_INS_VGFMAF = 1947 , SYSZ_INS_VGFMAG = 1948 , SYSZ_INS_VGFMAH = 1949 , SYSZ_INS_VGFMB = 1950 , SYSZ_INS_VGFMF = 1951 , SYSZ_INS_VGFMG = 1952 , SYSZ_INS_VGFMH = 1953 , SYSZ_INS_VGM = 1954 , SYSZ_INS_VGMB = 1955 , SYSZ_INS_VGMF = 1956 , SYSZ_INS_VGMG = 1957 , SYSZ_INS_VGMH = 1958 , SYSZ_INS_VISTR = 1959 , SYSZ_INS_VISTRB = 1960 , SYSZ_INS_VISTRBS = 1961 , SYSZ_INS_VISTRF = 1962 , SYSZ_INS_VISTRFS = 1963 , SYSZ_INS_VISTRH = 1964 , SYSZ_INS_VISTRHS = 1965 , SYSZ_INS_VL = 1966 , SYSZ_INS_VLBB = 1967 , SYSZ_INS_VLC = 1968 , SYSZ_INS_VLCB = 1969 , SYSZ_INS_VLCF = 1970 , SYSZ_INS_VLCG = 1971 , SYSZ_INS_VLCH = 1972 , SYSZ_INS_VLDE = 1973 , SYSZ_INS_VLDEB = 1974 , SYSZ_INS_VLEB = 1975 , SYSZ_INS_VLED = 1976 , SYSZ_INS_VLEDB = 1977 , SYSZ_INS_VLEF = 1978 , SYSZ_INS_VLEG = 1979 , SYSZ_INS_VLEH = 1980 , SYSZ_INS_VLEIB = 1981 , SYSZ_INS_VLEIF = 1982 , SYSZ_INS_VLEIG = 1983 , SYSZ_INS_VLEIH = 1984 , SYSZ_INS_VLGV = 1985 , SYSZ_INS_VLGVB = 1986 , SYSZ_INS_VLGVF = 1987 , SYSZ_INS_VLGVG = 1988 , SYSZ_INS_VLGVH = 1989 , SYSZ_INS_VLIP = 1990 , SYSZ_INS_VLL = 1991 , SYSZ_INS_VLLEZ = 1992 , SYSZ_INS_VLLEZB = 1993 , SYSZ_INS_VLLEZF = 1994 , SYSZ_INS_VLLEZG = 1995 , SYSZ_INS_VLLEZH = 1996 , SYSZ_INS_VLLEZLF = 1997 , SYSZ_INS_VLM = 1998 , SYSZ_INS_VLP = 1999 , SYSZ_INS_VLPB = 2000 , SYSZ_INS_VLPF = 2001 , SYSZ_INS_VLPG = 2002 , SYSZ_INS_VLPH = 2003 , SYSZ_INS_VLR = 2004 , SYSZ_INS_VLREP = 2005 , SYSZ_INS_VLREPB = 2006 , SYSZ_INS_VLREPF = 2007 , SYSZ_INS_VLREPG = 2008 , SYSZ_INS_VLREPH = 2009 , SYSZ_INS_VLRL = 2010 , SYSZ_INS_VLRLR = 2011 , SYSZ_INS_VLVG = 2012 , SYSZ_INS_VLVGB = 2013 , SYSZ_INS_VLVGF = 2014 , SYSZ_INS_VLVGG = 2015 , SYSZ_INS_VLVGH = 2016 , SYSZ_INS_VLVGP = 2017 , SYSZ_INS_VMAE = 2018 , SYSZ_INS_VMAEB = 2019 , SYSZ_INS_VMAEF = 2020 , SYSZ_INS_VMAEH = 2021 , SYSZ_INS_VMAH = 2022 , SYSZ_INS_VMAHB = 2023 , SYSZ_INS_VMAHF = 2024 , SYSZ_INS_VMAHH = 2025 , SYSZ_INS_VMAL = 2026 , SYSZ_INS_VMALB = 2027 , SYSZ_INS_VMALE = 2028 , SYSZ_INS_VMALEB = 2029 , SYSZ_INS_VMALEF = 2030 , SYSZ_INS_VMALEH = 2031 , SYSZ_INS_VMALF = 2032 , SYSZ_INS_VMALH = 2033 , SYSZ_INS_VMALHB = 2034 , SYSZ_INS_VMALHF = 2035 , SYSZ_INS_VMALHH = 2036 , SYSZ_INS_VMALHW = 2037 , SYSZ_INS_VMALO = 2038 , SYSZ_INS_VMALOB = 2039 , SYSZ_INS_VMALOF = 2040 , SYSZ_INS_VMALOH = 2041 , SYSZ_INS_VMAO = 2042 , SYSZ_INS_VMAOB = 2043 , SYSZ_INS_VMAOF = 2044 , SYSZ_INS_VMAOH = 2045 , SYSZ_INS_VME = 2046 , SYSZ_INS_VMEB = 2047 , SYSZ_INS_VMEF = 2048 , SYSZ_INS_VMEH = 2049 , SYSZ_INS_VMH = 2050 , SYSZ_INS_VMHB = 2051 , SYSZ_INS_VMHF = 2052 , SYSZ_INS_VMHH = 2053 , SYSZ_INS_VML = 2054 , SYSZ_INS_VMLB = 2055 , SYSZ_INS_VMLE = 2056 , SYSZ_INS_VMLEB = 2057 , SYSZ_INS_VMLEF = 2058 , SYSZ_INS_VMLEH = 2059 , SYSZ_INS_VMLF = 2060 , SYSZ_INS_VMLH = 2061 , SYSZ_INS_VMLHB = 2062 , SYSZ_INS_VMLHF = 2063 , SYSZ_INS_VMLHH = 2064 , SYSZ_INS_VMLHW = 2065 , SYSZ_INS_VMLO = 2066 , SYSZ_INS_VMLOB = 2067 , SYSZ_INS_VMLOF = 2068 , SYSZ_INS_VMLOH = 2069 , SYSZ_INS_VMN = 2070 , SYSZ_INS_VMNB = 2071 , SYSZ_INS_VMNF = 2072 , SYSZ_INS_VMNG = 2073 , SYSZ_INS_VMNH = 2074 , SYSZ_INS_VMNL = 2075 , SYSZ_INS_VMNLB = 2076 , SYSZ_INS_VMNLF = 2077 , SYSZ_INS_VMNLG = 2078 , SYSZ_INS_VMNLH = 2079 , SYSZ_INS_VMO = 2080 , SYSZ_INS_VMOB = 2081 , SYSZ_INS_VMOF = 2082 , SYSZ_INS_VMOH = 2083 , SYSZ_INS_VMP = 2084 , SYSZ_INS_VMRH = 2085 , SYSZ_INS_VMRHB = 2086 , SYSZ_INS_VMRHF = 2087 , SYSZ_INS_VMRHG = 2088 , SYSZ_INS_VMRHH = 2089 , SYSZ_INS_VMRL = 2090 , SYSZ_INS_VMRLB = 2091 , SYSZ_INS_VMRLF = 2092 , SYSZ_INS_VMRLG = 2093 , SYSZ_INS_VMRLH = 2094 , SYSZ_INS_VMSL = 2095 , SYSZ_INS_VMSLG = 2096 , SYSZ_INS_VMSP = 2097 , SYSZ_INS_VMX = 2098 , SYSZ_INS_VMXB = 2099 , SYSZ_INS_VMXF = 2100 , SYSZ_INS_VMXG = 2101 , SYSZ_INS_VMXH = 2102 , SYSZ_INS_VMXL = 2103 , SYSZ_INS_VMXLB = 2104 , SYSZ_INS_VMXLF = 2105 , SYSZ_INS_VMXLG = 2106 , SYSZ_INS_VMXLH = 2107 , SYSZ_INS_VN = 2108 , SYSZ_INS_VNC = 2109 , SYSZ_INS_VNN = 2110 , SYSZ_INS_VNO = 2111 , SYSZ_INS_VNX = 2112 , SYSZ_INS_VO = 2113 , SYSZ_INS_VOC = 2114 , SYSZ_INS_VONE = 2115 , SYSZ_INS_VPDI = 2116 , SYSZ_INS_VPERM = 2117 , SYSZ_INS_VPK = 2118 , SYSZ_INS_VPKF = 2119 , SYSZ_INS_VPKG = 2120 , SYSZ_INS_VPKH = 2121 , SYSZ_INS_VPKLS = 2122 , SYSZ_INS_VPKLSF = 2123 , SYSZ_INS_VPKLSFS = 2124 , SYSZ_INS_VPKLSG = 2125 , SYSZ_INS_VPKLSGS = 2126 , SYSZ_INS_VPKLSH = 2127 , SYSZ_INS_VPKLSHS = 2128 , SYSZ_INS_VPKS = 2129 , SYSZ_INS_VPKSF = 2130 , SYSZ_INS_VPKSFS = 2131 , SYSZ_INS_VPKSG = 2132 , SYSZ_INS_VPKSGS = 2133 , SYSZ_INS_VPKSH = 2134 , SYSZ_INS_VPKSHS = 2135 , SYSZ_INS_VPKZ = 2136 , SYSZ_INS_VPOPCT = 2137 , SYSZ_INS_VPOPCTB = 2138 , SYSZ_INS_VPOPCTF = 2139 , SYSZ_INS_VPOPCTG = 2140 , SYSZ_INS_VPOPCTH = 2141 , SYSZ_INS_VPSOP = 2142 , SYSZ_INS_VREP = 2143 , SYSZ_INS_VREPB = 2144 , SYSZ_INS_VREPF = 2145 , SYSZ_INS_VREPG = 2146 , SYSZ_INS_VREPH = 2147 , SYSZ_INS_VREPI = 2148 , SYSZ_INS_VREPIB = 2149 , SYSZ_INS_VREPIF = 2150 , SYSZ_INS_VREPIG = 2151 , SYSZ_INS_VREPIH = 2152 , SYSZ_INS_VRP = 2153 , SYSZ_INS_VS = 2154 , SYSZ_INS_VSB = 2155 , SYSZ_INS_VSBCBI = 2156 , SYSZ_INS_VSBCBIQ = 2157 , SYSZ_INS_VSBI = 2158 , SYSZ_INS_VSBIQ = 2159 , SYSZ_INS_VSCBI = 2160 , SYSZ_INS_VSCBIB = 2161 , SYSZ_INS_VSCBIF = 2162 , SYSZ_INS_VSCBIG = 2163 , SYSZ_INS_VSCBIH = 2164 , SYSZ_INS_VSCBIQ = 2165 , SYSZ_INS_VSCEF = 2166 , SYSZ_INS_VSCEG = 2167 , SYSZ_INS_VSDP = 2168 , SYSZ_INS_VSEG = 2169 , SYSZ_INS_VSEGB = 2170 , SYSZ_INS_VSEGF = 2171 , SYSZ_INS_VSEGH = 2172 , SYSZ_INS_VSEL = 2173 , SYSZ_INS_VSF = 2174 , SYSZ_INS_VSG = 2175 , SYSZ_INS_VSH = 2176 , SYSZ_INS_VSL = 2177 , SYSZ_INS_VSLB = 2178 , SYSZ_INS_VSLDB = 2179 , SYSZ_INS_VSP = 2180 , SYSZ_INS_VSQ = 2181 , SYSZ_INS_VSRA = 2182 , SYSZ_INS_VSRAB = 2183 , SYSZ_INS_VSRL = 2184 , SYSZ_INS_VSRLB = 2185 , SYSZ_INS_VSRP = 2186 , SYSZ_INS_VST = 2187 , SYSZ_INS_VSTEB = 2188 , SYSZ_INS_VSTEF = 2189 , SYSZ_INS_VSTEG = 2190 , SYSZ_INS_VSTEH = 2191 , SYSZ_INS_VSTL = 2192 , SYSZ_INS_VSTM = 2193 , SYSZ_INS_VSTRC = 2194 , SYSZ_INS_VSTRCB = 2195 , SYSZ_INS_VSTRCBS = 2196 , SYSZ_INS_VSTRCF = 2197 , SYSZ_INS_VSTRCFS = 2198 , SYSZ_INS_VSTRCH = 2199 , SYSZ_INS_VSTRCHS = 2200 , SYSZ_INS_VSTRCZB = 2201 , SYSZ_INS_VSTRCZBS = 2202 , SYSZ_INS_VSTRCZF = 2203 , SYSZ_INS_VSTRCZFS = 2204 , SYSZ_INS_VSTRCZH = 2205 , SYSZ_INS_VSTRCZHS = 2206 , SYSZ_INS_VSTRL = 2207 , SYSZ_INS_VSTRLR = 2208 , SYSZ_INS_VSUM = 2209 , SYSZ_INS_VSUMB = 2210 , SYSZ_INS_VSUMG = 2211 , SYSZ_INS_VSUMGF = 2212 , SYSZ_INS_VSUMGH = 2213 , SYSZ_INS_VSUMH = 2214 , SYSZ_INS_VSUMQ = 2215 , SYSZ_INS_VSUMQF = 2216 , SYSZ_INS_VSUMQG = 2217 , SYSZ_INS_VTM = 2218 , SYSZ_INS_VTP = 2219 , SYSZ_INS_VUPH = 2220 , SYSZ_INS_VUPHB = 2221 , SYSZ_INS_VUPHF = 2222 , SYSZ_INS_VUPHH = 2223 , SYSZ_INS_VUPKZ = 2224 , SYSZ_INS_VUPL = 2225 , SYSZ_INS_VUPLB = 2226 , SYSZ_INS_VUPLF = 2227 , SYSZ_INS_VUPLH = 2228 , SYSZ_INS_VUPLHB = 2229 , SYSZ_INS_VUPLHF = 2230 , SYSZ_INS_VUPLHH = 2231 , SYSZ_INS_VUPLHW = 2232 , SYSZ_INS_VUPLL = 2233 , SYSZ_INS_VUPLLB = 2234 , SYSZ_INS_VUPLLF = 2235 , SYSZ_INS_VUPLLH = 2236 , SYSZ_INS_VX = 2237 , SYSZ_INS_VZERO = 2238 , SYSZ_INS_WCDGB = 2239 , SYSZ_INS_WCDLGB = 2240 , SYSZ_INS_WCGDB = 2241 , SYSZ_INS_WCLGDB = 2242 , SYSZ_INS_WFADB = 2243 , SYSZ_INS_WFASB = 2244 , SYSZ_INS_WFAXB = 2245 , SYSZ_INS_WFC = 2246 , SYSZ_INS_WFCDB = 2247 , SYSZ_INS_WFCEDB = 2248 , SYSZ_INS_WFCEDBS = 2249 , SYSZ_INS_WFCESB = 2250 , SYSZ_INS_WFCESBS = 2251 , SYSZ_INS_WFCEXB = 2252 , SYSZ_INS_WFCEXBS = 2253 , SYSZ_INS_WFCHDB = 2254 , SYSZ_INS_WFCHDBS = 2255 , SYSZ_INS_WFCHEDB = 2256 , SYSZ_INS_WFCHEDBS = 2257 , SYSZ_INS_WFCHESB = 2258 , SYSZ_INS_WFCHESBS = 2259 , SYSZ_INS_WFCHEXB = 2260 , SYSZ_INS_WFCHEXBS = 2261 , SYSZ_INS_WFCHSB = 2262 , SYSZ_INS_WFCHSBS = 2263 , SYSZ_INS_WFCHXB = 2264 , SYSZ_INS_WFCHXBS = 2265 , SYSZ_INS_WFCSB = 2266 , SYSZ_INS_WFCXB = 2267 , SYSZ_INS_WFDDB = 2268 , SYSZ_INS_WFDSB = 2269 , SYSZ_INS_WFDXB = 2270 , SYSZ_INS_WFIDB = 2271 , SYSZ_INS_WFISB = 2272 , SYSZ_INS_WFIXB = 2273 , SYSZ_INS_WFK = 2274 , SYSZ_INS_WFKDB = 2275 , SYSZ_INS_WFKEDB = 2276 , SYSZ_INS_WFKEDBS = 2277 , SYSZ_INS_WFKESB = 2278 , SYSZ_INS_WFKESBS = 2279 , SYSZ_INS_WFKEXB = 2280 , SYSZ_INS_WFKEXBS = 2281 , SYSZ_INS_WFKHDB = 2282 , SYSZ_INS_WFKHDBS = 2283 , SYSZ_INS_WFKHEDB = 2284 , SYSZ_INS_WFKHEDBS = 2285 , SYSZ_INS_WFKHESB = 2286 , SYSZ_INS_WFKHESBS = 2287 , SYSZ_INS_WFKHEXB = 2288 , SYSZ_INS_WFKHEXBS = 2289 , SYSZ_INS_WFKHSB = 2290 , SYSZ_INS_WFKHSBS = 2291 , SYSZ_INS_WFKHXB = 2292 , SYSZ_INS_WFKHXBS = 2293 , SYSZ_INS_WFKSB = 2294 , SYSZ_INS_WFKXB = 2295 , SYSZ_INS_WFLCDB = 2296 , SYSZ_INS_WFLCSB = 2297 , SYSZ_INS_WFLCXB = 2298 , SYSZ_INS_WFLLD = 2299 , SYSZ_INS_WFLLS = 2300 , SYSZ_INS_WFLNDB = 2301 , SYSZ_INS_WFLNSB = 2302 , SYSZ_INS_WFLNXB = 2303 , SYSZ_INS_WFLPDB = 2304 , SYSZ_INS_WFLPSB = 2305 , SYSZ_INS_WFLPXB = 2306 , SYSZ_INS_WFLRD = 2307 , SYSZ_INS_WFLRX = 2308 , SYSZ_INS_WFMADB = 2309 , SYSZ_INS_WFMASB = 2310 , SYSZ_INS_WFMAXB = 2311 , SYSZ_INS_WFMAXDB = 2312 , SYSZ_INS_WFMAXSB = 2313 , SYSZ_INS_WFMAXXB = 2314 , SYSZ_INS_WFMDB = 2315 , SYSZ_INS_WFMINDB = 2316 , SYSZ_INS_WFMINSB = 2317 , SYSZ_INS_WFMINXB = 2318 , SYSZ_INS_WFMSB = 2319 , SYSZ_INS_WFMSDB = 2320 , SYSZ_INS_WFMSSB = 2321 , SYSZ_INS_WFMSXB = 2322 , SYSZ_INS_WFMXB = 2323 , SYSZ_INS_WFNMADB = 2324 , SYSZ_INS_WFNMASB = 2325 , SYSZ_INS_WFNMAXB = 2326 , SYSZ_INS_WFNMSDB = 2327 , SYSZ_INS_WFNMSSB = 2328 , SYSZ_INS_WFNMSXB = 2329 , SYSZ_INS_WFPSODB = 2330 , SYSZ_INS_WFPSOSB = 2331 , SYSZ_INS_WFPSOXB = 2332 , SYSZ_INS_WFSDB = 2333 , SYSZ_INS_WFSQDB = 2334 , SYSZ_INS_WFSQSB = 2335 , SYSZ_INS_WFSQXB = 2336 , SYSZ_INS_WFSSB = 2337 , SYSZ_INS_WFSXB = 2338 , SYSZ_INS_WFTCIDB = 2339 , SYSZ_INS_WFTCISB = 2340 , SYSZ_INS_WFTCIXB = 2341 , SYSZ_INS_WLDEB = 2342 , SYSZ_INS_WLEDB = 2343 , SYSZ_INS_XSCH = 2344 , SYSZ_INS_ZAP = 2345 , SYSZ_INS_ENDING = 2346 , } # [repr (u32)] # [doc = " Group of SystemZ instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn_group { # [doc = "< = CS_GRP_INVALID"] SYSZ_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SYSZ_GRP_JUMP = 1 , SYSZ_GRP_DISTINCTOPS = 128 , SYSZ_GRP_FPEXTENSION = 129 , SYSZ_GRP_HIGHWORD = 130 , SYSZ_GRP_INTERLOCKEDACCESS1 = 131 , SYSZ_GRP_LOADSTOREONCOND = 132 , SYSZ_GRP_DFPPACKEDCONVERSION = 133 , SYSZ_GRP_DFPZONEDCONVERSION = 134 , SYSZ_GRP_ENHANCEDDAT2 = 135 , SYSZ_GRP_EXECUTIONHINT = 136 , SYSZ_GRP_GUARDEDSTORAGE = 137 , SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 , SYSZ_GRP_LOADANDTRAP = 139 , SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 , SYSZ_GRP_LOADSTOREONCOND2 = 141 , SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 , SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 , SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 , SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 , SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 , SYSZ_GRP_NOVECTOR = 149 , SYSZ_GRP_POPULATIONCOUNT = 150 , SYSZ_GRP_PROCESSORASSIST = 151 , SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 , SYSZ_GRP_TRANSACTIONALEXECUTION = 153 , SYSZ_GRP_VECTOR = 154 , SYSZ_GRP_VECTORENHANCEMENTS1 = 155 , SYSZ_GRP_VECTORPACKEDDECIMAL = 156 , SYSZ_GRP_ENDING = 157 , } # [repr (u32)] # [doc = " X86 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_reg { X86_REG_INVALID = 0 , X86_REG_AH = 1 , X86_REG_AL = 2 , X86_REG_AX = 3 , X86_REG_BH = 4 , X86_REG_BL = 5 , X86_REG_BP = 6 , X86_REG_BPL = 7 , X86_REG_BX = 8 , X86_REG_CH = 9 , X86_REG_CL = 10 , X86_REG_CS = 11 , X86_REG_CX = 12 , X86_REG_DH = 13 , X86_REG_DI = 14 , X86_REG_DIL = 15 , X86_REG_DL = 16 , X86_REG_DS = 17 , X86_REG_DX = 18 , X86_REG_EAX = 19 , X86_REG_EBP = 20 , X86_REG_EBX = 21 , X86_REG_ECX = 22 , X86_REG_EDI = 23 , X86_REG_EDX = 24 , X86_REG_EFLAGS = 25 , X86_REG_EIP = 26 , X86_REG_EIZ = 27 , X86_REG_ES = 28 , X86_REG_ESI = 29 , X86_REG_ESP = 30 , X86_REG_FPSW = 31 , X86_REG_FS = 32 , X86_REG_GS = 33 , X86_REG_IP = 34 , X86_REG_RAX = 35 , X86_REG_RBP = 36 , X86_REG_RBX = 37 , X86_REG_RCX = 38 , X86_REG_RDI = 39 , X86_REG_RDX = 40 , X86_REG_RIP = 41 , X86_REG_RIZ = 42 , X86_REG_RSI = 43 , X86_REG_RSP = 44 , X86_REG_SI = 45 , X86_REG_SIL = 46 , X86_REG_SP = 47 , X86_REG_SPL = 48 , X86_REG_SS = 49 , X86_REG_CR0 = 50 , X86_REG_CR1 = 51 , X86_REG_CR2 = 52 , X86_REG_CR3 = 53 , X86_REG_CR4 = 54 , X86_REG_CR5 = 55 , X86_REG_CR6 = 56 , X86_REG_CR7 = 57 , X86_REG_CR8 = 58 , X86_REG_CR9 = 59 , X86_REG_CR10 = 60 , X86_REG_CR11 = 61 , X86_REG_CR12 = 62 , X86_REG_CR13 = 63 , X86_REG_CR14 = 64 , X86_REG_CR15 = 65 , X86_REG_DR0 = 66 , X86_REG_DR1 = 67 , X86_REG_DR2 = 68 , X86_REG_DR3 = 69 , X86_REG_DR4 = 70 , X86_REG_DR5 = 71 , X86_REG_DR6 = 72 , X86_REG_DR7 = 73 , X86_REG_DR8 = 74 , X86_REG_DR9 = 75 , X86_REG_DR10 = 76 , X86_REG_DR11 = 77 , X86_REG_DR12 = 78 , X86_REG_DR13 = 79 , X86_REG_DR14 = 80 , X86_REG_DR15 = 81 , X86_REG_FP0 = 82 , X86_REG_FP1 = 83 , X86_REG_FP2 = 84 , X86_REG_FP3 = 85 , X86_REG_FP4 = 86 , X86_REG_FP5 = 87 , X86_REG_FP6 = 88 , X86_REG_FP7 = 89 , X86_REG_K0 = 90 , X86_REG_K1 = 91 , X86_REG_K2 = 92 , X86_REG_K3 = 93 , X86_REG_K4 = 94 , X86_REG_K5 = 95 , X86_REG_K6 = 96 , X86_REG_K7 = 97 , X86_REG_MM0 = 98 , X86_REG_MM1 = 99 , X86_REG_MM2 = 100 , X86_REG_MM3 = 101 , X86_REG_MM4 = 102 , X86_REG_MM5 = 103 , X86_REG_MM6 = 104 , X86_REG_MM7 = 105 , X86_REG_R8 = 106 , X86_REG_R9 = 107 , X86_REG_R10 = 108 , X86_REG_R11 = 109 , X86_REG_R12 = 110 , X86_REG_R13 = 111 , X86_REG_R14 = 112 , X86_REG_R15 = 113 , X86_REG_ST0 = 114 , X86_REG_ST1 = 115 , X86_REG_ST2 = 116 , X86_REG_ST3 = 117 , X86_REG_ST4 = 118 , X86_REG_ST5 = 119 , X86_REG_ST6 = 120 , X86_REG_ST7 = 121 , X86_REG_XMM0 = 122 , X86_REG_XMM1 = 123 , X86_REG_XMM2 = 124 , X86_REG_XMM3 = 125 , X86_REG_XMM4 = 126 , X86_REG_XMM5 = 127 , X86_REG_XMM6 = 128 , X86_REG_XMM7 = 129 , X86_REG_XMM8 = 130 , X86_REG_XMM9 = 131 , X86_REG_XMM10 = 132 , X86_REG_XMM11 = 133 , X86_REG_XMM12 = 134 , X86_REG_XMM13 = 135 , X86_REG_XMM14 = 136 , X86_REG_XMM15 = 137 , X86_REG_XMM16 = 138 , X86_REG_XMM17 = 139 , X86_REG_XMM18 = 140 , X86_REG_XMM19 = 141 , X86_REG_XMM20 = 142 , X86_REG_XMM21 = 143 , X86_REG_XMM22 = 144 , X86_REG_XMM23 = 145 , X86_REG_XMM24 = 146 , X86_REG_XMM25 = 147 , X86_REG_XMM26 = 148 , X86_REG_XMM27 = 149 , X86_REG_XMM28 = 150 , X86_REG_XMM29 = 151 , X86_REG_XMM30 = 152 , X86_REG_XMM31 = 153 , X86_REG_YMM0 = 154 , X86_REG_YMM1 = 155 , X86_REG_YMM2 = 156 , X86_REG_YMM3 = 157 , X86_REG_YMM4 = 158 , X86_REG_YMM5 = 159 , X86_REG_YMM6 = 160 , X86_REG_YMM7 = 161 , X86_REG_YMM8 = 162 , X86_REG_YMM9 = 163 , X86_REG_YMM10 = 164 , X86_REG_YMM11 = 165 , X86_REG_YMM12 = 166 , X86_REG_YMM13 = 167 , X86_REG_YMM14 = 168 , X86_REG_YMM15 = 169 , X86_REG_YMM16 = 170 , X86_REG_YMM17 = 171 , X86_REG_YMM18 = 172 , X86_REG_YMM19 = 173 , X86_REG_YMM20 = 174 , X86_REG_YMM21 = 175 , X86_REG_YMM22 = 176 , X86_REG_YMM23 = 177 , X86_REG_YMM24 = 178 , X86_REG_YMM25 = 179 , X86_REG_YMM26 = 180 , X86_REG_YMM27 = 181 , X86_REG_YMM28 = 182 , X86_REG_YMM29 = 183 , X86_REG_YMM30 = 184 , X86_REG_YMM31 = 185 , X86_REG_ZMM0 = 186 , X86_REG_ZMM1 = 187 , X86_REG_ZMM2 = 188 , X86_REG_ZMM3 = 189 , X86_REG_ZMM4 = 190 , X86_REG_ZMM5 = 191 , X86_REG_ZMM6 = 192 , X86_REG_ZMM7 = 193 , X86_REG_ZMM8 = 194 , X86_REG_ZMM9 = 195 , X86_REG_ZMM10 = 196 , X86_REG_ZMM11 = 197 , X86_REG_ZMM12 = 198 , X86_REG_ZMM13 = 199 , X86_REG_ZMM14 = 200 , X86_REG_ZMM15 = 201 , X86_REG_ZMM16 = 202 , X86_REG_ZMM17 = 203 , X86_REG_ZMM18 = 204 , X86_REG_ZMM19 = 205 , X86_REG_ZMM20 = 206 , X86_REG_ZMM21 = 207 , X86_REG_ZMM22 = 208 , X86_REG_ZMM23 = 209 , X86_REG_ZMM24 = 210 , X86_REG_ZMM25 = 211 , X86_REG_ZMM26 = 212 , X86_REG_ZMM27 = 213 , X86_REG_ZMM28 = 214 , X86_REG_ZMM29 = 215 , X86_REG_ZMM30 = 216 , X86_REG_ZMM31 = 217 , X86_REG_R8B = 218 , X86_REG_R9B = 219 , X86_REG_R10B = 220 , X86_REG_R11B = 221 , X86_REG_R12B = 222 , X86_REG_R13B = 223 , X86_REG_R14B = 224 , X86_REG_R15B = 225 , X86_REG_R8D = 226 , X86_REG_R9D = 227 , X86_REG_R10D = 228 , X86_REG_R11D = 229 , X86_REG_R12D = 230 , X86_REG_R13D = 231 , X86_REG_R14D = 232 , X86_REG_R15D = 233 , X86_REG_R8W = 234 , X86_REG_R9W = 235 , X86_REG_R10W = 236 , X86_REG_R11W = 237 , X86_REG_R12W = 238 , X86_REG_R13W = 239 , X86_REG_R14W = 240 , X86_REG_R15W = 241 , X86_REG_BND0 = 242 , X86_REG_BND1 = 243 , X86_REG_BND2 = 244 , X86_REG_BND3 = 245 , X86_REG_ENDING = 246 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] X86_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] X86_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] X86_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] X86_OP_MEM = 3 , } # [repr (u32)] # [doc = " XOP Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_xop_cc { # [doc = "< Uninitialized."] X86_XOP_CC_INVALID = 0 , X86_XOP_CC_LT = 1 , X86_XOP_CC_LE = 2 , X86_XOP_CC_GT = 3 , X86_XOP_CC_GE = 4 , X86_XOP_CC_EQ = 5 , X86_XOP_CC_NEQ = 6 , X86_XOP_CC_FALSE = 7 , X86_XOP_CC_TRUE = 8 , } # [repr (u32)] # [doc = " AVX broadcast type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_bcast { # [doc = "< Uninitialized."] X86_AVX_BCAST_INVALID = 0 , # [doc = "< AVX512 broadcast type {1to2}"] X86_AVX_BCAST_2 = 1 , # [doc = "< AVX512 broadcast type {1to4}"] X86_AVX_BCAST_4 = 2 , # [doc = "< AVX512 broadcast type {1to8}"] X86_AVX_BCAST_8 = 3 , # [doc = "< AVX512 broadcast type {1to16}"] X86_AVX_BCAST_16 = 4 , } # [repr (u32)] # [doc = " SSE Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_sse_cc { # [doc = "< Uninitialized."] X86_SSE_CC_INVALID = 0 , X86_SSE_CC_EQ = 1 , X86_SSE_CC_LT = 2 , X86_SSE_CC_LE = 3 , X86_SSE_CC_UNORD = 4 , X86_SSE_CC_NEQ = 5 , X86_SSE_CC_NLT = 6 , X86_SSE_CC_NLE = 7 , X86_SSE_CC_ORD = 8 , } # [repr (u32)] # [doc = " AVX Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_cc { # [doc = "< Uninitialized."] X86_AVX_CC_INVALID = 0 , X86_AVX_CC_EQ = 1 , X86_AVX_CC_LT = 2 , X86_AVX_CC_LE = 3 , X86_AVX_CC_UNORD = 4 , X86_AVX_CC_NEQ = 5 , X86_AVX_CC_NLT = 6 , X86_AVX_CC_NLE = 7 , X86_AVX_CC_ORD = 8 , X86_AVX_CC_EQ_UQ = 9 , X86_AVX_CC_NGE = 10 , X86_AVX_CC_NGT = 11 , X86_AVX_CC_FALSE = 12 , X86_AVX_CC_NEQ_OQ = 13 , X86_AVX_CC_GE = 14 , X86_AVX_CC_GT = 15 , X86_AVX_CC_TRUE = 16 , X86_AVX_CC_EQ_OS = 17 , X86_AVX_CC_LT_OQ = 18 , X86_AVX_CC_LE_OQ = 19 , X86_AVX_CC_UNORD_S = 20 , X86_AVX_CC_NEQ_US = 21 , X86_AVX_CC_NLT_UQ = 22 , X86_AVX_CC_NLE_UQ = 23 , X86_AVX_CC_ORD_S = 24 , X86_AVX_CC_EQ_US = 25 , X86_AVX_CC_NGE_UQ = 26 , X86_AVX_CC_NGT_UQ = 27 , X86_AVX_CC_FALSE_OS = 28 , X86_AVX_CC_NEQ_OS = 29 , X86_AVX_CC_GE_OQ = 30 , X86_AVX_CC_GT_OQ = 31 , X86_AVX_CC_TRUE_US = 32 , } # [repr (u32)] # [doc = " AVX static rounding mode type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_rm { # [doc = "< Uninitialized."] X86_AVX_RM_INVALID = 0 , # [doc = "< Round to nearest"] X86_AVX_RM_RN = 1 , # [doc = "< Round down"] X86_AVX_RM_RD = 2 , # [doc = "< Round up"] X86_AVX_RM_RU = 3 , # [doc = "< Round toward zero"] X86_AVX_RM_RZ = 4 , } impl x86_prefix { pub const X86_PREFIX_REPE : x86_prefix = x86_prefix :: X86_PREFIX_REP ; } # [repr (u32)] # [doc = " Instruction prefixes - to be used in cs_x86.prefix[]"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_prefix { # [doc = "< lock (cs_x86.prefix[0]"] X86_PREFIX_LOCK = 240 , # [doc = "< rep (cs_x86.prefix[0]"] X86_PREFIX_REP = 243 , # [doc = "< repne/repnz (cs_x86.prefix[0]"] X86_PREFIX_REPNE = 242 , # [doc = "< segment override CS (cs_x86.prefix[1]"] X86_PREFIX_CS = 46 , # [doc = "< segment override SS (cs_x86.prefix[1]"] X86_PREFIX_SS = 54 , # [doc = "< segment override DS (cs_x86.prefix[1]"] X86_PREFIX_DS = 62 , # [doc = "< segment override ES (cs_x86.prefix[1]"] X86_PREFIX_ES = 38 , # [doc = "< segment override FS (cs_x86.prefix[1]"] X86_PREFIX_FS = 100 , # [doc = "< segment override GS (cs_x86.prefix[1]"] X86_PREFIX_GS = 101 , # [doc = "< operand-size override (cs_x86.prefix[2]"] X86_PREFIX_OPSIZE = 102 , # [doc = "< address-size override (cs_x86.prefix[3]"] X86_PREFIX_ADDRSIZE = 103 , } # [doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct x86_op_mem { # [doc = "< segment register (or X86_REG_INVALID if irrelevant)"] pub segment : x86_reg , # [doc = "< base register (or X86_REG_INVALID if irrelevant)"] pub base : x86_reg , # [doc = "< index register (or X86_REG_INVALID if irrelevant)"] pub index : x86_reg , # [doc = "< scale for index register"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of x86_op_mem"] [:: std :: mem :: size_of :: < x86_op_mem > () - 24usize] ; ["Alignment of x86_op_mem"] [:: std :: mem :: align_of :: < x86_op_mem > () - 8usize] ; ["Offset of field: x86_op_mem::segment"] [:: std :: mem :: offset_of ! (x86_op_mem , segment) - 0usize] ; ["Offset of field: x86_op_mem::base"] [:: std :: mem :: offset_of ! (x86_op_mem , base) - 4usize] ; ["Offset of field: x86_op_mem::index"] [:: std :: mem :: offset_of ! (x86_op_mem , index) - 8usize] ; ["Offset of field: x86_op_mem::scale"] [:: std :: mem :: offset_of ! (x86_op_mem , scale) - 12usize] ; ["Offset of field: x86_op_mem::disp"] [:: std :: mem :: offset_of ! (x86_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86_op { # [doc = "< operand type"] pub type_ : x86_op_type , pub __bindgen_anon_1 : cs_x86_op__bindgen_ty_1 , # [doc = " size of this operand (in bytes)."] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " AVX broadcast type, or 0 if irrelevant"] pub avx_bcast : x86_avx_bcast , # [doc = " AVX zero opmask {z}"] pub avx_zero_opmask : bool , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : x86_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : x86_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op"] [:: std :: mem :: size_of :: < cs_x86_op > () - 48usize] ; ["Alignment of cs_x86_op"] [:: std :: mem :: align_of :: < cs_x86_op > () - 8usize] ; ["Offset of field: cs_x86_op::type_"] [:: std :: mem :: offset_of ! (cs_x86_op , type_) - 0usize] ; ["Offset of field: cs_x86_op::size"] [:: std :: mem :: offset_of ! (cs_x86_op , size) - 32usize] ; ["Offset of field: cs_x86_op::access"] [:: std :: mem :: offset_of ! (cs_x86_op , access) - 33usize] ; ["Offset of field: cs_x86_op::avx_bcast"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_bcast) - 36usize] ; ["Offset of field: cs_x86_op::avx_zero_opmask"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_zero_opmask) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask) } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_x86_encoding { # [doc = " ModR/M offset, or 0 when irrelevant"] pub modrm_offset : u8 , # [doc = " Displacement offset, or 0 when irrelevant."] pub disp_offset : u8 , pub disp_size : u8 , # [doc = " Immediate offset, or 0 when irrelevant."] pub imm_offset : u8 , pub imm_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_encoding"] [:: std :: mem :: size_of :: < cs_x86_encoding > () - 5usize] ; ["Alignment of cs_x86_encoding"] [:: std :: mem :: align_of :: < cs_x86_encoding > () - 1usize] ; ["Offset of field: cs_x86_encoding::modrm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , modrm_offset) - 0usize] ; ["Offset of field: cs_x86_encoding::disp_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_offset) - 1usize] ; ["Offset of field: cs_x86_encoding::disp_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_size) - 2usize] ; ["Offset of field: cs_x86_encoding::imm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_offset) - 3usize] ; ["Offset of field: cs_x86_encoding::imm_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_size) - 4usize] ; } ; # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86 { # [doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"] pub prefix : [u8 ; 4usize] , # [doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."] pub opcode : [u8 ; 4usize] , # [doc = " REX prefix: only a non-zero value is relevant for x86_64"] pub rex : u8 , # [doc = " Address size, which can be overridden with above prefix[5]."] pub addr_size : u8 , # [doc = " ModR/M byte"] pub modrm : u8 , # [doc = " SIB value, or 0 when irrelevant."] pub sib : u8 , # [doc = " Displacement value, valid if encoding.disp_offset != 0"] pub disp : i64 , # [doc = " SIB index register, or X86_REG_INVALID when irrelevant."] pub sib_index : x86_reg , # [doc = " SIB scale, only applicable if sib_index is valid."] pub sib_scale : i8 , # [doc = " SIB base register, or X86_REG_INVALID when irrelevant."] pub sib_base : x86_reg , # [doc = " XOP Code Condition"] pub xop_cc : x86_xop_cc , # [doc = " SSE Code Condition"] pub sse_cc : x86_sse_cc , # [doc = " AVX Code Condition"] pub avx_cc : x86_avx_cc , # [doc = " AVX Suppress all Exception"] pub avx_sae : bool , # [doc = " AVX static rounding mode"] pub avx_rm : x86_avx_rm , pub __bindgen_anon_1 : cs_x86__bindgen_ty_1 , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_x86_op ; 8usize] , # [doc = "< encoding information"] pub encoding : cs_x86_encoding , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86__bindgen_ty_1 { # [doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"] pub eflags : u64 , # [doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"] pub fpu_flags : u64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_x86__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86__bindgen_ty_1::eflags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , eflags) - 0usize] ; ["Offset of field: cs_x86__bindgen_ty_1::fpu_flags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , fpu_flags) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86"] [:: std :: mem :: size_of :: < cs_x86 > () - 464usize] ; ["Alignment of cs_x86"] [:: std :: mem :: align_of :: < cs_x86 > () - 8usize] ; ["Offset of field: cs_x86::prefix"] [:: std :: mem :: offset_of ! (cs_x86 , prefix) - 0usize] ; ["Offset of field: cs_x86::opcode"] [:: std :: mem :: offset_of ! (cs_x86 , opcode) - 4usize] ; ["Offset of field: cs_x86::rex"] [:: std :: mem :: offset_of ! (cs_x86 , rex) - 8usize] ; ["Offset of field: cs_x86::addr_size"] [:: std :: mem :: offset_of ! (cs_x86 , addr_size) - 9usize] ; ["Offset of field: cs_x86::modrm"] [:: std :: mem :: offset_of ! (cs_x86 , modrm) - 10usize] ; ["Offset of field: cs_x86::sib"] [:: std :: mem :: offset_of ! (cs_x86 , sib) - 11usize] ; ["Offset of field: cs_x86::disp"] [:: std :: mem :: offset_of ! (cs_x86 , disp) - 16usize] ; ["Offset of field: cs_x86::sib_index"] [:: std :: mem :: offset_of ! (cs_x86 , sib_index) - 24usize] ; ["Offset of field: cs_x86::sib_scale"] [:: std :: mem :: offset_of ! (cs_x86 , sib_scale) - 28usize] ; ["Offset of field: cs_x86::sib_base"] [:: std :: mem :: offset_of ! (cs_x86 , sib_base) - 32usize] ; ["Offset of field: cs_x86::xop_cc"] [:: std :: mem :: offset_of ! (cs_x86 , xop_cc) - 36usize] ; ["Offset of field: cs_x86::sse_cc"] [:: std :: mem :: offset_of ! (cs_x86 , sse_cc) - 40usize] ; ["Offset of field: cs_x86::avx_cc"] [:: std :: mem :: offset_of ! (cs_x86 , avx_cc) - 44usize] ; ["Offset of field: cs_x86::avx_sae"] [:: std :: mem :: offset_of ! (cs_x86 , avx_sae) - 48usize] ; ["Offset of field: cs_x86::avx_rm"] [:: std :: mem :: offset_of ! (cs_x86 , avx_rm) - 52usize] ; ["Offset of field: cs_x86::op_count"] [:: std :: mem :: offset_of ! (cs_x86 , op_count) - 64usize] ; ["Offset of field: cs_x86::operands"] [:: std :: mem :: offset_of ! (cs_x86 , operands) - 72usize] ; ["Offset of field: cs_x86::encoding"] [:: std :: mem :: offset_of ! (cs_x86 , encoding) - 456usize] ; } ; impl :: std :: fmt :: Debug for cs_x86 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding) } } # [repr (u32)] # [doc = " X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn { X86_INS_INVALID = 0 , X86_INS_AAA = 1 , X86_INS_AAD = 2 , X86_INS_AAM = 3 , X86_INS_AAS = 4 , X86_INS_FABS = 5 , X86_INS_ADC = 6 , X86_INS_ADCX = 7 , X86_INS_ADD = 8 , X86_INS_ADDPD = 9 , X86_INS_ADDPS = 10 , X86_INS_ADDSD = 11 , X86_INS_ADDSS = 12 , X86_INS_ADDSUBPD = 13 , X86_INS_ADDSUBPS = 14 , X86_INS_FADD = 15 , X86_INS_FIADD = 16 , X86_INS_ADOX = 17 , X86_INS_AESDECLAST = 18 , X86_INS_AESDEC = 19 , X86_INS_AESENCLAST = 20 , X86_INS_AESENC = 21 , X86_INS_AESIMC = 22 , X86_INS_AESKEYGENASSIST = 23 , X86_INS_AND = 24 , X86_INS_ANDN = 25 , X86_INS_ANDNPD = 26 , X86_INS_ANDNPS = 27 , X86_INS_ANDPD = 28 , X86_INS_ANDPS = 29 , X86_INS_ARPL = 30 , X86_INS_BEXTR = 31 , X86_INS_BLCFILL = 32 , X86_INS_BLCI = 33 , X86_INS_BLCIC = 34 , X86_INS_BLCMSK = 35 , X86_INS_BLCS = 36 , X86_INS_BLENDPD = 37 , X86_INS_BLENDPS = 38 , X86_INS_BLENDVPD = 39 , X86_INS_BLENDVPS = 40 , X86_INS_BLSFILL = 41 , X86_INS_BLSI = 42 , X86_INS_BLSIC = 43 , X86_INS_BLSMSK = 44 , X86_INS_BLSR = 45 , X86_INS_BNDCL = 46 , X86_INS_BNDCN = 47 , X86_INS_BNDCU = 48 , X86_INS_BNDLDX = 49 , X86_INS_BNDMK = 50 , X86_INS_BNDMOV = 51 , X86_INS_BNDSTX = 52 , X86_INS_BOUND = 53 , X86_INS_BSF = 54 , X86_INS_BSR = 55 , X86_INS_BSWAP = 56 , X86_INS_BT = 57 , X86_INS_BTC = 58 , X86_INS_BTR = 59 , X86_INS_BTS = 60 , X86_INS_BZHI = 61 , X86_INS_CALL = 62 , X86_INS_CBW = 63 , X86_INS_CDQ = 64 , X86_INS_CDQE = 65 , X86_INS_FCHS = 66 , X86_INS_CLAC = 67 , X86_INS_CLC = 68 , X86_INS_CLD = 69 , X86_INS_CLDEMOTE = 70 , X86_INS_CLFLUSH = 71 , X86_INS_CLFLUSHOPT = 72 , X86_INS_CLGI = 73 , X86_INS_CLI = 74 , X86_INS_CLRSSBSY = 75 , X86_INS_CLTS = 76 , X86_INS_CLWB = 77 , X86_INS_CLZERO = 78 , X86_INS_CMC = 79 , X86_INS_CMOVA = 80 , X86_INS_CMOVAE = 81 , X86_INS_CMOVB = 82 , X86_INS_CMOVBE = 83 , X86_INS_FCMOVBE = 84 , X86_INS_FCMOVB = 85 , X86_INS_CMOVE = 86 , X86_INS_FCMOVE = 87 , X86_INS_CMOVG = 88 , X86_INS_CMOVGE = 89 , X86_INS_CMOVL = 90 , X86_INS_CMOVLE = 91 , X86_INS_FCMOVNBE = 92 , X86_INS_FCMOVNB = 93 , X86_INS_CMOVNE = 94 , X86_INS_FCMOVNE = 95 , X86_INS_CMOVNO = 96 , X86_INS_CMOVNP = 97 , X86_INS_FCMOVNU = 98 , X86_INS_FCMOVNP = 99 , X86_INS_CMOVNS = 100 , X86_INS_CMOVO = 101 , X86_INS_CMOVP = 102 , X86_INS_FCMOVU = 103 , X86_INS_CMOVS = 104 , X86_INS_CMP = 105 , X86_INS_CMPPD = 106 , X86_INS_CMPPS = 107 , X86_INS_CMPSB = 108 , X86_INS_CMPSD = 109 , X86_INS_CMPSQ = 110 , X86_INS_CMPSS = 111 , X86_INS_CMPSW = 112 , X86_INS_CMPXCHG16B = 113 , X86_INS_CMPXCHG = 114 , X86_INS_CMPXCHG8B = 115 , X86_INS_COMISD = 116 , X86_INS_COMISS = 117 , X86_INS_FCOMP = 118 , X86_INS_FCOMPI = 119 , X86_INS_FCOMI = 120 , X86_INS_FCOM = 121 , X86_INS_FCOS = 122 , X86_INS_CPUID = 123 , X86_INS_CQO = 124 , X86_INS_CRC32 = 125 , X86_INS_CVTDQ2PD = 126 , X86_INS_CVTDQ2PS = 127 , X86_INS_CVTPD2DQ = 128 , X86_INS_CVTPD2PS = 129 , X86_INS_CVTPS2DQ = 130 , X86_INS_CVTPS2PD = 131 , X86_INS_CVTSD2SI = 132 , X86_INS_CVTSD2SS = 133 , X86_INS_CVTSI2SD = 134 , X86_INS_CVTSI2SS = 135 , X86_INS_CVTSS2SD = 136 , X86_INS_CVTSS2SI = 137 , X86_INS_CVTTPD2DQ = 138 , X86_INS_CVTTPS2DQ = 139 , X86_INS_CVTTSD2SI = 140 , X86_INS_CVTTSS2SI = 141 , X86_INS_CWD = 142 , X86_INS_CWDE = 143 , X86_INS_DAA = 144 , X86_INS_DAS = 145 , X86_INS_DATA16 = 146 , X86_INS_DEC = 147 , X86_INS_DIV = 148 , X86_INS_DIVPD = 149 , X86_INS_DIVPS = 150 , X86_INS_FDIVR = 151 , X86_INS_FIDIVR = 152 , X86_INS_FDIVRP = 153 , X86_INS_DIVSD = 154 , X86_INS_DIVSS = 155 , X86_INS_FDIV = 156 , X86_INS_FIDIV = 157 , X86_INS_FDIVP = 158 , X86_INS_DPPD = 159 , X86_INS_DPPS = 160 , X86_INS_ENCLS = 161 , X86_INS_ENCLU = 162 , X86_INS_ENCLV = 163 , X86_INS_ENDBR32 = 164 , X86_INS_ENDBR64 = 165 , X86_INS_ENTER = 166 , X86_INS_EXTRACTPS = 167 , X86_INS_EXTRQ = 168 , X86_INS_F2XM1 = 169 , X86_INS_LCALL = 170 , X86_INS_LJMP = 171 , X86_INS_JMP = 172 , X86_INS_FBLD = 173 , X86_INS_FBSTP = 174 , X86_INS_FCOMPP = 175 , X86_INS_FDECSTP = 176 , X86_INS_FDISI8087_NOP = 177 , X86_INS_FEMMS = 178 , X86_INS_FENI8087_NOP = 179 , X86_INS_FFREE = 180 , X86_INS_FFREEP = 181 , X86_INS_FICOM = 182 , X86_INS_FICOMP = 183 , X86_INS_FINCSTP = 184 , X86_INS_FLDCW = 185 , X86_INS_FLDENV = 186 , X86_INS_FLDL2E = 187 , X86_INS_FLDL2T = 188 , X86_INS_FLDLG2 = 189 , X86_INS_FLDLN2 = 190 , X86_INS_FLDPI = 191 , X86_INS_FNCLEX = 192 , X86_INS_FNINIT = 193 , X86_INS_FNOP = 194 , X86_INS_FNSTCW = 195 , X86_INS_FNSTSW = 196 , X86_INS_FPATAN = 197 , X86_INS_FSTPNCE = 198 , X86_INS_FPREM = 199 , X86_INS_FPREM1 = 200 , X86_INS_FPTAN = 201 , X86_INS_FRNDINT = 202 , X86_INS_FRSTOR = 203 , X86_INS_FNSAVE = 204 , X86_INS_FSCALE = 205 , X86_INS_FSETPM = 206 , X86_INS_FSINCOS = 207 , X86_INS_FNSTENV = 208 , X86_INS_FXAM = 209 , X86_INS_FXRSTOR = 210 , X86_INS_FXRSTOR64 = 211 , X86_INS_FXSAVE = 212 , X86_INS_FXSAVE64 = 213 , X86_INS_FXTRACT = 214 , X86_INS_FYL2X = 215 , X86_INS_FYL2XP1 = 216 , X86_INS_GETSEC = 217 , X86_INS_GF2P8AFFINEINVQB = 218 , X86_INS_GF2P8AFFINEQB = 219 , X86_INS_GF2P8MULB = 220 , X86_INS_HADDPD = 221 , X86_INS_HADDPS = 222 , X86_INS_HLT = 223 , X86_INS_HSUBPD = 224 , X86_INS_HSUBPS = 225 , X86_INS_IDIV = 226 , X86_INS_FILD = 227 , X86_INS_IMUL = 228 , X86_INS_IN = 229 , X86_INS_INC = 230 , X86_INS_INCSSPD = 231 , X86_INS_INCSSPQ = 232 , X86_INS_INSB = 233 , X86_INS_INSERTPS = 234 , X86_INS_INSERTQ = 235 , X86_INS_INSD = 236 , X86_INS_INSW = 237 , X86_INS_INT = 238 , X86_INS_INT1 = 239 , X86_INS_INT3 = 240 , X86_INS_INTO = 241 , X86_INS_INVD = 242 , X86_INS_INVEPT = 243 , X86_INS_INVLPG = 244 , X86_INS_INVLPGA = 245 , X86_INS_INVPCID = 246 , X86_INS_INVVPID = 247 , X86_INS_IRET = 248 , X86_INS_IRETD = 249 , X86_INS_IRETQ = 250 , X86_INS_FISTTP = 251 , X86_INS_FIST = 252 , X86_INS_FISTP = 253 , X86_INS_JAE = 254 , X86_INS_JA = 255 , X86_INS_JBE = 256 , X86_INS_JB = 257 , X86_INS_JCXZ = 258 , X86_INS_JECXZ = 259 , X86_INS_JE = 260 , X86_INS_JGE = 261 , X86_INS_JG = 262 , X86_INS_JLE = 263 , X86_INS_JL = 264 , X86_INS_JNE = 265 , X86_INS_JNO = 266 , X86_INS_JNP = 267 , X86_INS_JNS = 268 , X86_INS_JO = 269 , X86_INS_JP = 270 , X86_INS_JRCXZ = 271 , X86_INS_JS = 272 , X86_INS_KADDB = 273 , X86_INS_KADDD = 274 , X86_INS_KADDQ = 275 , X86_INS_KADDW = 276 , X86_INS_KANDB = 277 , X86_INS_KANDD = 278 , X86_INS_KANDNB = 279 , X86_INS_KANDND = 280 , X86_INS_KANDNQ = 281 , X86_INS_KANDNW = 282 , X86_INS_KANDQ = 283 , X86_INS_KANDW = 284 , X86_INS_KMOVB = 285 , X86_INS_KMOVD = 286 , X86_INS_KMOVQ = 287 , X86_INS_KMOVW = 288 , X86_INS_KNOTB = 289 , X86_INS_KNOTD = 290 , X86_INS_KNOTQ = 291 , X86_INS_KNOTW = 292 , X86_INS_KORB = 293 , X86_INS_KORD = 294 , X86_INS_KORQ = 295 , X86_INS_KORTESTB = 296 , X86_INS_KORTESTD = 297 , X86_INS_KORTESTQ = 298 , X86_INS_KORTESTW = 299 , X86_INS_KORW = 300 , X86_INS_KSHIFTLB = 301 , X86_INS_KSHIFTLD = 302 , X86_INS_KSHIFTLQ = 303 , X86_INS_KSHIFTLW = 304 , X86_INS_KSHIFTRB = 305 , X86_INS_KSHIFTRD = 306 , X86_INS_KSHIFTRQ = 307 , X86_INS_KSHIFTRW = 308 , X86_INS_KTESTB = 309 , X86_INS_KTESTD = 310 , X86_INS_KTESTQ = 311 , X86_INS_KTESTW = 312 , X86_INS_KUNPCKBW = 313 , X86_INS_KUNPCKDQ = 314 , X86_INS_KUNPCKWD = 315 , X86_INS_KXNORB = 316 , X86_INS_KXNORD = 317 , X86_INS_KXNORQ = 318 , X86_INS_KXNORW = 319 , X86_INS_KXORB = 320 , X86_INS_KXORD = 321 , X86_INS_KXORQ = 322 , X86_INS_KXORW = 323 , X86_INS_LAHF = 324 , X86_INS_LAR = 325 , X86_INS_LDDQU = 326 , X86_INS_LDMXCSR = 327 , X86_INS_LDS = 328 , X86_INS_FLDZ = 329 , X86_INS_FLD1 = 330 , X86_INS_FLD = 331 , X86_INS_LEA = 332 , X86_INS_LEAVE = 333 , X86_INS_LES = 334 , X86_INS_LFENCE = 335 , X86_INS_LFS = 336 , X86_INS_LGDT = 337 , X86_INS_LGS = 338 , X86_INS_LIDT = 339 , X86_INS_LLDT = 340 , X86_INS_LLWPCB = 341 , X86_INS_LMSW = 342 , X86_INS_LOCK = 343 , X86_INS_LODSB = 344 , X86_INS_LODSD = 345 , X86_INS_LODSQ = 346 , X86_INS_LODSW = 347 , X86_INS_LOOP = 348 , X86_INS_LOOPE = 349 , X86_INS_LOOPNE = 350 , X86_INS_RETF = 351 , X86_INS_RETFQ = 352 , X86_INS_LSL = 353 , X86_INS_LSS = 354 , X86_INS_LTR = 355 , X86_INS_LWPINS = 356 , X86_INS_LWPVAL = 357 , X86_INS_LZCNT = 358 , X86_INS_MASKMOVDQU = 359 , X86_INS_MAXPD = 360 , X86_INS_MAXPS = 361 , X86_INS_MAXSD = 362 , X86_INS_MAXSS = 363 , X86_INS_MFENCE = 364 , X86_INS_MINPD = 365 , X86_INS_MINPS = 366 , X86_INS_MINSD = 367 , X86_INS_MINSS = 368 , X86_INS_CVTPD2PI = 369 , X86_INS_CVTPI2PD = 370 , X86_INS_CVTPI2PS = 371 , X86_INS_CVTPS2PI = 372 , X86_INS_CVTTPD2PI = 373 , X86_INS_CVTTPS2PI = 374 , X86_INS_EMMS = 375 , X86_INS_MASKMOVQ = 376 , X86_INS_MOVD = 377 , X86_INS_MOVQ = 378 , X86_INS_MOVDQ2Q = 379 , X86_INS_MOVNTQ = 380 , X86_INS_MOVQ2DQ = 381 , X86_INS_PABSB = 382 , X86_INS_PABSD = 383 , X86_INS_PABSW = 384 , X86_INS_PACKSSDW = 385 , X86_INS_PACKSSWB = 386 , X86_INS_PACKUSWB = 387 , X86_INS_PADDB = 388 , X86_INS_PADDD = 389 , X86_INS_PADDQ = 390 , X86_INS_PADDSB = 391 , X86_INS_PADDSW = 392 , X86_INS_PADDUSB = 393 , X86_INS_PADDUSW = 394 , X86_INS_PADDW = 395 , X86_INS_PALIGNR = 396 , X86_INS_PANDN = 397 , X86_INS_PAND = 398 , X86_INS_PAVGB = 399 , X86_INS_PAVGW = 400 , X86_INS_PCMPEQB = 401 , X86_INS_PCMPEQD = 402 , X86_INS_PCMPEQW = 403 , X86_INS_PCMPGTB = 404 , X86_INS_PCMPGTD = 405 , X86_INS_PCMPGTW = 406 , X86_INS_PEXTRW = 407 , X86_INS_PHADDD = 408 , X86_INS_PHADDSW = 409 , X86_INS_PHADDW = 410 , X86_INS_PHSUBD = 411 , X86_INS_PHSUBSW = 412 , X86_INS_PHSUBW = 413 , X86_INS_PINSRW = 414 , X86_INS_PMADDUBSW = 415 , X86_INS_PMADDWD = 416 , X86_INS_PMAXSW = 417 , X86_INS_PMAXUB = 418 , X86_INS_PMINSW = 419 , X86_INS_PMINUB = 420 , X86_INS_PMOVMSKB = 421 , X86_INS_PMULHRSW = 422 , X86_INS_PMULHUW = 423 , X86_INS_PMULHW = 424 , X86_INS_PMULLW = 425 , X86_INS_PMULUDQ = 426 , X86_INS_POR = 427 , X86_INS_PSADBW = 428 , X86_INS_PSHUFB = 429 , X86_INS_PSHUFW = 430 , X86_INS_PSIGNB = 431 , X86_INS_PSIGND = 432 , X86_INS_PSIGNW = 433 , X86_INS_PSLLD = 434 , X86_INS_PSLLQ = 435 , X86_INS_PSLLW = 436 , X86_INS_PSRAD = 437 , X86_INS_PSRAW = 438 , X86_INS_PSRLD = 439 , X86_INS_PSRLQ = 440 , X86_INS_PSRLW = 441 , X86_INS_PSUBB = 442 , X86_INS_PSUBD = 443 , X86_INS_PSUBQ = 444 , X86_INS_PSUBSB = 445 , X86_INS_PSUBSW = 446 , X86_INS_PSUBUSB = 447 , X86_INS_PSUBUSW = 448 , X86_INS_PSUBW = 449 , X86_INS_PUNPCKHBW = 450 , X86_INS_PUNPCKHDQ = 451 , X86_INS_PUNPCKHWD = 452 , X86_INS_PUNPCKLBW = 453 , X86_INS_PUNPCKLDQ = 454 , X86_INS_PUNPCKLWD = 455 , X86_INS_PXOR = 456 , X86_INS_MONITORX = 457 , X86_INS_MONITOR = 458 , X86_INS_MONTMUL = 459 , X86_INS_MOV = 460 , X86_INS_MOVABS = 461 , X86_INS_MOVAPD = 462 , X86_INS_MOVAPS = 463 , X86_INS_MOVBE = 464 , X86_INS_MOVDDUP = 465 , X86_INS_MOVDIR64B = 466 , X86_INS_MOVDIRI = 467 , X86_INS_MOVDQA = 468 , X86_INS_MOVDQU = 469 , X86_INS_MOVHLPS = 470 , X86_INS_MOVHPD = 471 , X86_INS_MOVHPS = 472 , X86_INS_MOVLHPS = 473 , X86_INS_MOVLPD = 474 , X86_INS_MOVLPS = 475 , X86_INS_MOVMSKPD = 476 , X86_INS_MOVMSKPS = 477 , X86_INS_MOVNTDQA = 478 , X86_INS_MOVNTDQ = 479 , X86_INS_MOVNTI = 480 , X86_INS_MOVNTPD = 481 , X86_INS_MOVNTPS = 482 , X86_INS_MOVNTSD = 483 , X86_INS_MOVNTSS = 484 , X86_INS_MOVSB = 485 , X86_INS_MOVSD = 486 , X86_INS_MOVSHDUP = 487 , X86_INS_MOVSLDUP = 488 , X86_INS_MOVSQ = 489 , X86_INS_MOVSS = 490 , X86_INS_MOVSW = 491 , X86_INS_MOVSX = 492 , X86_INS_MOVSXD = 493 , X86_INS_MOVUPD = 494 , X86_INS_MOVUPS = 495 , X86_INS_MOVZX = 496 , X86_INS_MPSADBW = 497 , X86_INS_MUL = 498 , X86_INS_MULPD = 499 , X86_INS_MULPS = 500 , X86_INS_MULSD = 501 , X86_INS_MULSS = 502 , X86_INS_MULX = 503 , X86_INS_FMUL = 504 , X86_INS_FIMUL = 505 , X86_INS_FMULP = 506 , X86_INS_MWAITX = 507 , X86_INS_MWAIT = 508 , X86_INS_NEG = 509 , X86_INS_NOP = 510 , X86_INS_NOT = 511 , X86_INS_OR = 512 , X86_INS_ORPD = 513 , X86_INS_ORPS = 514 , X86_INS_OUT = 515 , X86_INS_OUTSB = 516 , X86_INS_OUTSD = 517 , X86_INS_OUTSW = 518 , X86_INS_PACKUSDW = 519 , X86_INS_PAUSE = 520 , X86_INS_PAVGUSB = 521 , X86_INS_PBLENDVB = 522 , X86_INS_PBLENDW = 523 , X86_INS_PCLMULQDQ = 524 , X86_INS_PCMPEQQ = 525 , X86_INS_PCMPESTRI = 526 , X86_INS_PCMPESTRM = 527 , X86_INS_PCMPGTQ = 528 , X86_INS_PCMPISTRI = 529 , X86_INS_PCMPISTRM = 530 , X86_INS_PCONFIG = 531 , X86_INS_PDEP = 532 , X86_INS_PEXT = 533 , X86_INS_PEXTRB = 534 , X86_INS_PEXTRD = 535 , X86_INS_PEXTRQ = 536 , X86_INS_PF2ID = 537 , X86_INS_PF2IW = 538 , X86_INS_PFACC = 539 , X86_INS_PFADD = 540 , X86_INS_PFCMPEQ = 541 , X86_INS_PFCMPGE = 542 , X86_INS_PFCMPGT = 543 , X86_INS_PFMAX = 544 , X86_INS_PFMIN = 545 , X86_INS_PFMUL = 546 , X86_INS_PFNACC = 547 , X86_INS_PFPNACC = 548 , X86_INS_PFRCPIT1 = 549 , X86_INS_PFRCPIT2 = 550 , X86_INS_PFRCP = 551 , X86_INS_PFRSQIT1 = 552 , X86_INS_PFRSQRT = 553 , X86_INS_PFSUBR = 554 , X86_INS_PFSUB = 555 , X86_INS_PHMINPOSUW = 556 , X86_INS_PI2FD = 557 , X86_INS_PI2FW = 558 , X86_INS_PINSRB = 559 , X86_INS_PINSRD = 560 , X86_INS_PINSRQ = 561 , X86_INS_PMAXSB = 562 , X86_INS_PMAXSD = 563 , X86_INS_PMAXUD = 564 , X86_INS_PMAXUW = 565 , X86_INS_PMINSB = 566 , X86_INS_PMINSD = 567 , X86_INS_PMINUD = 568 , X86_INS_PMINUW = 569 , X86_INS_PMOVSXBD = 570 , X86_INS_PMOVSXBQ = 571 , X86_INS_PMOVSXBW = 572 , X86_INS_PMOVSXDQ = 573 , X86_INS_PMOVSXWD = 574 , X86_INS_PMOVSXWQ = 575 , X86_INS_PMOVZXBD = 576 , X86_INS_PMOVZXBQ = 577 , X86_INS_PMOVZXBW = 578 , X86_INS_PMOVZXDQ = 579 , X86_INS_PMOVZXWD = 580 , X86_INS_PMOVZXWQ = 581 , X86_INS_PMULDQ = 582 , X86_INS_PMULHRW = 583 , X86_INS_PMULLD = 584 , X86_INS_POP = 585 , X86_INS_POPAW = 586 , X86_INS_POPAL = 587 , X86_INS_POPCNT = 588 , X86_INS_POPF = 589 , X86_INS_POPFD = 590 , X86_INS_POPFQ = 591 , X86_INS_PREFETCH = 592 , X86_INS_PREFETCHNTA = 593 , X86_INS_PREFETCHT0 = 594 , X86_INS_PREFETCHT1 = 595 , X86_INS_PREFETCHT2 = 596 , X86_INS_PREFETCHW = 597 , X86_INS_PREFETCHWT1 = 598 , X86_INS_PSHUFD = 599 , X86_INS_PSHUFHW = 600 , X86_INS_PSHUFLW = 601 , X86_INS_PSLLDQ = 602 , X86_INS_PSRLDQ = 603 , X86_INS_PSWAPD = 604 , X86_INS_PTEST = 605 , X86_INS_PTWRITE = 606 , X86_INS_PUNPCKHQDQ = 607 , X86_INS_PUNPCKLQDQ = 608 , X86_INS_PUSH = 609 , X86_INS_PUSHAW = 610 , X86_INS_PUSHAL = 611 , X86_INS_PUSHF = 612 , X86_INS_PUSHFD = 613 , X86_INS_PUSHFQ = 614 , X86_INS_RCL = 615 , X86_INS_RCPPS = 616 , X86_INS_RCPSS = 617 , X86_INS_RCR = 618 , X86_INS_RDFSBASE = 619 , X86_INS_RDGSBASE = 620 , X86_INS_RDMSR = 621 , X86_INS_RDPID = 622 , X86_INS_RDPKRU = 623 , X86_INS_RDPMC = 624 , X86_INS_RDRAND = 625 , X86_INS_RDSEED = 626 , X86_INS_RDSSPD = 627 , X86_INS_RDSSPQ = 628 , X86_INS_RDTSC = 629 , X86_INS_RDTSCP = 630 , X86_INS_REPNE = 631 , X86_INS_REP = 632 , X86_INS_RET = 633 , X86_INS_REX64 = 634 , X86_INS_ROL = 635 , X86_INS_ROR = 636 , X86_INS_RORX = 637 , X86_INS_ROUNDPD = 638 , X86_INS_ROUNDPS = 639 , X86_INS_ROUNDSD = 640 , X86_INS_ROUNDSS = 641 , X86_INS_RSM = 642 , X86_INS_RSQRTPS = 643 , X86_INS_RSQRTSS = 644 , X86_INS_RSTORSSP = 645 , X86_INS_SAHF = 646 , X86_INS_SAL = 647 , X86_INS_SALC = 648 , X86_INS_SAR = 649 , X86_INS_SARX = 650 , X86_INS_SAVEPREVSSP = 651 , X86_INS_SBB = 652 , X86_INS_SCASB = 653 , X86_INS_SCASD = 654 , X86_INS_SCASQ = 655 , X86_INS_SCASW = 656 , X86_INS_SETAE = 657 , X86_INS_SETA = 658 , X86_INS_SETBE = 659 , X86_INS_SETB = 660 , X86_INS_SETE = 661 , X86_INS_SETGE = 662 , X86_INS_SETG = 663 , X86_INS_SETLE = 664 , X86_INS_SETL = 665 , X86_INS_SETNE = 666 , X86_INS_SETNO = 667 , X86_INS_SETNP = 668 , X86_INS_SETNS = 669 , X86_INS_SETO = 670 , X86_INS_SETP = 671 , X86_INS_SETSSBSY = 672 , X86_INS_SETS = 673 , X86_INS_SFENCE = 674 , X86_INS_SGDT = 675 , X86_INS_SHA1MSG1 = 676 , X86_INS_SHA1MSG2 = 677 , X86_INS_SHA1NEXTE = 678 , X86_INS_SHA1RNDS4 = 679 , X86_INS_SHA256MSG1 = 680 , X86_INS_SHA256MSG2 = 681 , X86_INS_SHA256RNDS2 = 682 , X86_INS_SHL = 683 , X86_INS_SHLD = 684 , X86_INS_SHLX = 685 , X86_INS_SHR = 686 , X86_INS_SHRD = 687 , X86_INS_SHRX = 688 , X86_INS_SHUFPD = 689 , X86_INS_SHUFPS = 690 , X86_INS_SIDT = 691 , X86_INS_FSIN = 692 , X86_INS_SKINIT = 693 , X86_INS_SLDT = 694 , X86_INS_SLWPCB = 695 , X86_INS_SMSW = 696 , X86_INS_SQRTPD = 697 , X86_INS_SQRTPS = 698 , X86_INS_SQRTSD = 699 , X86_INS_SQRTSS = 700 , X86_INS_FSQRT = 701 , X86_INS_STAC = 702 , X86_INS_STC = 703 , X86_INS_STD = 704 , X86_INS_STGI = 705 , X86_INS_STI = 706 , X86_INS_STMXCSR = 707 , X86_INS_STOSB = 708 , X86_INS_STOSD = 709 , X86_INS_STOSQ = 710 , X86_INS_STOSW = 711 , X86_INS_STR = 712 , X86_INS_FST = 713 , X86_INS_FSTP = 714 , X86_INS_SUB = 715 , X86_INS_SUBPD = 716 , X86_INS_SUBPS = 717 , X86_INS_FSUBR = 718 , X86_INS_FISUBR = 719 , X86_INS_FSUBRP = 720 , X86_INS_SUBSD = 721 , X86_INS_SUBSS = 722 , X86_INS_FSUB = 723 , X86_INS_FISUB = 724 , X86_INS_FSUBP = 725 , X86_INS_SWAPGS = 726 , X86_INS_SYSCALL = 727 , X86_INS_SYSENTER = 728 , X86_INS_SYSEXIT = 729 , X86_INS_SYSEXITQ = 730 , X86_INS_SYSRET = 731 , X86_INS_SYSRETQ = 732 , X86_INS_T1MSKC = 733 , X86_INS_TEST = 734 , X86_INS_TPAUSE = 735 , X86_INS_FTST = 736 , X86_INS_TZCNT = 737 , X86_INS_TZMSK = 738 , X86_INS_UCOMISD = 739 , X86_INS_UCOMISS = 740 , X86_INS_FUCOMPI = 741 , X86_INS_FUCOMI = 742 , X86_INS_FUCOMPP = 743 , X86_INS_FUCOMP = 744 , X86_INS_FUCOM = 745 , X86_INS_UD0 = 746 , X86_INS_UD1 = 747 , X86_INS_UD2 = 748 , X86_INS_UMONITOR = 749 , X86_INS_UMWAIT = 750 , X86_INS_UNPCKHPD = 751 , X86_INS_UNPCKHPS = 752 , X86_INS_UNPCKLPD = 753 , X86_INS_UNPCKLPS = 754 , X86_INS_V4FMADDPS = 755 , X86_INS_V4FMADDSS = 756 , X86_INS_V4FNMADDPS = 757 , X86_INS_V4FNMADDSS = 758 , X86_INS_VADDPD = 759 , X86_INS_VADDPS = 760 , X86_INS_VADDSD = 761 , X86_INS_VADDSS = 762 , X86_INS_VADDSUBPD = 763 , X86_INS_VADDSUBPS = 764 , X86_INS_VAESDECLAST = 765 , X86_INS_VAESDEC = 766 , X86_INS_VAESENCLAST = 767 , X86_INS_VAESENC = 768 , X86_INS_VAESIMC = 769 , X86_INS_VAESKEYGENASSIST = 770 , X86_INS_VALIGND = 771 , X86_INS_VALIGNQ = 772 , X86_INS_VANDNPD = 773 , X86_INS_VANDNPS = 774 , X86_INS_VANDPD = 775 , X86_INS_VANDPS = 776 , X86_INS_VBLENDMPD = 777 , X86_INS_VBLENDMPS = 778 , X86_INS_VBLENDPD = 779 , X86_INS_VBLENDPS = 780 , X86_INS_VBLENDVPD = 781 , X86_INS_VBLENDVPS = 782 , X86_INS_VBROADCASTF128 = 783 , X86_INS_VBROADCASTF32X2 = 784 , X86_INS_VBROADCASTF32X4 = 785 , X86_INS_VBROADCASTF32X8 = 786 , X86_INS_VBROADCASTF64X2 = 787 , X86_INS_VBROADCASTF64X4 = 788 , X86_INS_VBROADCASTI128 = 789 , X86_INS_VBROADCASTI32X2 = 790 , X86_INS_VBROADCASTI32X4 = 791 , X86_INS_VBROADCASTI32X8 = 792 , X86_INS_VBROADCASTI64X2 = 793 , X86_INS_VBROADCASTI64X4 = 794 , X86_INS_VBROADCASTSD = 795 , X86_INS_VBROADCASTSS = 796 , X86_INS_VCMP = 797 , X86_INS_VCMPPD = 798 , X86_INS_VCMPPS = 799 , X86_INS_VCMPSD = 800 , X86_INS_VCMPSS = 801 , X86_INS_VCOMISD = 802 , X86_INS_VCOMISS = 803 , X86_INS_VCOMPRESSPD = 804 , X86_INS_VCOMPRESSPS = 805 , X86_INS_VCVTDQ2PD = 806 , X86_INS_VCVTDQ2PS = 807 , X86_INS_VCVTPD2DQ = 808 , X86_INS_VCVTPD2PS = 809 , X86_INS_VCVTPD2QQ = 810 , X86_INS_VCVTPD2UDQ = 811 , X86_INS_VCVTPD2UQQ = 812 , X86_INS_VCVTPH2PS = 813 , X86_INS_VCVTPS2DQ = 814 , X86_INS_VCVTPS2PD = 815 , X86_INS_VCVTPS2PH = 816 , X86_INS_VCVTPS2QQ = 817 , X86_INS_VCVTPS2UDQ = 818 , X86_INS_VCVTPS2UQQ = 819 , X86_INS_VCVTQQ2PD = 820 , X86_INS_VCVTQQ2PS = 821 , X86_INS_VCVTSD2SI = 822 , X86_INS_VCVTSD2SS = 823 , X86_INS_VCVTSD2USI = 824 , X86_INS_VCVTSI2SD = 825 , X86_INS_VCVTSI2SS = 826 , X86_INS_VCVTSS2SD = 827 , X86_INS_VCVTSS2SI = 828 , X86_INS_VCVTSS2USI = 829 , X86_INS_VCVTTPD2DQ = 830 , X86_INS_VCVTTPD2QQ = 831 , X86_INS_VCVTTPD2UDQ = 832 , X86_INS_VCVTTPD2UQQ = 833 , X86_INS_VCVTTPS2DQ = 834 , X86_INS_VCVTTPS2QQ = 835 , X86_INS_VCVTTPS2UDQ = 836 , X86_INS_VCVTTPS2UQQ = 837 , X86_INS_VCVTTSD2SI = 838 , X86_INS_VCVTTSD2USI = 839 , X86_INS_VCVTTSS2SI = 840 , X86_INS_VCVTTSS2USI = 841 , X86_INS_VCVTUDQ2PD = 842 , X86_INS_VCVTUDQ2PS = 843 , X86_INS_VCVTUQQ2PD = 844 , X86_INS_VCVTUQQ2PS = 845 , X86_INS_VCVTUSI2SD = 846 , X86_INS_VCVTUSI2SS = 847 , X86_INS_VDBPSADBW = 848 , X86_INS_VDIVPD = 849 , X86_INS_VDIVPS = 850 , X86_INS_VDIVSD = 851 , X86_INS_VDIVSS = 852 , X86_INS_VDPPD = 853 , X86_INS_VDPPS = 854 , X86_INS_VERR = 855 , X86_INS_VERW = 856 , X86_INS_VEXP2PD = 857 , X86_INS_VEXP2PS = 858 , X86_INS_VEXPANDPD = 859 , X86_INS_VEXPANDPS = 860 , X86_INS_VEXTRACTF128 = 861 , X86_INS_VEXTRACTF32X4 = 862 , X86_INS_VEXTRACTF32X8 = 863 , X86_INS_VEXTRACTF64X2 = 864 , X86_INS_VEXTRACTF64X4 = 865 , X86_INS_VEXTRACTI128 = 866 , X86_INS_VEXTRACTI32X4 = 867 , X86_INS_VEXTRACTI32X8 = 868 , X86_INS_VEXTRACTI64X2 = 869 , X86_INS_VEXTRACTI64X4 = 870 , X86_INS_VEXTRACTPS = 871 , X86_INS_VFIXUPIMMPD = 872 , X86_INS_VFIXUPIMMPS = 873 , X86_INS_VFIXUPIMMSD = 874 , X86_INS_VFIXUPIMMSS = 875 , X86_INS_VFMADD132PD = 876 , X86_INS_VFMADD132PS = 877 , X86_INS_VFMADD132SD = 878 , X86_INS_VFMADD132SS = 879 , X86_INS_VFMADD213PD = 880 , X86_INS_VFMADD213PS = 881 , X86_INS_VFMADD213SD = 882 , X86_INS_VFMADD213SS = 883 , X86_INS_VFMADD231PD = 884 , X86_INS_VFMADD231PS = 885 , X86_INS_VFMADD231SD = 886 , X86_INS_VFMADD231SS = 887 , X86_INS_VFMADDPD = 888 , X86_INS_VFMADDPS = 889 , X86_INS_VFMADDSD = 890 , X86_INS_VFMADDSS = 891 , X86_INS_VFMADDSUB132PD = 892 , X86_INS_VFMADDSUB132PS = 893 , X86_INS_VFMADDSUB213PD = 894 , X86_INS_VFMADDSUB213PS = 895 , X86_INS_VFMADDSUB231PD = 896 , X86_INS_VFMADDSUB231PS = 897 , X86_INS_VFMADDSUBPD = 898 , X86_INS_VFMADDSUBPS = 899 , X86_INS_VFMSUB132PD = 900 , X86_INS_VFMSUB132PS = 901 , X86_INS_VFMSUB132SD = 902 , X86_INS_VFMSUB132SS = 903 , X86_INS_VFMSUB213PD = 904 , X86_INS_VFMSUB213PS = 905 , X86_INS_VFMSUB213SD = 906 , X86_INS_VFMSUB213SS = 907 , X86_INS_VFMSUB231PD = 908 , X86_INS_VFMSUB231PS = 909 , X86_INS_VFMSUB231SD = 910 , X86_INS_VFMSUB231SS = 911 , X86_INS_VFMSUBADD132PD = 912 , X86_INS_VFMSUBADD132PS = 913 , X86_INS_VFMSUBADD213PD = 914 , X86_INS_VFMSUBADD213PS = 915 , X86_INS_VFMSUBADD231PD = 916 , X86_INS_VFMSUBADD231PS = 917 , X86_INS_VFMSUBADDPD = 918 , X86_INS_VFMSUBADDPS = 919 , X86_INS_VFMSUBPD = 920 , X86_INS_VFMSUBPS = 921 , X86_INS_VFMSUBSD = 922 , X86_INS_VFMSUBSS = 923 , X86_INS_VFNMADD132PD = 924 , X86_INS_VFNMADD132PS = 925 , X86_INS_VFNMADD132SD = 926 , X86_INS_VFNMADD132SS = 927 , X86_INS_VFNMADD213PD = 928 , X86_INS_VFNMADD213PS = 929 , X86_INS_VFNMADD213SD = 930 , X86_INS_VFNMADD213SS = 931 , X86_INS_VFNMADD231PD = 932 , X86_INS_VFNMADD231PS = 933 , X86_INS_VFNMADD231SD = 934 , X86_INS_VFNMADD231SS = 935 , X86_INS_VFNMADDPD = 936 , X86_INS_VFNMADDPS = 937 , X86_INS_VFNMADDSD = 938 , X86_INS_VFNMADDSS = 939 , X86_INS_VFNMSUB132PD = 940 , X86_INS_VFNMSUB132PS = 941 , X86_INS_VFNMSUB132SD = 942 , X86_INS_VFNMSUB132SS = 943 , X86_INS_VFNMSUB213PD = 944 , X86_INS_VFNMSUB213PS = 945 , X86_INS_VFNMSUB213SD = 946 , X86_INS_VFNMSUB213SS = 947 , X86_INS_VFNMSUB231PD = 948 , X86_INS_VFNMSUB231PS = 949 , X86_INS_VFNMSUB231SD = 950 , X86_INS_VFNMSUB231SS = 951 , X86_INS_VFNMSUBPD = 952 , X86_INS_VFNMSUBPS = 953 , X86_INS_VFNMSUBSD = 954 , X86_INS_VFNMSUBSS = 955 , X86_INS_VFPCLASSPD = 956 , X86_INS_VFPCLASSPS = 957 , X86_INS_VFPCLASSSD = 958 , X86_INS_VFPCLASSSS = 959 , X86_INS_VFRCZPD = 960 , X86_INS_VFRCZPS = 961 , X86_INS_VFRCZSD = 962 , X86_INS_VFRCZSS = 963 , X86_INS_VGATHERDPD = 964 , X86_INS_VGATHERDPS = 965 , X86_INS_VGATHERPF0DPD = 966 , X86_INS_VGATHERPF0DPS = 967 , X86_INS_VGATHERPF0QPD = 968 , X86_INS_VGATHERPF0QPS = 969 , X86_INS_VGATHERPF1DPD = 970 , X86_INS_VGATHERPF1DPS = 971 , X86_INS_VGATHERPF1QPD = 972 , X86_INS_VGATHERPF1QPS = 973 , X86_INS_VGATHERQPD = 974 , X86_INS_VGATHERQPS = 975 , X86_INS_VGETEXPPD = 976 , X86_INS_VGETEXPPS = 977 , X86_INS_VGETEXPSD = 978 , X86_INS_VGETEXPSS = 979 , X86_INS_VGETMANTPD = 980 , X86_INS_VGETMANTPS = 981 , X86_INS_VGETMANTSD = 982 , X86_INS_VGETMANTSS = 983 , X86_INS_VGF2P8AFFINEINVQB = 984 , X86_INS_VGF2P8AFFINEQB = 985 , X86_INS_VGF2P8MULB = 986 , X86_INS_VHADDPD = 987 , X86_INS_VHADDPS = 988 , X86_INS_VHSUBPD = 989 , X86_INS_VHSUBPS = 990 , X86_INS_VINSERTF128 = 991 , X86_INS_VINSERTF32X4 = 992 , X86_INS_VINSERTF32X8 = 993 , X86_INS_VINSERTF64X2 = 994 , X86_INS_VINSERTF64X4 = 995 , X86_INS_VINSERTI128 = 996 , X86_INS_VINSERTI32X4 = 997 , X86_INS_VINSERTI32X8 = 998 , X86_INS_VINSERTI64X2 = 999 , X86_INS_VINSERTI64X4 = 1000 , X86_INS_VINSERTPS = 1001 , X86_INS_VLDDQU = 1002 , X86_INS_VLDMXCSR = 1003 , X86_INS_VMASKMOVDQU = 1004 , X86_INS_VMASKMOVPD = 1005 , X86_INS_VMASKMOVPS = 1006 , X86_INS_VMAXPD = 1007 , X86_INS_VMAXPS = 1008 , X86_INS_VMAXSD = 1009 , X86_INS_VMAXSS = 1010 , X86_INS_VMCALL = 1011 , X86_INS_VMCLEAR = 1012 , X86_INS_VMFUNC = 1013 , X86_INS_VMINPD = 1014 , X86_INS_VMINPS = 1015 , X86_INS_VMINSD = 1016 , X86_INS_VMINSS = 1017 , X86_INS_VMLAUNCH = 1018 , X86_INS_VMLOAD = 1019 , X86_INS_VMMCALL = 1020 , X86_INS_VMOVQ = 1021 , X86_INS_VMOVAPD = 1022 , X86_INS_VMOVAPS = 1023 , X86_INS_VMOVDDUP = 1024 , X86_INS_VMOVD = 1025 , X86_INS_VMOVDQA32 = 1026 , X86_INS_VMOVDQA64 = 1027 , X86_INS_VMOVDQA = 1028 , X86_INS_VMOVDQU16 = 1029 , X86_INS_VMOVDQU32 = 1030 , X86_INS_VMOVDQU64 = 1031 , X86_INS_VMOVDQU8 = 1032 , X86_INS_VMOVDQU = 1033 , X86_INS_VMOVHLPS = 1034 , X86_INS_VMOVHPD = 1035 , X86_INS_VMOVHPS = 1036 , X86_INS_VMOVLHPS = 1037 , X86_INS_VMOVLPD = 1038 , X86_INS_VMOVLPS = 1039 , X86_INS_VMOVMSKPD = 1040 , X86_INS_VMOVMSKPS = 1041 , X86_INS_VMOVNTDQA = 1042 , X86_INS_VMOVNTDQ = 1043 , X86_INS_VMOVNTPD = 1044 , X86_INS_VMOVNTPS = 1045 , X86_INS_VMOVSD = 1046 , X86_INS_VMOVSHDUP = 1047 , X86_INS_VMOVSLDUP = 1048 , X86_INS_VMOVSS = 1049 , X86_INS_VMOVUPD = 1050 , X86_INS_VMOVUPS = 1051 , X86_INS_VMPSADBW = 1052 , X86_INS_VMPTRLD = 1053 , X86_INS_VMPTRST = 1054 , X86_INS_VMREAD = 1055 , X86_INS_VMRESUME = 1056 , X86_INS_VMRUN = 1057 , X86_INS_VMSAVE = 1058 , X86_INS_VMULPD = 1059 , X86_INS_VMULPS = 1060 , X86_INS_VMULSD = 1061 , X86_INS_VMULSS = 1062 , X86_INS_VMWRITE = 1063 , X86_INS_VMXOFF = 1064 , X86_INS_VMXON = 1065 , X86_INS_VORPD = 1066 , X86_INS_VORPS = 1067 , X86_INS_VP4DPWSSDS = 1068 , X86_INS_VP4DPWSSD = 1069 , X86_INS_VPABSB = 1070 , X86_INS_VPABSD = 1071 , X86_INS_VPABSQ = 1072 , X86_INS_VPABSW = 1073 , X86_INS_VPACKSSDW = 1074 , X86_INS_VPACKSSWB = 1075 , X86_INS_VPACKUSDW = 1076 , X86_INS_VPACKUSWB = 1077 , X86_INS_VPADDB = 1078 , X86_INS_VPADDD = 1079 , X86_INS_VPADDQ = 1080 , X86_INS_VPADDSB = 1081 , X86_INS_VPADDSW = 1082 , X86_INS_VPADDUSB = 1083 , X86_INS_VPADDUSW = 1084 , X86_INS_VPADDW = 1085 , X86_INS_VPALIGNR = 1086 , X86_INS_VPANDD = 1087 , X86_INS_VPANDND = 1088 , X86_INS_VPANDNQ = 1089 , X86_INS_VPANDN = 1090 , X86_INS_VPANDQ = 1091 , X86_INS_VPAND = 1092 , X86_INS_VPAVGB = 1093 , X86_INS_VPAVGW = 1094 , X86_INS_VPBLENDD = 1095 , X86_INS_VPBLENDMB = 1096 , X86_INS_VPBLENDMD = 1097 , X86_INS_VPBLENDMQ = 1098 , X86_INS_VPBLENDMW = 1099 , X86_INS_VPBLENDVB = 1100 , X86_INS_VPBLENDW = 1101 , X86_INS_VPBROADCASTB = 1102 , X86_INS_VPBROADCASTD = 1103 , X86_INS_VPBROADCASTMB2Q = 1104 , X86_INS_VPBROADCASTMW2D = 1105 , X86_INS_VPBROADCASTQ = 1106 , X86_INS_VPBROADCASTW = 1107 , X86_INS_VPCLMULQDQ = 1108 , X86_INS_VPCMOV = 1109 , X86_INS_VPCMP = 1110 , X86_INS_VPCMPB = 1111 , X86_INS_VPCMPD = 1112 , X86_INS_VPCMPEQB = 1113 , X86_INS_VPCMPEQD = 1114 , X86_INS_VPCMPEQQ = 1115 , X86_INS_VPCMPEQW = 1116 , X86_INS_VPCMPESTRI = 1117 , X86_INS_VPCMPESTRM = 1118 , X86_INS_VPCMPGTB = 1119 , X86_INS_VPCMPGTD = 1120 , X86_INS_VPCMPGTQ = 1121 , X86_INS_VPCMPGTW = 1122 , X86_INS_VPCMPISTRI = 1123 , X86_INS_VPCMPISTRM = 1124 , X86_INS_VPCMPQ = 1125 , X86_INS_VPCMPUB = 1126 , X86_INS_VPCMPUD = 1127 , X86_INS_VPCMPUQ = 1128 , X86_INS_VPCMPUW = 1129 , X86_INS_VPCMPW = 1130 , X86_INS_VPCOM = 1131 , X86_INS_VPCOMB = 1132 , X86_INS_VPCOMD = 1133 , X86_INS_VPCOMPRESSB = 1134 , X86_INS_VPCOMPRESSD = 1135 , X86_INS_VPCOMPRESSQ = 1136 , X86_INS_VPCOMPRESSW = 1137 , X86_INS_VPCOMQ = 1138 , X86_INS_VPCOMUB = 1139 , X86_INS_VPCOMUD = 1140 , X86_INS_VPCOMUQ = 1141 , X86_INS_VPCOMUW = 1142 , X86_INS_VPCOMW = 1143 , X86_INS_VPCONFLICTD = 1144 , X86_INS_VPCONFLICTQ = 1145 , X86_INS_VPDPBUSDS = 1146 , X86_INS_VPDPBUSD = 1147 , X86_INS_VPDPWSSDS = 1148 , X86_INS_VPDPWSSD = 1149 , X86_INS_VPERM2F128 = 1150 , X86_INS_VPERM2I128 = 1151 , X86_INS_VPERMB = 1152 , X86_INS_VPERMD = 1153 , X86_INS_VPERMI2B = 1154 , X86_INS_VPERMI2D = 1155 , X86_INS_VPERMI2PD = 1156 , X86_INS_VPERMI2PS = 1157 , X86_INS_VPERMI2Q = 1158 , X86_INS_VPERMI2W = 1159 , X86_INS_VPERMIL2PD = 1160 , X86_INS_VPERMILPD = 1161 , X86_INS_VPERMIL2PS = 1162 , X86_INS_VPERMILPS = 1163 , X86_INS_VPERMPD = 1164 , X86_INS_VPERMPS = 1165 , X86_INS_VPERMQ = 1166 , X86_INS_VPERMT2B = 1167 , X86_INS_VPERMT2D = 1168 , X86_INS_VPERMT2PD = 1169 , X86_INS_VPERMT2PS = 1170 , X86_INS_VPERMT2Q = 1171 , X86_INS_VPERMT2W = 1172 , X86_INS_VPERMW = 1173 , X86_INS_VPEXPANDB = 1174 , X86_INS_VPEXPANDD = 1175 , X86_INS_VPEXPANDQ = 1176 , X86_INS_VPEXPANDW = 1177 , X86_INS_VPEXTRB = 1178 , X86_INS_VPEXTRD = 1179 , X86_INS_VPEXTRQ = 1180 , X86_INS_VPEXTRW = 1181 , X86_INS_VPGATHERDD = 1182 , X86_INS_VPGATHERDQ = 1183 , X86_INS_VPGATHERQD = 1184 , X86_INS_VPGATHERQQ = 1185 , X86_INS_VPHADDBD = 1186 , X86_INS_VPHADDBQ = 1187 , X86_INS_VPHADDBW = 1188 , X86_INS_VPHADDDQ = 1189 , X86_INS_VPHADDD = 1190 , X86_INS_VPHADDSW = 1191 , X86_INS_VPHADDUBD = 1192 , X86_INS_VPHADDUBQ = 1193 , X86_INS_VPHADDUBW = 1194 , X86_INS_VPHADDUDQ = 1195 , X86_INS_VPHADDUWD = 1196 , X86_INS_VPHADDUWQ = 1197 , X86_INS_VPHADDWD = 1198 , X86_INS_VPHADDWQ = 1199 , X86_INS_VPHADDW = 1200 , X86_INS_VPHMINPOSUW = 1201 , X86_INS_VPHSUBBW = 1202 , X86_INS_VPHSUBDQ = 1203 , X86_INS_VPHSUBD = 1204 , X86_INS_VPHSUBSW = 1205 , X86_INS_VPHSUBWD = 1206 , X86_INS_VPHSUBW = 1207 , X86_INS_VPINSRB = 1208 , X86_INS_VPINSRD = 1209 , X86_INS_VPINSRQ = 1210 , X86_INS_VPINSRW = 1211 , X86_INS_VPLZCNTD = 1212 , X86_INS_VPLZCNTQ = 1213 , X86_INS_VPMACSDD = 1214 , X86_INS_VPMACSDQH = 1215 , X86_INS_VPMACSDQL = 1216 , X86_INS_VPMACSSDD = 1217 , X86_INS_VPMACSSDQH = 1218 , X86_INS_VPMACSSDQL = 1219 , X86_INS_VPMACSSWD = 1220 , X86_INS_VPMACSSWW = 1221 , X86_INS_VPMACSWD = 1222 , X86_INS_VPMACSWW = 1223 , X86_INS_VPMADCSSWD = 1224 , X86_INS_VPMADCSWD = 1225 , X86_INS_VPMADD52HUQ = 1226 , X86_INS_VPMADD52LUQ = 1227 , X86_INS_VPMADDUBSW = 1228 , X86_INS_VPMADDWD = 1229 , X86_INS_VPMASKMOVD = 1230 , X86_INS_VPMASKMOVQ = 1231 , X86_INS_VPMAXSB = 1232 , X86_INS_VPMAXSD = 1233 , X86_INS_VPMAXSQ = 1234 , X86_INS_VPMAXSW = 1235 , X86_INS_VPMAXUB = 1236 , X86_INS_VPMAXUD = 1237 , X86_INS_VPMAXUQ = 1238 , X86_INS_VPMAXUW = 1239 , X86_INS_VPMINSB = 1240 , X86_INS_VPMINSD = 1241 , X86_INS_VPMINSQ = 1242 , X86_INS_VPMINSW = 1243 , X86_INS_VPMINUB = 1244 , X86_INS_VPMINUD = 1245 , X86_INS_VPMINUQ = 1246 , X86_INS_VPMINUW = 1247 , X86_INS_VPMOVB2M = 1248 , X86_INS_VPMOVD2M = 1249 , X86_INS_VPMOVDB = 1250 , X86_INS_VPMOVDW = 1251 , X86_INS_VPMOVM2B = 1252 , X86_INS_VPMOVM2D = 1253 , X86_INS_VPMOVM2Q = 1254 , X86_INS_VPMOVM2W = 1255 , X86_INS_VPMOVMSKB = 1256 , X86_INS_VPMOVQ2M = 1257 , X86_INS_VPMOVQB = 1258 , X86_INS_VPMOVQD = 1259 , X86_INS_VPMOVQW = 1260 , X86_INS_VPMOVSDB = 1261 , X86_INS_VPMOVSDW = 1262 , X86_INS_VPMOVSQB = 1263 , X86_INS_VPMOVSQD = 1264 , X86_INS_VPMOVSQW = 1265 , X86_INS_VPMOVSWB = 1266 , X86_INS_VPMOVSXBD = 1267 , X86_INS_VPMOVSXBQ = 1268 , X86_INS_VPMOVSXBW = 1269 , X86_INS_VPMOVSXDQ = 1270 , X86_INS_VPMOVSXWD = 1271 , X86_INS_VPMOVSXWQ = 1272 , X86_INS_VPMOVUSDB = 1273 , X86_INS_VPMOVUSDW = 1274 , X86_INS_VPMOVUSQB = 1275 , X86_INS_VPMOVUSQD = 1276 , X86_INS_VPMOVUSQW = 1277 , X86_INS_VPMOVUSWB = 1278 , X86_INS_VPMOVW2M = 1279 , X86_INS_VPMOVWB = 1280 , X86_INS_VPMOVZXBD = 1281 , X86_INS_VPMOVZXBQ = 1282 , X86_INS_VPMOVZXBW = 1283 , X86_INS_VPMOVZXDQ = 1284 , X86_INS_VPMOVZXWD = 1285 , X86_INS_VPMOVZXWQ = 1286 , X86_INS_VPMULDQ = 1287 , X86_INS_VPMULHRSW = 1288 , X86_INS_VPMULHUW = 1289 , X86_INS_VPMULHW = 1290 , X86_INS_VPMULLD = 1291 , X86_INS_VPMULLQ = 1292 , X86_INS_VPMULLW = 1293 , X86_INS_VPMULTISHIFTQB = 1294 , X86_INS_VPMULUDQ = 1295 , X86_INS_VPOPCNTB = 1296 , X86_INS_VPOPCNTD = 1297 , X86_INS_VPOPCNTQ = 1298 , X86_INS_VPOPCNTW = 1299 , X86_INS_VPORD = 1300 , X86_INS_VPORQ = 1301 , X86_INS_VPOR = 1302 , X86_INS_VPPERM = 1303 , X86_INS_VPROLD = 1304 , X86_INS_VPROLQ = 1305 , X86_INS_VPROLVD = 1306 , X86_INS_VPROLVQ = 1307 , X86_INS_VPRORD = 1308 , X86_INS_VPRORQ = 1309 , X86_INS_VPRORVD = 1310 , X86_INS_VPRORVQ = 1311 , X86_INS_VPROTB = 1312 , X86_INS_VPROTD = 1313 , X86_INS_VPROTQ = 1314 , X86_INS_VPROTW = 1315 , X86_INS_VPSADBW = 1316 , X86_INS_VPSCATTERDD = 1317 , X86_INS_VPSCATTERDQ = 1318 , X86_INS_VPSCATTERQD = 1319 , X86_INS_VPSCATTERQQ = 1320 , X86_INS_VPSHAB = 1321 , X86_INS_VPSHAD = 1322 , X86_INS_VPSHAQ = 1323 , X86_INS_VPSHAW = 1324 , X86_INS_VPSHLB = 1325 , X86_INS_VPSHLDD = 1326 , X86_INS_VPSHLDQ = 1327 , X86_INS_VPSHLDVD = 1328 , X86_INS_VPSHLDVQ = 1329 , X86_INS_VPSHLDVW = 1330 , X86_INS_VPSHLDW = 1331 , X86_INS_VPSHLD = 1332 , X86_INS_VPSHLQ = 1333 , X86_INS_VPSHLW = 1334 , X86_INS_VPSHRDD = 1335 , X86_INS_VPSHRDQ = 1336 , X86_INS_VPSHRDVD = 1337 , X86_INS_VPSHRDVQ = 1338 , X86_INS_VPSHRDVW = 1339 , X86_INS_VPSHRDW = 1340 , X86_INS_VPSHUFBITQMB = 1341 , X86_INS_VPSHUFB = 1342 , X86_INS_VPSHUFD = 1343 , X86_INS_VPSHUFHW = 1344 , X86_INS_VPSHUFLW = 1345 , X86_INS_VPSIGNB = 1346 , X86_INS_VPSIGND = 1347 , X86_INS_VPSIGNW = 1348 , X86_INS_VPSLLDQ = 1349 , X86_INS_VPSLLD = 1350 , X86_INS_VPSLLQ = 1351 , X86_INS_VPSLLVD = 1352 , X86_INS_VPSLLVQ = 1353 , X86_INS_VPSLLVW = 1354 , X86_INS_VPSLLW = 1355 , X86_INS_VPSRAD = 1356 , X86_INS_VPSRAQ = 1357 , X86_INS_VPSRAVD = 1358 , X86_INS_VPSRAVQ = 1359 , X86_INS_VPSRAVW = 1360 , X86_INS_VPSRAW = 1361 , X86_INS_VPSRLDQ = 1362 , X86_INS_VPSRLD = 1363 , X86_INS_VPSRLQ = 1364 , X86_INS_VPSRLVD = 1365 , X86_INS_VPSRLVQ = 1366 , X86_INS_VPSRLVW = 1367 , X86_INS_VPSRLW = 1368 , X86_INS_VPSUBB = 1369 , X86_INS_VPSUBD = 1370 , X86_INS_VPSUBQ = 1371 , X86_INS_VPSUBSB = 1372 , X86_INS_VPSUBSW = 1373 , X86_INS_VPSUBUSB = 1374 , X86_INS_VPSUBUSW = 1375 , X86_INS_VPSUBW = 1376 , X86_INS_VPTERNLOGD = 1377 , X86_INS_VPTERNLOGQ = 1378 , X86_INS_VPTESTMB = 1379 , X86_INS_VPTESTMD = 1380 , X86_INS_VPTESTMQ = 1381 , X86_INS_VPTESTMW = 1382 , X86_INS_VPTESTNMB = 1383 , X86_INS_VPTESTNMD = 1384 , X86_INS_VPTESTNMQ = 1385 , X86_INS_VPTESTNMW = 1386 , X86_INS_VPTEST = 1387 , X86_INS_VPUNPCKHBW = 1388 , X86_INS_VPUNPCKHDQ = 1389 , X86_INS_VPUNPCKHQDQ = 1390 , X86_INS_VPUNPCKHWD = 1391 , X86_INS_VPUNPCKLBW = 1392 , X86_INS_VPUNPCKLDQ = 1393 , X86_INS_VPUNPCKLQDQ = 1394 , X86_INS_VPUNPCKLWD = 1395 , X86_INS_VPXORD = 1396 , X86_INS_VPXORQ = 1397 , X86_INS_VPXOR = 1398 , X86_INS_VRANGEPD = 1399 , X86_INS_VRANGEPS = 1400 , X86_INS_VRANGESD = 1401 , X86_INS_VRANGESS = 1402 , X86_INS_VRCP14PD = 1403 , X86_INS_VRCP14PS = 1404 , X86_INS_VRCP14SD = 1405 , X86_INS_VRCP14SS = 1406 , X86_INS_VRCP28PD = 1407 , X86_INS_VRCP28PS = 1408 , X86_INS_VRCP28SD = 1409 , X86_INS_VRCP28SS = 1410 , X86_INS_VRCPPS = 1411 , X86_INS_VRCPSS = 1412 , X86_INS_VREDUCEPD = 1413 , X86_INS_VREDUCEPS = 1414 , X86_INS_VREDUCESD = 1415 , X86_INS_VREDUCESS = 1416 , X86_INS_VRNDSCALEPD = 1417 , X86_INS_VRNDSCALEPS = 1418 , X86_INS_VRNDSCALESD = 1419 , X86_INS_VRNDSCALESS = 1420 , X86_INS_VROUNDPD = 1421 , X86_INS_VROUNDPS = 1422 , X86_INS_VROUNDSD = 1423 , X86_INS_VROUNDSS = 1424 , X86_INS_VRSQRT14PD = 1425 , X86_INS_VRSQRT14PS = 1426 , X86_INS_VRSQRT14SD = 1427 , X86_INS_VRSQRT14SS = 1428 , X86_INS_VRSQRT28PD = 1429 , X86_INS_VRSQRT28PS = 1430 , X86_INS_VRSQRT28SD = 1431 , X86_INS_VRSQRT28SS = 1432 , X86_INS_VRSQRTPS = 1433 , X86_INS_VRSQRTSS = 1434 , X86_INS_VSCALEFPD = 1435 , X86_INS_VSCALEFPS = 1436 , X86_INS_VSCALEFSD = 1437 , X86_INS_VSCALEFSS = 1438 , X86_INS_VSCATTERDPD = 1439 , X86_INS_VSCATTERDPS = 1440 , X86_INS_VSCATTERPF0DPD = 1441 , X86_INS_VSCATTERPF0DPS = 1442 , X86_INS_VSCATTERPF0QPD = 1443 , X86_INS_VSCATTERPF0QPS = 1444 , X86_INS_VSCATTERPF1DPD = 1445 , X86_INS_VSCATTERPF1DPS = 1446 , X86_INS_VSCATTERPF1QPD = 1447 , X86_INS_VSCATTERPF1QPS = 1448 , X86_INS_VSCATTERQPD = 1449 , X86_INS_VSCATTERQPS = 1450 , X86_INS_VSHUFF32X4 = 1451 , X86_INS_VSHUFF64X2 = 1452 , X86_INS_VSHUFI32X4 = 1453 , X86_INS_VSHUFI64X2 = 1454 , X86_INS_VSHUFPD = 1455 , X86_INS_VSHUFPS = 1456 , X86_INS_VSQRTPD = 1457 , X86_INS_VSQRTPS = 1458 , X86_INS_VSQRTSD = 1459 , X86_INS_VSQRTSS = 1460 , X86_INS_VSTMXCSR = 1461 , X86_INS_VSUBPD = 1462 , X86_INS_VSUBPS = 1463 , X86_INS_VSUBSD = 1464 , X86_INS_VSUBSS = 1465 , X86_INS_VTESTPD = 1466 , X86_INS_VTESTPS = 1467 , X86_INS_VUCOMISD = 1468 , X86_INS_VUCOMISS = 1469 , X86_INS_VUNPCKHPD = 1470 , X86_INS_VUNPCKHPS = 1471 , X86_INS_VUNPCKLPD = 1472 , X86_INS_VUNPCKLPS = 1473 , X86_INS_VXORPD = 1474 , X86_INS_VXORPS = 1475 , X86_INS_VZEROALL = 1476 , X86_INS_VZEROUPPER = 1477 , X86_INS_WAIT = 1478 , X86_INS_WBINVD = 1479 , X86_INS_WBNOINVD = 1480 , X86_INS_WRFSBASE = 1481 , X86_INS_WRGSBASE = 1482 , X86_INS_WRMSR = 1483 , X86_INS_WRPKRU = 1484 , X86_INS_WRSSD = 1485 , X86_INS_WRSSQ = 1486 , X86_INS_WRUSSD = 1487 , X86_INS_WRUSSQ = 1488 , X86_INS_XABORT = 1489 , X86_INS_XACQUIRE = 1490 , X86_INS_XADD = 1491 , X86_INS_XBEGIN = 1492 , X86_INS_XCHG = 1493 , X86_INS_FXCH = 1494 , X86_INS_XCRYPTCBC = 1495 , X86_INS_XCRYPTCFB = 1496 , X86_INS_XCRYPTCTR = 1497 , X86_INS_XCRYPTECB = 1498 , X86_INS_XCRYPTOFB = 1499 , X86_INS_XEND = 1500 , X86_INS_XGETBV = 1501 , X86_INS_XLATB = 1502 , X86_INS_XOR = 1503 , X86_INS_XORPD = 1504 , X86_INS_XORPS = 1505 , X86_INS_XRELEASE = 1506 , X86_INS_XRSTOR = 1507 , X86_INS_XRSTOR64 = 1508 , X86_INS_XRSTORS = 1509 , X86_INS_XRSTORS64 = 1510 , X86_INS_XSAVE = 1511 , X86_INS_XSAVE64 = 1512 , X86_INS_XSAVEC = 1513 , X86_INS_XSAVEC64 = 1514 , X86_INS_XSAVEOPT = 1515 , X86_INS_XSAVEOPT64 = 1516 , X86_INS_XSAVES = 1517 , X86_INS_XSAVES64 = 1518 , X86_INS_XSETBV = 1519 , X86_INS_XSHA1 = 1520 , X86_INS_XSHA256 = 1521 , X86_INS_XSTORE = 1522 , X86_INS_XTEST = 1523 , X86_INS_ENDING = 1524 , } # [repr (u32)] # [doc = " Group of X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn_group { # [doc = "< = CS_GRP_INVALID"] X86_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] X86_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] X86_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] X86_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] X86_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] X86_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] X86_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] X86_GRP_BRANCH_RELATIVE = 7 , # [doc = "< all virtualization instructions (VT-x + AMD-V)"] X86_GRP_VM = 128 , X86_GRP_3DNOW = 129 , X86_GRP_AES = 130 , X86_GRP_ADX = 131 , X86_GRP_AVX = 132 , X86_GRP_AVX2 = 133 , X86_GRP_AVX512 = 134 , X86_GRP_BMI = 135 , X86_GRP_BMI2 = 136 , X86_GRP_CMOV = 137 , X86_GRP_F16C = 138 , X86_GRP_FMA = 139 , X86_GRP_FMA4 = 140 , X86_GRP_FSGSBASE = 141 , X86_GRP_HLE = 142 , X86_GRP_MMX = 143 , X86_GRP_MODE32 = 144 , X86_GRP_MODE64 = 145 , X86_GRP_RTM = 146 , X86_GRP_SHA = 147 , X86_GRP_SSE1 = 148 , X86_GRP_SSE2 = 149 , X86_GRP_SSE3 = 150 , X86_GRP_SSE41 = 151 , X86_GRP_SSE42 = 152 , X86_GRP_SSE4A = 153 , X86_GRP_SSSE3 = 154 , X86_GRP_PCLMUL = 155 , X86_GRP_XOP = 156 , X86_GRP_CDI = 157 , X86_GRP_ERI = 158 , X86_GRP_TBM = 159 , X86_GRP_16BITMODE = 160 , X86_GRP_NOT64BITMODE = 161 , X86_GRP_SGX = 162 , X86_GRP_DQI = 163 , X86_GRP_BWI = 164 , X86_GRP_PFI = 165 , X86_GRP_VLX = 166 , X86_GRP_SMAP = 167 , X86_GRP_NOVLX = 168 , X86_GRP_FPU = 169 , X86_GRP_ENDING = 170 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] XCORE_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] XCORE_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] XCORE_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] XCORE_OP_MEM = 3 , } # [repr (u32)] # [doc = " XCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_reg { XCORE_REG_INVALID = 0 , XCORE_REG_CP = 1 , XCORE_REG_DP = 2 , XCORE_REG_LR = 3 , XCORE_REG_SP = 4 , XCORE_REG_R0 = 5 , XCORE_REG_R1 = 6 , XCORE_REG_R2 = 7 , XCORE_REG_R3 = 8 , XCORE_REG_R4 = 9 , XCORE_REG_R5 = 10 , XCORE_REG_R6 = 11 , XCORE_REG_R7 = 12 , XCORE_REG_R8 = 13 , XCORE_REG_R9 = 14 , XCORE_REG_R10 = 15 , XCORE_REG_R11 = 16 , # [doc = "< pc"] XCORE_REG_PC = 17 , # [doc = "< save pc"] XCORE_REG_SCP = 18 , XCORE_REG_SSR = 19 , XCORE_REG_ET = 20 , XCORE_REG_ED = 21 , XCORE_REG_SED = 22 , XCORE_REG_KEP = 23 , XCORE_REG_KSP = 24 , XCORE_REG_ID = 25 , XCORE_REG_ENDING = 26 , } # [doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct xcore_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , # [doc = "< +1: forward, -1: backward"] pub direct : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of xcore_op_mem"] [:: std :: mem :: size_of :: < xcore_op_mem > () - 12usize] ; ["Alignment of xcore_op_mem"] [:: std :: mem :: align_of :: < xcore_op_mem > () - 4usize] ; ["Offset of field: xcore_op_mem::base"] [:: std :: mem :: offset_of ! (xcore_op_mem , base) - 0usize] ; ["Offset of field: xcore_op_mem::index"] [:: std :: mem :: offset_of ! (xcore_op_mem , index) - 1usize] ; ["Offset of field: xcore_op_mem::disp"] [:: std :: mem :: offset_of ! (xcore_op_mem , disp) - 4usize] ; ["Offset of field: xcore_op_mem::direct"] [:: std :: mem :: offset_of ! (xcore_op_mem , direct) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore_op { # [doc = "< operand type"] pub type_ : xcore_op_type , pub __bindgen_anon_1 : cs_xcore_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_xcore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : xcore_reg , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : xcore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_xcore_op__bindgen_ty_1 > () - 12usize] ; ["Alignment of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_xcore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op"] [:: std :: mem :: size_of :: < cs_xcore_op > () - 16usize] ; ["Alignment of cs_xcore_op"] [:: std :: mem :: align_of :: < cs_xcore_op > () - 4usize] ; ["Offset of field: cs_xcore_op::type_"] [:: std :: mem :: offset_of ! (cs_xcore_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_xcore_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore"] [:: std :: mem :: size_of :: < cs_xcore > () - 132usize] ; ["Alignment of cs_xcore"] [:: std :: mem :: align_of :: < cs_xcore > () - 4usize] ; ["Offset of field: cs_xcore::op_count"] [:: std :: mem :: offset_of ! (cs_xcore , op_count) - 0usize] ; ["Offset of field: cs_xcore::operands"] [:: std :: mem :: offset_of ! (cs_xcore , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " XCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn { XCORE_INS_INVALID = 0 , XCORE_INS_ADD = 1 , XCORE_INS_ANDNOT = 2 , XCORE_INS_AND = 3 , XCORE_INS_ASHR = 4 , XCORE_INS_BAU = 5 , XCORE_INS_BITREV = 6 , XCORE_INS_BLA = 7 , XCORE_INS_BLAT = 8 , XCORE_INS_BL = 9 , XCORE_INS_BF = 10 , XCORE_INS_BT = 11 , XCORE_INS_BU = 12 , XCORE_INS_BRU = 13 , XCORE_INS_BYTEREV = 14 , XCORE_INS_CHKCT = 15 , XCORE_INS_CLRE = 16 , XCORE_INS_CLRPT = 17 , XCORE_INS_CLRSR = 18 , XCORE_INS_CLZ = 19 , XCORE_INS_CRC8 = 20 , XCORE_INS_CRC32 = 21 , XCORE_INS_DCALL = 22 , XCORE_INS_DENTSP = 23 , XCORE_INS_DGETREG = 24 , XCORE_INS_DIVS = 25 , XCORE_INS_DIVU = 26 , XCORE_INS_DRESTSP = 27 , XCORE_INS_DRET = 28 , XCORE_INS_ECALLF = 29 , XCORE_INS_ECALLT = 30 , XCORE_INS_EDU = 31 , XCORE_INS_EEF = 32 , XCORE_INS_EET = 33 , XCORE_INS_EEU = 34 , XCORE_INS_ENDIN = 35 , XCORE_INS_ENTSP = 36 , XCORE_INS_EQ = 37 , XCORE_INS_EXTDP = 38 , XCORE_INS_EXTSP = 39 , XCORE_INS_FREER = 40 , XCORE_INS_FREET = 41 , XCORE_INS_GETD = 42 , XCORE_INS_GET = 43 , XCORE_INS_GETN = 44 , XCORE_INS_GETR = 45 , XCORE_INS_GETSR = 46 , XCORE_INS_GETST = 47 , XCORE_INS_GETTS = 48 , XCORE_INS_INCT = 49 , XCORE_INS_INIT = 50 , XCORE_INS_INPW = 51 , XCORE_INS_INSHR = 52 , XCORE_INS_INT = 53 , XCORE_INS_IN = 54 , XCORE_INS_KCALL = 55 , XCORE_INS_KENTSP = 56 , XCORE_INS_KRESTSP = 57 , XCORE_INS_KRET = 58 , XCORE_INS_LADD = 59 , XCORE_INS_LD16S = 60 , XCORE_INS_LD8U = 61 , XCORE_INS_LDA16 = 62 , XCORE_INS_LDAP = 63 , XCORE_INS_LDAW = 64 , XCORE_INS_LDC = 65 , XCORE_INS_LDW = 66 , XCORE_INS_LDIVU = 67 , XCORE_INS_LMUL = 68 , XCORE_INS_LSS = 69 , XCORE_INS_LSUB = 70 , XCORE_INS_LSU = 71 , XCORE_INS_MACCS = 72 , XCORE_INS_MACCU = 73 , XCORE_INS_MJOIN = 74 , XCORE_INS_MKMSK = 75 , XCORE_INS_MSYNC = 76 , XCORE_INS_MUL = 77 , XCORE_INS_NEG = 78 , XCORE_INS_NOT = 79 , XCORE_INS_OR = 80 , XCORE_INS_OUTCT = 81 , XCORE_INS_OUTPW = 82 , XCORE_INS_OUTSHR = 83 , XCORE_INS_OUTT = 84 , XCORE_INS_OUT = 85 , XCORE_INS_PEEK = 86 , XCORE_INS_REMS = 87 , XCORE_INS_REMU = 88 , XCORE_INS_RETSP = 89 , XCORE_INS_SETCLK = 90 , XCORE_INS_SET = 91 , XCORE_INS_SETC = 92 , XCORE_INS_SETD = 93 , XCORE_INS_SETEV = 94 , XCORE_INS_SETN = 95 , XCORE_INS_SETPSC = 96 , XCORE_INS_SETPT = 97 , XCORE_INS_SETRDY = 98 , XCORE_INS_SETSR = 99 , XCORE_INS_SETTW = 100 , XCORE_INS_SETV = 101 , XCORE_INS_SEXT = 102 , XCORE_INS_SHL = 103 , XCORE_INS_SHR = 104 , XCORE_INS_SSYNC = 105 , XCORE_INS_ST16 = 106 , XCORE_INS_ST8 = 107 , XCORE_INS_STW = 108 , XCORE_INS_SUB = 109 , XCORE_INS_SYNCR = 110 , XCORE_INS_TESTCT = 111 , XCORE_INS_TESTLCL = 112 , XCORE_INS_TESTWCT = 113 , XCORE_INS_TSETMR = 114 , XCORE_INS_START = 115 , XCORE_INS_WAITEF = 116 , XCORE_INS_WAITET = 117 , XCORE_INS_WAITEU = 118 , XCORE_INS_XOR = 119 , XCORE_INS_ZEXT = 120 , XCORE_INS_ENDING = 121 , } # [repr (u32)] # [doc = " Group of XCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn_group { # [doc = "< = CS_GRP_INVALID"] XCORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] XCORE_GRP_JUMP = 1 , XCORE_GRP_ENDING = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] TMS320C64X_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] TMS320C64X_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] TMS320C64X_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] TMS320C64X_OP_MEM = 3 , # [doc = "< Register pair for double word ops"] TMS320C64X_OP_REGPAIR = 64 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0 , TMS320C64X_MEM_DISP_CONSTANT = 1 , TMS320C64X_MEM_DISP_REGISTER = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0 , TMS320C64X_MEM_DIR_FW = 1 , TMS320C64X_MEM_DIR_BW = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0 , TMS320C64X_MEM_MOD_NO = 1 , TMS320C64X_MEM_MOD_PRE = 2 , TMS320C64X_MEM_MOD_POST = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tms320c64x_op_mem { # [doc = "< base register"] pub base : :: std :: os :: raw :: c_uint , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_uint , # [doc = "< unit of base and offset register"] pub unit : :: std :: os :: raw :: c_uint , # [doc = "< offset scaled"] pub scaled : :: std :: os :: raw :: c_uint , # [doc = "< displacement type"] pub disptype : :: std :: os :: raw :: c_uint , # [doc = "< direction"] pub direction : :: std :: os :: raw :: c_uint , # [doc = "< modification"] pub modify : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tms320c64x_op_mem"] [:: std :: mem :: size_of :: < tms320c64x_op_mem > () - 28usize] ; ["Alignment of tms320c64x_op_mem"] [:: std :: mem :: align_of :: < tms320c64x_op_mem > () - 4usize] ; ["Offset of field: tms320c64x_op_mem::base"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , base) - 0usize] ; ["Offset of field: tms320c64x_op_mem::disp"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disp) - 4usize] ; ["Offset of field: tms320c64x_op_mem::unit"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , unit) - 8usize] ; ["Offset of field: tms320c64x_op_mem::scaled"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , scaled) - 12usize] ; ["Offset of field: tms320c64x_op_mem::disptype"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disptype) - 16usize] ; ["Offset of field: tms320c64x_op_mem::direction"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , direction) - 20usize] ; ["Offset of field: tms320c64x_op_mem::modify"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , modify) - 24usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x_op { # [doc = "< operand type"] pub type_ : tms320c64x_op_type , pub __bindgen_anon_1 : cs_tms320c64x_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tms320c64x_op__bindgen_ty_1 { # [doc = "< register value for REG operand or first register for REGPAIR operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tms320c64x_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 28usize] ; ["Alignment of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op"] [:: std :: mem :: size_of :: < cs_tms320c64x_op > () - 32usize] ; ["Alignment of cs_tms320c64x_op"] [:: std :: mem :: align_of :: < cs_tms320c64x_op > () - 4usize] ; ["Offset of field: cs_tms320c64x_op::type_"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x { pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tms320c64x_op ; 8usize] , pub condition : cs_tms320c64x__bindgen_ty_1 , pub funit : cs_tms320c64x__bindgen_ty_2 , pub parallel : :: std :: os :: raw :: c_uint , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub zero : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::zero"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , zero) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_2 { pub unit : :: std :: os :: raw :: c_uint , pub side : :: std :: os :: raw :: c_uint , pub crosspath : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_2 > () - 12usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_2 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::unit"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , unit) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::side"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , side) - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::crosspath"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , crosspath) - 8usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x"] [:: std :: mem :: size_of :: < cs_tms320c64x > () - 284usize] ; ["Alignment of cs_tms320c64x"] [:: std :: mem :: align_of :: < cs_tms320c64x > () - 4usize] ; ["Offset of field: cs_tms320c64x::op_count"] [:: std :: mem :: offset_of ! (cs_tms320c64x , op_count) - 0usize] ; ["Offset of field: cs_tms320c64x::operands"] [:: std :: mem :: offset_of ! (cs_tms320c64x , operands) - 4usize] ; ["Offset of field: cs_tms320c64x::condition"] [:: std :: mem :: offset_of ! (cs_tms320c64x , condition) - 260usize] ; ["Offset of field: cs_tms320c64x::funit"] [:: std :: mem :: offset_of ! (cs_tms320c64x , funit) - 268usize] ; ["Offset of field: cs_tms320c64x::parallel"] [:: std :: mem :: offset_of ! (cs_tms320c64x , parallel) - 280usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel) } } impl tms320c64x_reg { pub const TMS320C64X_REG_EFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ECR ; } impl tms320c64x_reg { pub const TMS320C64X_REG_IFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ISR ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0 , TMS320C64X_REG_AMR = 1 , TMS320C64X_REG_CSR = 2 , TMS320C64X_REG_DIER = 3 , TMS320C64X_REG_DNUM = 4 , TMS320C64X_REG_ECR = 5 , TMS320C64X_REG_GFPGFR = 6 , TMS320C64X_REG_GPLYA = 7 , TMS320C64X_REG_GPLYB = 8 , TMS320C64X_REG_ICR = 9 , TMS320C64X_REG_IER = 10 , TMS320C64X_REG_IERR = 11 , TMS320C64X_REG_ILC = 12 , TMS320C64X_REG_IRP = 13 , TMS320C64X_REG_ISR = 14 , TMS320C64X_REG_ISTP = 15 , TMS320C64X_REG_ITSR = 16 , TMS320C64X_REG_NRP = 17 , TMS320C64X_REG_NTSR = 18 , TMS320C64X_REG_REP = 19 , TMS320C64X_REG_RILC = 20 , TMS320C64X_REG_SSR = 21 , TMS320C64X_REG_TSCH = 22 , TMS320C64X_REG_TSCL = 23 , TMS320C64X_REG_TSR = 24 , TMS320C64X_REG_A0 = 25 , TMS320C64X_REG_A1 = 26 , TMS320C64X_REG_A2 = 27 , TMS320C64X_REG_A3 = 28 , TMS320C64X_REG_A4 = 29 , TMS320C64X_REG_A5 = 30 , TMS320C64X_REG_A6 = 31 , TMS320C64X_REG_A7 = 32 , TMS320C64X_REG_A8 = 33 , TMS320C64X_REG_A9 = 34 , TMS320C64X_REG_A10 = 35 , TMS320C64X_REG_A11 = 36 , TMS320C64X_REG_A12 = 37 , TMS320C64X_REG_A13 = 38 , TMS320C64X_REG_A14 = 39 , TMS320C64X_REG_A15 = 40 , TMS320C64X_REG_A16 = 41 , TMS320C64X_REG_A17 = 42 , TMS320C64X_REG_A18 = 43 , TMS320C64X_REG_A19 = 44 , TMS320C64X_REG_A20 = 45 , TMS320C64X_REG_A21 = 46 , TMS320C64X_REG_A22 = 47 , TMS320C64X_REG_A23 = 48 , TMS320C64X_REG_A24 = 49 , TMS320C64X_REG_A25 = 50 , TMS320C64X_REG_A26 = 51 , TMS320C64X_REG_A27 = 52 , TMS320C64X_REG_A28 = 53 , TMS320C64X_REG_A29 = 54 , TMS320C64X_REG_A30 = 55 , TMS320C64X_REG_A31 = 56 , TMS320C64X_REG_B0 = 57 , TMS320C64X_REG_B1 = 58 , TMS320C64X_REG_B2 = 59 , TMS320C64X_REG_B3 = 60 , TMS320C64X_REG_B4 = 61 , TMS320C64X_REG_B5 = 62 , TMS320C64X_REG_B6 = 63 , TMS320C64X_REG_B7 = 64 , TMS320C64X_REG_B8 = 65 , TMS320C64X_REG_B9 = 66 , TMS320C64X_REG_B10 = 67 , TMS320C64X_REG_B11 = 68 , TMS320C64X_REG_B12 = 69 , TMS320C64X_REG_B13 = 70 , TMS320C64X_REG_B14 = 71 , TMS320C64X_REG_B15 = 72 , TMS320C64X_REG_B16 = 73 , TMS320C64X_REG_B17 = 74 , TMS320C64X_REG_B18 = 75 , TMS320C64X_REG_B19 = 76 , TMS320C64X_REG_B20 = 77 , TMS320C64X_REG_B21 = 78 , TMS320C64X_REG_B22 = 79 , TMS320C64X_REG_B23 = 80 , TMS320C64X_REG_B24 = 81 , TMS320C64X_REG_B25 = 82 , TMS320C64X_REG_B26 = 83 , TMS320C64X_REG_B27 = 84 , TMS320C64X_REG_B28 = 85 , TMS320C64X_REG_B29 = 86 , TMS320C64X_REG_B30 = 87 , TMS320C64X_REG_B31 = 88 , TMS320C64X_REG_PCE1 = 89 , TMS320C64X_REG_ENDING = 90 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0 , TMS320C64X_INS_ABS = 1 , TMS320C64X_INS_ABS2 = 2 , TMS320C64X_INS_ADD = 3 , TMS320C64X_INS_ADD2 = 4 , TMS320C64X_INS_ADD4 = 5 , TMS320C64X_INS_ADDAB = 6 , TMS320C64X_INS_ADDAD = 7 , TMS320C64X_INS_ADDAH = 8 , TMS320C64X_INS_ADDAW = 9 , TMS320C64X_INS_ADDK = 10 , TMS320C64X_INS_ADDKPC = 11 , TMS320C64X_INS_ADDU = 12 , TMS320C64X_INS_AND = 13 , TMS320C64X_INS_ANDN = 14 , TMS320C64X_INS_AVG2 = 15 , TMS320C64X_INS_AVGU4 = 16 , TMS320C64X_INS_B = 17 , TMS320C64X_INS_BDEC = 18 , TMS320C64X_INS_BITC4 = 19 , TMS320C64X_INS_BNOP = 20 , TMS320C64X_INS_BPOS = 21 , TMS320C64X_INS_CLR = 22 , TMS320C64X_INS_CMPEQ = 23 , TMS320C64X_INS_CMPEQ2 = 24 , TMS320C64X_INS_CMPEQ4 = 25 , TMS320C64X_INS_CMPGT = 26 , TMS320C64X_INS_CMPGT2 = 27 , TMS320C64X_INS_CMPGTU4 = 28 , TMS320C64X_INS_CMPLT = 29 , TMS320C64X_INS_CMPLTU = 30 , TMS320C64X_INS_DEAL = 31 , TMS320C64X_INS_DOTP2 = 32 , TMS320C64X_INS_DOTPN2 = 33 , TMS320C64X_INS_DOTPNRSU2 = 34 , TMS320C64X_INS_DOTPRSU2 = 35 , TMS320C64X_INS_DOTPSU4 = 36 , TMS320C64X_INS_DOTPU4 = 37 , TMS320C64X_INS_EXT = 38 , TMS320C64X_INS_EXTU = 39 , TMS320C64X_INS_GMPGTU = 40 , TMS320C64X_INS_GMPY4 = 41 , TMS320C64X_INS_LDB = 42 , TMS320C64X_INS_LDBU = 43 , TMS320C64X_INS_LDDW = 44 , TMS320C64X_INS_LDH = 45 , TMS320C64X_INS_LDHU = 46 , TMS320C64X_INS_LDNDW = 47 , TMS320C64X_INS_LDNW = 48 , TMS320C64X_INS_LDW = 49 , TMS320C64X_INS_LMBD = 50 , TMS320C64X_INS_MAX2 = 51 , TMS320C64X_INS_MAXU4 = 52 , TMS320C64X_INS_MIN2 = 53 , TMS320C64X_INS_MINU4 = 54 , TMS320C64X_INS_MPY = 55 , TMS320C64X_INS_MPY2 = 56 , TMS320C64X_INS_MPYH = 57 , TMS320C64X_INS_MPYHI = 58 , TMS320C64X_INS_MPYHIR = 59 , TMS320C64X_INS_MPYHL = 60 , TMS320C64X_INS_MPYHLU = 61 , TMS320C64X_INS_MPYHSLU = 62 , TMS320C64X_INS_MPYHSU = 63 , TMS320C64X_INS_MPYHU = 64 , TMS320C64X_INS_MPYHULS = 65 , TMS320C64X_INS_MPYHUS = 66 , TMS320C64X_INS_MPYLH = 67 , TMS320C64X_INS_MPYLHU = 68 , TMS320C64X_INS_MPYLI = 69 , TMS320C64X_INS_MPYLIR = 70 , TMS320C64X_INS_MPYLSHU = 71 , TMS320C64X_INS_MPYLUHS = 72 , TMS320C64X_INS_MPYSU = 73 , TMS320C64X_INS_MPYSU4 = 74 , TMS320C64X_INS_MPYU = 75 , TMS320C64X_INS_MPYU4 = 76 , TMS320C64X_INS_MPYUS = 77 , TMS320C64X_INS_MVC = 78 , TMS320C64X_INS_MVD = 79 , TMS320C64X_INS_MVK = 80 , TMS320C64X_INS_MVKL = 81 , TMS320C64X_INS_MVKLH = 82 , TMS320C64X_INS_NOP = 83 , TMS320C64X_INS_NORM = 84 , TMS320C64X_INS_OR = 85 , TMS320C64X_INS_PACK2 = 86 , TMS320C64X_INS_PACKH2 = 87 , TMS320C64X_INS_PACKH4 = 88 , TMS320C64X_INS_PACKHL2 = 89 , TMS320C64X_INS_PACKL4 = 90 , TMS320C64X_INS_PACKLH2 = 91 , TMS320C64X_INS_ROTL = 92 , TMS320C64X_INS_SADD = 93 , TMS320C64X_INS_SADD2 = 94 , TMS320C64X_INS_SADDU4 = 95 , TMS320C64X_INS_SADDUS2 = 96 , TMS320C64X_INS_SAT = 97 , TMS320C64X_INS_SET = 98 , TMS320C64X_INS_SHFL = 99 , TMS320C64X_INS_SHL = 100 , TMS320C64X_INS_SHLMB = 101 , TMS320C64X_INS_SHR = 102 , TMS320C64X_INS_SHR2 = 103 , TMS320C64X_INS_SHRMB = 104 , TMS320C64X_INS_SHRU = 105 , TMS320C64X_INS_SHRU2 = 106 , TMS320C64X_INS_SMPY = 107 , TMS320C64X_INS_SMPY2 = 108 , TMS320C64X_INS_SMPYH = 109 , TMS320C64X_INS_SMPYHL = 110 , TMS320C64X_INS_SMPYLH = 111 , TMS320C64X_INS_SPACK2 = 112 , TMS320C64X_INS_SPACKU4 = 113 , TMS320C64X_INS_SSHL = 114 , TMS320C64X_INS_SSHVL = 115 , TMS320C64X_INS_SSHVR = 116 , TMS320C64X_INS_SSUB = 117 , TMS320C64X_INS_STB = 118 , TMS320C64X_INS_STDW = 119 , TMS320C64X_INS_STH = 120 , TMS320C64X_INS_STNDW = 121 , TMS320C64X_INS_STNW = 122 , TMS320C64X_INS_STW = 123 , TMS320C64X_INS_SUB = 124 , TMS320C64X_INS_SUB2 = 125 , TMS320C64X_INS_SUB4 = 126 , TMS320C64X_INS_SUBAB = 127 , TMS320C64X_INS_SUBABS4 = 128 , TMS320C64X_INS_SUBAH = 129 , TMS320C64X_INS_SUBAW = 130 , TMS320C64X_INS_SUBC = 131 , TMS320C64X_INS_SUBU = 132 , TMS320C64X_INS_SWAP4 = 133 , TMS320C64X_INS_UNPKHU4 = 134 , TMS320C64X_INS_UNPKLU4 = 135 , TMS320C64X_INS_XOR = 136 , TMS320C64X_INS_XPND2 = 137 , TMS320C64X_INS_XPND4 = 138 , TMS320C64X_INS_IDLE = 139 , TMS320C64X_INS_MV = 140 , TMS320C64X_INS_NEG = 141 , TMS320C64X_INS_NOT = 142 , TMS320C64X_INS_SWAP2 = 143 , TMS320C64X_INS_ZERO = 144 , TMS320C64X_INS_ENDING = 145 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn_group { # [doc = "< = CS_GRP_INVALID"] TMS320C64X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] TMS320C64X_GRP_JUMP = 1 , TMS320C64X_GRP_FUNIT_D = 128 , TMS320C64X_GRP_FUNIT_L = 129 , TMS320C64X_GRP_FUNIT_M = 130 , TMS320C64X_GRP_FUNIT_S = 131 , TMS320C64X_GRP_FUNIT_NO = 132 , TMS320C64X_GRP_ENDING = 133 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0 , TMS320C64X_FUNIT_D = 1 , TMS320C64X_FUNIT_L = 2 , TMS320C64X_FUNIT_M = 3 , TMS320C64X_FUNIT_S = 4 , TMS320C64X_FUNIT_NO = 5 , } # [repr (u32)] # [doc = " M680X registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_reg { M680X_REG_INVALID = 0 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_A = 1 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_B = 2 , # [doc = "< HD6309"] M680X_REG_E = 3 , # [doc = "< HD6309"] M680X_REG_F = 4 , # [doc = "< HD6309"] M680X_REG_0 = 5 , # [doc = "< M6801/3/9, HD6301/9"] M680X_REG_D = 6 , # [doc = "< HD6309"] M680X_REG_W = 7 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_CC = 8 , # [doc = "< M6809/M6309"] M680X_REG_DP = 9 , # [doc = "< M6309"] M680X_REG_MD = 10 , # [doc = "< M6808"] M680X_REG_HX = 11 , # [doc = "< M6808"] M680X_REG_H = 12 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_X = 13 , # [doc = "< M6809/M6309"] M680X_REG_Y = 14 , # [doc = "< M6809/M6309"] M680X_REG_S = 15 , # [doc = "< M6809/M6309"] M680X_REG_U = 16 , # [doc = "< M6309"] M680X_REG_V = 17 , # [doc = "< M6309"] M680X_REG_Q = 18 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_PC = 19 , # [doc = "< CPU12"] M680X_REG_TMP2 = 20 , # [doc = "< CPU12"] M680X_REG_TMP3 = 21 , # [doc = "< <-- mark the end of the list of registers"] M680X_REG_ENDING = 22 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M680X_OP_INVALID = 0 , # [doc = "< = Register operand."] M680X_OP_REGISTER = 1 , # [doc = "< = Immediate operand."] M680X_OP_IMMEDIATE = 2 , # [doc = "< = Indexed addressing operand."] M680X_OP_INDEXED = 3 , # [doc = "< = Extended addressing operand."] M680X_OP_EXTENDED = 4 , # [doc = "< = Direct addressing operand."] M680X_OP_DIRECT = 5 , # [doc = "< = Relative addressing operand."] M680X_OP_RELATIVE = 6 , # [doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."] M680X_OP_CONSTANT = 7 , } # [doc = " Instruction's operand referring to indexed addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_idx { # [doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"] pub base_reg : m680x_reg , # [doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"] pub offset_reg : m680x_reg , # [doc = "< 5-,8- or 16-bit offset. See also offset_bits."] pub offset : i16 , # [doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"] pub offset_addr : u16 , # [doc = "< offset width in bits for indexed addressing"] pub offset_bits : u8 , # [doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"] pub inc_dec : i8 , # [doc = "< 8-bit flags (see above)"] pub flags : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_idx"] [:: std :: mem :: size_of :: < m680x_op_idx > () - 16usize] ; ["Alignment of m680x_op_idx"] [:: std :: mem :: align_of :: < m680x_op_idx > () - 4usize] ; ["Offset of field: m680x_op_idx::base_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , base_reg) - 0usize] ; ["Offset of field: m680x_op_idx::offset_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_reg) - 4usize] ; ["Offset of field: m680x_op_idx::offset"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset) - 8usize] ; ["Offset of field: m680x_op_idx::offset_addr"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_addr) - 10usize] ; ["Offset of field: m680x_op_idx::offset_bits"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_bits) - 12usize] ; ["Offset of field: m680x_op_idx::inc_dec"] [:: std :: mem :: offset_of ! (m680x_op_idx , inc_dec) - 13usize] ; ["Offset of field: m680x_op_idx::flags"] [:: std :: mem :: offset_of ! (m680x_op_idx , flags) - 14usize] ; } ; # [doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_rel { # [doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."] pub address : u16 , # [doc = "< the offset/displacement value"] pub offset : i16 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_rel"] [:: std :: mem :: size_of :: < m680x_op_rel > () - 4usize] ; ["Alignment of m680x_op_rel"] [:: std :: mem :: align_of :: < m680x_op_rel > () - 2usize] ; ["Offset of field: m680x_op_rel::address"] [:: std :: mem :: offset_of ! (m680x_op_rel , address) - 0usize] ; ["Offset of field: m680x_op_rel::offset"] [:: std :: mem :: offset_of ! (m680x_op_rel , offset) - 2usize] ; } ; # [doc = " Instruction's operand referring to extended addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_ext { # [doc = "< The absolute address"] pub address : u16 , # [doc = "< true if extended indirect addressing"] pub indirect : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_ext"] [:: std :: mem :: size_of :: < m680x_op_ext > () - 4usize] ; ["Alignment of m680x_op_ext"] [:: std :: mem :: align_of :: < m680x_op_ext > () - 2usize] ; ["Offset of field: m680x_op_ext::address"] [:: std :: mem :: offset_of ! (m680x_op_ext , address) - 0usize] ; ["Offset of field: m680x_op_ext::indirect"] [:: std :: mem :: offset_of ! (m680x_op_ext , indirect) - 2usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x_op { pub type_ : m680x_op_type , pub __bindgen_anon_1 : cs_m680x_op__bindgen_ty_1 , # [doc = "< size of this operand (in bytes)"] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m680x_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< register value for REG operand"] pub reg : m680x_reg , # [doc = "< Indexed addressing operand"] pub idx : m680x_op_idx , # [doc = "< Relative address. operand (Bcc/LBcc)"] pub rel : m680x_op_rel , # [doc = "< Extended address"] pub ext : m680x_op_ext , # [doc = "<</ Direct address (lower 8-bit)"] pub direct_addr : u8 , # [doc = "< constant value (bit index, page nr.)"] pub const_val : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m680x_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m680x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::idx"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , idx) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::rel"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , rel) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , ext) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::direct_addr"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , direct_addr) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::const_val"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , const_val) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op"] [:: std :: mem :: size_of :: < cs_m680x_op > () - 24usize] ; ["Alignment of cs_m680x_op"] [:: std :: mem :: align_of :: < cs_m680x_op > () - 4usize] ; ["Offset of field: cs_m680x_op::type_"] [:: std :: mem :: offset_of ! (cs_m680x_op , type_) - 0usize] ; ["Offset of field: cs_m680x_op::size"] [:: std :: mem :: offset_of ! (cs_m680x_op , size) - 20usize] ; ["Offset of field: cs_m680x_op::access"] [:: std :: mem :: offset_of ! (cs_m680x_op , access) - 21usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access) } } # [repr (u32)] # [doc = " Group of M680X instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_group_type { M680X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M680X_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] M680X_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] M680X_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] M680X_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] M680X_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEDGE; not used"] M680X_GRP_PRIV = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M680X_GRP_BRAREL = 7 , M680X_GRP_ENDING = 8 , } # [doc = " The M680X instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x { # [doc = "< See: M680X instruction flags"] pub flags : u8 , # [doc = "< number of operands for the instruction or 0"] pub op_count : u8 , # [doc = "< operands for this insn."] pub operands : [cs_m680x_op ; 9usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x"] [:: std :: mem :: size_of :: < cs_m680x > () - 220usize] ; ["Alignment of cs_m680x"] [:: std :: mem :: align_of :: < cs_m680x > () - 4usize] ; ["Offset of field: cs_m680x::flags"] [:: std :: mem :: offset_of ! (cs_m680x , flags) - 0usize] ; ["Offset of field: cs_m680x::op_count"] [:: std :: mem :: offset_of ! (cs_m680x , op_count) - 1usize] ; ["Offset of field: cs_m680x::operands"] [:: std :: mem :: offset_of ! (cs_m680x , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " M680X instruction IDs"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_insn { M680X_INS_INVLD = 0 , # [doc = "< M6800/1/2/3"] M680X_INS_ABA = 1 , M680X_INS_ABX = 2 , M680X_INS_ABY = 3 , M680X_INS_ADC = 4 , M680X_INS_ADCA = 5 , M680X_INS_ADCB = 6 , M680X_INS_ADCD = 7 , M680X_INS_ADCR = 8 , M680X_INS_ADD = 9 , M680X_INS_ADDA = 10 , M680X_INS_ADDB = 11 , M680X_INS_ADDD = 12 , M680X_INS_ADDE = 13 , M680X_INS_ADDF = 14 , M680X_INS_ADDR = 15 , M680X_INS_ADDW = 16 , M680X_INS_AIM = 17 , M680X_INS_AIS = 18 , M680X_INS_AIX = 19 , M680X_INS_AND = 20 , M680X_INS_ANDA = 21 , M680X_INS_ANDB = 22 , M680X_INS_ANDCC = 23 , M680X_INS_ANDD = 24 , M680X_INS_ANDR = 25 , M680X_INS_ASL = 26 , M680X_INS_ASLA = 27 , M680X_INS_ASLB = 28 , # [doc = "< or LSLD"] M680X_INS_ASLD = 29 , M680X_INS_ASR = 30 , M680X_INS_ASRA = 31 , M680X_INS_ASRB = 32 , M680X_INS_ASRD = 33 , M680X_INS_ASRX = 34 , M680X_INS_BAND = 35 , # [doc = "< or BHS"] M680X_INS_BCC = 36 , M680X_INS_BCLR = 37 , # [doc = "< or BLO"] M680X_INS_BCS = 38 , M680X_INS_BEOR = 39 , M680X_INS_BEQ = 40 , M680X_INS_BGE = 41 , M680X_INS_BGND = 42 , M680X_INS_BGT = 43 , M680X_INS_BHCC = 44 , M680X_INS_BHCS = 45 , M680X_INS_BHI = 46 , M680X_INS_BIAND = 47 , M680X_INS_BIEOR = 48 , M680X_INS_BIH = 49 , M680X_INS_BIL = 50 , M680X_INS_BIOR = 51 , M680X_INS_BIT = 52 , M680X_INS_BITA = 53 , M680X_INS_BITB = 54 , M680X_INS_BITD = 55 , M680X_INS_BITMD = 56 , M680X_INS_BLE = 57 , M680X_INS_BLS = 58 , M680X_INS_BLT = 59 , M680X_INS_BMC = 60 , M680X_INS_BMI = 61 , M680X_INS_BMS = 62 , M680X_INS_BNE = 63 , M680X_INS_BOR = 64 , M680X_INS_BPL = 65 , M680X_INS_BRCLR = 66 , M680X_INS_BRSET = 67 , M680X_INS_BRA = 68 , M680X_INS_BRN = 69 , M680X_INS_BSET = 70 , M680X_INS_BSR = 71 , M680X_INS_BVC = 72 , M680X_INS_BVS = 73 , M680X_INS_CALL = 74 , # [doc = "< M6800/1/2/3"] M680X_INS_CBA = 75 , M680X_INS_CBEQ = 76 , M680X_INS_CBEQA = 77 , M680X_INS_CBEQX = 78 , # [doc = "< M6800/1/2/3"] M680X_INS_CLC = 79 , # [doc = "< M6800/1/2/3"] M680X_INS_CLI = 80 , M680X_INS_CLR = 81 , M680X_INS_CLRA = 82 , M680X_INS_CLRB = 83 , M680X_INS_CLRD = 84 , M680X_INS_CLRE = 85 , M680X_INS_CLRF = 86 , M680X_INS_CLRH = 87 , M680X_INS_CLRW = 88 , M680X_INS_CLRX = 89 , # [doc = "< M6800/1/2/3"] M680X_INS_CLV = 90 , M680X_INS_CMP = 91 , M680X_INS_CMPA = 92 , M680X_INS_CMPB = 93 , M680X_INS_CMPD = 94 , M680X_INS_CMPE = 95 , M680X_INS_CMPF = 96 , M680X_INS_CMPR = 97 , M680X_INS_CMPS = 98 , M680X_INS_CMPU = 99 , M680X_INS_CMPW = 100 , M680X_INS_CMPX = 101 , M680X_INS_CMPY = 102 , M680X_INS_COM = 103 , M680X_INS_COMA = 104 , M680X_INS_COMB = 105 , M680X_INS_COMD = 106 , M680X_INS_COME = 107 , M680X_INS_COMF = 108 , M680X_INS_COMW = 109 , M680X_INS_COMX = 110 , M680X_INS_CPD = 111 , M680X_INS_CPHX = 112 , M680X_INS_CPS = 113 , # [doc = "< M6800/1/2/3"] M680X_INS_CPX = 114 , M680X_INS_CPY = 115 , M680X_INS_CWAI = 116 , M680X_INS_DAA = 117 , M680X_INS_DBEQ = 118 , M680X_INS_DBNE = 119 , M680X_INS_DBNZ = 120 , M680X_INS_DBNZA = 121 , M680X_INS_DBNZX = 122 , M680X_INS_DEC = 123 , M680X_INS_DECA = 124 , M680X_INS_DECB = 125 , M680X_INS_DECD = 126 , M680X_INS_DECE = 127 , M680X_INS_DECF = 128 , M680X_INS_DECW = 129 , M680X_INS_DECX = 130 , # [doc = "< M6800/1/2/3"] M680X_INS_DES = 131 , # [doc = "< M6800/1/2/3"] M680X_INS_DEX = 132 , M680X_INS_DEY = 133 , M680X_INS_DIV = 134 , M680X_INS_DIVD = 135 , M680X_INS_DIVQ = 136 , M680X_INS_EDIV = 137 , M680X_INS_EDIVS = 138 , M680X_INS_EIM = 139 , M680X_INS_EMACS = 140 , M680X_INS_EMAXD = 141 , M680X_INS_EMAXM = 142 , M680X_INS_EMIND = 143 , M680X_INS_EMINM = 144 , M680X_INS_EMUL = 145 , M680X_INS_EMULS = 146 , M680X_INS_EOR = 147 , M680X_INS_EORA = 148 , M680X_INS_EORB = 149 , M680X_INS_EORD = 150 , M680X_INS_EORR = 151 , M680X_INS_ETBL = 152 , M680X_INS_EXG = 153 , M680X_INS_FDIV = 154 , M680X_INS_IBEQ = 155 , M680X_INS_IBNE = 156 , M680X_INS_IDIV = 157 , M680X_INS_IDIVS = 158 , M680X_INS_ILLGL = 159 , M680X_INS_INC = 160 , M680X_INS_INCA = 161 , M680X_INS_INCB = 162 , M680X_INS_INCD = 163 , M680X_INS_INCE = 164 , M680X_INS_INCF = 165 , M680X_INS_INCW = 166 , M680X_INS_INCX = 167 , # [doc = "< M6800/1/2/3"] M680X_INS_INS = 168 , # [doc = "< M6800/1/2/3"] M680X_INS_INX = 169 , M680X_INS_INY = 170 , M680X_INS_JMP = 171 , M680X_INS_JSR = 172 , # [doc = "< or LBHS"] M680X_INS_LBCC = 173 , # [doc = "< or LBLO"] M680X_INS_LBCS = 174 , M680X_INS_LBEQ = 175 , M680X_INS_LBGE = 176 , M680X_INS_LBGT = 177 , M680X_INS_LBHI = 178 , M680X_INS_LBLE = 179 , M680X_INS_LBLS = 180 , M680X_INS_LBLT = 181 , M680X_INS_LBMI = 182 , M680X_INS_LBNE = 183 , M680X_INS_LBPL = 184 , M680X_INS_LBRA = 185 , M680X_INS_LBRN = 186 , M680X_INS_LBSR = 187 , M680X_INS_LBVC = 188 , M680X_INS_LBVS = 189 , M680X_INS_LDA = 190 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAA = 191 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAB = 192 , M680X_INS_LDB = 193 , M680X_INS_LDBT = 194 , M680X_INS_LDD = 195 , M680X_INS_LDE = 196 , M680X_INS_LDF = 197 , M680X_INS_LDHX = 198 , M680X_INS_LDMD = 199 , M680X_INS_LDQ = 200 , M680X_INS_LDS = 201 , M680X_INS_LDU = 202 , M680X_INS_LDW = 203 , M680X_INS_LDX = 204 , M680X_INS_LDY = 205 , M680X_INS_LEAS = 206 , M680X_INS_LEAU = 207 , M680X_INS_LEAX = 208 , M680X_INS_LEAY = 209 , M680X_INS_LSL = 210 , M680X_INS_LSLA = 211 , M680X_INS_LSLB = 212 , M680X_INS_LSLD = 213 , M680X_INS_LSLX = 214 , M680X_INS_LSR = 215 , M680X_INS_LSRA = 216 , M680X_INS_LSRB = 217 , # [doc = "< or ASRD"] M680X_INS_LSRD = 218 , M680X_INS_LSRW = 219 , M680X_INS_LSRX = 220 , M680X_INS_MAXA = 221 , M680X_INS_MAXM = 222 , M680X_INS_MEM = 223 , M680X_INS_MINA = 224 , M680X_INS_MINM = 225 , M680X_INS_MOV = 226 , M680X_INS_MOVB = 227 , M680X_INS_MOVW = 228 , M680X_INS_MUL = 229 , M680X_INS_MULD = 230 , M680X_INS_NEG = 231 , M680X_INS_NEGA = 232 , M680X_INS_NEGB = 233 , M680X_INS_NEGD = 234 , M680X_INS_NEGX = 235 , M680X_INS_NOP = 236 , M680X_INS_NSA = 237 , M680X_INS_OIM = 238 , M680X_INS_ORA = 239 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAA = 240 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAB = 241 , M680X_INS_ORB = 242 , M680X_INS_ORCC = 243 , M680X_INS_ORD = 244 , M680X_INS_ORR = 245 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHA = 246 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHB = 247 , M680X_INS_PSHC = 248 , M680X_INS_PSHD = 249 , M680X_INS_PSHH = 250 , M680X_INS_PSHS = 251 , M680X_INS_PSHSW = 252 , M680X_INS_PSHU = 253 , M680X_INS_PSHUW = 254 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHX = 255 , M680X_INS_PSHY = 256 , # [doc = "< M6800/1/2/3"] M680X_INS_PULA = 257 , # [doc = "< M6800/1/2/3"] M680X_INS_PULB = 258 , M680X_INS_PULC = 259 , M680X_INS_PULD = 260 , M680X_INS_PULH = 261 , M680X_INS_PULS = 262 , M680X_INS_PULSW = 263 , M680X_INS_PULU = 264 , M680X_INS_PULUW = 265 , # [doc = "< M6800/1/2/3"] M680X_INS_PULX = 266 , M680X_INS_PULY = 267 , M680X_INS_REV = 268 , M680X_INS_REVW = 269 , M680X_INS_ROL = 270 , M680X_INS_ROLA = 271 , M680X_INS_ROLB = 272 , M680X_INS_ROLD = 273 , M680X_INS_ROLW = 274 , M680X_INS_ROLX = 275 , M680X_INS_ROR = 276 , M680X_INS_RORA = 277 , M680X_INS_RORB = 278 , M680X_INS_RORD = 279 , M680X_INS_RORW = 280 , M680X_INS_RORX = 281 , M680X_INS_RSP = 282 , M680X_INS_RTC = 283 , M680X_INS_RTI = 284 , M680X_INS_RTS = 285 , # [doc = "< M6800/1/2/3"] M680X_INS_SBA = 286 , M680X_INS_SBC = 287 , M680X_INS_SBCA = 288 , M680X_INS_SBCB = 289 , M680X_INS_SBCD = 290 , M680X_INS_SBCR = 291 , M680X_INS_SEC = 292 , M680X_INS_SEI = 293 , M680X_INS_SEV = 294 , M680X_INS_SEX = 295 , M680X_INS_SEXW = 296 , M680X_INS_SLP = 297 , M680X_INS_STA = 298 , # [doc = "< M6800/1/2/3"] M680X_INS_STAA = 299 , # [doc = "< M6800/1/2/3"] M680X_INS_STAB = 300 , M680X_INS_STB = 301 , M680X_INS_STBT = 302 , M680X_INS_STD = 303 , M680X_INS_STE = 304 , M680X_INS_STF = 305 , M680X_INS_STOP = 306 , M680X_INS_STHX = 307 , M680X_INS_STQ = 308 , M680X_INS_STS = 309 , M680X_INS_STU = 310 , M680X_INS_STW = 311 , M680X_INS_STX = 312 , M680X_INS_STY = 313 , M680X_INS_SUB = 314 , M680X_INS_SUBA = 315 , M680X_INS_SUBB = 316 , M680X_INS_SUBD = 317 , M680X_INS_SUBE = 318 , M680X_INS_SUBF = 319 , M680X_INS_SUBR = 320 , M680X_INS_SUBW = 321 , M680X_INS_SWI = 322 , M680X_INS_SWI2 = 323 , M680X_INS_SWI3 = 324 , M680X_INS_SYNC = 325 , # [doc = "< M6800/1/2/3"] M680X_INS_TAB = 326 , # [doc = "< M6800/1/2/3"] M680X_INS_TAP = 327 , M680X_INS_TAX = 328 , # [doc = "< M6800/1/2/3"] M680X_INS_TBA = 329 , M680X_INS_TBEQ = 330 , M680X_INS_TBL = 331 , M680X_INS_TBNE = 332 , M680X_INS_TEST = 333 , M680X_INS_TFM = 334 , M680X_INS_TFR = 335 , M680X_INS_TIM = 336 , # [doc = "< M6800/1/2/3"] M680X_INS_TPA = 337 , M680X_INS_TST = 338 , M680X_INS_TSTA = 339 , M680X_INS_TSTB = 340 , M680X_INS_TSTD = 341 , M680X_INS_TSTE = 342 , M680X_INS_TSTF = 343 , M680X_INS_TSTW = 344 , M680X_INS_TSTX = 345 , # [doc = "< M6800/1/2/3"] M680X_INS_TSX = 346 , M680X_INS_TSY = 347 , M680X_INS_TXA = 348 , # [doc = "< M6800/1/2/3"] M680X_INS_TXS = 349 , M680X_INS_TYS = 350 , # [doc = "< M6800/1/2/3"] M680X_INS_WAI = 351 , M680X_INS_WAIT = 352 , M680X_INS_WAV = 353 , M680X_INS_WAVR = 354 , # [doc = "< HD6301"] M680X_INS_XGDX = 355 , M680X_INS_XGDY = 356 , M680X_INS_ENDING = 357 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_evm { # [doc = "< number of items popped from the stack"] pub pop : :: std :: os :: raw :: c_uchar , # [doc = "< number of items pushed into the stack"] pub push : :: std :: os :: raw :: c_uchar , # [doc = "< gas fee for the instruction"] pub fee : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_evm"] [:: std :: mem :: size_of :: < cs_evm > () - 8usize] ; ["Alignment of cs_evm"] [:: std :: mem :: align_of :: < cs_evm > () - 4usize] ; ["Offset of field: cs_evm::pop"] [:: std :: mem :: offset_of ! (cs_evm , pop) - 0usize] ; ["Offset of field: cs_evm::push"] [:: std :: mem :: offset_of ! (cs_evm , push) - 1usize] ; ["Offset of field: cs_evm::fee"] [:: std :: mem :: offset_of ! (cs_evm , fee) - 4usize] ; } ; # [repr (u32)] # [doc = " EVM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn { EVM_INS_STOP = 0 , EVM_INS_ADD = 1 , EVM_INS_MUL = 2 , EVM_INS_SUB = 3 , EVM_INS_DIV = 4 , EVM_INS_SDIV = 5 , EVM_INS_MOD = 6 , EVM_INS_SMOD = 7 , EVM_INS_ADDMOD = 8 , EVM_INS_MULMOD = 9 , EVM_INS_EXP = 10 , EVM_INS_SIGNEXTEND = 11 , EVM_INS_LT = 16 , EVM_INS_GT = 17 , EVM_INS_SLT = 18 , EVM_INS_SGT = 19 , EVM_INS_EQ = 20 , EVM_INS_ISZERO = 21 , EVM_INS_AND = 22 , EVM_INS_OR = 23 , EVM_INS_XOR = 24 , EVM_INS_NOT = 25 , EVM_INS_BYTE = 26 , EVM_INS_SHA3 = 32 , EVM_INS_ADDRESS = 48 , EVM_INS_BALANCE = 49 , EVM_INS_ORIGIN = 50 , EVM_INS_CALLER = 51 , EVM_INS_CALLVALUE = 52 , EVM_INS_CALLDATALOAD = 53 , EVM_INS_CALLDATASIZE = 54 , EVM_INS_CALLDATACOPY = 55 , EVM_INS_CODESIZE = 56 , EVM_INS_CODECOPY = 57 , EVM_INS_GASPRICE = 58 , EVM_INS_EXTCODESIZE = 59 , EVM_INS_EXTCODECOPY = 60 , EVM_INS_RETURNDATASIZE = 61 , EVM_INS_RETURNDATACOPY = 62 , EVM_INS_BLOCKHASH = 64 , EVM_INS_COINBASE = 65 , EVM_INS_TIMESTAMP = 66 , EVM_INS_NUMBER = 67 , EVM_INS_DIFFICULTY = 68 , EVM_INS_GASLIMIT = 69 , EVM_INS_POP = 80 , EVM_INS_MLOAD = 81 , EVM_INS_MSTORE = 82 , EVM_INS_MSTORE8 = 83 , EVM_INS_SLOAD = 84 , EVM_INS_SSTORE = 85 , EVM_INS_JUMP = 86 , EVM_INS_JUMPI = 87 , EVM_INS_PC = 88 , EVM_INS_MSIZE = 89 , EVM_INS_GAS = 90 , EVM_INS_JUMPDEST = 91 , EVM_INS_PUSH1 = 96 , EVM_INS_PUSH2 = 97 , EVM_INS_PUSH3 = 98 , EVM_INS_PUSH4 = 99 , EVM_INS_PUSH5 = 100 , EVM_INS_PUSH6 = 101 , EVM_INS_PUSH7 = 102 , EVM_INS_PUSH8 = 103 , EVM_INS_PUSH9 = 104 , EVM_INS_PUSH10 = 105 , EVM_INS_PUSH11 = 106 , EVM_INS_PUSH12 = 107 , EVM_INS_PUSH13 = 108 , EVM_INS_PUSH14 = 109 , EVM_INS_PUSH15 = 110 , EVM_INS_PUSH16 = 111 , EVM_INS_PUSH17 = 112 , EVM_INS_PUSH18 = 113 , EVM_INS_PUSH19 = 114 , EVM_INS_PUSH20 = 115 , EVM_INS_PUSH21 = 116 , EVM_INS_PUSH22 = 117 , EVM_INS_PUSH23 = 118 , EVM_INS_PUSH24 = 119 , EVM_INS_PUSH25 = 120 , EVM_INS_PUSH26 = 121 , EVM_INS_PUSH27 = 122 , EVM_INS_PUSH28 = 123 , EVM_INS_PUSH29 = 124 , EVM_INS_PUSH30 = 125 , EVM_INS_PUSH31 = 126 , EVM_INS_PUSH32 = 127 , EVM_INS_DUP1 = 128 , EVM_INS_DUP2 = 129 , EVM_INS_DUP3 = 130 , EVM_INS_DUP4 = 131 , EVM_INS_DUP5 = 132 , EVM_INS_DUP6 = 133 , EVM_INS_DUP7 = 134 , EVM_INS_DUP8 = 135 , EVM_INS_DUP9 = 136 , EVM_INS_DUP10 = 137 , EVM_INS_DUP11 = 138 , EVM_INS_DUP12 = 139 , EVM_INS_DUP13 = 140 , EVM_INS_DUP14 = 141 , EVM_INS_DUP15 = 142 , EVM_INS_DUP16 = 143 , EVM_INS_SWAP1 = 144 , EVM_INS_SWAP2 = 145 , EVM_INS_SWAP3 = 146 , EVM_INS_SWAP4 = 147 , EVM_INS_SWAP5 = 148 , EVM_INS_SWAP6 = 149 , EVM_INS_SWAP7 = 150 , EVM_INS_SWAP8 = 151 , EVM_INS_SWAP9 = 152 , EVM_INS_SWAP10 = 153 , EVM_INS_SWAP11 = 154 , EVM_INS_SWAP12 = 155 , EVM_INS_SWAP13 = 156 , EVM_INS_SWAP14 = 157 , EVM_INS_SWAP15 = 158 , EVM_INS_SWAP16 = 159 , EVM_INS_LOG0 = 160 , EVM_INS_LOG1 = 161 , EVM_INS_LOG2 = 162 , EVM_INS_LOG3 = 163 , EVM_INS_LOG4 = 164 , EVM_INS_CREATE = 240 , EVM_INS_CALL = 241 , EVM_INS_CALLCODE = 242 , EVM_INS_RETURN = 243 , EVM_INS_DELEGATECALL = 244 , EVM_INS_CALLBLACKBOX = 245 , EVM_INS_STATICCALL = 250 , EVM_INS_REVERT = 253 , EVM_INS_SUICIDE = 255 , EVM_INS_INVALID = 512 , EVM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of EVM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn_group { # [doc = "< = CS_GRP_INVALID"] EVM_GRP_INVALID = 0 , # [doc = "< all jump instructions"] EVM_GRP_JUMP = 1 , # [doc = "< math instructions"] EVM_GRP_MATH = 8 , # [doc = "< instructions write to stack"] EVM_GRP_STACK_WRITE = 9 , # [doc = "< instructions read from stack"] EVM_GRP_STACK_READ = 10 , # [doc = "< instructions write to memory"] EVM_GRP_MEM_WRITE = 11 , # [doc = "< instructions read from memory"] EVM_GRP_MEM_READ = 12 , # [doc = "< instructions write to storage"] EVM_GRP_STORE_WRITE = 13 , # [doc = "< instructions read from storage"] EVM_GRP_STORE_READ = 14 , # [doc = "< instructions halt execution"] EVM_GRP_HALT = 15 , # [doc = "< <-- mark the end of the list of groups"] EVM_GRP_ENDING = 16 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_op_type { RISCV_OP_INVALID = 0 , RISCV_OP_REG = 1 , RISCV_OP_IMM = 2 , RISCV_OP_MEM = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct riscv_op_mem { pub base : :: std :: os :: raw :: c_uint , pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of riscv_op_mem"] [:: std :: mem :: size_of :: < riscv_op_mem > () - 16usize] ; ["Alignment of riscv_op_mem"] [:: std :: mem :: align_of :: < riscv_op_mem > () - 8usize] ; ["Offset of field: riscv_op_mem::base"] [:: std :: mem :: offset_of ! (riscv_op_mem , base) - 0usize] ; ["Offset of field: riscv_op_mem::disp"] [:: std :: mem :: offset_of ! (riscv_op_mem , disp) - 8usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv_op { pub type_ : riscv_op_type , pub __bindgen_anon_1 : cs_riscv_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_riscv_op__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub imm : i64 , pub mem : riscv_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_riscv_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_riscv_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op"] [:: std :: mem :: size_of :: < cs_riscv_op > () - 24usize] ; ["Alignment of cs_riscv_op"] [:: std :: mem :: align_of :: < cs_riscv_op > () - 8usize] ; ["Offset of field: cs_riscv_op::type_"] [:: std :: mem :: offset_of ! (cs_riscv_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv { pub need_effective_addr : bool , pub op_count : u8 , pub operands : [cs_riscv_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv"] [:: std :: mem :: size_of :: < cs_riscv > () - 200usize] ; ["Alignment of cs_riscv"] [:: std :: mem :: align_of :: < cs_riscv > () - 8usize] ; ["Offset of field: cs_riscv::need_effective_addr"] [:: std :: mem :: offset_of ! (cs_riscv , need_effective_addr) - 0usize] ; ["Offset of field: cs_riscv::op_count"] [:: std :: mem :: offset_of ! (cs_riscv , op_count) - 1usize] ; ["Offset of field: cs_riscv::operands"] [:: std :: mem :: offset_of ! (cs_riscv , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}" , self . need_effective_addr , self . op_count , self . operands) } } impl riscv_reg { pub const RISCV_REG_ZERO : riscv_reg = riscv_reg :: RISCV_REG_X0 ; } impl riscv_reg { pub const RISCV_REG_RA : riscv_reg = riscv_reg :: RISCV_REG_X1 ; } impl riscv_reg { pub const RISCV_REG_SP : riscv_reg = riscv_reg :: RISCV_REG_X2 ; } impl riscv_reg { pub const RISCV_REG_GP : riscv_reg = riscv_reg :: RISCV_REG_X3 ; } impl riscv_reg { pub const RISCV_REG_TP : riscv_reg = riscv_reg :: RISCV_REG_X4 ; } impl riscv_reg { pub const RISCV_REG_T0 : riscv_reg = riscv_reg :: RISCV_REG_X5 ; } impl riscv_reg { pub const RISCV_REG_T1 : riscv_reg = riscv_reg :: RISCV_REG_X6 ; } impl riscv_reg { pub const RISCV_REG_T2 : riscv_reg = riscv_reg :: RISCV_REG_X7 ; } impl riscv_reg { pub const RISCV_REG_S0 : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_FP : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_S1 : riscv_reg = riscv_reg :: RISCV_REG_X9 ; } impl riscv_reg { pub const RISCV_REG_A0 : riscv_reg = riscv_reg :: RISCV_REG_X10 ; } impl riscv_reg { pub const RISCV_REG_A1 : riscv_reg = riscv_reg :: RISCV_REG_X11 ; } impl riscv_reg { pub const RISCV_REG_A2 : riscv_reg = riscv_reg :: RISCV_REG_X12 ; } impl riscv_reg { pub const RISCV_REG_A3 : riscv_reg = riscv_reg :: RISCV_REG_X13 ; } impl riscv_reg { pub const RISCV_REG_A4 : riscv_reg = riscv_reg :: RISCV_REG_X14 ; } impl riscv_reg { pub const RISCV_REG_A5 : riscv_reg = riscv_reg :: RISCV_REG_X15 ; } impl riscv_reg { pub const RISCV_REG_A6 : riscv_reg = riscv_reg :: RISCV_REG_X16 ; } impl riscv_reg { pub const RISCV_REG_A7 : riscv_reg = riscv_reg :: RISCV_REG_X17 ; } impl riscv_reg { pub const RISCV_REG_S2 : riscv_reg = riscv_reg :: RISCV_REG_X18 ; } impl riscv_reg { pub const RISCV_REG_S3 : riscv_reg = riscv_reg :: RISCV_REG_X19 ; } impl riscv_reg { pub const RISCV_REG_S4 : riscv_reg = riscv_reg :: RISCV_REG_X20 ; } impl riscv_reg { pub const RISCV_REG_S5 : riscv_reg = riscv_reg :: RISCV_REG_X21 ; } impl riscv_reg { pub const RISCV_REG_S6 : riscv_reg = riscv_reg :: RISCV_REG_X22 ; } impl riscv_reg { pub const RISCV_REG_S7 : riscv_reg = riscv_reg :: RISCV_REG_X23 ; } impl riscv_reg { pub const RISCV_REG_S8 : riscv_reg = riscv_reg :: RISCV_REG_X24 ; } impl riscv_reg { pub const RISCV_REG_S9 : riscv_reg = riscv_reg :: RISCV_REG_X25 ; } impl riscv_reg { pub const RISCV_REG_S10 : riscv_reg = riscv_reg :: RISCV_REG_X26 ; } impl riscv_reg { pub const RISCV_REG_S11 : riscv_reg = riscv_reg :: RISCV_REG_X27 ; } impl riscv_reg { pub const RISCV_REG_T3 : riscv_reg = riscv_reg :: RISCV_REG_X28 ; } impl riscv_reg { pub const RISCV_REG_T4 : riscv_reg = riscv_reg :: RISCV_REG_X29 ; } impl riscv_reg { pub const RISCV_REG_T5 : riscv_reg = riscv_reg :: RISCV_REG_X30 ; } impl riscv_reg { pub const RISCV_REG_T6 : riscv_reg = riscv_reg :: RISCV_REG_X31 ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_reg { RISCV_REG_INVALID = 0 , RISCV_REG_X0 = 1 , RISCV_REG_X1 = 2 , RISCV_REG_X2 = 3 , RISCV_REG_X3 = 4 , RISCV_REG_X4 = 5 , RISCV_REG_X5 = 6 , RISCV_REG_X6 = 7 , RISCV_REG_X7 = 8 , RISCV_REG_X8 = 9 , RISCV_REG_X9 = 10 , RISCV_REG_X10 = 11 , RISCV_REG_X11 = 12 , RISCV_REG_X12 = 13 , RISCV_REG_X13 = 14 , RISCV_REG_X14 = 15 , RISCV_REG_X15 = 16 , RISCV_REG_X16 = 17 , RISCV_REG_X17 = 18 , RISCV_REG_X18 = 19 , RISCV_REG_X19 = 20 , RISCV_REG_X20 = 21 , RISCV_REG_X21 = 22 , RISCV_REG_X22 = 23 , RISCV_REG_X23 = 24 , RISCV_REG_X24 = 25 , RISCV_REG_X25 = 26 , RISCV_REG_X26 = 27 , RISCV_REG_X27 = 28 , RISCV_REG_X28 = 29 , RISCV_REG_X29 = 30 , RISCV_REG_X30 = 31 , RISCV_REG_X31 = 32 , RISCV_REG_F0_32 = 33 , RISCV_REG_F0_64 = 34 , RISCV_REG_F1_32 = 35 , RISCV_REG_F1_64 = 36 , RISCV_REG_F2_32 = 37 , RISCV_REG_F2_64 = 38 , RISCV_REG_F3_32 = 39 , RISCV_REG_F3_64 = 40 , RISCV_REG_F4_32 = 41 , RISCV_REG_F4_64 = 42 , RISCV_REG_F5_32 = 43 , RISCV_REG_F5_64 = 44 , RISCV_REG_F6_32 = 45 , RISCV_REG_F6_64 = 46 , RISCV_REG_F7_32 = 47 , RISCV_REG_F7_64 = 48 , RISCV_REG_F8_32 = 49 , RISCV_REG_F8_64 = 50 , RISCV_REG_F9_32 = 51 , RISCV_REG_F9_64 = 52 , RISCV_REG_F10_32 = 53 , RISCV_REG_F10_64 = 54 , RISCV_REG_F11_32 = 55 , RISCV_REG_F11_64 = 56 , RISCV_REG_F12_32 = 57 , RISCV_REG_F12_64 = 58 , RISCV_REG_F13_32 = 59 , RISCV_REG_F13_64 = 60 , RISCV_REG_F14_32 = 61 , RISCV_REG_F14_64 = 62 , RISCV_REG_F15_32 = 63 , RISCV_REG_F15_64 = 64 , RISCV_REG_F16_32 = 65 , RISCV_REG_F16_64 = 66 , RISCV_REG_F17_32 = 67 , RISCV_REG_F17_64 = 68 , RISCV_REG_F18_32 = 69 , RISCV_REG_F18_64 = 70 , RISCV_REG_F19_32 = 71 , RISCV_REG_F19_64 = 72 , RISCV_REG_F20_32 = 73 , RISCV_REG_F20_64 = 74 , RISCV_REG_F21_32 = 75 , RISCV_REG_F21_64 = 76 , RISCV_REG_F22_32 = 77 , RISCV_REG_F22_64 = 78 , RISCV_REG_F23_32 = 79 , RISCV_REG_F23_64 = 80 , RISCV_REG_F24_32 = 81 , RISCV_REG_F24_64 = 82 , RISCV_REG_F25_32 = 83 , RISCV_REG_F25_64 = 84 , RISCV_REG_F26_32 = 85 , RISCV_REG_F26_64 = 86 , RISCV_REG_F27_32 = 87 , RISCV_REG_F27_64 = 88 , RISCV_REG_F28_32 = 89 , RISCV_REG_F28_64 = 90 , RISCV_REG_F29_32 = 91 , RISCV_REG_F29_64 = 92 , RISCV_REG_F30_32 = 93 , RISCV_REG_F30_64 = 94 , RISCV_REG_F31_32 = 95 , RISCV_REG_F31_64 = 96 , RISCV_REG_ENDING = 97 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn { RISCV_INS_INVALID = 0 , RISCV_INS_ADD = 1 , RISCV_INS_ADDI = 2 , RISCV_INS_ADDIW = 3 , RISCV_INS_ADDW = 4 , RISCV_INS_AMOADD_D = 5 , RISCV_INS_AMOADD_D_AQ = 6 , RISCV_INS_AMOADD_D_AQ_RL = 7 , RISCV_INS_AMOADD_D_RL = 8 , RISCV_INS_AMOADD_W = 9 , RISCV_INS_AMOADD_W_AQ = 10 , RISCV_INS_AMOADD_W_AQ_RL = 11 , RISCV_INS_AMOADD_W_RL = 12 , RISCV_INS_AMOAND_D = 13 , RISCV_INS_AMOAND_D_AQ = 14 , RISCV_INS_AMOAND_D_AQ_RL = 15 , RISCV_INS_AMOAND_D_RL = 16 , RISCV_INS_AMOAND_W = 17 , RISCV_INS_AMOAND_W_AQ = 18 , RISCV_INS_AMOAND_W_AQ_RL = 19 , RISCV_INS_AMOAND_W_RL = 20 , RISCV_INS_AMOMAXU_D = 21 , RISCV_INS_AMOMAXU_D_AQ = 22 , RISCV_INS_AMOMAXU_D_AQ_RL = 23 , RISCV_INS_AMOMAXU_D_RL = 24 , RISCV_INS_AMOMAXU_W = 25 , RISCV_INS_AMOMAXU_W_AQ = 26 , RISCV_INS_AMOMAXU_W_AQ_RL = 27 , RISCV_INS_AMOMAXU_W_RL = 28 , RISCV_INS_AMOMAX_D = 29 , RISCV_INS_AMOMAX_D_AQ = 30 , RISCV_INS_AMOMAX_D_AQ_RL = 31 , RISCV_INS_AMOMAX_D_RL = 32 , RISCV_INS_AMOMAX_W = 33 , RISCV_INS_AMOMAX_W_AQ = 34 , RISCV_INS_AMOMAX_W_AQ_RL = 35 , RISCV_INS_AMOMAX_W_RL = 36 , RISCV_INS_AMOMINU_D = 37 , RISCV_INS_AMOMINU_D_AQ = 38 , RISCV_INS_AMOMINU_D_AQ_RL = 39 , RISCV_INS_AMOMINU_D_RL = 40 , RISCV_INS_AMOMINU_W = 41 , RISCV_INS_AMOMINU_W_AQ = 42 , RISCV_INS_AMOMINU_W_AQ_RL = 43 , RISCV_INS_AMOMINU_W_RL = 44 , RISCV_INS_AMOMIN_D = 45 , RISCV_INS_AMOMIN_D_AQ = 46 , RISCV_INS_AMOMIN_D_AQ_RL = 47 , RISCV_INS_AMOMIN_D_RL = 48 , RISCV_INS_AMOMIN_W = 49 , RISCV_INS_AMOMIN_W_AQ = 50 , RISCV_INS_AMOMIN_W_AQ_RL = 51 , RISCV_INS_AMOMIN_W_RL = 52 , RISCV_INS_AMOOR_D = 53 , RISCV_INS_AMOOR_D_AQ = 54 , RISCV_INS_AMOOR_D_AQ_RL = 55 , RISCV_INS_AMOOR_D_RL = 56 , RISCV_INS_AMOOR_W = 57 , RISCV_INS_AMOOR_W_AQ = 58 , RISCV_INS_AMOOR_W_AQ_RL = 59 , RISCV_INS_AMOOR_W_RL = 60 , RISCV_INS_AMOSWAP_D = 61 , RISCV_INS_AMOSWAP_D_AQ = 62 , RISCV_INS_AMOSWAP_D_AQ_RL = 63 , RISCV_INS_AMOSWAP_D_RL = 64 , RISCV_INS_AMOSWAP_W = 65 , RISCV_INS_AMOSWAP_W_AQ = 66 , RISCV_INS_AMOSWAP_W_AQ_RL = 67 , RISCV_INS_AMOSWAP_W_RL = 68 , RISCV_INS_AMOXOR_D = 69 , RISCV_INS_AMOXOR_D_AQ = 70 , RISCV_INS_AMOXOR_D_AQ_RL = 71 , RISCV_INS_AMOXOR_D_RL = 72 , RISCV_INS_AMOXOR_W = 73 , RISCV_INS_AMOXOR_W_AQ = 74 , RISCV_INS_AMOXOR_W_AQ_RL = 75 , RISCV_INS_AMOXOR_W_RL = 76 , RISCV_INS_AND = 77 , RISCV_INS_ANDI = 78 , RISCV_INS_AUIPC = 79 , RISCV_INS_BEQ = 80 , RISCV_INS_BGE = 81 , RISCV_INS_BGEU = 82 , RISCV_INS_BLT = 83 , RISCV_INS_BLTU = 84 , RISCV_INS_BNE = 85 , RISCV_INS_CSRRC = 86 , RISCV_INS_CSRRCI = 87 , RISCV_INS_CSRRS = 88 , RISCV_INS_CSRRSI = 89 , RISCV_INS_CSRRW = 90 , RISCV_INS_CSRRWI = 91 , RISCV_INS_C_ADD = 92 , RISCV_INS_C_ADDI = 93 , RISCV_INS_C_ADDI16SP = 94 , RISCV_INS_C_ADDI4SPN = 95 , RISCV_INS_C_ADDIW = 96 , RISCV_INS_C_ADDW = 97 , RISCV_INS_C_AND = 98 , RISCV_INS_C_ANDI = 99 , RISCV_INS_C_BEQZ = 100 , RISCV_INS_C_BNEZ = 101 , RISCV_INS_C_EBREAK = 102 , RISCV_INS_C_FLD = 103 , RISCV_INS_C_FLDSP = 104 , RISCV_INS_C_FLW = 105 , RISCV_INS_C_FLWSP = 106 , RISCV_INS_C_FSD = 107 , RISCV_INS_C_FSDSP = 108 , RISCV_INS_C_FSW = 109 , RISCV_INS_C_FSWSP = 110 , RISCV_INS_C_J = 111 , RISCV_INS_C_JAL = 112 , RISCV_INS_C_JALR = 113 , RISCV_INS_C_JR = 114 , RISCV_INS_C_LD = 115 , RISCV_INS_C_LDSP = 116 , RISCV_INS_C_LI = 117 , RISCV_INS_C_LUI = 118 , RISCV_INS_C_LW = 119 , RISCV_INS_C_LWSP = 120 , RISCV_INS_C_MV = 121 , RISCV_INS_C_NOP = 122 , RISCV_INS_C_OR = 123 , RISCV_INS_C_SD = 124 , RISCV_INS_C_SDSP = 125 , RISCV_INS_C_SLLI = 126 , RISCV_INS_C_SRAI = 127 , RISCV_INS_C_SRLI = 128 , RISCV_INS_C_SUB = 129 , RISCV_INS_C_SUBW = 130 , RISCV_INS_C_SW = 131 , RISCV_INS_C_SWSP = 132 , RISCV_INS_C_UNIMP = 133 , RISCV_INS_C_XOR = 134 , RISCV_INS_DIV = 135 , RISCV_INS_DIVU = 136 , RISCV_INS_DIVUW = 137 , RISCV_INS_DIVW = 138 , RISCV_INS_EBREAK = 139 , RISCV_INS_ECALL = 140 , RISCV_INS_FADD_D = 141 , RISCV_INS_FADD_S = 142 , RISCV_INS_FCLASS_D = 143 , RISCV_INS_FCLASS_S = 144 , RISCV_INS_FCVT_D_L = 145 , RISCV_INS_FCVT_D_LU = 146 , RISCV_INS_FCVT_D_S = 147 , RISCV_INS_FCVT_D_W = 148 , RISCV_INS_FCVT_D_WU = 149 , RISCV_INS_FCVT_LU_D = 150 , RISCV_INS_FCVT_LU_S = 151 , RISCV_INS_FCVT_L_D = 152 , RISCV_INS_FCVT_L_S = 153 , RISCV_INS_FCVT_S_D = 154 , RISCV_INS_FCVT_S_L = 155 , RISCV_INS_FCVT_S_LU = 156 , RISCV_INS_FCVT_S_W = 157 , RISCV_INS_FCVT_S_WU = 158 , RISCV_INS_FCVT_WU_D = 159 , RISCV_INS_FCVT_WU_S = 160 , RISCV_INS_FCVT_W_D = 161 , RISCV_INS_FCVT_W_S = 162 , RISCV_INS_FDIV_D = 163 , RISCV_INS_FDIV_S = 164 , RISCV_INS_FENCE = 165 , RISCV_INS_FENCE_I = 166 , RISCV_INS_FENCE_TSO = 167 , RISCV_INS_FEQ_D = 168 , RISCV_INS_FEQ_S = 169 , RISCV_INS_FLD = 170 , RISCV_INS_FLE_D = 171 , RISCV_INS_FLE_S = 172 , RISCV_INS_FLT_D = 173 , RISCV_INS_FLT_S = 174 , RISCV_INS_FLW = 175 , RISCV_INS_FMADD_D = 176 , RISCV_INS_FMADD_S = 177 , RISCV_INS_FMAX_D = 178 , RISCV_INS_FMAX_S = 179 , RISCV_INS_FMIN_D = 180 , RISCV_INS_FMIN_S = 181 , RISCV_INS_FMSUB_D = 182 , RISCV_INS_FMSUB_S = 183 , RISCV_INS_FMUL_D = 184 , RISCV_INS_FMUL_S = 185 , RISCV_INS_FMV_D_X = 186 , RISCV_INS_FMV_W_X = 187 , RISCV_INS_FMV_X_D = 188 , RISCV_INS_FMV_X_W = 189 , RISCV_INS_FNMADD_D = 190 , RISCV_INS_FNMADD_S = 191 , RISCV_INS_FNMSUB_D = 192 , RISCV_INS_FNMSUB_S = 193 , RISCV_INS_FSD = 194 , RISCV_INS_FSGNJN_D = 195 , RISCV_INS_FSGNJN_S = 196 , RISCV_INS_FSGNJX_D = 197 , RISCV_INS_FSGNJX_S = 198 , RISCV_INS_FSGNJ_D = 199 , RISCV_INS_FSGNJ_S = 200 , RISCV_INS_FSQRT_D = 201 , RISCV_INS_FSQRT_S = 202 , RISCV_INS_FSUB_D = 203 , RISCV_INS_FSUB_S = 204 , RISCV_INS_FSW = 205 , RISCV_INS_JAL = 206 , RISCV_INS_JALR = 207 , RISCV_INS_LB = 208 , RISCV_INS_LBU = 209 , RISCV_INS_LD = 210 , RISCV_INS_LH = 211 , RISCV_INS_LHU = 212 , RISCV_INS_LR_D = 213 , RISCV_INS_LR_D_AQ = 214 , RISCV_INS_LR_D_AQ_RL = 215 , RISCV_INS_LR_D_RL = 216 , RISCV_INS_LR_W = 217 , RISCV_INS_LR_W_AQ = 218 , RISCV_INS_LR_W_AQ_RL = 219 , RISCV_INS_LR_W_RL = 220 , RISCV_INS_LUI = 221 , RISCV_INS_LW = 222 , RISCV_INS_LWU = 223 , RISCV_INS_MRET = 224 , RISCV_INS_MUL = 225 , RISCV_INS_MULH = 226 , RISCV_INS_MULHSU = 227 , RISCV_INS_MULHU = 228 , RISCV_INS_MULW = 229 , RISCV_INS_OR = 230 , RISCV_INS_ORI = 231 , RISCV_INS_REM = 232 , RISCV_INS_REMU = 233 , RISCV_INS_REMUW = 234 , RISCV_INS_REMW = 235 , RISCV_INS_SB = 236 , RISCV_INS_SC_D = 237 , RISCV_INS_SC_D_AQ = 238 , RISCV_INS_SC_D_AQ_RL = 239 , RISCV_INS_SC_D_RL = 240 , RISCV_INS_SC_W = 241 , RISCV_INS_SC_W_AQ = 242 , RISCV_INS_SC_W_AQ_RL = 243 , RISCV_INS_SC_W_RL = 244 , RISCV_INS_SD = 245 , RISCV_INS_SFENCE_VMA = 246 , RISCV_INS_SH = 247 , RISCV_INS_SLL = 248 , RISCV_INS_SLLI = 249 , RISCV_INS_SLLIW = 250 , RISCV_INS_SLLW = 251 , RISCV_INS_SLT = 252 , RISCV_INS_SLTI = 253 , RISCV_INS_SLTIU = 254 , RISCV_INS_SLTU = 255 , RISCV_INS_SRA = 256 , RISCV_INS_SRAI = 257 , RISCV_INS_SRAIW = 258 , RISCV_INS_SRAW = 259 , RISCV_INS_SRET = 260 , RISCV_INS_SRL = 261 , RISCV_INS_SRLI = 262 , RISCV_INS_SRLIW = 263 , RISCV_INS_SRLW = 264 , RISCV_INS_SUB = 265 , RISCV_INS_SUBW = 266 , RISCV_INS_SW = 267 , RISCV_INS_UNIMP = 268 , RISCV_INS_URET = 269 , RISCV_INS_WFI = 270 , RISCV_INS_XOR = 271 , RISCV_INS_XORI = 272 , RISCV_INS_ENDING = 273 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn_group { # [doc = "< = CS_GRP_INVALID"] RISCV_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] RISCV_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] RISCV_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] RISCV_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] RISCV_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] RISCV_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] RISCV_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] RISCV_GRP_BRANCH_RELATIVE = 7 , RISCV_GRP_ISRV32 = 128 , RISCV_GRP_ISRV64 = 129 , RISCV_GRP_HASSTDEXTA = 130 , RISCV_GRP_HASSTDEXTC = 131 , RISCV_GRP_HASSTDEXTD = 132 , RISCV_GRP_HASSTDEXTF = 133 , RISCV_GRP_HASSTDEXTM = 134 , RISCV_GRP_ENDING = 135 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_op_type { WASM_OP_INVALID = 0 , WASM_OP_NONE = 1 , WASM_OP_INT7 = 2 , WASM_OP_VARUINT32 = 3 , WASM_OP_VARUINT64 = 4 , WASM_OP_UINT32 = 5 , WASM_OP_UINT64 = 6 , WASM_OP_IMM = 7 , WASM_OP_BRTABLE = 8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_wasm_brtable { pub length : u32 , pub address : u64 , pub default_target : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_brtable"] [:: std :: mem :: size_of :: < cs_wasm_brtable > () - 24usize] ; ["Alignment of cs_wasm_brtable"] [:: std :: mem :: align_of :: < cs_wasm_brtable > () - 8usize] ; ["Offset of field: cs_wasm_brtable::length"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , length) - 0usize] ; ["Offset of field: cs_wasm_brtable::address"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , address) - 8usize] ; ["Offset of field: cs_wasm_brtable::default_target"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , default_target) - 16usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm_op { pub type_ : wasm_op_type , pub size : u32 , pub __bindgen_anon_1 : cs_wasm_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_wasm_op__bindgen_ty_1 { pub int7 : i8 , pub varuint32 : u32 , pub varuint64 : u64 , pub uint32 : u32 , pub uint64 : u64 , pub immediate : [u32 ; 2usize] , pub brtable : cs_wasm_brtable , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_wasm_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_wasm_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::int7"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , int7) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::immediate"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , immediate) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::brtable"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , brtable) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op"] [:: std :: mem :: size_of :: < cs_wasm_op > () - 32usize] ; ["Alignment of cs_wasm_op"] [:: std :: mem :: align_of :: < cs_wasm_op > () - 8usize] ; ["Offset of field: cs_wasm_op::type_"] [:: std :: mem :: offset_of ! (cs_wasm_op , type_) - 0usize] ; ["Offset of field: cs_wasm_op::size"] [:: std :: mem :: offset_of ! (cs_wasm_op , size) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . size , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm { pub op_count : u8 , pub operands : [cs_wasm_op ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm"] [:: std :: mem :: size_of :: < cs_wasm > () - 72usize] ; ["Alignment of cs_wasm"] [:: std :: mem :: align_of :: < cs_wasm > () - 8usize] ; ["Offset of field: cs_wasm::op_count"] [:: std :: mem :: offset_of ! (cs_wasm , op_count) - 0usize] ; ["Offset of field: cs_wasm::operands"] [:: std :: mem :: offset_of ! (cs_wasm , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " WASM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn { WASM_INS_UNREACHABLE = 0 , WASM_INS_NOP = 1 , WASM_INS_BLOCK = 2 , WASM_INS_LOOP = 3 , WASM_INS_IF = 4 , WASM_INS_ELSE = 5 , WASM_INS_END = 11 , WASM_INS_BR = 12 , WASM_INS_BR_IF = 13 , WASM_INS_BR_TABLE = 14 , WASM_INS_RETURN = 15 , WASM_INS_CALL = 16 , WASM_INS_CALL_INDIRECT = 17 , WASM_INS_DROP = 26 , WASM_INS_SELECT = 27 , WASM_INS_GET_LOCAL = 32 , WASM_INS_SET_LOCAL = 33 , WASM_INS_TEE_LOCAL = 34 , WASM_INS_GET_GLOBAL = 35 , WASM_INS_SET_GLOBAL = 36 , WASM_INS_I32_LOAD = 40 , WASM_INS_I64_LOAD = 41 , WASM_INS_F32_LOAD = 42 , WASM_INS_F64_LOAD = 43 , WASM_INS_I32_LOAD8_S = 44 , WASM_INS_I32_LOAD8_U = 45 , WASM_INS_I32_LOAD16_S = 46 , WASM_INS_I32_LOAD16_U = 47 , WASM_INS_I64_LOAD8_S = 48 , WASM_INS_I64_LOAD8_U = 49 , WASM_INS_I64_LOAD16_S = 50 , WASM_INS_I64_LOAD16_U = 51 , WASM_INS_I64_LOAD32_S = 52 , WASM_INS_I64_LOAD32_U = 53 , WASM_INS_I32_STORE = 54 , WASM_INS_I64_STORE = 55 , WASM_INS_F32_STORE = 56 , WASM_INS_F64_STORE = 57 , WASM_INS_I32_STORE8 = 58 , WASM_INS_I32_STORE16 = 59 , WASM_INS_I64_STORE8 = 60 , WASM_INS_I64_STORE16 = 61 , WASM_INS_I64_STORE32 = 62 , WASM_INS_CURRENT_MEMORY = 63 , WASM_INS_GROW_MEMORY = 64 , WASM_INS_I32_CONST = 65 , WASM_INS_I64_CONST = 66 , WASM_INS_F32_CONST = 67 , WASM_INS_F64_CONST = 68 , WASM_INS_I32_EQZ = 69 , WASM_INS_I32_EQ = 70 , WASM_INS_I32_NE = 71 , WASM_INS_I32_LT_S = 72 , WASM_INS_I32_LT_U = 73 , WASM_INS_I32_GT_S = 74 , WASM_INS_I32_GT_U = 75 , WASM_INS_I32_LE_S = 76 , WASM_INS_I32_LE_U = 77 , WASM_INS_I32_GE_S = 78 , WASM_INS_I32_GE_U = 79 , WASM_INS_I64_EQZ = 80 , WASM_INS_I64_EQ = 81 , WASM_INS_I64_NE = 82 , WASM_INS_I64_LT_S = 83 , WASM_INS_I64_LT_U = 84 , WASN_INS_I64_GT_S = 85 , WASM_INS_I64_GT_U = 86 , WASM_INS_I64_LE_S = 87 , WASM_INS_I64_LE_U = 88 , WASM_INS_I64_GE_S = 89 , WASM_INS_I64_GE_U = 90 , WASM_INS_F32_EQ = 91 , WASM_INS_F32_NE = 92 , WASM_INS_F32_LT = 93 , WASM_INS_F32_GT = 94 , WASM_INS_F32_LE = 95 , WASM_INS_F32_GE = 96 , WASM_INS_F64_EQ = 97 , WASM_INS_F64_NE = 98 , WASM_INS_F64_LT = 99 , WASM_INS_F64_GT = 100 , WASM_INS_F64_LE = 101 , WASM_INS_F64_GE = 102 , WASM_INS_I32_CLZ = 103 , WASM_INS_I32_CTZ = 104 , WASM_INS_I32_POPCNT = 105 , WASM_INS_I32_ADD = 106 , WASM_INS_I32_SUB = 107 , WASM_INS_I32_MUL = 108 , WASM_INS_I32_DIV_S = 109 , WASM_INS_I32_DIV_U = 110 , WASM_INS_I32_REM_S = 111 , WASM_INS_I32_REM_U = 112 , WASM_INS_I32_AND = 113 , WASM_INS_I32_OR = 114 , WASM_INS_I32_XOR = 115 , WASM_INS_I32_SHL = 116 , WASM_INS_I32_SHR_S = 117 , WASM_INS_I32_SHR_U = 118 , WASM_INS_I32_ROTL = 119 , WASM_INS_I32_ROTR = 120 , WASM_INS_I64_CLZ = 121 , WASM_INS_I64_CTZ = 122 , WASM_INS_I64_POPCNT = 123 , WASM_INS_I64_ADD = 124 , WASM_INS_I64_SUB = 125 , WASM_INS_I64_MUL = 126 , WASM_INS_I64_DIV_S = 127 , WASM_INS_I64_DIV_U = 128 , WASM_INS_I64_REM_S = 129 , WASM_INS_I64_REM_U = 130 , WASM_INS_I64_AND = 131 , WASM_INS_I64_OR = 132 , WASM_INS_I64_XOR = 133 , WASM_INS_I64_SHL = 134 , WASM_INS_I64_SHR_S = 135 , WASM_INS_I64_SHR_U = 136 , WASM_INS_I64_ROTL = 137 , WASM_INS_I64_ROTR = 138 , WASM_INS_F32_ABS = 139 , WASM_INS_F32_NEG = 140 , WASM_INS_F32_CEIL = 141 , WASM_INS_F32_FLOOR = 142 , WASM_INS_F32_TRUNC = 143 , WASM_INS_F32_NEAREST = 144 , WASM_INS_F32_SQRT = 145 , WASM_INS_F32_ADD = 146 , WASM_INS_F32_SUB = 147 , WASM_INS_F32_MUL = 148 , WASM_INS_F32_DIV = 149 , WASM_INS_F32_MIN = 150 , WASM_INS_F32_MAX = 151 , WASM_INS_F32_COPYSIGN = 152 , WASM_INS_F64_ABS = 153 , WASM_INS_F64_NEG = 154 , WASM_INS_F64_CEIL = 155 , WASM_INS_F64_FLOOR = 156 , WASM_INS_F64_TRUNC = 157 , WASM_INS_F64_NEAREST = 158 , WASM_INS_F64_SQRT = 159 , WASM_INS_F64_ADD = 160 , WASM_INS_F64_SUB = 161 , WASM_INS_F64_MUL = 162 , WASM_INS_F64_DIV = 163 , WASM_INS_F64_MIN = 164 , WASM_INS_F64_MAX = 165 , WASM_INS_F64_COPYSIGN = 166 , WASM_INS_I32_WARP_I64 = 167 , WASP_INS_I32_TRUNC_S_F32 = 168 , WASM_INS_I32_TRUNC_U_F32 = 169 , WASM_INS_I32_TRUNC_S_F64 = 170 , WASM_INS_I32_TRUNC_U_F64 = 171 , WASM_INS_I64_EXTEND_S_I32 = 172 , WASM_INS_I64_EXTEND_U_I32 = 173 , WASM_INS_I64_TRUNC_S_F32 = 174 , WASM_INS_I64_TRUNC_U_F32 = 175 , WASM_INS_I64_TRUNC_S_F64 = 176 , WASM_INS_I64_TRUNC_U_F64 = 177 , WASM_INS_F32_CONVERT_S_I32 = 178 , WASM_INS_F32_CONVERT_U_I32 = 179 , WASM_INS_F32_CONVERT_S_I64 = 180 , WASM_INS_F32_CONVERT_U_I64 = 181 , WASM_INS_F32_DEMOTE_F64 = 182 , WASM_INS_F64_CONVERT_S_I32 = 183 , WASM_INS_F64_CONVERT_U_I32 = 184 , WASM_INS_F64_CONVERT_S_I64 = 185 , WASM_INS_F64_CONVERT_U_I64 = 186 , WASM_INS_F64_PROMOTE_F32 = 187 , WASM_INS_I32_REINTERPRET_F32 = 188 , WASM_INS_I64_REINTERPRET_F64 = 189 , WASM_INS_F32_REINTERPRET_I32 = 190 , WASM_INS_F64_REINTERPRET_I64 = 191 , WASM_INS_INVALID = 512 , WASM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of WASM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn_group { # [doc = "< = CS_GRP_INVALID"] WASM_GRP_INVALID = 0 , WASM_GRP_NUMBERIC = 8 , WASM_GRP_PARAMETRIC = 9 , WASM_GRP_VARIABLE = 10 , WASM_GRP_MEMORY = 11 , WASM_GRP_CONTROL = 12 , # [doc = "< <-- mark the end of the list of groups"] WASM_GRP_ENDING = 13 , } # [repr (u32)] # [doc = " MOS65XX registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_reg { MOS65XX_REG_INVALID = 0 , # [doc = "< accumulator"] MOS65XX_REG_ACC = 1 , # [doc = "< X index register"] MOS65XX_REG_X = 2 , # [doc = "< Y index register"] MOS65XX_REG_Y = 3 , # [doc = "< status register"] MOS65XX_REG_P = 4 , # [doc = "< stack pointer register"] MOS65XX_REG_SP = 5 , # [doc = "< direct page register"] MOS65XX_REG_DP = 6 , # [doc = "< data bank register"] MOS65XX_REG_B = 7 , # [doc = "< program bank register"] MOS65XX_REG_K = 8 , MOS65XX_REG_ENDING = 9 , } # [repr (u32)] # [doc = " MOS65XX Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_address_mode { # [doc = "< No address mode."] MOS65XX_AM_NONE = 0 , # [doc = "< implied addressing (no addressing mode)"] MOS65XX_AM_IMP = 1 , # [doc = "< accumulator addressing"] MOS65XX_AM_ACC = 2 , # [doc = "< 8/16 Bit immediate value"] MOS65XX_AM_IMM = 3 , # [doc = "< relative addressing used by branches"] MOS65XX_AM_REL = 4 , # [doc = "< interrupt addressing"] MOS65XX_AM_INT = 5 , # [doc = "< memory block addressing"] MOS65XX_AM_BLOCK = 6 , # [doc = "< zeropage addressing"] MOS65XX_AM_ZP = 7 , # [doc = "< indexed zeropage addressing by the X index register"] MOS65XX_AM_ZP_X = 8 , # [doc = "< indexed zeropage addressing by the Y index register"] MOS65XX_AM_ZP_Y = 9 , # [doc = "< zero page address, branch relative address"] MOS65XX_AM_ZP_REL = 10 , # [doc = "< indirect zeropage addressing"] MOS65XX_AM_ZP_IND = 11 , # [doc = "< indexed zeropage indirect addressing by the X index register"] MOS65XX_AM_ZP_X_IND = 12 , # [doc = "< indirect zeropage indexed addressing by the Y index register"] MOS65XX_AM_ZP_IND_Y = 13 , # [doc = "< zeropage indirect long addressing"] MOS65XX_AM_ZP_IND_LONG = 14 , # [doc = "< zeropage indirect long addressing indexed by Y register"] MOS65XX_AM_ZP_IND_LONG_Y = 15 , # [doc = "< absolute addressing"] MOS65XX_AM_ABS = 16 , # [doc = "< indexed absolute addressing by the X index register"] MOS65XX_AM_ABS_X = 17 , # [doc = "< indexed absolute addressing by the Y index register"] MOS65XX_AM_ABS_Y = 18 , # [doc = "< absolute indirect addressing"] MOS65XX_AM_ABS_IND = 19 , # [doc = "< indexed absolute indirect addressing by the X index register"] MOS65XX_AM_ABS_X_IND = 20 , # [doc = "< absolute indirect long addressing"] MOS65XX_AM_ABS_IND_LONG = 21 , # [doc = "< absolute long address mode"] MOS65XX_AM_ABS_LONG = 22 , # [doc = "< absolute long address mode, indexed by X register"] MOS65XX_AM_ABS_LONG_X = 23 , # [doc = "< stack relative addressing"] MOS65XX_AM_SR = 24 , # [doc = "< indirect stack relative addressing indexed by the Y index register"] MOS65XX_AM_SR_IND_Y = 25 , } # [repr (u32)] # [doc = " MOS65XX instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_insn { MOS65XX_INS_INVALID = 0 , MOS65XX_INS_ADC = 1 , MOS65XX_INS_AND = 2 , MOS65XX_INS_ASL = 3 , MOS65XX_INS_BBR = 4 , MOS65XX_INS_BBS = 5 , MOS65XX_INS_BCC = 6 , MOS65XX_INS_BCS = 7 , MOS65XX_INS_BEQ = 8 , MOS65XX_INS_BIT = 9 , MOS65XX_INS_BMI = 10 , MOS65XX_INS_BNE = 11 , MOS65XX_INS_BPL = 12 , MOS65XX_INS_BRA = 13 , MOS65XX_INS_BRK = 14 , MOS65XX_INS_BRL = 15 , MOS65XX_INS_BVC = 16 , MOS65XX_INS_BVS = 17 , MOS65XX_INS_CLC = 18 , MOS65XX_INS_CLD = 19 , MOS65XX_INS_CLI = 20 , MOS65XX_INS_CLV = 21 , MOS65XX_INS_CMP = 22 , MOS65XX_INS_COP = 23 , MOS65XX_INS_CPX = 24 , MOS65XX_INS_CPY = 25 , MOS65XX_INS_DEC = 26 , MOS65XX_INS_DEX = 27 , MOS65XX_INS_DEY = 28 , MOS65XX_INS_EOR = 29 , MOS65XX_INS_INC = 30 , MOS65XX_INS_INX = 31 , MOS65XX_INS_INY = 32 , MOS65XX_INS_JML = 33 , MOS65XX_INS_JMP = 34 , MOS65XX_INS_JSL = 35 , MOS65XX_INS_JSR = 36 , MOS65XX_INS_LDA = 37 , MOS65XX_INS_LDX = 38 , MOS65XX_INS_LDY = 39 , MOS65XX_INS_LSR = 40 , MOS65XX_INS_MVN = 41 , MOS65XX_INS_MVP = 42 , MOS65XX_INS_NOP = 43 , MOS65XX_INS_ORA = 44 , MOS65XX_INS_PEA = 45 , MOS65XX_INS_PEI = 46 , MOS65XX_INS_PER = 47 , MOS65XX_INS_PHA = 48 , MOS65XX_INS_PHB = 49 , MOS65XX_INS_PHD = 50 , MOS65XX_INS_PHK = 51 , MOS65XX_INS_PHP = 52 , MOS65XX_INS_PHX = 53 , MOS65XX_INS_PHY = 54 , MOS65XX_INS_PLA = 55 , MOS65XX_INS_PLB = 56 , MOS65XX_INS_PLD = 57 , MOS65XX_INS_PLP = 58 , MOS65XX_INS_PLX = 59 , MOS65XX_INS_PLY = 60 , MOS65XX_INS_REP = 61 , MOS65XX_INS_RMB = 62 , MOS65XX_INS_ROL = 63 , MOS65XX_INS_ROR = 64 , MOS65XX_INS_RTI = 65 , MOS65XX_INS_RTL = 66 , MOS65XX_INS_RTS = 67 , MOS65XX_INS_SBC = 68 , MOS65XX_INS_SEC = 69 , MOS65XX_INS_SED = 70 , MOS65XX_INS_SEI = 71 , MOS65XX_INS_SEP = 72 , MOS65XX_INS_SMB = 73 , MOS65XX_INS_STA = 74 , MOS65XX_INS_STP = 75 , MOS65XX_INS_STX = 76 , MOS65XX_INS_STY = 77 , MOS65XX_INS_STZ = 78 , MOS65XX_INS_TAX = 79 , MOS65XX_INS_TAY = 80 , MOS65XX_INS_TCD = 81 , MOS65XX_INS_TCS = 82 , MOS65XX_INS_TDC = 83 , MOS65XX_INS_TRB = 84 , MOS65XX_INS_TSB = 85 , MOS65XX_INS_TSC = 86 , MOS65XX_INS_TSX = 87 , MOS65XX_INS_TXA = 88 , MOS65XX_INS_TXS = 89 , MOS65XX_INS_TXY = 90 , MOS65XX_INS_TYA = 91 , MOS65XX_INS_TYX = 92 , MOS65XX_INS_WAI = 93 , MOS65XX_INS_WDM = 94 , MOS65XX_INS_XBA = 95 , MOS65XX_INS_XCE = 96 , MOS65XX_INS_ENDING = 97 , } # [repr (u32)] # [doc = " Group of MOS65XX instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_group_type { # [doc = "< CS_GRP_INVALID"] MOS65XX_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MOS65XX_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MOS65XX_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MOS65XX_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MOS65XX_GRP_BRANCH_RELATIVE = 6 , MOS65XX_GRP_ENDING = 7 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MOS65XX_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MOS65XX_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MOS65XX_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MOS65XX_OP_MEM = 3 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx_op { # [doc = "< operand type"] pub type_ : mos65xx_op_type , pub __bindgen_anon_1 : cs_mos65xx_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mos65xx_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : mos65xx_reg , # [doc = "< immediate value for IMM operand"] pub imm : u16 , # [doc = "< address for MEM operand"] pub mem : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Alignment of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op"] [:: std :: mem :: size_of :: < cs_mos65xx_op > () - 8usize] ; ["Alignment of cs_mos65xx_op"] [:: std :: mem :: align_of :: < cs_mos65xx_op > () - 4usize] ; ["Offset of field: cs_mos65xx_op::type_"] [:: std :: mem :: offset_of ! (cs_mos65xx_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The MOS65XX address mode and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx { pub am : mos65xx_address_mode , pub modifies_flags : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mos65xx_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx"] [:: std :: mem :: size_of :: < cs_mos65xx > () - 32usize] ; ["Alignment of cs_mos65xx"] [:: std :: mem :: align_of :: < cs_mos65xx > () - 4usize] ; ["Offset of field: cs_mos65xx::am"] [:: std :: mem :: offset_of ! (cs_mos65xx , am) - 0usize] ; ["Offset of field: cs_mos65xx::modifies_flags"] [:: std :: mem :: offset_of ! (cs_mos65xx , modifies_flags) - 4usize] ; ["Offset of field: cs_mos65xx::op_count"] [:: std :: mem :: offset_of ! (cs_mos65xx , op_count) - 5usize] ; ["Offset of field: cs_mos65xx::operands"] [:: std :: mem :: offset_of ! (cs_mos65xx , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . am , self . modifies_flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_op_type { BPF_OP_INVALID = 0 , BPF_OP_REG = 1 , BPF_OP_IMM = 2 , BPF_OP_OFF = 3 , BPF_OP_MEM = 4 , # [doc = "< M[k] in cBPF"] BPF_OP_MMEM = 5 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] BPF_OP_MSH = 6 , # [doc = "< cBPF's extension (not eBPF)"] BPF_OP_EXT = 7 , } # [repr (u32)] # [doc = " BPF registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_reg { BPF_REG_INVALID = 0 , BPF_REG_A = 1 , BPF_REG_X = 2 , BPF_REG_R0 = 3 , BPF_REG_R1 = 4 , BPF_REG_R2 = 5 , BPF_REG_R3 = 6 , BPF_REG_R4 = 7 , BPF_REG_R5 = 8 , BPF_REG_R6 = 9 , BPF_REG_R7 = 10 , BPF_REG_R8 = 11 , BPF_REG_R9 = 12 , BPF_REG_R10 = 13 , BPF_REG_ENDING = 14 , } # [doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct bpf_op_mem { # [doc = "< base register"] pub base : bpf_reg , # [doc = "< offset value"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of bpf_op_mem"] [:: std :: mem :: size_of :: < bpf_op_mem > () - 8usize] ; ["Alignment of bpf_op_mem"] [:: std :: mem :: align_of :: < bpf_op_mem > () - 4usize] ; ["Offset of field: bpf_op_mem::base"] [:: std :: mem :: offset_of ! (bpf_op_mem , base) - 0usize] ; ["Offset of field: bpf_op_mem::disp"] [:: std :: mem :: offset_of ! (bpf_op_mem , disp) - 4usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_ext_type { BPF_EXT_INVALID = 0 , BPF_EXT_LEN = 1 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf_op { pub type_ : bpf_op_type , pub __bindgen_anon_1 : cs_bpf_op__bindgen_ty_1 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_bpf_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : u8 , # [doc = "< immediate value IMM operand"] pub imm : u64 , # [doc = "< offset value, used in jump & call"] pub off : u32 , # [doc = "< base/disp value for MEM operand"] pub mem : bpf_op_mem , # [doc = "< M[k] in cBPF"] pub mmem : u32 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] pub msh : u32 , # [doc = "< cBPF's extension (not eBPF)"] pub ext : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::off"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , off) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mmem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mmem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::msh"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , msh) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , ext) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op"] [:: std :: mem :: size_of :: < cs_bpf_op > () - 24usize] ; ["Alignment of cs_bpf_op"] [:: std :: mem :: align_of :: < cs_bpf_op > () - 8usize] ; ["Offset of field: cs_bpf_op::type_"] [:: std :: mem :: offset_of ! (cs_bpf_op , type_) - 0usize] ; ["Offset of field: cs_bpf_op::access"] [:: std :: mem :: offset_of ! (cs_bpf_op , access) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf { pub op_count : u8 , pub operands : [cs_bpf_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf"] [:: std :: mem :: size_of :: < cs_bpf > () - 104usize] ; ["Alignment of cs_bpf"] [:: std :: mem :: align_of :: < cs_bpf > () - 8usize] ; ["Offset of field: cs_bpf::op_count"] [:: std :: mem :: offset_of ! (cs_bpf , op_count) - 0usize] ; ["Offset of field: cs_bpf::operands"] [:: std :: mem :: offset_of ! (cs_bpf , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } impl bpf_insn { pub const BPF_INS_LD : bpf_insn = bpf_insn :: BPF_INS_LDW ; } impl bpf_insn { pub const BPF_INS_LDX : bpf_insn = bpf_insn :: BPF_INS_LDXW ; } impl bpf_insn { pub const BPF_INS_ST : bpf_insn = bpf_insn :: BPF_INS_STW ; } impl bpf_insn { pub const BPF_INS_STX : bpf_insn = bpf_insn :: BPF_INS_STXW ; } # [repr (u32)] # [doc = " BPF instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn { BPF_INS_INVALID = 0 , BPF_INS_ADD = 1 , BPF_INS_SUB = 2 , BPF_INS_MUL = 3 , BPF_INS_DIV = 4 , BPF_INS_OR = 5 , BPF_INS_AND = 6 , BPF_INS_LSH = 7 , BPF_INS_RSH = 8 , BPF_INS_NEG = 9 , BPF_INS_MOD = 10 , BPF_INS_XOR = 11 , # [doc = "< eBPF only"] BPF_INS_MOV = 12 , # [doc = "< eBPF only"] BPF_INS_ARSH = 13 , BPF_INS_ADD64 = 14 , BPF_INS_SUB64 = 15 , BPF_INS_MUL64 = 16 , BPF_INS_DIV64 = 17 , BPF_INS_OR64 = 18 , BPF_INS_AND64 = 19 , BPF_INS_LSH64 = 20 , BPF_INS_RSH64 = 21 , BPF_INS_NEG64 = 22 , BPF_INS_MOD64 = 23 , BPF_INS_XOR64 = 24 , BPF_INS_MOV64 = 25 , BPF_INS_ARSH64 = 26 , BPF_INS_LE16 = 27 , BPF_INS_LE32 = 28 , BPF_INS_LE64 = 29 , BPF_INS_BE16 = 30 , BPF_INS_BE32 = 31 , BPF_INS_BE64 = 32 , # [doc = "< eBPF only"] BPF_INS_LDW = 33 , BPF_INS_LDH = 34 , BPF_INS_LDB = 35 , # [doc = "< eBPF only: load 64-bit imm"] BPF_INS_LDDW = 36 , # [doc = "< eBPF only"] BPF_INS_LDXW = 37 , # [doc = "< eBPF only"] BPF_INS_LDXH = 38 , # [doc = "< eBPF only"] BPF_INS_LDXB = 39 , # [doc = "< eBPF only"] BPF_INS_LDXDW = 40 , # [doc = "< eBPF only"] BPF_INS_STW = 41 , # [doc = "< eBPF only"] BPF_INS_STH = 42 , # [doc = "< eBPF only"] BPF_INS_STB = 43 , # [doc = "< eBPF only"] BPF_INS_STDW = 44 , # [doc = "< eBPF only"] BPF_INS_STXW = 45 , # [doc = "< eBPF only"] BPF_INS_STXH = 46 , # [doc = "< eBPF only"] BPF_INS_STXB = 47 , # [doc = "< eBPF only"] BPF_INS_STXDW = 48 , # [doc = "< eBPF only"] BPF_INS_XADDW = 49 , # [doc = "< eBPF only"] BPF_INS_XADDDW = 50 , BPF_INS_JMP = 51 , BPF_INS_JEQ = 52 , BPF_INS_JGT = 53 , BPF_INS_JGE = 54 , BPF_INS_JSET = 55 , # [doc = "< eBPF only"] BPF_INS_JNE = 56 , # [doc = "< eBPF only"] BPF_INS_JSGT = 57 , # [doc = "< eBPF only"] BPF_INS_JSGE = 58 , # [doc = "< eBPF only"] BPF_INS_CALL = 59 , # [doc = "< eBPF only"] BPF_INS_CALLX = 60 , # [doc = "< eBPF only"] BPF_INS_EXIT = 61 , # [doc = "< eBPF only"] BPF_INS_JLT = 62 , # [doc = "< eBPF only"] BPF_INS_JLE = 63 , # [doc = "< eBPF only"] BPF_INS_JSLT = 64 , # [doc = "< eBPF only"] BPF_INS_JSLE = 65 , BPF_INS_RET = 66 , BPF_INS_TAX = 67 , BPF_INS_TXA = 68 , BPF_INS_ENDING = 69 , } # [repr (u32)] # [doc = " Group of BPF instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn_group { # [doc = "< = CS_GRP_INVALID"] BPF_GRP_INVALID = 0 , BPF_GRP_LOAD = 1 , BPF_GRP_STORE = 2 , BPF_GRP_ALU = 3 , BPF_GRP_JUMP = 4 , # [doc = "< eBPF only"] BPF_GRP_CALL = 5 , BPF_GRP_RETURN = 6 , # [doc = "< cBPF only"] BPF_GRP_MISC = 7 , BPF_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " SH registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_reg { SH_REG_INVALID = 0 , SH_REG_R0 = 1 , SH_REG_R1 = 2 , SH_REG_R2 = 3 , SH_REG_R3 = 4 , SH_REG_R4 = 5 , SH_REG_R5 = 6 , SH_REG_R6 = 7 , SH_REG_R7 = 8 , SH_REG_R8 = 9 , SH_REG_R9 = 10 , SH_REG_R10 = 11 , SH_REG_R11 = 12 , SH_REG_R12 = 13 , SH_REG_R13 = 14 , SH_REG_R14 = 15 , SH_REG_R15 = 16 , SH_REG_R0_BANK = 17 , SH_REG_R1_BANK = 18 , SH_REG_R2_BANK = 19 , SH_REG_R3_BANK = 20 , SH_REG_R4_BANK = 21 , SH_REG_R5_BANK = 22 , SH_REG_R6_BANK = 23 , SH_REG_R7_BANK = 24 , SH_REG_FR0 = 25 , SH_REG_FR1 = 26 , SH_REG_FR2 = 27 , SH_REG_FR3 = 28 , SH_REG_FR4 = 29 , SH_REG_FR5 = 30 , SH_REG_FR6 = 31 , SH_REG_FR7 = 32 , SH_REG_FR8 = 33 , SH_REG_FR9 = 34 , SH_REG_FR10 = 35 , SH_REG_FR11 = 36 , SH_REG_FR12 = 37 , SH_REG_FR13 = 38 , SH_REG_FR14 = 39 , SH_REG_FR15 = 40 , SH_REG_DR0 = 41 , SH_REG_DR2 = 42 , SH_REG_DR4 = 43 , SH_REG_DR6 = 44 , SH_REG_DR8 = 45 , SH_REG_DR10 = 46 , SH_REG_DR12 = 47 , SH_REG_DR14 = 48 , SH_REG_XD0 = 49 , SH_REG_XD2 = 50 , SH_REG_XD4 = 51 , SH_REG_XD6 = 52 , SH_REG_XD8 = 53 , SH_REG_XD10 = 54 , SH_REG_XD12 = 55 , SH_REG_XD14 = 56 , SH_REG_XF0 = 57 , SH_REG_XF1 = 58 , SH_REG_XF2 = 59 , SH_REG_XF3 = 60 , SH_REG_XF4 = 61 , SH_REG_XF5 = 62 , SH_REG_XF6 = 63 , SH_REG_XF7 = 64 , SH_REG_XF8 = 65 , SH_REG_XF9 = 66 , SH_REG_XF10 = 67 , SH_REG_XF11 = 68 , SH_REG_XF12 = 69 , SH_REG_XF13 = 70 , SH_REG_XF14 = 71 , SH_REG_XF15 = 72 , SH_REG_FV0 = 73 , SH_REG_FV4 = 74 , SH_REG_FV8 = 75 , SH_REG_FV12 = 76 , SH_REG_XMATRX = 77 , SH_REG_PC = 78 , SH_REG_PR = 79 , SH_REG_MACH = 80 , SH_REG_MACL = 81 , SH_REG_SR = 82 , SH_REG_GBR = 83 , SH_REG_SSR = 84 , SH_REG_SPC = 85 , SH_REG_SGR = 86 , SH_REG_DBR = 87 , SH_REG_VBR = 88 , SH_REG_TBR = 89 , SH_REG_RS = 90 , SH_REG_RE = 91 , SH_REG_MOD = 92 , SH_REG_FPUL = 93 , SH_REG_FPSCR = 94 , SH_REG_DSP_X0 = 95 , SH_REG_DSP_X1 = 96 , SH_REG_DSP_Y0 = 97 , SH_REG_DSP_Y1 = 98 , SH_REG_DSP_A0 = 99 , SH_REG_DSP_A1 = 100 , SH_REG_DSP_A0G = 101 , SH_REG_DSP_A1G = 102 , SH_REG_DSP_M0 = 103 , SH_REG_DSP_M1 = 104 , SH_REG_DSP_DSR = 105 , SH_REG_DSP_RSV0 = 106 , SH_REG_DSP_RSV1 = 107 , SH_REG_DSP_RSV2 = 108 , SH_REG_DSP_RSV3 = 109 , SH_REG_DSP_RSV4 = 110 , SH_REG_DSP_RSV5 = 111 , SH_REG_DSP_RSV6 = 112 , SH_REG_DSP_RSV7 = 113 , SH_REG_DSP_RSV8 = 114 , SH_REG_DSP_RSV9 = 115 , SH_REG_DSP_RSVA = 116 , SH_REG_DSP_RSVB = 117 , SH_REG_DSP_RSVC = 118 , SH_REG_DSP_RSVD = 119 , SH_REG_DSP_RSVE = 120 , SH_REG_DSP_RSVF = 121 , SH_REG_ENDING = 122 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SH_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SH_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SH_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SH_OP_MEM = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_mem_type { SH_OP_MEM_INVALID = 0 , # [doc = " <= Invalid"] SH_OP_MEM_REG_IND = 1 , # [doc = " <= Register indirect"] SH_OP_MEM_REG_POST = 2 , # [doc = " <= Register post increment"] SH_OP_MEM_REG_PRE = 3 , # [doc = " <= Register pre decrement"] SH_OP_MEM_REG_DISP = 4 , # [doc = " <= displacement"] SH_OP_MEM_REG_R0 = 5 , # [doc = " <= R0 indexed"] SH_OP_MEM_GBR_DISP = 6 , # [doc = " <= GBR based displacement"] SH_OP_MEM_GBR_R0 = 7 , # [doc = " <= GBR based R0 indexed"] SH_OP_MEM_PCR = 8 , # [doc = " <= PC relative"] SH_OP_MEM_TBR_DISP = 9 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_mem { pub address : sh_op_mem_type , # [doc = " <= memory address"] pub reg : sh_reg , # [doc = " <= base register"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_mem"] [:: std :: mem :: size_of :: < sh_op_mem > () - 12usize] ; ["Alignment of sh_op_mem"] [:: std :: mem :: align_of :: < sh_op_mem > () - 4usize] ; ["Offset of field: sh_op_mem::address"] [:: std :: mem :: offset_of ! (sh_op_mem , address) - 0usize] ; ["Offset of field: sh_op_mem::reg"] [:: std :: mem :: offset_of ! (sh_op_mem , reg) - 4usize] ; ["Offset of field: sh_op_mem::disp"] [:: std :: mem :: offset_of ! (sh_op_mem , disp) - 8usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn_type { SH_INS_DSP_INVALID = 0 , SH_INS_DSP_DOUBLE = 1 , SH_INS_DSP_SINGLE = 2 , SH_INS_DSP_PARALLEL = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn { SH_INS_DSP_NOP = 1 , SH_INS_DSP_MOV = 2 , SH_INS_DSP_PSHL = 3 , SH_INS_DSP_PSHA = 4 , SH_INS_DSP_PMULS = 5 , SH_INS_DSP_PCLR_PMULS = 6 , SH_INS_DSP_PSUB_PMULS = 7 , SH_INS_DSP_PADD_PMULS = 8 , SH_INS_DSP_PSUBC = 9 , SH_INS_DSP_PADDC = 10 , SH_INS_DSP_PCMP = 11 , SH_INS_DSP_PABS = 12 , SH_INS_DSP_PRND = 13 , SH_INS_DSP_PSUB = 14 , SH_INS_DSP_PSUBr = 15 , SH_INS_DSP_PADD = 16 , SH_INS_DSP_PAND = 17 , SH_INS_DSP_PXOR = 18 , SH_INS_DSP_POR = 19 , SH_INS_DSP_PDEC = 20 , SH_INS_DSP_PINC = 21 , SH_INS_DSP_PCLR = 22 , SH_INS_DSP_PDMSB = 23 , SH_INS_DSP_PNEG = 24 , SH_INS_DSP_PCOPY = 25 , SH_INS_DSP_PSTS = 26 , SH_INS_DSP_PLDS = 27 , SH_INS_DSP_PSWAP = 28 , SH_INS_DSP_PWAD = 29 , SH_INS_DSP_PWSB = 30 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_operand { SH_OP_DSP_INVALID = 0 , SH_OP_DSP_REG_PRE = 1 , SH_OP_DSP_REG_IND = 2 , SH_OP_DSP_REG_POST = 3 , SH_OP_DSP_REG_INDEX = 4 , SH_OP_DSP_REG = 5 , SH_OP_DSP_IMM = 6 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_cc { SH_DSP_CC_INVALID = 0 , SH_DSP_CC_NONE = 1 , SH_DSP_CC_DCT = 2 , SH_DSP_CC_DCF = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_dsp { pub insn : sh_dsp_insn , pub operand : [sh_dsp_operand ; 2usize] , pub r : [sh_reg ; 6usize] , pub cc : sh_dsp_cc , pub imm : u8 , pub size : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_dsp"] [:: std :: mem :: size_of :: < sh_op_dsp > () - 48usize] ; ["Alignment of sh_op_dsp"] [:: std :: mem :: align_of :: < sh_op_dsp > () - 4usize] ; ["Offset of field: sh_op_dsp::insn"] [:: std :: mem :: offset_of ! (sh_op_dsp , insn) - 0usize] ; ["Offset of field: sh_op_dsp::operand"] [:: std :: mem :: offset_of ! (sh_op_dsp , operand) - 4usize] ; ["Offset of field: sh_op_dsp::r"] [:: std :: mem :: offset_of ! (sh_op_dsp , r) - 12usize] ; ["Offset of field: sh_op_dsp::cc"] [:: std :: mem :: offset_of ! (sh_op_dsp , cc) - 36usize] ; ["Offset of field: sh_op_dsp::imm"] [:: std :: mem :: offset_of ! (sh_op_dsp , imm) - 40usize] ; ["Offset of field: sh_op_dsp::size"] [:: std :: mem :: offset_of ! (sh_op_dsp , size) - 44usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh_op { pub type_ : sh_op_type , pub __bindgen_anon_1 : cs_sh_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sh_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< register value for REG operand"] pub reg : sh_reg , # [doc = "< data when operand is targeting memory"] pub mem : sh_op_mem , # [doc = "< dsp instruction"] pub dsp : sh_op_dsp , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sh_op__bindgen_ty_1 > () - 48usize] ; ["Alignment of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sh_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::dsp"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , dsp) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op"] [:: std :: mem :: size_of :: < cs_sh_op > () - 56usize] ; ["Alignment of cs_sh_op"] [:: std :: mem :: align_of :: < cs_sh_op > () - 8usize] ; ["Offset of field: cs_sh_op::type_"] [:: std :: mem :: offset_of ! (cs_sh_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (u32)] # [doc = " SH instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn { SH_INS_INVALID = 0 , SH_INS_ADD_r = 1 , SH_INS_ADD = 2 , SH_INS_ADDC = 3 , SH_INS_ADDV = 4 , SH_INS_AND = 5 , SH_INS_BAND = 6 , SH_INS_BANDNOT = 7 , SH_INS_BCLR = 8 , SH_INS_BF = 9 , SH_INS_BF_S = 10 , SH_INS_BLD = 11 , SH_INS_BLDNOT = 12 , SH_INS_BOR = 13 , SH_INS_BORNOT = 14 , SH_INS_BRA = 15 , SH_INS_BRAF = 16 , SH_INS_BSET = 17 , SH_INS_BSR = 18 , SH_INS_BSRF = 19 , SH_INS_BST = 20 , SH_INS_BT = 21 , SH_INS_BT_S = 22 , SH_INS_BXOR = 23 , SH_INS_CLIPS = 24 , SH_INS_CLIPU = 25 , SH_INS_CLRDMXY = 26 , SH_INS_CLRMAC = 27 , SH_INS_CLRS = 28 , SH_INS_CLRT = 29 , SH_INS_CMP_EQ = 30 , SH_INS_CMP_GE = 31 , SH_INS_CMP_GT = 32 , SH_INS_CMP_HI = 33 , SH_INS_CMP_HS = 34 , SH_INS_CMP_PL = 35 , SH_INS_CMP_PZ = 36 , SH_INS_CMP_STR = 37 , SH_INS_DIV0S = 38 , SH_INS_DIV0U = 39 , SH_INS_DIV1 = 40 , SH_INS_DIVS = 41 , SH_INS_DIVU = 42 , SH_INS_DMULS_L = 43 , SH_INS_DMULU_L = 44 , SH_INS_DT = 45 , SH_INS_EXTS_B = 46 , SH_INS_EXTS_W = 47 , SH_INS_EXTU_B = 48 , SH_INS_EXTU_W = 49 , SH_INS_FABS = 50 , SH_INS_FADD = 51 , SH_INS_FCMP_EQ = 52 , SH_INS_FCMP_GT = 53 , SH_INS_FCNVDS = 54 , SH_INS_FCNVSD = 55 , SH_INS_FDIV = 56 , SH_INS_FIPR = 57 , SH_INS_FLDI0 = 58 , SH_INS_FLDI1 = 59 , SH_INS_FLDS = 60 , SH_INS_FLOAT = 61 , SH_INS_FMAC = 62 , SH_INS_FMOV = 63 , SH_INS_FMUL = 64 , SH_INS_FNEG = 65 , SH_INS_FPCHG = 66 , SH_INS_FRCHG = 67 , SH_INS_FSCA = 68 , SH_INS_FSCHG = 69 , SH_INS_FSQRT = 70 , SH_INS_FSRRA = 71 , SH_INS_FSTS = 72 , SH_INS_FSUB = 73 , SH_INS_FTRC = 74 , SH_INS_FTRV = 75 , SH_INS_ICBI = 76 , SH_INS_JMP = 77 , SH_INS_JSR = 78 , SH_INS_JSR_N = 79 , SH_INS_LDBANK = 80 , SH_INS_LDC = 81 , SH_INS_LDRC = 82 , SH_INS_LDRE = 83 , SH_INS_LDRS = 84 , SH_INS_LDS = 85 , SH_INS_LDTLB = 86 , SH_INS_MAC_L = 87 , SH_INS_MAC_W = 88 , SH_INS_MOV = 89 , SH_INS_MOVA = 90 , SH_INS_MOVCA = 91 , SH_INS_MOVCO = 92 , SH_INS_MOVI20 = 93 , SH_INS_MOVI20S = 94 , SH_INS_MOVLI = 95 , SH_INS_MOVML = 96 , SH_INS_MOVMU = 97 , SH_INS_MOVRT = 98 , SH_INS_MOVT = 99 , SH_INS_MOVU = 100 , SH_INS_MOVUA = 101 , SH_INS_MUL_L = 102 , SH_INS_MULR = 103 , SH_INS_MULS_W = 104 , SH_INS_MULU_W = 105 , SH_INS_NEG = 106 , SH_INS_NEGC = 107 , SH_INS_NOP = 108 , SH_INS_NOT = 109 , SH_INS_NOTT = 110 , SH_INS_OCBI = 111 , SH_INS_OCBP = 112 , SH_INS_OCBWB = 113 , SH_INS_OR = 114 , SH_INS_PREF = 115 , SH_INS_PREFI = 116 , SH_INS_RESBANK = 117 , SH_INS_ROTCL = 118 , SH_INS_ROTCR = 119 , SH_INS_ROTL = 120 , SH_INS_ROTR = 121 , SH_INS_RTE = 122 , SH_INS_RTS = 123 , SH_INS_RTS_N = 124 , SH_INS_RTV_N = 125 , SH_INS_SETDMX = 126 , SH_INS_SETDMY = 127 , SH_INS_SETRC = 128 , SH_INS_SETS = 129 , SH_INS_SETT = 130 , SH_INS_SHAD = 131 , SH_INS_SHAL = 132 , SH_INS_SHAR = 133 , SH_INS_SHLD = 134 , SH_INS_SHLL = 135 , SH_INS_SHLL16 = 136 , SH_INS_SHLL2 = 137 , SH_INS_SHLL8 = 138 , SH_INS_SHLR = 139 , SH_INS_SHLR16 = 140 , SH_INS_SHLR2 = 141 , SH_INS_SHLR8 = 142 , SH_INS_SLEEP = 143 , SH_INS_STBANK = 144 , SH_INS_STC = 145 , SH_INS_STS = 146 , SH_INS_SUB = 147 , SH_INS_SUBC = 148 , SH_INS_SUBV = 149 , SH_INS_SWAP_B = 150 , SH_INS_SWAP_W = 151 , SH_INS_SYNCO = 152 , SH_INS_TAS = 153 , SH_INS_TRAPA = 154 , SH_INS_TST = 155 , SH_INS_XOR = 156 , SH_INS_XTRCT = 157 , SH_INS_DSP = 158 , SH_INS_ENDING = 159 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh { pub insn : sh_insn , pub size : u8 , pub op_count : u8 , pub operands : [cs_sh_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh"] [:: std :: mem :: size_of :: < cs_sh > () - 176usize] ; ["Alignment of cs_sh"] [:: std :: mem :: align_of :: < cs_sh > () - 8usize] ; ["Offset of field: cs_sh::insn"] [:: std :: mem :: offset_of ! (cs_sh , insn) - 0usize] ; ["Offset of field: cs_sh::size"] [:: std :: mem :: offset_of ! (cs_sh , size) - 4usize] ; ["Offset of field: cs_sh::op_count"] [:: std :: mem :: offset_of ! (cs_sh , op_count) - 5usize] ; ["Offset of field: cs_sh::operands"] [:: std :: mem :: offset_of ! (cs_sh , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sh { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh {{ insn: {:?}, size: {:?}, op_count: {:?}, operands: {:?} }}" , self . insn , self . size , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Group of SH instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn_group { # [doc = "< CS_GRUP_INVALID"] SH_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SH_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] SH_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] SH_GRP_INT = 3 , # [doc = "< = CS_GRP_RET"] SH_GRP_RET = 4 , # [doc = "< = CS_GRP_IRET"] SH_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] SH_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] SH_GRP_BRANCH_RELATIVE = 7 , SH_GRP_SH1 = 8 , SH_GRP_SH2 = 9 , SH_GRP_SH2E = 10 , SH_GRP_SH2DSP = 11 , SH_GRP_SH2A = 12 , SH_GRP_SH2AFPU = 13 , SH_GRP_SH3 = 14 , SH_GRP_SH3DSP = 15 , SH_GRP_SH4 = 16 , SH_GRP_SH4A = 17 , SH_GRP_ENDING = 18 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_op_type { # [doc = "< CS_OP_INVALID (Uninitialized)."] TRICORE_OP_INVALID = 0 , # [doc = "< CS_OP_REG (Register operand)."] TRICORE_OP_REG = 1 , # [doc = "< CS_OP_IMM (Immediate operand)."] TRICORE_OP_IMM = 2 , # [doc = "< CS_OP_MEM (Memory operand)."] TRICORE_OP_MEM = 3 , } # [doc = " Instruction's operand referring to memory\n This is associated with TRICORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tricore_op_mem { # [doc = "< base register"] pub base : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tricore_op_mem"] [:: std :: mem :: size_of :: < tricore_op_mem > () - 8usize] ; ["Alignment of tricore_op_mem"] [:: std :: mem :: align_of :: < tricore_op_mem > () - 4usize] ; ["Offset of field: tricore_op_mem::base"] [:: std :: mem :: offset_of ! (tricore_op_mem , base) - 0usize] ; ["Offset of field: tricore_op_mem::disp"] [:: std :: mem :: offset_of ! (tricore_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore_op { # [doc = "< operand type"] pub type_ : tricore_op_type , pub __bindgen_anon_1 : cs_tricore_op__bindgen_ty_1 , # [doc = "< How is this operand accessed? (READ, WRITE or READ|WRITE)"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tricore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tricore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tricore_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tricore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op"] [:: std :: mem :: size_of :: < cs_tricore_op > () - 16usize] ; ["Alignment of cs_tricore_op"] [:: std :: mem :: align_of :: < cs_tricore_op > () - 4usize] ; ["Offset of field: cs_tricore_op::type_"] [:: std :: mem :: offset_of ! (cs_tricore_op , type_) - 0usize] ; ["Offset of field: cs_tricore_op::access"] [:: std :: mem :: offset_of ! (cs_tricore_op , access) - 12usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore { # [doc = "< number of operands of this instruction."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tricore_op ; 8usize] , # [doc = "< whether the flags register is updated."] pub update_flags : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore"] [:: std :: mem :: size_of :: < cs_tricore > () - 136usize] ; ["Alignment of cs_tricore"] [:: std :: mem :: align_of :: < cs_tricore > () - 4usize] ; ["Offset of field: cs_tricore::op_count"] [:: std :: mem :: offset_of ! (cs_tricore , op_count) - 0usize] ; ["Offset of field: cs_tricore::operands"] [:: std :: mem :: offset_of ! (cs_tricore , operands) - 4usize] ; ["Offset of field: cs_tricore::update_flags"] [:: std :: mem :: offset_of ! (cs_tricore , update_flags) - 132usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore {{ op_count: {:?}, operands: {:?}, update_flags: {:?} }}" , self . op_count , self . operands , self . update_flags) } } # [repr (u32)] # [doc = " TriCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_reg { TRICORE_REG_INVALID = 0 , TRICORE_REG_FCX = 1 , TRICORE_REG_PC = 2 , TRICORE_REG_PCXI = 3 , TRICORE_REG_PSW = 4 , TRICORE_REG_A0 = 5 , TRICORE_REG_A1 = 6 , TRICORE_REG_A2 = 7 , TRICORE_REG_A3 = 8 , TRICORE_REG_A4 = 9 , TRICORE_REG_A5 = 10 , TRICORE_REG_A6 = 11 , TRICORE_REG_A7 = 12 , TRICORE_REG_A8 = 13 , TRICORE_REG_A9 = 14 , TRICORE_REG_A10 = 15 , TRICORE_REG_A11 = 16 , TRICORE_REG_A12 = 17 , TRICORE_REG_A13 = 18 , TRICORE_REG_A14 = 19 , TRICORE_REG_A15 = 20 , TRICORE_REG_D0 = 21 , TRICORE_REG_D1 = 22 , TRICORE_REG_D2 = 23 , TRICORE_REG_D3 = 24 , TRICORE_REG_D4 = 25 , TRICORE_REG_D5 = 26 , TRICORE_REG_D6 = 27 , TRICORE_REG_D7 = 28 , TRICORE_REG_D8 = 29 , TRICORE_REG_D9 = 30 , TRICORE_REG_D10 = 31 , TRICORE_REG_D11 = 32 , TRICORE_REG_D12 = 33 , TRICORE_REG_D13 = 34 , TRICORE_REG_D14 = 35 , TRICORE_REG_D15 = 36 , TRICORE_REG_E0 = 37 , TRICORE_REG_E2 = 38 , TRICORE_REG_E4 = 39 , TRICORE_REG_E6 = 40 , TRICORE_REG_E8 = 41 , TRICORE_REG_E10 = 42 , TRICORE_REG_E12 = 43 , TRICORE_REG_E14 = 44 , TRICORE_REG_P0 = 45 , TRICORE_REG_P2 = 46 , TRICORE_REG_P4 = 47 , TRICORE_REG_P6 = 48 , TRICORE_REG_P8 = 49 , TRICORE_REG_P10 = 50 , TRICORE_REG_P12 = 51 , TRICORE_REG_P14 = 52 , TRICORE_REG_A0_A1 = 53 , TRICORE_REG_A2_A3 = 54 , TRICORE_REG_A4_A5 = 55 , TRICORE_REG_A6_A7 = 56 , TRICORE_REG_A8_A9 = 57 , TRICORE_REG_A10_A11 = 58 , TRICORE_REG_A12_A13 = 59 , TRICORE_REG_A14_A15 = 60 , TRICORE_REG_ENDING = 61 , } # [repr (u32)] # [doc = " TriCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn { TRICORE_INS_INVALID = 0 , TRICORE_INS_XOR_T = 1 , TRICORE_INS_ABSDIFS_B = 2 , TRICORE_INS_ABSDIFS_H = 3 , TRICORE_INS_ABSDIFS = 4 , TRICORE_INS_ABSDIF_B = 5 , TRICORE_INS_ABSDIF_H = 6 , TRICORE_INS_ABSDIF = 7 , TRICORE_INS_ABSS_B = 8 , TRICORE_INS_ABSS_H = 9 , TRICORE_INS_ABSS = 10 , TRICORE_INS_ABS_B = 11 , TRICORE_INS_ABS_H = 12 , TRICORE_INS_ABS = 13 , TRICORE_INS_ADDC = 14 , TRICORE_INS_ADDIH_A = 15 , TRICORE_INS_ADDIH = 16 , TRICORE_INS_ADDI = 17 , TRICORE_INS_ADDSC_AT = 18 , TRICORE_INS_ADDSC_A = 19 , TRICORE_INS_ADDS_BU = 20 , TRICORE_INS_ADDS_B = 21 , TRICORE_INS_ADDS_H = 22 , TRICORE_INS_ADDS_HU = 23 , TRICORE_INS_ADDS_U = 24 , TRICORE_INS_ADDS = 25 , TRICORE_INS_ADDX = 26 , TRICORE_INS_ADD_A = 27 , TRICORE_INS_ADD_B = 28 , TRICORE_INS_ADD_F = 29 , TRICORE_INS_ADD_H = 30 , TRICORE_INS_ADD = 31 , TRICORE_INS_ANDN_T = 32 , TRICORE_INS_ANDN = 33 , TRICORE_INS_AND_ANDN_T = 34 , TRICORE_INS_AND_AND_T = 35 , TRICORE_INS_AND_EQ = 36 , TRICORE_INS_AND_GE_U = 37 , TRICORE_INS_AND_GE = 38 , TRICORE_INS_AND_LT_U = 39 , TRICORE_INS_AND_LT = 40 , TRICORE_INS_AND_NE = 41 , TRICORE_INS_AND_NOR_T = 42 , TRICORE_INS_AND_OR_T = 43 , TRICORE_INS_AND_T = 44 , TRICORE_INS_AND = 45 , TRICORE_INS_BISR = 46 , TRICORE_INS_BMERGE = 47 , TRICORE_INS_BSPLIT = 48 , TRICORE_INS_CACHEA_I = 49 , TRICORE_INS_CACHEA_WI = 50 , TRICORE_INS_CACHEA_W = 51 , TRICORE_INS_CACHEI_I = 52 , TRICORE_INS_CACHEI_WI = 53 , TRICORE_INS_CACHEI_W = 54 , TRICORE_INS_CADDN_A = 55 , TRICORE_INS_CADDN = 56 , TRICORE_INS_CADD_A = 57 , TRICORE_INS_CADD = 58 , TRICORE_INS_CALLA = 59 , TRICORE_INS_CALLI = 60 , TRICORE_INS_CALL = 61 , TRICORE_INS_CLO_B = 62 , TRICORE_INS_CLO_H = 63 , TRICORE_INS_CLO = 64 , TRICORE_INS_CLS_B = 65 , TRICORE_INS_CLS_H = 66 , TRICORE_INS_CLS = 67 , TRICORE_INS_CLZ_B = 68 , TRICORE_INS_CLZ_H = 69 , TRICORE_INS_CLZ = 70 , TRICORE_INS_CMOVN = 71 , TRICORE_INS_CMOV = 72 , TRICORE_INS_CMPSWAP_W = 73 , TRICORE_INS_CMP_F = 74 , TRICORE_INS_CRC32B_W = 75 , TRICORE_INS_CRC32L_W = 76 , TRICORE_INS_CRC32_B = 77 , TRICORE_INS_CRCN = 78 , TRICORE_INS_CSUBN_A = 79 , TRICORE_INS_CSUBN = 80 , TRICORE_INS_CSUB_A = 81 , TRICORE_INS_CSUB = 82 , TRICORE_INS_DEBUG = 83 , TRICORE_INS_DEXTR = 84 , TRICORE_INS_DIFSC_A = 85 , TRICORE_INS_DISABLE = 86 , TRICORE_INS_DIV_F = 87 , TRICORE_INS_DIV_U = 88 , TRICORE_INS_DIV = 89 , TRICORE_INS_DSYNC = 90 , TRICORE_INS_DVADJ = 91 , TRICORE_INS_DVINIT_BU = 92 , TRICORE_INS_DVINIT_B = 93 , TRICORE_INS_DVINIT_HU = 94 , TRICORE_INS_DVINIT_H = 95 , TRICORE_INS_DVINIT_U = 96 , TRICORE_INS_DVINIT = 97 , TRICORE_INS_DVSTEP_U = 98 , TRICORE_INS_DVSTEP = 99 , TRICORE_INS_ENABLE = 100 , TRICORE_INS_EQANY_B = 101 , TRICORE_INS_EQANY_H = 102 , TRICORE_INS_EQZ_A = 103 , TRICORE_INS_EQ_A = 104 , TRICORE_INS_EQ_B = 105 , TRICORE_INS_EQ_H = 106 , TRICORE_INS_EQ_W = 107 , TRICORE_INS_EQ = 108 , TRICORE_INS_EXTR_U = 109 , TRICORE_INS_EXTR = 110 , TRICORE_INS_FCALLA = 111 , TRICORE_INS_FCALLI = 112 , TRICORE_INS_FCALL = 113 , TRICORE_INS_FRET = 114 , TRICORE_INS_FTOHP = 115 , TRICORE_INS_FTOIZ = 116 , TRICORE_INS_FTOI = 117 , TRICORE_INS_FTOQ31Z = 118 , TRICORE_INS_FTOQ31 = 119 , TRICORE_INS_FTOUZ = 120 , TRICORE_INS_FTOU = 121 , TRICORE_INS_GE_A = 122 , TRICORE_INS_GE_U = 123 , TRICORE_INS_GE = 124 , TRICORE_INS_HPTOF = 125 , TRICORE_INS_IMASK = 126 , TRICORE_INS_INSERT = 127 , TRICORE_INS_INSN_T = 128 , TRICORE_INS_INS_T = 129 , TRICORE_INS_ISYNC = 130 , TRICORE_INS_ITOF = 131 , TRICORE_INS_IXMAX_U = 132 , TRICORE_INS_IXMAX = 133 , TRICORE_INS_IXMIN_U = 134 , TRICORE_INS_IXMIN = 135 , TRICORE_INS_JA = 136 , TRICORE_INS_JEQ_A = 137 , TRICORE_INS_JEQ = 138 , TRICORE_INS_JGEZ = 139 , TRICORE_INS_JGE_U = 140 , TRICORE_INS_JGE = 141 , TRICORE_INS_JGTZ = 142 , TRICORE_INS_JI = 143 , TRICORE_INS_JLA = 144 , TRICORE_INS_JLEZ = 145 , TRICORE_INS_JLI = 146 , TRICORE_INS_JLTZ = 147 , TRICORE_INS_JLT_U = 148 , TRICORE_INS_JLT = 149 , TRICORE_INS_JL = 150 , TRICORE_INS_JNED = 151 , TRICORE_INS_JNEI = 152 , TRICORE_INS_JNE_A = 153 , TRICORE_INS_JNE = 154 , TRICORE_INS_JNZ_A = 155 , TRICORE_INS_JNZ_T = 156 , TRICORE_INS_JNZ = 157 , TRICORE_INS_JZ_A = 158 , TRICORE_INS_JZ_T = 159 , TRICORE_INS_JZ = 160 , TRICORE_INS_J = 161 , TRICORE_INS_LDLCX = 162 , TRICORE_INS_LDMST = 163 , TRICORE_INS_LDUCX = 164 , TRICORE_INS_LD_A = 165 , TRICORE_INS_LD_BU = 166 , TRICORE_INS_LD_B = 167 , TRICORE_INS_LD_DA = 168 , TRICORE_INS_LD_D = 169 , TRICORE_INS_LD_HU = 170 , TRICORE_INS_LD_H = 171 , TRICORE_INS_LD_Q = 172 , TRICORE_INS_LD_W = 173 , TRICORE_INS_LEA = 174 , TRICORE_INS_LHA = 175 , TRICORE_INS_LOOPU = 176 , TRICORE_INS_LOOP = 177 , TRICORE_INS_LT_A = 178 , TRICORE_INS_LT_B = 179 , TRICORE_INS_LT_BU = 180 , TRICORE_INS_LT_H = 181 , TRICORE_INS_LT_HU = 182 , TRICORE_INS_LT_U = 183 , TRICORE_INS_LT_W = 184 , TRICORE_INS_LT_WU = 185 , TRICORE_INS_LT = 186 , TRICORE_INS_MADDMS_H = 187 , TRICORE_INS_MADDMS_U = 188 , TRICORE_INS_MADDMS = 189 , TRICORE_INS_MADDM_H = 190 , TRICORE_INS_MADDM_Q = 191 , TRICORE_INS_MADDM_U = 192 , TRICORE_INS_MADDM = 193 , TRICORE_INS_MADDRS_H = 194 , TRICORE_INS_MADDRS_Q = 195 , TRICORE_INS_MADDR_H = 196 , TRICORE_INS_MADDR_Q = 197 , TRICORE_INS_MADDSUMS_H = 198 , TRICORE_INS_MADDSUM_H = 199 , TRICORE_INS_MADDSURS_H = 200 , TRICORE_INS_MADDSUR_H = 201 , TRICORE_INS_MADDSUS_H = 202 , TRICORE_INS_MADDSU_H = 203 , TRICORE_INS_MADDS_H = 204 , TRICORE_INS_MADDS_Q = 205 , TRICORE_INS_MADDS_U = 206 , TRICORE_INS_MADDS = 207 , TRICORE_INS_MADD_F = 208 , TRICORE_INS_MADD_H = 209 , TRICORE_INS_MADD_Q = 210 , TRICORE_INS_MADD_U = 211 , TRICORE_INS_MADD = 212 , TRICORE_INS_MAX_B = 213 , TRICORE_INS_MAX_BU = 214 , TRICORE_INS_MAX_H = 215 , TRICORE_INS_MAX_HU = 216 , TRICORE_INS_MAX_U = 217 , TRICORE_INS_MAX = 218 , TRICORE_INS_MFCR = 219 , TRICORE_INS_MIN_B = 220 , TRICORE_INS_MIN_BU = 221 , TRICORE_INS_MIN_H = 222 , TRICORE_INS_MIN_HU = 223 , TRICORE_INS_MIN_U = 224 , TRICORE_INS_MIN = 225 , TRICORE_INS_MOVH_A = 226 , TRICORE_INS_MOVH = 227 , TRICORE_INS_MOVZ_A = 228 , TRICORE_INS_MOV_AA = 229 , TRICORE_INS_MOV_A = 230 , TRICORE_INS_MOV_D = 231 , TRICORE_INS_MOV_U = 232 , TRICORE_INS_MOV = 233 , TRICORE_INS_MSUBADMS_H = 234 , TRICORE_INS_MSUBADM_H = 235 , TRICORE_INS_MSUBADRS_H = 236 , TRICORE_INS_MSUBADR_H = 237 , TRICORE_INS_MSUBADS_H = 238 , TRICORE_INS_MSUBAD_H = 239 , TRICORE_INS_MSUBMS_H = 240 , TRICORE_INS_MSUBMS_U = 241 , TRICORE_INS_MSUBMS = 242 , TRICORE_INS_MSUBM_H = 243 , TRICORE_INS_MSUBM_Q = 244 , TRICORE_INS_MSUBM_U = 245 , TRICORE_INS_MSUBM = 246 , TRICORE_INS_MSUBRS_H = 247 , TRICORE_INS_MSUBRS_Q = 248 , TRICORE_INS_MSUBR_H = 249 , TRICORE_INS_MSUBR_Q = 250 , TRICORE_INS_MSUBS_H = 251 , TRICORE_INS_MSUBS_Q = 252 , TRICORE_INS_MSUBS_U = 253 , TRICORE_INS_MSUBS = 254 , TRICORE_INS_MSUB_F = 255 , TRICORE_INS_MSUB_H = 256 , TRICORE_INS_MSUB_Q = 257 , TRICORE_INS_MSUB_U = 258 , TRICORE_INS_MSUB = 259 , TRICORE_INS_MTCR = 260 , TRICORE_INS_MULMS_H = 261 , TRICORE_INS_MULM_H = 262 , TRICORE_INS_MULM_U = 263 , TRICORE_INS_MULM = 264 , TRICORE_INS_MULR_H = 265 , TRICORE_INS_MULR_Q = 266 , TRICORE_INS_MULS_U = 267 , TRICORE_INS_MULS = 268 , TRICORE_INS_MUL_F = 269 , TRICORE_INS_MUL_H = 270 , TRICORE_INS_MUL_Q = 271 , TRICORE_INS_MUL_U = 272 , TRICORE_INS_MUL = 273 , TRICORE_INS_NAND_T = 274 , TRICORE_INS_NAND = 275 , TRICORE_INS_NEZ_A = 276 , TRICORE_INS_NE_A = 277 , TRICORE_INS_NE = 278 , TRICORE_INS_NOP = 279 , TRICORE_INS_NOR_T = 280 , TRICORE_INS_NOR = 281 , TRICORE_INS_NOT = 282 , TRICORE_INS_ORN_T = 283 , TRICORE_INS_ORN = 284 , TRICORE_INS_OR_ANDN_T = 285 , TRICORE_INS_OR_AND_T = 286 , TRICORE_INS_OR_EQ = 287 , TRICORE_INS_OR_GE_U = 288 , TRICORE_INS_OR_GE = 289 , TRICORE_INS_OR_LT_U = 290 , TRICORE_INS_OR_LT = 291 , TRICORE_INS_OR_NE = 292 , TRICORE_INS_OR_NOR_T = 293 , TRICORE_INS_OR_OR_T = 294 , TRICORE_INS_OR_T = 295 , TRICORE_INS_OR = 296 , TRICORE_INS_PACK = 297 , TRICORE_INS_PARITY = 298 , TRICORE_INS_POPCNT_W = 299 , TRICORE_INS_Q31TOF = 300 , TRICORE_INS_QSEED_F = 301 , TRICORE_INS_RESTORE = 302 , TRICORE_INS_RET = 303 , TRICORE_INS_RFE = 304 , TRICORE_INS_RFM = 305 , TRICORE_INS_RSLCX = 306 , TRICORE_INS_RSTV = 307 , TRICORE_INS_RSUBS_U = 308 , TRICORE_INS_RSUBS = 309 , TRICORE_INS_RSUB = 310 , TRICORE_INS_SAT_BU = 311 , TRICORE_INS_SAT_B = 312 , TRICORE_INS_SAT_HU = 313 , TRICORE_INS_SAT_H = 314 , TRICORE_INS_SELN_A = 315 , TRICORE_INS_SELN = 316 , TRICORE_INS_SEL_A = 317 , TRICORE_INS_SEL = 318 , TRICORE_INS_SHAS = 319 , TRICORE_INS_SHA_B = 320 , TRICORE_INS_SHA_H = 321 , TRICORE_INS_SHA = 322 , TRICORE_INS_SHUFFLE = 323 , TRICORE_INS_SH_ANDN_T = 324 , TRICORE_INS_SH_AND_T = 325 , TRICORE_INS_SH_B = 326 , TRICORE_INS_SH_EQ = 327 , TRICORE_INS_SH_GE_U = 328 , TRICORE_INS_SH_GE = 329 , TRICORE_INS_SH_H = 330 , TRICORE_INS_SH_LT_U = 331 , TRICORE_INS_SH_LT = 332 , TRICORE_INS_SH_NAND_T = 333 , TRICORE_INS_SH_NE = 334 , TRICORE_INS_SH_NOR_T = 335 , TRICORE_INS_SH_ORN_T = 336 , TRICORE_INS_SH_OR_T = 337 , TRICORE_INS_SH_XNOR_T = 338 , TRICORE_INS_SH_XOR_T = 339 , TRICORE_INS_SH = 340 , TRICORE_INS_STLCX = 341 , TRICORE_INS_STUCX = 342 , TRICORE_INS_ST_A = 343 , TRICORE_INS_ST_B = 344 , TRICORE_INS_ST_DA = 345 , TRICORE_INS_ST_D = 346 , TRICORE_INS_ST_H = 347 , TRICORE_INS_ST_Q = 348 , TRICORE_INS_ST_T = 349 , TRICORE_INS_ST_W = 350 , TRICORE_INS_SUBC = 351 , TRICORE_INS_SUBSC_A = 352 , TRICORE_INS_SUBS_BU = 353 , TRICORE_INS_SUBS_B = 354 , TRICORE_INS_SUBS_HU = 355 , TRICORE_INS_SUBS_H = 356 , TRICORE_INS_SUBS_U = 357 , TRICORE_INS_SUBS = 358 , TRICORE_INS_SUBX = 359 , TRICORE_INS_SUB_A = 360 , TRICORE_INS_SUB_B = 361 , TRICORE_INS_SUB_F = 362 , TRICORE_INS_SUB_H = 363 , TRICORE_INS_SUB = 364 , TRICORE_INS_SVLCX = 365 , TRICORE_INS_SWAPMSK_W = 366 , TRICORE_INS_SWAP_A = 367 , TRICORE_INS_SWAP_W = 368 , TRICORE_INS_SYSCALL = 369 , TRICORE_INS_TLBDEMAP = 370 , TRICORE_INS_TLBFLUSH_A = 371 , TRICORE_INS_TLBFLUSH_B = 372 , TRICORE_INS_TLBMAP = 373 , TRICORE_INS_TLBPROBE_A = 374 , TRICORE_INS_TLBPROBE_I = 375 , TRICORE_INS_TRAPSV = 376 , TRICORE_INS_TRAPV = 377 , TRICORE_INS_UNPACK = 378 , TRICORE_INS_UPDFL = 379 , TRICORE_INS_UTOF = 380 , TRICORE_INS_WAIT = 381 , TRICORE_INS_XNOR_T = 382 , TRICORE_INS_XNOR = 383 , TRICORE_INS_XOR_EQ = 384 , TRICORE_INS_XOR_GE_U = 385 , TRICORE_INS_XOR_GE = 386 , TRICORE_INS_XOR_LT_U = 387 , TRICORE_INS_XOR_LT = 388 , TRICORE_INS_XOR_NE = 389 , TRICORE_INS_XOR = 390 , TRICORE_INS_ENDING = 391 , } # [repr (u32)] # [doc = " Group of TriCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn_group { # [doc = "< = CS_GRP_INVALID"] TRICORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_CALL"] TRICORE_GRP_CALL = 1 , # [doc = "< = CS_GRP_JUMP"] TRICORE_GRP_JUMP = 2 , # [doc = "< mark the end of the list of groups"] TRICORE_GRP_ENDING = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_feature_t { TRICORE_FEATURE_INVALID = 0 , TRICORE_FEATURE_HasV110 = 128 , TRICORE_FEATURE_HasV120_UP = 129 , TRICORE_FEATURE_HasV130_UP = 130 , TRICORE_FEATURE_HasV161 = 131 , TRICORE_FEATURE_HasV160_UP = 132 , TRICORE_FEATURE_HasV131_UP = 133 , TRICORE_FEATURE_HasV161_UP = 134 , TRICORE_FEATURE_HasV162 = 135 , TRICORE_FEATURE_HasV162_UP = 136 , # [doc = "< mark the end of the list of features"] TRICORE_FEATURE_ENDING = 137 , } pub use self :: tricore_feature_t as tricore_feature ; # [doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_detail { pub regs_read : [u16 ; 20usize] , # [doc = "< number of implicit registers read by this insn"] pub regs_read_count : u8 , pub regs_write : [u16 ; 20usize] , # [doc = "< number of implicit registers modified by this insn"] pub regs_write_count : u8 , # [doc = "< list of group this instruction belong to"] pub groups : [u8 ; 8usize] , # [doc = "< number of groups this insn belongs to"] pub groups_count : u8 , # [doc = "< Instruction has writeback operands."] pub writeback : bool , pub __bindgen_anon_1 : cs_detail__bindgen_ty_1 , } # [doc = " Architecture-specific instruction info"] # [repr (C)] # [derive (Copy , Clone)] pub union cs_detail__bindgen_ty_1 { # [doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"] pub x86 : cs_x86 , # [doc = "< ARM64 architecture (aka AArch64)"] pub arm64 : cs_arm64 , # [doc = "< ARM architecture (including Thumb/Thumb2)"] pub arm : cs_arm , # [doc = "< M68K architecture"] pub m68k : cs_m68k , # [doc = "< MIPS architecture"] pub mips : cs_mips , # [doc = "< PowerPC architecture"] pub ppc : cs_ppc , # [doc = "< Sparc architecture"] pub sparc : cs_sparc , # [doc = "< SystemZ architecture"] pub sysz : cs_sysz , # [doc = "< XCore architecture"] pub xcore : cs_xcore , # [doc = "< TMS320C64x architecture"] pub tms320c64x : cs_tms320c64x , # [doc = "< M680X architecture"] pub m680x : cs_m680x , # [doc = "< Ethereum architecture"] pub evm : cs_evm , # [doc = "< MOS65XX architecture (including MOS6502)"] pub mos65xx : cs_mos65xx , # [doc = "< Web Assembly architecture"] pub wasm : cs_wasm , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] pub bpf : cs_bpf , # [doc = "< RISCV architecture"] pub riscv : cs_riscv , # [doc = "< SH architecture"] pub sh : cs_sh , # [doc = "< TriCore architecture"] pub tricore : cs_tricore , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_detail__bindgen_ty_1 > () - 1768usize] ; ["Alignment of cs_detail__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_detail__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_detail__bindgen_ty_1::x86"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , x86) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm64"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm64) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m68k"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m68k) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mips"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mips) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::ppc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , ppc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sparc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sparc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sysz"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sysz) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::xcore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , xcore) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tms320c64x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tms320c64x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m680x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m680x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::evm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , evm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mos65xx"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mos65xx) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::wasm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , wasm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::bpf"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , bpf) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::riscv"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , riscv) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sh"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sh) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tricore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tricore) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_detail__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail"] [:: std :: mem :: size_of :: < cs_detail > () - 1864usize] ; ["Alignment of cs_detail"] [:: std :: mem :: align_of :: < cs_detail > () - 8usize] ; ["Offset of field: cs_detail::regs_read"] [:: std :: mem :: offset_of ! (cs_detail , regs_read) - 0usize] ; ["Offset of field: cs_detail::regs_read_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_read_count) - 40usize] ; ["Offset of field: cs_detail::regs_write"] [:: std :: mem :: offset_of ! (cs_detail , regs_write) - 42usize] ; ["Offset of field: cs_detail::regs_write_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_write_count) - 82usize] ; ["Offset of field: cs_detail::groups"] [:: std :: mem :: offset_of ! (cs_detail , groups) - 83usize] ; ["Offset of field: cs_detail::groups_count"] [:: std :: mem :: offset_of ! (cs_detail , groups_count) - 91usize] ; ["Offset of field: cs_detail::writeback"] [:: std :: mem :: offset_of ! (cs_detail , writeback) - 92usize] ; } ; impl :: std :: fmt :: Debug for cs_detail { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, writeback: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . writeback , self . __bindgen_anon_1) } } # [doc = " Detail information of disassembled instruction"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_insn { # [doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub address : u64 , # [doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub size : u16 , # [doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub bytes : [u8 ; 24usize] , # [doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub mnemonic : [:: std :: os :: raw :: c_char ; 32usize] , # [doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub op_str : [:: std :: os :: raw :: c_char ; 160usize] , # [doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."] pub detail : * mut cs_detail , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_insn"] [:: std :: mem :: size_of :: < cs_insn > () - 248usize] ; ["Alignment of cs_insn"] [:: std :: mem :: align_of :: < cs_insn > () - 8usize] ; ["Offset of field: cs_insn::id"] [:: std :: mem :: offset_of ! (cs_insn , id) - 0usize] ; ["Offset of field: cs_insn::address"] [:: std :: mem :: offset_of ! (cs_insn , address) - 8usize] ; ["Offset of field: cs_insn::size"] [:: std :: mem :: offset_of ! (cs_insn , size) - 16usize] ; ["Offset of field: cs_insn::bytes"] [:: std :: mem :: offset_of ! (cs_insn , bytes) - 18usize] ; ["Offset of field: cs_insn::mnemonic"] [:: std :: mem :: offset_of ! (cs_insn , mnemonic) - 42usize] ; ["Offset of field: cs_insn::op_str"] [:: std :: mem :: offset_of ! (cs_insn , op_str) - 74usize] ; ["Offset of field: cs_insn::detail"] [:: std :: mem :: offset_of ! (cs_insn , detail) - 240usize] ; } ; # [repr (u32)] # [doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_err { # [doc = "< No error: everything was fine"] CS_ERR_OK = 0 , # [doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"] CS_ERR_MEM = 1 , # [doc = "< Unsupported architecture: cs_open()"] CS_ERR_ARCH = 2 , # [doc = "< Invalid handle: cs_op_count(), cs_op_index()"] CS_ERR_HANDLE = 3 , # [doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"] CS_ERR_CSH = 4 , # [doc = "< Invalid/unsupported mode: cs_open()"] CS_ERR_MODE = 5 , # [doc = "< Invalid/unsupported option: cs_option()"] CS_ERR_OPTION = 6 , # [doc = "< Information is unavailable because detail option is OFF"] CS_ERR_DETAIL = 7 , # [doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"] CS_ERR_MEMSETUP = 8 , # [doc = "< Unsupported version (bindings)"] CS_ERR_VERSION = 9 , # [doc = "< Access irrelevant data in \"diet\" engine"] CS_ERR_DIET = 10 , # [doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"] CS_ERR_SKIPDATA = 11 , # [doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_ATT = 12 , # [doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_INTEL = 13 , # [doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_MASM = 14 , } unsafe extern "C" { # [doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."] pub fn cs_version (major : * mut :: std :: os :: raw :: c_int , minor : * mut :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_uint ; } unsafe extern "C" { # [doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."] pub fn cs_support (query : :: std :: os :: raw :: c_int) -> bool ; } unsafe extern "C" { # [doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_open (arch : cs_arch , mode : cs_mode , handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_close (handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"] pub fn cs_option (handle : csh , type_ : cs_opt_type , value : usize) -> cs_err ; } unsafe extern "C" { # [doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"] pub fn cs_errno (handle : csh) -> cs_err ; } unsafe extern "C" { # [doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"] pub fn cs_strerror (code : cs_err) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm (handle : csh , code : * const u8 , code_size : usize , address : u64 , count : usize , insn : * mut * mut cs_insn) -> usize ; } unsafe extern "C" { # [doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."] pub fn cs_free (insn : * mut cs_insn , count : usize) ; } unsafe extern "C" { # [doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"] pub fn cs_malloc (handle : csh) -> * mut cs_insn ; } unsafe extern "C" { # [doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm_iter (handle : csh , code : * mut * const u8 , size : * mut usize , address : * mut u64 , insn : * mut cs_insn) -> bool ; } unsafe extern "C" { # [doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."] pub fn cs_reg_name (handle : csh , reg_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."] pub fn cs_insn_name (handle : csh , insn_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."] pub fn cs_group_name (handle : csh , group_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."] pub fn cs_insn_group (handle : csh , insn : * const cs_insn , group_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."] pub fn cs_reg_read (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."] pub fn cs_reg_write (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."] pub fn cs_op_count (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."] pub fn cs_op_index (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint , position : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } # [doc = " Type of array to keep the list of registers"] pub type cs_regs = [u16 ; 64usize] ; unsafe extern "C" { # [doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_regs_access (handle : csh , insn : * const cs_insn , regs_read : * mut u16 , regs_read_count : * mut u8 , regs_write : * mut u16 , regs_write_count : * mut u8) -> cs_err ; } pub type __builtin_va_list = [__va_list_tag ; 1usize] ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __va_list_tag { pub gp_offset : :: std :: os :: raw :: c_uint , pub fp_offset : :: std :: os :: raw :: c_uint , pub overflow_arg_area : * mut :: std :: os :: raw :: c_void , pub reg_save_area : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __va_list_tag"] [:: std :: mem :: size_of :: < __va_list_tag > () - 24usize] ; ["Alignment of __va_list_tag"] [:: std :: mem :: align_of :: < __va_list_tag > () - 8usize] ; ["Offset of field: __va_list_tag::gp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , gp_offset) - 0usize] ; ["Offset of field: __va_list_tag::fp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , fp_offset) - 4usize] ; ["Offset of field: __va_list_tag::overflow_arg_area"] [:: std :: mem :: offset_of ! (__va_list_tag , overflow_arg_area) - 8usize] ; ["Offset of field: __va_list_tag::reg_save_area"] [:: std :: mem :: offset_of ! (__va_list_tag , reg_save_area) - 16usize] ; } ;
[INFO] [stdout]   |
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: unnecessary transmute
[INFO] [stdout]  --> /opt/rustwide/target/debug/build/falcon_capstone/f982cdb455ed4cf6/out/bindings.rs:3:80329
[INFO] [stdout]   |
[INFO] [stdout] 3 | ...: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; self . _bitfield_1 . set (0usize , 24u8 , val ...
[INFO] [stdout]   |                                                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout] help: replace this with
[INFO] [stdout]   |
[INFO] [stdout] 3 - # [repr (C)] # [derive (Copy , Clone , Debug , Default , Eq , Hash , Ord , PartialEq , PartialOrd)] pub struct __BindgenBitfieldUnit < Storage > { storage : Storage , } impl < Storage > __BindgenBitfieldUnit < Storage > { # [inline] pub const fn new (storage : Storage) -> Self { Self { storage } } } impl < Storage > __BindgenBitfieldUnit < Storage > where Storage : AsRef < [u8] > + AsMut < [u8] >, { # [inline] fn extract_bit (byte : u8 , index : usize) -> bool { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; byte & mask == mask } # [inline] pub fn get_bit (& self , index : usize) -> bool { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = self . storage . as_ref () [byte_index] ; Self :: extract_bit (byte , index) } # [inline] pub unsafe fn raw_get_bit (this : * const Self , index : usize) -> bool { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { * (core :: ptr :: addr_of ! ((* this) . storage) as * const u8) . offset (byte_index as isize) } ; Self :: extract_bit (byte , index) } # [inline] fn change_bit (byte : u8 , index : usize , val : bool) -> u8 { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; if val { byte | mask } else { byte & ! mask } } # [inline] pub fn set_bit (& mut self , index : usize , val : bool) { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = & mut self . storage . as_mut () [byte_index] ; * byte = Self :: change_bit (* byte , index , val) ; } # [inline] pub unsafe fn raw_set_bit (this : * mut Self , index : usize , val : bool) { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { (core :: ptr :: addr_of_mut ! ((* this) . storage) as * mut u8) . offset (byte_index as isize) } ; unsafe { * byte = Self :: change_bit (* byte , index , val) } ; } # [inline] pub fn get (& self , bit_offset : usize , bit_width : u8) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if self . get_bit (i + bit_offset) { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub unsafe fn raw_get (this : * const Self , bit_offset : usize , bit_width : u8 ,) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if unsafe { Self :: raw_get_bit (this , i + bit_offset) } { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub fn set (& mut self , bit_offset : usize , bit_width : u8 , val : u64) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; self . set_bit (index + bit_offset , val_bit_is_set) ; } } # [inline] pub unsafe fn raw_set (this : * mut Self , bit_offset : usize , bit_width : u8 , val : u64 ,) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; unsafe { Self :: raw_set_bit (this , index + bit_offset , val_bit_is_set) } ; } } } # [derive (PartialEq , Copy , Clone , Hash , Debug , Default)] # [repr (C)] pub struct __BindgenComplex < T > { pub re : T , pub im : T } pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __GLIBC_USE_ISOC2Y : u32 = 0 ; pub const __GLIBC_USE_ISOC23 : u32 = 0 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 202405 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_XOPEN2K24 : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const __TIMESIZE : u32 = 64 ; pub const __USE_TIME_BITS64 : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_GETS : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_SCANF : u32 = 0 ; pub const __GLIBC_USE_C23_STRTOL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_60559_BFP__ : u32 = 201404 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_IEC_60559_COMPLEX__ : u32 = 201404 ; pub const __STDC_ISO_10646__ : u32 = 201706 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 43 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __glibc_c99_flexarr_available : u32 = 1 ; pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI : u32 = 0 ; pub const __HAVE_GENERIC_SELECTION : u32 = 1 ; pub const __GLIBC_USE_LIB_EXT2 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_TYPES_EXT : u32 = 0 ; pub const _STDLIB_H : u32 = 1 ; pub const WNOHANG : u32 = 1 ; pub const WUNTRACED : u32 = 2 ; pub const WSTOPPED : u32 = 2 ; pub const WEXITED : u32 = 4 ; pub const WCONTINUED : u32 = 8 ; pub const WNOWAIT : u32 = 16777216 ; pub const __WNOTHREAD : u32 = 536870912 ; pub const __WALL : u32 = 1073741824 ; pub const __WCLONE : u32 = 2147483648 ; pub const __W_CONTINUED : u32 = 65535 ; pub const __WCOREFLAG : u32 = 128 ; pub const __HAVE_FLOAT128 : u32 = 1 ; pub const __HAVE_DISTINCT_FLOAT128 : u32 = 1 ; pub const __HAVE_FLOAT64X : u32 = 1 ; pub const __HAVE_FLOAT64X_LONG_DOUBLE : u32 = 1 ; pub const __HAVE_FLOAT16 : u32 = 0 ; pub const __HAVE_FLOAT32 : u32 = 1 ; pub const __HAVE_FLOAT64 : u32 = 1 ; pub const __HAVE_FLOAT32X : u32 = 1 ; pub const __HAVE_FLOAT128X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT16 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT128X : u32 = 0 ; pub const __HAVE_FLOATN_NOT_TYPEDEF : u32 = 0 ; pub const __ldiv_t_defined : u32 = 1 ; pub const __lldiv_t_defined : u32 = 1 ; pub const RAND_MAX : u32 = 2147483647 ; pub const EXIT_FAILURE : u32 = 1 ; pub const EXIT_SUCCESS : u32 = 0 ; pub const _SYS_TYPES_H : u32 = 1 ; pub const _BITS_TYPES_H : u32 = 1 ; pub const _BITS_TYPESIZES_H : u32 = 1 ; pub const __OFF_T_MATCHES_OFF64_T : u32 = 1 ; pub const __INO_T_MATCHES_INO64_T : u32 = 1 ; pub const __RLIM_T_MATCHES_RLIM64_T : u32 = 1 ; pub const __STATFS_MATCHES_STATFS64 : u32 = 1 ; pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 : u32 = 1 ; pub const __FD_SETSIZE : u32 = 1024 ; pub const _BITS_TIME64_H : u32 = 1 ; pub const __clock_t_defined : u32 = 1 ; pub const __clockid_t_defined : u32 = 1 ; pub const __time_t_defined : u32 = 1 ; pub const __timer_t_defined : u32 = 1 ; pub const _BITS_STDINT_INTN_H : u32 = 1 ; pub const __BIT_TYPES_DEFINED__ : u32 = 1 ; pub const _ENDIAN_H : u32 = 1 ; pub const _BITS_ENDIAN_H : u32 = 1 ; pub const __LITTLE_ENDIAN : u32 = 1234 ; pub const __BIG_ENDIAN : u32 = 4321 ; pub const __PDP_ENDIAN : u32 = 3412 ; pub const _BITS_ENDIANNESS_H : u32 = 1 ; pub const __BYTE_ORDER : u32 = 1234 ; pub const __FLOAT_WORD_ORDER : u32 = 1234 ; pub const LITTLE_ENDIAN : u32 = 1234 ; pub const BIG_ENDIAN : u32 = 4321 ; pub const PDP_ENDIAN : u32 = 3412 ; pub const BYTE_ORDER : u32 = 1234 ; pub const _BITS_BYTESWAP_H : u32 = 1 ; pub const _BITS_UINTN_IDENTITY_H : u32 = 1 ; pub const _SYS_SELECT_H : u32 = 1 ; pub const __sigset_t_defined : u32 = 1 ; pub const __timeval_defined : u32 = 1 ; pub const _STRUCT_TIMESPEC : u32 = 1 ; pub const FD_SETSIZE : u32 = 1024 ; pub const _BITS_PTHREADTYPES_COMMON_H : u32 = 1 ; pub const _THREAD_SHARED_TYPES_H : u32 = 1 ; pub const _BITS_PTHREADTYPES_ARCH_H : u32 = 1 ; pub const __SIZEOF_PTHREAD_MUTEX_T : u32 = 40 ; pub const __SIZEOF_PTHREAD_ATTR_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_RWLOCK_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_BARRIER_T : u32 = 32 ; pub const __SIZEOF_PTHREAD_MUTEXATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_COND_T : u32 = 48 ; pub const __SIZEOF_PTHREAD_CONDATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_RWLOCKATTR_T : u32 = 8 ; pub const __SIZEOF_PTHREAD_BARRIERATTR_T : u32 = 4 ; pub const _THREAD_MUTEX_INTERNAL_H : u32 = 1 ; pub const __PTHREAD_MUTEX_HAVE_PREV : u32 = 1 ; pub const __have_pthread_attr_t : u32 = 1 ; pub const _ALLOCA_H : u32 = 1 ; pub const _STDIO_H : u32 = 1 ; pub const _____fpos_t_defined : u32 = 1 ; pub const ____mbstate_t_defined : u32 = 1 ; pub const _____fpos64_t_defined : u32 = 1 ; pub const ____FILE_defined : u32 = 1 ; pub const __FILE_defined : u32 = 1 ; pub const __struct_FILE_defined : u32 = 1 ; pub const _IO_EOF_SEEN : u32 = 16 ; pub const _IO_ERR_SEEN : u32 = 32 ; pub const _IO_USER_LOCK : u32 = 32768 ; pub const __cookie_io_functions_t_defined : u32 = 1 ; pub const _IOFBF : u32 = 0 ; pub const _IOLBF : u32 = 1 ; pub const _IONBF : u32 = 2 ; pub const BUFSIZ : u32 = 8192 ; pub const EOF : i32 = - 1 ; pub const SEEK_SET : u32 = 0 ; pub const SEEK_CUR : u32 = 1 ; pub const SEEK_END : u32 = 2 ; pub const P_tmpdir : & [u8 ; 5] = b"/tmp\0" ; pub const L_tmpnam : u32 = 20 ; pub const TMP_MAX : u32 = 238328 ; pub const _BITS_STDIO_LIM_H : u32 = 1 ; pub const FILENAME_MAX : u32 = 4096 ; pub const L_ctermid : u32 = 9 ; pub const FOPEN_MAX : u32 = 16 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const _INTTYPES_H : u32 = 1 ; pub const _STDINT_H : u32 = 1 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const _BITS_STDINT_UINTN_H : u32 = 1 ; pub const _BITS_STDINT_LEAST_H : u32 = 1 ; pub const INT8_MIN : i32 = - 128 ; pub const INT16_MIN : i32 = - 32768 ; pub const INT32_MIN : i32 = - 2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = - 128 ; pub const INT_LEAST16_MIN : i32 = - 32768 ; pub const INT_LEAST32_MIN : i32 = - 2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = - 128 ; pub const INT_FAST16_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST32_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = - 1 ; pub const UINT_FAST32_MAX : i32 = - 1 ; pub const INTPTR_MIN : i64 = - 9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = - 1 ; pub const PTRDIFF_MIN : i64 = - 9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = - 2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = - 1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const ____gwchar_t_defined : u32 = 1 ; pub const __PRI64_PREFIX : & [u8 ; 2] = b"l\0" ; pub const __PRIPTR_PREFIX : & [u8 ; 2] = b"l\0" ; pub const PRId8 : & [u8 ; 4] = b"hhd\0" ; pub const PRId16 : & [u8 ; 3] = b"hd\0" ; pub const PRId32 : & [u8 ; 2] = b"d\0" ; pub const PRId64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const PRIdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const PRIdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIi8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIi16 : & [u8 ; 3] = b"hi\0" ; pub const PRIi32 : & [u8 ; 2] = b"i\0" ; pub const PRIi64 : & [u8 ; 3] = b"li\0" ; pub const PRIiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const PRIiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const PRIiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiFAST16 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST32 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIo8 : & [u8 ; 4] = b"hho\0" ; pub const PRIo16 : & [u8 ; 3] = b"ho\0" ; pub const PRIo32 : & [u8 ; 2] = b"o\0" ; pub const PRIo64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const PRIoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const PRIoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIu8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIu16 : & [u8 ; 3] = b"hu\0" ; pub const PRIu32 : & [u8 ; 2] = b"u\0" ; pub const PRIu64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const PRIuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const PRIuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIx8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIx16 : & [u8 ; 3] = b"hx\0" ; pub const PRIx32 : & [u8 ; 2] = b"x\0" ; pub const PRIx64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const PRIxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const PRIxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIX8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIX16 : & [u8 ; 3] = b"hX\0" ; pub const PRIX32 : & [u8 ; 2] = b"X\0" ; pub const PRIX64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXLEAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXLEAST16 : & [u8 ; 3] = b"hX\0" ; pub const PRIXLEAST32 : & [u8 ; 2] = b"X\0" ; pub const PRIXLEAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXFAST16 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST32 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIdMAX : & [u8 ; 3] = b"ld\0" ; pub const PRIiMAX : & [u8 ; 3] = b"li\0" ; pub const PRIoMAX : & [u8 ; 3] = b"lo\0" ; pub const PRIuMAX : & [u8 ; 3] = b"lu\0" ; pub const PRIxMAX : & [u8 ; 3] = b"lx\0" ; pub const PRIXMAX : & [u8 ; 3] = b"lX\0" ; pub const PRIdPTR : & [u8 ; 3] = b"ld\0" ; pub const PRIiPTR : & [u8 ; 3] = b"li\0" ; pub const PRIoPTR : & [u8 ; 3] = b"lo\0" ; pub const PRIuPTR : & [u8 ; 3] = b"lu\0" ; pub const PRIxPTR : & [u8 ; 3] = b"lx\0" ; pub const PRIXPTR : & [u8 ; 3] = b"lX\0" ; pub const SCNd8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNd16 : & [u8 ; 3] = b"hd\0" ; pub const SCNd32 : & [u8 ; 2] = b"d\0" ; pub const SCNd64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const SCNdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const SCNdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNi8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNi16 : & [u8 ; 3] = b"hi\0" ; pub const SCNi32 : & [u8 ; 2] = b"i\0" ; pub const SCNi64 : & [u8 ; 3] = b"li\0" ; pub const SCNiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const SCNiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const SCNiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiFAST16 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST32 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNu8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNu16 : & [u8 ; 3] = b"hu\0" ; pub const SCNu32 : & [u8 ; 2] = b"u\0" ; pub const SCNu64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const SCNuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const SCNuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNo8 : & [u8 ; 4] = b"hho\0" ; pub const SCNo16 : & [u8 ; 3] = b"ho\0" ; pub const SCNo32 : & [u8 ; 2] = b"o\0" ; pub const SCNo64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const SCNoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const SCNoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNx8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNx16 : & [u8 ; 3] = b"hx\0" ; pub const SCNx32 : & [u8 ; 2] = b"x\0" ; pub const SCNx64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const SCNxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const SCNxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNdMAX : & [u8 ; 3] = b"ld\0" ; pub const SCNiMAX : & [u8 ; 3] = b"li\0" ; pub const SCNoMAX : & [u8 ; 3] = b"lo\0" ; pub const SCNuMAX : & [u8 ; 3] = b"lu\0" ; pub const SCNxMAX : & [u8 ; 3] = b"lx\0" ; pub const SCNdPTR : & [u8 ; 3] = b"ld\0" ; pub const SCNiPTR : & [u8 ; 3] = b"li\0" ; pub const SCNoPTR : & [u8 ; 3] = b"lo\0" ; pub const SCNuPTR : & [u8 ; 3] = b"lu\0" ; pub const SCNxPTR : & [u8 ; 3] = b"lx\0" ; pub const CS_API_MAJOR : u32 = 5 ; pub const CS_API_MINOR : u32 = 0 ; pub const CS_NEXT_VERSION : u32 = 5 ; pub const CS_VERSION_MAJOR : u32 = 5 ; pub const CS_VERSION_MINOR : u32 = 0 ; pub const CS_VERSION_EXTRA : u32 = 7 ; pub const CS_MNEMONIC_SIZE : u32 = 32 ; pub const M68K_OPERAND_COUNT : u32 = 4 ; pub const X86_EFLAGS_MODIFY_AF : u32 = 1 ; pub const X86_EFLAGS_MODIFY_CF : u32 = 2 ; pub const X86_EFLAGS_MODIFY_SF : u32 = 4 ; pub const X86_EFLAGS_MODIFY_ZF : u32 = 8 ; pub const X86_EFLAGS_MODIFY_PF : u32 = 16 ; pub const X86_EFLAGS_MODIFY_OF : u32 = 32 ; pub const X86_EFLAGS_MODIFY_TF : u32 = 64 ; pub const X86_EFLAGS_MODIFY_IF : u32 = 128 ; pub const X86_EFLAGS_MODIFY_DF : u32 = 256 ; pub const X86_EFLAGS_MODIFY_NT : u32 = 512 ; pub const X86_EFLAGS_MODIFY_RF : u32 = 1024 ; pub const X86_EFLAGS_PRIOR_OF : u32 = 2048 ; pub const X86_EFLAGS_PRIOR_SF : u32 = 4096 ; pub const X86_EFLAGS_PRIOR_ZF : u32 = 8192 ; pub const X86_EFLAGS_PRIOR_AF : u32 = 16384 ; pub const X86_EFLAGS_PRIOR_PF : u32 = 32768 ; pub const X86_EFLAGS_PRIOR_CF : u32 = 65536 ; pub const X86_EFLAGS_PRIOR_TF : u32 = 131072 ; pub const X86_EFLAGS_PRIOR_IF : u32 = 262144 ; pub const X86_EFLAGS_PRIOR_DF : u32 = 524288 ; pub const X86_EFLAGS_PRIOR_NT : u32 = 1048576 ; pub const X86_EFLAGS_RESET_OF : u32 = 2097152 ; pub const X86_EFLAGS_RESET_CF : u32 = 4194304 ; pub const X86_EFLAGS_RESET_DF : u32 = 8388608 ; pub const X86_EFLAGS_RESET_IF : u32 = 16777216 ; pub const X86_EFLAGS_RESET_SF : u32 = 33554432 ; pub const X86_EFLAGS_RESET_AF : u32 = 67108864 ; pub const X86_EFLAGS_RESET_TF : u32 = 134217728 ; pub const X86_EFLAGS_RESET_NT : u32 = 268435456 ; pub const X86_EFLAGS_RESET_PF : u32 = 536870912 ; pub const X86_EFLAGS_SET_CF : u32 = 1073741824 ; pub const X86_EFLAGS_SET_DF : u32 = 2147483648 ; pub const X86_EFLAGS_SET_IF : u64 = 4294967296 ; pub const X86_EFLAGS_TEST_OF : u64 = 8589934592 ; pub const X86_EFLAGS_TEST_SF : u64 = 17179869184 ; pub const X86_EFLAGS_TEST_ZF : u64 = 34359738368 ; pub const X86_EFLAGS_TEST_PF : u64 = 68719476736 ; pub const X86_EFLAGS_TEST_CF : u64 = 137438953472 ; pub const X86_EFLAGS_TEST_NT : u64 = 274877906944 ; pub const X86_EFLAGS_TEST_DF : u64 = 549755813888 ; pub const X86_EFLAGS_UNDEFINED_OF : u64 = 1099511627776 ; pub const X86_EFLAGS_UNDEFINED_SF : u64 = 2199023255552 ; pub const X86_EFLAGS_UNDEFINED_ZF : u64 = 4398046511104 ; pub const X86_EFLAGS_UNDEFINED_PF : u64 = 8796093022208 ; pub const X86_EFLAGS_UNDEFINED_AF : u64 = 17592186044416 ; pub const X86_EFLAGS_UNDEFINED_CF : u64 = 35184372088832 ; pub const X86_EFLAGS_RESET_RF : u64 = 70368744177664 ; pub const X86_EFLAGS_TEST_RF : u64 = 140737488355328 ; pub const X86_EFLAGS_TEST_IF : u64 = 281474976710656 ; pub const X86_EFLAGS_TEST_TF : u64 = 562949953421312 ; pub const X86_EFLAGS_TEST_AF : u64 = 1125899906842624 ; pub const X86_EFLAGS_RESET_ZF : u64 = 2251799813685248 ; pub const X86_EFLAGS_SET_OF : u64 = 4503599627370496 ; pub const X86_EFLAGS_SET_SF : u64 = 9007199254740992 ; pub const X86_EFLAGS_SET_ZF : u64 = 18014398509481984 ; pub const X86_EFLAGS_SET_AF : u64 = 36028797018963968 ; pub const X86_EFLAGS_SET_PF : u64 = 72057594037927936 ; pub const X86_EFLAGS_RESET_0F : u64 = 144115188075855872 ; pub const X86_EFLAGS_RESET_AC : u64 = 288230376151711744 ; pub const X86_FPU_FLAGS_MODIFY_C0 : u32 = 1 ; pub const X86_FPU_FLAGS_MODIFY_C1 : u32 = 2 ; pub const X86_FPU_FLAGS_MODIFY_C2 : u32 = 4 ; pub const X86_FPU_FLAGS_MODIFY_C3 : u32 = 8 ; pub const X86_FPU_FLAGS_RESET_C0 : u32 = 16 ; pub const X86_FPU_FLAGS_RESET_C1 : u32 = 32 ; pub const X86_FPU_FLAGS_RESET_C2 : u32 = 64 ; pub const X86_FPU_FLAGS_RESET_C3 : u32 = 128 ; pub const X86_FPU_FLAGS_SET_C0 : u32 = 256 ; pub const X86_FPU_FLAGS_SET_C1 : u32 = 512 ; pub const X86_FPU_FLAGS_SET_C2 : u32 = 1024 ; pub const X86_FPU_FLAGS_SET_C3 : u32 = 2048 ; pub const X86_FPU_FLAGS_UNDEFINED_C0 : u32 = 4096 ; pub const X86_FPU_FLAGS_UNDEFINED_C1 : u32 = 8192 ; pub const X86_FPU_FLAGS_UNDEFINED_C2 : u32 = 16384 ; pub const X86_FPU_FLAGS_UNDEFINED_C3 : u32 = 32768 ; pub const X86_FPU_FLAGS_TEST_C0 : u32 = 65536 ; pub const X86_FPU_FLAGS_TEST_C1 : u32 = 131072 ; pub const X86_FPU_FLAGS_TEST_C2 : u32 = 262144 ; pub const X86_FPU_FLAGS_TEST_C3 : u32 = 524288 ; pub const M680X_OPERAND_COUNT : u32 = 9 ; pub const M680X_OFFSET_NONE : u32 = 0 ; pub const M680X_OFFSET_BITS_5 : u32 = 5 ; pub const M680X_OFFSET_BITS_8 : u32 = 8 ; pub const M680X_OFFSET_BITS_9 : u32 = 9 ; pub const M680X_OFFSET_BITS_16 : u32 = 16 ; pub const M680X_IDX_INDIRECT : u32 = 1 ; pub const M680X_IDX_NO_COMMA : u32 = 2 ; pub const M680X_IDX_POST_INC_DEC : u32 = 4 ; pub const M680X_FIRST_OP_IN_MNEM : u32 = 1 ; pub const M680X_SECOND_OP_IN_MNEM : u32 = 2 ; pub const TRICORE_OP_COUNT : u32 = 8 ; pub const MAX_IMPL_W_REGS : u32 = 20 ; pub const MAX_IMPL_R_REGS : u32 = 20 ; pub const MAX_NUM_GROUPS : u32 = 8 ; pub type __gnuc_va_list = __builtin_va_list ; pub type va_list = __builtin_va_list ; pub type wchar_t = :: std :: os :: raw :: c_int ; pub type __cfloat128 = __BindgenComplex < u128 > ; pub type _Float128 = u128 ; pub type _Float32 = f32 ; pub type _Float64 = f64 ; pub type _Float32x = f64 ; pub type _Float64x = u128 ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct div_t { pub quot : :: std :: os :: raw :: c_int , pub rem : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of div_t"] [:: std :: mem :: size_of :: < div_t > () - 8usize] ; ["Alignment of div_t"] [:: std :: mem :: align_of :: < div_t > () - 4usize] ; ["Offset of field: div_t::quot"] [:: std :: mem :: offset_of ! (div_t , quot) - 0usize] ; ["Offset of field: div_t::rem"] [:: std :: mem :: offset_of ! (div_t , rem) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ldiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ldiv_t"] [:: std :: mem :: size_of :: < ldiv_t > () - 16usize] ; ["Alignment of ldiv_t"] [:: std :: mem :: align_of :: < ldiv_t > () - 8usize] ; ["Offset of field: ldiv_t::quot"] [:: std :: mem :: offset_of ! (ldiv_t , quot) - 0usize] ; ["Offset of field: ldiv_t::rem"] [:: std :: mem :: offset_of ! (ldiv_t , rem) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct lldiv_t { pub quot : :: std :: os :: raw :: c_longlong , pub rem : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of lldiv_t"] [:: std :: mem :: size_of :: < lldiv_t > () - 16usize] ; ["Alignment of lldiv_t"] [:: std :: mem :: align_of :: < lldiv_t > () - 8usize] ; ["Offset of field: lldiv_t::quot"] [:: std :: mem :: offset_of ! (lldiv_t , quot) - 0usize] ; ["Offset of field: lldiv_t::rem"] [:: std :: mem :: offset_of ! (lldiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn __ctype_get_mb_cur_max () -> usize ; } unsafe extern "C" { pub fn atof (__nptr : * const :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn atoi (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn atol (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn atoll (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtod (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn strtof (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f32 ; } unsafe extern "C" { pub fn strtold (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> u128 ; } unsafe extern "C" { pub fn strtol (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn strtoul (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn strtoq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtouq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn strtoll (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtoull (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn l64a (__n : :: std :: os :: raw :: c_long) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn a64l (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } pub type __u_char = :: std :: os :: raw :: c_uchar ; pub type __u_short = :: std :: os :: raw :: c_ushort ; pub type __u_int = :: std :: os :: raw :: c_uint ; pub type __u_long = :: std :: os :: raw :: c_ulong ; pub type __int8_t = :: std :: os :: raw :: c_schar ; pub type __uint8_t = :: std :: os :: raw :: c_uchar ; pub type __int16_t = :: std :: os :: raw :: c_short ; pub type __uint16_t = :: std :: os :: raw :: c_ushort ; pub type __int32_t = :: std :: os :: raw :: c_int ; pub type __uint32_t = :: std :: os :: raw :: c_uint ; pub type __int64_t = :: std :: os :: raw :: c_long ; pub type __uint64_t = :: std :: os :: raw :: c_ulong ; pub type __int_least8_t = __int8_t ; pub type __uint_least8_t = __uint8_t ; pub type __int_least16_t = __int16_t ; pub type __uint_least16_t = __uint16_t ; pub type __int_least32_t = __int32_t ; pub type __uint_least32_t = __uint32_t ; pub type __int_least64_t = __int64_t ; pub type __uint_least64_t = __uint64_t ; pub type __quad_t = :: std :: os :: raw :: c_long ; pub type __u_quad_t = :: std :: os :: raw :: c_ulong ; pub type __intmax_t = :: std :: os :: raw :: c_long ; pub type __uintmax_t = :: std :: os :: raw :: c_ulong ; pub type __dev_t = :: std :: os :: raw :: c_ulong ; pub type __uid_t = :: std :: os :: raw :: c_uint ; pub type __gid_t = :: std :: os :: raw :: c_uint ; pub type __ino_t = :: std :: os :: raw :: c_ulong ; pub type __ino64_t = :: std :: os :: raw :: c_ulong ; pub type __mode_t = :: std :: os :: raw :: c_uint ; pub type __nlink_t = :: std :: os :: raw :: c_ulong ; pub type __off_t = :: std :: os :: raw :: c_long ; pub type __off64_t = :: std :: os :: raw :: c_long ; pub type __pid_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __fsid_t { pub __val : [:: std :: os :: raw :: c_int ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __fsid_t"] [:: std :: mem :: size_of :: < __fsid_t > () - 8usize] ; ["Alignment of __fsid_t"] [:: std :: mem :: align_of :: < __fsid_t > () - 4usize] ; ["Offset of field: __fsid_t::__val"] [:: std :: mem :: offset_of ! (__fsid_t , __val) - 0usize] ; } ; pub type __clock_t = :: std :: os :: raw :: c_long ; pub type __rlim_t = :: std :: os :: raw :: c_ulong ; pub type __rlim64_t = :: std :: os :: raw :: c_ulong ; pub type __id_t = :: std :: os :: raw :: c_uint ; pub type __time_t = :: std :: os :: raw :: c_long ; pub type __useconds_t = :: std :: os :: raw :: c_uint ; pub type __suseconds_t = :: std :: os :: raw :: c_long ; pub type __suseconds64_t = :: std :: os :: raw :: c_long ; pub type __daddr_t = :: std :: os :: raw :: c_int ; pub type __key_t = :: std :: os :: raw :: c_int ; pub type __clockid_t = :: std :: os :: raw :: c_int ; pub type __timer_t = * mut :: std :: os :: raw :: c_void ; pub type __blksize_t = :: std :: os :: raw :: c_long ; pub type __blkcnt_t = :: std :: os :: raw :: c_long ; pub type __blkcnt64_t = :: std :: os :: raw :: c_long ; pub type __fsblkcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsblkcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsword_t = :: std :: os :: raw :: c_long ; pub type __ssize_t = :: std :: os :: raw :: c_long ; pub type __syscall_slong_t = :: std :: os :: raw :: c_long ; pub type __syscall_ulong_t = :: std :: os :: raw :: c_ulong ; pub type __loff_t = __off64_t ; pub type __caddr_t = * mut :: std :: os :: raw :: c_char ; pub type __intptr_t = :: std :: os :: raw :: c_long ; pub type __socklen_t = :: std :: os :: raw :: c_uint ; pub type __sig_atomic_t = :: std :: os :: raw :: c_int ; pub type u_char = __u_char ; pub type u_short = __u_short ; pub type u_int = __u_int ; pub type u_long = __u_long ; pub type quad_t = __quad_t ; pub type u_quad_t = __u_quad_t ; pub type fsid_t = __fsid_t ; pub type loff_t = __loff_t ; pub type ino_t = __ino_t ; pub type dev_t = __dev_t ; pub type gid_t = __gid_t ; pub type mode_t = __mode_t ; pub type nlink_t = __nlink_t ; pub type uid_t = __uid_t ; pub type off_t = __off_t ; pub type pid_t = __pid_t ; pub type id_t = __id_t ; pub type daddr_t = __daddr_t ; pub type caddr_t = __caddr_t ; pub type key_t = __key_t ; pub type clock_t = __clock_t ; pub type clockid_t = __clockid_t ; pub type time_t = __time_t ; pub type timer_t = __timer_t ; pub type ulong = :: std :: os :: raw :: c_ulong ; pub type ushort = :: std :: os :: raw :: c_ushort ; pub type uint = :: std :: os :: raw :: c_uint ; pub type u_int8_t = __uint8_t ; pub type u_int16_t = __uint16_t ; pub type u_int32_t = __uint32_t ; pub type u_int64_t = __uint64_t ; pub type register_t = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __sigset_t { pub __val : [:: std :: os :: raw :: c_ulong ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __sigset_t"] [:: std :: mem :: size_of :: < __sigset_t > () - 128usize] ; ["Alignment of __sigset_t"] [:: std :: mem :: align_of :: < __sigset_t > () - 8usize] ; ["Offset of field: __sigset_t::__val"] [:: std :: mem :: offset_of ! (__sigset_t , __val) - 0usize] ; } ; pub type sigset_t = __sigset_t ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timeval { pub tv_sec : __time_t , pub tv_usec : __suseconds_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timeval"] [:: std :: mem :: size_of :: < timeval > () - 16usize] ; ["Alignment of timeval"] [:: std :: mem :: align_of :: < timeval > () - 8usize] ; ["Offset of field: timeval::tv_sec"] [:: std :: mem :: offset_of ! (timeval , tv_sec) - 0usize] ; ["Offset of field: timeval::tv_usec"] [:: std :: mem :: offset_of ! (timeval , tv_usec) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timespec { pub tv_sec : __time_t , pub tv_nsec : __syscall_slong_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timespec"] [:: std :: mem :: size_of :: < timespec > () - 16usize] ; ["Alignment of timespec"] [:: std :: mem :: align_of :: < timespec > () - 8usize] ; ["Offset of field: timespec::tv_sec"] [:: std :: mem :: offset_of ! (timespec , tv_sec) - 0usize] ; ["Offset of field: timespec::tv_nsec"] [:: std :: mem :: offset_of ! (timespec , tv_nsec) - 8usize] ; } ; pub type suseconds_t = __suseconds_t ; pub type __fd_mask = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct fd_set { pub __fds_bits : [__fd_mask ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of fd_set"] [:: std :: mem :: size_of :: < fd_set > () - 128usize] ; ["Alignment of fd_set"] [:: std :: mem :: align_of :: < fd_set > () - 8usize] ; ["Offset of field: fd_set::__fds_bits"] [:: std :: mem :: offset_of ! (fd_set , __fds_bits) - 0usize] ; } ; pub type fd_mask = __fd_mask ; unsafe extern "C" { pub fn select (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * mut timeval) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pselect (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * const timespec , __sigmask : * const __sigset_t) -> :: std :: os :: raw :: c_int ; } pub type blksize_t = __blksize_t ; pub type blkcnt_t = __blkcnt_t ; pub type fsblkcnt_t = __fsblkcnt_t ; pub type fsfilcnt_t = __fsfilcnt_t ; # [repr (C)] # [derive (Copy , Clone)] pub union __atomic_wide_counter { pub __value64 : :: std :: os :: raw :: c_ulonglong , pub __value32 : __atomic_wide_counter__bindgen_ty_1 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __atomic_wide_counter__bindgen_ty_1 { pub __low : :: std :: os :: raw :: c_uint , pub __high : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: size_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 8usize] ; ["Alignment of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: align_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__low"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __low) - 0usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__high"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __high) - 4usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter"] [:: std :: mem :: size_of :: < __atomic_wide_counter > () - 8usize] ; ["Alignment of __atomic_wide_counter"] [:: std :: mem :: align_of :: < __atomic_wide_counter > () - 8usize] ; ["Offset of field: __atomic_wide_counter::__value64"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value64) - 0usize] ; ["Offset of field: __atomic_wide_counter::__value32"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value32) - 0usize] ; } ; impl :: std :: fmt :: Debug for __atomic_wide_counter { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__atomic_wide_counter {{ union }}") } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_list { pub __prev : * mut __pthread_internal_list , pub __next : * mut __pthread_internal_list , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_list"] [:: std :: mem :: size_of :: < __pthread_internal_list > () - 16usize] ; ["Alignment of __pthread_internal_list"] [:: std :: mem :: align_of :: < __pthread_internal_list > () - 8usize] ; ["Offset of field: __pthread_internal_list::__prev"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __prev) - 0usize] ; ["Offset of field: __pthread_internal_list::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __next) - 8usize] ; } ; pub type __pthread_list_t = __pthread_internal_list ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_slist { pub __next : * mut __pthread_internal_slist , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_slist"] [:: std :: mem :: size_of :: < __pthread_internal_slist > () - 8usize] ; ["Alignment of __pthread_internal_slist"] [:: std :: mem :: align_of :: < __pthread_internal_slist > () - 8usize] ; ["Offset of field: __pthread_internal_slist::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_slist , __next) - 0usize] ; } ; pub type __pthread_slist_t = __pthread_internal_slist ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_mutex_s { pub __lock : :: std :: os :: raw :: c_int , pub __count : :: std :: os :: raw :: c_uint , pub __owner : :: std :: os :: raw :: c_int , pub __nusers : :: std :: os :: raw :: c_uint , pub __kind : :: std :: os :: raw :: c_int , pub __spins : :: std :: os :: raw :: c_short , pub __unused : :: std :: os :: raw :: c_short , pub __list : __pthread_list_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_mutex_s"] [:: std :: mem :: size_of :: < __pthread_mutex_s > () - 40usize] ; ["Alignment of __pthread_mutex_s"] [:: std :: mem :: align_of :: < __pthread_mutex_s > () - 8usize] ; ["Offset of field: __pthread_mutex_s::__lock"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __lock) - 0usize] ; ["Offset of field: __pthread_mutex_s::__count"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __count) - 4usize] ; ["Offset of field: __pthread_mutex_s::__owner"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __owner) - 8usize] ; ["Offset of field: __pthread_mutex_s::__nusers"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __nusers) - 12usize] ; ["Offset of field: __pthread_mutex_s::__kind"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __kind) - 16usize] ; ["Offset of field: __pthread_mutex_s::__spins"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __spins) - 20usize] ; ["Offset of field: __pthread_mutex_s::__unused"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __unused) - 22usize] ; ["Offset of field: __pthread_mutex_s::__list"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __list) - 24usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_rwlock_arch_t { pub __readers : :: std :: os :: raw :: c_uint , pub __writers : :: std :: os :: raw :: c_uint , pub __wrphase_futex : :: std :: os :: raw :: c_uint , pub __writers_futex : :: std :: os :: raw :: c_uint , pub __pad3 : :: std :: os :: raw :: c_uint , pub __pad4 : :: std :: os :: raw :: c_uint , pub __cur_writer : :: std :: os :: raw :: c_int , pub __shared : :: std :: os :: raw :: c_int , pub __pad1 : :: std :: os :: raw :: c_ulong , pub __pad2 : :: std :: os :: raw :: c_ulong , pub __flags : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_rwlock_arch_t"] [:: std :: mem :: size_of :: < __pthread_rwlock_arch_t > () - 56usize] ; ["Alignment of __pthread_rwlock_arch_t"] [:: std :: mem :: align_of :: < __pthread_rwlock_arch_t > () - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__readers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __readers) - 0usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers) - 4usize] ; ["Offset of field: __pthread_rwlock_arch_t::__wrphase_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __wrphase_futex) - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers_futex) - 12usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad3"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad3) - 16usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad4"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad4) - 20usize] ; ["Offset of field: __pthread_rwlock_arch_t::__cur_writer"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __cur_writer) - 24usize] ; ["Offset of field: __pthread_rwlock_arch_t::__shared"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __shared) - 28usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad1"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad1) - 32usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad2"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad2) - 40usize] ; ["Offset of field: __pthread_rwlock_arch_t::__flags"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __flags) - 48usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct __pthread_cond_s { pub __wseq : __atomic_wide_counter , pub __g1_start : __atomic_wide_counter , pub __g_size : [:: std :: os :: raw :: c_uint ; 2usize] , pub __g1_orig_size : :: std :: os :: raw :: c_uint , pub __wrefs : :: std :: os :: raw :: c_uint , pub __g_signals : [:: std :: os :: raw :: c_uint ; 2usize] , pub __unused_initialized_1 : :: std :: os :: raw :: c_uint , pub __unused_initialized_2 : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_cond_s"] [:: std :: mem :: size_of :: < __pthread_cond_s > () - 48usize] ; ["Alignment of __pthread_cond_s"] [:: std :: mem :: align_of :: < __pthread_cond_s > () - 8usize] ; ["Offset of field: __pthread_cond_s::__wseq"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wseq) - 0usize] ; ["Offset of field: __pthread_cond_s::__g1_start"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_start) - 8usize] ; ["Offset of field: __pthread_cond_s::__g_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_size) - 16usize] ; ["Offset of field: __pthread_cond_s::__g1_orig_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_orig_size) - 24usize] ; ["Offset of field: __pthread_cond_s::__wrefs"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wrefs) - 28usize] ; ["Offset of field: __pthread_cond_s::__g_signals"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_signals) - 32usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_1"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_1) - 40usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_2"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_2) - 44usize] ; } ; impl :: std :: fmt :: Debug for __pthread_cond_s { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__pthread_cond_s {{ __wseq: {:?}, __g1_start: {:?}, __g_size: {:?}, __g1_orig_size: {:?}, __wrefs: {:?}, __g_signals: {:?}, __unused_initialized_1: {:?}, __unused_initialized_2: {:?} }}" , self . __wseq , self . __g1_start , self . __g_size , self . __g1_orig_size , self . __wrefs , self . __g_signals , self . __unused_initialized_1 , self . __unused_initialized_2) } } pub type __tss_t = :: std :: os :: raw :: c_uint ; pub type __thrd_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __once_flag { pub __data : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __once_flag"] [:: std :: mem :: size_of :: < __once_flag > () - 4usize] ; ["Alignment of __once_flag"] [:: std :: mem :: align_of :: < __once_flag > () - 4usize] ; ["Offset of field: __once_flag::__data"] [:: std :: mem :: offset_of ! (__once_flag , __data) - 0usize] ; } ; pub type pthread_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutexattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutexattr_t"] [:: std :: mem :: size_of :: < pthread_mutexattr_t > () - 4usize] ; ["Alignment of pthread_mutexattr_t"] [:: std :: mem :: align_of :: < pthread_mutexattr_t > () - 4usize] ; ["Offset of field: pthread_mutexattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __size) - 0usize] ; ["Offset of field: pthread_mutexattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutexattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutexattr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_condattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_condattr_t"] [:: std :: mem :: size_of :: < pthread_condattr_t > () - 4usize] ; ["Alignment of pthread_condattr_t"] [:: std :: mem :: align_of :: < pthread_condattr_t > () - 4usize] ; ["Offset of field: pthread_condattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __size) - 0usize] ; ["Offset of field: pthread_condattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_condattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_condattr_t {{ union }}") } } pub type pthread_key_t = :: std :: os :: raw :: c_uint ; pub type pthread_once_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_attr_t { pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_attr_t"] [:: std :: mem :: size_of :: < pthread_attr_t > () - 56usize] ; ["Alignment of pthread_attr_t"] [:: std :: mem :: align_of :: < pthread_attr_t > () - 8usize] ; ["Offset of field: pthread_attr_t::__size"] [:: std :: mem :: offset_of ! (pthread_attr_t , __size) - 0usize] ; ["Offset of field: pthread_attr_t::__align"] [:: std :: mem :: offset_of ! (pthread_attr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_attr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_attr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutex_t { pub __data : __pthread_mutex_s , pub __size : [:: std :: os :: raw :: c_char ; 40usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutex_t"] [:: std :: mem :: size_of :: < pthread_mutex_t > () - 40usize] ; ["Alignment of pthread_mutex_t"] [:: std :: mem :: align_of :: < pthread_mutex_t > () - 8usize] ; ["Offset of field: pthread_mutex_t::__data"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __data) - 0usize] ; ["Offset of field: pthread_mutex_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __size) - 0usize] ; ["Offset of field: pthread_mutex_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutex_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutex_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_cond_t { pub __data : __pthread_cond_s , pub __size : [:: std :: os :: raw :: c_char ; 48usize] , pub __align : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_cond_t"] [:: std :: mem :: size_of :: < pthread_cond_t > () - 48usize] ; ["Alignment of pthread_cond_t"] [:: std :: mem :: align_of :: < pthread_cond_t > () - 8usize] ; ["Offset of field: pthread_cond_t::__data"] [:: std :: mem :: offset_of ! (pthread_cond_t , __data) - 0usize] ; ["Offset of field: pthread_cond_t::__size"] [:: std :: mem :: offset_of ! (pthread_cond_t , __size) - 0usize] ; ["Offset of field: pthread_cond_t::__align"] [:: std :: mem :: offset_of ! (pthread_cond_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_cond_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_cond_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlock_t { pub __data : __pthread_rwlock_arch_t , pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlock_t"] [:: std :: mem :: size_of :: < pthread_rwlock_t > () - 56usize] ; ["Alignment of pthread_rwlock_t"] [:: std :: mem :: align_of :: < pthread_rwlock_t > () - 8usize] ; ["Offset of field: pthread_rwlock_t::__data"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __data) - 0usize] ; ["Offset of field: pthread_rwlock_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __size) - 0usize] ; ["Offset of field: pthread_rwlock_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlock_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlock_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlockattr_t { pub __size : [:: std :: os :: raw :: c_char ; 8usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlockattr_t"] [:: std :: mem :: size_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Alignment of pthread_rwlockattr_t"] [:: std :: mem :: align_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Offset of field: pthread_rwlockattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __size) - 0usize] ; ["Offset of field: pthread_rwlockattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlockattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlockattr_t {{ union }}") } } pub type pthread_spinlock_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrier_t { pub __size : [:: std :: os :: raw :: c_char ; 32usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrier_t"] [:: std :: mem :: size_of :: < pthread_barrier_t > () - 32usize] ; ["Alignment of pthread_barrier_t"] [:: std :: mem :: align_of :: < pthread_barrier_t > () - 8usize] ; ["Offset of field: pthread_barrier_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __size) - 0usize] ; ["Offset of field: pthread_barrier_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrier_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrier_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrierattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrierattr_t"] [:: std :: mem :: size_of :: < pthread_barrierattr_t > () - 4usize] ; ["Alignment of pthread_barrierattr_t"] [:: std :: mem :: align_of :: < pthread_barrierattr_t > () - 4usize] ; ["Offset of field: pthread_barrierattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __size) - 0usize] ; ["Offset of field: pthread_barrierattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrierattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrierattr_t {{ union }}") } } unsafe extern "C" { pub fn random () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srandom (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn initstate (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn setstate (__statebuf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct random_data { pub fptr : * mut i32 , pub rptr : * mut i32 , pub state : * mut i32 , pub rand_type : :: std :: os :: raw :: c_int , pub rand_deg : :: std :: os :: raw :: c_int , pub rand_sep : :: std :: os :: raw :: c_int , pub end_ptr : * mut i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of random_data"] [:: std :: mem :: size_of :: < random_data > () - 48usize] ; ["Alignment of random_data"] [:: std :: mem :: align_of :: < random_data > () - 8usize] ; ["Offset of field: random_data::fptr"] [:: std :: mem :: offset_of ! (random_data , fptr) - 0usize] ; ["Offset of field: random_data::rptr"] [:: std :: mem :: offset_of ! (random_data , rptr) - 8usize] ; ["Offset of field: random_data::state"] [:: std :: mem :: offset_of ! (random_data , state) - 16usize] ; ["Offset of field: random_data::rand_type"] [:: std :: mem :: offset_of ! (random_data , rand_type) - 24usize] ; ["Offset of field: random_data::rand_deg"] [:: std :: mem :: offset_of ! (random_data , rand_deg) - 28usize] ; ["Offset of field: random_data::rand_sep"] [:: std :: mem :: offset_of ! (random_data , rand_sep) - 32usize] ; ["Offset of field: random_data::end_ptr"] [:: std :: mem :: offset_of ! (random_data , end_ptr) - 40usize] ; } ; unsafe extern "C" { pub fn random_r (__buf : * mut random_data , __result : * mut i32) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srandom_r (__seed : :: std :: os :: raw :: c_uint , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn initstate_r (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setstate_r (__statebuf : * mut :: std :: os :: raw :: c_char , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rand () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn rand_r (__seed : * mut :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn drand48 () -> f64 ; } unsafe extern "C" { pub fn erand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> f64 ; } unsafe extern "C" { pub fn lrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn nrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn mrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn jrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srand48 (__seedval : :: std :: os :: raw :: c_long) ; } unsafe extern "C" { pub fn seed48 (__seed16v : * mut :: std :: os :: raw :: c_ushort) -> * mut :: std :: os :: raw :: c_ushort ; } unsafe extern "C" { pub fn lcong48 (__param : * mut :: std :: os :: raw :: c_ushort) ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct drand48_data { pub __x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __old_x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __c : :: std :: os :: raw :: c_ushort , pub __init : :: std :: os :: raw :: c_ushort , pub __a : :: std :: os :: raw :: c_ulonglong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of drand48_data"] [:: std :: mem :: size_of :: < drand48_data > () - 24usize] ; ["Alignment of drand48_data"] [:: std :: mem :: align_of :: < drand48_data > () - 8usize] ; ["Offset of field: drand48_data::__x"] [:: std :: mem :: offset_of ! (drand48_data , __x) - 0usize] ; ["Offset of field: drand48_data::__old_x"] [:: std :: mem :: offset_of ! (drand48_data , __old_x) - 6usize] ; ["Offset of field: drand48_data::__c"] [:: std :: mem :: offset_of ! (drand48_data , __c) - 12usize] ; ["Offset of field: drand48_data::__init"] [:: std :: mem :: offset_of ! (drand48_data , __init) - 14usize] ; ["Offset of field: drand48_data::__a"] [:: std :: mem :: offset_of ! (drand48_data , __a) - 16usize] ; } ; unsafe extern "C" { pub fn drand48_r (__buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn erand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn nrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn jrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand48_r (__seedval : :: std :: os :: raw :: c_long , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn seed48_r (__seed16v : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lcong48_r (__param : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn arc4random () -> __uint32_t ; } unsafe extern "C" { pub fn arc4random_buf (__buf : * mut :: std :: os :: raw :: c_void , __size : usize) ; } unsafe extern "C" { pub fn arc4random_uniform (__upper_bound : __uint32_t) -> __uint32_t ; } unsafe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn calloc (__nmemb : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn free (__ptr : * mut :: std :: os :: raw :: c_void) ; } unsafe extern "C" { pub fn reallocarray (__ptr : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn alloca (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn valloc (__size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn posix_memalign (__memptr : * mut * mut :: std :: os :: raw :: c_void , __alignment : usize , __size : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn aligned_alloc (__alignment : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn abort () -> ! ; } unsafe extern "C" { pub fn atexit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn at_quick_exit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn on_exit (__func : :: std :: option :: Option < unsafe extern "C" fn (__status : :: std :: os :: raw :: c_int , __arg : * mut :: std :: os :: raw :: c_void) > , __arg : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn quick_exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn _Exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn getenv (__name : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn putenv (__string : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setenv (__name : * const :: std :: os :: raw :: c_char , __value : * const :: std :: os :: raw :: c_char , __replace : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn unsetenv (__name : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearenv () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mktemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn mkstemp (__template : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkstemps (__template : * mut :: std :: os :: raw :: c_char , __suffixlen : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkdtemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn system (__command : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn realpath (__name : * const :: std :: os :: raw :: c_char , __resolved : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } pub type __compar_fn_t = :: std :: option :: Option < unsafe extern "C" fn (arg1 : * const :: std :: os :: raw :: c_void , arg2 : * const :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; unsafe extern "C" { pub fn bsearch (__key : * const :: std :: os :: raw :: c_void , __base : * const :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn qsort (__base : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) ; } unsafe extern "C" { pub fn abs (__x : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn labs (__x : :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn llabs (__x : :: std :: os :: raw :: c_longlong) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn div (__numer : :: std :: os :: raw :: c_int , __denom : :: std :: os :: raw :: c_int) -> div_t ; } unsafe extern "C" { pub fn ldiv (__numer : :: std :: os :: raw :: c_long , __denom : :: std :: os :: raw :: c_long) -> ldiv_t ; } unsafe extern "C" { pub fn lldiv (__numer : :: std :: os :: raw :: c_longlong , __denom : :: std :: os :: raw :: c_longlong) -> lldiv_t ; } unsafe extern "C" { pub fn ecvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn gcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qecvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qfcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qgcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn ecvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fcvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qecvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qfcvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mblen (__s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbtowc (__pwc : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn wctomb (__s : * mut :: std :: os :: raw :: c_char , __wchar : wchar_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbstowcs (__pwcs : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> usize ; } unsafe extern "C" { pub fn wcstombs (__s : * mut :: std :: os :: raw :: c_char , __pwcs : * const wchar_t , __n : usize) -> usize ; } unsafe extern "C" { pub fn rpmatch (__response : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getsubopt (__optionp : * mut * mut :: std :: os :: raw :: c_char , __tokens : * const * mut :: std :: os :: raw :: c_char , __valuep : * mut * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getloadavg (__loadavg : * mut f64 , __nelem : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } # [repr (C)] # [derive (Copy , Clone)] pub struct __mbstate_t { pub __count : :: std :: os :: raw :: c_int , pub __value : __mbstate_t__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union __mbstate_t__bindgen_ty_1 { pub __wch : :: std :: os :: raw :: c_uint , pub __wchb : [:: std :: os :: raw :: c_char ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: size_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Alignment of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: align_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wch"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wch) - 0usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wchb"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wchb) - 0usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t"] [:: std :: mem :: size_of :: < __mbstate_t > () - 8usize] ; ["Alignment of __mbstate_t"] [:: std :: mem :: align_of :: < __mbstate_t > () - 4usize] ; ["Offset of field: __mbstate_t::__count"] [:: std :: mem :: offset_of ! (__mbstate_t , __count) - 0usize] ; ["Offset of field: __mbstate_t::__value"] [:: std :: mem :: offset_of ! (__mbstate_t , __value) - 4usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t {{ __count: {:?}, __value: {:?} }}" , self . __count , self . __value) } } # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos_t { pub __pos : __off_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos_t"] [:: std :: mem :: size_of :: < _G_fpos_t > () - 16usize] ; ["Alignment of _G_fpos_t"] [:: std :: mem :: align_of :: < _G_fpos_t > () - 8usize] ; ["Offset of field: _G_fpos_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos_t , __pos) - 0usize] ; ["Offset of field: _G_fpos_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos_t = _G_fpos_t ; # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos64_t { pub __pos : __off64_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos64_t"] [:: std :: mem :: size_of :: < _G_fpos64_t > () - 16usize] ; ["Alignment of _G_fpos64_t"] [:: std :: mem :: align_of :: < _G_fpos64_t > () - 8usize] ; ["Offset of field: _G_fpos64_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __pos) - 0usize] ; ["Offset of field: _G_fpos64_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos64_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos64_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos64_t = _G_fpos64_t ; pub type __FILE = _IO_FILE ; pub type FILE = _IO_FILE ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_marker { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_codecvt { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_wide_data { _unused : [u8 ; 0] , } pub type _IO_lock_t = :: std :: os :: raw :: c_void ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_FILE { pub _flags : :: std :: os :: raw :: c_int , pub _IO_read_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_read_end : * mut :: std :: os :: raw :: c_char , pub _IO_read_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_write_end : * mut :: std :: os :: raw :: c_char , pub _IO_buf_base : * mut :: std :: os :: raw :: c_char , pub _IO_buf_end : * mut :: std :: os :: raw :: c_char , pub _IO_save_base : * mut :: std :: os :: raw :: c_char , pub _IO_backup_base : * mut :: std :: os :: raw :: c_char , pub _IO_save_end : * mut :: std :: os :: raw :: c_char , pub _markers : * mut _IO_marker , pub _chain : * mut _IO_FILE , pub _fileno : :: std :: os :: raw :: c_int , pub _bitfield_align_1 : [u32 ; 0] , pub _bitfield_1 : __BindgenBitfieldUnit < [u8 ; 3usize] > , pub _short_backupbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _old_offset : __off_t , pub _cur_column : :: std :: os :: raw :: c_ushort , pub _vtable_offset : :: std :: os :: raw :: c_schar , pub _shortbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _lock : * mut _IO_lock_t , pub _offset : __off64_t , pub _codecvt : * mut _IO_codecvt , pub _wide_data : * mut _IO_wide_data , pub _freeres_list : * mut _IO_FILE , pub _freeres_buf : * mut :: std :: os :: raw :: c_void , pub _prevchain : * mut * mut _IO_FILE , pub _mode : :: std :: os :: raw :: c_int , pub _unused3 : :: std :: os :: raw :: c_int , pub _total_written : __uint64_t , pub _unused2 : [:: std :: os :: raw :: c_char ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_FILE"] [:: std :: mem :: size_of :: < _IO_FILE > () - 216usize] ; ["Alignment of _IO_FILE"] [:: std :: mem :: align_of :: < _IO_FILE > () - 8usize] ; ["Offset of field: _IO_FILE::_flags"] [:: std :: mem :: offset_of ! (_IO_FILE , _flags) - 0usize] ; ["Offset of field: _IO_FILE::_IO_read_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_ptr) - 8usize] ; ["Offset of field: _IO_FILE::_IO_read_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_end) - 16usize] ; ["Offset of field: _IO_FILE::_IO_read_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_base) - 24usize] ; ["Offset of field: _IO_FILE::_IO_write_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_base) - 32usize] ; ["Offset of field: _IO_FILE::_IO_write_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_ptr) - 40usize] ; ["Offset of field: _IO_FILE::_IO_write_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_end) - 48usize] ; ["Offset of field: _IO_FILE::_IO_buf_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_base) - 56usize] ; ["Offset of field: _IO_FILE::_IO_buf_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_end) - 64usize] ; ["Offset of field: _IO_FILE::_IO_save_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_base) - 72usize] ; ["Offset of field: _IO_FILE::_IO_backup_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_backup_base) - 80usize] ; ["Offset of field: _IO_FILE::_IO_save_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_end) - 88usize] ; ["Offset of field: _IO_FILE::_markers"] [:: std :: mem :: offset_of ! (_IO_FILE , _markers) - 96usize] ; ["Offset of field: _IO_FILE::_chain"] [:: std :: mem :: offset_of ! (_IO_FILE , _chain) - 104usize] ; ["Offset of field: _IO_FILE::_fileno"] [:: std :: mem :: offset_of ! (_IO_FILE , _fileno) - 112usize] ; ["Offset of field: _IO_FILE::_short_backupbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _short_backupbuf) - 119usize] ; ["Offset of field: _IO_FILE::_old_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _old_offset) - 120usize] ; ["Offset of field: _IO_FILE::_cur_column"] [:: std :: mem :: offset_of ! (_IO_FILE , _cur_column) - 128usize] ; ["Offset of field: _IO_FILE::_vtable_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _vtable_offset) - 130usize] ; ["Offset of field: _IO_FILE::_shortbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _shortbuf) - 131usize] ; ["Offset of field: _IO_FILE::_lock"] [:: std :: mem :: offset_of ! (_IO_FILE , _lock) - 136usize] ; ["Offset of field: _IO_FILE::_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _offset) - 144usize] ; ["Offset of field: _IO_FILE::_codecvt"] [:: std :: mem :: offset_of ! (_IO_FILE , _codecvt) - 152usize] ; ["Offset of field: _IO_FILE::_wide_data"] [:: std :: mem :: offset_of ! (_IO_FILE , _wide_data) - 160usize] ; ["Offset of field: _IO_FILE::_freeres_list"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_list) - 168usize] ; ["Offset of field: _IO_FILE::_freeres_buf"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_buf) - 176usize] ; ["Offset of field: _IO_FILE::_prevchain"] [:: std :: mem :: offset_of ! (_IO_FILE , _prevchain) - 184usize] ; ["Offset of field: _IO_FILE::_mode"] [:: std :: mem :: offset_of ! (_IO_FILE , _mode) - 192usize] ; ["Offset of field: _IO_FILE::_unused3"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused3) - 196usize] ; ["Offset of field: _IO_FILE::_total_written"] [:: std :: mem :: offset_of ! (_IO_FILE , _total_written) - 200usize] ; ["Offset of field: _IO_FILE::_unused2"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused2) - 208usize] ; } ; impl _IO_FILE { # [inline] pub fn _flags2 (& self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set__flags2 (& mut self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; self . _bitfield_1 . set (0usize , 24u8 , val as u64) } } # [inline] pub unsafe fn _flags2_raw (this : * const Self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } } # [inline] pub unsafe fn set__flags2_raw (this : * mut Self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_set (:: std :: ptr :: addr_of_mut ! ((* this) . _bitfield_1) , 0usize , 24u8 , val as u64 ,) } } # [inline] pub fn new_bitfield_1 (_flags2 : :: std :: os :: raw :: c_int) -> __BindgenBitfieldUnit < [u8 ; 3usize] > { let mut __bindgen_bitfield_unit : __BindgenBitfieldUnit < [u8 ; 3usize] > = Default :: default () ; __bindgen_bitfield_unit . set (0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_unit } } pub type cookie_read_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * mut :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_write_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * const :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_seek_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __pos : * mut __off64_t , __w : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int > ; pub type cookie_close_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_cookie_io_functions_t { pub read : cookie_read_function_t , pub write : cookie_write_function_t , pub seek : cookie_seek_function_t , pub close : cookie_close_function_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_cookie_io_functions_t"] [:: std :: mem :: size_of :: < _IO_cookie_io_functions_t > () - 32usize] ; ["Alignment of _IO_cookie_io_functions_t"] [:: std :: mem :: align_of :: < _IO_cookie_io_functions_t > () - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::read"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , read) - 0usize] ; ["Offset of field: _IO_cookie_io_functions_t::write"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , write) - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::seek"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , seek) - 16usize] ; ["Offset of field: _IO_cookie_io_functions_t::close"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , close) - 24usize] ; } ; pub type cookie_io_functions_t = _IO_cookie_io_functions_t ; pub type fpos_t = __fpos_t ; unsafe extern "C" { pub static mut stdin : * mut FILE ; } unsafe extern "C" { pub static mut stdout : * mut FILE ; } unsafe extern "C" { pub static mut stderr : * mut FILE ; } unsafe extern "C" { pub fn remove (__filename : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rename (__old : * const :: std :: os :: raw :: c_char , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn renameat (__oldfd : :: std :: os :: raw :: c_int , __old : * const :: std :: os :: raw :: c_char , __newfd : :: std :: os :: raw :: c_int , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn tmpfile () -> * mut FILE ; } unsafe extern "C" { pub fn tmpnam (arg1 : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tmpnam_r (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tempnam (__dir : * const :: std :: os :: raw :: c_char , __pfx : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fflush (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fflush_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn freopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> * mut FILE ; } unsafe extern "C" { pub fn fdopen (__fd : :: std :: os :: raw :: c_int , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn fopencookie (__magic_cookie : * mut :: std :: os :: raw :: c_void , __modes : * const :: std :: os :: raw :: c_char , __io_funcs : cookie_io_functions_t) -> * mut FILE ; } unsafe extern "C" { pub fn fmemopen (__s : * mut :: std :: os :: raw :: c_void , __len : usize , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn open_memstream (__bufloc : * mut * mut :: std :: os :: raw :: c_char , __sizeloc : * mut usize) -> * mut FILE ; } unsafe extern "C" { pub fn setbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn setvbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __modes : :: std :: os :: raw :: c_int , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setbuffer (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __size : usize) ; } unsafe extern "C" { pub fn setlinebuf (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fprintf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn printf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfprintf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vprintf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn snprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsnprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vasprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __f : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vdprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn dprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fscanf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn scanf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_fscanf"] pub fn fscanf1 (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_scanf"] pub fn scanf1 (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_sscanf"] pub fn sscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfscanf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vscanf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vfscanf"] pub fn vfscanf1 (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vscanf"] pub fn vscanf1 (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vsscanf"] pub fn vsscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar_unlocked () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar_unlocked (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getw (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putw (__w : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgets (__s : * mut :: std :: os :: raw :: c_char , __n : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn __getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getline (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn fputs (__s : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn puts (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ungetc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fread (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __stream : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fwrite (__ptr : * const :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __s : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fread_unlocked (__ptr : * mut :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fwrite_unlocked (__ptr : * const :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fseek (__stream : * mut FILE , __off : :: std :: os :: raw :: c_long , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftell (__stream : * mut FILE) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn rewind (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fseeko (__stream : * mut FILE , __off : __off_t , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftello (__stream : * mut FILE) -> __off_t ; } unsafe extern "C" { pub fn fgetpos (__stream : * mut FILE , __pos : * mut fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fsetpos (__stream : * mut FILE , __pos : * const fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr_unlocked (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn perror (__s : * const :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn fileno (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fileno_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn popen (__command : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn ctermid (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn flockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn ftrylockfile (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn funlockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn __uflow (arg1 : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __overflow (arg1 : * mut FILE , arg2 : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } pub type int_least8_t = __int_least8_t ; pub type int_least16_t = __int_least16_t ; pub type int_least32_t = __int_least32_t ; pub type int_least64_t = __int_least64_t ; pub type uint_least8_t = __uint_least8_t ; pub type uint_least16_t = __uint_least16_t ; pub type uint_least32_t = __uint_least32_t ; pub type uint_least64_t = __uint_least64_t ; pub type int_fast8_t = :: std :: os :: raw :: c_schar ; pub type int_fast16_t = :: std :: os :: raw :: c_long ; pub type int_fast32_t = :: std :: os :: raw :: c_long ; pub type int_fast64_t = :: std :: os :: raw :: c_long ; pub type uint_fast8_t = :: std :: os :: raw :: c_uchar ; pub type uint_fast16_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast32_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast64_t = :: std :: os :: raw :: c_ulong ; pub type intmax_t = __intmax_t ; pub type uintmax_t = __uintmax_t ; pub type __gwchar_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct imaxdiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of imaxdiv_t"] [:: std :: mem :: size_of :: < imaxdiv_t > () - 16usize] ; ["Alignment of imaxdiv_t"] [:: std :: mem :: align_of :: < imaxdiv_t > () - 8usize] ; ["Offset of field: imaxdiv_t::quot"] [:: std :: mem :: offset_of ! (imaxdiv_t , quot) - 0usize] ; ["Offset of field: imaxdiv_t::rem"] [:: std :: mem :: offset_of ! (imaxdiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn imaxabs (__n : intmax_t) -> intmax_t ; } unsafe extern "C" { pub fn imaxdiv (__numer : intmax_t , __denom : intmax_t) -> imaxdiv_t ; } unsafe extern "C" { pub fn strtoimax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn strtoumax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } unsafe extern "C" { pub fn wcstoimax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn wcstoumax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } pub type csh = usize ; # [repr (u32)] # [doc = " Architecture type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_arch { # [doc = "< ARM architecture (including Thumb, Thumb-2)"] CS_ARCH_ARM = 0 , # [doc = "< ARM-64, also called AArch64"] CS_ARCH_ARM64 = 1 , # [doc = "< Mips architecture"] CS_ARCH_MIPS = 2 , # [doc = "< X86 architecture (including x86 & x86-64)"] CS_ARCH_X86 = 3 , # [doc = "< PowerPC architecture"] CS_ARCH_PPC = 4 , # [doc = "< Sparc architecture"] CS_ARCH_SPARC = 5 , # [doc = "< SystemZ architecture"] CS_ARCH_SYSZ = 6 , # [doc = "< XCore architecture"] CS_ARCH_XCORE = 7 , # [doc = "< 68K architecture"] CS_ARCH_M68K = 8 , # [doc = "< TMS320C64x architecture"] CS_ARCH_TMS320C64X = 9 , # [doc = "< 680X architecture"] CS_ARCH_M680X = 10 , # [doc = "< Ethereum architecture"] CS_ARCH_EVM = 11 , # [doc = "< MOS65XX architecture (including MOS6502)"] CS_ARCH_MOS65XX = 12 , # [doc = "< WebAssembly architecture"] CS_ARCH_WASM = 13 , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] CS_ARCH_BPF = 14 , # [doc = "< RISCV architecture"] CS_ARCH_RISCV = 15 , # [doc = "< SH architecture"] CS_ARCH_SH = 16 , # [doc = "< TriCore architecture"] CS_ARCH_TRICORE = 17 , CS_ARCH_MAX = 18 , CS_ARCH_ALL = 65535 , } # [doc = "< little-endian mode (default mode)"] pub const cs_mode_CS_MODE_LITTLE_ENDIAN : cs_mode = 0 ; # [doc = "< 32-bit ARM"] pub const cs_mode_CS_MODE_ARM : cs_mode = 0 ; # [doc = "< 16-bit mode (X86)"] pub const cs_mode_CS_MODE_16 : cs_mode = 2 ; # [doc = "< 32-bit mode (X86)"] pub const cs_mode_CS_MODE_32 : cs_mode = 4 ; # [doc = "< 64-bit mode (X86, PPC)"] pub const cs_mode_CS_MODE_64 : cs_mode = 8 ; # [doc = "< ARM's Thumb mode, including Thumb-2"] pub const cs_mode_CS_MODE_THUMB : cs_mode = 16 ; # [doc = "< ARM's Cortex-M series"] pub const cs_mode_CS_MODE_MCLASS : cs_mode = 32 ; # [doc = "< ARMv8 A32 encodings for ARM"] pub const cs_mode_CS_MODE_V8 : cs_mode = 64 ; # [doc = "< MicroMips mode (MIPS)"] pub const cs_mode_CS_MODE_MICRO : cs_mode = 16 ; # [doc = "< Mips III ISA"] pub const cs_mode_CS_MODE_MIPS3 : cs_mode = 32 ; # [doc = "< Mips32r6 ISA"] pub const cs_mode_CS_MODE_MIPS32R6 : cs_mode = 64 ; # [doc = "< Mips II ISA"] pub const cs_mode_CS_MODE_MIPS2 : cs_mode = 128 ; # [doc = "< SparcV9 mode (Sparc)"] pub const cs_mode_CS_MODE_V9 : cs_mode = 16 ; # [doc = "< Quad Processing eXtensions mode (PPC)"] pub const cs_mode_CS_MODE_QPX : cs_mode = 16 ; # [doc = "< Signal Processing Engine mode (PPC)"] pub const cs_mode_CS_MODE_SPE : cs_mode = 32 ; # [doc = "< Book-E mode (PPC)"] pub const cs_mode_CS_MODE_BOOKE : cs_mode = 64 ; # [doc = "< Paired-singles mode (PPC)"] pub const cs_mode_CS_MODE_PS : cs_mode = 128 ; # [doc = "< M68K 68000 mode"] pub const cs_mode_CS_MODE_M68K_000 : cs_mode = 2 ; # [doc = "< M68K 68010 mode"] pub const cs_mode_CS_MODE_M68K_010 : cs_mode = 4 ; # [doc = "< M68K 68020 mode"] pub const cs_mode_CS_MODE_M68K_020 : cs_mode = 8 ; # [doc = "< M68K 68030 mode"] pub const cs_mode_CS_MODE_M68K_030 : cs_mode = 16 ; # [doc = "< M68K 68040 mode"] pub const cs_mode_CS_MODE_M68K_040 : cs_mode = 32 ; # [doc = "< M68K 68060 mode"] pub const cs_mode_CS_MODE_M68K_060 : cs_mode = 64 ; # [doc = "< big-endian mode"] pub const cs_mode_CS_MODE_BIG_ENDIAN : cs_mode = 2147483648 ; # [doc = "< Mips32 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS32 : cs_mode = 4 ; # [doc = "< Mips64 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS64 : cs_mode = 8 ; # [doc = "< M680X Hitachi 6301,6303 mode"] pub const cs_mode_CS_MODE_M680X_6301 : cs_mode = 2 ; # [doc = "< M680X Hitachi 6309 mode"] pub const cs_mode_CS_MODE_M680X_6309 : cs_mode = 4 ; # [doc = "< M680X Motorola 6800,6802 mode"] pub const cs_mode_CS_MODE_M680X_6800 : cs_mode = 8 ; # [doc = "< M680X Motorola 6801,6803 mode"] pub const cs_mode_CS_MODE_M680X_6801 : cs_mode = 16 ; # [doc = "< M680X Motorola/Freescale 6805 mode"] pub const cs_mode_CS_MODE_M680X_6805 : cs_mode = 32 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"] pub const cs_mode_CS_MODE_M680X_6808 : cs_mode = 64 ; # [doc = "< M680X Motorola 6809 mode"] pub const cs_mode_CS_MODE_M680X_6809 : cs_mode = 128 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"] pub const cs_mode_CS_MODE_M680X_6811 : cs_mode = 256 ; # [doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"] pub const cs_mode_CS_MODE_M680X_CPU12 : cs_mode = 512 ; # [doc = "< M680X Freescale/NXP HCS08 mode"] pub const cs_mode_CS_MODE_M680X_HCS08 : cs_mode = 1024 ; # [doc = "< Classic BPF mode (default)"] pub const cs_mode_CS_MODE_BPF_CLASSIC : cs_mode = 0 ; # [doc = "< Extended BPF mode"] pub const cs_mode_CS_MODE_BPF_EXTENDED : cs_mode = 1 ; # [doc = "< RISCV RV32G"] pub const cs_mode_CS_MODE_RISCV32 : cs_mode = 1 ; # [doc = "< RISCV RV64G"] pub const cs_mode_CS_MODE_RISCV64 : cs_mode = 2 ; # [doc = "< RISCV compressed instructure mode"] pub const cs_mode_CS_MODE_RISCVC : cs_mode = 4 ; # [doc = "< MOS65XXX MOS 6502"] pub const cs_mode_CS_MODE_MOS65XX_6502 : cs_mode = 2 ; # [doc = "< MOS65XXX WDC 65c02"] pub const cs_mode_CS_MODE_MOS65XX_65C02 : cs_mode = 4 ; # [doc = "< MOS65XXX WDC W65c02"] pub const cs_mode_CS_MODE_MOS65XX_W65C02 : cs_mode = 8 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m/x"] pub const cs_mode_CS_MODE_MOS65XX_65816 : cs_mode = 16 ; # [doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_M : cs_mode = 32 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_X : cs_mode = 64 ; pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_MX : cs_mode = 96 ; # [doc = "< SH2"] pub const cs_mode_CS_MODE_SH2 : cs_mode = 2 ; # [doc = "< SH2A"] pub const cs_mode_CS_MODE_SH2A : cs_mode = 4 ; # [doc = "< SH3"] pub const cs_mode_CS_MODE_SH3 : cs_mode = 8 ; # [doc = "< SH4"] pub const cs_mode_CS_MODE_SH4 : cs_mode = 16 ; # [doc = "< SH4A"] pub const cs_mode_CS_MODE_SH4A : cs_mode = 32 ; # [doc = "< w/ FPU"] pub const cs_mode_CS_MODE_SHFPU : cs_mode = 64 ; # [doc = "< w/ DSP"] pub const cs_mode_CS_MODE_SHDSP : cs_mode = 128 ; # [doc = "< Tricore 1.1"] pub const cs_mode_CS_MODE_TRICORE_110 : cs_mode = 2 ; # [doc = "< Tricore 1.2"] pub const cs_mode_CS_MODE_TRICORE_120 : cs_mode = 4 ; # [doc = "< Tricore 1.3"] pub const cs_mode_CS_MODE_TRICORE_130 : cs_mode = 8 ; # [doc = "< Tricore 1.3.1"] pub const cs_mode_CS_MODE_TRICORE_131 : cs_mode = 16 ; # [doc = "< Tricore 1.6"] pub const cs_mode_CS_MODE_TRICORE_160 : cs_mode = 32 ; # [doc = "< Tricore 1.6.1"] pub const cs_mode_CS_MODE_TRICORE_161 : cs_mode = 64 ; # [doc = "< Tricore 1.6.2"] pub const cs_mode_CS_MODE_TRICORE_162 : cs_mode = 128 ; # [doc = " Mode type"] pub type cs_mode = :: std :: os :: raw :: c_uint ; pub type cs_malloc_t = :: std :: option :: Option < unsafe extern "C" fn (size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_calloc_t = :: std :: option :: Option < unsafe extern "C" fn (nmemb : usize , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_realloc_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_free_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void) > ; pub type cs_vsnprintf_t = :: std :: option :: Option < unsafe extern "C" fn (str_ : * mut :: std :: os :: raw :: c_char , size : usize , format : * const :: std :: os :: raw :: c_char , ap : * mut __va_list_tag) -> :: std :: os :: raw :: c_int > ; # [doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mem { pub malloc : cs_malloc_t , pub calloc : cs_calloc_t , pub realloc : cs_realloc_t , pub free : cs_free_t , pub vsnprintf : cs_vsnprintf_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mem"] [:: std :: mem :: size_of :: < cs_opt_mem > () - 40usize] ; ["Alignment of cs_opt_mem"] [:: std :: mem :: align_of :: < cs_opt_mem > () - 8usize] ; ["Offset of field: cs_opt_mem::malloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , malloc) - 0usize] ; ["Offset of field: cs_opt_mem::calloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , calloc) - 8usize] ; ["Offset of field: cs_opt_mem::realloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , realloc) - 16usize] ; ["Offset of field: cs_opt_mem::free"] [:: std :: mem :: offset_of ! (cs_opt_mem , free) - 24usize] ; ["Offset of field: cs_opt_mem::vsnprintf"] [:: std :: mem :: offset_of ! (cs_opt_mem , vsnprintf) - 32usize] ; } ; # [doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mnem { # [doc = " ID of instruction to be customized."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Customized instruction mnemonic."] pub mnemonic : * const :: std :: os :: raw :: c_char , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mnem"] [:: std :: mem :: size_of :: < cs_opt_mnem > () - 16usize] ; ["Alignment of cs_opt_mnem"] [:: std :: mem :: align_of :: < cs_opt_mnem > () - 8usize] ; ["Offset of field: cs_opt_mnem::id"] [:: std :: mem :: offset_of ! (cs_opt_mnem , id) - 0usize] ; ["Offset of field: cs_opt_mnem::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_mnem , mnemonic) - 8usize] ; } ; # [repr (u32)] # [doc = " Runtime option for the disassembled engine"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_type { # [doc = "< No option specified"] CS_OPT_INVALID = 0 , # [doc = "< Assembly output syntax"] CS_OPT_SYNTAX = 1 , # [doc = "< Break down instruction structure into details"] CS_OPT_DETAIL = 2 , # [doc = "< Change engine's mode at run-time"] CS_OPT_MODE = 3 , # [doc = "< User-defined dynamic memory related functions"] CS_OPT_MEM = 4 , # [doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."] CS_OPT_SKIPDATA = 5 , # [doc = "< Setup user-defined function for SKIPDATA option"] CS_OPT_SKIPDATA_SETUP = 6 , # [doc = "< Customize instruction mnemonic"] CS_OPT_MNEMONIC = 7 , # [doc = "< print immediate operands in unsigned form"] CS_OPT_UNSIGNED = 8 , # [doc = "< ARM, prints branch immediates without offset."] CS_OPT_NO_BRANCH_OFFSET = 9 , } impl cs_opt_value { pub const CS_OPT_SYNTAX_DEFAULT : cs_opt_value = cs_opt_value :: CS_OPT_OFF ; } impl cs_opt_value { pub const CS_OPT_SYNTAX_NOREGNAME : cs_opt_value = cs_opt_value :: CS_OPT_ON ; } # [repr (u32)] # [doc = " Runtime option value (associated with option type above)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_value { # [doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."] CS_OPT_OFF = 0 , # [doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."] CS_OPT_ON = 3 , # [doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_INTEL = 1 , # [doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_ATT = 2 , # [doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_MASM = 4 , # [doc = "< MOS65XX use $ as hex prefix"] CS_OPT_SYNTAX_MOTOROLA = 5 , } # [repr (u32)] # [doc = " Common instruction operand types - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_op_type { # [doc = "< uninitialized/invalid operand."] CS_OP_INVALID = 0 , # [doc = "< Register operand."] CS_OP_REG = 1 , # [doc = "< Immediate operand."] CS_OP_IMM = 2 , # [doc = "< Memory operand. Can be ORed with another operand type."] CS_OP_MEM = 3 , # [doc = "< Floating-Point operand."] CS_OP_FP = 4 , } # [repr (u32)] # [doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_ac_type { # [doc = "< Uninitialized/invalid access type."] CS_AC_INVALID = 0 , # [doc = "< Operand read from memory or register."] CS_AC_READ = 1 , # [doc = "< Operand write to memory or register."] CS_AC_WRITE = 2 , } # [repr (u32)] # [doc = " Common instruction groups - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_group_type { # [doc = "< uninitialized/invalid group."] CS_GRP_INVALID = 0 , # [doc = "< all jump instructions (conditional+direct+indirect jumps)"] CS_GRP_JUMP = 1 , # [doc = "< all call instructions"] CS_GRP_CALL = 2 , # [doc = "< all return instructions"] CS_GRP_RET = 3 , # [doc = "< all interrupt instructions (int+syscall)"] CS_GRP_INT = 4 , # [doc = "< all interrupt return instructions"] CS_GRP_IRET = 5 , # [doc = "< all privileged instructions"] CS_GRP_PRIVILEGE = 6 , # [doc = "< all relative branching instructions"] CS_GRP_BRANCH_RELATIVE = 7 , } # [doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."] pub type cs_skipdata_cb_t = :: std :: option :: Option < unsafe extern "C" fn (code : * const u8 , code_size : usize , offset : usize , user_data : * mut :: std :: os :: raw :: c_void) -> usize > ; # [doc = " User-customized setup for SKIPDATA option"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_skipdata { # [doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."] pub mnemonic : * const :: std :: os :: raw :: c_char , # [doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes.\n TriCore: 2 bytes."] pub callback : cs_skipdata_cb_t , # [doc = " User-defined data to be passed to @callback function pointer."] pub user_data : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_skipdata"] [:: std :: mem :: size_of :: < cs_opt_skipdata > () - 24usize] ; ["Alignment of cs_opt_skipdata"] [:: std :: mem :: align_of :: < cs_opt_skipdata > () - 8usize] ; ["Offset of field: cs_opt_skipdata::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , mnemonic) - 0usize] ; ["Offset of field: cs_opt_skipdata::callback"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , callback) - 8usize] ; ["Offset of field: cs_opt_skipdata::user_data"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , user_data) - 16usize] ; } ; # [repr (u32)] # [doc = " ARM shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_shifter { ARM_SFT_INVALID = 0 , # [doc = "< shift with immediate const"] ARM_SFT_ASR = 1 , # [doc = "< shift with immediate const"] ARM_SFT_LSL = 2 , # [doc = "< shift with immediate const"] ARM_SFT_LSR = 3 , # [doc = "< shift with immediate const"] ARM_SFT_ROR = 4 , # [doc = "< shift with immediate const"] ARM_SFT_RRX = 5 , # [doc = "< shift with register"] ARM_SFT_ASR_REG = 6 , # [doc = "< shift with register"] ARM_SFT_LSL_REG = 7 , # [doc = "< shift with register"] ARM_SFT_LSR_REG = 8 , # [doc = "< shift with register"] ARM_SFT_ROR_REG = 9 , # [doc = "< shift with register"] ARM_SFT_RRX_REG = 10 , } # [repr (u32)] # [doc = " ARM condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cc { ARM_CC_INVALID = 0 , # [doc = "< Equal                      Equal"] ARM_CC_EQ = 1 , # [doc = "< Not equal                  Not equal, or unordered"] ARM_CC_NE = 2 , # [doc = "< Carry set                  >, ==, or unordered"] ARM_CC_HS = 3 , # [doc = "< Carry clear                Less than"] ARM_CC_LO = 4 , # [doc = "< Minus, negative            Less than"] ARM_CC_MI = 5 , # [doc = "< Plus, positive or zero     >, ==, or unordered"] ARM_CC_PL = 6 , # [doc = "< Overflow                   Unordered"] ARM_CC_VS = 7 , # [doc = "< No overflow                Not unordered"] ARM_CC_VC = 8 , # [doc = "< Unsigned higher            Greater than, or unordered"] ARM_CC_HI = 9 , # [doc = "< Unsigned lower or same     Less than or equal"] ARM_CC_LS = 10 , # [doc = "< Greater than or equal      Greater than or equal"] ARM_CC_GE = 11 , # [doc = "< Less than                  Less than, or unordered"] ARM_CC_LT = 12 , # [doc = "< Greater than               Greater than"] ARM_CC_GT = 13 , # [doc = "< Less than or equal         <, ==, or unordered"] ARM_CC_LE = 14 , # [doc = "< Always (unconditional)     Always (unconditional)"] ARM_CC_AL = 15 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_sysreg { # [doc = " Special registers for MSR"] ARM_SYSREG_INVALID = 0 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_C = 1 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_X = 2 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_S = 4 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_F = 8 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_C = 16 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_X = 32 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_S = 64 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_F = 128 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR = 256 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_G = 257 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQ = 258 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQG = 259 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR = 260 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_G = 261 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQG = 262 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQ = 263 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR = 264 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_G = 265 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQG = 266 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQ = 267 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR = 268 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_G = 269 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQG = 270 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQ = 271 , # [doc = " Special registers for MSR"] ARM_SYSREG_IPSR = 272 , # [doc = " Special registers for MSR"] ARM_SYSREG_EPSR = 273 , # [doc = " Special registers for MSR"] ARM_SYSREG_IEPSR = 274 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP = 275 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP = 276 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK = 277 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI = 278 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_MAX = 279 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK = 280 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL = 281 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM = 282 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM = 283 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP_NS = 284 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP_NS = 285 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM_NS = 286 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM_NS = 287 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK_NS = 288 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_NS = 289 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK_NS = 290 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL_NS = 291 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_NS = 292 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_USR = 293 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_USR = 294 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_USR = 295 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_USR = 296 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_USR = 297 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_USR = 298 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_USR = 299 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_FIQ = 300 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_FIQ = 301 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_FIQ = 302 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_FIQ = 303 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_FIQ = 304 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_FIQ = 305 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_FIQ = 306 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_IRQ = 307 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_IRQ = 308 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_SVC = 309 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_SVC = 310 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_ABT = 311 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_ABT = 312 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_UND = 313 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_UND = 314 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_MON = 315 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_MON = 316 , # [doc = " Special registers for MSR"] ARM_SYSREG_ELR_HYP = 317 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_HYP = 318 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_FIQ = 319 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_IRQ = 320 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_SVC = 321 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_ABT = 322 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_UND = 323 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_MON = 324 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_HYP = 325 , } # [repr (u32)] # [doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_mem_barrier { ARM_MB_INVALID = 0 , ARM_MB_RESERVED_0 = 1 , ARM_MB_OSHLD = 2 , ARM_MB_OSHST = 3 , ARM_MB_OSH = 4 , ARM_MB_RESERVED_4 = 5 , ARM_MB_NSHLD = 6 , ARM_MB_NSHST = 7 , ARM_MB_NSH = 8 , ARM_MB_RESERVED_8 = 9 , ARM_MB_ISHLD = 10 , ARM_MB_ISHST = 11 , ARM_MB_ISH = 12 , ARM_MB_RESERVED_12 = 13 , ARM_MB_LD = 14 , ARM_MB_ST = 15 , ARM_MB_SY = 16 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM_OP_FP = 4 , # [doc = "< C-Immediate (coprocessor registers)"] ARM_OP_CIMM = 64 , # [doc = "< P-Immediate (coprocessor registers)"] ARM_OP_PIMM = 65 , # [doc = "< operand for SETEND instruction"] ARM_OP_SETEND = 66 , # [doc = "< MSR/MRS special register operand"] ARM_OP_SYSREG = 67 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_setend_type { # [doc = "< Uninitialized."] ARM_SETEND_INVALID = 0 , # [doc = "< BE operand."] ARM_SETEND_BE = 1 , # [doc = "< LE operand"] ARM_SETEND_LE = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0 , ARM_CPSMODE_IE = 2 , ARM_CPSMODE_ID = 3 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0 , ARM_CPSFLAG_F = 1 , ARM_CPSFLAG_I = 2 , ARM_CPSFLAG_A = 4 , # [doc = "< no flag"] ARM_CPSFLAG_NONE = 16 , } # [repr (u32)] # [doc = " Data type for elements of vector instructions."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0 , ARM_VECTORDATA_I8 = 1 , ARM_VECTORDATA_I16 = 2 , ARM_VECTORDATA_I32 = 3 , ARM_VECTORDATA_I64 = 4 , ARM_VECTORDATA_S8 = 5 , ARM_VECTORDATA_S16 = 6 , ARM_VECTORDATA_S32 = 7 , ARM_VECTORDATA_S64 = 8 , ARM_VECTORDATA_U8 = 9 , ARM_VECTORDATA_U16 = 10 , ARM_VECTORDATA_U32 = 11 , ARM_VECTORDATA_U64 = 12 , ARM_VECTORDATA_P8 = 13 , ARM_VECTORDATA_F16 = 14 , ARM_VECTORDATA_F32 = 15 , ARM_VECTORDATA_F64 = 16 , ARM_VECTORDATA_F16F64 = 17 , ARM_VECTORDATA_F64F16 = 18 , ARM_VECTORDATA_F32F16 = 19 , ARM_VECTORDATA_F16F32 = 20 , ARM_VECTORDATA_F64F32 = 21 , ARM_VECTORDATA_F32F64 = 22 , ARM_VECTORDATA_S32F32 = 23 , ARM_VECTORDATA_U32F32 = 24 , ARM_VECTORDATA_F32S32 = 25 , ARM_VECTORDATA_F32U32 = 26 , ARM_VECTORDATA_F64S16 = 27 , ARM_VECTORDATA_F32S16 = 28 , ARM_VECTORDATA_F64S32 = 29 , ARM_VECTORDATA_S16F64 = 30 , ARM_VECTORDATA_S16F32 = 31 , ARM_VECTORDATA_S32F64 = 32 , ARM_VECTORDATA_U16F64 = 33 , ARM_VECTORDATA_U16F32 = 34 , ARM_VECTORDATA_U32F64 = 35 , ARM_VECTORDATA_F64U16 = 36 , ARM_VECTORDATA_F32U16 = 37 , ARM_VECTORDATA_F64U32 = 38 , ARM_VECTORDATA_F16U16 = 39 , ARM_VECTORDATA_U16F16 = 40 , ARM_VECTORDATA_F16U32 = 41 , ARM_VECTORDATA_U32F16 = 42 , } impl arm_reg { pub const ARM_REG_R13 : arm_reg = arm_reg :: ARM_REG_SP ; } impl arm_reg { pub const ARM_REG_R14 : arm_reg = arm_reg :: ARM_REG_LR ; } impl arm_reg { pub const ARM_REG_R15 : arm_reg = arm_reg :: ARM_REG_PC ; } impl arm_reg { pub const ARM_REG_SB : arm_reg = arm_reg :: ARM_REG_R9 ; } impl arm_reg { pub const ARM_REG_SL : arm_reg = arm_reg :: ARM_REG_R10 ; } impl arm_reg { pub const ARM_REG_FP : arm_reg = arm_reg :: ARM_REG_R11 ; } impl arm_reg { pub const ARM_REG_IP : arm_reg = arm_reg :: ARM_REG_R12 ; } # [repr (u32)] # [doc = " ARM registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_reg { ARM_REG_INVALID = 0 , ARM_REG_APSR = 1 , ARM_REG_APSR_NZCV = 2 , ARM_REG_CPSR = 3 , ARM_REG_FPEXC = 4 , ARM_REG_FPINST = 5 , ARM_REG_FPSCR = 6 , ARM_REG_FPSCR_NZCV = 7 , ARM_REG_FPSID = 8 , ARM_REG_ITSTATE = 9 , ARM_REG_LR = 10 , ARM_REG_PC = 11 , ARM_REG_SP = 12 , ARM_REG_SPSR = 13 , ARM_REG_D0 = 14 , ARM_REG_D1 = 15 , ARM_REG_D2 = 16 , ARM_REG_D3 = 17 , ARM_REG_D4 = 18 , ARM_REG_D5 = 19 , ARM_REG_D6 = 20 , ARM_REG_D7 = 21 , ARM_REG_D8 = 22 , ARM_REG_D9 = 23 , ARM_REG_D10 = 24 , ARM_REG_D11 = 25 , ARM_REG_D12 = 26 , ARM_REG_D13 = 27 , ARM_REG_D14 = 28 , ARM_REG_D15 = 29 , ARM_REG_D16 = 30 , ARM_REG_D17 = 31 , ARM_REG_D18 = 32 , ARM_REG_D19 = 33 , ARM_REG_D20 = 34 , ARM_REG_D21 = 35 , ARM_REG_D22 = 36 , ARM_REG_D23 = 37 , ARM_REG_D24 = 38 , ARM_REG_D25 = 39 , ARM_REG_D26 = 40 , ARM_REG_D27 = 41 , ARM_REG_D28 = 42 , ARM_REG_D29 = 43 , ARM_REG_D30 = 44 , ARM_REG_D31 = 45 , ARM_REG_FPINST2 = 46 , ARM_REG_MVFR0 = 47 , ARM_REG_MVFR1 = 48 , ARM_REG_MVFR2 = 49 , ARM_REG_Q0 = 50 , ARM_REG_Q1 = 51 , ARM_REG_Q2 = 52 , ARM_REG_Q3 = 53 , ARM_REG_Q4 = 54 , ARM_REG_Q5 = 55 , ARM_REG_Q6 = 56 , ARM_REG_Q7 = 57 , ARM_REG_Q8 = 58 , ARM_REG_Q9 = 59 , ARM_REG_Q10 = 60 , ARM_REG_Q11 = 61 , ARM_REG_Q12 = 62 , ARM_REG_Q13 = 63 , ARM_REG_Q14 = 64 , ARM_REG_Q15 = 65 , ARM_REG_R0 = 66 , ARM_REG_R1 = 67 , ARM_REG_R2 = 68 , ARM_REG_R3 = 69 , ARM_REG_R4 = 70 , ARM_REG_R5 = 71 , ARM_REG_R6 = 72 , ARM_REG_R7 = 73 , ARM_REG_R8 = 74 , ARM_REG_R9 = 75 , ARM_REG_R10 = 76 , ARM_REG_R11 = 77 , ARM_REG_R12 = 78 , ARM_REG_S0 = 79 , ARM_REG_S1 = 80 , ARM_REG_S2 = 81 , ARM_REG_S3 = 82 , ARM_REG_S4 = 83 , ARM_REG_S5 = 84 , ARM_REG_S6 = 85 , ARM_REG_S7 = 86 , ARM_REG_S8 = 87 , ARM_REG_S9 = 88 , ARM_REG_S10 = 89 , ARM_REG_S11 = 90 , ARM_REG_S12 = 91 , ARM_REG_S13 = 92 , ARM_REG_S14 = 93 , ARM_REG_S15 = 94 , ARM_REG_S16 = 95 , ARM_REG_S17 = 96 , ARM_REG_S18 = 97 , ARM_REG_S19 = 98 , ARM_REG_S20 = 99 , ARM_REG_S21 = 100 , ARM_REG_S22 = 101 , ARM_REG_S23 = 102 , ARM_REG_S24 = 103 , ARM_REG_S25 = 104 , ARM_REG_S26 = 105 , ARM_REG_S27 = 106 , ARM_REG_S28 = 107 , ARM_REG_S29 = 108 , ARM_REG_S30 = 109 , ARM_REG_S31 = 110 , ARM_REG_ENDING = 111 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm_op_mem { # [doc = "< base register"] pub base : arm_reg , # [doc = "< index register"] pub index : arm_reg , # [doc = "< scale for index register (can be 1, or -1)"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_int , # [doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"] pub lshift : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm_op_mem"] [:: std :: mem :: size_of :: < arm_op_mem > () - 20usize] ; ["Alignment of arm_op_mem"] [:: std :: mem :: align_of :: < arm_op_mem > () - 4usize] ; ["Offset of field: arm_op_mem::base"] [:: std :: mem :: offset_of ! (arm_op_mem , base) - 0usize] ; ["Offset of field: arm_op_mem::index"] [:: std :: mem :: offset_of ! (arm_op_mem , index) - 4usize] ; ["Offset of field: arm_op_mem::scale"] [:: std :: mem :: offset_of ! (arm_op_mem , scale) - 8usize] ; ["Offset of field: arm_op_mem::disp"] [:: std :: mem :: offset_of ! (arm_op_mem , disp) - 12usize] ; ["Offset of field: arm_op_mem::lshift"] [:: std :: mem :: offset_of ! (arm_op_mem , lshift) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm_op { # [doc = "< Vector Index for some vector operands (or -1 if irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , pub shift : cs_arm_op__bindgen_ty_1 , # [doc = "< operand type"] pub type_ : arm_op_type , pub __bindgen_anon_1 : cs_arm_op__bindgen_ty_2 , # [doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."] pub subtracted : bool , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"] pub neon_lane : i8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm_op__bindgen_ty_1 { pub type_ : arm_shifter , pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm_op__bindgen_ty_2 { # [doc = "< register value for REG/SYSREG operand"] pub reg : :: std :: os :: raw :: c_int , # [doc = "< immediate value for C-IMM, P-IMM or IMM operand"] pub imm : i32 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm_op_mem , # [doc = "< SETEND instruction's operand type"] pub setend : arm_setend_type , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_2 > () - 24usize] ; ["Alignment of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::setend"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , setend) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op"] [:: std :: mem :: size_of :: < cs_arm_op > () - 48usize] ; ["Alignment of cs_arm_op"] [:: std :: mem :: align_of :: < cs_arm_op > () - 8usize] ; ["Offset of field: cs_arm_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm_op , vector_index) - 0usize] ; ["Offset of field: cs_arm_op::shift"] [:: std :: mem :: offset_of ! (cs_arm_op , shift) - 4usize] ; ["Offset of field: cs_arm_op::type_"] [:: std :: mem :: offset_of ! (cs_arm_op , type_) - 12usize] ; ["Offset of field: cs_arm_op::subtracted"] [:: std :: mem :: offset_of ! (cs_arm_op , subtracted) - 40usize] ; ["Offset of field: cs_arm_op::access"] [:: std :: mem :: offset_of ! (cs_arm_op , access) - 41usize] ; ["Offset of field: cs_arm_op::neon_lane"] [:: std :: mem :: offset_of ! (cs_arm_op , neon_lane) - 42usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm { # [doc = "< User-mode registers to be loaded (for LDM/STM instructions)"] pub usermode : bool , # [doc = "< Scalar size for vector instructions"] pub vector_size : :: std :: os :: raw :: c_int , # [doc = "< Data type for elements of vector instructions"] pub vector_data : arm_vectordata_type , # [doc = "< CPS mode for CPS instruction"] pub cps_mode : arm_cpsmode_type , # [doc = "< CPS mode for CPS instruction"] pub cps_flag : arm_cpsflag_type , # [doc = "< conditional code for this insn"] pub cc : arm_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn write-back?"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = "< Option for some memory barrier instructions"] pub mem_barrier : arm_mem_barrier , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm_op ; 36usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm"] [:: std :: mem :: size_of :: < cs_arm > () - 1768usize] ; ["Alignment of cs_arm"] [:: std :: mem :: align_of :: < cs_arm > () - 8usize] ; ["Offset of field: cs_arm::usermode"] [:: std :: mem :: offset_of ! (cs_arm , usermode) - 0usize] ; ["Offset of field: cs_arm::vector_size"] [:: std :: mem :: offset_of ! (cs_arm , vector_size) - 4usize] ; ["Offset of field: cs_arm::vector_data"] [:: std :: mem :: offset_of ! (cs_arm , vector_data) - 8usize] ; ["Offset of field: cs_arm::cps_mode"] [:: std :: mem :: offset_of ! (cs_arm , cps_mode) - 12usize] ; ["Offset of field: cs_arm::cps_flag"] [:: std :: mem :: offset_of ! (cs_arm , cps_flag) - 16usize] ; ["Offset of field: cs_arm::cc"] [:: std :: mem :: offset_of ! (cs_arm , cc) - 20usize] ; ["Offset of field: cs_arm::update_flags"] [:: std :: mem :: offset_of ! (cs_arm , update_flags) - 24usize] ; ["Offset of field: cs_arm::writeback"] [:: std :: mem :: offset_of ! (cs_arm , writeback) - 25usize] ; ["Offset of field: cs_arm::post_index"] [:: std :: mem :: offset_of ! (cs_arm , post_index) - 26usize] ; ["Offset of field: cs_arm::mem_barrier"] [:: std :: mem :: offset_of ! (cs_arm , mem_barrier) - 28usize] ; ["Offset of field: cs_arm::op_count"] [:: std :: mem :: offset_of ! (cs_arm , op_count) - 32usize] ; ["Offset of field: cs_arm::operands"] [:: std :: mem :: offset_of ! (cs_arm , operands) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_arm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . post_index , self . mem_barrier , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn { ARM_INS_INVALID = 0 , ARM_INS_ADC = 1 , ARM_INS_ADD = 2 , ARM_INS_ADDW = 3 , ARM_INS_ADR = 4 , ARM_INS_AESD = 5 , ARM_INS_AESE = 6 , ARM_INS_AESIMC = 7 , ARM_INS_AESMC = 8 , ARM_INS_AND = 9 , ARM_INS_ASR = 10 , ARM_INS_B = 11 , ARM_INS_BFC = 12 , ARM_INS_BFI = 13 , ARM_INS_BIC = 14 , ARM_INS_BKPT = 15 , ARM_INS_BL = 16 , ARM_INS_BLX = 17 , ARM_INS_BLXNS = 18 , ARM_INS_BX = 19 , ARM_INS_BXJ = 20 , ARM_INS_BXNS = 21 , ARM_INS_CBNZ = 22 , ARM_INS_CBZ = 23 , ARM_INS_CDP = 24 , ARM_INS_CDP2 = 25 , ARM_INS_CLREX = 26 , ARM_INS_CLZ = 27 , ARM_INS_CMN = 28 , ARM_INS_CMP = 29 , ARM_INS_CPS = 30 , ARM_INS_CRC32B = 31 , ARM_INS_CRC32CB = 32 , ARM_INS_CRC32CH = 33 , ARM_INS_CRC32CW = 34 , ARM_INS_CRC32H = 35 , ARM_INS_CRC32W = 36 , ARM_INS_CSDB = 37 , ARM_INS_DBG = 38 , ARM_INS_DCPS1 = 39 , ARM_INS_DCPS2 = 40 , ARM_INS_DCPS3 = 41 , ARM_INS_DFB = 42 , ARM_INS_DMB = 43 , ARM_INS_DSB = 44 , ARM_INS_EOR = 45 , ARM_INS_ERET = 46 , ARM_INS_ESB = 47 , ARM_INS_FADDD = 48 , ARM_INS_FADDS = 49 , ARM_INS_FCMPZD = 50 , ARM_INS_FCMPZS = 51 , ARM_INS_FCONSTD = 52 , ARM_INS_FCONSTS = 53 , ARM_INS_FLDMDBX = 54 , ARM_INS_FLDMIAX = 55 , ARM_INS_FMDHR = 56 , ARM_INS_FMDLR = 57 , ARM_INS_FMSTAT = 58 , ARM_INS_FSTMDBX = 59 , ARM_INS_FSTMIAX = 60 , ARM_INS_FSUBD = 61 , ARM_INS_FSUBS = 62 , ARM_INS_HINT = 63 , ARM_INS_HLT = 64 , ARM_INS_HVC = 65 , ARM_INS_ISB = 66 , ARM_INS_IT = 67 , ARM_INS_LDA = 68 , ARM_INS_LDAB = 69 , ARM_INS_LDAEX = 70 , ARM_INS_LDAEXB = 71 , ARM_INS_LDAEXD = 72 , ARM_INS_LDAEXH = 73 , ARM_INS_LDAH = 74 , ARM_INS_LDC = 75 , ARM_INS_LDC2 = 76 , ARM_INS_LDC2L = 77 , ARM_INS_LDCL = 78 , ARM_INS_LDM = 79 , ARM_INS_LDMDA = 80 , ARM_INS_LDMDB = 81 , ARM_INS_LDMIB = 82 , ARM_INS_LDR = 83 , ARM_INS_LDRB = 84 , ARM_INS_LDRBT = 85 , ARM_INS_LDRD = 86 , ARM_INS_LDREX = 87 , ARM_INS_LDREXB = 88 , ARM_INS_LDREXD = 89 , ARM_INS_LDREXH = 90 , ARM_INS_LDRH = 91 , ARM_INS_LDRHT = 92 , ARM_INS_LDRSB = 93 , ARM_INS_LDRSBT = 94 , ARM_INS_LDRSH = 95 , ARM_INS_LDRSHT = 96 , ARM_INS_LDRT = 97 , ARM_INS_LSL = 98 , ARM_INS_LSR = 99 , ARM_INS_MCR = 100 , ARM_INS_MCR2 = 101 , ARM_INS_MCRR = 102 , ARM_INS_MCRR2 = 103 , ARM_INS_MLA = 104 , ARM_INS_MLS = 105 , ARM_INS_MOV = 106 , ARM_INS_MOVS = 107 , ARM_INS_MOVT = 108 , ARM_INS_MOVW = 109 , ARM_INS_MRC = 110 , ARM_INS_MRC2 = 111 , ARM_INS_MRRC = 112 , ARM_INS_MRRC2 = 113 , ARM_INS_MRS = 114 , ARM_INS_MSR = 115 , ARM_INS_MUL = 116 , ARM_INS_MVN = 117 , ARM_INS_NEG = 118 , ARM_INS_NOP = 119 , ARM_INS_ORN = 120 , ARM_INS_ORR = 121 , ARM_INS_PKHBT = 122 , ARM_INS_PKHTB = 123 , ARM_INS_PLD = 124 , ARM_INS_PLDW = 125 , ARM_INS_PLI = 126 , ARM_INS_POP = 127 , ARM_INS_PUSH = 128 , ARM_INS_QADD = 129 , ARM_INS_QADD16 = 130 , ARM_INS_QADD8 = 131 , ARM_INS_QASX = 132 , ARM_INS_QDADD = 133 , ARM_INS_QDSUB = 134 , ARM_INS_QSAX = 135 , ARM_INS_QSUB = 136 , ARM_INS_QSUB16 = 137 , ARM_INS_QSUB8 = 138 , ARM_INS_RBIT = 139 , ARM_INS_REV = 140 , ARM_INS_REV16 = 141 , ARM_INS_REVSH = 142 , ARM_INS_RFEDA = 143 , ARM_INS_RFEDB = 144 , ARM_INS_RFEIA = 145 , ARM_INS_RFEIB = 146 , ARM_INS_ROR = 147 , ARM_INS_RRX = 148 , ARM_INS_RSB = 149 , ARM_INS_RSC = 150 , ARM_INS_SADD16 = 151 , ARM_INS_SADD8 = 152 , ARM_INS_SASX = 153 , ARM_INS_SBC = 154 , ARM_INS_SBFX = 155 , ARM_INS_SDIV = 156 , ARM_INS_SEL = 157 , ARM_INS_SETEND = 158 , ARM_INS_SETPAN = 159 , ARM_INS_SEV = 160 , ARM_INS_SEVL = 161 , ARM_INS_SG = 162 , ARM_INS_SHA1C = 163 , ARM_INS_SHA1H = 164 , ARM_INS_SHA1M = 165 , ARM_INS_SHA1P = 166 , ARM_INS_SHA1SU0 = 167 , ARM_INS_SHA1SU1 = 168 , ARM_INS_SHA256H = 169 , ARM_INS_SHA256H2 = 170 , ARM_INS_SHA256SU0 = 171 , ARM_INS_SHA256SU1 = 172 , ARM_INS_SHADD16 = 173 , ARM_INS_SHADD8 = 174 , ARM_INS_SHASX = 175 , ARM_INS_SHSAX = 176 , ARM_INS_SHSUB16 = 177 , ARM_INS_SHSUB8 = 178 , ARM_INS_SMC = 179 , ARM_INS_SMLABB = 180 , ARM_INS_SMLABT = 181 , ARM_INS_SMLAD = 182 , ARM_INS_SMLADX = 183 , ARM_INS_SMLAL = 184 , ARM_INS_SMLALBB = 185 , ARM_INS_SMLALBT = 186 , ARM_INS_SMLALD = 187 , ARM_INS_SMLALDX = 188 , ARM_INS_SMLALTB = 189 , ARM_INS_SMLALTT = 190 , ARM_INS_SMLATB = 191 , ARM_INS_SMLATT = 192 , ARM_INS_SMLAWB = 193 , ARM_INS_SMLAWT = 194 , ARM_INS_SMLSD = 195 , ARM_INS_SMLSDX = 196 , ARM_INS_SMLSLD = 197 , ARM_INS_SMLSLDX = 198 , ARM_INS_SMMLA = 199 , ARM_INS_SMMLAR = 200 , ARM_INS_SMMLS = 201 , ARM_INS_SMMLSR = 202 , ARM_INS_SMMUL = 203 , ARM_INS_SMMULR = 204 , ARM_INS_SMUAD = 205 , ARM_INS_SMUADX = 206 , ARM_INS_SMULBB = 207 , ARM_INS_SMULBT = 208 , ARM_INS_SMULL = 209 , ARM_INS_SMULTB = 210 , ARM_INS_SMULTT = 211 , ARM_INS_SMULWB = 212 , ARM_INS_SMULWT = 213 , ARM_INS_SMUSD = 214 , ARM_INS_SMUSDX = 215 , ARM_INS_SRSDA = 216 , ARM_INS_SRSDB = 217 , ARM_INS_SRSIA = 218 , ARM_INS_SRSIB = 219 , ARM_INS_SSAT = 220 , ARM_INS_SSAT16 = 221 , ARM_INS_SSAX = 222 , ARM_INS_SSUB16 = 223 , ARM_INS_SSUB8 = 224 , ARM_INS_STC = 225 , ARM_INS_STC2 = 226 , ARM_INS_STC2L = 227 , ARM_INS_STCL = 228 , ARM_INS_STL = 229 , ARM_INS_STLB = 230 , ARM_INS_STLEX = 231 , ARM_INS_STLEXB = 232 , ARM_INS_STLEXD = 233 , ARM_INS_STLEXH = 234 , ARM_INS_STLH = 235 , ARM_INS_STM = 236 , ARM_INS_STMDA = 237 , ARM_INS_STMDB = 238 , ARM_INS_STMIB = 239 , ARM_INS_STR = 240 , ARM_INS_STRB = 241 , ARM_INS_STRBT = 242 , ARM_INS_STRD = 243 , ARM_INS_STREX = 244 , ARM_INS_STREXB = 245 , ARM_INS_STREXD = 246 , ARM_INS_STREXH = 247 , ARM_INS_STRH = 248 , ARM_INS_STRHT = 249 , ARM_INS_STRT = 250 , ARM_INS_SUB = 251 , ARM_INS_SUBS = 252 , ARM_INS_SUBW = 253 , ARM_INS_SVC = 254 , ARM_INS_SWP = 255 , ARM_INS_SWPB = 256 , ARM_INS_SXTAB = 257 , ARM_INS_SXTAB16 = 258 , ARM_INS_SXTAH = 259 , ARM_INS_SXTB = 260 , ARM_INS_SXTB16 = 261 , ARM_INS_SXTH = 262 , ARM_INS_TBB = 263 , ARM_INS_TBH = 264 , ARM_INS_TEQ = 265 , ARM_INS_TRAP = 266 , ARM_INS_TSB = 267 , ARM_INS_TST = 268 , ARM_INS_TT = 269 , ARM_INS_TTA = 270 , ARM_INS_TTAT = 271 , ARM_INS_TTT = 272 , ARM_INS_UADD16 = 273 , ARM_INS_UADD8 = 274 , ARM_INS_UASX = 275 , ARM_INS_UBFX = 276 , ARM_INS_UDF = 277 , ARM_INS_UDIV = 278 , ARM_INS_UHADD16 = 279 , ARM_INS_UHADD8 = 280 , ARM_INS_UHASX = 281 , ARM_INS_UHSAX = 282 , ARM_INS_UHSUB16 = 283 , ARM_INS_UHSUB8 = 284 , ARM_INS_UMAAL = 285 , ARM_INS_UMLAL = 286 , ARM_INS_UMULL = 287 , ARM_INS_UQADD16 = 288 , ARM_INS_UQADD8 = 289 , ARM_INS_UQASX = 290 , ARM_INS_UQSAX = 291 , ARM_INS_UQSUB16 = 292 , ARM_INS_UQSUB8 = 293 , ARM_INS_USAD8 = 294 , ARM_INS_USADA8 = 295 , ARM_INS_USAT = 296 , ARM_INS_USAT16 = 297 , ARM_INS_USAX = 298 , ARM_INS_USUB16 = 299 , ARM_INS_USUB8 = 300 , ARM_INS_UXTAB = 301 , ARM_INS_UXTAB16 = 302 , ARM_INS_UXTAH = 303 , ARM_INS_UXTB = 304 , ARM_INS_UXTB16 = 305 , ARM_INS_UXTH = 306 , ARM_INS_VABA = 307 , ARM_INS_VABAL = 308 , ARM_INS_VABD = 309 , ARM_INS_VABDL = 310 , ARM_INS_VABS = 311 , ARM_INS_VACGE = 312 , ARM_INS_VACGT = 313 , ARM_INS_VACLE = 314 , ARM_INS_VACLT = 315 , ARM_INS_VADD = 316 , ARM_INS_VADDHN = 317 , ARM_INS_VADDL = 318 , ARM_INS_VADDW = 319 , ARM_INS_VAND = 320 , ARM_INS_VBIC = 321 , ARM_INS_VBIF = 322 , ARM_INS_VBIT = 323 , ARM_INS_VBSL = 324 , ARM_INS_VCADD = 325 , ARM_INS_VCEQ = 326 , ARM_INS_VCGE = 327 , ARM_INS_VCGT = 328 , ARM_INS_VCLE = 329 , ARM_INS_VCLS = 330 , ARM_INS_VCLT = 331 , ARM_INS_VCLZ = 332 , ARM_INS_VCMLA = 333 , ARM_INS_VCMP = 334 , ARM_INS_VCMPE = 335 , ARM_INS_VCNT = 336 , ARM_INS_VCVT = 337 , ARM_INS_VCVTA = 338 , ARM_INS_VCVTB = 339 , ARM_INS_VCVTM = 340 , ARM_INS_VCVTN = 341 , ARM_INS_VCVTP = 342 , ARM_INS_VCVTR = 343 , ARM_INS_VCVTT = 344 , ARM_INS_VDIV = 345 , ARM_INS_VDUP = 346 , ARM_INS_VEOR = 347 , ARM_INS_VEXT = 348 , ARM_INS_VFMA = 349 , ARM_INS_VFMS = 350 , ARM_INS_VFNMA = 351 , ARM_INS_VFNMS = 352 , ARM_INS_VHADD = 353 , ARM_INS_VHSUB = 354 , ARM_INS_VINS = 355 , ARM_INS_VJCVT = 356 , ARM_INS_VLD1 = 357 , ARM_INS_VLD2 = 358 , ARM_INS_VLD3 = 359 , ARM_INS_VLD4 = 360 , ARM_INS_VLDMDB = 361 , ARM_INS_VLDMIA = 362 , ARM_INS_VLDR = 363 , ARM_INS_VLLDM = 364 , ARM_INS_VLSTM = 365 , ARM_INS_VMAX = 366 , ARM_INS_VMAXNM = 367 , ARM_INS_VMIN = 368 , ARM_INS_VMINNM = 369 , ARM_INS_VMLA = 370 , ARM_INS_VMLAL = 371 , ARM_INS_VMLS = 372 , ARM_INS_VMLSL = 373 , ARM_INS_VMOV = 374 , ARM_INS_VMOVL = 375 , ARM_INS_VMOVN = 376 , ARM_INS_VMOVX = 377 , ARM_INS_VMRS = 378 , ARM_INS_VMSR = 379 , ARM_INS_VMUL = 380 , ARM_INS_VMULL = 381 , ARM_INS_VMVN = 382 , ARM_INS_VNEG = 383 , ARM_INS_VNMLA = 384 , ARM_INS_VNMLS = 385 , ARM_INS_VNMUL = 386 , ARM_INS_VORN = 387 , ARM_INS_VORR = 388 , ARM_INS_VPADAL = 389 , ARM_INS_VPADD = 390 , ARM_INS_VPADDL = 391 , ARM_INS_VPMAX = 392 , ARM_INS_VPMIN = 393 , ARM_INS_VPOP = 394 , ARM_INS_VPUSH = 395 , ARM_INS_VQABS = 396 , ARM_INS_VQADD = 397 , ARM_INS_VQDMLAL = 398 , ARM_INS_VQDMLSL = 399 , ARM_INS_VQDMULH = 400 , ARM_INS_VQDMULL = 401 , ARM_INS_VQMOVN = 402 , ARM_INS_VQMOVUN = 403 , ARM_INS_VQNEG = 404 , ARM_INS_VQRDMLAH = 405 , ARM_INS_VQRDMLSH = 406 , ARM_INS_VQRDMULH = 407 , ARM_INS_VQRSHL = 408 , ARM_INS_VQRSHRN = 409 , ARM_INS_VQRSHRUN = 410 , ARM_INS_VQSHL = 411 , ARM_INS_VQSHLU = 412 , ARM_INS_VQSHRN = 413 , ARM_INS_VQSHRUN = 414 , ARM_INS_VQSUB = 415 , ARM_INS_VRADDHN = 416 , ARM_INS_VRECPE = 417 , ARM_INS_VRECPS = 418 , ARM_INS_VREV16 = 419 , ARM_INS_VREV32 = 420 , ARM_INS_VREV64 = 421 , ARM_INS_VRHADD = 422 , ARM_INS_VRINTA = 423 , ARM_INS_VRINTM = 424 , ARM_INS_VRINTN = 425 , ARM_INS_VRINTP = 426 , ARM_INS_VRINTR = 427 , ARM_INS_VRINTX = 428 , ARM_INS_VRINTZ = 429 , ARM_INS_VRSHL = 430 , ARM_INS_VRSHR = 431 , ARM_INS_VRSHRN = 432 , ARM_INS_VRSQRTE = 433 , ARM_INS_VRSQRTS = 434 , ARM_INS_VRSRA = 435 , ARM_INS_VRSUBHN = 436 , ARM_INS_VSDOT = 437 , ARM_INS_VSELEQ = 438 , ARM_INS_VSELGE = 439 , ARM_INS_VSELGT = 440 , ARM_INS_VSELVS = 441 , ARM_INS_VSHL = 442 , ARM_INS_VSHLL = 443 , ARM_INS_VSHR = 444 , ARM_INS_VSHRN = 445 , ARM_INS_VSLI = 446 , ARM_INS_VSQRT = 447 , ARM_INS_VSRA = 448 , ARM_INS_VSRI = 449 , ARM_INS_VST1 = 450 , ARM_INS_VST2 = 451 , ARM_INS_VST3 = 452 , ARM_INS_VST4 = 453 , ARM_INS_VSTMDB = 454 , ARM_INS_VSTMIA = 455 , ARM_INS_VSTR = 456 , ARM_INS_VSUB = 457 , ARM_INS_VSUBHN = 458 , ARM_INS_VSUBL = 459 , ARM_INS_VSUBW = 460 , ARM_INS_VSWP = 461 , ARM_INS_VTBL = 462 , ARM_INS_VTBX = 463 , ARM_INS_VTRN = 464 , ARM_INS_VTST = 465 , ARM_INS_VUDOT = 466 , ARM_INS_VUZP = 467 , ARM_INS_VZIP = 468 , ARM_INS_WFE = 469 , ARM_INS_WFI = 470 , ARM_INS_YIELD = 471 , ARM_INS_ENDING = 472 , } # [repr (u32)] # [doc = " Group of ARM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] ARM_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] ARM_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM_GRP_BRANCH_RELATIVE = 7 , ARM_GRP_CRYPTO = 128 , ARM_GRP_DATABARRIER = 129 , ARM_GRP_DIVIDE = 130 , ARM_GRP_FPARMV8 = 131 , ARM_GRP_MULTPRO = 132 , ARM_GRP_NEON = 133 , ARM_GRP_T2EXTRACTPACK = 134 , ARM_GRP_THUMB2DSP = 135 , ARM_GRP_TRUSTZONE = 136 , ARM_GRP_V4T = 137 , ARM_GRP_V5T = 138 , ARM_GRP_V5TE = 139 , ARM_GRP_V6 = 140 , ARM_GRP_V6T2 = 141 , ARM_GRP_V7 = 142 , ARM_GRP_V8 = 143 , ARM_GRP_VFP2 = 144 , ARM_GRP_VFP3 = 145 , ARM_GRP_VFP4 = 146 , ARM_GRP_ARM = 147 , ARM_GRP_MCLASS = 148 , ARM_GRP_NOTMCLASS = 149 , ARM_GRP_THUMB = 150 , ARM_GRP_THUMB1ONLY = 151 , ARM_GRP_THUMB2 = 152 , ARM_GRP_PREV8 = 153 , ARM_GRP_FPVMLX = 154 , ARM_GRP_MULOPS = 155 , ARM_GRP_CRC = 156 , ARM_GRP_DPVFP = 157 , ARM_GRP_V6M = 158 , ARM_GRP_VIRTUALIZATION = 159 , ARM_GRP_ENDING = 160 , } # [repr (u32)] # [doc = " ARM64 shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_shifter { ARM64_SFT_INVALID = 0 , ARM64_SFT_LSL = 1 , ARM64_SFT_MSL = 2 , ARM64_SFT_LSR = 3 , ARM64_SFT_ASR = 4 , ARM64_SFT_ROR = 5 , } # [repr (u32)] # [doc = " ARM64 extender type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_extender { ARM64_EXT_INVALID = 0 , ARM64_EXT_UXTB = 1 , ARM64_EXT_UXTH = 2 , ARM64_EXT_UXTW = 3 , ARM64_EXT_UXTX = 4 , ARM64_EXT_SXTB = 5 , ARM64_EXT_SXTH = 6 , ARM64_EXT_SXTW = 7 , ARM64_EXT_SXTX = 8 , } # [repr (u32)] # [doc = " ARM64 condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_cc { ARM64_CC_INVALID = 0 , # [doc = "< Equal"] ARM64_CC_EQ = 1 , # [doc = "< Not equal:                 Not equal, or unordered"] ARM64_CC_NE = 2 , # [doc = "< Unsigned higher or same:   >, ==, or unordered"] ARM64_CC_HS = 3 , # [doc = "< Unsigned lower or same:    Less than"] ARM64_CC_LO = 4 , # [doc = "< Minus, negative:           Less than"] ARM64_CC_MI = 5 , # [doc = "< Plus, positive or zero:    >, ==, or unordered"] ARM64_CC_PL = 6 , # [doc = "< Overflow:                  Unordered"] ARM64_CC_VS = 7 , # [doc = "< No overflow:               Ordered"] ARM64_CC_VC = 8 , # [doc = "< Unsigned higher:           Greater than, or unordered"] ARM64_CC_HI = 9 , # [doc = "< Unsigned lower or same:    Less than or equal"] ARM64_CC_LS = 10 , # [doc = "< Greater than or equal:     Greater than or equal"] ARM64_CC_GE = 11 , # [doc = "< Less than:                 Less than, or unordered"] ARM64_CC_LT = 12 , # [doc = "< Signed greater than:       Greater than"] ARM64_CC_GT = 13 , # [doc = "< Signed less than or equal: <, ==, or unordered"] ARM64_CC_LE = 14 , # [doc = "< Always (unconditional):    Always (unconditional)"] ARM64_CC_AL = 15 , # [doc = "< Always (unconditional):   Always (unconditional)"] ARM64_CC_NV = 16 , } impl arm64_sysreg { pub const ARM64_SYSREG_DBGDTRTX_EL0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_DBGDTRRX_EL0 ; } impl arm64_sysreg { pub const ARM64_SYSREG_TRCEXTINSELR0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TRCEXTINSELR ; } impl arm64_sysreg { pub const ARM64_SYSREG_VSCTLR_EL2 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TTBR0_EL2 ; } # [repr (u32)] # [doc = " System registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sysreg { ARM64_SYSREG_INVALID = 0 , ARM64_SYSREG_ACCDATA_EL1 = 50821 , ARM64_SYSREG_ACTLR_EL1 = 49281 , ARM64_SYSREG_ACTLR_EL2 = 57473 , ARM64_SYSREG_ACTLR_EL3 = 61569 , ARM64_SYSREG_AFSR0_EL1 = 49800 , ARM64_SYSREG_AFSR0_EL12 = 60040 , ARM64_SYSREG_AFSR0_EL2 = 57992 , ARM64_SYSREG_AFSR0_EL3 = 62088 , ARM64_SYSREG_AFSR1_EL1 = 49801 , ARM64_SYSREG_AFSR1_EL12 = 60041 , ARM64_SYSREG_AFSR1_EL2 = 57993 , ARM64_SYSREG_AFSR1_EL3 = 62089 , ARM64_SYSREG_AIDR_EL1 = 51207 , ARM64_SYSREG_AMAIR_EL1 = 50456 , ARM64_SYSREG_AMAIR_EL12 = 60696 , ARM64_SYSREG_AMAIR_EL2 = 58648 , ARM64_SYSREG_AMAIR_EL3 = 62744 , ARM64_SYSREG_AMCFGR_EL0 = 56977 , ARM64_SYSREG_AMCGCR_EL0 = 56978 , ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980 , ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984 , ARM64_SYSREG_AMCNTENSET0_EL0 = 56981 , ARM64_SYSREG_AMCNTENSET1_EL0 = 56985 , ARM64_SYSREG_AMCR_EL0 = 56976 , ARM64_SYSREG_AMEVCNTR00_EL0 = 56992 , ARM64_SYSREG_AMEVCNTR01_EL0 = 56993 , ARM64_SYSREG_AMEVCNTR02_EL0 = 56994 , ARM64_SYSREG_AMEVCNTR03_EL0 = 56995 , ARM64_SYSREG_AMEVCNTR10_EL0 = 57056 , ARM64_SYSREG_AMEVCNTR110_EL0 = 57066 , ARM64_SYSREG_AMEVCNTR111_EL0 = 57067 , ARM64_SYSREG_AMEVCNTR112_EL0 = 57068 , ARM64_SYSREG_AMEVCNTR113_EL0 = 57069 , ARM64_SYSREG_AMEVCNTR114_EL0 = 57070 , ARM64_SYSREG_AMEVCNTR115_EL0 = 57071 , ARM64_SYSREG_AMEVCNTR11_EL0 = 57057 , ARM64_SYSREG_AMEVCNTR12_EL0 = 57058 , ARM64_SYSREG_AMEVCNTR13_EL0 = 57059 , ARM64_SYSREG_AMEVCNTR14_EL0 = 57060 , ARM64_SYSREG_AMEVCNTR15_EL0 = 57061 , ARM64_SYSREG_AMEVCNTR16_EL0 = 57062 , ARM64_SYSREG_AMEVCNTR17_EL0 = 57063 , ARM64_SYSREG_AMEVCNTR18_EL0 = 57064 , ARM64_SYSREG_AMEVCNTR19_EL0 = 57065 , ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 59072 , ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 59082 , ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 59083 , ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 59084 , ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 59085 , ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 59086 , ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 59087 , ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 59073 , ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 59074 , ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 59075 , ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 59076 , ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 59077 , ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 59078 , ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 59079 , ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 59080 , ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 59081 , ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 59088 , ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 59098 , ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 59099 , ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 59100 , ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 59101 , ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 59102 , ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 59103 , ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 59089 , ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 59090 , ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 59091 , ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 59092 , ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 59093 , ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 59094 , ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 59095 , ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 59096 , ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 59097 , ARM64_SYSREG_AMEVTYPER00_EL0 = 57008 , ARM64_SYSREG_AMEVTYPER01_EL0 = 57009 , ARM64_SYSREG_AMEVTYPER02_EL0 = 57010 , ARM64_SYSREG_AMEVTYPER03_EL0 = 57011 , ARM64_SYSREG_AMEVTYPER10_EL0 = 57072 , ARM64_SYSREG_AMEVTYPER110_EL0 = 57082 , ARM64_SYSREG_AMEVTYPER111_EL0 = 57083 , ARM64_SYSREG_AMEVTYPER112_EL0 = 57084 , ARM64_SYSREG_AMEVTYPER113_EL0 = 57085 , ARM64_SYSREG_AMEVTYPER114_EL0 = 57086 , ARM64_SYSREG_AMEVTYPER115_EL0 = 57087 , ARM64_SYSREG_AMEVTYPER11_EL0 = 57073 , ARM64_SYSREG_AMEVTYPER12_EL0 = 57074 , ARM64_SYSREG_AMEVTYPER13_EL0 = 57075 , ARM64_SYSREG_AMEVTYPER14_EL0 = 57076 , ARM64_SYSREG_AMEVTYPER15_EL0 = 57077 , ARM64_SYSREG_AMEVTYPER16_EL0 = 57078 , ARM64_SYSREG_AMEVTYPER17_EL0 = 57079 , ARM64_SYSREG_AMEVTYPER18_EL0 = 57080 , ARM64_SYSREG_AMEVTYPER19_EL0 = 57081 , ARM64_SYSREG_AMUSERENR_EL0 = 56979 , ARM64_SYSREG_APDAKEYHI_EL1 = 49425 , ARM64_SYSREG_APDAKEYLO_EL1 = 49424 , ARM64_SYSREG_APDBKEYHI_EL1 = 49427 , ARM64_SYSREG_APDBKEYLO_EL1 = 49426 , ARM64_SYSREG_APGAKEYHI_EL1 = 49433 , ARM64_SYSREG_APGAKEYLO_EL1 = 49432 , ARM64_SYSREG_APIAKEYHI_EL1 = 49417 , ARM64_SYSREG_APIAKEYLO_EL1 = 49416 , ARM64_SYSREG_APIBKEYHI_EL1 = 49419 , ARM64_SYSREG_APIBKEYLO_EL1 = 49418 , ARM64_SYSREG_BRBCR_EL1 = 35968 , ARM64_SYSREG_BRBCR_EL12 = 44160 , ARM64_SYSREG_BRBCR_EL2 = 42112 , ARM64_SYSREG_BRBFCR_EL1 = 35969 , ARM64_SYSREG_BRBIDR0_EL1 = 35984 , ARM64_SYSREG_BRBINF0_EL1 = 35840 , ARM64_SYSREG_BRBINF10_EL1 = 35920 , ARM64_SYSREG_BRBINF11_EL1 = 35928 , ARM64_SYSREG_BRBINF12_EL1 = 35936 , ARM64_SYSREG_BRBINF13_EL1 = 35944 , ARM64_SYSREG_BRBINF14_EL1 = 35952 , ARM64_SYSREG_BRBINF15_EL1 = 35960 , ARM64_SYSREG_BRBINF16_EL1 = 35844 , ARM64_SYSREG_BRBINF17_EL1 = 35852 , ARM64_SYSREG_BRBINF18_EL1 = 35860 , ARM64_SYSREG_BRBINF19_EL1 = 35868 , ARM64_SYSREG_BRBINF1_EL1 = 35848 , ARM64_SYSREG_BRBINF20_EL1 = 35876 , ARM64_SYSREG_BRBINF21_EL1 = 35884 , ARM64_SYSREG_BRBINF22_EL1 = 35892 , ARM64_SYSREG_BRBINF23_EL1 = 35900 , ARM64_SYSREG_BRBINF24_EL1 = 35908 , ARM64_SYSREG_BRBINF25_EL1 = 35916 , ARM64_SYSREG_BRBINF26_EL1 = 35924 , ARM64_SYSREG_BRBINF27_EL1 = 35932 , ARM64_SYSREG_BRBINF28_EL1 = 35940 , ARM64_SYSREG_BRBINF29_EL1 = 35948 , ARM64_SYSREG_BRBINF2_EL1 = 35856 , ARM64_SYSREG_BRBINF30_EL1 = 35956 , ARM64_SYSREG_BRBINF31_EL1 = 35964 , ARM64_SYSREG_BRBINF3_EL1 = 35864 , ARM64_SYSREG_BRBINF4_EL1 = 35872 , ARM64_SYSREG_BRBINF5_EL1 = 35880 , ARM64_SYSREG_BRBINF6_EL1 = 35888 , ARM64_SYSREG_BRBINF7_EL1 = 35896 , ARM64_SYSREG_BRBINF8_EL1 = 35904 , ARM64_SYSREG_BRBINF9_EL1 = 35912 , ARM64_SYSREG_BRBINFINJ_EL1 = 35976 , ARM64_SYSREG_BRBSRC0_EL1 = 35841 , ARM64_SYSREG_BRBSRC10_EL1 = 35921 , ARM64_SYSREG_BRBSRC11_EL1 = 35929 , ARM64_SYSREG_BRBSRC12_EL1 = 35937 , ARM64_SYSREG_BRBSRC13_EL1 = 35945 , ARM64_SYSREG_BRBSRC14_EL1 = 35953 , ARM64_SYSREG_BRBSRC15_EL1 = 35961 , ARM64_SYSREG_BRBSRC16_EL1 = 35845 , ARM64_SYSREG_BRBSRC17_EL1 = 35853 , ARM64_SYSREG_BRBSRC18_EL1 = 35861 , ARM64_SYSREG_BRBSRC19_EL1 = 35869 , ARM64_SYSREG_BRBSRC1_EL1 = 35849 , ARM64_SYSREG_BRBSRC20_EL1 = 35877 , ARM64_SYSREG_BRBSRC21_EL1 = 35885 , ARM64_SYSREG_BRBSRC22_EL1 = 35893 , ARM64_SYSREG_BRBSRC23_EL1 = 35901 , ARM64_SYSREG_BRBSRC24_EL1 = 35909 , ARM64_SYSREG_BRBSRC25_EL1 = 35917 , ARM64_SYSREG_BRBSRC26_EL1 = 35925 , ARM64_SYSREG_BRBSRC27_EL1 = 35933 , ARM64_SYSREG_BRBSRC28_EL1 = 35941 , ARM64_SYSREG_BRBSRC29_EL1 = 35949 , ARM64_SYSREG_BRBSRC2_EL1 = 35857 , ARM64_SYSREG_BRBSRC30_EL1 = 35957 , ARM64_SYSREG_BRBSRC31_EL1 = 35965 , ARM64_SYSREG_BRBSRC3_EL1 = 35865 , ARM64_SYSREG_BRBSRC4_EL1 = 35873 , ARM64_SYSREG_BRBSRC5_EL1 = 35881 , ARM64_SYSREG_BRBSRC6_EL1 = 35889 , ARM64_SYSREG_BRBSRC7_EL1 = 35897 , ARM64_SYSREG_BRBSRC8_EL1 = 35905 , ARM64_SYSREG_BRBSRC9_EL1 = 35913 , ARM64_SYSREG_BRBSRCINJ_EL1 = 35977 , ARM64_SYSREG_BRBTGT0_EL1 = 35842 , ARM64_SYSREG_BRBTGT10_EL1 = 35922 , ARM64_SYSREG_BRBTGT11_EL1 = 35930 , ARM64_SYSREG_BRBTGT12_EL1 = 35938 , ARM64_SYSREG_BRBTGT13_EL1 = 35946 , ARM64_SYSREG_BRBTGT14_EL1 = 35954 , ARM64_SYSREG_BRBTGT15_EL1 = 35962 , ARM64_SYSREG_BRBTGT16_EL1 = 35846 , ARM64_SYSREG_BRBTGT17_EL1 = 35854 , ARM64_SYSREG_BRBTGT18_EL1 = 35862 , ARM64_SYSREG_BRBTGT19_EL1 = 35870 , ARM64_SYSREG_BRBTGT1_EL1 = 35850 , ARM64_SYSREG_BRBTGT20_EL1 = 35878 , ARM64_SYSREG_BRBTGT21_EL1 = 35886 , ARM64_SYSREG_BRBTGT22_EL1 = 35894 , ARM64_SYSREG_BRBTGT23_EL1 = 35902 , ARM64_SYSREG_BRBTGT24_EL1 = 35910 , ARM64_SYSREG_BRBTGT25_EL1 = 35918 , ARM64_SYSREG_BRBTGT26_EL1 = 35926 , ARM64_SYSREG_BRBTGT27_EL1 = 35934 , ARM64_SYSREG_BRBTGT28_EL1 = 35942 , ARM64_SYSREG_BRBTGT29_EL1 = 35950 , ARM64_SYSREG_BRBTGT2_EL1 = 35858 , ARM64_SYSREG_BRBTGT30_EL1 = 35958 , ARM64_SYSREG_BRBTGT31_EL1 = 35966 , ARM64_SYSREG_BRBTGT3_EL1 = 35866 , ARM64_SYSREG_BRBTGT4_EL1 = 35874 , ARM64_SYSREG_BRBTGT5_EL1 = 35882 , ARM64_SYSREG_BRBTGT6_EL1 = 35890 , ARM64_SYSREG_BRBTGT7_EL1 = 35898 , ARM64_SYSREG_BRBTGT8_EL1 = 35906 , ARM64_SYSREG_BRBTGT9_EL1 = 35914 , ARM64_SYSREG_BRBTGTINJ_EL1 = 35978 , ARM64_SYSREG_BRBTS_EL1 = 35970 , ARM64_SYSREG_CCSIDR2_EL1 = 51202 , ARM64_SYSREG_CCSIDR_EL1 = 51200 , ARM64_SYSREG_CLIDR_EL1 = 51201 , ARM64_SYSREG_CNTFRQ_EL0 = 57088 , ARM64_SYSREG_CNTHCTL_EL2 = 59144 , ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177 , ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178 , ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176 , ARM64_SYSREG_CNTHP_CTL_EL2 = 59153 , ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154 , ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152 , ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169 , ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170 , ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168 , ARM64_SYSREG_CNTHV_CTL_EL2 = 59161 , ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162 , ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160 , ARM64_SYSREG_CNTISCALE_EL2 = 59141 , ARM64_SYSREG_CNTKCTL_EL1 = 50952 , ARM64_SYSREG_CNTKCTL_EL12 = 61192 , ARM64_SYSREG_CNTPCTSS_EL0 = 57093 , ARM64_SYSREG_CNTPCT_EL0 = 57089 , ARM64_SYSREG_CNTPOFF_EL2 = 59142 , ARM64_SYSREG_CNTPS_CTL_EL1 = 65297 , ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298 , ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296 , ARM64_SYSREG_CNTP_CTL_EL0 = 57105 , ARM64_SYSREG_CNTP_CTL_EL02 = 61201 , ARM64_SYSREG_CNTP_CVAL_EL0 = 57106 , ARM64_SYSREG_CNTP_CVAL_EL02 = 61202 , ARM64_SYSREG_CNTP_TVAL_EL0 = 57104 , ARM64_SYSREG_CNTP_TVAL_EL02 = 61200 , ARM64_SYSREG_CNTSCALE_EL2 = 59140 , ARM64_SYSREG_CNTVCTSS_EL0 = 57094 , ARM64_SYSREG_CNTVCT_EL0 = 57090 , ARM64_SYSREG_CNTVFRQ_EL2 = 59143 , ARM64_SYSREG_CNTVOFF_EL2 = 59139 , ARM64_SYSREG_CNTV_CTL_EL0 = 57113 , ARM64_SYSREG_CNTV_CTL_EL02 = 61209 , ARM64_SYSREG_CNTV_CVAL_EL0 = 57114 , ARM64_SYSREG_CNTV_CVAL_EL02 = 61210 , ARM64_SYSREG_CNTV_TVAL_EL0 = 57112 , ARM64_SYSREG_CNTV_TVAL_EL02 = 61208 , ARM64_SYSREG_CONTEXTIDR_EL1 = 50817 , ARM64_SYSREG_CONTEXTIDR_EL12 = 61057 , ARM64_SYSREG_CONTEXTIDR_EL2 = 59009 , ARM64_SYSREG_CPACR_EL1 = 49282 , ARM64_SYSREG_CPACR_EL12 = 59522 , ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424 , ARM64_SYSREG_CPTR_EL2 = 57482 , ARM64_SYSREG_CPTR_EL3 = 61578 , ARM64_SYSREG_CSSELR_EL1 = 53248 , ARM64_SYSREG_CTR_EL0 = 55297 , ARM64_SYSREG_CURRENTEL = 49682 , ARM64_SYSREG_DACR32_EL2 = 57728 , ARM64_SYSREG_DAIF = 55825 , ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782 , ARM64_SYSREG_DBGBCR0_EL1 = 32773 , ARM64_SYSREG_DBGBCR10_EL1 = 32853 , ARM64_SYSREG_DBGBCR11_EL1 = 32861 , ARM64_SYSREG_DBGBCR12_EL1 = 32869 , ARM64_SYSREG_DBGBCR13_EL1 = 32877 , ARM64_SYSREG_DBGBCR14_EL1 = 32885 , ARM64_SYSREG_DBGBCR15_EL1 = 32893 , ARM64_SYSREG_DBGBCR1_EL1 = 32781 , ARM64_SYSREG_DBGBCR2_EL1 = 32789 , ARM64_SYSREG_DBGBCR3_EL1 = 32797 , ARM64_SYSREG_DBGBCR4_EL1 = 32805 , ARM64_SYSREG_DBGBCR5_EL1 = 32813 , ARM64_SYSREG_DBGBCR6_EL1 = 32821 , ARM64_SYSREG_DBGBCR7_EL1 = 32829 , ARM64_SYSREG_DBGBCR8_EL1 = 32837 , ARM64_SYSREG_DBGBCR9_EL1 = 32845 , ARM64_SYSREG_DBGBVR0_EL1 = 32772 , ARM64_SYSREG_DBGBVR10_EL1 = 32852 , ARM64_SYSREG_DBGBVR11_EL1 = 32860 , ARM64_SYSREG_DBGBVR12_EL1 = 32868 , ARM64_SYSREG_DBGBVR13_EL1 = 32876 , ARM64_SYSREG_DBGBVR14_EL1 = 32884 , ARM64_SYSREG_DBGBVR15_EL1 = 32892 , ARM64_SYSREG_DBGBVR1_EL1 = 32780 , ARM64_SYSREG_DBGBVR2_EL1 = 32788 , ARM64_SYSREG_DBGBVR3_EL1 = 32796 , ARM64_SYSREG_DBGBVR4_EL1 = 32804 , ARM64_SYSREG_DBGBVR5_EL1 = 32812 , ARM64_SYSREG_DBGBVR6_EL1 = 32820 , ARM64_SYSREG_DBGBVR7_EL1 = 32828 , ARM64_SYSREG_DBGBVR8_EL1 = 32836 , ARM64_SYSREG_DBGBVR9_EL1 = 32844 , ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742 , ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734 , ARM64_SYSREG_DBGDTRRX_EL0 = 38952 , ARM64_SYSREG_DBGDTR_EL0 = 38944 , ARM64_SYSREG_DBGPRCR_EL1 = 32932 , ARM64_SYSREG_DBGVCR32_EL2 = 41016 , ARM64_SYSREG_DBGWCR0_EL1 = 32775 , ARM64_SYSREG_DBGWCR10_EL1 = 32855 , ARM64_SYSREG_DBGWCR11_EL1 = 32863 , ARM64_SYSREG_DBGWCR12_EL1 = 32871 , ARM64_SYSREG_DBGWCR13_EL1 = 32879 , ARM64_SYSREG_DBGWCR14_EL1 = 32887 , ARM64_SYSREG_DBGWCR15_EL1 = 32895 , ARM64_SYSREG_DBGWCR1_EL1 = 32783 , ARM64_SYSREG_DBGWCR2_EL1 = 32791 , ARM64_SYSREG_DBGWCR3_EL1 = 32799 , ARM64_SYSREG_DBGWCR4_EL1 = 32807 , ARM64_SYSREG_DBGWCR5_EL1 = 32815 , ARM64_SYSREG_DBGWCR6_EL1 = 32823 , ARM64_SYSREG_DBGWCR7_EL1 = 32831 , ARM64_SYSREG_DBGWCR8_EL1 = 32839 , ARM64_SYSREG_DBGWCR9_EL1 = 32847 , ARM64_SYSREG_DBGWVR0_EL1 = 32774 , ARM64_SYSREG_DBGWVR10_EL1 = 32854 , ARM64_SYSREG_DBGWVR11_EL1 = 32862 , ARM64_SYSREG_DBGWVR12_EL1 = 32870 , ARM64_SYSREG_DBGWVR13_EL1 = 32878 , ARM64_SYSREG_DBGWVR14_EL1 = 32886 , ARM64_SYSREG_DBGWVR15_EL1 = 32894 , ARM64_SYSREG_DBGWVR1_EL1 = 32782 , ARM64_SYSREG_DBGWVR2_EL1 = 32790 , ARM64_SYSREG_DBGWVR3_EL1 = 32798 , ARM64_SYSREG_DBGWVR4_EL1 = 32806 , ARM64_SYSREG_DBGWVR5_EL1 = 32814 , ARM64_SYSREG_DBGWVR6_EL1 = 32822 , ARM64_SYSREG_DBGWVR7_EL1 = 32830 , ARM64_SYSREG_DBGWVR8_EL1 = 32838 , ARM64_SYSREG_DBGWVR9_EL1 = 32846 , ARM64_SYSREG_DCZID_EL0 = 55303 , ARM64_SYSREG_DISR_EL1 = 50697 , ARM64_SYSREG_DIT = 55829 , ARM64_SYSREG_DLR_EL0 = 55849 , ARM64_SYSREG_DSPSR_EL0 = 55848 , ARM64_SYSREG_ELR_EL1 = 49665 , ARM64_SYSREG_ELR_EL12 = 59905 , ARM64_SYSREG_ELR_EL2 = 57857 , ARM64_SYSREG_ELR_EL3 = 61953 , ARM64_SYSREG_ERRIDR_EL1 = 49816 , ARM64_SYSREG_ERRSELR_EL1 = 49817 , ARM64_SYSREG_ERXADDR_EL1 = 49827 , ARM64_SYSREG_ERXCTLR_EL1 = 49825 , ARM64_SYSREG_ERXFR_EL1 = 49824 , ARM64_SYSREG_ERXMISC0_EL1 = 49832 , ARM64_SYSREG_ERXMISC1_EL1 = 49833 , ARM64_SYSREG_ERXMISC2_EL1 = 49834 , ARM64_SYSREG_ERXMISC3_EL1 = 49835 , ARM64_SYSREG_ERXPFGCDN_EL1 = 49830 , ARM64_SYSREG_ERXPFGCTL_EL1 = 49829 , ARM64_SYSREG_ERXPFGF_EL1 = 49828 , ARM64_SYSREG_ERXSTATUS_EL1 = 49826 , ARM64_SYSREG_ESR_EL1 = 49808 , ARM64_SYSREG_ESR_EL12 = 60048 , ARM64_SYSREG_ESR_EL2 = 58000 , ARM64_SYSREG_ESR_EL3 = 62096 , ARM64_SYSREG_FAR_EL1 = 49920 , ARM64_SYSREG_FAR_EL12 = 60160 , ARM64_SYSREG_FAR_EL2 = 58112 , ARM64_SYSREG_FAR_EL3 = 62208 , ARM64_SYSREG_FPCR = 55840 , ARM64_SYSREG_FPEXC32_EL2 = 58008 , ARM64_SYSREG_FPSR = 55841 , ARM64_SYSREG_GCR_EL1 = 49286 , ARM64_SYSREG_GMID_EL1 = 51204 , ARM64_SYSREG_GPCCR_EL3 = 61710 , ARM64_SYSREG_GPTBR_EL3 = 61708 , ARM64_SYSREG_HACR_EL2 = 57487 , ARM64_SYSREG_HCRX_EL2 = 57490 , ARM64_SYSREG_HCR_EL2 = 57480 , ARM64_SYSREG_HDFGRTR_EL2 = 57740 , ARM64_SYSREG_HDFGWTR_EL2 = 57741 , ARM64_SYSREG_HFGITR_EL2 = 57486 , ARM64_SYSREG_HFGRTR_EL2 = 57484 , ARM64_SYSREG_HFGWTR_EL2 = 57485 , ARM64_SYSREG_HPFAR_EL2 = 58116 , ARM64_SYSREG_HSTR_EL2 = 57483 , ARM64_SYSREG_ICC_AP0R0_EL1 = 50756 , ARM64_SYSREG_ICC_AP0R1_EL1 = 50757 , ARM64_SYSREG_ICC_AP0R2_EL1 = 50758 , ARM64_SYSREG_ICC_AP0R3_EL1 = 50759 , ARM64_SYSREG_ICC_AP1R0_EL1 = 50760 , ARM64_SYSREG_ICC_AP1R1_EL1 = 50761 , ARM64_SYSREG_ICC_AP1R2_EL1 = 50762 , ARM64_SYSREG_ICC_AP1R3_EL1 = 50763 , ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782 , ARM64_SYSREG_ICC_BPR0_EL1 = 50755 , ARM64_SYSREG_ICC_BPR1_EL1 = 50787 , ARM64_SYSREG_ICC_CTLR_EL1 = 50788 , ARM64_SYSREG_ICC_CTLR_EL3 = 63076 , ARM64_SYSREG_ICC_DIR_EL1 = 50777 , ARM64_SYSREG_ICC_EOIR0_EL1 = 50753 , ARM64_SYSREG_ICC_EOIR1_EL1 = 50785 , ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754 , ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786 , ARM64_SYSREG_ICC_IAR0_EL1 = 50752 , ARM64_SYSREG_ICC_IAR1_EL1 = 50784 , ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790 , ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791 , ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079 , ARM64_SYSREG_ICC_PMR_EL1 = 49712 , ARM64_SYSREG_ICC_RPR_EL1 = 50779 , ARM64_SYSREG_ICC_SGI0R_EL1 = 50783 , ARM64_SYSREG_ICC_SGI1R_EL1 = 50781 , ARM64_SYSREG_ICC_SRE_EL1 = 50789 , ARM64_SYSREG_ICC_SRE_EL2 = 58957 , ARM64_SYSREG_ICC_SRE_EL3 = 63077 , ARM64_SYSREG_ICH_AP0R0_EL2 = 58944 , ARM64_SYSREG_ICH_AP0R1_EL2 = 58945 , ARM64_SYSREG_ICH_AP0R2_EL2 = 58946 , ARM64_SYSREG_ICH_AP0R3_EL2 = 58947 , ARM64_SYSREG_ICH_AP1R0_EL2 = 58952 , ARM64_SYSREG_ICH_AP1R1_EL2 = 58953 , ARM64_SYSREG_ICH_AP1R2_EL2 = 58954 , ARM64_SYSREG_ICH_AP1R3_EL2 = 58955 , ARM64_SYSREG_ICH_EISR_EL2 = 58971 , ARM64_SYSREG_ICH_ELRSR_EL2 = 58973 , ARM64_SYSREG_ICH_HCR_EL2 = 58968 , ARM64_SYSREG_ICH_LR0_EL2 = 58976 , ARM64_SYSREG_ICH_LR10_EL2 = 58986 , ARM64_SYSREG_ICH_LR11_EL2 = 58987 , ARM64_SYSREG_ICH_LR12_EL2 = 58988 , ARM64_SYSREG_ICH_LR13_EL2 = 58989 , ARM64_SYSREG_ICH_LR14_EL2 = 58990 , ARM64_SYSREG_ICH_LR15_EL2 = 58991 , ARM64_SYSREG_ICH_LR1_EL2 = 58977 , ARM64_SYSREG_ICH_LR2_EL2 = 58978 , ARM64_SYSREG_ICH_LR3_EL2 = 58979 , ARM64_SYSREG_ICH_LR4_EL2 = 58980 , ARM64_SYSREG_ICH_LR5_EL2 = 58981 , ARM64_SYSREG_ICH_LR6_EL2 = 58982 , ARM64_SYSREG_ICH_LR7_EL2 = 58983 , ARM64_SYSREG_ICH_LR8_EL2 = 58984 , ARM64_SYSREG_ICH_LR9_EL2 = 58985 , ARM64_SYSREG_ICH_MISR_EL2 = 58970 , ARM64_SYSREG_ICH_VMCR_EL2 = 58975 , ARM64_SYSREG_ICH_VTR_EL2 = 58969 , ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196 , ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197 , ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192 , ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193 , ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200 , ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201 , ARM64_SYSREG_ID_AA64ISAR2_EL1 = 49202 , ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208 , ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209 , ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210 , ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184 , ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185 , ARM64_SYSREG_ID_AA64SMFR0_EL1 = 49189 , ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188 , ARM64_SYSREG_ID_AFR0_EL1 = 49163 , ARM64_SYSREG_ID_DFR0_EL1 = 49162 , ARM64_SYSREG_ID_ISAR0_EL1 = 49168 , ARM64_SYSREG_ID_ISAR1_EL1 = 49169 , ARM64_SYSREG_ID_ISAR2_EL1 = 49170 , ARM64_SYSREG_ID_ISAR3_EL1 = 49171 , ARM64_SYSREG_ID_ISAR4_EL1 = 49172 , ARM64_SYSREG_ID_ISAR5_EL1 = 49173 , ARM64_SYSREG_ID_ISAR6_EL1 = 49175 , ARM64_SYSREG_ID_MMFR0_EL1 = 49164 , ARM64_SYSREG_ID_MMFR1_EL1 = 49165 , ARM64_SYSREG_ID_MMFR2_EL1 = 49166 , ARM64_SYSREG_ID_MMFR3_EL1 = 49167 , ARM64_SYSREG_ID_MMFR4_EL1 = 49174 , ARM64_SYSREG_ID_MMFR5_EL1 = 49182 , ARM64_SYSREG_ID_PFR0_EL1 = 49160 , ARM64_SYSREG_ID_PFR1_EL1 = 49161 , ARM64_SYSREG_ID_PFR2_EL1 = 49180 , ARM64_SYSREG_IFSR32_EL2 = 57985 , ARM64_SYSREG_ISR_EL1 = 50696 , ARM64_SYSREG_LORC_EL1 = 50467 , ARM64_SYSREG_LOREA_EL1 = 50465 , ARM64_SYSREG_LORID_EL1 = 50471 , ARM64_SYSREG_LORN_EL1 = 50466 , ARM64_SYSREG_LORSA_EL1 = 50464 , ARM64_SYSREG_MAIR_EL1 = 50448 , ARM64_SYSREG_MAIR_EL12 = 60688 , ARM64_SYSREG_MAIR_EL2 = 58640 , ARM64_SYSREG_MAIR_EL3 = 62736 , ARM64_SYSREG_MDCCINT_EL1 = 32784 , ARM64_SYSREG_MDCCSR_EL0 = 38920 , ARM64_SYSREG_MDCR_EL2 = 57481 , ARM64_SYSREG_MDCR_EL3 = 61593 , ARM64_SYSREG_MDRAR_EL1 = 32896 , ARM64_SYSREG_MDSCR_EL1 = 32786 , ARM64_SYSREG_MFAR_EL3 = 62213 , ARM64_SYSREG_MIDR_EL1 = 49152 , ARM64_SYSREG_MPAM0_EL1 = 50473 , ARM64_SYSREG_MPAM1_EL1 = 50472 , ARM64_SYSREG_MPAM1_EL12 = 60712 , ARM64_SYSREG_MPAM2_EL2 = 58664 , ARM64_SYSREG_MPAM3_EL3 = 62760 , ARM64_SYSREG_MPAMHCR_EL2 = 58656 , ARM64_SYSREG_MPAMIDR_EL1 = 50468 , ARM64_SYSREG_MPAMSM_EL1 = 50475 , ARM64_SYSREG_MPAMVPM0_EL2 = 58672 , ARM64_SYSREG_MPAMVPM1_EL2 = 58673 , ARM64_SYSREG_MPAMVPM2_EL2 = 58674 , ARM64_SYSREG_MPAMVPM3_EL2 = 58675 , ARM64_SYSREG_MPAMVPM4_EL2 = 58676 , ARM64_SYSREG_MPAMVPM5_EL2 = 58677 , ARM64_SYSREG_MPAMVPM6_EL2 = 58678 , ARM64_SYSREG_MPAMVPM7_EL2 = 58679 , ARM64_SYSREG_MPAMVPMV_EL2 = 58657 , ARM64_SYSREG_MPIDR_EL1 = 49157 , ARM64_SYSREG_MPUIR_EL1 = 49156 , ARM64_SYSREG_MPUIR_EL2 = 57348 , ARM64_SYSREG_MVFR0_EL1 = 49176 , ARM64_SYSREG_MVFR1_EL1 = 49177 , ARM64_SYSREG_MVFR2_EL1 = 49178 , ARM64_SYSREG_NZCV = 55824 , ARM64_SYSREG_OSDLR_EL1 = 32924 , ARM64_SYSREG_OSDTRRX_EL1 = 32770 , ARM64_SYSREG_OSDTRTX_EL1 = 32794 , ARM64_SYSREG_OSECCR_EL1 = 32818 , ARM64_SYSREG_OSLAR_EL1 = 32900 , ARM64_SYSREG_OSLSR_EL1 = 32908 , ARM64_SYSREG_PAN = 49683 , ARM64_SYSREG_PAR_EL1 = 50080 , ARM64_SYSREG_PMBIDR_EL1 = 50391 , ARM64_SYSREG_PMBLIMITR_EL1 = 50384 , ARM64_SYSREG_PMBPTR_EL1 = 50385 , ARM64_SYSREG_PMBSR_EL1 = 50387 , ARM64_SYSREG_PMCCFILTR_EL0 = 57215 , ARM64_SYSREG_PMCCNTR_EL0 = 56552 , ARM64_SYSREG_PMCEID0_EL0 = 56550 , ARM64_SYSREG_PMCEID1_EL0 = 56551 , ARM64_SYSREG_PMCNTENCLR_EL0 = 56546 , ARM64_SYSREG_PMCNTENSET_EL0 = 56545 , ARM64_SYSREG_PMCR_EL0 = 56544 , ARM64_SYSREG_PMEVCNTR0_EL0 = 57152 , ARM64_SYSREG_PMEVCNTR10_EL0 = 57162 , ARM64_SYSREG_PMEVCNTR11_EL0 = 57163 , ARM64_SYSREG_PMEVCNTR12_EL0 = 57164 , ARM64_SYSREG_PMEVCNTR13_EL0 = 57165 , ARM64_SYSREG_PMEVCNTR14_EL0 = 57166 , ARM64_SYSREG_PMEVCNTR15_EL0 = 57167 , ARM64_SYSREG_PMEVCNTR16_EL0 = 57168 , ARM64_SYSREG_PMEVCNTR17_EL0 = 57169 , ARM64_SYSREG_PMEVCNTR18_EL0 = 57170 , ARM64_SYSREG_PMEVCNTR19_EL0 = 57171 , ARM64_SYSREG_PMEVCNTR1_EL0 = 57153 , ARM64_SYSREG_PMEVCNTR20_EL0 = 57172 , ARM64_SYSREG_PMEVCNTR21_EL0 = 57173 , ARM64_SYSREG_PMEVCNTR22_EL0 = 57174 , ARM64_SYSREG_PMEVCNTR23_EL0 = 57175 , ARM64_SYSREG_PMEVCNTR24_EL0 = 57176 , ARM64_SYSREG_PMEVCNTR25_EL0 = 57177 , ARM64_SYSREG_PMEVCNTR26_EL0 = 57178 , ARM64_SYSREG_PMEVCNTR27_EL0 = 57179 , ARM64_SYSREG_PMEVCNTR28_EL0 = 57180 , ARM64_SYSREG_PMEVCNTR29_EL0 = 57181 , ARM64_SYSREG_PMEVCNTR2_EL0 = 57154 , ARM64_SYSREG_PMEVCNTR30_EL0 = 57182 , ARM64_SYSREG_PMEVCNTR3_EL0 = 57155 , ARM64_SYSREG_PMEVCNTR4_EL0 = 57156 , ARM64_SYSREG_PMEVCNTR5_EL0 = 57157 , ARM64_SYSREG_PMEVCNTR6_EL0 = 57158 , ARM64_SYSREG_PMEVCNTR7_EL0 = 57159 , ARM64_SYSREG_PMEVCNTR8_EL0 = 57160 , ARM64_SYSREG_PMEVCNTR9_EL0 = 57161 , ARM64_SYSREG_PMEVTYPER0_EL0 = 57184 , ARM64_SYSREG_PMEVTYPER10_EL0 = 57194 , ARM64_SYSREG_PMEVTYPER11_EL0 = 57195 , ARM64_SYSREG_PMEVTYPER12_EL0 = 57196 , ARM64_SYSREG_PMEVTYPER13_EL0 = 57197 , ARM64_SYSREG_PMEVTYPER14_EL0 = 57198 , ARM64_SYSREG_PMEVTYPER15_EL0 = 57199 , ARM64_SYSREG_PMEVTYPER16_EL0 = 57200 , ARM64_SYSREG_PMEVTYPER17_EL0 = 57201 , ARM64_SYSREG_PMEVTYPER18_EL0 = 57202 , ARM64_SYSREG_PMEVTYPER19_EL0 = 57203 , ARM64_SYSREG_PMEVTYPER1_EL0 = 57185 , ARM64_SYSREG_PMEVTYPER20_EL0 = 57204 , ARM64_SYSREG_PMEVTYPER21_EL0 = 57205 , ARM64_SYSREG_PMEVTYPER22_EL0 = 57206 , ARM64_SYSREG_PMEVTYPER23_EL0 = 57207 , ARM64_SYSREG_PMEVTYPER24_EL0 = 57208 , ARM64_SYSREG_PMEVTYPER25_EL0 = 57209 , ARM64_SYSREG_PMEVTYPER26_EL0 = 57210 , ARM64_SYSREG_PMEVTYPER27_EL0 = 57211 , ARM64_SYSREG_PMEVTYPER28_EL0 = 57212 , ARM64_SYSREG_PMEVTYPER29_EL0 = 57213 , ARM64_SYSREG_PMEVTYPER2_EL0 = 57186 , ARM64_SYSREG_PMEVTYPER30_EL0 = 57214 , ARM64_SYSREG_PMEVTYPER3_EL0 = 57187 , ARM64_SYSREG_PMEVTYPER4_EL0 = 57188 , ARM64_SYSREG_PMEVTYPER5_EL0 = 57189 , ARM64_SYSREG_PMEVTYPER6_EL0 = 57190 , ARM64_SYSREG_PMEVTYPER7_EL0 = 57191 , ARM64_SYSREG_PMEVTYPER8_EL0 = 57192 , ARM64_SYSREG_PMEVTYPER9_EL0 = 57193 , ARM64_SYSREG_PMINTENCLR_EL1 = 50418 , ARM64_SYSREG_PMINTENSET_EL1 = 50417 , ARM64_SYSREG_PMMIR_EL1 = 50422 , ARM64_SYSREG_PMOVSCLR_EL0 = 56547 , ARM64_SYSREG_PMOVSSET_EL0 = 56563 , ARM64_SYSREG_PMSCR_EL1 = 50376 , ARM64_SYSREG_PMSCR_EL12 = 60616 , ARM64_SYSREG_PMSCR_EL2 = 58568 , ARM64_SYSREG_PMSELR_EL0 = 56549 , ARM64_SYSREG_PMSEVFR_EL1 = 50381 , ARM64_SYSREG_PMSFCR_EL1 = 50380 , ARM64_SYSREG_PMSICR_EL1 = 50378 , ARM64_SYSREG_PMSIDR_EL1 = 50383 , ARM64_SYSREG_PMSIRR_EL1 = 50379 , ARM64_SYSREG_PMSLATFR_EL1 = 50382 , ARM64_SYSREG_PMSNEVFR_EL1 = 50377 , ARM64_SYSREG_PMSWINC_EL0 = 56548 , ARM64_SYSREG_PMUSERENR_EL0 = 56560 , ARM64_SYSREG_PMXEVCNTR_EL0 = 56554 , ARM64_SYSREG_PMXEVTYPER_EL0 = 56553 , ARM64_SYSREG_PRBAR10_EL1 = 50024 , ARM64_SYSREG_PRBAR10_EL2 = 58216 , ARM64_SYSREG_PRBAR11_EL1 = 50028 , ARM64_SYSREG_PRBAR11_EL2 = 58220 , ARM64_SYSREG_PRBAR12_EL1 = 50032 , ARM64_SYSREG_PRBAR12_EL2 = 58224 , ARM64_SYSREG_PRBAR13_EL1 = 50036 , ARM64_SYSREG_PRBAR13_EL2 = 58228 , ARM64_SYSREG_PRBAR14_EL1 = 50040 , ARM64_SYSREG_PRBAR14_EL2 = 58232 , ARM64_SYSREG_PRBAR15_EL1 = 50044 , ARM64_SYSREG_PRBAR15_EL2 = 58236 , ARM64_SYSREG_PRBAR1_EL1 = 49988 , ARM64_SYSREG_PRBAR1_EL2 = 58180 , ARM64_SYSREG_PRBAR2_EL1 = 49992 , ARM64_SYSREG_PRBAR2_EL2 = 58184 , ARM64_SYSREG_PRBAR3_EL1 = 49996 , ARM64_SYSREG_PRBAR3_EL2 = 58188 , ARM64_SYSREG_PRBAR4_EL1 = 50000 , ARM64_SYSREG_PRBAR4_EL2 = 58192 , ARM64_SYSREG_PRBAR5_EL1 = 50004 , ARM64_SYSREG_PRBAR5_EL2 = 58196 , ARM64_SYSREG_PRBAR6_EL1 = 50008 , ARM64_SYSREG_PRBAR6_EL2 = 58200 , ARM64_SYSREG_PRBAR7_EL1 = 50012 , ARM64_SYSREG_PRBAR7_EL2 = 58204 , ARM64_SYSREG_PRBAR8_EL1 = 50016 , ARM64_SYSREG_PRBAR8_EL2 = 58208 , ARM64_SYSREG_PRBAR9_EL1 = 50020 , ARM64_SYSREG_PRBAR9_EL2 = 58212 , ARM64_SYSREG_PRBAR_EL1 = 49984 , ARM64_SYSREG_PRBAR_EL2 = 58176 , ARM64_SYSREG_PRENR_EL1 = 49929 , ARM64_SYSREG_PRENR_EL2 = 58121 , ARM64_SYSREG_PRLAR10_EL1 = 50025 , ARM64_SYSREG_PRLAR10_EL2 = 58217 , ARM64_SYSREG_PRLAR11_EL1 = 50029 , ARM64_SYSREG_PRLAR11_EL2 = 58221 , ARM64_SYSREG_PRLAR12_EL1 = 50033 , ARM64_SYSREG_PRLAR12_EL2 = 58225 , ARM64_SYSREG_PRLAR13_EL1 = 50037 , ARM64_SYSREG_PRLAR13_EL2 = 58229 , ARM64_SYSREG_PRLAR14_EL1 = 50041 , ARM64_SYSREG_PRLAR14_EL2 = 58233 , ARM64_SYSREG_PRLAR15_EL1 = 50045 , ARM64_SYSREG_PRLAR15_EL2 = 58237 , ARM64_SYSREG_PRLAR1_EL1 = 49989 , ARM64_SYSREG_PRLAR1_EL2 = 58181 , ARM64_SYSREG_PRLAR2_EL1 = 49993 , ARM64_SYSREG_PRLAR2_EL2 = 58185 , ARM64_SYSREG_PRLAR3_EL1 = 49997 , ARM64_SYSREG_PRLAR3_EL2 = 58189 , ARM64_SYSREG_PRLAR4_EL1 = 50001 , ARM64_SYSREG_PRLAR4_EL2 = 58193 , ARM64_SYSREG_PRLAR5_EL1 = 50005 , ARM64_SYSREG_PRLAR5_EL2 = 58197 , ARM64_SYSREG_PRLAR6_EL1 = 50009 , ARM64_SYSREG_PRLAR6_EL2 = 58201 , ARM64_SYSREG_PRLAR7_EL1 = 50013 , ARM64_SYSREG_PRLAR7_EL2 = 58205 , ARM64_SYSREG_PRLAR8_EL1 = 50017 , ARM64_SYSREG_PRLAR8_EL2 = 58209 , ARM64_SYSREG_PRLAR9_EL1 = 50021 , ARM64_SYSREG_PRLAR9_EL2 = 58213 , ARM64_SYSREG_PRLAR_EL1 = 49985 , ARM64_SYSREG_PRLAR_EL2 = 58177 , ARM64_SYSREG_PRSELR_EL1 = 49937 , ARM64_SYSREG_PRSELR_EL2 = 58129 , ARM64_SYSREG_REVIDR_EL1 = 49158 , ARM64_SYSREG_RGSR_EL1 = 49285 , ARM64_SYSREG_RMR_EL1 = 50690 , ARM64_SYSREG_RMR_EL2 = 58882 , ARM64_SYSREG_RMR_EL3 = 62978 , ARM64_SYSREG_RNDR = 55584 , ARM64_SYSREG_RNDRRS = 55585 , ARM64_SYSREG_RVBAR_EL1 = 50689 , ARM64_SYSREG_RVBAR_EL2 = 58881 , ARM64_SYSREG_RVBAR_EL3 = 62977 , ARM64_SYSREG_SCR_EL3 = 61576 , ARM64_SYSREG_SCTLR_EL1 = 49280 , ARM64_SYSREG_SCTLR_EL12 = 59520 , ARM64_SYSREG_SCTLR_EL2 = 57472 , ARM64_SYSREG_SCTLR_EL3 = 61568 , ARM64_SYSREG_SCXTNUM_EL0 = 56967 , ARM64_SYSREG_SCXTNUM_EL1 = 50823 , ARM64_SYSREG_SCXTNUM_EL12 = 61063 , ARM64_SYSREG_SCXTNUM_EL2 = 59015 , ARM64_SYSREG_SCXTNUM_EL3 = 63111 , ARM64_SYSREG_SDER32_EL2 = 57497 , ARM64_SYSREG_SDER32_EL3 = 61577 , ARM64_SYSREG_SMCR_EL1 = 49302 , ARM64_SYSREG_SMCR_EL12 = 59542 , ARM64_SYSREG_SMCR_EL2 = 57494 , ARM64_SYSREG_SMCR_EL3 = 61590 , ARM64_SYSREG_SMIDR_EL1 = 51206 , ARM64_SYSREG_SMPRIMAP_EL2 = 57493 , ARM64_SYSREG_SMPRI_EL1 = 49300 , ARM64_SYSREG_SPSEL = 49680 , ARM64_SYSREG_SPSR_ABT = 57881 , ARM64_SYSREG_SPSR_EL1 = 49664 , ARM64_SYSREG_SPSR_EL12 = 59904 , ARM64_SYSREG_SPSR_EL2 = 57856 , ARM64_SYSREG_SPSR_EL3 = 61952 , ARM64_SYSREG_SPSR_FIQ = 57883 , ARM64_SYSREG_SPSR_IRQ = 57880 , ARM64_SYSREG_SPSR_UND = 57882 , ARM64_SYSREG_SP_EL0 = 49672 , ARM64_SYSREG_SP_EL1 = 57864 , ARM64_SYSREG_SP_EL2 = 61960 , ARM64_SYSREG_SSBS = 55830 , ARM64_SYSREG_SVCR = 55826 , ARM64_SYSREG_TCO = 55831 , ARM64_SYSREG_TCR_EL1 = 49410 , ARM64_SYSREG_TCR_EL12 = 59650 , ARM64_SYSREG_TCR_EL2 = 57602 , ARM64_SYSREG_TCR_EL3 = 61698 , ARM64_SYSREG_TEECR32_EL1 = 36864 , ARM64_SYSREG_TEEHBR32_EL1 = 36992 , ARM64_SYSREG_TFSRE0_EL1 = 49841 , ARM64_SYSREG_TFSR_EL1 = 49840 , ARM64_SYSREG_TFSR_EL12 = 60080 , ARM64_SYSREG_TFSR_EL2 = 58032 , ARM64_SYSREG_TFSR_EL3 = 62128 , ARM64_SYSREG_TPIDR2_EL0 = 56965 , ARM64_SYSREG_TPIDRRO_EL0 = 56963 , ARM64_SYSREG_TPIDR_EL0 = 56962 , ARM64_SYSREG_TPIDR_EL1 = 50820 , ARM64_SYSREG_TPIDR_EL2 = 59010 , ARM64_SYSREG_TPIDR_EL3 = 63106 , ARM64_SYSREG_TRBBASER_EL1 = 50394 , ARM64_SYSREG_TRBIDR_EL1 = 50399 , ARM64_SYSREG_TRBLIMITR_EL1 = 50392 , ARM64_SYSREG_TRBMAR_EL1 = 50396 , ARM64_SYSREG_TRBPTR_EL1 = 50393 , ARM64_SYSREG_TRBSR_EL1 = 50395 , ARM64_SYSREG_TRBTRG_EL1 = 50398 , ARM64_SYSREG_TRCACATR0 = 35074 , ARM64_SYSREG_TRCACATR1 = 35090 , ARM64_SYSREG_TRCACATR10 = 35107 , ARM64_SYSREG_TRCACATR11 = 35123 , ARM64_SYSREG_TRCACATR12 = 35139 , ARM64_SYSREG_TRCACATR13 = 35155 , ARM64_SYSREG_TRCACATR14 = 35171 , ARM64_SYSREG_TRCACATR15 = 35187 , ARM64_SYSREG_TRCACATR2 = 35106 , ARM64_SYSREG_TRCACATR3 = 35122 , ARM64_SYSREG_TRCACATR4 = 35138 , ARM64_SYSREG_TRCACATR5 = 35154 , ARM64_SYSREG_TRCACATR6 = 35170 , ARM64_SYSREG_TRCACATR7 = 35186 , ARM64_SYSREG_TRCACATR8 = 35075 , ARM64_SYSREG_TRCACATR9 = 35091 , ARM64_SYSREG_TRCACVR0 = 35072 , ARM64_SYSREG_TRCACVR1 = 35088 , ARM64_SYSREG_TRCACVR10 = 35105 , ARM64_SYSREG_TRCACVR11 = 35121 , ARM64_SYSREG_TRCACVR12 = 35137 , ARM64_SYSREG_TRCACVR13 = 35153 , ARM64_SYSREG_TRCACVR14 = 35169 , ARM64_SYSREG_TRCACVR15 = 35185 , ARM64_SYSREG_TRCACVR2 = 35104 , ARM64_SYSREG_TRCACVR3 = 35120 , ARM64_SYSREG_TRCACVR4 = 35136 , ARM64_SYSREG_TRCACVR5 = 35152 , ARM64_SYSREG_TRCACVR6 = 35168 , ARM64_SYSREG_TRCACVR7 = 35184 , ARM64_SYSREG_TRCACVR8 = 35073 , ARM64_SYSREG_TRCACVR9 = 35089 , ARM64_SYSREG_TRCAUTHSTATUS = 35830 , ARM64_SYSREG_TRCAUXCTLR = 34864 , ARM64_SYSREG_TRCBBCTLR = 34936 , ARM64_SYSREG_TRCCCCTLR = 34928 , ARM64_SYSREG_TRCCIDCCTLR0 = 35202 , ARM64_SYSREG_TRCCIDCCTLR1 = 35210 , ARM64_SYSREG_TRCCIDCVR0 = 35200 , ARM64_SYSREG_TRCCIDCVR1 = 35216 , ARM64_SYSREG_TRCCIDCVR2 = 35232 , ARM64_SYSREG_TRCCIDCVR3 = 35248 , ARM64_SYSREG_TRCCIDCVR4 = 35264 , ARM64_SYSREG_TRCCIDCVR5 = 35280 , ARM64_SYSREG_TRCCIDCVR6 = 35296 , ARM64_SYSREG_TRCCIDCVR7 = 35312 , ARM64_SYSREG_TRCCIDR0 = 35815 , ARM64_SYSREG_TRCCIDR1 = 35823 , ARM64_SYSREG_TRCCIDR2 = 35831 , ARM64_SYSREG_TRCCIDR3 = 35839 , ARM64_SYSREG_TRCCLAIMCLR = 35790 , ARM64_SYSREG_TRCCLAIMSET = 35782 , ARM64_SYSREG_TRCCNTCTLR0 = 34853 , ARM64_SYSREG_TRCCNTCTLR1 = 34861 , ARM64_SYSREG_TRCCNTCTLR2 = 34869 , ARM64_SYSREG_TRCCNTCTLR3 = 34877 , ARM64_SYSREG_TRCCNTRLDVR0 = 34821 , ARM64_SYSREG_TRCCNTRLDVR1 = 34829 , ARM64_SYSREG_TRCCNTRLDVR2 = 34837 , ARM64_SYSREG_TRCCNTRLDVR3 = 34845 , ARM64_SYSREG_TRCCNTVR0 = 34885 , ARM64_SYSREG_TRCCNTVR1 = 34893 , ARM64_SYSREG_TRCCNTVR2 = 34901 , ARM64_SYSREG_TRCCNTVR3 = 34909 , ARM64_SYSREG_TRCCONFIGR = 34848 , ARM64_SYSREG_TRCDEVAFF0 = 35798 , ARM64_SYSREG_TRCDEVAFF1 = 35806 , ARM64_SYSREG_TRCDEVARCH = 35838 , ARM64_SYSREG_TRCDEVID = 35735 , ARM64_SYSREG_TRCDEVTYPE = 35743 , ARM64_SYSREG_TRCDVCMR0 = 35078 , ARM64_SYSREG_TRCDVCMR1 = 35110 , ARM64_SYSREG_TRCDVCMR2 = 35142 , ARM64_SYSREG_TRCDVCMR3 = 35174 , ARM64_SYSREG_TRCDVCMR4 = 35079 , ARM64_SYSREG_TRCDVCMR5 = 35111 , ARM64_SYSREG_TRCDVCMR6 = 35143 , ARM64_SYSREG_TRCDVCMR7 = 35175 , ARM64_SYSREG_TRCDVCVR0 = 35076 , ARM64_SYSREG_TRCDVCVR1 = 35108 , ARM64_SYSREG_TRCDVCVR2 = 35140 , ARM64_SYSREG_TRCDVCVR3 = 35172 , ARM64_SYSREG_TRCDVCVR4 = 35077 , ARM64_SYSREG_TRCDVCVR5 = 35109 , ARM64_SYSREG_TRCDVCVR6 = 35141 , ARM64_SYSREG_TRCDVCVR7 = 35173 , ARM64_SYSREG_TRCEVENTCTL0R = 34880 , ARM64_SYSREG_TRCEVENTCTL1R = 34888 , ARM64_SYSREG_TRCEXTINSELR = 34884 , ARM64_SYSREG_TRCEXTINSELR1 = 34892 , ARM64_SYSREG_TRCEXTINSELR2 = 34900 , ARM64_SYSREG_TRCEXTINSELR3 = 34908 , ARM64_SYSREG_TRCIDR0 = 34887 , ARM64_SYSREG_TRCIDR1 = 34895 , ARM64_SYSREG_TRCIDR10 = 34838 , ARM64_SYSREG_TRCIDR11 = 34846 , ARM64_SYSREG_TRCIDR12 = 34854 , ARM64_SYSREG_TRCIDR13 = 34862 , ARM64_SYSREG_TRCIDR2 = 34903 , ARM64_SYSREG_TRCIDR3 = 34911 , ARM64_SYSREG_TRCIDR4 = 34919 , ARM64_SYSREG_TRCIDR5 = 34927 , ARM64_SYSREG_TRCIDR6 = 34935 , ARM64_SYSREG_TRCIDR7 = 34943 , ARM64_SYSREG_TRCIDR8 = 34822 , ARM64_SYSREG_TRCIDR9 = 34830 , ARM64_SYSREG_TRCIMSPEC0 = 34823 , ARM64_SYSREG_TRCIMSPEC1 = 34831 , ARM64_SYSREG_TRCIMSPEC2 = 34839 , ARM64_SYSREG_TRCIMSPEC3 = 34847 , ARM64_SYSREG_TRCIMSPEC4 = 34855 , ARM64_SYSREG_TRCIMSPEC5 = 34863 , ARM64_SYSREG_TRCIMSPEC6 = 34871 , ARM64_SYSREG_TRCIMSPEC7 = 34879 , ARM64_SYSREG_TRCITCTRL = 35716 , ARM64_SYSREG_TRCLAR = 35814 , ARM64_SYSREG_TRCLSR = 35822 , ARM64_SYSREG_TRCOSLAR = 34948 , ARM64_SYSREG_TRCOSLSR = 34956 , ARM64_SYSREG_TRCPDCR = 34980 , ARM64_SYSREG_TRCPDSR = 34988 , ARM64_SYSREG_TRCPIDR0 = 35783 , ARM64_SYSREG_TRCPIDR1 = 35791 , ARM64_SYSREG_TRCPIDR2 = 35799 , ARM64_SYSREG_TRCPIDR3 = 35807 , ARM64_SYSREG_TRCPIDR4 = 35751 , ARM64_SYSREG_TRCPIDR5 = 35759 , ARM64_SYSREG_TRCPIDR6 = 35767 , ARM64_SYSREG_TRCPIDR7 = 35775 , ARM64_SYSREG_TRCPRGCTLR = 34824 , ARM64_SYSREG_TRCPROCSELR = 34832 , ARM64_SYSREG_TRCQCTLR = 34825 , ARM64_SYSREG_TRCRSCTLR10 = 35024 , ARM64_SYSREG_TRCRSCTLR11 = 35032 , ARM64_SYSREG_TRCRSCTLR12 = 35040 , ARM64_SYSREG_TRCRSCTLR13 = 35048 , ARM64_SYSREG_TRCRSCTLR14 = 35056 , ARM64_SYSREG_TRCRSCTLR15 = 35064 , ARM64_SYSREG_TRCRSCTLR16 = 34945 , ARM64_SYSREG_TRCRSCTLR17 = 34953 , ARM64_SYSREG_TRCRSCTLR18 = 34961 , ARM64_SYSREG_TRCRSCTLR19 = 34969 , ARM64_SYSREG_TRCRSCTLR2 = 34960 , ARM64_SYSREG_TRCRSCTLR20 = 34977 , ARM64_SYSREG_TRCRSCTLR21 = 34985 , ARM64_SYSREG_TRCRSCTLR22 = 34993 , ARM64_SYSREG_TRCRSCTLR23 = 35001 , ARM64_SYSREG_TRCRSCTLR24 = 35009 , ARM64_SYSREG_TRCRSCTLR25 = 35017 , ARM64_SYSREG_TRCRSCTLR26 = 35025 , ARM64_SYSREG_TRCRSCTLR27 = 35033 , ARM64_SYSREG_TRCRSCTLR28 = 35041 , ARM64_SYSREG_TRCRSCTLR29 = 35049 , ARM64_SYSREG_TRCRSCTLR3 = 34968 , ARM64_SYSREG_TRCRSCTLR30 = 35057 , ARM64_SYSREG_TRCRSCTLR31 = 35065 , ARM64_SYSREG_TRCRSCTLR4 = 34976 , ARM64_SYSREG_TRCRSCTLR5 = 34984 , ARM64_SYSREG_TRCRSCTLR6 = 34992 , ARM64_SYSREG_TRCRSCTLR7 = 35000 , ARM64_SYSREG_TRCRSCTLR8 = 35008 , ARM64_SYSREG_TRCRSCTLR9 = 35016 , ARM64_SYSREG_TRCRSR = 34896 , ARM64_SYSREG_TRCSEQEVR0 = 34820 , ARM64_SYSREG_TRCSEQEVR1 = 34828 , ARM64_SYSREG_TRCSEQEVR2 = 34836 , ARM64_SYSREG_TRCSEQRSTEVR = 34868 , ARM64_SYSREG_TRCSEQSTR = 34876 , ARM64_SYSREG_TRCSSCCR0 = 34946 , ARM64_SYSREG_TRCSSCCR1 = 34954 , ARM64_SYSREG_TRCSSCCR2 = 34962 , ARM64_SYSREG_TRCSSCCR3 = 34970 , ARM64_SYSREG_TRCSSCCR4 = 34978 , ARM64_SYSREG_TRCSSCCR5 = 34986 , ARM64_SYSREG_TRCSSCCR6 = 34994 , ARM64_SYSREG_TRCSSCCR7 = 35002 , ARM64_SYSREG_TRCSSCSR0 = 35010 , ARM64_SYSREG_TRCSSCSR1 = 35018 , ARM64_SYSREG_TRCSSCSR2 = 35026 , ARM64_SYSREG_TRCSSCSR3 = 35034 , ARM64_SYSREG_TRCSSCSR4 = 35042 , ARM64_SYSREG_TRCSSCSR5 = 35050 , ARM64_SYSREG_TRCSSCSR6 = 35058 , ARM64_SYSREG_TRCSSCSR7 = 35066 , ARM64_SYSREG_TRCSSPCICR0 = 34947 , ARM64_SYSREG_TRCSSPCICR1 = 34955 , ARM64_SYSREG_TRCSSPCICR2 = 34963 , ARM64_SYSREG_TRCSSPCICR3 = 34971 , ARM64_SYSREG_TRCSSPCICR4 = 34979 , ARM64_SYSREG_TRCSSPCICR5 = 34987 , ARM64_SYSREG_TRCSSPCICR6 = 34995 , ARM64_SYSREG_TRCSSPCICR7 = 35003 , ARM64_SYSREG_TRCSTALLCTLR = 34904 , ARM64_SYSREG_TRCSTATR = 34840 , ARM64_SYSREG_TRCSYNCPR = 34920 , ARM64_SYSREG_TRCTRACEIDR = 34817 , ARM64_SYSREG_TRCTSCTLR = 34912 , ARM64_SYSREG_TRCVDARCCTLR = 34898 , ARM64_SYSREG_TRCVDCTLR = 34882 , ARM64_SYSREG_TRCVDSACCTLR = 34890 , ARM64_SYSREG_TRCVICTLR = 34818 , ARM64_SYSREG_TRCVIIECTLR = 34826 , ARM64_SYSREG_TRCVIPCSSCTLR = 34842 , ARM64_SYSREG_TRCVISSCTLR = 34834 , ARM64_SYSREG_TRCVMIDCCTLR0 = 35218 , ARM64_SYSREG_TRCVMIDCCTLR1 = 35226 , ARM64_SYSREG_TRCVMIDCVR0 = 35201 , ARM64_SYSREG_TRCVMIDCVR1 = 35217 , ARM64_SYSREG_TRCVMIDCVR2 = 35233 , ARM64_SYSREG_TRCVMIDCVR3 = 35249 , ARM64_SYSREG_TRCVMIDCVR4 = 35265 , ARM64_SYSREG_TRCVMIDCVR5 = 35281 , ARM64_SYSREG_TRCVMIDCVR6 = 35297 , ARM64_SYSREG_TRCVMIDCVR7 = 35313 , ARM64_SYSREG_TRFCR_EL1 = 49297 , ARM64_SYSREG_TRFCR_EL12 = 59537 , ARM64_SYSREG_TRFCR_EL2 = 57489 , ARM64_SYSREG_TTBR0_EL1 = 49408 , ARM64_SYSREG_TTBR0_EL12 = 59648 , ARM64_SYSREG_TTBR0_EL2 = 57600 , ARM64_SYSREG_TTBR0_EL3 = 61696 , ARM64_SYSREG_TTBR1_EL1 = 49409 , ARM64_SYSREG_TTBR1_EL12 = 59649 , ARM64_SYSREG_TTBR1_EL2 = 57601 , ARM64_SYSREG_UAO = 49684 , ARM64_SYSREG_VBAR_EL1 = 50688 , ARM64_SYSREG_VBAR_EL12 = 60928 , ARM64_SYSREG_VBAR_EL2 = 58880 , ARM64_SYSREG_VBAR_EL3 = 62976 , ARM64_SYSREG_VDISR_EL2 = 58889 , ARM64_SYSREG_VMPIDR_EL2 = 57349 , ARM64_SYSREG_VNCR_EL2 = 57616 , ARM64_SYSREG_VPIDR_EL2 = 57344 , ARM64_SYSREG_VSESR_EL2 = 58003 , ARM64_SYSREG_VSTCR_EL2 = 57650 , ARM64_SYSREG_VSTTBR_EL2 = 57648 , ARM64_SYSREG_VTCR_EL2 = 57610 , ARM64_SYSREG_VTTBR_EL2 = 57608 , ARM64_SYSREG_ZCR_EL1 = 49296 , ARM64_SYSREG_ZCR_EL12 = 59536 , ARM64_SYSREG_ZCR_EL2 = 57488 , ARM64_SYSREG_ZCR_EL3 = 61584 , } # [repr (u32)] # [doc = " System PState Field (MSR instruction)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_pstate { ARM64_PSTATE_INVALID = 0 , ARM64_PSTATE_SPSEL = 5 , ARM64_PSTATE_DAIFSET = 30 , ARM64_PSTATE_DAIFCLR = 31 , ARM64_PSTATE_PAN = 4 , ARM64_PSTATE_UAO = 3 , ARM64_PSTATE_DIT = 26 , } # [repr (u32)] # [doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_vas { ARM64_VAS_INVALID = 0 , ARM64_VAS_16B = 1 , ARM64_VAS_8B = 2 , ARM64_VAS_4B = 3 , ARM64_VAS_1B = 4 , ARM64_VAS_8H = 5 , ARM64_VAS_4H = 6 , ARM64_VAS_2H = 7 , ARM64_VAS_1H = 8 , ARM64_VAS_4S = 9 , ARM64_VAS_2S = 10 , ARM64_VAS_1S = 11 , ARM64_VAS_2D = 12 , ARM64_VAS_1D = 13 , ARM64_VAS_1Q = 14 , } # [repr (u32)] # [doc = " Memory barrier operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0 , ARM64_BARRIER_OSHLD = 1 , ARM64_BARRIER_OSHST = 2 , ARM64_BARRIER_OSH = 3 , ARM64_BARRIER_NSHLD = 5 , ARM64_BARRIER_NSHST = 6 , ARM64_BARRIER_NSH = 7 , ARM64_BARRIER_ISHLD = 9 , ARM64_BARRIER_ISHST = 10 , ARM64_BARRIER_ISH = 11 , ARM64_BARRIER_LD = 13 , ARM64_BARRIER_ST = 14 , ARM64_BARRIER_SY = 15 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM64_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM64_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM64_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM64_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM64_OP_FP = 4 , # [doc = "< C-Immediate"] ARM64_OP_CIMM = 64 , # [doc = "< MRS register operand."] ARM64_OP_REG_MRS = 65 , # [doc = "< MSR register operand."] ARM64_OP_REG_MSR = 66 , # [doc = "< PState operand."] ARM64_OP_PSTATE = 67 , # [doc = "< SYS operand for IC/DC/AT/TLBI instructions."] ARM64_OP_SYS = 68 , # [doc = "< SVCR operand for MSR SVCR instructions."] ARM64_OP_SVCR = 69 , # [doc = "< Prefetch operand (PRFM)."] ARM64_OP_PREFETCH = 70 , # [doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."] ARM64_OP_BARRIER = 71 , # [doc = "< SME instruction operand with with index."] ARM64_OP_SME_INDEX = 72 , } # [repr (u32)] # [doc = " SYS operands (IC/DC/AC/TLBI)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sys_op { ARM64_SYS_INVALID = 0 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1 = 1 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1IS = 2 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1ISNXS = 3 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1NXS = 4 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OS = 5 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OSNXS = 6 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2 = 7 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2IS = 8 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2ISNXS = 9 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2NXS = 10 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OS = 11 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OSNXS = 12 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3 = 13 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3IS = 14 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3ISNXS = 15 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3NXS = 16 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OS = 17 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OSNXS = 18 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1 = 19 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1IS = 20 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1ISNXS = 21 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1NXS = 22 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OS = 23 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OSNXS = 24 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1 = 25 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1IS = 26 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1ISNXS = 27 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1NXS = 28 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OS = 29 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OSNXS = 30 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1 = 31 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1IS = 32 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1ISNXS = 33 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1NXS = 34 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OS = 35 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OSNXS = 36 , # [doc = " TLBI operations"] ARM64_TLBI_PAALL = 37 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLNXS = 38 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOS = 39 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOSNXS = 40 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1 = 41 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1IS = 42 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1ISNXS = 43 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1NXS = 44 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OS = 45 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OSNXS = 46 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1 = 47 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1IS = 48 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1ISNXS = 49 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1NXS = 50 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OS = 51 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OSNXS = 52 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOS = 53 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOSNXS = 54 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOS = 55 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOSNXS = 56 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1 = 57 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1IS = 58 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1ISNXS = 59 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1NXS = 60 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OS = 61 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OSNXS = 62 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1 = 63 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1IS = 64 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1ISNXS = 65 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1NXS = 66 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OS = 67 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OSNXS = 68 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1 = 69 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1IS = 70 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1ISNXS = 71 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1NXS = 72 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OS = 73 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OSNXS = 74 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2 = 75 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2IS = 76 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2ISNXS = 77 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2NXS = 78 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OS = 79 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OSNXS = 80 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3 = 81 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3IS = 82 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3ISNXS = 83 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3NXS = 84 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OS = 85 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OSNXS = 86 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1 = 87 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1IS = 88 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1ISNXS = 89 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1NXS = 90 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OS = 91 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OSNXS = 92 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2 = 93 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2IS = 94 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2ISNXS = 95 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2NXS = 96 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OS = 97 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OSNXS = 98 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3 = 99 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3IS = 100 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3ISNXS = 101 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3NXS = 102 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OS = 103 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OSNXS = 104 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1 = 105 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1IS = 106 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1ISNXS = 107 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1NXS = 108 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OS = 109 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OSNXS = 110 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1 = 111 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1IS = 112 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1ISNXS = 113 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1NXS = 114 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OS = 115 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OSNXS = 116 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1 = 117 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1IS = 118 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1ISNXS = 119 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1NXS = 120 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OS = 121 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OSNXS = 122 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2 = 123 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2IS = 124 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2ISNXS = 125 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2NXS = 126 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OS = 127 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OSNXS = 128 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3 = 129 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3IS = 130 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3ISNXS = 131 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3NXS = 132 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OS = 133 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OSNXS = 134 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1 = 135 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1IS = 136 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1ISNXS = 137 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1NXS = 138 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OS = 139 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OSNXS = 140 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2 = 141 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2IS = 142 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2ISNXS = 143 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2NXS = 144 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OS = 145 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OSNXS = 146 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3 = 147 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3IS = 148 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3ISNXS = 149 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3NXS = 150 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OS = 151 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OSNXS = 152 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1 = 153 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1IS = 154 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1ISNXS = 155 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1NXS = 156 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OS = 157 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OSNXS = 158 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1 = 159 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1IS = 160 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1ISNXS = 161 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1NXS = 162 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OS = 163 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OSNXS = 164 , # [doc = " AT operations"] ARM64_AT_S1E1R = 165 , # [doc = " AT operations"] ARM64_AT_S1E2R = 166 , # [doc = " AT operations"] ARM64_AT_S1E3R = 167 , # [doc = " AT operations"] ARM64_AT_S1E1W = 168 , # [doc = " AT operations"] ARM64_AT_S1E2W = 169 , # [doc = " AT operations"] ARM64_AT_S1E3W = 170 , # [doc = " AT operations"] ARM64_AT_S1E0R = 171 , # [doc = " AT operations"] ARM64_AT_S1E0W = 172 , # [doc = " AT operations"] ARM64_AT_S12E1R = 173 , # [doc = " AT operations"] ARM64_AT_S12E1W = 174 , # [doc = " AT operations"] ARM64_AT_S12E0R = 175 , # [doc = " AT operations"] ARM64_AT_S12E0W = 176 , # [doc = " AT operations"] ARM64_AT_S1E1RP = 177 , # [doc = " AT operations"] ARM64_AT_S1E1WP = 178 , # [doc = " DC operations"] ARM64_DC_CGDSW = 179 , # [doc = " DC operations"] ARM64_DC_CGDVAC = 180 , # [doc = " DC operations"] ARM64_DC_CGDVADP = 181 , # [doc = " DC operations"] ARM64_DC_CGDVAP = 182 , # [doc = " DC operations"] ARM64_DC_CGSW = 183 , # [doc = " DC operations"] ARM64_DC_CGVAC = 184 , # [doc = " DC operations"] ARM64_DC_CGVADP = 185 , # [doc = " DC operations"] ARM64_DC_CGVAP = 186 , # [doc = " DC operations"] ARM64_DC_CIGDSW = 187 , # [doc = " DC operations"] ARM64_DC_CIGDVAC = 188 , # [doc = " DC operations"] ARM64_DC_CIGSW = 189 , # [doc = " DC operations"] ARM64_DC_CIGVAC = 190 , # [doc = " DC operations"] ARM64_DC_CISW = 191 , # [doc = " DC operations"] ARM64_DC_CIVAC = 192 , # [doc = " DC operations"] ARM64_DC_CSW = 193 , # [doc = " DC operations"] ARM64_DC_CVAC = 194 , # [doc = " DC operations"] ARM64_DC_CVADP = 195 , # [doc = " DC operations"] ARM64_DC_CVAP = 196 , # [doc = " DC operations"] ARM64_DC_CVAU = 197 , # [doc = " DC operations"] ARM64_DC_GVA = 198 , # [doc = " DC operations"] ARM64_DC_GZVA = 199 , # [doc = " DC operations"] ARM64_DC_IGDSW = 200 , # [doc = " DC operations"] ARM64_DC_IGDVAC = 201 , # [doc = " DC operations"] ARM64_DC_IGSW = 202 , # [doc = " DC operations"] ARM64_DC_IGVAC = 203 , # [doc = " DC operations"] ARM64_DC_ISW = 204 , # [doc = " DC operations"] ARM64_DC_IVAC = 205 , # [doc = " DC operations"] ARM64_DC_ZVA = 206 , # [doc = " IC operations"] ARM64_IC_IALLUIS = 207 , # [doc = " IC operations"] ARM64_IC_IALLU = 208 , # [doc = " IC operations"] ARM64_IC_IVAU = 209 , } # [repr (u32)] # [doc = " SVCR operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_svcr_op { ARM64_SVCR_INVALID = 0 , ARM64_SVCR_SVCRSM = 1 , ARM64_SVCR_SVCRSMZA = 3 , ARM64_SVCR_SVCRZA = 2 , } # [repr (u32)] # [doc = " Prefetch operations (PRFM)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0 , ARM64_PRFM_PLDL1KEEP = 1 , ARM64_PRFM_PLDL1STRM = 2 , ARM64_PRFM_PLDL2KEEP = 3 , ARM64_PRFM_PLDL2STRM = 4 , ARM64_PRFM_PLDL3KEEP = 5 , ARM64_PRFM_PLDL3STRM = 6 , ARM64_PRFM_PLIL1KEEP = 9 , ARM64_PRFM_PLIL1STRM = 10 , ARM64_PRFM_PLIL2KEEP = 11 , ARM64_PRFM_PLIL2STRM = 12 , ARM64_PRFM_PLIL3KEEP = 13 , ARM64_PRFM_PLIL3STRM = 14 , ARM64_PRFM_PSTL1KEEP = 17 , ARM64_PRFM_PSTL1STRM = 18 , ARM64_PRFM_PSTL2KEEP = 19 , ARM64_PRFM_PSTL2STRM = 20 , ARM64_PRFM_PSTL3KEEP = 21 , ARM64_PRFM_PSTL3STRM = 22 , } impl arm64_reg { pub const ARM64_REG_IP0 : arm64_reg = arm64_reg :: ARM64_REG_X16 ; } impl arm64_reg { pub const ARM64_REG_IP1 : arm64_reg = arm64_reg :: ARM64_REG_X17 ; } impl arm64_reg { pub const ARM64_REG_X29 : arm64_reg = arm64_reg :: ARM64_REG_FP ; } impl arm64_reg { pub const ARM64_REG_X30 : arm64_reg = arm64_reg :: ARM64_REG_LR ; } # [repr (u32)] # [doc = " ARM64 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_reg { ARM64_REG_INVALID = 0 , ARM64_REG_FFR = 1 , ARM64_REG_FP = 2 , ARM64_REG_LR = 3 , ARM64_REG_NZCV = 4 , ARM64_REG_SP = 5 , ARM64_REG_VG = 6 , ARM64_REG_WSP = 7 , ARM64_REG_WZR = 8 , ARM64_REG_XZR = 9 , ARM64_REG_ZA = 10 , ARM64_REG_B0 = 11 , ARM64_REG_B1 = 12 , ARM64_REG_B2 = 13 , ARM64_REG_B3 = 14 , ARM64_REG_B4 = 15 , ARM64_REG_B5 = 16 , ARM64_REG_B6 = 17 , ARM64_REG_B7 = 18 , ARM64_REG_B8 = 19 , ARM64_REG_B9 = 20 , ARM64_REG_B10 = 21 , ARM64_REG_B11 = 22 , ARM64_REG_B12 = 23 , ARM64_REG_B13 = 24 , ARM64_REG_B14 = 25 , ARM64_REG_B15 = 26 , ARM64_REG_B16 = 27 , ARM64_REG_B17 = 28 , ARM64_REG_B18 = 29 , ARM64_REG_B19 = 30 , ARM64_REG_B20 = 31 , ARM64_REG_B21 = 32 , ARM64_REG_B22 = 33 , ARM64_REG_B23 = 34 , ARM64_REG_B24 = 35 , ARM64_REG_B25 = 36 , ARM64_REG_B26 = 37 , ARM64_REG_B27 = 38 , ARM64_REG_B28 = 39 , ARM64_REG_B29 = 40 , ARM64_REG_B30 = 41 , ARM64_REG_B31 = 42 , ARM64_REG_D0 = 43 , ARM64_REG_D1 = 44 , ARM64_REG_D2 = 45 , ARM64_REG_D3 = 46 , ARM64_REG_D4 = 47 , ARM64_REG_D5 = 48 , ARM64_REG_D6 = 49 , ARM64_REG_D7 = 50 , ARM64_REG_D8 = 51 , ARM64_REG_D9 = 52 , ARM64_REG_D10 = 53 , ARM64_REG_D11 = 54 , ARM64_REG_D12 = 55 , ARM64_REG_D13 = 56 , ARM64_REG_D14 = 57 , ARM64_REG_D15 = 58 , ARM64_REG_D16 = 59 , ARM64_REG_D17 = 60 , ARM64_REG_D18 = 61 , ARM64_REG_D19 = 62 , ARM64_REG_D20 = 63 , ARM64_REG_D21 = 64 , ARM64_REG_D22 = 65 , ARM64_REG_D23 = 66 , ARM64_REG_D24 = 67 , ARM64_REG_D25 = 68 , ARM64_REG_D26 = 69 , ARM64_REG_D27 = 70 , ARM64_REG_D28 = 71 , ARM64_REG_D29 = 72 , ARM64_REG_D30 = 73 , ARM64_REG_D31 = 74 , ARM64_REG_H0 = 75 , ARM64_REG_H1 = 76 , ARM64_REG_H2 = 77 , ARM64_REG_H3 = 78 , ARM64_REG_H4 = 79 , ARM64_REG_H5 = 80 , ARM64_REG_H6 = 81 , ARM64_REG_H7 = 82 , ARM64_REG_H8 = 83 , ARM64_REG_H9 = 84 , ARM64_REG_H10 = 85 , ARM64_REG_H11 = 86 , ARM64_REG_H12 = 87 , ARM64_REG_H13 = 88 , ARM64_REG_H14 = 89 , ARM64_REG_H15 = 90 , ARM64_REG_H16 = 91 , ARM64_REG_H17 = 92 , ARM64_REG_H18 = 93 , ARM64_REG_H19 = 94 , ARM64_REG_H20 = 95 , ARM64_REG_H21 = 96 , ARM64_REG_H22 = 97 , ARM64_REG_H23 = 98 , ARM64_REG_H24 = 99 , ARM64_REG_H25 = 100 , ARM64_REG_H26 = 101 , ARM64_REG_H27 = 102 , ARM64_REG_H28 = 103 , ARM64_REG_H29 = 104 , ARM64_REG_H30 = 105 , ARM64_REG_H31 = 106 , ARM64_REG_P0 = 107 , ARM64_REG_P1 = 108 , ARM64_REG_P2 = 109 , ARM64_REG_P3 = 110 , ARM64_REG_P4 = 111 , ARM64_REG_P5 = 112 , ARM64_REG_P6 = 113 , ARM64_REG_P7 = 114 , ARM64_REG_P8 = 115 , ARM64_REG_P9 = 116 , ARM64_REG_P10 = 117 , ARM64_REG_P11 = 118 , ARM64_REG_P12 = 119 , ARM64_REG_P13 = 120 , ARM64_REG_P14 = 121 , ARM64_REG_P15 = 122 , ARM64_REG_Q0 = 123 , ARM64_REG_Q1 = 124 , ARM64_REG_Q2 = 125 , ARM64_REG_Q3 = 126 , ARM64_REG_Q4 = 127 , ARM64_REG_Q5 = 128 , ARM64_REG_Q6 = 129 , ARM64_REG_Q7 = 130 , ARM64_REG_Q8 = 131 , ARM64_REG_Q9 = 132 , ARM64_REG_Q10 = 133 , ARM64_REG_Q11 = 134 , ARM64_REG_Q12 = 135 , ARM64_REG_Q13 = 136 , ARM64_REG_Q14 = 137 , ARM64_REG_Q15 = 138 , ARM64_REG_Q16 = 139 , ARM64_REG_Q17 = 140 , ARM64_REG_Q18 = 141 , ARM64_REG_Q19 = 142 , ARM64_REG_Q20 = 143 , ARM64_REG_Q21 = 144 , ARM64_REG_Q22 = 145 , ARM64_REG_Q23 = 146 , ARM64_REG_Q24 = 147 , ARM64_REG_Q25 = 148 , ARM64_REG_Q26 = 149 , ARM64_REG_Q27 = 150 , ARM64_REG_Q28 = 151 , ARM64_REG_Q29 = 152 , ARM64_REG_Q30 = 153 , ARM64_REG_Q31 = 154 , ARM64_REG_S0 = 155 , ARM64_REG_S1 = 156 , ARM64_REG_S2 = 157 , ARM64_REG_S3 = 158 , ARM64_REG_S4 = 159 , ARM64_REG_S5 = 160 , ARM64_REG_S6 = 161 , ARM64_REG_S7 = 162 , ARM64_REG_S8 = 163 , ARM64_REG_S9 = 164 , ARM64_REG_S10 = 165 , ARM64_REG_S11 = 166 , ARM64_REG_S12 = 167 , ARM64_REG_S13 = 168 , ARM64_REG_S14 = 169 , ARM64_REG_S15 = 170 , ARM64_REG_S16 = 171 , ARM64_REG_S17 = 172 , ARM64_REG_S18 = 173 , ARM64_REG_S19 = 174 , ARM64_REG_S20 = 175 , ARM64_REG_S21 = 176 , ARM64_REG_S22 = 177 , ARM64_REG_S23 = 178 , ARM64_REG_S24 = 179 , ARM64_REG_S25 = 180 , ARM64_REG_S26 = 181 , ARM64_REG_S27 = 182 , ARM64_REG_S28 = 183 , ARM64_REG_S29 = 184 , ARM64_REG_S30 = 185 , ARM64_REG_S31 = 186 , ARM64_REG_W0 = 187 , ARM64_REG_W1 = 188 , ARM64_REG_W2 = 189 , ARM64_REG_W3 = 190 , ARM64_REG_W4 = 191 , ARM64_REG_W5 = 192 , ARM64_REG_W6 = 193 , ARM64_REG_W7 = 194 , ARM64_REG_W8 = 195 , ARM64_REG_W9 = 196 , ARM64_REG_W10 = 197 , ARM64_REG_W11 = 198 , ARM64_REG_W12 = 199 , ARM64_REG_W13 = 200 , ARM64_REG_W14 = 201 , ARM64_REG_W15 = 202 , ARM64_REG_W16 = 203 , ARM64_REG_W17 = 204 , ARM64_REG_W18 = 205 , ARM64_REG_W19 = 206 , ARM64_REG_W20 = 207 , ARM64_REG_W21 = 208 , ARM64_REG_W22 = 209 , ARM64_REG_W23 = 210 , ARM64_REG_W24 = 211 , ARM64_REG_W25 = 212 , ARM64_REG_W26 = 213 , ARM64_REG_W27 = 214 , ARM64_REG_W28 = 215 , ARM64_REG_W29 = 216 , ARM64_REG_W30 = 217 , ARM64_REG_X0 = 218 , ARM64_REG_X1 = 219 , ARM64_REG_X2 = 220 , ARM64_REG_X3 = 221 , ARM64_REG_X4 = 222 , ARM64_REG_X5 = 223 , ARM64_REG_X6 = 224 , ARM64_REG_X7 = 225 , ARM64_REG_X8 = 226 , ARM64_REG_X9 = 227 , ARM64_REG_X10 = 228 , ARM64_REG_X11 = 229 , ARM64_REG_X12 = 230 , ARM64_REG_X13 = 231 , ARM64_REG_X14 = 232 , ARM64_REG_X15 = 233 , ARM64_REG_X16 = 234 , ARM64_REG_X17 = 235 , ARM64_REG_X18 = 236 , ARM64_REG_X19 = 237 , ARM64_REG_X20 = 238 , ARM64_REG_X21 = 239 , ARM64_REG_X22 = 240 , ARM64_REG_X23 = 241 , ARM64_REG_X24 = 242 , ARM64_REG_X25 = 243 , ARM64_REG_X26 = 244 , ARM64_REG_X27 = 245 , ARM64_REG_X28 = 246 , ARM64_REG_Z0 = 247 , ARM64_REG_Z1 = 248 , ARM64_REG_Z2 = 249 , ARM64_REG_Z3 = 250 , ARM64_REG_Z4 = 251 , ARM64_REG_Z5 = 252 , ARM64_REG_Z6 = 253 , ARM64_REG_Z7 = 254 , ARM64_REG_Z8 = 255 , ARM64_REG_Z9 = 256 , ARM64_REG_Z10 = 257 , ARM64_REG_Z11 = 258 , ARM64_REG_Z12 = 259 , ARM64_REG_Z13 = 260 , ARM64_REG_Z14 = 261 , ARM64_REG_Z15 = 262 , ARM64_REG_Z16 = 263 , ARM64_REG_Z17 = 264 , ARM64_REG_Z18 = 265 , ARM64_REG_Z19 = 266 , ARM64_REG_Z20 = 267 , ARM64_REG_Z21 = 268 , ARM64_REG_Z22 = 269 , ARM64_REG_Z23 = 270 , ARM64_REG_Z24 = 271 , ARM64_REG_Z25 = 272 , ARM64_REG_Z26 = 273 , ARM64_REG_Z27 = 274 , ARM64_REG_Z28 = 275 , ARM64_REG_Z29 = 276 , ARM64_REG_Z30 = 277 , ARM64_REG_Z31 = 278 , ARM64_REG_ZAB0 = 279 , ARM64_REG_ZAD0 = 280 , ARM64_REG_ZAD1 = 281 , ARM64_REG_ZAD2 = 282 , ARM64_REG_ZAD3 = 283 , ARM64_REG_ZAD4 = 284 , ARM64_REG_ZAD5 = 285 , ARM64_REG_ZAD6 = 286 , ARM64_REG_ZAD7 = 287 , ARM64_REG_ZAH0 = 288 , ARM64_REG_ZAH1 = 289 , ARM64_REG_ZAQ0 = 290 , ARM64_REG_ZAQ1 = 291 , ARM64_REG_ZAQ2 = 292 , ARM64_REG_ZAQ3 = 293 , ARM64_REG_ZAQ4 = 294 , ARM64_REG_ZAQ5 = 295 , ARM64_REG_ZAQ6 = 296 , ARM64_REG_ZAQ7 = 297 , ARM64_REG_ZAQ8 = 298 , ARM64_REG_ZAQ9 = 299 , ARM64_REG_ZAQ10 = 300 , ARM64_REG_ZAQ11 = 301 , ARM64_REG_ZAQ12 = 302 , ARM64_REG_ZAQ13 = 303 , ARM64_REG_ZAQ14 = 304 , ARM64_REG_ZAQ15 = 305 , ARM64_REG_ZAS0 = 306 , ARM64_REG_ZAS1 = 307 , ARM64_REG_ZAS2 = 308 , ARM64_REG_ZAS3 = 309 , ARM64_REG_V0 = 310 , ARM64_REG_V1 = 311 , ARM64_REG_V2 = 312 , ARM64_REG_V3 = 313 , ARM64_REG_V4 = 314 , ARM64_REG_V5 = 315 , ARM64_REG_V6 = 316 , ARM64_REG_V7 = 317 , ARM64_REG_V8 = 318 , ARM64_REG_V9 = 319 , ARM64_REG_V10 = 320 , ARM64_REG_V11 = 321 , ARM64_REG_V12 = 322 , ARM64_REG_V13 = 323 , ARM64_REG_V14 = 324 , ARM64_REG_V15 = 325 , ARM64_REG_V16 = 326 , ARM64_REG_V17 = 327 , ARM64_REG_V18 = 328 , ARM64_REG_V19 = 329 , ARM64_REG_V20 = 330 , ARM64_REG_V21 = 331 , ARM64_REG_V22 = 332 , ARM64_REG_V23 = 333 , ARM64_REG_V24 = 334 , ARM64_REG_V25 = 335 , ARM64_REG_V26 = 336 , ARM64_REG_V27 = 337 , ARM64_REG_V28 = 338 , ARM64_REG_V29 = 339 , ARM64_REG_V30 = 340 , ARM64_REG_V31 = 341 , ARM64_REG_ENDING = 342 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_mem { # [doc = "< base register"] pub base : arm64_reg , # [doc = "< index register"] pub index : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_mem"] [:: std :: mem :: size_of :: < arm64_op_mem > () - 12usize] ; ["Alignment of arm64_op_mem"] [:: std :: mem :: align_of :: < arm64_op_mem > () - 4usize] ; ["Offset of field: arm64_op_mem::base"] [:: std :: mem :: offset_of ! (arm64_op_mem , base) - 0usize] ; ["Offset of field: arm64_op_mem::index"] [:: std :: mem :: offset_of ! (arm64_op_mem , index) - 4usize] ; ["Offset of field: arm64_op_mem::disp"] [:: std :: mem :: offset_of ! (arm64_op_mem , disp) - 8usize] ; } ; # [doc = " SME Instruction's operand has index\n This is associated with ARM64_OP_SME_INDEX operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_sme_index { # [doc = "< register being indexed"] pub reg : arm64_reg , # [doc = "< base register"] pub base : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_sme_index"] [:: std :: mem :: size_of :: < arm64_op_sme_index > () - 12usize] ; ["Alignment of arm64_op_sme_index"] [:: std :: mem :: align_of :: < arm64_op_sme_index > () - 4usize] ; ["Offset of field: arm64_op_sme_index::reg"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , reg) - 0usize] ; ["Offset of field: arm64_op_sme_index::base"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , base) - 4usize] ; ["Offset of field: arm64_op_sme_index::disp"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64_op { # [doc = "< Vector Index for some vector operands (or -1 if\n< irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , # [doc = "< Vector Arrangement Specifier"] pub vas : arm64_vas , pub shift : cs_arm64_op__bindgen_ty_1 , # [doc = "< extender type of this operand"] pub ext : arm64_extender , # [doc = "< operand type"] pub type_ : arm64_op_type , # [doc = "< MSR/MRS SVCR instruction variant."] pub svcr : arm64_svcr_op , pub __bindgen_anon_1 : cs_arm64_op__bindgen_ty_2 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm64_op__bindgen_ty_1 { # [doc = "< shifter type of this operand"] pub type_ : arm64_shifter , # [doc = "< shifter value of this operand"] pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm64_op__bindgen_ty_2 { # [doc = "< register value for REG operand"] pub reg : arm64_reg , # [doc = "< immediate value, or index for C-IMM or IMM operand"] pub imm : i64 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm64_op_mem , # [doc = "< PState field of MSR instruction."] pub pstate : arm64_pstate , # [doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op,\n< arm64_dc_op, arm64_at_op, arm64_tlbi_op)"] pub sys : arm64_sys_op , # [doc = "< PRFM operation."] pub prefetch : arm64_prefetch_op , # [doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."] pub barrier : arm64_barrier_op , # [doc = "< base/disp value for matrix tile slice\n< instructions."] pub sme_index : arm64_op_sme_index , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_2 > () - 16usize] ; ["Alignment of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::pstate"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , pstate) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sys"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sys) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::prefetch"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , prefetch) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::barrier"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , barrier) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sme_index"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sme_index) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op"] [:: std :: mem :: size_of :: < cs_arm64_op > () - 56usize] ; ["Alignment of cs_arm64_op"] [:: std :: mem :: align_of :: < cs_arm64_op > () - 8usize] ; ["Offset of field: cs_arm64_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm64_op , vector_index) - 0usize] ; ["Offset of field: cs_arm64_op::vas"] [:: std :: mem :: offset_of ! (cs_arm64_op , vas) - 4usize] ; ["Offset of field: cs_arm64_op::shift"] [:: std :: mem :: offset_of ! (cs_arm64_op , shift) - 8usize] ; ["Offset of field: cs_arm64_op::ext"] [:: std :: mem :: offset_of ! (cs_arm64_op , ext) - 16usize] ; ["Offset of field: cs_arm64_op::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op , type_) - 20usize] ; ["Offset of field: cs_arm64_op::svcr"] [:: std :: mem :: offset_of ! (cs_arm64_op , svcr) - 24usize] ; ["Offset of field: cs_arm64_op::access"] [:: std :: mem :: offset_of ! (cs_arm64_op , access) - 48usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, svcr: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . svcr , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64 { # [doc = "< conditional code for this insn"] pub cc : arm64_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn request writeback? 'True' means 'yes'"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm64_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64"] [:: std :: mem :: size_of :: < cs_arm64 > () - 456usize] ; ["Alignment of cs_arm64"] [:: std :: mem :: align_of :: < cs_arm64 > () - 8usize] ; ["Offset of field: cs_arm64::cc"] [:: std :: mem :: offset_of ! (cs_arm64 , cc) - 0usize] ; ["Offset of field: cs_arm64::update_flags"] [:: std :: mem :: offset_of ! (cs_arm64 , update_flags) - 4usize] ; ["Offset of field: cs_arm64::writeback"] [:: std :: mem :: offset_of ! (cs_arm64 , writeback) - 5usize] ; ["Offset of field: cs_arm64::post_index"] [:: std :: mem :: offset_of ! (cs_arm64 , post_index) - 6usize] ; ["Offset of field: cs_arm64::op_count"] [:: std :: mem :: offset_of ! (cs_arm64 , op_count) - 7usize] ; ["Offset of field: cs_arm64::operands"] [:: std :: mem :: offset_of ! (cs_arm64 , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . post_index , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM64 instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn { ARM64_INS_INVALID = 0 , ARM64_INS_ABS = 1 , ARM64_INS_ADC = 2 , ARM64_INS_ADCLB = 3 , ARM64_INS_ADCLT = 4 , ARM64_INS_ADCS = 5 , ARM64_INS_ADD = 6 , ARM64_INS_ADDG = 7 , ARM64_INS_ADDHA = 8 , ARM64_INS_ADDHN = 9 , ARM64_INS_ADDHN2 = 10 , ARM64_INS_ADDHNB = 11 , ARM64_INS_ADDHNT = 12 , ARM64_INS_ADDP = 13 , ARM64_INS_ADDPL = 14 , ARM64_INS_ADDS = 15 , ARM64_INS_ADDV = 16 , ARM64_INS_ADDVA = 17 , ARM64_INS_ADDVL = 18 , ARM64_INS_ADR = 19 , ARM64_INS_ADRP = 20 , ARM64_INS_AESD = 21 , ARM64_INS_AESE = 22 , ARM64_INS_AESIMC = 23 , ARM64_INS_AESMC = 24 , ARM64_INS_AND = 25 , ARM64_INS_ANDS = 26 , ARM64_INS_ANDV = 27 , ARM64_INS_ASR = 28 , ARM64_INS_ASRD = 29 , ARM64_INS_ASRR = 30 , ARM64_INS_ASRV = 31 , ARM64_INS_AUTDA = 32 , ARM64_INS_AUTDB = 33 , ARM64_INS_AUTDZA = 34 , ARM64_INS_AUTDZB = 35 , ARM64_INS_AUTIA = 36 , ARM64_INS_AUTIA1716 = 37 , ARM64_INS_AUTIASP = 38 , ARM64_INS_AUTIAZ = 39 , ARM64_INS_AUTIB = 40 , ARM64_INS_AUTIB1716 = 41 , ARM64_INS_AUTIBSP = 42 , ARM64_INS_AUTIBZ = 43 , ARM64_INS_AUTIZA = 44 , ARM64_INS_AUTIZB = 45 , ARM64_INS_AXFLAG = 46 , ARM64_INS_B = 47 , ARM64_INS_BC = 48 , ARM64_INS_BCAX = 49 , ARM64_INS_BDEP = 50 , ARM64_INS_BEXT = 51 , ARM64_INS_BFCVT = 52 , ARM64_INS_BFCVTN = 53 , ARM64_INS_BFCVTN2 = 54 , ARM64_INS_BFCVTNT = 55 , ARM64_INS_BFDOT = 56 , ARM64_INS_BFM = 57 , ARM64_INS_BFMLALB = 58 , ARM64_INS_BFMLALT = 59 , ARM64_INS_BFMMLA = 60 , ARM64_INS_BFMOPA = 61 , ARM64_INS_BFMOPS = 62 , ARM64_INS_BGRP = 63 , ARM64_INS_BIC = 64 , ARM64_INS_BICS = 65 , ARM64_INS_BIF = 66 , ARM64_INS_BIT = 67 , ARM64_INS_BL = 68 , ARM64_INS_BLR = 69 , ARM64_INS_BLRAA = 70 , ARM64_INS_BLRAAZ = 71 , ARM64_INS_BLRAB = 72 , ARM64_INS_BLRABZ = 73 , ARM64_INS_BR = 74 , ARM64_INS_BRAA = 75 , ARM64_INS_BRAAZ = 76 , ARM64_INS_BRAB = 77 , ARM64_INS_BRABZ = 78 , ARM64_INS_BRB = 79 , ARM64_INS_BRK = 80 , ARM64_INS_BRKA = 81 , ARM64_INS_BRKAS = 82 , ARM64_INS_BRKB = 83 , ARM64_INS_BRKBS = 84 , ARM64_INS_BRKN = 85 , ARM64_INS_BRKNS = 86 , ARM64_INS_BRKPA = 87 , ARM64_INS_BRKPAS = 88 , ARM64_INS_BRKPB = 89 , ARM64_INS_BRKPBS = 90 , ARM64_INS_BSL = 91 , ARM64_INS_BSL1N = 92 , ARM64_INS_BSL2N = 93 , ARM64_INS_BTI = 94 , ARM64_INS_CADD = 95 , ARM64_INS_CAS = 96 , ARM64_INS_CASA = 97 , ARM64_INS_CASAB = 98 , ARM64_INS_CASAH = 99 , ARM64_INS_CASAL = 100 , ARM64_INS_CASALB = 101 , ARM64_INS_CASALH = 102 , ARM64_INS_CASB = 103 , ARM64_INS_CASH = 104 , ARM64_INS_CASL = 105 , ARM64_INS_CASLB = 106 , ARM64_INS_CASLH = 107 , ARM64_INS_CASP = 108 , ARM64_INS_CASPA = 109 , ARM64_INS_CASPAL = 110 , ARM64_INS_CASPL = 111 , ARM64_INS_CBNZ = 112 , ARM64_INS_CBZ = 113 , ARM64_INS_CCMN = 114 , ARM64_INS_CCMP = 115 , ARM64_INS_CDOT = 116 , ARM64_INS_CFINV = 117 , ARM64_INS_CINC = 118 , ARM64_INS_CINV = 119 , ARM64_INS_CLASTA = 120 , ARM64_INS_CLASTB = 121 , ARM64_INS_CLREX = 122 , ARM64_INS_CLS = 123 , ARM64_INS_CLZ = 124 , ARM64_INS_CMEQ = 125 , ARM64_INS_CMGE = 126 , ARM64_INS_CMGT = 127 , ARM64_INS_CMHI = 128 , ARM64_INS_CMHS = 129 , ARM64_INS_CMLA = 130 , ARM64_INS_CMLE = 131 , ARM64_INS_CMLO = 132 , ARM64_INS_CMLS = 133 , ARM64_INS_CMLT = 134 , ARM64_INS_CMN = 135 , ARM64_INS_CMP = 136 , ARM64_INS_CMPEQ = 137 , ARM64_INS_CMPGE = 138 , ARM64_INS_CMPGT = 139 , ARM64_INS_CMPHI = 140 , ARM64_INS_CMPHS = 141 , ARM64_INS_CMPLE = 142 , ARM64_INS_CMPLO = 143 , ARM64_INS_CMPLS = 144 , ARM64_INS_CMPLT = 145 , ARM64_INS_CMPNE = 146 , ARM64_INS_CMPP = 147 , ARM64_INS_CMTST = 148 , ARM64_INS_CNEG = 149 , ARM64_INS_CNOT = 150 , ARM64_INS_CNT = 151 , ARM64_INS_CNTB = 152 , ARM64_INS_CNTD = 153 , ARM64_INS_CNTH = 154 , ARM64_INS_CNTP = 155 , ARM64_INS_CNTW = 156 , ARM64_INS_COMPACT = 157 , ARM64_INS_CPY = 158 , ARM64_INS_CPYE = 159 , ARM64_INS_CPYEN = 160 , ARM64_INS_CPYERN = 161 , ARM64_INS_CPYERT = 162 , ARM64_INS_CPYERTN = 163 , ARM64_INS_CPYERTRN = 164 , ARM64_INS_CPYERTWN = 165 , ARM64_INS_CPYET = 166 , ARM64_INS_CPYETN = 167 , ARM64_INS_CPYETRN = 168 , ARM64_INS_CPYETWN = 169 , ARM64_INS_CPYEWN = 170 , ARM64_INS_CPYEWT = 171 , ARM64_INS_CPYEWTN = 172 , ARM64_INS_CPYEWTRN = 173 , ARM64_INS_CPYEWTWN = 174 , ARM64_INS_CPYFE = 175 , ARM64_INS_CPYFEN = 176 , ARM64_INS_CPYFERN = 177 , ARM64_INS_CPYFERT = 178 , ARM64_INS_CPYFERTN = 179 , ARM64_INS_CPYFERTRN = 180 , ARM64_INS_CPYFERTWN = 181 , ARM64_INS_CPYFET = 182 , ARM64_INS_CPYFETN = 183 , ARM64_INS_CPYFETRN = 184 , ARM64_INS_CPYFETWN = 185 , ARM64_INS_CPYFEWN = 186 , ARM64_INS_CPYFEWT = 187 , ARM64_INS_CPYFEWTN = 188 , ARM64_INS_CPYFEWTRN = 189 , ARM64_INS_CPYFEWTWN = 190 , ARM64_INS_CPYFM = 191 , ARM64_INS_CPYFMN = 192 , ARM64_INS_CPYFMRN = 193 , ARM64_INS_CPYFMRT = 194 , ARM64_INS_CPYFMRTN = 195 , ARM64_INS_CPYFMRTRN = 196 , ARM64_INS_CPYFMRTWN = 197 , ARM64_INS_CPYFMT = 198 , ARM64_INS_CPYFMTN = 199 , ARM64_INS_CPYFMTRN = 200 , ARM64_INS_CPYFMTWN = 201 , ARM64_INS_CPYFMWN = 202 , ARM64_INS_CPYFMWT = 203 , ARM64_INS_CPYFMWTN = 204 , ARM64_INS_CPYFMWTRN = 205 , ARM64_INS_CPYFMWTWN = 206 , ARM64_INS_CPYFP = 207 , ARM64_INS_CPYFPN = 208 , ARM64_INS_CPYFPRN = 209 , ARM64_INS_CPYFPRT = 210 , ARM64_INS_CPYFPRTN = 211 , ARM64_INS_CPYFPRTRN = 212 , ARM64_INS_CPYFPRTWN = 213 , ARM64_INS_CPYFPT = 214 , ARM64_INS_CPYFPTN = 215 , ARM64_INS_CPYFPTRN = 216 , ARM64_INS_CPYFPTWN = 217 , ARM64_INS_CPYFPWN = 218 , ARM64_INS_CPYFPWT = 219 , ARM64_INS_CPYFPWTN = 220 , ARM64_INS_CPYFPWTRN = 221 , ARM64_INS_CPYFPWTWN = 222 , ARM64_INS_CPYM = 223 , ARM64_INS_CPYMN = 224 , ARM64_INS_CPYMRN = 225 , ARM64_INS_CPYMRT = 226 , ARM64_INS_CPYMRTN = 227 , ARM64_INS_CPYMRTRN = 228 , ARM64_INS_CPYMRTWN = 229 , ARM64_INS_CPYMT = 230 , ARM64_INS_CPYMTN = 231 , ARM64_INS_CPYMTRN = 232 , ARM64_INS_CPYMTWN = 233 , ARM64_INS_CPYMWN = 234 , ARM64_INS_CPYMWT = 235 , ARM64_INS_CPYMWTN = 236 , ARM64_INS_CPYMWTRN = 237 , ARM64_INS_CPYMWTWN = 238 , ARM64_INS_CPYP = 239 , ARM64_INS_CPYPN = 240 , ARM64_INS_CPYPRN = 241 , ARM64_INS_CPYPRT = 242 , ARM64_INS_CPYPRTN = 243 , ARM64_INS_CPYPRTRN = 244 , ARM64_INS_CPYPRTWN = 245 , ARM64_INS_CPYPT = 246 , ARM64_INS_CPYPTN = 247 , ARM64_INS_CPYPTRN = 248 , ARM64_INS_CPYPTWN = 249 , ARM64_INS_CPYPWN = 250 , ARM64_INS_CPYPWT = 251 , ARM64_INS_CPYPWTN = 252 , ARM64_INS_CPYPWTRN = 253 , ARM64_INS_CPYPWTWN = 254 , ARM64_INS_CRC32B = 255 , ARM64_INS_CRC32CB = 256 , ARM64_INS_CRC32CH = 257 , ARM64_INS_CRC32CW = 258 , ARM64_INS_CRC32CX = 259 , ARM64_INS_CRC32H = 260 , ARM64_INS_CRC32W = 261 , ARM64_INS_CRC32X = 262 , ARM64_INS_CSDB = 263 , ARM64_INS_CSEL = 264 , ARM64_INS_CSET = 265 , ARM64_INS_CSETM = 266 , ARM64_INS_CSINC = 267 , ARM64_INS_CSINV = 268 , ARM64_INS_CSNEG = 269 , ARM64_INS_CTERMEQ = 270 , ARM64_INS_CTERMNE = 271 , ARM64_INS_DCPS1 = 272 , ARM64_INS_DCPS2 = 273 , ARM64_INS_DCPS3 = 274 , ARM64_INS_DECB = 275 , ARM64_INS_DECD = 276 , ARM64_INS_DECH = 277 , ARM64_INS_DECP = 278 , ARM64_INS_DECW = 279 , ARM64_INS_DFB = 280 , ARM64_INS_DGH = 281 , ARM64_INS_DMB = 282 , ARM64_INS_DRPS = 283 , ARM64_INS_DSB = 284 , ARM64_INS_DUP = 285 , ARM64_INS_DUPM = 286 , ARM64_INS_EON = 287 , ARM64_INS_EOR = 288 , ARM64_INS_EOR3 = 289 , ARM64_INS_EORBT = 290 , ARM64_INS_EORS = 291 , ARM64_INS_EORTB = 292 , ARM64_INS_EORV = 293 , ARM64_INS_ERET = 294 , ARM64_INS_ERETAA = 295 , ARM64_INS_ERETAB = 296 , ARM64_INS_ESB = 297 , ARM64_INS_EXT = 298 , ARM64_INS_EXTR = 299 , ARM64_INS_FABD = 300 , ARM64_INS_FABS = 301 , ARM64_INS_FACGE = 302 , ARM64_INS_FACGT = 303 , ARM64_INS_FACLE = 304 , ARM64_INS_FACLT = 305 , ARM64_INS_FADD = 306 , ARM64_INS_FADDA = 307 , ARM64_INS_FADDP = 308 , ARM64_INS_FADDV = 309 , ARM64_INS_FCADD = 310 , ARM64_INS_FCCMP = 311 , ARM64_INS_FCCMPE = 312 , ARM64_INS_FCMEQ = 313 , ARM64_INS_FCMGE = 314 , ARM64_INS_FCMGT = 315 , ARM64_INS_FCMLA = 316 , ARM64_INS_FCMLE = 317 , ARM64_INS_FCMLT = 318 , ARM64_INS_FCMNE = 319 , ARM64_INS_FCMP = 320 , ARM64_INS_FCMPE = 321 , ARM64_INS_FCMUO = 322 , ARM64_INS_FCPY = 323 , ARM64_INS_FCSEL = 324 , ARM64_INS_FCVT = 325 , ARM64_INS_FCVTAS = 326 , ARM64_INS_FCVTAU = 327 , ARM64_INS_FCVTL = 328 , ARM64_INS_FCVTL2 = 329 , ARM64_INS_FCVTLT = 330 , ARM64_INS_FCVTMS = 331 , ARM64_INS_FCVTMU = 332 , ARM64_INS_FCVTN = 333 , ARM64_INS_FCVTN2 = 334 , ARM64_INS_FCVTNS = 335 , ARM64_INS_FCVTNT = 336 , ARM64_INS_FCVTNU = 337 , ARM64_INS_FCVTPS = 338 , ARM64_INS_FCVTPU = 339 , ARM64_INS_FCVTX = 340 , ARM64_INS_FCVTXN = 341 , ARM64_INS_FCVTXN2 = 342 , ARM64_INS_FCVTXNT = 343 , ARM64_INS_FCVTZS = 344 , ARM64_INS_FCVTZU = 345 , ARM64_INS_FDIV = 346 , ARM64_INS_FDIVR = 347 , ARM64_INS_FDUP = 348 , ARM64_INS_FEXPA = 349 , ARM64_INS_FJCVTZS = 350 , ARM64_INS_FLOGB = 351 , ARM64_INS_FMAD = 352 , ARM64_INS_FMADD = 353 , ARM64_INS_FMAX = 354 , ARM64_INS_FMAXNM = 355 , ARM64_INS_FMAXNMP = 356 , ARM64_INS_FMAXNMV = 357 , ARM64_INS_FMAXP = 358 , ARM64_INS_FMAXV = 359 , ARM64_INS_FMIN = 360 , ARM64_INS_FMINNM = 361 , ARM64_INS_FMINNMP = 362 , ARM64_INS_FMINNMV = 363 , ARM64_INS_FMINP = 364 , ARM64_INS_FMINV = 365 , ARM64_INS_FMLA = 366 , ARM64_INS_FMLAL = 367 , ARM64_INS_FMLAL2 = 368 , ARM64_INS_FMLALB = 369 , ARM64_INS_FMLALT = 370 , ARM64_INS_FMLS = 371 , ARM64_INS_FMLSL = 372 , ARM64_INS_FMLSL2 = 373 , ARM64_INS_FMLSLB = 374 , ARM64_INS_FMLSLT = 375 , ARM64_INS_FMMLA = 376 , ARM64_INS_FMOPA = 377 , ARM64_INS_FMOPS = 378 , ARM64_INS_FMOV = 379 , ARM64_INS_FMSB = 380 , ARM64_INS_FMSUB = 381 , ARM64_INS_FMUL = 382 , ARM64_INS_FMULX = 383 , ARM64_INS_FNEG = 384 , ARM64_INS_FNMAD = 385 , ARM64_INS_FNMADD = 386 , ARM64_INS_FNMLA = 387 , ARM64_INS_FNMLS = 388 , ARM64_INS_FNMSB = 389 , ARM64_INS_FNMSUB = 390 , ARM64_INS_FNMUL = 391 , ARM64_INS_FRECPE = 392 , ARM64_INS_FRECPS = 393 , ARM64_INS_FRECPX = 394 , ARM64_INS_FRINT32X = 395 , ARM64_INS_FRINT32Z = 396 , ARM64_INS_FRINT64X = 397 , ARM64_INS_FRINT64Z = 398 , ARM64_INS_FRINTA = 399 , ARM64_INS_FRINTI = 400 , ARM64_INS_FRINTM = 401 , ARM64_INS_FRINTN = 402 , ARM64_INS_FRINTP = 403 , ARM64_INS_FRINTX = 404 , ARM64_INS_FRINTZ = 405 , ARM64_INS_FRSQRTE = 406 , ARM64_INS_FRSQRTS = 407 , ARM64_INS_FSCALE = 408 , ARM64_INS_FSQRT = 409 , ARM64_INS_FSUB = 410 , ARM64_INS_FSUBR = 411 , ARM64_INS_FTMAD = 412 , ARM64_INS_FTSMUL = 413 , ARM64_INS_FTSSEL = 414 , ARM64_INS_GMI = 415 , ARM64_INS_HINT = 416 , ARM64_INS_HISTCNT = 417 , ARM64_INS_HISTSEG = 418 , ARM64_INS_HLT = 419 , ARM64_INS_HVC = 420 , ARM64_INS_INCB = 421 , ARM64_INS_INCD = 422 , ARM64_INS_INCH = 423 , ARM64_INS_INCP = 424 , ARM64_INS_INCW = 425 , ARM64_INS_INDEX = 426 , ARM64_INS_INS = 427 , ARM64_INS_INSR = 428 , ARM64_INS_IRG = 429 , ARM64_INS_ISB = 430 , ARM64_INS_LASTA = 431 , ARM64_INS_LASTB = 432 , ARM64_INS_LD1 = 433 , ARM64_INS_LD1B = 434 , ARM64_INS_LD1D = 435 , ARM64_INS_LD1H = 436 , ARM64_INS_LD1Q = 437 , ARM64_INS_LD1R = 438 , ARM64_INS_LD1RB = 439 , ARM64_INS_LD1RD = 440 , ARM64_INS_LD1RH = 441 , ARM64_INS_LD1ROB = 442 , ARM64_INS_LD1ROD = 443 , ARM64_INS_LD1ROH = 444 , ARM64_INS_LD1ROW = 445 , ARM64_INS_LD1RQB = 446 , ARM64_INS_LD1RQD = 447 , ARM64_INS_LD1RQH = 448 , ARM64_INS_LD1RQW = 449 , ARM64_INS_LD1RSB = 450 , ARM64_INS_LD1RSH = 451 , ARM64_INS_LD1RSW = 452 , ARM64_INS_LD1RW = 453 , ARM64_INS_LD1SB = 454 , ARM64_INS_LD1SH = 455 , ARM64_INS_LD1SW = 456 , ARM64_INS_LD1W = 457 , ARM64_INS_LD2 = 458 , ARM64_INS_LD2B = 459 , ARM64_INS_LD2D = 460 , ARM64_INS_LD2H = 461 , ARM64_INS_LD2R = 462 , ARM64_INS_LD2W = 463 , ARM64_INS_LD3 = 464 , ARM64_INS_LD3B = 465 , ARM64_INS_LD3D = 466 , ARM64_INS_LD3H = 467 , ARM64_INS_LD3R = 468 , ARM64_INS_LD3W = 469 , ARM64_INS_LD4 = 470 , ARM64_INS_LD4B = 471 , ARM64_INS_LD4D = 472 , ARM64_INS_LD4H = 473 , ARM64_INS_LD4R = 474 , ARM64_INS_LD4W = 475 , ARM64_INS_LD64B = 476 , ARM64_INS_LDADD = 477 , ARM64_INS_LDADDA = 478 , ARM64_INS_LDADDAB = 479 , ARM64_INS_LDADDAH = 480 , ARM64_INS_LDADDAL = 481 , ARM64_INS_LDADDALB = 482 , ARM64_INS_LDADDALH = 483 , ARM64_INS_LDADDB = 484 , ARM64_INS_LDADDH = 485 , ARM64_INS_LDADDL = 486 , ARM64_INS_LDADDLB = 487 , ARM64_INS_LDADDLH = 488 , ARM64_INS_LDAPR = 489 , ARM64_INS_LDAPRB = 490 , ARM64_INS_LDAPRH = 491 , ARM64_INS_LDAPUR = 492 , ARM64_INS_LDAPURB = 493 , ARM64_INS_LDAPURH = 494 , ARM64_INS_LDAPURSB = 495 , ARM64_INS_LDAPURSH = 496 , ARM64_INS_LDAPURSW = 497 , ARM64_INS_LDAR = 498 , ARM64_INS_LDARB = 499 , ARM64_INS_LDARH = 500 , ARM64_INS_LDAXP = 501 , ARM64_INS_LDAXR = 502 , ARM64_INS_LDAXRB = 503 , ARM64_INS_LDAXRH = 504 , ARM64_INS_LDCLR = 505 , ARM64_INS_LDCLRA = 506 , ARM64_INS_LDCLRAB = 507 , ARM64_INS_LDCLRAH = 508 , ARM64_INS_LDCLRAL = 509 , ARM64_INS_LDCLRALB = 510 , ARM64_INS_LDCLRALH = 511 , ARM64_INS_LDCLRB = 512 , ARM64_INS_LDCLRH = 513 , ARM64_INS_LDCLRL = 514 , ARM64_INS_LDCLRLB = 515 , ARM64_INS_LDCLRLH = 516 , ARM64_INS_LDEOR = 517 , ARM64_INS_LDEORA = 518 , ARM64_INS_LDEORAB = 519 , ARM64_INS_LDEORAH = 520 , ARM64_INS_LDEORAL = 521 , ARM64_INS_LDEORALB = 522 , ARM64_INS_LDEORALH = 523 , ARM64_INS_LDEORB = 524 , ARM64_INS_LDEORH = 525 , ARM64_INS_LDEORL = 526 , ARM64_INS_LDEORLB = 527 , ARM64_INS_LDEORLH = 528 , ARM64_INS_LDFF1B = 529 , ARM64_INS_LDFF1D = 530 , ARM64_INS_LDFF1H = 531 , ARM64_INS_LDFF1SB = 532 , ARM64_INS_LDFF1SH = 533 , ARM64_INS_LDFF1SW = 534 , ARM64_INS_LDFF1W = 535 , ARM64_INS_LDG = 536 , ARM64_INS_LDGM = 537 , ARM64_INS_LDLAR = 538 , ARM64_INS_LDLARB = 539 , ARM64_INS_LDLARH = 540 , ARM64_INS_LDNF1B = 541 , ARM64_INS_LDNF1D = 542 , ARM64_INS_LDNF1H = 543 , ARM64_INS_LDNF1SB = 544 , ARM64_INS_LDNF1SH = 545 , ARM64_INS_LDNF1SW = 546 , ARM64_INS_LDNF1W = 547 , ARM64_INS_LDNP = 548 , ARM64_INS_LDNT1B = 549 , ARM64_INS_LDNT1D = 550 , ARM64_INS_LDNT1H = 551 , ARM64_INS_LDNT1SB = 552 , ARM64_INS_LDNT1SH = 553 , ARM64_INS_LDNT1SW = 554 , ARM64_INS_LDNT1W = 555 , ARM64_INS_LDP = 556 , ARM64_INS_LDPSW = 557 , ARM64_INS_LDR = 558 , ARM64_INS_LDRAA = 559 , ARM64_INS_LDRAB = 560 , ARM64_INS_LDRB = 561 , ARM64_INS_LDRH = 562 , ARM64_INS_LDRSB = 563 , ARM64_INS_LDRSH = 564 , ARM64_INS_LDRSW = 565 , ARM64_INS_LDSET = 566 , ARM64_INS_LDSETA = 567 , ARM64_INS_LDSETAB = 568 , ARM64_INS_LDSETAH = 569 , ARM64_INS_LDSETAL = 570 , ARM64_INS_LDSETALB = 571 , ARM64_INS_LDSETALH = 572 , ARM64_INS_LDSETB = 573 , ARM64_INS_LDSETH = 574 , ARM64_INS_LDSETL = 575 , ARM64_INS_LDSETLB = 576 , ARM64_INS_LDSETLH = 577 , ARM64_INS_LDSMAX = 578 , ARM64_INS_LDSMAXA = 579 , ARM64_INS_LDSMAXAB = 580 , ARM64_INS_LDSMAXAH = 581 , ARM64_INS_LDSMAXAL = 582 , ARM64_INS_LDSMAXALB = 583 , ARM64_INS_LDSMAXALH = 584 , ARM64_INS_LDSMAXB = 585 , ARM64_INS_LDSMAXH = 586 , ARM64_INS_LDSMAXL = 587 , ARM64_INS_LDSMAXLB = 588 , ARM64_INS_LDSMAXLH = 589 , ARM64_INS_LDSMIN = 590 , ARM64_INS_LDSMINA = 591 , ARM64_INS_LDSMINAB = 592 , ARM64_INS_LDSMINAH = 593 , ARM64_INS_LDSMINAL = 594 , ARM64_INS_LDSMINALB = 595 , ARM64_INS_LDSMINALH = 596 , ARM64_INS_LDSMINB = 597 , ARM64_INS_LDSMINH = 598 , ARM64_INS_LDSMINL = 599 , ARM64_INS_LDSMINLB = 600 , ARM64_INS_LDSMINLH = 601 , ARM64_INS_LDTR = 602 , ARM64_INS_LDTRB = 603 , ARM64_INS_LDTRH = 604 , ARM64_INS_LDTRSB = 605 , ARM64_INS_LDTRSH = 606 , ARM64_INS_LDTRSW = 607 , ARM64_INS_LDUMAX = 608 , ARM64_INS_LDUMAXA = 609 , ARM64_INS_LDUMAXAB = 610 , ARM64_INS_LDUMAXAH = 611 , ARM64_INS_LDUMAXAL = 612 , ARM64_INS_LDUMAXALB = 613 , ARM64_INS_LDUMAXALH = 614 , ARM64_INS_LDUMAXB = 615 , ARM64_INS_LDUMAXH = 616 , ARM64_INS_LDUMAXL = 617 , ARM64_INS_LDUMAXLB = 618 , ARM64_INS_LDUMAXLH = 619 , ARM64_INS_LDUMIN = 620 , ARM64_INS_LDUMINA = 621 , ARM64_INS_LDUMINAB = 622 , ARM64_INS_LDUMINAH = 623 , ARM64_INS_LDUMINAL = 624 , ARM64_INS_LDUMINALB = 625 , ARM64_INS_LDUMINALH = 626 , ARM64_INS_LDUMINB = 627 , ARM64_INS_LDUMINH = 628 , ARM64_INS_LDUMINL = 629 , ARM64_INS_LDUMINLB = 630 , ARM64_INS_LDUMINLH = 631 , ARM64_INS_LDUR = 632 , ARM64_INS_LDURB = 633 , ARM64_INS_LDURH = 634 , ARM64_INS_LDURSB = 635 , ARM64_INS_LDURSH = 636 , ARM64_INS_LDURSW = 637 , ARM64_INS_LDXP = 638 , ARM64_INS_LDXR = 639 , ARM64_INS_LDXRB = 640 , ARM64_INS_LDXRH = 641 , ARM64_INS_LSL = 642 , ARM64_INS_LSLR = 643 , ARM64_INS_LSLV = 644 , ARM64_INS_LSR = 645 , ARM64_INS_LSRR = 646 , ARM64_INS_LSRV = 647 , ARM64_INS_MAD = 648 , ARM64_INS_MADD = 649 , ARM64_INS_MATCH = 650 , ARM64_INS_MLA = 651 , ARM64_INS_MLS = 652 , ARM64_INS_MNEG = 653 , ARM64_INS_MOV = 654 , ARM64_INS_MOVA = 655 , ARM64_INS_MOVI = 656 , ARM64_INS_MOVK = 657 , ARM64_INS_MOVN = 658 , ARM64_INS_MOVPRFX = 659 , ARM64_INS_MOVS = 660 , ARM64_INS_MOVZ = 661 , ARM64_INS_MRS = 662 , ARM64_INS_MSB = 663 , ARM64_INS_MSR = 664 , ARM64_INS_MSUB = 665 , ARM64_INS_MUL = 666 , ARM64_INS_MVN = 667 , ARM64_INS_MVNI = 668 , ARM64_INS_NAND = 669 , ARM64_INS_NANDS = 670 , ARM64_INS_NBSL = 671 , ARM64_INS_NEG = 672 , ARM64_INS_NEGS = 673 , ARM64_INS_NGC = 674 , ARM64_INS_NGCS = 675 , ARM64_INS_NMATCH = 676 , ARM64_INS_NOP = 677 , ARM64_INS_NOR = 678 , ARM64_INS_NORS = 679 , ARM64_INS_NOT = 680 , ARM64_INS_NOTS = 681 , ARM64_INS_ORN = 682 , ARM64_INS_ORNS = 683 , ARM64_INS_ORR = 684 , ARM64_INS_ORRS = 685 , ARM64_INS_ORV = 686 , ARM64_INS_PACDA = 687 , ARM64_INS_PACDB = 688 , ARM64_INS_PACDZA = 689 , ARM64_INS_PACDZB = 690 , ARM64_INS_PACGA = 691 , ARM64_INS_PACIA = 692 , ARM64_INS_PACIA1716 = 693 , ARM64_INS_PACIASP = 694 , ARM64_INS_PACIAZ = 695 , ARM64_INS_PACIB = 696 , ARM64_INS_PACIB1716 = 697 , ARM64_INS_PACIBSP = 698 , ARM64_INS_PACIBZ = 699 , ARM64_INS_PACIZA = 700 , ARM64_INS_PACIZB = 701 , ARM64_INS_PFALSE = 702 , ARM64_INS_PFIRST = 703 , ARM64_INS_PMUL = 704 , ARM64_INS_PMULL = 705 , ARM64_INS_PMULL2 = 706 , ARM64_INS_PMULLB = 707 , ARM64_INS_PMULLT = 708 , ARM64_INS_PNEXT = 709 , ARM64_INS_PRFB = 710 , ARM64_INS_PRFD = 711 , ARM64_INS_PRFH = 712 , ARM64_INS_PRFM = 713 , ARM64_INS_PRFUM = 714 , ARM64_INS_PRFW = 715 , ARM64_INS_PSB = 716 , ARM64_INS_PSEL = 717 , ARM64_INS_PSSBB = 718 , ARM64_INS_PTEST = 719 , ARM64_INS_PTRUE = 720 , ARM64_INS_PTRUES = 721 , ARM64_INS_PUNPKHI = 722 , ARM64_INS_PUNPKLO = 723 , ARM64_INS_RADDHN = 724 , ARM64_INS_RADDHN2 = 725 , ARM64_INS_RADDHNB = 726 , ARM64_INS_RADDHNT = 727 , ARM64_INS_RAX1 = 728 , ARM64_INS_RBIT = 729 , ARM64_INS_RDFFR = 730 , ARM64_INS_RDFFRS = 731 , ARM64_INS_RDVL = 732 , ARM64_INS_RET = 733 , ARM64_INS_RETAA = 734 , ARM64_INS_RETAB = 735 , ARM64_INS_REV = 736 , ARM64_INS_REV16 = 737 , ARM64_INS_REV32 = 738 , ARM64_INS_REV64 = 739 , ARM64_INS_REVB = 740 , ARM64_INS_REVD = 741 , ARM64_INS_REVH = 742 , ARM64_INS_REVW = 743 , ARM64_INS_RMIF = 744 , ARM64_INS_ROR = 745 , ARM64_INS_RORV = 746 , ARM64_INS_RSHRN = 747 , ARM64_INS_RSHRN2 = 748 , ARM64_INS_RSHRNB = 749 , ARM64_INS_RSHRNT = 750 , ARM64_INS_RSUBHN = 751 , ARM64_INS_RSUBHN2 = 752 , ARM64_INS_RSUBHNB = 753 , ARM64_INS_RSUBHNT = 754 , ARM64_INS_SABA = 755 , ARM64_INS_SABAL = 756 , ARM64_INS_SABAL2 = 757 , ARM64_INS_SABALB = 758 , ARM64_INS_SABALT = 759 , ARM64_INS_SABD = 760 , ARM64_INS_SABDL = 761 , ARM64_INS_SABDL2 = 762 , ARM64_INS_SABDLB = 763 , ARM64_INS_SABDLT = 764 , ARM64_INS_SADALP = 765 , ARM64_INS_SADDL = 766 , ARM64_INS_SADDL2 = 767 , ARM64_INS_SADDLB = 768 , ARM64_INS_SADDLBT = 769 , ARM64_INS_SADDLP = 770 , ARM64_INS_SADDLT = 771 , ARM64_INS_SADDLV = 772 , ARM64_INS_SADDV = 773 , ARM64_INS_SADDW = 774 , ARM64_INS_SADDW2 = 775 , ARM64_INS_SADDWB = 776 , ARM64_INS_SADDWT = 777 , ARM64_INS_SB = 778 , ARM64_INS_SBC = 779 , ARM64_INS_SBCLB = 780 , ARM64_INS_SBCLT = 781 , ARM64_INS_SBCS = 782 , ARM64_INS_SBFM = 783 , ARM64_INS_SCLAMP = 784 , ARM64_INS_SCVTF = 785 , ARM64_INS_SDIV = 786 , ARM64_INS_SDIVR = 787 , ARM64_INS_SDOT = 788 , ARM64_INS_SEL = 789 , ARM64_INS_SETE = 790 , ARM64_INS_SETEN = 791 , ARM64_INS_SETET = 792 , ARM64_INS_SETETN = 793 , ARM64_INS_SETF16 = 794 , ARM64_INS_SETF8 = 795 , ARM64_INS_SETFFR = 796 , ARM64_INS_SETGE = 797 , ARM64_INS_SETGEN = 798 , ARM64_INS_SETGET = 799 , ARM64_INS_SETGETN = 800 , ARM64_INS_SETGM = 801 , ARM64_INS_SETGMN = 802 , ARM64_INS_SETGMT = 803 , ARM64_INS_SETGMTN = 804 , ARM64_INS_SETGP = 805 , ARM64_INS_SETGPN = 806 , ARM64_INS_SETGPT = 807 , ARM64_INS_SETGPTN = 808 , ARM64_INS_SETM = 809 , ARM64_INS_SETMN = 810 , ARM64_INS_SETMT = 811 , ARM64_INS_SETMTN = 812 , ARM64_INS_SETP = 813 , ARM64_INS_SETPN = 814 , ARM64_INS_SETPT = 815 , ARM64_INS_SETPTN = 816 , ARM64_INS_SEV = 817 , ARM64_INS_SEVL = 818 , ARM64_INS_SHA1C = 819 , ARM64_INS_SHA1H = 820 , ARM64_INS_SHA1M = 821 , ARM64_INS_SHA1P = 822 , ARM64_INS_SHA1SU0 = 823 , ARM64_INS_SHA1SU1 = 824 , ARM64_INS_SHA256H = 825 , ARM64_INS_SHA256H2 = 826 , ARM64_INS_SHA256SU0 = 827 , ARM64_INS_SHA256SU1 = 828 , ARM64_INS_SHA512H = 829 , ARM64_INS_SHA512H2 = 830 , ARM64_INS_SHA512SU0 = 831 , ARM64_INS_SHA512SU1 = 832 , ARM64_INS_SHADD = 833 , ARM64_INS_SHL = 834 , ARM64_INS_SHLL = 835 , ARM64_INS_SHLL2 = 836 , ARM64_INS_SHRN = 837 , ARM64_INS_SHRN2 = 838 , ARM64_INS_SHRNB = 839 , ARM64_INS_SHRNT = 840 , ARM64_INS_SHSUB = 841 , ARM64_INS_SHSUBR = 842 , ARM64_INS_SLI = 843 , ARM64_INS_SM3PARTW1 = 844 , ARM64_INS_SM3PARTW2 = 845 , ARM64_INS_SM3SS1 = 846 , ARM64_INS_SM3TT1A = 847 , ARM64_INS_SM3TT1B = 848 , ARM64_INS_SM3TT2A = 849 , ARM64_INS_SM3TT2B = 850 , ARM64_INS_SM4E = 851 , ARM64_INS_SM4EKEY = 852 , ARM64_INS_SMADDL = 853 , ARM64_INS_SMAX = 854 , ARM64_INS_SMAXP = 855 , ARM64_INS_SMAXV = 856 , ARM64_INS_SMC = 857 , ARM64_INS_SMIN = 858 , ARM64_INS_SMINP = 859 , ARM64_INS_SMINV = 860 , ARM64_INS_SMLAL = 861 , ARM64_INS_SMLAL2 = 862 , ARM64_INS_SMLALB = 863 , ARM64_INS_SMLALT = 864 , ARM64_INS_SMLSL = 865 , ARM64_INS_SMLSL2 = 866 , ARM64_INS_SMLSLB = 867 , ARM64_INS_SMLSLT = 868 , ARM64_INS_SMMLA = 869 , ARM64_INS_SMNEGL = 870 , ARM64_INS_SMOPA = 871 , ARM64_INS_SMOPS = 872 , ARM64_INS_SMOV = 873 , ARM64_INS_SMSTART = 874 , ARM64_INS_SMSTOP = 875 , ARM64_INS_SMSUBL = 876 , ARM64_INS_SMULH = 877 , ARM64_INS_SMULL = 878 , ARM64_INS_SMULL2 = 879 , ARM64_INS_SMULLB = 880 , ARM64_INS_SMULLT = 881 , ARM64_INS_SPLICE = 882 , ARM64_INS_SQABS = 883 , ARM64_INS_SQADD = 884 , ARM64_INS_SQCADD = 885 , ARM64_INS_SQDECB = 886 , ARM64_INS_SQDECD = 887 , ARM64_INS_SQDECH = 888 , ARM64_INS_SQDECP = 889 , ARM64_INS_SQDECW = 890 , ARM64_INS_SQDMLAL = 891 , ARM64_INS_SQDMLAL2 = 892 , ARM64_INS_SQDMLALB = 893 , ARM64_INS_SQDMLALBT = 894 , ARM64_INS_SQDMLALT = 895 , ARM64_INS_SQDMLSL = 896 , ARM64_INS_SQDMLSL2 = 897 , ARM64_INS_SQDMLSLB = 898 , ARM64_INS_SQDMLSLBT = 899 , ARM64_INS_SQDMLSLT = 900 , ARM64_INS_SQDMULH = 901 , ARM64_INS_SQDMULL = 902 , ARM64_INS_SQDMULL2 = 903 , ARM64_INS_SQDMULLB = 904 , ARM64_INS_SQDMULLT = 905 , ARM64_INS_SQINCB = 906 , ARM64_INS_SQINCD = 907 , ARM64_INS_SQINCH = 908 , ARM64_INS_SQINCP = 909 , ARM64_INS_SQINCW = 910 , ARM64_INS_SQNEG = 911 , ARM64_INS_SQRDCMLAH = 912 , ARM64_INS_SQRDMLAH = 913 , ARM64_INS_SQRDMLSH = 914 , ARM64_INS_SQRDMULH = 915 , ARM64_INS_SQRSHL = 916 , ARM64_INS_SQRSHLR = 917 , ARM64_INS_SQRSHRN = 918 , ARM64_INS_SQRSHRN2 = 919 , ARM64_INS_SQRSHRNB = 920 , ARM64_INS_SQRSHRNT = 921 , ARM64_INS_SQRSHRUN = 922 , ARM64_INS_SQRSHRUN2 = 923 , ARM64_INS_SQRSHRUNB = 924 , ARM64_INS_SQRSHRUNT = 925 , ARM64_INS_SQSHL = 926 , ARM64_INS_SQSHLR = 927 , ARM64_INS_SQSHLU = 928 , ARM64_INS_SQSHRN = 929 , ARM64_INS_SQSHRN2 = 930 , ARM64_INS_SQSHRNB = 931 , ARM64_INS_SQSHRNT = 932 , ARM64_INS_SQSHRUN = 933 , ARM64_INS_SQSHRUN2 = 934 , ARM64_INS_SQSHRUNB = 935 , ARM64_INS_SQSHRUNT = 936 , ARM64_INS_SQSUB = 937 , ARM64_INS_SQSUBR = 938 , ARM64_INS_SQXTN = 939 , ARM64_INS_SQXTN2 = 940 , ARM64_INS_SQXTNB = 941 , ARM64_INS_SQXTNT = 942 , ARM64_INS_SQXTUN = 943 , ARM64_INS_SQXTUN2 = 944 , ARM64_INS_SQXTUNB = 945 , ARM64_INS_SQXTUNT = 946 , ARM64_INS_SRHADD = 947 , ARM64_INS_SRI = 948 , ARM64_INS_SRSHL = 949 , ARM64_INS_SRSHLR = 950 , ARM64_INS_SRSHR = 951 , ARM64_INS_SRSRA = 952 , ARM64_INS_SSBB = 953 , ARM64_INS_SSHL = 954 , ARM64_INS_SSHLL = 955 , ARM64_INS_SSHLL2 = 956 , ARM64_INS_SSHLLB = 957 , ARM64_INS_SSHLLT = 958 , ARM64_INS_SSHR = 959 , ARM64_INS_SSRA = 960 , ARM64_INS_SSUBL = 961 , ARM64_INS_SSUBL2 = 962 , ARM64_INS_SSUBLB = 963 , ARM64_INS_SSUBLBT = 964 , ARM64_INS_SSUBLT = 965 , ARM64_INS_SSUBLTB = 966 , ARM64_INS_SSUBW = 967 , ARM64_INS_SSUBW2 = 968 , ARM64_INS_SSUBWB = 969 , ARM64_INS_SSUBWT = 970 , ARM64_INS_ST1 = 971 , ARM64_INS_ST1B = 972 , ARM64_INS_ST1D = 973 , ARM64_INS_ST1H = 974 , ARM64_INS_ST1Q = 975 , ARM64_INS_ST1W = 976 , ARM64_INS_ST2 = 977 , ARM64_INS_ST2B = 978 , ARM64_INS_ST2D = 979 , ARM64_INS_ST2G = 980 , ARM64_INS_ST2H = 981 , ARM64_INS_ST2W = 982 , ARM64_INS_ST3 = 983 , ARM64_INS_ST3B = 984 , ARM64_INS_ST3D = 985 , ARM64_INS_ST3H = 986 , ARM64_INS_ST3W = 987 , ARM64_INS_ST4 = 988 , ARM64_INS_ST4B = 989 , ARM64_INS_ST4D = 990 , ARM64_INS_ST4H = 991 , ARM64_INS_ST4W = 992 , ARM64_INS_ST64B = 993 , ARM64_INS_ST64BV = 994 , ARM64_INS_ST64BV0 = 995 , ARM64_INS_STADD = 996 , ARM64_INS_STADDB = 997 , ARM64_INS_STADDH = 998 , ARM64_INS_STADDL = 999 , ARM64_INS_STADDLB = 1000 , ARM64_INS_STADDLH = 1001 , ARM64_INS_STCLR = 1002 , ARM64_INS_STCLRB = 1003 , ARM64_INS_STCLRH = 1004 , ARM64_INS_STCLRL = 1005 , ARM64_INS_STCLRLB = 1006 , ARM64_INS_STCLRLH = 1007 , ARM64_INS_STEOR = 1008 , ARM64_INS_STEORB = 1009 , ARM64_INS_STEORH = 1010 , ARM64_INS_STEORL = 1011 , ARM64_INS_STEORLB = 1012 , ARM64_INS_STEORLH = 1013 , ARM64_INS_STG = 1014 , ARM64_INS_STGM = 1015 , ARM64_INS_STGP = 1016 , ARM64_INS_STLLR = 1017 , ARM64_INS_STLLRB = 1018 , ARM64_INS_STLLRH = 1019 , ARM64_INS_STLR = 1020 , ARM64_INS_STLRB = 1021 , ARM64_INS_STLRH = 1022 , ARM64_INS_STLUR = 1023 , ARM64_INS_STLURB = 1024 , ARM64_INS_STLURH = 1025 , ARM64_INS_STLXP = 1026 , ARM64_INS_STLXR = 1027 , ARM64_INS_STLXRB = 1028 , ARM64_INS_STLXRH = 1029 , ARM64_INS_STNP = 1030 , ARM64_INS_STNT1B = 1031 , ARM64_INS_STNT1D = 1032 , ARM64_INS_STNT1H = 1033 , ARM64_INS_STNT1W = 1034 , ARM64_INS_STP = 1035 , ARM64_INS_STR = 1036 , ARM64_INS_STRB = 1037 , ARM64_INS_STRH = 1038 , ARM64_INS_STSET = 1039 , ARM64_INS_STSETB = 1040 , ARM64_INS_STSETH = 1041 , ARM64_INS_STSETL = 1042 , ARM64_INS_STSETLB = 1043 , ARM64_INS_STSETLH = 1044 , ARM64_INS_STSMAX = 1045 , ARM64_INS_STSMAXB = 1046 , ARM64_INS_STSMAXH = 1047 , ARM64_INS_STSMAXL = 1048 , ARM64_INS_STSMAXLB = 1049 , ARM64_INS_STSMAXLH = 1050 , ARM64_INS_STSMIN = 1051 , ARM64_INS_STSMINB = 1052 , ARM64_INS_STSMINH = 1053 , ARM64_INS_STSMINL = 1054 , ARM64_INS_STSMINLB = 1055 , ARM64_INS_STSMINLH = 1056 , ARM64_INS_STTR = 1057 , ARM64_INS_STTRB = 1058 , ARM64_INS_STTRH = 1059 , ARM64_INS_STUMAX = 1060 , ARM64_INS_STUMAXB = 1061 , ARM64_INS_STUMAXH = 1062 , ARM64_INS_STUMAXL = 1063 , ARM64_INS_STUMAXLB = 1064 , ARM64_INS_STUMAXLH = 1065 , ARM64_INS_STUMIN = 1066 , ARM64_INS_STUMINB = 1067 , ARM64_INS_STUMINH = 1068 , ARM64_INS_STUMINL = 1069 , ARM64_INS_STUMINLB = 1070 , ARM64_INS_STUMINLH = 1071 , ARM64_INS_STUR = 1072 , ARM64_INS_STURB = 1073 , ARM64_INS_STURH = 1074 , ARM64_INS_STXP = 1075 , ARM64_INS_STXR = 1076 , ARM64_INS_STXRB = 1077 , ARM64_INS_STXRH = 1078 , ARM64_INS_STZ2G = 1079 , ARM64_INS_STZG = 1080 , ARM64_INS_STZGM = 1081 , ARM64_INS_SUB = 1082 , ARM64_INS_SUBG = 1083 , ARM64_INS_SUBHN = 1084 , ARM64_INS_SUBHN2 = 1085 , ARM64_INS_SUBHNB = 1086 , ARM64_INS_SUBHNT = 1087 , ARM64_INS_SUBP = 1088 , ARM64_INS_SUBPS = 1089 , ARM64_INS_SUBR = 1090 , ARM64_INS_SUBS = 1091 , ARM64_INS_SUDOT = 1092 , ARM64_INS_SUMOPA = 1093 , ARM64_INS_SUMOPS = 1094 , ARM64_INS_SUNPKHI = 1095 , ARM64_INS_SUNPKLO = 1096 , ARM64_INS_SUQADD = 1097 , ARM64_INS_SVC = 1098 , ARM64_INS_SWP = 1099 , ARM64_INS_SWPA = 1100 , ARM64_INS_SWPAB = 1101 , ARM64_INS_SWPAH = 1102 , ARM64_INS_SWPAL = 1103 , ARM64_INS_SWPALB = 1104 , ARM64_INS_SWPALH = 1105 , ARM64_INS_SWPB = 1106 , ARM64_INS_SWPH = 1107 , ARM64_INS_SWPL = 1108 , ARM64_INS_SWPLB = 1109 , ARM64_INS_SWPLH = 1110 , ARM64_INS_SXTB = 1111 , ARM64_INS_SXTH = 1112 , ARM64_INS_SXTL = 1113 , ARM64_INS_SXTL2 = 1114 , ARM64_INS_SXTW = 1115 , ARM64_INS_SYS = 1116 , ARM64_INS_SYSL = 1117 , ARM64_INS_TBL = 1118 , ARM64_INS_TBNZ = 1119 , ARM64_INS_TBX = 1120 , ARM64_INS_TBZ = 1121 , ARM64_INS_TCANCEL = 1122 , ARM64_INS_TCOMMIT = 1123 , ARM64_INS_TRN1 = 1124 , ARM64_INS_TRN2 = 1125 , ARM64_INS_TSB = 1126 , ARM64_INS_TST = 1127 , ARM64_INS_TSTART = 1128 , ARM64_INS_TTEST = 1129 , ARM64_INS_UABA = 1130 , ARM64_INS_UABAL = 1131 , ARM64_INS_UABAL2 = 1132 , ARM64_INS_UABALB = 1133 , ARM64_INS_UABALT = 1134 , ARM64_INS_UABD = 1135 , ARM64_INS_UABDL = 1136 , ARM64_INS_UABDL2 = 1137 , ARM64_INS_UABDLB = 1138 , ARM64_INS_UABDLT = 1139 , ARM64_INS_UADALP = 1140 , ARM64_INS_UADDL = 1141 , ARM64_INS_UADDL2 = 1142 , ARM64_INS_UADDLB = 1143 , ARM64_INS_UADDLP = 1144 , ARM64_INS_UADDLT = 1145 , ARM64_INS_UADDLV = 1146 , ARM64_INS_UADDV = 1147 , ARM64_INS_UADDW = 1148 , ARM64_INS_UADDW2 = 1149 , ARM64_INS_UADDWB = 1150 , ARM64_INS_UADDWT = 1151 , ARM64_INS_UBFM = 1152 , ARM64_INS_UCLAMP = 1153 , ARM64_INS_UCVTF = 1154 , ARM64_INS_UDF = 1155 , ARM64_INS_UDIV = 1156 , ARM64_INS_UDIVR = 1157 , ARM64_INS_UDOT = 1158 , ARM64_INS_UHADD = 1159 , ARM64_INS_UHSUB = 1160 , ARM64_INS_UHSUBR = 1161 , ARM64_INS_UMADDL = 1162 , ARM64_INS_UMAX = 1163 , ARM64_INS_UMAXP = 1164 , ARM64_INS_UMAXV = 1165 , ARM64_INS_UMIN = 1166 , ARM64_INS_UMINP = 1167 , ARM64_INS_UMINV = 1168 , ARM64_INS_UMLAL = 1169 , ARM64_INS_UMLAL2 = 1170 , ARM64_INS_UMLALB = 1171 , ARM64_INS_UMLALT = 1172 , ARM64_INS_UMLSL = 1173 , ARM64_INS_UMLSL2 = 1174 , ARM64_INS_UMLSLB = 1175 , ARM64_INS_UMLSLT = 1176 , ARM64_INS_UMMLA = 1177 , ARM64_INS_UMNEGL = 1178 , ARM64_INS_UMOPA = 1179 , ARM64_INS_UMOPS = 1180 , ARM64_INS_UMOV = 1181 , ARM64_INS_UMSUBL = 1182 , ARM64_INS_UMULH = 1183 , ARM64_INS_UMULL = 1184 , ARM64_INS_UMULL2 = 1185 , ARM64_INS_UMULLB = 1186 , ARM64_INS_UMULLT = 1187 , ARM64_INS_UQADD = 1188 , ARM64_INS_UQDECB = 1189 , ARM64_INS_UQDECD = 1190 , ARM64_INS_UQDECH = 1191 , ARM64_INS_UQDECP = 1192 , ARM64_INS_UQDECW = 1193 , ARM64_INS_UQINCB = 1194 , ARM64_INS_UQINCD = 1195 , ARM64_INS_UQINCH = 1196 , ARM64_INS_UQINCP = 1197 , ARM64_INS_UQINCW = 1198 , ARM64_INS_UQRSHL = 1199 , ARM64_INS_UQRSHLR = 1200 , ARM64_INS_UQRSHRN = 1201 , ARM64_INS_UQRSHRN2 = 1202 , ARM64_INS_UQRSHRNB = 1203 , ARM64_INS_UQRSHRNT = 1204 , ARM64_INS_UQSHL = 1205 , ARM64_INS_UQSHLR = 1206 , ARM64_INS_UQSHRN = 1207 , ARM64_INS_UQSHRN2 = 1208 , ARM64_INS_UQSHRNB = 1209 , ARM64_INS_UQSHRNT = 1210 , ARM64_INS_UQSUB = 1211 , ARM64_INS_UQSUBR = 1212 , ARM64_INS_UQXTN = 1213 , ARM64_INS_UQXTN2 = 1214 , ARM64_INS_UQXTNB = 1215 , ARM64_INS_UQXTNT = 1216 , ARM64_INS_URECPE = 1217 , ARM64_INS_URHADD = 1218 , ARM64_INS_URSHL = 1219 , ARM64_INS_URSHLR = 1220 , ARM64_INS_URSHR = 1221 , ARM64_INS_URSQRTE = 1222 , ARM64_INS_URSRA = 1223 , ARM64_INS_USDOT = 1224 , ARM64_INS_USHL = 1225 , ARM64_INS_USHLL = 1226 , ARM64_INS_USHLL2 = 1227 , ARM64_INS_USHLLB = 1228 , ARM64_INS_USHLLT = 1229 , ARM64_INS_USHR = 1230 , ARM64_INS_USMMLA = 1231 , ARM64_INS_USMOPA = 1232 , ARM64_INS_USMOPS = 1233 , ARM64_INS_USQADD = 1234 , ARM64_INS_USRA = 1235 , ARM64_INS_USUBL = 1236 , ARM64_INS_USUBL2 = 1237 , ARM64_INS_USUBLB = 1238 , ARM64_INS_USUBLT = 1239 , ARM64_INS_USUBW = 1240 , ARM64_INS_USUBW2 = 1241 , ARM64_INS_USUBWB = 1242 , ARM64_INS_USUBWT = 1243 , ARM64_INS_UUNPKHI = 1244 , ARM64_INS_UUNPKLO = 1245 , ARM64_INS_UXTB = 1246 , ARM64_INS_UXTH = 1247 , ARM64_INS_UXTL = 1248 , ARM64_INS_UXTL2 = 1249 , ARM64_INS_UXTW = 1250 , ARM64_INS_UZP1 = 1251 , ARM64_INS_UZP2 = 1252 , ARM64_INS_WFE = 1253 , ARM64_INS_WFET = 1254 , ARM64_INS_WFI = 1255 , ARM64_INS_WFIT = 1256 , ARM64_INS_WHILEGE = 1257 , ARM64_INS_WHILEGT = 1258 , ARM64_INS_WHILEHI = 1259 , ARM64_INS_WHILEHS = 1260 , ARM64_INS_WHILELE = 1261 , ARM64_INS_WHILELO = 1262 , ARM64_INS_WHILELS = 1263 , ARM64_INS_WHILELT = 1264 , ARM64_INS_WHILERW = 1265 , ARM64_INS_WHILEWR = 1266 , ARM64_INS_WRFFR = 1267 , ARM64_INS_XAFLAG = 1268 , ARM64_INS_XAR = 1269 , ARM64_INS_XPACD = 1270 , ARM64_INS_XPACI = 1271 , ARM64_INS_XPACLRI = 1272 , ARM64_INS_XTN = 1273 , ARM64_INS_XTN2 = 1274 , ARM64_INS_YIELD = 1275 , ARM64_INS_ZERO = 1276 , ARM64_INS_ZIP1 = 1277 , ARM64_INS_ZIP2 = 1278 , ARM64_INS_SBFIZ = 1279 , ARM64_INS_UBFIZ = 1280 , ARM64_INS_SBFX = 1281 , ARM64_INS_UBFX = 1282 , ARM64_INS_BFI = 1283 , ARM64_INS_BFXIL = 1284 , ARM64_INS_IC = 1285 , ARM64_INS_DC = 1286 , ARM64_INS_AT = 1287 , ARM64_INS_TLBI = 1288 , ARM64_INS_ENDING = 1289 , } # [repr (u32)] # [doc = " Group of ARM64 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM64_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM64_GRP_JUMP = 1 , ARM64_GRP_CALL = 2 , ARM64_GRP_RET = 3 , ARM64_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM64_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM64_GRP_BRANCH_RELATIVE = 7 , ARM64_GRP_PAC = 8 , ARM64_GRP_CRYPTO = 128 , ARM64_GRP_FPARMV8 = 129 , ARM64_GRP_NEON = 130 , ARM64_GRP_CRC = 131 , ARM64_GRP_AES = 132 , ARM64_GRP_DOTPROD = 133 , ARM64_GRP_FULLFP16 = 134 , ARM64_GRP_LSE = 135 , ARM64_GRP_RCPC = 136 , ARM64_GRP_RDM = 137 , ARM64_GRP_SHA2 = 138 , ARM64_GRP_SHA3 = 139 , ARM64_GRP_SM4 = 140 , ARM64_GRP_SVE = 141 , ARM64_GRP_SVE2 = 142 , ARM64_GRP_SVE2AES = 143 , ARM64_GRP_SVE2BitPerm = 144 , ARM64_GRP_SVE2SHA3 = 145 , ARM64_GRP_SVE2SM4 = 146 , ARM64_GRP_SME = 147 , ARM64_GRP_SMEF64 = 148 , ARM64_GRP_SMEI64 = 149 , ARM64_GRP_MatMulFP32 = 150 , ARM64_GRP_MatMulFP64 = 151 , ARM64_GRP_MatMulInt8 = 152 , ARM64_GRP_V8_1A = 153 , ARM64_GRP_V8_3A = 154 , ARM64_GRP_V8_4A = 155 , ARM64_GRP_ENDING = 156 , } # [repr (u32)] # [doc = " M68K registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_reg { M68K_REG_INVALID = 0 , M68K_REG_D0 = 1 , M68K_REG_D1 = 2 , M68K_REG_D2 = 3 , M68K_REG_D3 = 4 , M68K_REG_D4 = 5 , M68K_REG_D5 = 6 , M68K_REG_D6 = 7 , M68K_REG_D7 = 8 , M68K_REG_A0 = 9 , M68K_REG_A1 = 10 , M68K_REG_A2 = 11 , M68K_REG_A3 = 12 , M68K_REG_A4 = 13 , M68K_REG_A5 = 14 , M68K_REG_A6 = 15 , M68K_REG_A7 = 16 , M68K_REG_FP0 = 17 , M68K_REG_FP1 = 18 , M68K_REG_FP2 = 19 , M68K_REG_FP3 = 20 , M68K_REG_FP4 = 21 , M68K_REG_FP5 = 22 , M68K_REG_FP6 = 23 , M68K_REG_FP7 = 24 , M68K_REG_PC = 25 , M68K_REG_SR = 26 , M68K_REG_CCR = 27 , M68K_REG_SFC = 28 , M68K_REG_DFC = 29 , M68K_REG_USP = 30 , M68K_REG_VBR = 31 , M68K_REG_CACR = 32 , M68K_REG_CAAR = 33 , M68K_REG_MSP = 34 , M68K_REG_ISP = 35 , M68K_REG_TC = 36 , M68K_REG_ITT0 = 37 , M68K_REG_ITT1 = 38 , M68K_REG_DTT0 = 39 , M68K_REG_DTT1 = 40 , M68K_REG_MMUSR = 41 , M68K_REG_URP = 42 , M68K_REG_SRP = 43 , M68K_REG_FPCR = 44 , M68K_REG_FPSR = 45 , M68K_REG_FPIAR = 46 , M68K_REG_ENDING = 47 , } # [repr (u32)] # [doc = " M68K Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_address_mode { # [doc = "< No address mode."] M68K_AM_NONE = 0 , # [doc = "< Register Direct - Data"] M68K_AM_REG_DIRECT_DATA = 1 , # [doc = "< Register Direct - Address"] M68K_AM_REG_DIRECT_ADDR = 2 , # [doc = "< Register Indirect - Address"] M68K_AM_REGI_ADDR = 3 , # [doc = "< Register Indirect - Address with Postincrement"] M68K_AM_REGI_ADDR_POST_INC = 4 , # [doc = "< Register Indirect - Address with Predecrement"] M68K_AM_REGI_ADDR_PRE_DEC = 5 , # [doc = "< Register Indirect - Address with Displacement"] M68K_AM_REGI_ADDR_DISP = 6 , # [doc = "< Address Register Indirect With Index- 8-bit displacement"] M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 , # [doc = "< Address Register Indirect With Index- Base displacement"] M68K_AM_AREGI_INDEX_BASE_DISP = 8 , # [doc = "< Memory indirect - Postindex"] M68K_AM_MEMI_POST_INDEX = 9 , # [doc = "< Memory indirect - Preindex"] M68K_AM_MEMI_PRE_INDEX = 10 , # [doc = "< Program Counter Indirect - with Displacement"] M68K_AM_PCI_DISP = 11 , # [doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"] M68K_AM_PCI_INDEX_8_BIT_DISP = 12 , # [doc = "< Program Counter Indirect with Index - with Base Displacement"] M68K_AM_PCI_INDEX_BASE_DISP = 13 , # [doc = "< Program Counter Memory Indirect - Postindexed"] M68K_AM_PC_MEMI_POST_INDEX = 14 , # [doc = "< Program Counter Memory Indirect - Preindexed"] M68K_AM_PC_MEMI_PRE_INDEX = 15 , # [doc = "< Absolute Data Addressing  - Short"] M68K_AM_ABSOLUTE_DATA_SHORT = 16 , # [doc = "< Absolute Data Addressing  - Long"] M68K_AM_ABSOLUTE_DATA_LONG = 17 , # [doc = "< Immediate value"] M68K_AM_IMMEDIATE = 18 , # [doc = "< Address as displacement from (PC+2) used by branches"] M68K_AM_BRANCH_DISPLACEMENT = 19 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] M68K_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] M68K_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] M68K_OP_MEM = 3 , # [doc = "< single precision Floating-Point operand"] M68K_OP_FP_SINGLE = 4 , # [doc = "< double precision Floating-Point operand"] M68K_OP_FP_DOUBLE = 5 , # [doc = "< Register bits move"] M68K_OP_REG_BITS = 6 , # [doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"] M68K_OP_REG_PAIR = 7 , # [doc = "< Branch displacement"] M68K_OP_BR_DISP = 8 , } # [doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_mem { # [doc = "< base register (or M68K_REG_INVALID if irrelevant)"] pub base_reg : m68k_reg , # [doc = "< index register (or M68K_REG_INVALID if irrelevant)"] pub index_reg : m68k_reg , # [doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"] pub in_base_reg : m68k_reg , # [doc = "< indirect displacement"] pub in_disp : u32 , # [doc = "< other displacement"] pub out_disp : u32 , # [doc = "< displacement value"] pub disp : i16 , # [doc = "< scale for index register"] pub scale : u8 , # [doc = "< set to true if the two values below should be used"] pub bitfield : u8 , # [doc = "< used for bf* instructions"] pub width : u8 , # [doc = "< used for bf* instructions"] pub offset : u8 , # [doc = "< 0 = w, 1 = l"] pub index_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_mem"] [:: std :: mem :: size_of :: < m68k_op_mem > () - 28usize] ; ["Alignment of m68k_op_mem"] [:: std :: mem :: align_of :: < m68k_op_mem > () - 4usize] ; ["Offset of field: m68k_op_mem::base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , base_reg) - 0usize] ; ["Offset of field: m68k_op_mem::index_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_reg) - 4usize] ; ["Offset of field: m68k_op_mem::in_base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_base_reg) - 8usize] ; ["Offset of field: m68k_op_mem::in_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_disp) - 12usize] ; ["Offset of field: m68k_op_mem::out_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , out_disp) - 16usize] ; ["Offset of field: m68k_op_mem::disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , disp) - 20usize] ; ["Offset of field: m68k_op_mem::scale"] [:: std :: mem :: offset_of ! (m68k_op_mem , scale) - 22usize] ; ["Offset of field: m68k_op_mem::bitfield"] [:: std :: mem :: offset_of ! (m68k_op_mem , bitfield) - 23usize] ; ["Offset of field: m68k_op_mem::width"] [:: std :: mem :: offset_of ! (m68k_op_mem , width) - 24usize] ; ["Offset of field: m68k_op_mem::offset"] [:: std :: mem :: offset_of ! (m68k_op_mem , offset) - 25usize] ; ["Offset of field: m68k_op_mem::index_size"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_size) - 26usize] ; } ; # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_br_disp_size { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_BR_DISP_SIZE_INVALID = 0 , # [doc = "< signed 8-bit displacement"] M68K_OP_BR_DISP_SIZE_BYTE = 1 , # [doc = "< signed 16-bit displacement"] M68K_OP_BR_DISP_SIZE_WORD = 2 , # [doc = "< signed 32-bit displacement"] M68K_OP_BR_DISP_SIZE_LONG = 4 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_br_disp { # [doc = "< displacement value"] pub disp : i32 , # [doc = "< Size from m68k_op_br_disp_size type above"] pub disp_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_br_disp"] [:: std :: mem :: size_of :: < m68k_op_br_disp > () - 8usize] ; ["Alignment of m68k_op_br_disp"] [:: std :: mem :: align_of :: < m68k_op_br_disp > () - 4usize] ; ["Offset of field: m68k_op_br_disp::disp"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp) - 0usize] ; ["Offset of field: m68k_op_br_disp::disp_size"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp_size) - 4usize] ; } ; # [doc = " Register pair in one operand."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_m68k_op_reg_pair { pub reg_0 : m68k_reg , pub reg_1 : m68k_reg , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op_reg_pair"] [:: std :: mem :: size_of :: < cs_m68k_op_reg_pair > () - 8usize] ; ["Alignment of cs_m68k_op_reg_pair"] [:: std :: mem :: align_of :: < cs_m68k_op_reg_pair > () - 4usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_0"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_0) - 0usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_1"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_1) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k_op { pub __bindgen_anon_1 : cs_m68k_op__bindgen_ty_1 , # [doc = "< data when operand is targeting memory"] pub mem : m68k_op_mem , # [doc = "< data when operand is a branch displacement"] pub br_disp : m68k_op_br_disp , # [doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"] pub register_bits : u32 , pub type_ : m68k_op_type , # [doc = "< M68K addressing mode for this op"] pub address_mode : m68k_address_mode , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m68k_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< double imm"] pub dimm : f64 , # [doc = "< float imm"] pub simm : f32 , # [doc = "< register value for REG operand"] pub reg : m68k_reg , # [doc = "< register pair in one operand"] pub reg_pair : cs_m68k_op_reg_pair , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::dimm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , dimm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::simm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , simm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg_pair"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg_pair) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op"] [:: std :: mem :: size_of :: < cs_m68k_op > () - 56usize] ; ["Alignment of cs_m68k_op"] [:: std :: mem :: align_of :: < cs_m68k_op > () - 8usize] ; ["Offset of field: cs_m68k_op::mem"] [:: std :: mem :: offset_of ! (cs_m68k_op , mem) - 8usize] ; ["Offset of field: cs_m68k_op::br_disp"] [:: std :: mem :: offset_of ! (cs_m68k_op , br_disp) - 36usize] ; ["Offset of field: cs_m68k_op::register_bits"] [:: std :: mem :: offset_of ! (cs_m68k_op , register_bits) - 44usize] ; ["Offset of field: cs_m68k_op::type_"] [:: std :: mem :: offset_of ! (cs_m68k_op , type_) - 48usize] ; ["Offset of field: cs_m68k_op::address_mode"] [:: std :: mem :: offset_of ! (cs_m68k_op , address_mode) - 52usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode) } } # [repr (u32)] # [doc = " Operation size of the CPU instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_cpu_size { # [doc = "< unsized or unspecified"] M68K_CPU_SIZE_NONE = 0 , # [doc = "< 1 byte in size"] M68K_CPU_SIZE_BYTE = 1 , # [doc = "< 2 bytes in size"] M68K_CPU_SIZE_WORD = 2 , # [doc = "< 4 bytes in size"] M68K_CPU_SIZE_LONG = 4 , } # [repr (u32)] # [doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_fpu_size { # [doc = "< unsized like fsave/frestore"] M68K_FPU_SIZE_NONE = 0 , # [doc = "< 4 byte in size (single float)"] M68K_FPU_SIZE_SINGLE = 4 , # [doc = "< 8 byte in size (double)"] M68K_FPU_SIZE_DOUBLE = 8 , # [doc = "< 12 byte in size (extended real format)"] M68K_FPU_SIZE_EXTENDED = 12 , } # [repr (u32)] # [doc = " Type of size that is being used for the current instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0 , M68K_SIZE_TYPE_CPU = 1 , M68K_SIZE_TYPE_FPU = 2 , } # [doc = " Operation size of the current instruction (NOT the actually size of instruction)"] # [repr (C)] # [derive (Copy , Clone)] pub struct m68k_op_size { pub type_ : m68k_size_type , pub __bindgen_anon_1 : m68k_op_size__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union m68k_op_size__bindgen_ty_1 { pub cpu_size : m68k_cpu_size , pub fpu_size : m68k_fpu_size , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: size_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Alignment of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: align_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::cpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , cpu_size) - 0usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::fpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , fpu_size) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size"] [:: std :: mem :: size_of :: < m68k_op_size > () - 8usize] ; ["Alignment of m68k_op_size"] [:: std :: mem :: align_of :: < m68k_op_size > () - 4usize] ; ["Offset of field: m68k_op_size::type_"] [:: std :: mem :: offset_of ! (m68k_op_size , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The M68K instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k { # [doc = "< operands for this instruction."] pub operands : [cs_m68k_op ; 4usize] , # [doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"] pub op_size : m68k_op_size , # [doc = "< number of operands for the instruction"] pub op_count : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k"] [:: std :: mem :: size_of :: < cs_m68k > () - 240usize] ; ["Alignment of cs_m68k"] [:: std :: mem :: align_of :: < cs_m68k > () - 8usize] ; ["Offset of field: cs_m68k::operands"] [:: std :: mem :: offset_of ! (cs_m68k , operands) - 0usize] ; ["Offset of field: cs_m68k::op_size"] [:: std :: mem :: offset_of ! (cs_m68k , op_size) - 224usize] ; ["Offset of field: cs_m68k::op_count"] [:: std :: mem :: offset_of ! (cs_m68k , op_count) - 232usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}" , self . operands , self . op_size , self . op_count) } } # [repr (u32)] # [doc = " M68K instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_insn { M68K_INS_INVALID = 0 , M68K_INS_ABCD = 1 , M68K_INS_ADD = 2 , M68K_INS_ADDA = 3 , M68K_INS_ADDI = 4 , M68K_INS_ADDQ = 5 , M68K_INS_ADDX = 6 , M68K_INS_AND = 7 , M68K_INS_ANDI = 8 , M68K_INS_ASL = 9 , M68K_INS_ASR = 10 , M68K_INS_BHS = 11 , M68K_INS_BLO = 12 , M68K_INS_BHI = 13 , M68K_INS_BLS = 14 , M68K_INS_BCC = 15 , M68K_INS_BCS = 16 , M68K_INS_BNE = 17 , M68K_INS_BEQ = 18 , M68K_INS_BVC = 19 , M68K_INS_BVS = 20 , M68K_INS_BPL = 21 , M68K_INS_BMI = 22 , M68K_INS_BGE = 23 , M68K_INS_BLT = 24 , M68K_INS_BGT = 25 , M68K_INS_BLE = 26 , M68K_INS_BRA = 27 , M68K_INS_BSR = 28 , M68K_INS_BCHG = 29 , M68K_INS_BCLR = 30 , M68K_INS_BSET = 31 , M68K_INS_BTST = 32 , M68K_INS_BFCHG = 33 , M68K_INS_BFCLR = 34 , M68K_INS_BFEXTS = 35 , M68K_INS_BFEXTU = 36 , M68K_INS_BFFFO = 37 , M68K_INS_BFINS = 38 , M68K_INS_BFSET = 39 , M68K_INS_BFTST = 40 , M68K_INS_BKPT = 41 , M68K_INS_CALLM = 42 , M68K_INS_CAS = 43 , M68K_INS_CAS2 = 44 , M68K_INS_CHK = 45 , M68K_INS_CHK2 = 46 , M68K_INS_CLR = 47 , M68K_INS_CMP = 48 , M68K_INS_CMPA = 49 , M68K_INS_CMPI = 50 , M68K_INS_CMPM = 51 , M68K_INS_CMP2 = 52 , M68K_INS_CINVL = 53 , M68K_INS_CINVP = 54 , M68K_INS_CINVA = 55 , M68K_INS_CPUSHL = 56 , M68K_INS_CPUSHP = 57 , M68K_INS_CPUSHA = 58 , M68K_INS_DBT = 59 , M68K_INS_DBF = 60 , M68K_INS_DBHI = 61 , M68K_INS_DBLS = 62 , M68K_INS_DBCC = 63 , M68K_INS_DBCS = 64 , M68K_INS_DBNE = 65 , M68K_INS_DBEQ = 66 , M68K_INS_DBVC = 67 , M68K_INS_DBVS = 68 , M68K_INS_DBPL = 69 , M68K_INS_DBMI = 70 , M68K_INS_DBGE = 71 , M68K_INS_DBLT = 72 , M68K_INS_DBGT = 73 , M68K_INS_DBLE = 74 , M68K_INS_DBRA = 75 , M68K_INS_DIVS = 76 , M68K_INS_DIVSL = 77 , M68K_INS_DIVU = 78 , M68K_INS_DIVUL = 79 , M68K_INS_EOR = 80 , M68K_INS_EORI = 81 , M68K_INS_EXG = 82 , M68K_INS_EXT = 83 , M68K_INS_EXTB = 84 , M68K_INS_FABS = 85 , M68K_INS_FSABS = 86 , M68K_INS_FDABS = 87 , M68K_INS_FACOS = 88 , M68K_INS_FADD = 89 , M68K_INS_FSADD = 90 , M68K_INS_FDADD = 91 , M68K_INS_FASIN = 92 , M68K_INS_FATAN = 93 , M68K_INS_FATANH = 94 , M68K_INS_FBF = 95 , M68K_INS_FBEQ = 96 , M68K_INS_FBOGT = 97 , M68K_INS_FBOGE = 98 , M68K_INS_FBOLT = 99 , M68K_INS_FBOLE = 100 , M68K_INS_FBOGL = 101 , M68K_INS_FBOR = 102 , M68K_INS_FBUN = 103 , M68K_INS_FBUEQ = 104 , M68K_INS_FBUGT = 105 , M68K_INS_FBUGE = 106 , M68K_INS_FBULT = 107 , M68K_INS_FBULE = 108 , M68K_INS_FBNE = 109 , M68K_INS_FBT = 110 , M68K_INS_FBSF = 111 , M68K_INS_FBSEQ = 112 , M68K_INS_FBGT = 113 , M68K_INS_FBGE = 114 , M68K_INS_FBLT = 115 , M68K_INS_FBLE = 116 , M68K_INS_FBGL = 117 , M68K_INS_FBGLE = 118 , M68K_INS_FBNGLE = 119 , M68K_INS_FBNGL = 120 , M68K_INS_FBNLE = 121 , M68K_INS_FBNLT = 122 , M68K_INS_FBNGE = 123 , M68K_INS_FBNGT = 124 , M68K_INS_FBSNE = 125 , M68K_INS_FBST = 126 , M68K_INS_FCMP = 127 , M68K_INS_FCOS = 128 , M68K_INS_FCOSH = 129 , M68K_INS_FDBF = 130 , M68K_INS_FDBEQ = 131 , M68K_INS_FDBOGT = 132 , M68K_INS_FDBOGE = 133 , M68K_INS_FDBOLT = 134 , M68K_INS_FDBOLE = 135 , M68K_INS_FDBOGL = 136 , M68K_INS_FDBOR = 137 , M68K_INS_FDBUN = 138 , M68K_INS_FDBUEQ = 139 , M68K_INS_FDBUGT = 140 , M68K_INS_FDBUGE = 141 , M68K_INS_FDBULT = 142 , M68K_INS_FDBULE = 143 , M68K_INS_FDBNE = 144 , M68K_INS_FDBT = 145 , M68K_INS_FDBSF = 146 , M68K_INS_FDBSEQ = 147 , M68K_INS_FDBGT = 148 , M68K_INS_FDBGE = 149 , M68K_INS_FDBLT = 150 , M68K_INS_FDBLE = 151 , M68K_INS_FDBGL = 152 , M68K_INS_FDBGLE = 153 , M68K_INS_FDBNGLE = 154 , M68K_INS_FDBNGL = 155 , M68K_INS_FDBNLE = 156 , M68K_INS_FDBNLT = 157 , M68K_INS_FDBNGE = 158 , M68K_INS_FDBNGT = 159 , M68K_INS_FDBSNE = 160 , M68K_INS_FDBST = 161 , M68K_INS_FDIV = 162 , M68K_INS_FSDIV = 163 , M68K_INS_FDDIV = 164 , M68K_INS_FETOX = 165 , M68K_INS_FETOXM1 = 166 , M68K_INS_FGETEXP = 167 , M68K_INS_FGETMAN = 168 , M68K_INS_FINT = 169 , M68K_INS_FINTRZ = 170 , M68K_INS_FLOG10 = 171 , M68K_INS_FLOG2 = 172 , M68K_INS_FLOGN = 173 , M68K_INS_FLOGNP1 = 174 , M68K_INS_FMOD = 175 , M68K_INS_FMOVE = 176 , M68K_INS_FSMOVE = 177 , M68K_INS_FDMOVE = 178 , M68K_INS_FMOVECR = 179 , M68K_INS_FMOVEM = 180 , M68K_INS_FMUL = 181 , M68K_INS_FSMUL = 182 , M68K_INS_FDMUL = 183 , M68K_INS_FNEG = 184 , M68K_INS_FSNEG = 185 , M68K_INS_FDNEG = 186 , M68K_INS_FNOP = 187 , M68K_INS_FREM = 188 , M68K_INS_FRESTORE = 189 , M68K_INS_FSAVE = 190 , M68K_INS_FSCALE = 191 , M68K_INS_FSGLDIV = 192 , M68K_INS_FSGLMUL = 193 , M68K_INS_FSIN = 194 , M68K_INS_FSINCOS = 195 , M68K_INS_FSINH = 196 , M68K_INS_FSQRT = 197 , M68K_INS_FSSQRT = 198 , M68K_INS_FDSQRT = 199 , M68K_INS_FSF = 200 , M68K_INS_FSBEQ = 201 , M68K_INS_FSOGT = 202 , M68K_INS_FSOGE = 203 , M68K_INS_FSOLT = 204 , M68K_INS_FSOLE = 205 , M68K_INS_FSOGL = 206 , M68K_INS_FSOR = 207 , M68K_INS_FSUN = 208 , M68K_INS_FSUEQ = 209 , M68K_INS_FSUGT = 210 , M68K_INS_FSUGE = 211 , M68K_INS_FSULT = 212 , M68K_INS_FSULE = 213 , M68K_INS_FSNE = 214 , M68K_INS_FST = 215 , M68K_INS_FSSF = 216 , M68K_INS_FSSEQ = 217 , M68K_INS_FSGT = 218 , M68K_INS_FSGE = 219 , M68K_INS_FSLT = 220 , M68K_INS_FSLE = 221 , M68K_INS_FSGL = 222 , M68K_INS_FSGLE = 223 , M68K_INS_FSNGLE = 224 , M68K_INS_FSNGL = 225 , M68K_INS_FSNLE = 226 , M68K_INS_FSNLT = 227 , M68K_INS_FSNGE = 228 , M68K_INS_FSNGT = 229 , M68K_INS_FSSNE = 230 , M68K_INS_FSST = 231 , M68K_INS_FSUB = 232 , M68K_INS_FSSUB = 233 , M68K_INS_FDSUB = 234 , M68K_INS_FTAN = 235 , M68K_INS_FTANH = 236 , M68K_INS_FTENTOX = 237 , M68K_INS_FTRAPF = 238 , M68K_INS_FTRAPEQ = 239 , M68K_INS_FTRAPOGT = 240 , M68K_INS_FTRAPOGE = 241 , M68K_INS_FTRAPOLT = 242 , M68K_INS_FTRAPOLE = 243 , M68K_INS_FTRAPOGL = 244 , M68K_INS_FTRAPOR = 245 , M68K_INS_FTRAPUN = 246 , M68K_INS_FTRAPUEQ = 247 , M68K_INS_FTRAPUGT = 248 , M68K_INS_FTRAPUGE = 249 , M68K_INS_FTRAPULT = 250 , M68K_INS_FTRAPULE = 251 , M68K_INS_FTRAPNE = 252 , M68K_INS_FTRAPT = 253 , M68K_INS_FTRAPSF = 254 , M68K_INS_FTRAPSEQ = 255 , M68K_INS_FTRAPGT = 256 , M68K_INS_FTRAPGE = 257 , M68K_INS_FTRAPLT = 258 , M68K_INS_FTRAPLE = 259 , M68K_INS_FTRAPGL = 260 , M68K_INS_FTRAPGLE = 261 , M68K_INS_FTRAPNGLE = 262 , M68K_INS_FTRAPNGL = 263 , M68K_INS_FTRAPNLE = 264 , M68K_INS_FTRAPNLT = 265 , M68K_INS_FTRAPNGE = 266 , M68K_INS_FTRAPNGT = 267 , M68K_INS_FTRAPSNE = 268 , M68K_INS_FTRAPST = 269 , M68K_INS_FTST = 270 , M68K_INS_FTWOTOX = 271 , M68K_INS_HALT = 272 , M68K_INS_ILLEGAL = 273 , M68K_INS_JMP = 274 , M68K_INS_JSR = 275 , M68K_INS_LEA = 276 , M68K_INS_LINK = 277 , M68K_INS_LPSTOP = 278 , M68K_INS_LSL = 279 , M68K_INS_LSR = 280 , M68K_INS_MOVE = 281 , M68K_INS_MOVEA = 282 , M68K_INS_MOVEC = 283 , M68K_INS_MOVEM = 284 , M68K_INS_MOVEP = 285 , M68K_INS_MOVEQ = 286 , M68K_INS_MOVES = 287 , M68K_INS_MOVE16 = 288 , M68K_INS_MULS = 289 , M68K_INS_MULU = 290 , M68K_INS_NBCD = 291 , M68K_INS_NEG = 292 , M68K_INS_NEGX = 293 , M68K_INS_NOP = 294 , M68K_INS_NOT = 295 , M68K_INS_OR = 296 , M68K_INS_ORI = 297 , M68K_INS_PACK = 298 , M68K_INS_PEA = 299 , M68K_INS_PFLUSH = 300 , M68K_INS_PFLUSHA = 301 , M68K_INS_PFLUSHAN = 302 , M68K_INS_PFLUSHN = 303 , M68K_INS_PLOADR = 304 , M68K_INS_PLOADW = 305 , M68K_INS_PLPAR = 306 , M68K_INS_PLPAW = 307 , M68K_INS_PMOVE = 308 , M68K_INS_PMOVEFD = 309 , M68K_INS_PTESTR = 310 , M68K_INS_PTESTW = 311 , M68K_INS_PULSE = 312 , M68K_INS_REMS = 313 , M68K_INS_REMU = 314 , M68K_INS_RESET = 315 , M68K_INS_ROL = 316 , M68K_INS_ROR = 317 , M68K_INS_ROXL = 318 , M68K_INS_ROXR = 319 , M68K_INS_RTD = 320 , M68K_INS_RTE = 321 , M68K_INS_RTM = 322 , M68K_INS_RTR = 323 , M68K_INS_RTS = 324 , M68K_INS_SBCD = 325 , M68K_INS_ST = 326 , M68K_INS_SF = 327 , M68K_INS_SHI = 328 , M68K_INS_SLS = 329 , M68K_INS_SCC = 330 , M68K_INS_SHS = 331 , M68K_INS_SCS = 332 , M68K_INS_SLO = 333 , M68K_INS_SNE = 334 , M68K_INS_SEQ = 335 , M68K_INS_SVC = 336 , M68K_INS_SVS = 337 , M68K_INS_SPL = 338 , M68K_INS_SMI = 339 , M68K_INS_SGE = 340 , M68K_INS_SLT = 341 , M68K_INS_SGT = 342 , M68K_INS_SLE = 343 , M68K_INS_STOP = 344 , M68K_INS_SUB = 345 , M68K_INS_SUBA = 346 , M68K_INS_SUBI = 347 , M68K_INS_SUBQ = 348 , M68K_INS_SUBX = 349 , M68K_INS_SWAP = 350 , M68K_INS_TAS = 351 , M68K_INS_TRAP = 352 , M68K_INS_TRAPV = 353 , M68K_INS_TRAPT = 354 , M68K_INS_TRAPF = 355 , M68K_INS_TRAPHI = 356 , M68K_INS_TRAPLS = 357 , M68K_INS_TRAPCC = 358 , M68K_INS_TRAPHS = 359 , M68K_INS_TRAPCS = 360 , M68K_INS_TRAPLO = 361 , M68K_INS_TRAPNE = 362 , M68K_INS_TRAPEQ = 363 , M68K_INS_TRAPVC = 364 , M68K_INS_TRAPVS = 365 , M68K_INS_TRAPPL = 366 , M68K_INS_TRAPMI = 367 , M68K_INS_TRAPGE = 368 , M68K_INS_TRAPLT = 369 , M68K_INS_TRAPGT = 370 , M68K_INS_TRAPLE = 371 , M68K_INS_TST = 372 , M68K_INS_UNLK = 373 , M68K_INS_UNPK = 374 , M68K_INS_ENDING = 375 , } # [repr (u32)] # [doc = " Group of M68K instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_group_type { # [doc = "< CS_GRUP_INVALID"] M68K_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M68K_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] M68K_GRP_RET = 3 , # [doc = "< = CS_GRP_IRET"] M68K_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M68K_GRP_BRANCH_RELATIVE = 7 , M68K_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MIPS_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MIPS_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MIPS_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MIPS_OP_MEM = 3 , } impl mips_reg { pub const MIPS_REG_ZERO : mips_reg = mips_reg :: MIPS_REG_0 ; } impl mips_reg { pub const MIPS_REG_AT : mips_reg = mips_reg :: MIPS_REG_1 ; } impl mips_reg { pub const MIPS_REG_V0 : mips_reg = mips_reg :: MIPS_REG_2 ; } impl mips_reg { pub const MIPS_REG_V1 : mips_reg = mips_reg :: MIPS_REG_3 ; } impl mips_reg { pub const MIPS_REG_A0 : mips_reg = mips_reg :: MIPS_REG_4 ; } impl mips_reg { pub const MIPS_REG_A1 : mips_reg = mips_reg :: MIPS_REG_5 ; } impl mips_reg { pub const MIPS_REG_A2 : mips_reg = mips_reg :: MIPS_REG_6 ; } impl mips_reg { pub const MIPS_REG_A3 : mips_reg = mips_reg :: MIPS_REG_7 ; } impl mips_reg { pub const MIPS_REG_T0 : mips_reg = mips_reg :: MIPS_REG_8 ; } impl mips_reg { pub const MIPS_REG_T1 : mips_reg = mips_reg :: MIPS_REG_9 ; } impl mips_reg { pub const MIPS_REG_T2 : mips_reg = mips_reg :: MIPS_REG_10 ; } impl mips_reg { pub const MIPS_REG_T3 : mips_reg = mips_reg :: MIPS_REG_11 ; } impl mips_reg { pub const MIPS_REG_T4 : mips_reg = mips_reg :: MIPS_REG_12 ; } impl mips_reg { pub const MIPS_REG_T5 : mips_reg = mips_reg :: MIPS_REG_13 ; } impl mips_reg { pub const MIPS_REG_T6 : mips_reg = mips_reg :: MIPS_REG_14 ; } impl mips_reg { pub const MIPS_REG_T7 : mips_reg = mips_reg :: MIPS_REG_15 ; } impl mips_reg { pub const MIPS_REG_S0 : mips_reg = mips_reg :: MIPS_REG_16 ; } impl mips_reg { pub const MIPS_REG_S1 : mips_reg = mips_reg :: MIPS_REG_17 ; } impl mips_reg { pub const MIPS_REG_S2 : mips_reg = mips_reg :: MIPS_REG_18 ; } impl mips_reg { pub const MIPS_REG_S3 : mips_reg = mips_reg :: MIPS_REG_19 ; } impl mips_reg { pub const MIPS_REG_S4 : mips_reg = mips_reg :: MIPS_REG_20 ; } impl mips_reg { pub const MIPS_REG_S5 : mips_reg = mips_reg :: MIPS_REG_21 ; } impl mips_reg { pub const MIPS_REG_S6 : mips_reg = mips_reg :: MIPS_REG_22 ; } impl mips_reg { pub const MIPS_REG_S7 : mips_reg = mips_reg :: MIPS_REG_23 ; } impl mips_reg { pub const MIPS_REG_T8 : mips_reg = mips_reg :: MIPS_REG_24 ; } impl mips_reg { pub const MIPS_REG_T9 : mips_reg = mips_reg :: MIPS_REG_25 ; } impl mips_reg { pub const MIPS_REG_K0 : mips_reg = mips_reg :: MIPS_REG_26 ; } impl mips_reg { pub const MIPS_REG_K1 : mips_reg = mips_reg :: MIPS_REG_27 ; } impl mips_reg { pub const MIPS_REG_GP : mips_reg = mips_reg :: MIPS_REG_28 ; } impl mips_reg { pub const MIPS_REG_SP : mips_reg = mips_reg :: MIPS_REG_29 ; } impl mips_reg { pub const MIPS_REG_FP : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_S8 : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_RA : mips_reg = mips_reg :: MIPS_REG_31 ; } impl mips_reg { pub const MIPS_REG_HI0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_HI1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_HI2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_HI3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } impl mips_reg { pub const MIPS_REG_LO0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_LO1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_LO2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_LO3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } # [repr (u32)] # [doc = " MIPS registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_reg { MIPS_REG_INVALID = 0 , MIPS_REG_PC = 1 , MIPS_REG_0 = 2 , MIPS_REG_1 = 3 , MIPS_REG_2 = 4 , MIPS_REG_3 = 5 , MIPS_REG_4 = 6 , MIPS_REG_5 = 7 , MIPS_REG_6 = 8 , MIPS_REG_7 = 9 , MIPS_REG_8 = 10 , MIPS_REG_9 = 11 , MIPS_REG_10 = 12 , MIPS_REG_11 = 13 , MIPS_REG_12 = 14 , MIPS_REG_13 = 15 , MIPS_REG_14 = 16 , MIPS_REG_15 = 17 , MIPS_REG_16 = 18 , MIPS_REG_17 = 19 , MIPS_REG_18 = 20 , MIPS_REG_19 = 21 , MIPS_REG_20 = 22 , MIPS_REG_21 = 23 , MIPS_REG_22 = 24 , MIPS_REG_23 = 25 , MIPS_REG_24 = 26 , MIPS_REG_25 = 27 , MIPS_REG_26 = 28 , MIPS_REG_27 = 29 , MIPS_REG_28 = 30 , MIPS_REG_29 = 31 , MIPS_REG_30 = 32 , MIPS_REG_31 = 33 , MIPS_REG_DSPCCOND = 34 , MIPS_REG_DSPCARRY = 35 , MIPS_REG_DSPEFI = 36 , MIPS_REG_DSPOUTFLAG = 37 , MIPS_REG_DSPOUTFLAG16_19 = 38 , MIPS_REG_DSPOUTFLAG20 = 39 , MIPS_REG_DSPOUTFLAG21 = 40 , MIPS_REG_DSPOUTFLAG22 = 41 , MIPS_REG_DSPOUTFLAG23 = 42 , MIPS_REG_DSPPOS = 43 , MIPS_REG_DSPSCOUNT = 44 , MIPS_REG_AC0 = 45 , MIPS_REG_AC1 = 46 , MIPS_REG_AC2 = 47 , MIPS_REG_AC3 = 48 , MIPS_REG_CC0 = 49 , MIPS_REG_CC1 = 50 , MIPS_REG_CC2 = 51 , MIPS_REG_CC3 = 52 , MIPS_REG_CC4 = 53 , MIPS_REG_CC5 = 54 , MIPS_REG_CC6 = 55 , MIPS_REG_CC7 = 56 , MIPS_REG_F0 = 57 , MIPS_REG_F1 = 58 , MIPS_REG_F2 = 59 , MIPS_REG_F3 = 60 , MIPS_REG_F4 = 61 , MIPS_REG_F5 = 62 , MIPS_REG_F6 = 63 , MIPS_REG_F7 = 64 , MIPS_REG_F8 = 65 , MIPS_REG_F9 = 66 , MIPS_REG_F10 = 67 , MIPS_REG_F11 = 68 , MIPS_REG_F12 = 69 , MIPS_REG_F13 = 70 , MIPS_REG_F14 = 71 , MIPS_REG_F15 = 72 , MIPS_REG_F16 = 73 , MIPS_REG_F17 = 74 , MIPS_REG_F18 = 75 , MIPS_REG_F19 = 76 , MIPS_REG_F20 = 77 , MIPS_REG_F21 = 78 , MIPS_REG_F22 = 79 , MIPS_REG_F23 = 80 , MIPS_REG_F24 = 81 , MIPS_REG_F25 = 82 , MIPS_REG_F26 = 83 , MIPS_REG_F27 = 84 , MIPS_REG_F28 = 85 , MIPS_REG_F29 = 86 , MIPS_REG_F30 = 87 , MIPS_REG_F31 = 88 , MIPS_REG_FCC0 = 89 , MIPS_REG_FCC1 = 90 , MIPS_REG_FCC2 = 91 , MIPS_REG_FCC3 = 92 , MIPS_REG_FCC4 = 93 , MIPS_REG_FCC5 = 94 , MIPS_REG_FCC6 = 95 , MIPS_REG_FCC7 = 96 , MIPS_REG_W0 = 97 , MIPS_REG_W1 = 98 , MIPS_REG_W2 = 99 , MIPS_REG_W3 = 100 , MIPS_REG_W4 = 101 , MIPS_REG_W5 = 102 , MIPS_REG_W6 = 103 , MIPS_REG_W7 = 104 , MIPS_REG_W8 = 105 , MIPS_REG_W9 = 106 , MIPS_REG_W10 = 107 , MIPS_REG_W11 = 108 , MIPS_REG_W12 = 109 , MIPS_REG_W13 = 110 , MIPS_REG_W14 = 111 , MIPS_REG_W15 = 112 , MIPS_REG_W16 = 113 , MIPS_REG_W17 = 114 , MIPS_REG_W18 = 115 , MIPS_REG_W19 = 116 , MIPS_REG_W20 = 117 , MIPS_REG_W21 = 118 , MIPS_REG_W22 = 119 , MIPS_REG_W23 = 120 , MIPS_REG_W24 = 121 , MIPS_REG_W25 = 122 , MIPS_REG_W26 = 123 , MIPS_REG_W27 = 124 , MIPS_REG_W28 = 125 , MIPS_REG_W29 = 126 , MIPS_REG_W30 = 127 , MIPS_REG_W31 = 128 , MIPS_REG_HI = 129 , MIPS_REG_LO = 130 , MIPS_REG_P0 = 131 , MIPS_REG_P1 = 132 , MIPS_REG_P2 = 133 , MIPS_REG_MPL0 = 134 , MIPS_REG_MPL1 = 135 , MIPS_REG_MPL2 = 136 , MIPS_REG_ENDING = 137 , } # [doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct mips_op_mem { # [doc = "< base register"] pub base : mips_reg , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of mips_op_mem"] [:: std :: mem :: size_of :: < mips_op_mem > () - 16usize] ; ["Alignment of mips_op_mem"] [:: std :: mem :: align_of :: < mips_op_mem > () - 8usize] ; ["Offset of field: mips_op_mem::base"] [:: std :: mem :: offset_of ! (mips_op_mem , base) - 0usize] ; ["Offset of field: mips_op_mem::disp"] [:: std :: mem :: offset_of ! (mips_op_mem , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips_op { # [doc = "< operand type"] pub type_ : mips_op_type , pub __bindgen_anon_1 : cs_mips_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mips_op__bindgen_ty_1 { # [doc = "< register id for REG operand"] pub reg : mips_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : mips_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mips_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mips_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op"] [:: std :: mem :: size_of :: < cs_mips_op > () - 24usize] ; ["Alignment of cs_mips_op"] [:: std :: mem :: align_of :: < cs_mips_op > () - 8usize] ; ["Offset of field: cs_mips_op::type_"] [:: std :: mem :: offset_of ! (cs_mips_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mips_op ; 10usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips"] [:: std :: mem :: size_of :: < cs_mips > () - 248usize] ; ["Alignment of cs_mips"] [:: std :: mem :: align_of :: < cs_mips > () - 8usize] ; ["Offset of field: cs_mips::op_count"] [:: std :: mem :: offset_of ! (cs_mips , op_count) - 0usize] ; ["Offset of field: cs_mips::operands"] [:: std :: mem :: offset_of ! (cs_mips , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mips { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " MIPS instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn { MIPS_INS_INVALID = 0 , MIPS_INS_ABSQ_S = 1 , MIPS_INS_ADD = 2 , MIPS_INS_ADDIUPC = 3 , MIPS_INS_ADDIUR1SP = 4 , MIPS_INS_ADDIUR2 = 5 , MIPS_INS_ADDIUS5 = 6 , MIPS_INS_ADDIUSP = 7 , MIPS_INS_ADDQH = 8 , MIPS_INS_ADDQH_R = 9 , MIPS_INS_ADDQ = 10 , MIPS_INS_ADDQ_S = 11 , MIPS_INS_ADDSC = 12 , MIPS_INS_ADDS_A = 13 , MIPS_INS_ADDS_S = 14 , MIPS_INS_ADDS_U = 15 , MIPS_INS_ADDU16 = 16 , MIPS_INS_ADDUH = 17 , MIPS_INS_ADDUH_R = 18 , MIPS_INS_ADDU = 19 , MIPS_INS_ADDU_S = 20 , MIPS_INS_ADDVI = 21 , MIPS_INS_ADDV = 22 , MIPS_INS_ADDWC = 23 , MIPS_INS_ADD_A = 24 , MIPS_INS_ADDI = 25 , MIPS_INS_ADDIU = 26 , MIPS_INS_ALIGN = 27 , MIPS_INS_ALUIPC = 28 , MIPS_INS_AND = 29 , MIPS_INS_AND16 = 30 , MIPS_INS_ANDI16 = 31 , MIPS_INS_ANDI = 32 , MIPS_INS_APPEND = 33 , MIPS_INS_ASUB_S = 34 , MIPS_INS_ASUB_U = 35 , MIPS_INS_AUI = 36 , MIPS_INS_AUIPC = 37 , MIPS_INS_AVER_S = 38 , MIPS_INS_AVER_U = 39 , MIPS_INS_AVE_S = 40 , MIPS_INS_AVE_U = 41 , MIPS_INS_B16 = 42 , MIPS_INS_BADDU = 43 , MIPS_INS_BAL = 44 , MIPS_INS_BALC = 45 , MIPS_INS_BALIGN = 46 , MIPS_INS_BBIT0 = 47 , MIPS_INS_BBIT032 = 48 , MIPS_INS_BBIT1 = 49 , MIPS_INS_BBIT132 = 50 , MIPS_INS_BC = 51 , MIPS_INS_BC0F = 52 , MIPS_INS_BC0FL = 53 , MIPS_INS_BC0T = 54 , MIPS_INS_BC0TL = 55 , MIPS_INS_BC1EQZ = 56 , MIPS_INS_BC1F = 57 , MIPS_INS_BC1FL = 58 , MIPS_INS_BC1NEZ = 59 , MIPS_INS_BC1T = 60 , MIPS_INS_BC1TL = 61 , MIPS_INS_BC2EQZ = 62 , MIPS_INS_BC2F = 63 , MIPS_INS_BC2FL = 64 , MIPS_INS_BC2NEZ = 65 , MIPS_INS_BC2T = 66 , MIPS_INS_BC2TL = 67 , MIPS_INS_BC3F = 68 , MIPS_INS_BC3FL = 69 , MIPS_INS_BC3T = 70 , MIPS_INS_BC3TL = 71 , MIPS_INS_BCLRI = 72 , MIPS_INS_BCLR = 73 , MIPS_INS_BEQ = 74 , MIPS_INS_BEQC = 75 , MIPS_INS_BEQL = 76 , MIPS_INS_BEQZ16 = 77 , MIPS_INS_BEQZALC = 78 , MIPS_INS_BEQZC = 79 , MIPS_INS_BGEC = 80 , MIPS_INS_BGEUC = 81 , MIPS_INS_BGEZ = 82 , MIPS_INS_BGEZAL = 83 , MIPS_INS_BGEZALC = 84 , MIPS_INS_BGEZALL = 85 , MIPS_INS_BGEZALS = 86 , MIPS_INS_BGEZC = 87 , MIPS_INS_BGEZL = 88 , MIPS_INS_BGTZ = 89 , MIPS_INS_BGTZALC = 90 , MIPS_INS_BGTZC = 91 , MIPS_INS_BGTZL = 92 , MIPS_INS_BINSLI = 93 , MIPS_INS_BINSL = 94 , MIPS_INS_BINSRI = 95 , MIPS_INS_BINSR = 96 , MIPS_INS_BITREV = 97 , MIPS_INS_BITSWAP = 98 , MIPS_INS_BLEZ = 99 , MIPS_INS_BLEZALC = 100 , MIPS_INS_BLEZC = 101 , MIPS_INS_BLEZL = 102 , MIPS_INS_BLTC = 103 , MIPS_INS_BLTUC = 104 , MIPS_INS_BLTZ = 105 , MIPS_INS_BLTZAL = 106 , MIPS_INS_BLTZALC = 107 , MIPS_INS_BLTZALL = 108 , MIPS_INS_BLTZALS = 109 , MIPS_INS_BLTZC = 110 , MIPS_INS_BLTZL = 111 , MIPS_INS_BMNZI = 112 , MIPS_INS_BMNZ = 113 , MIPS_INS_BMZI = 114 , MIPS_INS_BMZ = 115 , MIPS_INS_BNE = 116 , MIPS_INS_BNEC = 117 , MIPS_INS_BNEGI = 118 , MIPS_INS_BNEG = 119 , MIPS_INS_BNEL = 120 , MIPS_INS_BNEZ16 = 121 , MIPS_INS_BNEZALC = 122 , MIPS_INS_BNEZC = 123 , MIPS_INS_BNVC = 124 , MIPS_INS_BNZ = 125 , MIPS_INS_BOVC = 126 , MIPS_INS_BPOSGE32 = 127 , MIPS_INS_BREAK = 128 , MIPS_INS_BREAK16 = 129 , MIPS_INS_BSELI = 130 , MIPS_INS_BSEL = 131 , MIPS_INS_BSETI = 132 , MIPS_INS_BSET = 133 , MIPS_INS_BZ = 134 , MIPS_INS_BEQZ = 135 , MIPS_INS_B = 136 , MIPS_INS_BNEZ = 137 , MIPS_INS_BTEQZ = 138 , MIPS_INS_BTNEZ = 139 , MIPS_INS_CACHE = 140 , MIPS_INS_CEIL = 141 , MIPS_INS_CEQI = 142 , MIPS_INS_CEQ = 143 , MIPS_INS_CFC1 = 144 , MIPS_INS_CFCMSA = 145 , MIPS_INS_CINS = 146 , MIPS_INS_CINS32 = 147 , MIPS_INS_CLASS = 148 , MIPS_INS_CLEI_S = 149 , MIPS_INS_CLEI_U = 150 , MIPS_INS_CLE_S = 151 , MIPS_INS_CLE_U = 152 , MIPS_INS_CLO = 153 , MIPS_INS_CLTI_S = 154 , MIPS_INS_CLTI_U = 155 , MIPS_INS_CLT_S = 156 , MIPS_INS_CLT_U = 157 , MIPS_INS_CLZ = 158 , MIPS_INS_CMPGDU = 159 , MIPS_INS_CMPGU = 160 , MIPS_INS_CMPU = 161 , MIPS_INS_CMP = 162 , MIPS_INS_COPY_S = 163 , MIPS_INS_COPY_U = 164 , MIPS_INS_CTC1 = 165 , MIPS_INS_CTCMSA = 166 , MIPS_INS_CVT = 167 , MIPS_INS_C = 168 , MIPS_INS_CMPI = 169 , MIPS_INS_DADD = 170 , MIPS_INS_DADDI = 171 , MIPS_INS_DADDIU = 172 , MIPS_INS_DADDU = 173 , MIPS_INS_DAHI = 174 , MIPS_INS_DALIGN = 175 , MIPS_INS_DATI = 176 , MIPS_INS_DAUI = 177 , MIPS_INS_DBITSWAP = 178 , MIPS_INS_DCLO = 179 , MIPS_INS_DCLZ = 180 , MIPS_INS_DDIV = 181 , MIPS_INS_DDIVU = 182 , MIPS_INS_DERET = 183 , MIPS_INS_DEXT = 184 , MIPS_INS_DEXTM = 185 , MIPS_INS_DEXTU = 186 , MIPS_INS_DI = 187 , MIPS_INS_DINS = 188 , MIPS_INS_DINSM = 189 , MIPS_INS_DINSU = 190 , MIPS_INS_DIV = 191 , MIPS_INS_DIVU = 192 , MIPS_INS_DIV_S = 193 , MIPS_INS_DIV_U = 194 , MIPS_INS_DLSA = 195 , MIPS_INS_DMFC0 = 196 , MIPS_INS_DMFC1 = 197 , MIPS_INS_DMFC2 = 198 , MIPS_INS_DMOD = 199 , MIPS_INS_DMODU = 200 , MIPS_INS_DMTC0 = 201 , MIPS_INS_DMTC1 = 202 , MIPS_INS_DMTC2 = 203 , MIPS_INS_DMUH = 204 , MIPS_INS_DMUHU = 205 , MIPS_INS_DMUL = 206 , MIPS_INS_DMULT = 207 , MIPS_INS_DMULTU = 208 , MIPS_INS_DMULU = 209 , MIPS_INS_DOTP_S = 210 , MIPS_INS_DOTP_U = 211 , MIPS_INS_DPADD_S = 212 , MIPS_INS_DPADD_U = 213 , MIPS_INS_DPAQX_SA = 214 , MIPS_INS_DPAQX_S = 215 , MIPS_INS_DPAQ_SA = 216 , MIPS_INS_DPAQ_S = 217 , MIPS_INS_DPAU = 218 , MIPS_INS_DPAX = 219 , MIPS_INS_DPA = 220 , MIPS_INS_DPOP = 221 , MIPS_INS_DPSQX_SA = 222 , MIPS_INS_DPSQX_S = 223 , MIPS_INS_DPSQ_SA = 224 , MIPS_INS_DPSQ_S = 225 , MIPS_INS_DPSUB_S = 226 , MIPS_INS_DPSUB_U = 227 , MIPS_INS_DPSU = 228 , MIPS_INS_DPSX = 229 , MIPS_INS_DPS = 230 , MIPS_INS_DROTR = 231 , MIPS_INS_DROTR32 = 232 , MIPS_INS_DROTRV = 233 , MIPS_INS_DSBH = 234 , MIPS_INS_DSHD = 235 , MIPS_INS_DSLL = 236 , MIPS_INS_DSLL32 = 237 , MIPS_INS_DSLLV = 238 , MIPS_INS_DSRA = 239 , MIPS_INS_DSRA32 = 240 , MIPS_INS_DSRAV = 241 , MIPS_INS_DSRL = 242 , MIPS_INS_DSRL32 = 243 , MIPS_INS_DSRLV = 244 , MIPS_INS_DSUB = 245 , MIPS_INS_DSUBU = 246 , MIPS_INS_EHB = 247 , MIPS_INS_EI = 248 , MIPS_INS_ERET = 249 , MIPS_INS_EXT = 250 , MIPS_INS_EXTP = 251 , MIPS_INS_EXTPDP = 252 , MIPS_INS_EXTPDPV = 253 , MIPS_INS_EXTPV = 254 , MIPS_INS_EXTRV_RS = 255 , MIPS_INS_EXTRV_R = 256 , MIPS_INS_EXTRV_S = 257 , MIPS_INS_EXTRV = 258 , MIPS_INS_EXTR_RS = 259 , MIPS_INS_EXTR_R = 260 , MIPS_INS_EXTR_S = 261 , MIPS_INS_EXTR = 262 , MIPS_INS_EXTS = 263 , MIPS_INS_EXTS32 = 264 , MIPS_INS_ABS = 265 , MIPS_INS_FADD = 266 , MIPS_INS_FCAF = 267 , MIPS_INS_FCEQ = 268 , MIPS_INS_FCLASS = 269 , MIPS_INS_FCLE = 270 , MIPS_INS_FCLT = 271 , MIPS_INS_FCNE = 272 , MIPS_INS_FCOR = 273 , MIPS_INS_FCUEQ = 274 , MIPS_INS_FCULE = 275 , MIPS_INS_FCULT = 276 , MIPS_INS_FCUNE = 277 , MIPS_INS_FCUN = 278 , MIPS_INS_FDIV = 279 , MIPS_INS_FEXDO = 280 , MIPS_INS_FEXP2 = 281 , MIPS_INS_FEXUPL = 282 , MIPS_INS_FEXUPR = 283 , MIPS_INS_FFINT_S = 284 , MIPS_INS_FFINT_U = 285 , MIPS_INS_FFQL = 286 , MIPS_INS_FFQR = 287 , MIPS_INS_FILL = 288 , MIPS_INS_FLOG2 = 289 , MIPS_INS_FLOOR = 290 , MIPS_INS_FMADD = 291 , MIPS_INS_FMAX_A = 292 , MIPS_INS_FMAX = 293 , MIPS_INS_FMIN_A = 294 , MIPS_INS_FMIN = 295 , MIPS_INS_MOV = 296 , MIPS_INS_FMSUB = 297 , MIPS_INS_FMUL = 298 , MIPS_INS_MUL = 299 , MIPS_INS_NEG = 300 , MIPS_INS_FRCP = 301 , MIPS_INS_FRINT = 302 , MIPS_INS_FRSQRT = 303 , MIPS_INS_FSAF = 304 , MIPS_INS_FSEQ = 305 , MIPS_INS_FSLE = 306 , MIPS_INS_FSLT = 307 , MIPS_INS_FSNE = 308 , MIPS_INS_FSOR = 309 , MIPS_INS_FSQRT = 310 , MIPS_INS_SQRT = 311 , MIPS_INS_FSUB = 312 , MIPS_INS_SUB = 313 , MIPS_INS_FSUEQ = 314 , MIPS_INS_FSULE = 315 , MIPS_INS_FSULT = 316 , MIPS_INS_FSUNE = 317 , MIPS_INS_FSUN = 318 , MIPS_INS_FTINT_S = 319 , MIPS_INS_FTINT_U = 320 , MIPS_INS_FTQ = 321 , MIPS_INS_FTRUNC_S = 322 , MIPS_INS_FTRUNC_U = 323 , MIPS_INS_HADD_S = 324 , MIPS_INS_HADD_U = 325 , MIPS_INS_HSUB_S = 326 , MIPS_INS_HSUB_U = 327 , MIPS_INS_ILVEV = 328 , MIPS_INS_ILVL = 329 , MIPS_INS_ILVOD = 330 , MIPS_INS_ILVR = 331 , MIPS_INS_INS = 332 , MIPS_INS_INSERT = 333 , MIPS_INS_INSV = 334 , MIPS_INS_INSVE = 335 , MIPS_INS_J = 336 , MIPS_INS_JAL = 337 , MIPS_INS_JALR = 338 , MIPS_INS_JALRS16 = 339 , MIPS_INS_JALRS = 340 , MIPS_INS_JALS = 341 , MIPS_INS_JALX = 342 , MIPS_INS_JIALC = 343 , MIPS_INS_JIC = 344 , MIPS_INS_JR = 345 , MIPS_INS_JR16 = 346 , MIPS_INS_JRADDIUSP = 347 , MIPS_INS_JRC = 348 , MIPS_INS_JALRC = 349 , MIPS_INS_LB = 350 , MIPS_INS_LBU16 = 351 , MIPS_INS_LBUX = 352 , MIPS_INS_LBU = 353 , MIPS_INS_LD = 354 , MIPS_INS_LDC1 = 355 , MIPS_INS_LDC2 = 356 , MIPS_INS_LDC3 = 357 , MIPS_INS_LDI = 358 , MIPS_INS_LDL = 359 , MIPS_INS_LDPC = 360 , MIPS_INS_LDR = 361 , MIPS_INS_LDXC1 = 362 , MIPS_INS_LH = 363 , MIPS_INS_LHU16 = 364 , MIPS_INS_LHX = 365 , MIPS_INS_LHU = 366 , MIPS_INS_LI16 = 367 , MIPS_INS_LL = 368 , MIPS_INS_LLD = 369 , MIPS_INS_LSA = 370 , MIPS_INS_LUXC1 = 371 , MIPS_INS_LUI = 372 , MIPS_INS_LW = 373 , MIPS_INS_LW16 = 374 , MIPS_INS_LWC1 = 375 , MIPS_INS_LWC2 = 376 , MIPS_INS_LWC3 = 377 , MIPS_INS_LWL = 378 , MIPS_INS_LWM16 = 379 , MIPS_INS_LWM32 = 380 , MIPS_INS_LWPC = 381 , MIPS_INS_LWP = 382 , MIPS_INS_LWR = 383 , MIPS_INS_LWUPC = 384 , MIPS_INS_LWU = 385 , MIPS_INS_LWX = 386 , MIPS_INS_LWXC1 = 387 , MIPS_INS_LWXS = 388 , MIPS_INS_LI = 389 , MIPS_INS_MADD = 390 , MIPS_INS_MADDF = 391 , MIPS_INS_MADDR_Q = 392 , MIPS_INS_MADDU = 393 , MIPS_INS_MADDV = 394 , MIPS_INS_MADD_Q = 395 , MIPS_INS_MAQ_SA = 396 , MIPS_INS_MAQ_S = 397 , MIPS_INS_MAXA = 398 , MIPS_INS_MAXI_S = 399 , MIPS_INS_MAXI_U = 400 , MIPS_INS_MAX_A = 401 , MIPS_INS_MAX = 402 , MIPS_INS_MAX_S = 403 , MIPS_INS_MAX_U = 404 , MIPS_INS_MFC0 = 405 , MIPS_INS_MFC1 = 406 , MIPS_INS_MFC2 = 407 , MIPS_INS_MFHC1 = 408 , MIPS_INS_MFHI = 409 , MIPS_INS_MFLO = 410 , MIPS_INS_MINA = 411 , MIPS_INS_MINI_S = 412 , MIPS_INS_MINI_U = 413 , MIPS_INS_MIN_A = 414 , MIPS_INS_MIN = 415 , MIPS_INS_MIN_S = 416 , MIPS_INS_MIN_U = 417 , MIPS_INS_MOD = 418 , MIPS_INS_MODSUB = 419 , MIPS_INS_MODU = 420 , MIPS_INS_MOD_S = 421 , MIPS_INS_MOD_U = 422 , MIPS_INS_MOVE = 423 , MIPS_INS_MOVEP = 424 , MIPS_INS_MOVF = 425 , MIPS_INS_MOVN = 426 , MIPS_INS_MOVT = 427 , MIPS_INS_MOVZ = 428 , MIPS_INS_MSUB = 429 , MIPS_INS_MSUBF = 430 , MIPS_INS_MSUBR_Q = 431 , MIPS_INS_MSUBU = 432 , MIPS_INS_MSUBV = 433 , MIPS_INS_MSUB_Q = 434 , MIPS_INS_MTC0 = 435 , MIPS_INS_MTC1 = 436 , MIPS_INS_MTC2 = 437 , MIPS_INS_MTHC1 = 438 , MIPS_INS_MTHI = 439 , MIPS_INS_MTHLIP = 440 , MIPS_INS_MTLO = 441 , MIPS_INS_MTM0 = 442 , MIPS_INS_MTM1 = 443 , MIPS_INS_MTM2 = 444 , MIPS_INS_MTP0 = 445 , MIPS_INS_MTP1 = 446 , MIPS_INS_MTP2 = 447 , MIPS_INS_MUH = 448 , MIPS_INS_MUHU = 449 , MIPS_INS_MULEQ_S = 450 , MIPS_INS_MULEU_S = 451 , MIPS_INS_MULQ_RS = 452 , MIPS_INS_MULQ_S = 453 , MIPS_INS_MULR_Q = 454 , MIPS_INS_MULSAQ_S = 455 , MIPS_INS_MULSA = 456 , MIPS_INS_MULT = 457 , MIPS_INS_MULTU = 458 , MIPS_INS_MULU = 459 , MIPS_INS_MULV = 460 , MIPS_INS_MUL_Q = 461 , MIPS_INS_MUL_S = 462 , MIPS_INS_NLOC = 463 , MIPS_INS_NLZC = 464 , MIPS_INS_NMADD = 465 , MIPS_INS_NMSUB = 466 , MIPS_INS_NOR = 467 , MIPS_INS_NORI = 468 , MIPS_INS_NOT16 = 469 , MIPS_INS_NOT = 470 , MIPS_INS_OR = 471 , MIPS_INS_OR16 = 472 , MIPS_INS_ORI = 473 , MIPS_INS_PACKRL = 474 , MIPS_INS_PAUSE = 475 , MIPS_INS_PCKEV = 476 , MIPS_INS_PCKOD = 477 , MIPS_INS_PCNT = 478 , MIPS_INS_PICK = 479 , MIPS_INS_POP = 480 , MIPS_INS_PRECEQU = 481 , MIPS_INS_PRECEQ = 482 , MIPS_INS_PRECEU = 483 , MIPS_INS_PRECRQU_S = 484 , MIPS_INS_PRECRQ = 485 , MIPS_INS_PRECRQ_RS = 486 , MIPS_INS_PRECR = 487 , MIPS_INS_PRECR_SRA = 488 , MIPS_INS_PRECR_SRA_R = 489 , MIPS_INS_PREF = 490 , MIPS_INS_PREPEND = 491 , MIPS_INS_RADDU = 492 , MIPS_INS_RDDSP = 493 , MIPS_INS_RDHWR = 494 , MIPS_INS_REPLV = 495 , MIPS_INS_REPL = 496 , MIPS_INS_RINT = 497 , MIPS_INS_ROTR = 498 , MIPS_INS_ROTRV = 499 , MIPS_INS_ROUND = 500 , MIPS_INS_SAT_S = 501 , MIPS_INS_SAT_U = 502 , MIPS_INS_SB = 503 , MIPS_INS_SB16 = 504 , MIPS_INS_SC = 505 , MIPS_INS_SCD = 506 , MIPS_INS_SD = 507 , MIPS_INS_SDBBP = 508 , MIPS_INS_SDBBP16 = 509 , MIPS_INS_SDC1 = 510 , MIPS_INS_SDC2 = 511 , MIPS_INS_SDC3 = 512 , MIPS_INS_SDL = 513 , MIPS_INS_SDR = 514 , MIPS_INS_SDXC1 = 515 , MIPS_INS_SEB = 516 , MIPS_INS_SEH = 517 , MIPS_INS_SELEQZ = 518 , MIPS_INS_SELNEZ = 519 , MIPS_INS_SEL = 520 , MIPS_INS_SEQ = 521 , MIPS_INS_SEQI = 522 , MIPS_INS_SH = 523 , MIPS_INS_SH16 = 524 , MIPS_INS_SHF = 525 , MIPS_INS_SHILO = 526 , MIPS_INS_SHILOV = 527 , MIPS_INS_SHLLV = 528 , MIPS_INS_SHLLV_S = 529 , MIPS_INS_SHLL = 530 , MIPS_INS_SHLL_S = 531 , MIPS_INS_SHRAV = 532 , MIPS_INS_SHRAV_R = 533 , MIPS_INS_SHRA = 534 , MIPS_INS_SHRA_R = 535 , MIPS_INS_SHRLV = 536 , MIPS_INS_SHRL = 537 , MIPS_INS_SLDI = 538 , MIPS_INS_SLD = 539 , MIPS_INS_SLL = 540 , MIPS_INS_SLL16 = 541 , MIPS_INS_SLLI = 542 , MIPS_INS_SLLV = 543 , MIPS_INS_SLT = 544 , MIPS_INS_SLTI = 545 , MIPS_INS_SLTIU = 546 , MIPS_INS_SLTU = 547 , MIPS_INS_SNE = 548 , MIPS_INS_SNEI = 549 , MIPS_INS_SPLATI = 550 , MIPS_INS_SPLAT = 551 , MIPS_INS_SRA = 552 , MIPS_INS_SRAI = 553 , MIPS_INS_SRARI = 554 , MIPS_INS_SRAR = 555 , MIPS_INS_SRAV = 556 , MIPS_INS_SRL = 557 , MIPS_INS_SRL16 = 558 , MIPS_INS_SRLI = 559 , MIPS_INS_SRLRI = 560 , MIPS_INS_SRLR = 561 , MIPS_INS_SRLV = 562 , MIPS_INS_SSNOP = 563 , MIPS_INS_ST = 564 , MIPS_INS_SUBQH = 565 , MIPS_INS_SUBQH_R = 566 , MIPS_INS_SUBQ = 567 , MIPS_INS_SUBQ_S = 568 , MIPS_INS_SUBSUS_U = 569 , MIPS_INS_SUBSUU_S = 570 , MIPS_INS_SUBS_S = 571 , MIPS_INS_SUBS_U = 572 , MIPS_INS_SUBU16 = 573 , MIPS_INS_SUBUH = 574 , MIPS_INS_SUBUH_R = 575 , MIPS_INS_SUBU = 576 , MIPS_INS_SUBU_S = 577 , MIPS_INS_SUBVI = 578 , MIPS_INS_SUBV = 579 , MIPS_INS_SUXC1 = 580 , MIPS_INS_SW = 581 , MIPS_INS_SW16 = 582 , MIPS_INS_SWC1 = 583 , MIPS_INS_SWC2 = 584 , MIPS_INS_SWC3 = 585 , MIPS_INS_SWL = 586 , MIPS_INS_SWM16 = 587 , MIPS_INS_SWM32 = 588 , MIPS_INS_SWP = 589 , MIPS_INS_SWR = 590 , MIPS_INS_SWXC1 = 591 , MIPS_INS_SYNC = 592 , MIPS_INS_SYNCI = 593 , MIPS_INS_SYSCALL = 594 , MIPS_INS_TEQ = 595 , MIPS_INS_TEQI = 596 , MIPS_INS_TGE = 597 , MIPS_INS_TGEI = 598 , MIPS_INS_TGEIU = 599 , MIPS_INS_TGEU = 600 , MIPS_INS_TLBP = 601 , MIPS_INS_TLBR = 602 , MIPS_INS_TLBWI = 603 , MIPS_INS_TLBWR = 604 , MIPS_INS_TLT = 605 , MIPS_INS_TLTI = 606 , MIPS_INS_TLTIU = 607 , MIPS_INS_TLTU = 608 , MIPS_INS_TNE = 609 , MIPS_INS_TNEI = 610 , MIPS_INS_TRUNC = 611 , MIPS_INS_V3MULU = 612 , MIPS_INS_VMM0 = 613 , MIPS_INS_VMULU = 614 , MIPS_INS_VSHF = 615 , MIPS_INS_WAIT = 616 , MIPS_INS_WRDSP = 617 , MIPS_INS_WSBH = 618 , MIPS_INS_XOR = 619 , MIPS_INS_XOR16 = 620 , MIPS_INS_XORI = 621 , MIPS_INS_NOP = 622 , MIPS_INS_NEGU = 623 , MIPS_INS_JALR_HB = 624 , MIPS_INS_JR_HB = 625 , MIPS_INS_ENDING = 626 , } # [repr (u32)] # [doc = " Group of MIPS instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn_group { # [doc = "< = CS_GRP_INVALID"] MIPS_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MIPS_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] MIPS_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MIPS_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MIPS_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MIPS_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] MIPS_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MIPS_GRP_BRANCH_RELATIVE = 7 , MIPS_GRP_BITCOUNT = 128 , MIPS_GRP_DSP = 129 , MIPS_GRP_DSPR2 = 130 , MIPS_GRP_FPIDX = 131 , MIPS_GRP_MSA = 132 , MIPS_GRP_MIPS32R2 = 133 , MIPS_GRP_MIPS64 = 134 , MIPS_GRP_MIPS64R2 = 135 , MIPS_GRP_SEINREG = 136 , MIPS_GRP_STDENC = 137 , MIPS_GRP_SWAP = 138 , MIPS_GRP_MICROMIPS = 139 , MIPS_GRP_MIPS16MODE = 140 , MIPS_GRP_FP64BIT = 141 , MIPS_GRP_NONANSFPMATH = 142 , MIPS_GRP_NOTFP64BIT = 143 , MIPS_GRP_NOTINMICROMIPS = 144 , MIPS_GRP_NOTNACL = 145 , MIPS_GRP_NOTMIPS32R6 = 146 , MIPS_GRP_NOTMIPS64R6 = 147 , MIPS_GRP_CNMIPS = 148 , MIPS_GRP_MIPS32 = 149 , MIPS_GRP_MIPS32R6 = 150 , MIPS_GRP_MIPS64R6 = 151 , MIPS_GRP_MIPS2 = 152 , MIPS_GRP_MIPS3 = 153 , MIPS_GRP_MIPS3_32 = 154 , MIPS_GRP_MIPS3_32R2 = 155 , MIPS_GRP_MIPS4_32 = 156 , MIPS_GRP_MIPS4_32R2 = 157 , MIPS_GRP_MIPS5_32R2 = 158 , MIPS_GRP_GP32BIT = 159 , MIPS_GRP_GP64BIT = 160 , MIPS_GRP_ENDING = 161 , } # [repr (u32)] # [doc = " PPC branch codes for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bc { PPC_BC_INVALID = 0 , PPC_BC_LT = 12 , PPC_BC_LE = 36 , PPC_BC_EQ = 76 , PPC_BC_GE = 4 , PPC_BC_GT = 44 , PPC_BC_NE = 68 , PPC_BC_UN = 108 , PPC_BC_NU = 100 , # [doc = "< summary overflow"] PPC_BC_SO = 140 , # [doc = "< not summary overflow"] PPC_BC_NS = 132 , } # [repr (u32)] # [doc = " PPC branch hint for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bh { # [doc = "< no hint"] PPC_BH_INVALID = 0 , # [doc = "< PLUS hint"] PPC_BH_PLUS = 1 , # [doc = "< MINUS hint"] PPC_BH_MINUS = 2 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] PPC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] PPC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] PPC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] PPC_OP_MEM = 3 , # [doc = "< Condition Register field"] PPC_OP_CRX = 64 , } # [repr (u32)] # [doc = " PPC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_reg { PPC_REG_INVALID = 0 , PPC_REG_CARRY = 2 , PPC_REG_CTR = 3 , PPC_REG_LR = 5 , PPC_REG_RM = 6 , PPC_REG_VRSAVE = 8 , PPC_REG_XER = 9 , PPC_REG_ZERO = 10 , PPC_REG_CR0 = 12 , PPC_REG_CR1 = 13 , PPC_REG_CR2 = 14 , PPC_REG_CR3 = 15 , PPC_REG_CR4 = 16 , PPC_REG_CR5 = 17 , PPC_REG_CR6 = 18 , PPC_REG_CR7 = 19 , PPC_REG_CTR8 = 20 , PPC_REG_F0 = 21 , PPC_REG_F1 = 22 , PPC_REG_F2 = 23 , PPC_REG_F3 = 24 , PPC_REG_F4 = 25 , PPC_REG_F5 = 26 , PPC_REG_F6 = 27 , PPC_REG_F7 = 28 , PPC_REG_F8 = 29 , PPC_REG_F9 = 30 , PPC_REG_F10 = 31 , PPC_REG_F11 = 32 , PPC_REG_F12 = 33 , PPC_REG_F13 = 34 , PPC_REG_F14 = 35 , PPC_REG_F15 = 36 , PPC_REG_F16 = 37 , PPC_REG_F17 = 38 , PPC_REG_F18 = 39 , PPC_REG_F19 = 40 , PPC_REG_F20 = 41 , PPC_REG_F21 = 42 , PPC_REG_F22 = 43 , PPC_REG_F23 = 44 , PPC_REG_F24 = 45 , PPC_REG_F25 = 46 , PPC_REG_F26 = 47 , PPC_REG_F27 = 48 , PPC_REG_F28 = 49 , PPC_REG_F29 = 50 , PPC_REG_F30 = 51 , PPC_REG_F31 = 52 , PPC_REG_LR8 = 54 , PPC_REG_Q0 = 55 , PPC_REG_Q1 = 56 , PPC_REG_Q2 = 57 , PPC_REG_Q3 = 58 , PPC_REG_Q4 = 59 , PPC_REG_Q5 = 60 , PPC_REG_Q6 = 61 , PPC_REG_Q7 = 62 , PPC_REG_Q8 = 63 , PPC_REG_Q9 = 64 , PPC_REG_Q10 = 65 , PPC_REG_Q11 = 66 , PPC_REG_Q12 = 67 , PPC_REG_Q13 = 68 , PPC_REG_Q14 = 69 , PPC_REG_Q15 = 70 , PPC_REG_Q16 = 71 , PPC_REG_Q17 = 72 , PPC_REG_Q18 = 73 , PPC_REG_Q19 = 74 , PPC_REG_Q20 = 75 , PPC_REG_Q21 = 76 , PPC_REG_Q22 = 77 , PPC_REG_Q23 = 78 , PPC_REG_Q24 = 79 , PPC_REG_Q25 = 80 , PPC_REG_Q26 = 81 , PPC_REG_Q27 = 82 , PPC_REG_Q28 = 83 , PPC_REG_Q29 = 84 , PPC_REG_Q30 = 85 , PPC_REG_Q31 = 86 , PPC_REG_R0 = 87 , PPC_REG_R1 = 88 , PPC_REG_R2 = 89 , PPC_REG_R3 = 90 , PPC_REG_R4 = 91 , PPC_REG_R5 = 92 , PPC_REG_R6 = 93 , PPC_REG_R7 = 94 , PPC_REG_R8 = 95 , PPC_REG_R9 = 96 , PPC_REG_R10 = 97 , PPC_REG_R11 = 98 , PPC_REG_R12 = 99 , PPC_REG_R13 = 100 , PPC_REG_R14 = 101 , PPC_REG_R15 = 102 , PPC_REG_R16 = 103 , PPC_REG_R17 = 104 , PPC_REG_R18 = 105 , PPC_REG_R19 = 106 , PPC_REG_R20 = 107 , PPC_REG_R21 = 108 , PPC_REG_R22 = 109 , PPC_REG_R23 = 110 , PPC_REG_R24 = 111 , PPC_REG_R25 = 112 , PPC_REG_R26 = 113 , PPC_REG_R27 = 114 , PPC_REG_R28 = 115 , PPC_REG_R29 = 116 , PPC_REG_R30 = 117 , PPC_REG_R31 = 118 , PPC_REG_V0 = 151 , PPC_REG_V1 = 152 , PPC_REG_V2 = 153 , PPC_REG_V3 = 154 , PPC_REG_V4 = 155 , PPC_REG_V5 = 156 , PPC_REG_V6 = 157 , PPC_REG_V7 = 158 , PPC_REG_V8 = 159 , PPC_REG_V9 = 160 , PPC_REG_V10 = 161 , PPC_REG_V11 = 162 , PPC_REG_V12 = 163 , PPC_REG_V13 = 164 , PPC_REG_V14 = 165 , PPC_REG_V15 = 166 , PPC_REG_V16 = 167 , PPC_REG_V17 = 168 , PPC_REG_V18 = 169 , PPC_REG_V19 = 170 , PPC_REG_V20 = 171 , PPC_REG_V21 = 172 , PPC_REG_V22 = 173 , PPC_REG_V23 = 174 , PPC_REG_V24 = 175 , PPC_REG_V25 = 176 , PPC_REG_V26 = 177 , PPC_REG_V27 = 178 , PPC_REG_V28 = 179 , PPC_REG_V29 = 180 , PPC_REG_V30 = 181 , PPC_REG_V31 = 182 , PPC_REG_VS0 = 215 , PPC_REG_VS1 = 216 , PPC_REG_VS2 = 217 , PPC_REG_VS3 = 218 , PPC_REG_VS4 = 219 , PPC_REG_VS5 = 220 , PPC_REG_VS6 = 221 , PPC_REG_VS7 = 222 , PPC_REG_VS8 = 223 , PPC_REG_VS9 = 224 , PPC_REG_VS10 = 225 , PPC_REG_VS11 = 226 , PPC_REG_VS12 = 227 , PPC_REG_VS13 = 228 , PPC_REG_VS14 = 229 , PPC_REG_VS15 = 230 , PPC_REG_VS16 = 231 , PPC_REG_VS17 = 232 , PPC_REG_VS18 = 233 , PPC_REG_VS19 = 234 , PPC_REG_VS20 = 235 , PPC_REG_VS21 = 236 , PPC_REG_VS22 = 237 , PPC_REG_VS23 = 238 , PPC_REG_VS24 = 239 , PPC_REG_VS25 = 240 , PPC_REG_VS26 = 241 , PPC_REG_VS27 = 242 , PPC_REG_VS28 = 243 , PPC_REG_VS29 = 244 , PPC_REG_VS30 = 245 , PPC_REG_VS31 = 246 , PPC_REG_VS32 = 247 , PPC_REG_VS33 = 248 , PPC_REG_VS34 = 249 , PPC_REG_VS35 = 250 , PPC_REG_VS36 = 251 , PPC_REG_VS37 = 252 , PPC_REG_VS38 = 253 , PPC_REG_VS39 = 254 , PPC_REG_VS40 = 255 , PPC_REG_VS41 = 256 , PPC_REG_VS42 = 257 , PPC_REG_VS43 = 258 , PPC_REG_VS44 = 259 , PPC_REG_VS45 = 260 , PPC_REG_VS46 = 261 , PPC_REG_VS47 = 262 , PPC_REG_VS48 = 263 , PPC_REG_VS49 = 264 , PPC_REG_VS50 = 265 , PPC_REG_VS51 = 266 , PPC_REG_VS52 = 267 , PPC_REG_VS53 = 268 , PPC_REG_VS54 = 269 , PPC_REG_VS55 = 270 , PPC_REG_VS56 = 271 , PPC_REG_VS57 = 272 , PPC_REG_VS58 = 273 , PPC_REG_VS59 = 274 , PPC_REG_VS60 = 275 , PPC_REG_VS61 = 276 , PPC_REG_VS62 = 277 , PPC_REG_VS63 = 278 , PPC_REG_CR0EQ = 312 , PPC_REG_CR1EQ = 313 , PPC_REG_CR2EQ = 314 , PPC_REG_CR3EQ = 315 , PPC_REG_CR4EQ = 316 , PPC_REG_CR5EQ = 317 , PPC_REG_CR6EQ = 318 , PPC_REG_CR7EQ = 319 , PPC_REG_CR0GT = 320 , PPC_REG_CR1GT = 321 , PPC_REG_CR2GT = 322 , PPC_REG_CR3GT = 323 , PPC_REG_CR4GT = 324 , PPC_REG_CR5GT = 325 , PPC_REG_CR6GT = 326 , PPC_REG_CR7GT = 327 , PPC_REG_CR0LT = 328 , PPC_REG_CR1LT = 329 , PPC_REG_CR2LT = 330 , PPC_REG_CR3LT = 331 , PPC_REG_CR4LT = 332 , PPC_REG_CR5LT = 333 , PPC_REG_CR6LT = 334 , PPC_REG_CR7LT = 335 , PPC_REG_CR0UN = 336 , PPC_REG_CR1UN = 337 , PPC_REG_CR2UN = 338 , PPC_REG_CR3UN = 339 , PPC_REG_CR4UN = 340 , PPC_REG_CR5UN = 341 , PPC_REG_CR6UN = 342 , PPC_REG_CR7UN = 343 , PPC_REG_ENDING = 344 , } # [doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_mem { # [doc = "< base register"] pub base : ppc_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_mem"] [:: std :: mem :: size_of :: < ppc_op_mem > () - 8usize] ; ["Alignment of ppc_op_mem"] [:: std :: mem :: align_of :: < ppc_op_mem > () - 4usize] ; ["Offset of field: ppc_op_mem::base"] [:: std :: mem :: offset_of ! (ppc_op_mem , base) - 0usize] ; ["Offset of field: ppc_op_mem::disp"] [:: std :: mem :: offset_of ! (ppc_op_mem , disp) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_crx { pub scale : :: std :: os :: raw :: c_uint , pub reg : ppc_reg , pub cond : ppc_bc , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_crx"] [:: std :: mem :: size_of :: < ppc_op_crx > () - 12usize] ; ["Alignment of ppc_op_crx"] [:: std :: mem :: align_of :: < ppc_op_crx > () - 4usize] ; ["Offset of field: ppc_op_crx::scale"] [:: std :: mem :: offset_of ! (ppc_op_crx , scale) - 0usize] ; ["Offset of field: ppc_op_crx::reg"] [:: std :: mem :: offset_of ! (ppc_op_crx , reg) - 4usize] ; ["Offset of field: ppc_op_crx::cond"] [:: std :: mem :: offset_of ! (ppc_op_crx , cond) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc_op { # [doc = "< operand type"] pub type_ : ppc_op_type , pub __bindgen_anon_1 : cs_ppc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_ppc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : ppc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : ppc_op_mem , # [doc = "< operand with condition register"] pub crx : ppc_op_crx , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_ppc_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_ppc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::crx"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , crx) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op"] [:: std :: mem :: size_of :: < cs_ppc_op > () - 24usize] ; ["Alignment of cs_ppc_op"] [:: std :: mem :: align_of :: < cs_ppc_op > () - 8usize] ; ["Offset of field: cs_ppc_op::type_"] [:: std :: mem :: offset_of ! (cs_ppc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc { # [doc = " branch code for branch instructions"] pub bc : ppc_bc , # [doc = " branch hint for branch instructions"] pub bh : ppc_bh , # [doc = " if update_cr0 = True, then this 'dot' insn updates CR0"] pub update_cr0 : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_ppc_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc"] [:: std :: mem :: size_of :: < cs_ppc > () - 208usize] ; ["Alignment of cs_ppc"] [:: std :: mem :: align_of :: < cs_ppc > () - 8usize] ; ["Offset of field: cs_ppc::bc"] [:: std :: mem :: offset_of ! (cs_ppc , bc) - 0usize] ; ["Offset of field: cs_ppc::bh"] [:: std :: mem :: offset_of ! (cs_ppc , bh) - 4usize] ; ["Offset of field: cs_ppc::update_cr0"] [:: std :: mem :: offset_of ! (cs_ppc , update_cr0) - 8usize] ; ["Offset of field: cs_ppc::op_count"] [:: std :: mem :: offset_of ! (cs_ppc , op_count) - 9usize] ; ["Offset of field: cs_ppc::operands"] [:: std :: mem :: offset_of ! (cs_ppc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}" , self . bc , self . bh , self . update_cr0 , self . op_count , self . operands) } } # [repr (u32)] # [doc = " PPC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn { PPC_INS_INVALID = 0 , PPC_INS_ADD = 1 , PPC_INS_ADDC = 2 , PPC_INS_ADDE = 3 , PPC_INS_ADDI = 4 , PPC_INS_ADDIC = 5 , PPC_INS_ADDIS = 6 , PPC_INS_ADDME = 7 , PPC_INS_ADDPCIS = 8 , PPC_INS_ADDZE = 9 , PPC_INS_AND = 10 , PPC_INS_ANDC = 11 , PPC_INS_ANDI = 12 , PPC_INS_ANDIS = 13 , PPC_INS_ATTN = 14 , PPC_INS_B = 15 , PPC_INS_BA = 16 , PPC_INS_BC = 17 , PPC_INS_BCA = 18 , PPC_INS_BCCTR = 19 , PPC_INS_BCCTRL = 20 , PPC_INS_BCDCFN = 21 , PPC_INS_BCDCFSQ = 22 , PPC_INS_BCDCFZ = 23 , PPC_INS_BCDCPSGN = 24 , PPC_INS_BCDCTN = 25 , PPC_INS_BCDCTSQ = 26 , PPC_INS_BCDCTZ = 27 , PPC_INS_BCDS = 28 , PPC_INS_BCDSETSGN = 29 , PPC_INS_BCDSR = 30 , PPC_INS_BCDTRUNC = 31 , PPC_INS_BCDUS = 32 , PPC_INS_BCDUTRUNC = 33 , PPC_INS_BCL = 34 , PPC_INS_BCLA = 35 , PPC_INS_BCLR = 36 , PPC_INS_BCLRL = 37 , PPC_INS_BCTR = 38 , PPC_INS_BCTRL = 39 , PPC_INS_BDNZ = 40 , PPC_INS_BDNZA = 41 , PPC_INS_BDNZF = 42 , PPC_INS_BDNZFA = 43 , PPC_INS_BDNZFL = 44 , PPC_INS_BDNZFLA = 45 , PPC_INS_BDNZFLR = 46 , PPC_INS_BDNZFLRL = 47 , PPC_INS_BDNZL = 48 , PPC_INS_BDNZLA = 49 , PPC_INS_BDNZLR = 50 , PPC_INS_BDNZLRL = 51 , PPC_INS_BDNZT = 52 , PPC_INS_BDNZTA = 53 , PPC_INS_BDNZTL = 54 , PPC_INS_BDNZTLA = 55 , PPC_INS_BDNZTLR = 56 , PPC_INS_BDNZTLRL = 57 , PPC_INS_BDZ = 58 , PPC_INS_BDZA = 59 , PPC_INS_BDZF = 60 , PPC_INS_BDZFA = 61 , PPC_INS_BDZFL = 62 , PPC_INS_BDZFLA = 63 , PPC_INS_BDZFLR = 64 , PPC_INS_BDZFLRL = 65 , PPC_INS_BDZL = 66 , PPC_INS_BDZLA = 67 , PPC_INS_BDZLR = 68 , PPC_INS_BDZLRL = 69 , PPC_INS_BDZT = 70 , PPC_INS_BDZTA = 71 , PPC_INS_BDZTL = 72 , PPC_INS_BDZTLA = 73 , PPC_INS_BDZTLR = 74 , PPC_INS_BDZTLRL = 75 , PPC_INS_BEQ = 76 , PPC_INS_BEQA = 77 , PPC_INS_BEQCTR = 78 , PPC_INS_BEQCTRL = 79 , PPC_INS_BEQL = 80 , PPC_INS_BEQLA = 81 , PPC_INS_BEQLR = 82 , PPC_INS_BEQLRL = 83 , PPC_INS_BF = 84 , PPC_INS_BFA = 85 , PPC_INS_BFCTR = 86 , PPC_INS_BFCTRL = 87 , PPC_INS_BFL = 88 , PPC_INS_BFLA = 89 , PPC_INS_BFLR = 90 , PPC_INS_BFLRL = 91 , PPC_INS_BGE = 92 , PPC_INS_BGEA = 93 , PPC_INS_BGECTR = 94 , PPC_INS_BGECTRL = 95 , PPC_INS_BGEL = 96 , PPC_INS_BGELA = 97 , PPC_INS_BGELR = 98 , PPC_INS_BGELRL = 99 , PPC_INS_BGT = 100 , PPC_INS_BGTA = 101 , PPC_INS_BGTCTR = 102 , PPC_INS_BGTCTRL = 103 , PPC_INS_BGTL = 104 , PPC_INS_BGTLA = 105 , PPC_INS_BGTLR = 106 , PPC_INS_BGTLRL = 107 , PPC_INS_BL = 108 , PPC_INS_BLA = 109 , PPC_INS_BLE = 110 , PPC_INS_BLEA = 111 , PPC_INS_BLECTR = 112 , PPC_INS_BLECTRL = 113 , PPC_INS_BLEL = 114 , PPC_INS_BLELA = 115 , PPC_INS_BLELR = 116 , PPC_INS_BLELRL = 117 , PPC_INS_BLR = 118 , PPC_INS_BLRL = 119 , PPC_INS_BLT = 120 , PPC_INS_BLTA = 121 , PPC_INS_BLTCTR = 122 , PPC_INS_BLTCTRL = 123 , PPC_INS_BLTL = 124 , PPC_INS_BLTLA = 125 , PPC_INS_BLTLR = 126 , PPC_INS_BLTLRL = 127 , PPC_INS_BNE = 128 , PPC_INS_BNEA = 129 , PPC_INS_BNECTR = 130 , PPC_INS_BNECTRL = 131 , PPC_INS_BNEL = 132 , PPC_INS_BNELA = 133 , PPC_INS_BNELR = 134 , PPC_INS_BNELRL = 135 , PPC_INS_BNG = 136 , PPC_INS_BNGA = 137 , PPC_INS_BNGCTR = 138 , PPC_INS_BNGCTRL = 139 , PPC_INS_BNGL = 140 , PPC_INS_BNGLA = 141 , PPC_INS_BNGLR = 142 , PPC_INS_BNGLRL = 143 , PPC_INS_BNL = 144 , PPC_INS_BNLA = 145 , PPC_INS_BNLCTR = 146 , PPC_INS_BNLCTRL = 147 , PPC_INS_BNLL = 148 , PPC_INS_BNLLA = 149 , PPC_INS_BNLLR = 150 , PPC_INS_BNLLRL = 151 , PPC_INS_BNS = 152 , PPC_INS_BNSA = 153 , PPC_INS_BNSCTR = 154 , PPC_INS_BNSCTRL = 155 , PPC_INS_BNSL = 156 , PPC_INS_BNSLA = 157 , PPC_INS_BNSLR = 158 , PPC_INS_BNSLRL = 159 , PPC_INS_BNU = 160 , PPC_INS_BNUA = 161 , PPC_INS_BNUCTR = 162 , PPC_INS_BNUCTRL = 163 , PPC_INS_BNUL = 164 , PPC_INS_BNULA = 165 , PPC_INS_BNULR = 166 , PPC_INS_BNULRL = 167 , PPC_INS_BPERMD = 168 , PPC_INS_BRINC = 169 , PPC_INS_BSO = 170 , PPC_INS_BSOA = 171 , PPC_INS_BSOCTR = 172 , PPC_INS_BSOCTRL = 173 , PPC_INS_BSOL = 174 , PPC_INS_BSOLA = 175 , PPC_INS_BSOLR = 176 , PPC_INS_BSOLRL = 177 , PPC_INS_BT = 178 , PPC_INS_BTA = 179 , PPC_INS_BTCTR = 180 , PPC_INS_BTCTRL = 181 , PPC_INS_BTL = 182 , PPC_INS_BTLA = 183 , PPC_INS_BTLR = 184 , PPC_INS_BTLRL = 185 , PPC_INS_BUN = 186 , PPC_INS_BUNA = 187 , PPC_INS_BUNCTR = 188 , PPC_INS_BUNCTRL = 189 , PPC_INS_BUNL = 190 , PPC_INS_BUNLA = 191 , PPC_INS_BUNLR = 192 , PPC_INS_BUNLRL = 193 , PPC_INS_CLRBHRB = 194 , PPC_INS_CLRLDI = 195 , PPC_INS_CLRLSLDI = 196 , PPC_INS_CLRLSLWI = 197 , PPC_INS_CLRLWI = 198 , PPC_INS_CLRRDI = 199 , PPC_INS_CLRRWI = 200 , PPC_INS_CMP = 201 , PPC_INS_CMPB = 202 , PPC_INS_CMPD = 203 , PPC_INS_CMPDI = 204 , PPC_INS_CMPEQB = 205 , PPC_INS_CMPI = 206 , PPC_INS_CMPL = 207 , PPC_INS_CMPLD = 208 , PPC_INS_CMPLDI = 209 , PPC_INS_CMPLI = 210 , PPC_INS_CMPLW = 211 , PPC_INS_CMPLWI = 212 , PPC_INS_CMPRB = 213 , PPC_INS_CMPW = 214 , PPC_INS_CMPWI = 215 , PPC_INS_CNTLZD = 216 , PPC_INS_CNTLZW = 217 , PPC_INS_CNTTZD = 218 , PPC_INS_CNTTZW = 219 , PPC_INS_COPY = 220 , PPC_INS_COPY_FIRST = 221 , PPC_INS_CP_ABORT = 222 , PPC_INS_CRAND = 223 , PPC_INS_CRANDC = 224 , PPC_INS_CRCLR = 225 , PPC_INS_CREQV = 226 , PPC_INS_CRMOVE = 227 , PPC_INS_CRNAND = 228 , PPC_INS_CRNOR = 229 , PPC_INS_CRNOT = 230 , PPC_INS_CROR = 231 , PPC_INS_CRORC = 232 , PPC_INS_CRSET = 233 , PPC_INS_CRXOR = 234 , PPC_INS_DARN = 235 , PPC_INS_DCBA = 236 , PPC_INS_DCBF = 237 , PPC_INS_DCBFEP = 238 , PPC_INS_DCBFL = 239 , PPC_INS_DCBFLP = 240 , PPC_INS_DCBI = 241 , PPC_INS_DCBST = 242 , PPC_INS_DCBSTEP = 243 , PPC_INS_DCBT = 244 , PPC_INS_DCBTCT = 245 , PPC_INS_DCBTDS = 246 , PPC_INS_DCBTEP = 247 , PPC_INS_DCBTST = 248 , PPC_INS_DCBTSTCT = 249 , PPC_INS_DCBTSTDS = 250 , PPC_INS_DCBTSTEP = 251 , PPC_INS_DCBTSTT = 252 , PPC_INS_DCBTT = 253 , PPC_INS_DCBZ = 254 , PPC_INS_DCBZEP = 255 , PPC_INS_DCBZL = 256 , PPC_INS_DCBZLEP = 257 , PPC_INS_DCCCI = 258 , PPC_INS_DCI = 259 , PPC_INS_DIVD = 260 , PPC_INS_DIVDE = 261 , PPC_INS_DIVDEU = 262 , PPC_INS_DIVDU = 263 , PPC_INS_DIVW = 264 , PPC_INS_DIVWE = 265 , PPC_INS_DIVWEU = 266 , PPC_INS_DIVWU = 267 , PPC_INS_DSS = 268 , PPC_INS_DSSALL = 269 , PPC_INS_DST = 270 , PPC_INS_DSTST = 271 , PPC_INS_DSTSTT = 272 , PPC_INS_DSTT = 273 , PPC_INS_EFDABS = 274 , PPC_INS_EFDADD = 275 , PPC_INS_EFDCFS = 276 , PPC_INS_EFDCFSF = 277 , PPC_INS_EFDCFSI = 278 , PPC_INS_EFDCFSID = 279 , PPC_INS_EFDCFUF = 280 , PPC_INS_EFDCFUI = 281 , PPC_INS_EFDCFUID = 282 , PPC_INS_EFDCMPEQ = 283 , PPC_INS_EFDCMPGT = 284 , PPC_INS_EFDCMPLT = 285 , PPC_INS_EFDCTSF = 286 , PPC_INS_EFDCTSI = 287 , PPC_INS_EFDCTSIDZ = 288 , PPC_INS_EFDCTSIZ = 289 , PPC_INS_EFDCTUF = 290 , PPC_INS_EFDCTUI = 291 , PPC_INS_EFDCTUIDZ = 292 , PPC_INS_EFDCTUIZ = 293 , PPC_INS_EFDDIV = 294 , PPC_INS_EFDMUL = 295 , PPC_INS_EFDNABS = 296 , PPC_INS_EFDNEG = 297 , PPC_INS_EFDSUB = 298 , PPC_INS_EFDTSTEQ = 299 , PPC_INS_EFDTSTGT = 300 , PPC_INS_EFDTSTLT = 301 , PPC_INS_EFSABS = 302 , PPC_INS_EFSADD = 303 , PPC_INS_EFSCFD = 304 , PPC_INS_EFSCFSF = 305 , PPC_INS_EFSCFSI = 306 , PPC_INS_EFSCFUF = 307 , PPC_INS_EFSCFUI = 308 , PPC_INS_EFSCMPEQ = 309 , PPC_INS_EFSCMPGT = 310 , PPC_INS_EFSCMPLT = 311 , PPC_INS_EFSCTSF = 312 , PPC_INS_EFSCTSI = 313 , PPC_INS_EFSCTSIZ = 314 , PPC_INS_EFSCTUF = 315 , PPC_INS_EFSCTUI = 316 , PPC_INS_EFSCTUIZ = 317 , PPC_INS_EFSDIV = 318 , PPC_INS_EFSMUL = 319 , PPC_INS_EFSNABS = 320 , PPC_INS_EFSNEG = 321 , PPC_INS_EFSSUB = 322 , PPC_INS_EFSTSTEQ = 323 , PPC_INS_EFSTSTGT = 324 , PPC_INS_EFSTSTLT = 325 , PPC_INS_EIEIO = 326 , PPC_INS_EQV = 327 , PPC_INS_EVABS = 328 , PPC_INS_EVADDIW = 329 , PPC_INS_EVADDSMIAAW = 330 , PPC_INS_EVADDSSIAAW = 331 , PPC_INS_EVADDUMIAAW = 332 , PPC_INS_EVADDUSIAAW = 333 , PPC_INS_EVADDW = 334 , PPC_INS_EVAND = 335 , PPC_INS_EVANDC = 336 , PPC_INS_EVCMPEQ = 337 , PPC_INS_EVCMPGTS = 338 , PPC_INS_EVCMPGTU = 339 , PPC_INS_EVCMPLTS = 340 , PPC_INS_EVCMPLTU = 341 , PPC_INS_EVCNTLSW = 342 , PPC_INS_EVCNTLZW = 343 , PPC_INS_EVDIVWS = 344 , PPC_INS_EVDIVWU = 345 , PPC_INS_EVEQV = 346 , PPC_INS_EVEXTSB = 347 , PPC_INS_EVEXTSH = 348 , PPC_INS_EVFSABS = 349 , PPC_INS_EVFSADD = 350 , PPC_INS_EVFSCFSF = 351 , PPC_INS_EVFSCFSI = 352 , PPC_INS_EVFSCFUF = 353 , PPC_INS_EVFSCFUI = 354 , PPC_INS_EVFSCMPEQ = 355 , PPC_INS_EVFSCMPGT = 356 , PPC_INS_EVFSCMPLT = 357 , PPC_INS_EVFSCTSF = 358 , PPC_INS_EVFSCTSI = 359 , PPC_INS_EVFSCTSIZ = 360 , PPC_INS_EVFSCTUI = 361 , PPC_INS_EVFSDIV = 362 , PPC_INS_EVFSMUL = 363 , PPC_INS_EVFSNABS = 364 , PPC_INS_EVFSNEG = 365 , PPC_INS_EVFSSUB = 366 , PPC_INS_EVFSTSTEQ = 367 , PPC_INS_EVFSTSTGT = 368 , PPC_INS_EVFSTSTLT = 369 , PPC_INS_EVLDD = 370 , PPC_INS_EVLDDX = 371 , PPC_INS_EVLDH = 372 , PPC_INS_EVLDHX = 373 , PPC_INS_EVLDW = 374 , PPC_INS_EVLDWX = 375 , PPC_INS_EVLHHESPLAT = 376 , PPC_INS_EVLHHESPLATX = 377 , PPC_INS_EVLHHOSSPLAT = 378 , PPC_INS_EVLHHOSSPLATX = 379 , PPC_INS_EVLHHOUSPLAT = 380 , PPC_INS_EVLHHOUSPLATX = 381 , PPC_INS_EVLWHE = 382 , PPC_INS_EVLWHEX = 383 , PPC_INS_EVLWHOS = 384 , PPC_INS_EVLWHOSX = 385 , PPC_INS_EVLWHOU = 386 , PPC_INS_EVLWHOUX = 387 , PPC_INS_EVLWHSPLAT = 388 , PPC_INS_EVLWHSPLATX = 389 , PPC_INS_EVLWWSPLAT = 390 , PPC_INS_EVLWWSPLATX = 391 , PPC_INS_EVMERGEHI = 392 , PPC_INS_EVMERGEHILO = 393 , PPC_INS_EVMERGELO = 394 , PPC_INS_EVMERGELOHI = 395 , PPC_INS_EVMHEGSMFAA = 396 , PPC_INS_EVMHEGSMFAN = 397 , PPC_INS_EVMHEGSMIAA = 398 , PPC_INS_EVMHEGSMIAN = 399 , PPC_INS_EVMHEGUMIAA = 400 , PPC_INS_EVMHEGUMIAN = 401 , PPC_INS_EVMHESMF = 402 , PPC_INS_EVMHESMFA = 403 , PPC_INS_EVMHESMFAAW = 404 , PPC_INS_EVMHESMFANW = 405 , PPC_INS_EVMHESMI = 406 , PPC_INS_EVMHESMIA = 407 , PPC_INS_EVMHESMIAAW = 408 , PPC_INS_EVMHESMIANW = 409 , PPC_INS_EVMHESSF = 410 , PPC_INS_EVMHESSFA = 411 , PPC_INS_EVMHESSFAAW = 412 , PPC_INS_EVMHESSFANW = 413 , PPC_INS_EVMHESSIAAW = 414 , PPC_INS_EVMHESSIANW = 415 , PPC_INS_EVMHEUMI = 416 , PPC_INS_EVMHEUMIA = 417 , PPC_INS_EVMHEUMIAAW = 418 , PPC_INS_EVMHEUMIANW = 419 , PPC_INS_EVMHEUSIAAW = 420 , PPC_INS_EVMHEUSIANW = 421 , PPC_INS_EVMHOGSMFAA = 422 , PPC_INS_EVMHOGSMFAN = 423 , PPC_INS_EVMHOGSMIAA = 424 , PPC_INS_EVMHOGSMIAN = 425 , PPC_INS_EVMHOGUMIAA = 426 , PPC_INS_EVMHOGUMIAN = 427 , PPC_INS_EVMHOSMF = 428 , PPC_INS_EVMHOSMFA = 429 , PPC_INS_EVMHOSMFAAW = 430 , PPC_INS_EVMHOSMFANW = 431 , PPC_INS_EVMHOSMI = 432 , PPC_INS_EVMHOSMIA = 433 , PPC_INS_EVMHOSMIAAW = 434 , PPC_INS_EVMHOSMIANW = 435 , PPC_INS_EVMHOSSF = 436 , PPC_INS_EVMHOSSFA = 437 , PPC_INS_EVMHOSSFAAW = 438 , PPC_INS_EVMHOSSFANW = 439 , PPC_INS_EVMHOSSIAAW = 440 , PPC_INS_EVMHOSSIANW = 441 , PPC_INS_EVMHOUMI = 442 , PPC_INS_EVMHOUMIA = 443 , PPC_INS_EVMHOUMIAAW = 444 , PPC_INS_EVMHOUMIANW = 445 , PPC_INS_EVMHOUSIAAW = 446 , PPC_INS_EVMHOUSIANW = 447 , PPC_INS_EVMRA = 448 , PPC_INS_EVMWHSMF = 449 , PPC_INS_EVMWHSMFA = 450 , PPC_INS_EVMWHSMI = 451 , PPC_INS_EVMWHSMIA = 452 , PPC_INS_EVMWHSSF = 453 , PPC_INS_EVMWHSSFA = 454 , PPC_INS_EVMWHUMI = 455 , PPC_INS_EVMWHUMIA = 456 , PPC_INS_EVMWLSMIAAW = 457 , PPC_INS_EVMWLSMIANW = 458 , PPC_INS_EVMWLSSIAAW = 459 , PPC_INS_EVMWLSSIANW = 460 , PPC_INS_EVMWLUMI = 461 , PPC_INS_EVMWLUMIA = 462 , PPC_INS_EVMWLUMIAAW = 463 , PPC_INS_EVMWLUMIANW = 464 , PPC_INS_EVMWLUSIAAW = 465 , PPC_INS_EVMWLUSIANW = 466 , PPC_INS_EVMWSMF = 467 , PPC_INS_EVMWSMFA = 468 , PPC_INS_EVMWSMFAA = 469 , PPC_INS_EVMWSMFAN = 470 , PPC_INS_EVMWSMI = 471 , PPC_INS_EVMWSMIA = 472 , PPC_INS_EVMWSMIAA = 473 , PPC_INS_EVMWSMIAN = 474 , PPC_INS_EVMWSSF = 475 , PPC_INS_EVMWSSFA = 476 , PPC_INS_EVMWSSFAA = 477 , PPC_INS_EVMWSSFAN = 478 , PPC_INS_EVMWUMI = 479 , PPC_INS_EVMWUMIA = 480 , PPC_INS_EVMWUMIAA = 481 , PPC_INS_EVMWUMIAN = 482 , PPC_INS_EVNAND = 483 , PPC_INS_EVNEG = 484 , PPC_INS_EVNOR = 485 , PPC_INS_EVOR = 486 , PPC_INS_EVORC = 487 , PPC_INS_EVRLW = 488 , PPC_INS_EVRLWI = 489 , PPC_INS_EVRNDW = 490 , PPC_INS_EVSEL = 491 , PPC_INS_EVSLW = 492 , PPC_INS_EVSLWI = 493 , PPC_INS_EVSPLATFI = 494 , PPC_INS_EVSPLATI = 495 , PPC_INS_EVSRWIS = 496 , PPC_INS_EVSRWIU = 497 , PPC_INS_EVSRWS = 498 , PPC_INS_EVSRWU = 499 , PPC_INS_EVSTDD = 500 , PPC_INS_EVSTDDX = 501 , PPC_INS_EVSTDH = 502 , PPC_INS_EVSTDHX = 503 , PPC_INS_EVSTDW = 504 , PPC_INS_EVSTDWX = 505 , PPC_INS_EVSTWHE = 506 , PPC_INS_EVSTWHEX = 507 , PPC_INS_EVSTWHO = 508 , PPC_INS_EVSTWHOX = 509 , PPC_INS_EVSTWWE = 510 , PPC_INS_EVSTWWEX = 511 , PPC_INS_EVSTWWO = 512 , PPC_INS_EVSTWWOX = 513 , PPC_INS_EVSUBFSMIAAW = 514 , PPC_INS_EVSUBFSSIAAW = 515 , PPC_INS_EVSUBFUMIAAW = 516 , PPC_INS_EVSUBFUSIAAW = 517 , PPC_INS_EVSUBFW = 518 , PPC_INS_EVSUBIFW = 519 , PPC_INS_EVXOR = 520 , PPC_INS_EXTLDI = 521 , PPC_INS_EXTLWI = 522 , PPC_INS_EXTRDI = 523 , PPC_INS_EXTRWI = 524 , PPC_INS_EXTSB = 525 , PPC_INS_EXTSH = 526 , PPC_INS_EXTSW = 527 , PPC_INS_EXTSWSLI = 528 , PPC_INS_FABS = 529 , PPC_INS_FADD = 530 , PPC_INS_FADDS = 531 , PPC_INS_FCFID = 532 , PPC_INS_FCFIDS = 533 , PPC_INS_FCFIDU = 534 , PPC_INS_FCFIDUS = 535 , PPC_INS_FCMPU = 536 , PPC_INS_FCPSGN = 537 , PPC_INS_FCTID = 538 , PPC_INS_FCTIDU = 539 , PPC_INS_FCTIDUZ = 540 , PPC_INS_FCTIDZ = 541 , PPC_INS_FCTIW = 542 , PPC_INS_FCTIWU = 543 , PPC_INS_FCTIWUZ = 544 , PPC_INS_FCTIWZ = 545 , PPC_INS_FDIV = 546 , PPC_INS_FDIVS = 547 , PPC_INS_FMADD = 548 , PPC_INS_FMADDS = 549 , PPC_INS_FMR = 550 , PPC_INS_FMSUB = 551 , PPC_INS_FMSUBS = 552 , PPC_INS_FMUL = 553 , PPC_INS_FMULS = 554 , PPC_INS_FNABS = 555 , PPC_INS_FNEG = 556 , PPC_INS_FNMADD = 557 , PPC_INS_FNMADDS = 558 , PPC_INS_FNMSUB = 559 , PPC_INS_FNMSUBS = 560 , PPC_INS_FRE = 561 , PPC_INS_FRES = 562 , PPC_INS_FRIM = 563 , PPC_INS_FRIN = 564 , PPC_INS_FRIP = 565 , PPC_INS_FRIZ = 566 , PPC_INS_FRSP = 567 , PPC_INS_FRSQRTE = 568 , PPC_INS_FRSQRTES = 569 , PPC_INS_FSEL = 570 , PPC_INS_FSQRT = 571 , PPC_INS_FSQRTS = 572 , PPC_INS_FSUB = 573 , PPC_INS_FSUBS = 574 , PPC_INS_FTDIV = 575 , PPC_INS_FTSQRT = 576 , PPC_INS_HRFID = 577 , PPC_INS_ICBI = 578 , PPC_INS_ICBIEP = 579 , PPC_INS_ICBLC = 580 , PPC_INS_ICBLQ = 581 , PPC_INS_ICBT = 582 , PPC_INS_ICBTLS = 583 , PPC_INS_ICCCI = 584 , PPC_INS_ICI = 585 , PPC_INS_INSLWI = 586 , PPC_INS_INSRDI = 587 , PPC_INS_INSRWI = 588 , PPC_INS_ISEL = 589 , PPC_INS_ISYNC = 590 , PPC_INS_LA = 591 , PPC_INS_LBARX = 592 , PPC_INS_LBEPX = 593 , PPC_INS_LBZ = 594 , PPC_INS_LBZCIX = 595 , PPC_INS_LBZU = 596 , PPC_INS_LBZUX = 597 , PPC_INS_LBZX = 598 , PPC_INS_LD = 599 , PPC_INS_LDARX = 600 , PPC_INS_LDAT = 601 , PPC_INS_LDBRX = 602 , PPC_INS_LDCIX = 603 , PPC_INS_LDMX = 604 , PPC_INS_LDU = 605 , PPC_INS_LDUX = 606 , PPC_INS_LDX = 607 , PPC_INS_LFD = 608 , PPC_INS_LFDEPX = 609 , PPC_INS_LFDU = 610 , PPC_INS_LFDUX = 611 , PPC_INS_LFDX = 612 , PPC_INS_LFIWAX = 613 , PPC_INS_LFIWZX = 614 , PPC_INS_LFS = 615 , PPC_INS_LFSU = 616 , PPC_INS_LFSUX = 617 , PPC_INS_LFSX = 618 , PPC_INS_LHA = 619 , PPC_INS_LHARX = 620 , PPC_INS_LHAU = 621 , PPC_INS_LHAUX = 622 , PPC_INS_LHAX = 623 , PPC_INS_LHBRX = 624 , PPC_INS_LHEPX = 625 , PPC_INS_LHZ = 626 , PPC_INS_LHZCIX = 627 , PPC_INS_LHZU = 628 , PPC_INS_LHZUX = 629 , PPC_INS_LHZX = 630 , PPC_INS_LI = 631 , PPC_INS_LIS = 632 , PPC_INS_LMW = 633 , PPC_INS_LNIA = 634 , PPC_INS_LSWI = 635 , PPC_INS_LVEBX = 636 , PPC_INS_LVEHX = 637 , PPC_INS_LVEWX = 638 , PPC_INS_LVSL = 639 , PPC_INS_LVSR = 640 , PPC_INS_LVX = 641 , PPC_INS_LVXL = 642 , PPC_INS_LWA = 643 , PPC_INS_LWARX = 644 , PPC_INS_LWAT = 645 , PPC_INS_LWAUX = 646 , PPC_INS_LWAX = 647 , PPC_INS_LWBRX = 648 , PPC_INS_LWEPX = 649 , PPC_INS_LWSYNC = 650 , PPC_INS_LWZ = 651 , PPC_INS_LWZCIX = 652 , PPC_INS_LWZU = 653 , PPC_INS_LWZUX = 654 , PPC_INS_LWZX = 655 , PPC_INS_LXSD = 656 , PPC_INS_LXSDX = 657 , PPC_INS_LXSIBZX = 658 , PPC_INS_LXSIHZX = 659 , PPC_INS_LXSIWAX = 660 , PPC_INS_LXSIWZX = 661 , PPC_INS_LXSSP = 662 , PPC_INS_LXSSPX = 663 , PPC_INS_LXV = 664 , PPC_INS_LXVB16X = 665 , PPC_INS_LXVD2X = 666 , PPC_INS_LXVDSX = 667 , PPC_INS_LXVH8X = 668 , PPC_INS_LXVL = 669 , PPC_INS_LXVLL = 670 , PPC_INS_LXVW4X = 671 , PPC_INS_LXVWSX = 672 , PPC_INS_LXVX = 673 , PPC_INS_MADDHD = 674 , PPC_INS_MADDHDU = 675 , PPC_INS_MADDLD = 676 , PPC_INS_MBAR = 677 , PPC_INS_MCRF = 678 , PPC_INS_MCRFS = 679 , PPC_INS_MCRXRX = 680 , PPC_INS_MFAMR = 681 , PPC_INS_MFASR = 682 , PPC_INS_MFBHRBE = 683 , PPC_INS_MFBR0 = 684 , PPC_INS_MFBR1 = 685 , PPC_INS_MFBR2 = 686 , PPC_INS_MFBR3 = 687 , PPC_INS_MFBR4 = 688 , PPC_INS_MFBR5 = 689 , PPC_INS_MFBR6 = 690 , PPC_INS_MFBR7 = 691 , PPC_INS_MFCFAR = 692 , PPC_INS_MFCR = 693 , PPC_INS_MFCTR = 694 , PPC_INS_MFDAR = 695 , PPC_INS_MFDBATL = 696 , PPC_INS_MFDBATU = 697 , PPC_INS_MFDCCR = 698 , PPC_INS_MFDCR = 699 , PPC_INS_MFDEAR = 700 , PPC_INS_MFDEC = 701 , PPC_INS_MFDSCR = 702 , PPC_INS_MFDSISR = 703 , PPC_INS_MFESR = 704 , PPC_INS_MFFPRD = 705 , PPC_INS_MFFS = 706 , PPC_INS_MFFSCDRN = 707 , PPC_INS_MFFSCDRNI = 708 , PPC_INS_MFFSCE = 709 , PPC_INS_MFFSCRN = 710 , PPC_INS_MFFSCRNI = 711 , PPC_INS_MFFSL = 712 , PPC_INS_MFIBATL = 713 , PPC_INS_MFIBATU = 714 , PPC_INS_MFICCR = 715 , PPC_INS_MFLR = 716 , PPC_INS_MFMSR = 717 , PPC_INS_MFOCRF = 718 , PPC_INS_MFPID = 719 , PPC_INS_MFPMR = 720 , PPC_INS_MFPVR = 721 , PPC_INS_MFRTCL = 722 , PPC_INS_MFRTCU = 723 , PPC_INS_MFSDR1 = 724 , PPC_INS_MFSPEFSCR = 725 , PPC_INS_MFSPR = 726 , PPC_INS_MFSPRG = 727 , PPC_INS_MFSPRG0 = 728 , PPC_INS_MFSPRG1 = 729 , PPC_INS_MFSPRG2 = 730 , PPC_INS_MFSPRG3 = 731 , PPC_INS_MFSPRG4 = 732 , PPC_INS_MFSPRG5 = 733 , PPC_INS_MFSPRG6 = 734 , PPC_INS_MFSPRG7 = 735 , PPC_INS_MFSR = 736 , PPC_INS_MFSRIN = 737 , PPC_INS_MFSRR0 = 738 , PPC_INS_MFSRR1 = 739 , PPC_INS_MFSRR2 = 740 , PPC_INS_MFSRR3 = 741 , PPC_INS_MFTB = 742 , PPC_INS_MFTBHI = 743 , PPC_INS_MFTBL = 744 , PPC_INS_MFTBLO = 745 , PPC_INS_MFTBU = 746 , PPC_INS_MFTCR = 747 , PPC_INS_MFVRD = 748 , PPC_INS_MFVRSAVE = 749 , PPC_INS_MFVSCR = 750 , PPC_INS_MFVSRD = 751 , PPC_INS_MFVSRLD = 752 , PPC_INS_MFVSRWZ = 753 , PPC_INS_MFXER = 754 , PPC_INS_MODSD = 755 , PPC_INS_MODSW = 756 , PPC_INS_MODUD = 757 , PPC_INS_MODUW = 758 , PPC_INS_MR = 759 , PPC_INS_MSGSYNC = 760 , PPC_INS_MSYNC = 761 , PPC_INS_MTAMR = 762 , PPC_INS_MTASR = 763 , PPC_INS_MTBR0 = 764 , PPC_INS_MTBR1 = 765 , PPC_INS_MTBR2 = 766 , PPC_INS_MTBR3 = 767 , PPC_INS_MTBR4 = 768 , PPC_INS_MTBR5 = 769 , PPC_INS_MTBR6 = 770 , PPC_INS_MTBR7 = 771 , PPC_INS_MTCFAR = 772 , PPC_INS_MTCR = 773 , PPC_INS_MTCRF = 774 , PPC_INS_MTCTR = 775 , PPC_INS_MTDAR = 776 , PPC_INS_MTDBATL = 777 , PPC_INS_MTDBATU = 778 , PPC_INS_MTDCCR = 779 , PPC_INS_MTDCR = 780 , PPC_INS_MTDEAR = 781 , PPC_INS_MTDEC = 782 , PPC_INS_MTDSCR = 783 , PPC_INS_MTDSISR = 784 , PPC_INS_MTESR = 785 , PPC_INS_MTFSB0 = 786 , PPC_INS_MTFSB1 = 787 , PPC_INS_MTFSF = 788 , PPC_INS_MTFSFI = 789 , PPC_INS_MTIBATL = 790 , PPC_INS_MTIBATU = 791 , PPC_INS_MTICCR = 792 , PPC_INS_MTLR = 793 , PPC_INS_MTMSR = 794 , PPC_INS_MTMSRD = 795 , PPC_INS_MTOCRF = 796 , PPC_INS_MTPID = 797 , PPC_INS_MTPMR = 798 , PPC_INS_MTSDR1 = 799 , PPC_INS_MTSPEFSCR = 800 , PPC_INS_MTSPR = 801 , PPC_INS_MTSPRG = 802 , PPC_INS_MTSPRG0 = 803 , PPC_INS_MTSPRG1 = 804 , PPC_INS_MTSPRG2 = 805 , PPC_INS_MTSPRG3 = 806 , PPC_INS_MTSPRG4 = 807 , PPC_INS_MTSPRG5 = 808 , PPC_INS_MTSPRG6 = 809 , PPC_INS_MTSPRG7 = 810 , PPC_INS_MTSR = 811 , PPC_INS_MTSRIN = 812 , PPC_INS_MTSRR0 = 813 , PPC_INS_MTSRR1 = 814 , PPC_INS_MTSRR2 = 815 , PPC_INS_MTSRR3 = 816 , PPC_INS_MTTBHI = 817 , PPC_INS_MTTBL = 818 , PPC_INS_MTTBLO = 819 , PPC_INS_MTTBU = 820 , PPC_INS_MTTCR = 821 , PPC_INS_MTVRSAVE = 822 , PPC_INS_MTVSCR = 823 , PPC_INS_MTVSRD = 824 , PPC_INS_MTVSRDD = 825 , PPC_INS_MTVSRWA = 826 , PPC_INS_MTVSRWS = 827 , PPC_INS_MTVSRWZ = 828 , PPC_INS_MTXER = 829 , PPC_INS_MULHD = 830 , PPC_INS_MULHDU = 831 , PPC_INS_MULHW = 832 , PPC_INS_MULHWU = 833 , PPC_INS_MULLD = 834 , PPC_INS_MULLI = 835 , PPC_INS_MULLW = 836 , PPC_INS_NAND = 837 , PPC_INS_NAP = 838 , PPC_INS_NEG = 839 , PPC_INS_NOP = 840 , PPC_INS_NOR = 841 , PPC_INS_NOT = 842 , PPC_INS_OR = 843 , PPC_INS_ORC = 844 , PPC_INS_ORI = 845 , PPC_INS_ORIS = 846 , PPC_INS_PASTE = 847 , PPC_INS_PASTE_LAST = 848 , PPC_INS_POPCNTB = 849 , PPC_INS_POPCNTD = 850 , PPC_INS_POPCNTW = 851 , PPC_INS_PTESYNC = 852 , PPC_INS_QVALIGNI = 853 , PPC_INS_QVESPLATI = 854 , PPC_INS_QVFABS = 855 , PPC_INS_QVFADD = 856 , PPC_INS_QVFADDS = 857 , PPC_INS_QVFAND = 858 , PPC_INS_QVFANDC = 859 , PPC_INS_QVFCFID = 860 , PPC_INS_QVFCFIDS = 861 , PPC_INS_QVFCFIDU = 862 , PPC_INS_QVFCFIDUS = 863 , PPC_INS_QVFCLR = 864 , PPC_INS_QVFCMPEQ = 865 , PPC_INS_QVFCMPGT = 866 , PPC_INS_QVFCMPLT = 867 , PPC_INS_QVFCPSGN = 868 , PPC_INS_QVFCTFB = 869 , PPC_INS_QVFCTID = 870 , PPC_INS_QVFCTIDU = 871 , PPC_INS_QVFCTIDUZ = 872 , PPC_INS_QVFCTIDZ = 873 , PPC_INS_QVFCTIW = 874 , PPC_INS_QVFCTIWU = 875 , PPC_INS_QVFCTIWUZ = 876 , PPC_INS_QVFCTIWZ = 877 , PPC_INS_QVFEQU = 878 , PPC_INS_QVFLOGICAL = 879 , PPC_INS_QVFMADD = 880 , PPC_INS_QVFMADDS = 881 , PPC_INS_QVFMR = 882 , PPC_INS_QVFMSUB = 883 , PPC_INS_QVFMSUBS = 884 , PPC_INS_QVFMUL = 885 , PPC_INS_QVFMULS = 886 , PPC_INS_QVFNABS = 887 , PPC_INS_QVFNAND = 888 , PPC_INS_QVFNEG = 889 , PPC_INS_QVFNMADD = 890 , PPC_INS_QVFNMADDS = 891 , PPC_INS_QVFNMSUB = 892 , PPC_INS_QVFNMSUBS = 893 , PPC_INS_QVFNOR = 894 , PPC_INS_QVFNOT = 895 , PPC_INS_QVFOR = 896 , PPC_INS_QVFORC = 897 , PPC_INS_QVFPERM = 898 , PPC_INS_QVFRE = 899 , PPC_INS_QVFRES = 900 , PPC_INS_QVFRIM = 901 , PPC_INS_QVFRIN = 902 , PPC_INS_QVFRIP = 903 , PPC_INS_QVFRIZ = 904 , PPC_INS_QVFRSP = 905 , PPC_INS_QVFRSQRTE = 906 , PPC_INS_QVFRSQRTES = 907 , PPC_INS_QVFSEL = 908 , PPC_INS_QVFSET = 909 , PPC_INS_QVFSUB = 910 , PPC_INS_QVFSUBS = 911 , PPC_INS_QVFTSTNAN = 912 , PPC_INS_QVFXMADD = 913 , PPC_INS_QVFXMADDS = 914 , PPC_INS_QVFXMUL = 915 , PPC_INS_QVFXMULS = 916 , PPC_INS_QVFXOR = 917 , PPC_INS_QVFXXCPNMADD = 918 , PPC_INS_QVFXXCPNMADDS = 919 , PPC_INS_QVFXXMADD = 920 , PPC_INS_QVFXXMADDS = 921 , PPC_INS_QVFXXNPMADD = 922 , PPC_INS_QVFXXNPMADDS = 923 , PPC_INS_QVGPCI = 924 , PPC_INS_QVLFCDUX = 925 , PPC_INS_QVLFCDUXA = 926 , PPC_INS_QVLFCDX = 927 , PPC_INS_QVLFCDXA = 928 , PPC_INS_QVLFCSUX = 929 , PPC_INS_QVLFCSUXA = 930 , PPC_INS_QVLFCSX = 931 , PPC_INS_QVLFCSXA = 932 , PPC_INS_QVLFDUX = 933 , PPC_INS_QVLFDUXA = 934 , PPC_INS_QVLFDX = 935 , PPC_INS_QVLFDXA = 936 , PPC_INS_QVLFIWAX = 937 , PPC_INS_QVLFIWAXA = 938 , PPC_INS_QVLFIWZX = 939 , PPC_INS_QVLFIWZXA = 940 , PPC_INS_QVLFSUX = 941 , PPC_INS_QVLFSUXA = 942 , PPC_INS_QVLFSX = 943 , PPC_INS_QVLFSXA = 944 , PPC_INS_QVLPCLDX = 945 , PPC_INS_QVLPCLSX = 946 , PPC_INS_QVLPCRDX = 947 , PPC_INS_QVLPCRSX = 948 , PPC_INS_QVSTFCDUX = 949 , PPC_INS_QVSTFCDUXA = 950 , PPC_INS_QVSTFCDUXI = 951 , PPC_INS_QVSTFCDUXIA = 952 , PPC_INS_QVSTFCDX = 953 , PPC_INS_QVSTFCDXA = 954 , PPC_INS_QVSTFCDXI = 955 , PPC_INS_QVSTFCDXIA = 956 , PPC_INS_QVSTFCSUX = 957 , PPC_INS_QVSTFCSUXA = 958 , PPC_INS_QVSTFCSUXI = 959 , PPC_INS_QVSTFCSUXIA = 960 , PPC_INS_QVSTFCSX = 961 , PPC_INS_QVSTFCSXA = 962 , PPC_INS_QVSTFCSXI = 963 , PPC_INS_QVSTFCSXIA = 964 , PPC_INS_QVSTFDUX = 965 , PPC_INS_QVSTFDUXA = 966 , PPC_INS_QVSTFDUXI = 967 , PPC_INS_QVSTFDUXIA = 968 , PPC_INS_QVSTFDX = 969 , PPC_INS_QVSTFDXA = 970 , PPC_INS_QVSTFDXI = 971 , PPC_INS_QVSTFDXIA = 972 , PPC_INS_QVSTFIWX = 973 , PPC_INS_QVSTFIWXA = 974 , PPC_INS_QVSTFSUX = 975 , PPC_INS_QVSTFSUXA = 976 , PPC_INS_QVSTFSUXI = 977 , PPC_INS_QVSTFSUXIA = 978 , PPC_INS_QVSTFSX = 979 , PPC_INS_QVSTFSXA = 980 , PPC_INS_QVSTFSXI = 981 , PPC_INS_QVSTFSXIA = 982 , PPC_INS_RFCI = 983 , PPC_INS_RFDI = 984 , PPC_INS_RFEBB = 985 , PPC_INS_RFI = 986 , PPC_INS_RFID = 987 , PPC_INS_RFMCI = 988 , PPC_INS_RLDCL = 989 , PPC_INS_RLDCR = 990 , PPC_INS_RLDIC = 991 , PPC_INS_RLDICL = 992 , PPC_INS_RLDICR = 993 , PPC_INS_RLDIMI = 994 , PPC_INS_RLWIMI = 995 , PPC_INS_RLWINM = 996 , PPC_INS_RLWNM = 997 , PPC_INS_ROTLD = 998 , PPC_INS_ROTLDI = 999 , PPC_INS_ROTLW = 1000 , PPC_INS_ROTLWI = 1001 , PPC_INS_ROTRDI = 1002 , PPC_INS_ROTRWI = 1003 , PPC_INS_SC = 1004 , PPC_INS_SETB = 1005 , PPC_INS_SLBIA = 1006 , PPC_INS_SLBIE = 1007 , PPC_INS_SLBIEG = 1008 , PPC_INS_SLBMFEE = 1009 , PPC_INS_SLBMFEV = 1010 , PPC_INS_SLBMTE = 1011 , PPC_INS_SLBSYNC = 1012 , PPC_INS_SLD = 1013 , PPC_INS_SLDI = 1014 , PPC_INS_SLW = 1015 , PPC_INS_SLWI = 1016 , PPC_INS_SRAD = 1017 , PPC_INS_SRADI = 1018 , PPC_INS_SRAW = 1019 , PPC_INS_SRAWI = 1020 , PPC_INS_SRD = 1021 , PPC_INS_SRDI = 1022 , PPC_INS_SRW = 1023 , PPC_INS_SRWI = 1024 , PPC_INS_STB = 1025 , PPC_INS_STBCIX = 1026 , PPC_INS_STBCX = 1027 , PPC_INS_STBEPX = 1028 , PPC_INS_STBU = 1029 , PPC_INS_STBUX = 1030 , PPC_INS_STBX = 1031 , PPC_INS_STD = 1032 , PPC_INS_STDAT = 1033 , PPC_INS_STDBRX = 1034 , PPC_INS_STDCIX = 1035 , PPC_INS_STDCX = 1036 , PPC_INS_STDU = 1037 , PPC_INS_STDUX = 1038 , PPC_INS_STDX = 1039 , PPC_INS_STFD = 1040 , PPC_INS_STFDEPX = 1041 , PPC_INS_STFDU = 1042 , PPC_INS_STFDUX = 1043 , PPC_INS_STFDX = 1044 , PPC_INS_STFIWX = 1045 , PPC_INS_STFS = 1046 , PPC_INS_STFSU = 1047 , PPC_INS_STFSUX = 1048 , PPC_INS_STFSX = 1049 , PPC_INS_STH = 1050 , PPC_INS_STHBRX = 1051 , PPC_INS_STHCIX = 1052 , PPC_INS_STHCX = 1053 , PPC_INS_STHEPX = 1054 , PPC_INS_STHU = 1055 , PPC_INS_STHUX = 1056 , PPC_INS_STHX = 1057 , PPC_INS_STMW = 1058 , PPC_INS_STOP = 1059 , PPC_INS_STSWI = 1060 , PPC_INS_STVEBX = 1061 , PPC_INS_STVEHX = 1062 , PPC_INS_STVEWX = 1063 , PPC_INS_STVX = 1064 , PPC_INS_STVXL = 1065 , PPC_INS_STW = 1066 , PPC_INS_STWAT = 1067 , PPC_INS_STWBRX = 1068 , PPC_INS_STWCIX = 1069 , PPC_INS_STWCX = 1070 , PPC_INS_STWEPX = 1071 , PPC_INS_STWU = 1072 , PPC_INS_STWUX = 1073 , PPC_INS_STWX = 1074 , PPC_INS_STXSD = 1075 , PPC_INS_STXSDX = 1076 , PPC_INS_STXSIBX = 1077 , PPC_INS_STXSIHX = 1078 , PPC_INS_STXSIWX = 1079 , PPC_INS_STXSSP = 1080 , PPC_INS_STXSSPX = 1081 , PPC_INS_STXV = 1082 , PPC_INS_STXVB16X = 1083 , PPC_INS_STXVD2X = 1084 , PPC_INS_STXVH8X = 1085 , PPC_INS_STXVL = 1086 , PPC_INS_STXVLL = 1087 , PPC_INS_STXVW4X = 1088 , PPC_INS_STXVX = 1089 , PPC_INS_SUB = 1090 , PPC_INS_SUBC = 1091 , PPC_INS_SUBF = 1092 , PPC_INS_SUBFC = 1093 , PPC_INS_SUBFE = 1094 , PPC_INS_SUBFIC = 1095 , PPC_INS_SUBFME = 1096 , PPC_INS_SUBFZE = 1097 , PPC_INS_SUBI = 1098 , PPC_INS_SUBIC = 1099 , PPC_INS_SUBIS = 1100 , PPC_INS_SUBPCIS = 1101 , PPC_INS_SYNC = 1102 , PPC_INS_TABORT = 1103 , PPC_INS_TABORTDC = 1104 , PPC_INS_TABORTDCI = 1105 , PPC_INS_TABORTWC = 1106 , PPC_INS_TABORTWCI = 1107 , PPC_INS_TBEGIN = 1108 , PPC_INS_TCHECK = 1109 , PPC_INS_TD = 1110 , PPC_INS_TDEQ = 1111 , PPC_INS_TDEQI = 1112 , PPC_INS_TDGE = 1113 , PPC_INS_TDGEI = 1114 , PPC_INS_TDGT = 1115 , PPC_INS_TDGTI = 1116 , PPC_INS_TDI = 1117 , PPC_INS_TDLE = 1118 , PPC_INS_TDLEI = 1119 , PPC_INS_TDLGE = 1120 , PPC_INS_TDLGEI = 1121 , PPC_INS_TDLGT = 1122 , PPC_INS_TDLGTI = 1123 , PPC_INS_TDLLE = 1124 , PPC_INS_TDLLEI = 1125 , PPC_INS_TDLLT = 1126 , PPC_INS_TDLLTI = 1127 , PPC_INS_TDLNG = 1128 , PPC_INS_TDLNGI = 1129 , PPC_INS_TDLNL = 1130 , PPC_INS_TDLNLI = 1131 , PPC_INS_TDLT = 1132 , PPC_INS_TDLTI = 1133 , PPC_INS_TDNE = 1134 , PPC_INS_TDNEI = 1135 , PPC_INS_TDNG = 1136 , PPC_INS_TDNGI = 1137 , PPC_INS_TDNL = 1138 , PPC_INS_TDNLI = 1139 , PPC_INS_TDU = 1140 , PPC_INS_TDUI = 1141 , PPC_INS_TEND = 1142 , PPC_INS_TLBIA = 1143 , PPC_INS_TLBIE = 1144 , PPC_INS_TLBIEL = 1145 , PPC_INS_TLBIVAX = 1146 , PPC_INS_TLBLD = 1147 , PPC_INS_TLBLI = 1148 , PPC_INS_TLBRE = 1149 , PPC_INS_TLBREHI = 1150 , PPC_INS_TLBRELO = 1151 , PPC_INS_TLBSX = 1152 , PPC_INS_TLBSYNC = 1153 , PPC_INS_TLBWE = 1154 , PPC_INS_TLBWEHI = 1155 , PPC_INS_TLBWELO = 1156 , PPC_INS_TRAP = 1157 , PPC_INS_TRECHKPT = 1158 , PPC_INS_TRECLAIM = 1159 , PPC_INS_TSR = 1160 , PPC_INS_TW = 1161 , PPC_INS_TWEQ = 1162 , PPC_INS_TWEQI = 1163 , PPC_INS_TWGE = 1164 , PPC_INS_TWGEI = 1165 , PPC_INS_TWGT = 1166 , PPC_INS_TWGTI = 1167 , PPC_INS_TWI = 1168 , PPC_INS_TWLE = 1169 , PPC_INS_TWLEI = 1170 , PPC_INS_TWLGE = 1171 , PPC_INS_TWLGEI = 1172 , PPC_INS_TWLGT = 1173 , PPC_INS_TWLGTI = 1174 , PPC_INS_TWLLE = 1175 , PPC_INS_TWLLEI = 1176 , PPC_INS_TWLLT = 1177 , PPC_INS_TWLLTI = 1178 , PPC_INS_TWLNG = 1179 , PPC_INS_TWLNGI = 1180 , PPC_INS_TWLNL = 1181 , PPC_INS_TWLNLI = 1182 , PPC_INS_TWLT = 1183 , PPC_INS_TWLTI = 1184 , PPC_INS_TWNE = 1185 , PPC_INS_TWNEI = 1186 , PPC_INS_TWNG = 1187 , PPC_INS_TWNGI = 1188 , PPC_INS_TWNL = 1189 , PPC_INS_TWNLI = 1190 , PPC_INS_TWU = 1191 , PPC_INS_TWUI = 1192 , PPC_INS_VABSDUB = 1193 , PPC_INS_VABSDUH = 1194 , PPC_INS_VABSDUW = 1195 , PPC_INS_VADDCUQ = 1196 , PPC_INS_VADDCUW = 1197 , PPC_INS_VADDECUQ = 1198 , PPC_INS_VADDEUQM = 1199 , PPC_INS_VADDFP = 1200 , PPC_INS_VADDSBS = 1201 , PPC_INS_VADDSHS = 1202 , PPC_INS_VADDSWS = 1203 , PPC_INS_VADDUBM = 1204 , PPC_INS_VADDUBS = 1205 , PPC_INS_VADDUDM = 1206 , PPC_INS_VADDUHM = 1207 , PPC_INS_VADDUHS = 1208 , PPC_INS_VADDUQM = 1209 , PPC_INS_VADDUWM = 1210 , PPC_INS_VADDUWS = 1211 , PPC_INS_VAND = 1212 , PPC_INS_VANDC = 1213 , PPC_INS_VAVGSB = 1214 , PPC_INS_VAVGSH = 1215 , PPC_INS_VAVGSW = 1216 , PPC_INS_VAVGUB = 1217 , PPC_INS_VAVGUH = 1218 , PPC_INS_VAVGUW = 1219 , PPC_INS_VBPERMD = 1220 , PPC_INS_VBPERMQ = 1221 , PPC_INS_VCFSX = 1222 , PPC_INS_VCFUX = 1223 , PPC_INS_VCIPHER = 1224 , PPC_INS_VCIPHERLAST = 1225 , PPC_INS_VCLZB = 1226 , PPC_INS_VCLZD = 1227 , PPC_INS_VCLZH = 1228 , PPC_INS_VCLZLSBB = 1229 , PPC_INS_VCLZW = 1230 , PPC_INS_VCMPBFP = 1231 , PPC_INS_VCMPEQFP = 1232 , PPC_INS_VCMPEQUB = 1233 , PPC_INS_VCMPEQUD = 1234 , PPC_INS_VCMPEQUH = 1235 , PPC_INS_VCMPEQUW = 1236 , PPC_INS_VCMPGEFP = 1237 , PPC_INS_VCMPGTFP = 1238 , PPC_INS_VCMPGTSB = 1239 , PPC_INS_VCMPGTSD = 1240 , PPC_INS_VCMPGTSH = 1241 , PPC_INS_VCMPGTSW = 1242 , PPC_INS_VCMPGTUB = 1243 , PPC_INS_VCMPGTUD = 1244 , PPC_INS_VCMPGTUH = 1245 , PPC_INS_VCMPGTUW = 1246 , PPC_INS_VCMPNEB = 1247 , PPC_INS_VCMPNEH = 1248 , PPC_INS_VCMPNEW = 1249 , PPC_INS_VCMPNEZB = 1250 , PPC_INS_VCMPNEZH = 1251 , PPC_INS_VCMPNEZW = 1252 , PPC_INS_VCTSXS = 1253 , PPC_INS_VCTUXS = 1254 , PPC_INS_VCTZB = 1255 , PPC_INS_VCTZD = 1256 , PPC_INS_VCTZH = 1257 , PPC_INS_VCTZLSBB = 1258 , PPC_INS_VCTZW = 1259 , PPC_INS_VEQV = 1260 , PPC_INS_VEXPTEFP = 1261 , PPC_INS_VEXTRACTD = 1262 , PPC_INS_VEXTRACTUB = 1263 , PPC_INS_VEXTRACTUH = 1264 , PPC_INS_VEXTRACTUW = 1265 , PPC_INS_VEXTSB2D = 1266 , PPC_INS_VEXTSB2W = 1267 , PPC_INS_VEXTSH2D = 1268 , PPC_INS_VEXTSH2W = 1269 , PPC_INS_VEXTSW2D = 1270 , PPC_INS_VEXTUBLX = 1271 , PPC_INS_VEXTUBRX = 1272 , PPC_INS_VEXTUHLX = 1273 , PPC_INS_VEXTUHRX = 1274 , PPC_INS_VEXTUWLX = 1275 , PPC_INS_VEXTUWRX = 1276 , PPC_INS_VGBBD = 1277 , PPC_INS_VINSERTB = 1278 , PPC_INS_VINSERTD = 1279 , PPC_INS_VINSERTH = 1280 , PPC_INS_VINSERTW = 1281 , PPC_INS_VLOGEFP = 1282 , PPC_INS_VMADDFP = 1283 , PPC_INS_VMAXFP = 1284 , PPC_INS_VMAXSB = 1285 , PPC_INS_VMAXSD = 1286 , PPC_INS_VMAXSH = 1287 , PPC_INS_VMAXSW = 1288 , PPC_INS_VMAXUB = 1289 , PPC_INS_VMAXUD = 1290 , PPC_INS_VMAXUH = 1291 , PPC_INS_VMAXUW = 1292 , PPC_INS_VMHADDSHS = 1293 , PPC_INS_VMHRADDSHS = 1294 , PPC_INS_VMINFP = 1295 , PPC_INS_VMINSB = 1296 , PPC_INS_VMINSD = 1297 , PPC_INS_VMINSH = 1298 , PPC_INS_VMINSW = 1299 , PPC_INS_VMINUB = 1300 , PPC_INS_VMINUD = 1301 , PPC_INS_VMINUH = 1302 , PPC_INS_VMINUW = 1303 , PPC_INS_VMLADDUHM = 1304 , PPC_INS_VMR = 1305 , PPC_INS_VMRGEW = 1306 , PPC_INS_VMRGHB = 1307 , PPC_INS_VMRGHH = 1308 , PPC_INS_VMRGHW = 1309 , PPC_INS_VMRGLB = 1310 , PPC_INS_VMRGLH = 1311 , PPC_INS_VMRGLW = 1312 , PPC_INS_VMRGOW = 1313 , PPC_INS_VMSUMMBM = 1314 , PPC_INS_VMSUMSHM = 1315 , PPC_INS_VMSUMSHS = 1316 , PPC_INS_VMSUMUBM = 1317 , PPC_INS_VMSUMUHM = 1318 , PPC_INS_VMSUMUHS = 1319 , PPC_INS_VMUL10CUQ = 1320 , PPC_INS_VMUL10ECUQ = 1321 , PPC_INS_VMUL10EUQ = 1322 , PPC_INS_VMUL10UQ = 1323 , PPC_INS_VMULESB = 1324 , PPC_INS_VMULESH = 1325 , PPC_INS_VMULESW = 1326 , PPC_INS_VMULEUB = 1327 , PPC_INS_VMULEUH = 1328 , PPC_INS_VMULEUW = 1329 , PPC_INS_VMULOSB = 1330 , PPC_INS_VMULOSH = 1331 , PPC_INS_VMULOSW = 1332 , PPC_INS_VMULOUB = 1333 , PPC_INS_VMULOUH = 1334 , PPC_INS_VMULOUW = 1335 , PPC_INS_VMULUWM = 1336 , PPC_INS_VNAND = 1337 , PPC_INS_VNCIPHER = 1338 , PPC_INS_VNCIPHERLAST = 1339 , PPC_INS_VNEGD = 1340 , PPC_INS_VNEGW = 1341 , PPC_INS_VNMSUBFP = 1342 , PPC_INS_VNOR = 1343 , PPC_INS_VNOT = 1344 , PPC_INS_VOR = 1345 , PPC_INS_VORC = 1346 , PPC_INS_VPERM = 1347 , PPC_INS_VPERMR = 1348 , PPC_INS_VPERMXOR = 1349 , PPC_INS_VPKPX = 1350 , PPC_INS_VPKSDSS = 1351 , PPC_INS_VPKSDUS = 1352 , PPC_INS_VPKSHSS = 1353 , PPC_INS_VPKSHUS = 1354 , PPC_INS_VPKSWSS = 1355 , PPC_INS_VPKSWUS = 1356 , PPC_INS_VPKUDUM = 1357 , PPC_INS_VPKUDUS = 1358 , PPC_INS_VPKUHUM = 1359 , PPC_INS_VPKUHUS = 1360 , PPC_INS_VPKUWUM = 1361 , PPC_INS_VPKUWUS = 1362 , PPC_INS_VPMSUMB = 1363 , PPC_INS_VPMSUMD = 1364 , PPC_INS_VPMSUMH = 1365 , PPC_INS_VPMSUMW = 1366 , PPC_INS_VPOPCNTB = 1367 , PPC_INS_VPOPCNTD = 1368 , PPC_INS_VPOPCNTH = 1369 , PPC_INS_VPOPCNTW = 1370 , PPC_INS_VPRTYBD = 1371 , PPC_INS_VPRTYBQ = 1372 , PPC_INS_VPRTYBW = 1373 , PPC_INS_VREFP = 1374 , PPC_INS_VRFIM = 1375 , PPC_INS_VRFIN = 1376 , PPC_INS_VRFIP = 1377 , PPC_INS_VRFIZ = 1378 , PPC_INS_VRLB = 1379 , PPC_INS_VRLD = 1380 , PPC_INS_VRLDMI = 1381 , PPC_INS_VRLDNM = 1382 , PPC_INS_VRLH = 1383 , PPC_INS_VRLW = 1384 , PPC_INS_VRLWMI = 1385 , PPC_INS_VRLWNM = 1386 , PPC_INS_VRSQRTEFP = 1387 , PPC_INS_VSBOX = 1388 , PPC_INS_VSEL = 1389 , PPC_INS_VSHASIGMAD = 1390 , PPC_INS_VSHASIGMAW = 1391 , PPC_INS_VSL = 1392 , PPC_INS_VSLB = 1393 , PPC_INS_VSLD = 1394 , PPC_INS_VSLDOI = 1395 , PPC_INS_VSLH = 1396 , PPC_INS_VSLO = 1397 , PPC_INS_VSLV = 1398 , PPC_INS_VSLW = 1399 , PPC_INS_VSPLTB = 1400 , PPC_INS_VSPLTH = 1401 , PPC_INS_VSPLTISB = 1402 , PPC_INS_VSPLTISH = 1403 , PPC_INS_VSPLTISW = 1404 , PPC_INS_VSPLTW = 1405 , PPC_INS_VSR = 1406 , PPC_INS_VSRAB = 1407 , PPC_INS_VSRAD = 1408 , PPC_INS_VSRAH = 1409 , PPC_INS_VSRAW = 1410 , PPC_INS_VSRB = 1411 , PPC_INS_VSRD = 1412 , PPC_INS_VSRH = 1413 , PPC_INS_VSRO = 1414 , PPC_INS_VSRV = 1415 , PPC_INS_VSRW = 1416 , PPC_INS_VSUBCUQ = 1417 , PPC_INS_VSUBCUW = 1418 , PPC_INS_VSUBECUQ = 1419 , PPC_INS_VSUBEUQM = 1420 , PPC_INS_VSUBFP = 1421 , PPC_INS_VSUBSBS = 1422 , PPC_INS_VSUBSHS = 1423 , PPC_INS_VSUBSWS = 1424 , PPC_INS_VSUBUBM = 1425 , PPC_INS_VSUBUBS = 1426 , PPC_INS_VSUBUDM = 1427 , PPC_INS_VSUBUHM = 1428 , PPC_INS_VSUBUHS = 1429 , PPC_INS_VSUBUQM = 1430 , PPC_INS_VSUBUWM = 1431 , PPC_INS_VSUBUWS = 1432 , PPC_INS_VSUM2SWS = 1433 , PPC_INS_VSUM4SBS = 1434 , PPC_INS_VSUM4SHS = 1435 , PPC_INS_VSUM4UBS = 1436 , PPC_INS_VSUMSWS = 1437 , PPC_INS_VUPKHPX = 1438 , PPC_INS_VUPKHSB = 1439 , PPC_INS_VUPKHSH = 1440 , PPC_INS_VUPKHSW = 1441 , PPC_INS_VUPKLPX = 1442 , PPC_INS_VUPKLSB = 1443 , PPC_INS_VUPKLSH = 1444 , PPC_INS_VUPKLSW = 1445 , PPC_INS_VXOR = 1446 , PPC_INS_WAIT = 1447 , PPC_INS_WAITIMPL = 1448 , PPC_INS_WAITRSV = 1449 , PPC_INS_WRTEE = 1450 , PPC_INS_WRTEEI = 1451 , PPC_INS_XNOP = 1452 , PPC_INS_XOR = 1453 , PPC_INS_XORI = 1454 , PPC_INS_XORIS = 1455 , PPC_INS_XSABSDP = 1456 , PPC_INS_XSABSQP = 1457 , PPC_INS_XSADDDP = 1458 , PPC_INS_XSADDQP = 1459 , PPC_INS_XSADDQPO = 1460 , PPC_INS_XSADDSP = 1461 , PPC_INS_XSCMPEQDP = 1462 , PPC_INS_XSCMPEXPDP = 1463 , PPC_INS_XSCMPEXPQP = 1464 , PPC_INS_XSCMPGEDP = 1465 , PPC_INS_XSCMPGTDP = 1466 , PPC_INS_XSCMPODP = 1467 , PPC_INS_XSCMPOQP = 1468 , PPC_INS_XSCMPUDP = 1469 , PPC_INS_XSCMPUQP = 1470 , PPC_INS_XSCPSGNDP = 1471 , PPC_INS_XSCPSGNQP = 1472 , PPC_INS_XSCVDPHP = 1473 , PPC_INS_XSCVDPQP = 1474 , PPC_INS_XSCVDPSP = 1475 , PPC_INS_XSCVDPSPN = 1476 , PPC_INS_XSCVDPSXDS = 1477 , PPC_INS_XSCVDPSXWS = 1478 , PPC_INS_XSCVDPUXDS = 1479 , PPC_INS_XSCVDPUXWS = 1480 , PPC_INS_XSCVHPDP = 1481 , PPC_INS_XSCVQPDP = 1482 , PPC_INS_XSCVQPDPO = 1483 , PPC_INS_XSCVQPSDZ = 1484 , PPC_INS_XSCVQPSWZ = 1485 , PPC_INS_XSCVQPUDZ = 1486 , PPC_INS_XSCVQPUWZ = 1487 , PPC_INS_XSCVSDQP = 1488 , PPC_INS_XSCVSPDP = 1489 , PPC_INS_XSCVSPDPN = 1490 , PPC_INS_XSCVSXDDP = 1491 , PPC_INS_XSCVSXDSP = 1492 , PPC_INS_XSCVUDQP = 1493 , PPC_INS_XSCVUXDDP = 1494 , PPC_INS_XSCVUXDSP = 1495 , PPC_INS_XSDIVDP = 1496 , PPC_INS_XSDIVQP = 1497 , PPC_INS_XSDIVQPO = 1498 , PPC_INS_XSDIVSP = 1499 , PPC_INS_XSIEXPDP = 1500 , PPC_INS_XSIEXPQP = 1501 , PPC_INS_XSMADDADP = 1502 , PPC_INS_XSMADDASP = 1503 , PPC_INS_XSMADDMDP = 1504 , PPC_INS_XSMADDMSP = 1505 , PPC_INS_XSMADDQP = 1506 , PPC_INS_XSMADDQPO = 1507 , PPC_INS_XSMAXCDP = 1508 , PPC_INS_XSMAXDP = 1509 , PPC_INS_XSMAXJDP = 1510 , PPC_INS_XSMINCDP = 1511 , PPC_INS_XSMINDP = 1512 , PPC_INS_XSMINJDP = 1513 , PPC_INS_XSMSUBADP = 1514 , PPC_INS_XSMSUBASP = 1515 , PPC_INS_XSMSUBMDP = 1516 , PPC_INS_XSMSUBMSP = 1517 , PPC_INS_XSMSUBQP = 1518 , PPC_INS_XSMSUBQPO = 1519 , PPC_INS_XSMULDP = 1520 , PPC_INS_XSMULQP = 1521 , PPC_INS_XSMULQPO = 1522 , PPC_INS_XSMULSP = 1523 , PPC_INS_XSNABSDP = 1524 , PPC_INS_XSNABSQP = 1525 , PPC_INS_XSNEGDP = 1526 , PPC_INS_XSNEGQP = 1527 , PPC_INS_XSNMADDADP = 1528 , PPC_INS_XSNMADDASP = 1529 , PPC_INS_XSNMADDMDP = 1530 , PPC_INS_XSNMADDMSP = 1531 , PPC_INS_XSNMADDQP = 1532 , PPC_INS_XSNMADDQPO = 1533 , PPC_INS_XSNMSUBADP = 1534 , PPC_INS_XSNMSUBASP = 1535 , PPC_INS_XSNMSUBMDP = 1536 , PPC_INS_XSNMSUBMSP = 1537 , PPC_INS_XSNMSUBQP = 1538 , PPC_INS_XSNMSUBQPO = 1539 , PPC_INS_XSRDPI = 1540 , PPC_INS_XSRDPIC = 1541 , PPC_INS_XSRDPIM = 1542 , PPC_INS_XSRDPIP = 1543 , PPC_INS_XSRDPIZ = 1544 , PPC_INS_XSREDP = 1545 , PPC_INS_XSRESP = 1546 , PPC_INS_XSRQPI = 1547 , PPC_INS_XSRQPIX = 1548 , PPC_INS_XSRQPXP = 1549 , PPC_INS_XSRSP = 1550 , PPC_INS_XSRSQRTEDP = 1551 , PPC_INS_XSRSQRTESP = 1552 , PPC_INS_XSSQRTDP = 1553 , PPC_INS_XSSQRTQP = 1554 , PPC_INS_XSSQRTQPO = 1555 , PPC_INS_XSSQRTSP = 1556 , PPC_INS_XSSUBDP = 1557 , PPC_INS_XSSUBQP = 1558 , PPC_INS_XSSUBQPO = 1559 , PPC_INS_XSSUBSP = 1560 , PPC_INS_XSTDIVDP = 1561 , PPC_INS_XSTSQRTDP = 1562 , PPC_INS_XSTSTDCDP = 1563 , PPC_INS_XSTSTDCQP = 1564 , PPC_INS_XSTSTDCSP = 1565 , PPC_INS_XSXEXPDP = 1566 , PPC_INS_XSXEXPQP = 1567 , PPC_INS_XSXSIGDP = 1568 , PPC_INS_XSXSIGQP = 1569 , PPC_INS_XVABSDP = 1570 , PPC_INS_XVABSSP = 1571 , PPC_INS_XVADDDP = 1572 , PPC_INS_XVADDSP = 1573 , PPC_INS_XVCMPEQDP = 1574 , PPC_INS_XVCMPEQSP = 1575 , PPC_INS_XVCMPGEDP = 1576 , PPC_INS_XVCMPGESP = 1577 , PPC_INS_XVCMPGTDP = 1578 , PPC_INS_XVCMPGTSP = 1579 , PPC_INS_XVCPSGNDP = 1580 , PPC_INS_XVCPSGNSP = 1581 , PPC_INS_XVCVDPSP = 1582 , PPC_INS_XVCVDPSXDS = 1583 , PPC_INS_XVCVDPSXWS = 1584 , PPC_INS_XVCVDPUXDS = 1585 , PPC_INS_XVCVDPUXWS = 1586 , PPC_INS_XVCVHPSP = 1587 , PPC_INS_XVCVSPDP = 1588 , PPC_INS_XVCVSPHP = 1589 , PPC_INS_XVCVSPSXDS = 1590 , PPC_INS_XVCVSPSXWS = 1591 , PPC_INS_XVCVSPUXDS = 1592 , PPC_INS_XVCVSPUXWS = 1593 , PPC_INS_XVCVSXDDP = 1594 , PPC_INS_XVCVSXDSP = 1595 , PPC_INS_XVCVSXWDP = 1596 , PPC_INS_XVCVSXWSP = 1597 , PPC_INS_XVCVUXDDP = 1598 , PPC_INS_XVCVUXDSP = 1599 , PPC_INS_XVCVUXWDP = 1600 , PPC_INS_XVCVUXWSP = 1601 , PPC_INS_XVDIVDP = 1602 , PPC_INS_XVDIVSP = 1603 , PPC_INS_XVIEXPDP = 1604 , PPC_INS_XVIEXPSP = 1605 , PPC_INS_XVMADDADP = 1606 , PPC_INS_XVMADDASP = 1607 , PPC_INS_XVMADDMDP = 1608 , PPC_INS_XVMADDMSP = 1609 , PPC_INS_XVMAXDP = 1610 , PPC_INS_XVMAXSP = 1611 , PPC_INS_XVMINDP = 1612 , PPC_INS_XVMINSP = 1613 , PPC_INS_XVMOVDP = 1614 , PPC_INS_XVMOVSP = 1615 , PPC_INS_XVMSUBADP = 1616 , PPC_INS_XVMSUBASP = 1617 , PPC_INS_XVMSUBMDP = 1618 , PPC_INS_XVMSUBMSP = 1619 , PPC_INS_XVMULDP = 1620 , PPC_INS_XVMULSP = 1621 , PPC_INS_XVNABSDP = 1622 , PPC_INS_XVNABSSP = 1623 , PPC_INS_XVNEGDP = 1624 , PPC_INS_XVNEGSP = 1625 , PPC_INS_XVNMADDADP = 1626 , PPC_INS_XVNMADDASP = 1627 , PPC_INS_XVNMADDMDP = 1628 , PPC_INS_XVNMADDMSP = 1629 , PPC_INS_XVNMSUBADP = 1630 , PPC_INS_XVNMSUBASP = 1631 , PPC_INS_XVNMSUBMDP = 1632 , PPC_INS_XVNMSUBMSP = 1633 , PPC_INS_XVRDPI = 1634 , PPC_INS_XVRDPIC = 1635 , PPC_INS_XVRDPIM = 1636 , PPC_INS_XVRDPIP = 1637 , PPC_INS_XVRDPIZ = 1638 , PPC_INS_XVREDP = 1639 , PPC_INS_XVRESP = 1640 , PPC_INS_XVRSPI = 1641 , PPC_INS_XVRSPIC = 1642 , PPC_INS_XVRSPIM = 1643 , PPC_INS_XVRSPIP = 1644 , PPC_INS_XVRSPIZ = 1645 , PPC_INS_XVRSQRTEDP = 1646 , PPC_INS_XVRSQRTESP = 1647 , PPC_INS_XVSQRTDP = 1648 , PPC_INS_XVSQRTSP = 1649 , PPC_INS_XVSUBDP = 1650 , PPC_INS_XVSUBSP = 1651 , PPC_INS_XVTDIVDP = 1652 , PPC_INS_XVTDIVSP = 1653 , PPC_INS_XVTSQRTDP = 1654 , PPC_INS_XVTSQRTSP = 1655 , PPC_INS_XVTSTDCDP = 1656 , PPC_INS_XVTSTDCSP = 1657 , PPC_INS_XVXEXPDP = 1658 , PPC_INS_XVXEXPSP = 1659 , PPC_INS_XVXSIGDP = 1660 , PPC_INS_XVXSIGSP = 1661 , PPC_INS_XXBRD = 1662 , PPC_INS_XXBRH = 1663 , PPC_INS_XXBRQ = 1664 , PPC_INS_XXBRW = 1665 , PPC_INS_XXEXTRACTUW = 1666 , PPC_INS_XXINSERTW = 1667 , PPC_INS_XXLAND = 1668 , PPC_INS_XXLANDC = 1669 , PPC_INS_XXLEQV = 1670 , PPC_INS_XXLNAND = 1671 , PPC_INS_XXLNOR = 1672 , PPC_INS_XXLOR = 1673 , PPC_INS_XXLORC = 1674 , PPC_INS_XXLXOR = 1675 , PPC_INS_XXMRGHD = 1676 , PPC_INS_XXMRGHW = 1677 , PPC_INS_XXMRGLD = 1678 , PPC_INS_XXMRGLW = 1679 , PPC_INS_XXPERM = 1680 , PPC_INS_XXPERMDI = 1681 , PPC_INS_XXPERMR = 1682 , PPC_INS_XXSEL = 1683 , PPC_INS_XXSLDWI = 1684 , PPC_INS_XXSPLTD = 1685 , PPC_INS_XXSPLTIB = 1686 , PPC_INS_XXSPLTW = 1687 , PPC_INS_XXSWAPD = 1688 , PPC_INS_DCBZ_L = 1689 , PPC_INS_PSQ_L = 1690 , PPC_INS_PSQ_LU = 1691 , PPC_INS_PSQ_LUX = 1692 , PPC_INS_PSQ_LX = 1693 , PPC_INS_PSQ_ST = 1694 , PPC_INS_PSQ_STU = 1695 , PPC_INS_PSQ_STUX = 1696 , PPC_INS_PSQ_STX = 1697 , PPC_INS_PS_ABS = 1698 , PPC_INS_PS_ADD = 1699 , PPC_INS_PS_CMPO0 = 1700 , PPC_INS_PS_CMPO1 = 1701 , PPC_INS_PS_CMPU0 = 1702 , PPC_INS_PS_CMPU1 = 1703 , PPC_INS_PS_DIV = 1704 , PPC_INS_PS_MADD = 1705 , PPC_INS_PS_MADDS0 = 1706 , PPC_INS_PS_MADDS1 = 1707 , PPC_INS_PS_MERGE00 = 1708 , PPC_INS_PS_MERGE01 = 1709 , PPC_INS_PS_MERGE10 = 1710 , PPC_INS_PS_MERGE11 = 1711 , PPC_INS_PS_MR = 1712 , PPC_INS_PS_MSUB = 1713 , PPC_INS_PS_MUL = 1714 , PPC_INS_PS_MULS0 = 1715 , PPC_INS_PS_MULS1 = 1716 , PPC_INS_PS_NABS = 1717 , PPC_INS_PS_NEG = 1718 , PPC_INS_PS_NMADD = 1719 , PPC_INS_PS_NMSUB = 1720 , PPC_INS_PS_RES = 1721 , PPC_INS_PS_RSQRTE = 1722 , PPC_INS_PS_SEL = 1723 , PPC_INS_PS_SUB = 1724 , PPC_INS_PS_SUM0 = 1725 , PPC_INS_PS_SUM1 = 1726 , PPC_INS_ENDING = 1727 , } # [repr (u32)] # [doc = " Group of PPC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn_group { # [doc = "< = CS_GRP_INVALID"] PPC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] PPC_GRP_JUMP = 1 , PPC_GRP_ALTIVEC = 128 , PPC_GRP_MODE32 = 129 , PPC_GRP_MODE64 = 130 , PPC_GRP_BOOKE = 131 , PPC_GRP_NOTBOOKE = 132 , PPC_GRP_SPE = 133 , PPC_GRP_VSX = 134 , PPC_GRP_E500 = 135 , PPC_GRP_PPC4XX = 136 , PPC_GRP_PPC6XX = 137 , PPC_GRP_ICBT = 138 , PPC_GRP_P8ALTIVEC = 139 , PPC_GRP_P8VECTOR = 140 , PPC_GRP_QPX = 141 , PPC_GRP_PS = 142 , PPC_GRP_ENDING = 143 , } # [repr (u32)] # [doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_cc { # [doc = "< invalid CC (default)"] SPARC_CC_INVALID = 0 , # [doc = "< Always"] SPARC_CC_ICC_A = 264 , # [doc = "< Never"] SPARC_CC_ICC_N = 256 , # [doc = "< Not Equal"] SPARC_CC_ICC_NE = 265 , # [doc = "< Equal"] SPARC_CC_ICC_E = 257 , # [doc = "< Greater"] SPARC_CC_ICC_G = 266 , # [doc = "< Less or Equal"] SPARC_CC_ICC_LE = 258 , # [doc = "< Greater or Equal"] SPARC_CC_ICC_GE = 267 , # [doc = "< Less"] SPARC_CC_ICC_L = 259 , # [doc = "< Greater Unsigned"] SPARC_CC_ICC_GU = 268 , # [doc = "< Less or Equal Unsigned"] SPARC_CC_ICC_LEU = 260 , # [doc = "< Carry Clear/Great or Equal Unsigned"] SPARC_CC_ICC_CC = 269 , # [doc = "< Carry Set/Less Unsigned"] SPARC_CC_ICC_CS = 261 , # [doc = "< Positive"] SPARC_CC_ICC_POS = 270 , # [doc = "< Negative"] SPARC_CC_ICC_NEG = 262 , # [doc = "< Overflow Clear"] SPARC_CC_ICC_VC = 271 , # [doc = "< Overflow Set"] SPARC_CC_ICC_VS = 263 , # [doc = "< Always"] SPARC_CC_FCC_A = 280 , # [doc = "< Never"] SPARC_CC_FCC_N = 272 , # [doc = "< Unordered"] SPARC_CC_FCC_U = 279 , # [doc = "< Greater"] SPARC_CC_FCC_G = 278 , # [doc = "< Unordered or Greater"] SPARC_CC_FCC_UG = 277 , # [doc = "< Less"] SPARC_CC_FCC_L = 276 , # [doc = "< Unordered or Less"] SPARC_CC_FCC_UL = 275 , # [doc = "< Less or Greater"] SPARC_CC_FCC_LG = 274 , # [doc = "< Not Equal"] SPARC_CC_FCC_NE = 273 , # [doc = "< Equal"] SPARC_CC_FCC_E = 281 , # [doc = "< Unordered or Equal"] SPARC_CC_FCC_UE = 282 , # [doc = "< Greater or Equal"] SPARC_CC_FCC_GE = 283 , # [doc = "< Unordered or Greater or Equal"] SPARC_CC_FCC_UGE = 284 , # [doc = "< Less or Equal"] SPARC_CC_FCC_LE = 285 , # [doc = "< Unordered or Less or Equal"] SPARC_CC_FCC_ULE = 286 , # [doc = "< Ordered"] SPARC_CC_FCC_O = 287 , } # [repr (u32)] # [doc = " Branch hint"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_hint { # [doc = "< no hint"] SPARC_HINT_INVALID = 0 , # [doc = "< annul delay slot instruction"] SPARC_HINT_A = 1 , # [doc = "< branch taken"] SPARC_HINT_PT = 2 , # [doc = "< branch NOT taken"] SPARC_HINT_PN = 4 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SPARC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SPARC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SPARC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SPARC_OP_MEM = 3 , } impl sparc_reg { pub const SPARC_REG_O6 : sparc_reg = sparc_reg :: SPARC_REG_SP ; } impl sparc_reg { pub const SPARC_REG_I6 : sparc_reg = sparc_reg :: SPARC_REG_FP ; } # [repr (u32)] # [doc = " SPARC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_reg { SPARC_REG_INVALID = 0 , SPARC_REG_F0 = 1 , SPARC_REG_F1 = 2 , SPARC_REG_F2 = 3 , SPARC_REG_F3 = 4 , SPARC_REG_F4 = 5 , SPARC_REG_F5 = 6 , SPARC_REG_F6 = 7 , SPARC_REG_F7 = 8 , SPARC_REG_F8 = 9 , SPARC_REG_F9 = 10 , SPARC_REG_F10 = 11 , SPARC_REG_F11 = 12 , SPARC_REG_F12 = 13 , SPARC_REG_F13 = 14 , SPARC_REG_F14 = 15 , SPARC_REG_F15 = 16 , SPARC_REG_F16 = 17 , SPARC_REG_F17 = 18 , SPARC_REG_F18 = 19 , SPARC_REG_F19 = 20 , SPARC_REG_F20 = 21 , SPARC_REG_F21 = 22 , SPARC_REG_F22 = 23 , SPARC_REG_F23 = 24 , SPARC_REG_F24 = 25 , SPARC_REG_F25 = 26 , SPARC_REG_F26 = 27 , SPARC_REG_F27 = 28 , SPARC_REG_F28 = 29 , SPARC_REG_F29 = 30 , SPARC_REG_F30 = 31 , SPARC_REG_F31 = 32 , SPARC_REG_F32 = 33 , SPARC_REG_F34 = 34 , SPARC_REG_F36 = 35 , SPARC_REG_F38 = 36 , SPARC_REG_F40 = 37 , SPARC_REG_F42 = 38 , SPARC_REG_F44 = 39 , SPARC_REG_F46 = 40 , SPARC_REG_F48 = 41 , SPARC_REG_F50 = 42 , SPARC_REG_F52 = 43 , SPARC_REG_F54 = 44 , SPARC_REG_F56 = 45 , SPARC_REG_F58 = 46 , SPARC_REG_F60 = 47 , SPARC_REG_F62 = 48 , SPARC_REG_FCC0 = 49 , SPARC_REG_FCC1 = 50 , SPARC_REG_FCC2 = 51 , SPARC_REG_FCC3 = 52 , SPARC_REG_FP = 53 , SPARC_REG_G0 = 54 , SPARC_REG_G1 = 55 , SPARC_REG_G2 = 56 , SPARC_REG_G3 = 57 , SPARC_REG_G4 = 58 , SPARC_REG_G5 = 59 , SPARC_REG_G6 = 60 , SPARC_REG_G7 = 61 , SPARC_REG_I0 = 62 , SPARC_REG_I1 = 63 , SPARC_REG_I2 = 64 , SPARC_REG_I3 = 65 , SPARC_REG_I4 = 66 , SPARC_REG_I5 = 67 , SPARC_REG_I7 = 68 , SPARC_REG_ICC = 69 , SPARC_REG_L0 = 70 , SPARC_REG_L1 = 71 , SPARC_REG_L2 = 72 , SPARC_REG_L3 = 73 , SPARC_REG_L4 = 74 , SPARC_REG_L5 = 75 , SPARC_REG_L6 = 76 , SPARC_REG_L7 = 77 , SPARC_REG_O0 = 78 , SPARC_REG_O1 = 79 , SPARC_REG_O2 = 80 , SPARC_REG_O3 = 81 , SPARC_REG_O4 = 82 , SPARC_REG_O5 = 83 , SPARC_REG_O7 = 84 , SPARC_REG_SP = 85 , SPARC_REG_Y = 86 , SPARC_REG_XCC = 87 , SPARC_REG_ENDING = 88 , } # [doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sparc_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sparc_op_mem"] [:: std :: mem :: size_of :: < sparc_op_mem > () - 8usize] ; ["Alignment of sparc_op_mem"] [:: std :: mem :: align_of :: < sparc_op_mem > () - 4usize] ; ["Offset of field: sparc_op_mem::base"] [:: std :: mem :: offset_of ! (sparc_op_mem , base) - 0usize] ; ["Offset of field: sparc_op_mem::index"] [:: std :: mem :: offset_of ! (sparc_op_mem , index) - 1usize] ; ["Offset of field: sparc_op_mem::disp"] [:: std :: mem :: offset_of ! (sparc_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc_op { # [doc = "< operand type"] pub type_ : sparc_op_type , pub __bindgen_anon_1 : cs_sparc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sparc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sparc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sparc_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op"] [:: std :: mem :: size_of :: < cs_sparc_op > () - 16usize] ; ["Alignment of cs_sparc_op"] [:: std :: mem :: align_of :: < cs_sparc_op > () - 8usize] ; ["Offset of field: cs_sparc_op::type_"] [:: std :: mem :: offset_of ! (cs_sparc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc { # [doc = "< code condition for this insn"] pub cc : sparc_cc , # [doc = "< branch hint: encoding as bitwise OR of sparc_hint."] pub hint : sparc_hint , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sparc_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc"] [:: std :: mem :: size_of :: < cs_sparc > () - 80usize] ; ["Alignment of cs_sparc"] [:: std :: mem :: align_of :: < cs_sparc > () - 8usize] ; ["Offset of field: cs_sparc::cc"] [:: std :: mem :: offset_of ! (cs_sparc , cc) - 0usize] ; ["Offset of field: cs_sparc::hint"] [:: std :: mem :: offset_of ! (cs_sparc , hint) - 4usize] ; ["Offset of field: cs_sparc::op_count"] [:: std :: mem :: offset_of ! (cs_sparc , op_count) - 8usize] ; ["Offset of field: cs_sparc::operands"] [:: std :: mem :: offset_of ! (cs_sparc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . hint , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SPARC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn { SPARC_INS_INVALID = 0 , SPARC_INS_ADDCC = 1 , SPARC_INS_ADDX = 2 , SPARC_INS_ADDXCC = 3 , SPARC_INS_ADDXC = 4 , SPARC_INS_ADDXCCC = 5 , SPARC_INS_ADD = 6 , SPARC_INS_ALIGNADDR = 7 , SPARC_INS_ALIGNADDRL = 8 , SPARC_INS_ANDCC = 9 , SPARC_INS_ANDNCC = 10 , SPARC_INS_ANDN = 11 , SPARC_INS_AND = 12 , SPARC_INS_ARRAY16 = 13 , SPARC_INS_ARRAY32 = 14 , SPARC_INS_ARRAY8 = 15 , SPARC_INS_B = 16 , SPARC_INS_JMP = 17 , SPARC_INS_BMASK = 18 , SPARC_INS_FB = 19 , SPARC_INS_BRGEZ = 20 , SPARC_INS_BRGZ = 21 , SPARC_INS_BRLEZ = 22 , SPARC_INS_BRLZ = 23 , SPARC_INS_BRNZ = 24 , SPARC_INS_BRZ = 25 , SPARC_INS_BSHUFFLE = 26 , SPARC_INS_CALL = 27 , SPARC_INS_CASX = 28 , SPARC_INS_CAS = 29 , SPARC_INS_CMASK16 = 30 , SPARC_INS_CMASK32 = 31 , SPARC_INS_CMASK8 = 32 , SPARC_INS_CMP = 33 , SPARC_INS_EDGE16 = 34 , SPARC_INS_EDGE16L = 35 , SPARC_INS_EDGE16LN = 36 , SPARC_INS_EDGE16N = 37 , SPARC_INS_EDGE32 = 38 , SPARC_INS_EDGE32L = 39 , SPARC_INS_EDGE32LN = 40 , SPARC_INS_EDGE32N = 41 , SPARC_INS_EDGE8 = 42 , SPARC_INS_EDGE8L = 43 , SPARC_INS_EDGE8LN = 44 , SPARC_INS_EDGE8N = 45 , SPARC_INS_FABSD = 46 , SPARC_INS_FABSQ = 47 , SPARC_INS_FABSS = 48 , SPARC_INS_FADDD = 49 , SPARC_INS_FADDQ = 50 , SPARC_INS_FADDS = 51 , SPARC_INS_FALIGNDATA = 52 , SPARC_INS_FAND = 53 , SPARC_INS_FANDNOT1 = 54 , SPARC_INS_FANDNOT1S = 55 , SPARC_INS_FANDNOT2 = 56 , SPARC_INS_FANDNOT2S = 57 , SPARC_INS_FANDS = 58 , SPARC_INS_FCHKSM16 = 59 , SPARC_INS_FCMPD = 60 , SPARC_INS_FCMPEQ16 = 61 , SPARC_INS_FCMPEQ32 = 62 , SPARC_INS_FCMPGT16 = 63 , SPARC_INS_FCMPGT32 = 64 , SPARC_INS_FCMPLE16 = 65 , SPARC_INS_FCMPLE32 = 66 , SPARC_INS_FCMPNE16 = 67 , SPARC_INS_FCMPNE32 = 68 , SPARC_INS_FCMPQ = 69 , SPARC_INS_FCMPS = 70 , SPARC_INS_FDIVD = 71 , SPARC_INS_FDIVQ = 72 , SPARC_INS_FDIVS = 73 , SPARC_INS_FDMULQ = 74 , SPARC_INS_FDTOI = 75 , SPARC_INS_FDTOQ = 76 , SPARC_INS_FDTOS = 77 , SPARC_INS_FDTOX = 78 , SPARC_INS_FEXPAND = 79 , SPARC_INS_FHADDD = 80 , SPARC_INS_FHADDS = 81 , SPARC_INS_FHSUBD = 82 , SPARC_INS_FHSUBS = 83 , SPARC_INS_FITOD = 84 , SPARC_INS_FITOQ = 85 , SPARC_INS_FITOS = 86 , SPARC_INS_FLCMPD = 87 , SPARC_INS_FLCMPS = 88 , SPARC_INS_FLUSHW = 89 , SPARC_INS_FMEAN16 = 90 , SPARC_INS_FMOVD = 91 , SPARC_INS_FMOVQ = 92 , SPARC_INS_FMOVRDGEZ = 93 , SPARC_INS_FMOVRQGEZ = 94 , SPARC_INS_FMOVRSGEZ = 95 , SPARC_INS_FMOVRDGZ = 96 , SPARC_INS_FMOVRQGZ = 97 , SPARC_INS_FMOVRSGZ = 98 , SPARC_INS_FMOVRDLEZ = 99 , SPARC_INS_FMOVRQLEZ = 100 , SPARC_INS_FMOVRSLEZ = 101 , SPARC_INS_FMOVRDLZ = 102 , SPARC_INS_FMOVRQLZ = 103 , SPARC_INS_FMOVRSLZ = 104 , SPARC_INS_FMOVRDNZ = 105 , SPARC_INS_FMOVRQNZ = 106 , SPARC_INS_FMOVRSNZ = 107 , SPARC_INS_FMOVRDZ = 108 , SPARC_INS_FMOVRQZ = 109 , SPARC_INS_FMOVRSZ = 110 , SPARC_INS_FMOVS = 111 , SPARC_INS_FMUL8SUX16 = 112 , SPARC_INS_FMUL8ULX16 = 113 , SPARC_INS_FMUL8X16 = 114 , SPARC_INS_FMUL8X16AL = 115 , SPARC_INS_FMUL8X16AU = 116 , SPARC_INS_FMULD = 117 , SPARC_INS_FMULD8SUX16 = 118 , SPARC_INS_FMULD8ULX16 = 119 , SPARC_INS_FMULQ = 120 , SPARC_INS_FMULS = 121 , SPARC_INS_FNADDD = 122 , SPARC_INS_FNADDS = 123 , SPARC_INS_FNAND = 124 , SPARC_INS_FNANDS = 125 , SPARC_INS_FNEGD = 126 , SPARC_INS_FNEGQ = 127 , SPARC_INS_FNEGS = 128 , SPARC_INS_FNHADDD = 129 , SPARC_INS_FNHADDS = 130 , SPARC_INS_FNOR = 131 , SPARC_INS_FNORS = 132 , SPARC_INS_FNOT1 = 133 , SPARC_INS_FNOT1S = 134 , SPARC_INS_FNOT2 = 135 , SPARC_INS_FNOT2S = 136 , SPARC_INS_FONE = 137 , SPARC_INS_FONES = 138 , SPARC_INS_FOR = 139 , SPARC_INS_FORNOT1 = 140 , SPARC_INS_FORNOT1S = 141 , SPARC_INS_FORNOT2 = 142 , SPARC_INS_FORNOT2S = 143 , SPARC_INS_FORS = 144 , SPARC_INS_FPACK16 = 145 , SPARC_INS_FPACK32 = 146 , SPARC_INS_FPACKFIX = 147 , SPARC_INS_FPADD16 = 148 , SPARC_INS_FPADD16S = 149 , SPARC_INS_FPADD32 = 150 , SPARC_INS_FPADD32S = 151 , SPARC_INS_FPADD64 = 152 , SPARC_INS_FPMERGE = 153 , SPARC_INS_FPSUB16 = 154 , SPARC_INS_FPSUB16S = 155 , SPARC_INS_FPSUB32 = 156 , SPARC_INS_FPSUB32S = 157 , SPARC_INS_FQTOD = 158 , SPARC_INS_FQTOI = 159 , SPARC_INS_FQTOS = 160 , SPARC_INS_FQTOX = 161 , SPARC_INS_FSLAS16 = 162 , SPARC_INS_FSLAS32 = 163 , SPARC_INS_FSLL16 = 164 , SPARC_INS_FSLL32 = 165 , SPARC_INS_FSMULD = 166 , SPARC_INS_FSQRTD = 167 , SPARC_INS_FSQRTQ = 168 , SPARC_INS_FSQRTS = 169 , SPARC_INS_FSRA16 = 170 , SPARC_INS_FSRA32 = 171 , SPARC_INS_FSRC1 = 172 , SPARC_INS_FSRC1S = 173 , SPARC_INS_FSRC2 = 174 , SPARC_INS_FSRC2S = 175 , SPARC_INS_FSRL16 = 176 , SPARC_INS_FSRL32 = 177 , SPARC_INS_FSTOD = 178 , SPARC_INS_FSTOI = 179 , SPARC_INS_FSTOQ = 180 , SPARC_INS_FSTOX = 181 , SPARC_INS_FSUBD = 182 , SPARC_INS_FSUBQ = 183 , SPARC_INS_FSUBS = 184 , SPARC_INS_FXNOR = 185 , SPARC_INS_FXNORS = 186 , SPARC_INS_FXOR = 187 , SPARC_INS_FXORS = 188 , SPARC_INS_FXTOD = 189 , SPARC_INS_FXTOQ = 190 , SPARC_INS_FXTOS = 191 , SPARC_INS_FZERO = 192 , SPARC_INS_FZEROS = 193 , SPARC_INS_JMPL = 194 , SPARC_INS_LDD = 195 , SPARC_INS_LD = 196 , SPARC_INS_LDQ = 197 , SPARC_INS_LDSB = 198 , SPARC_INS_LDSH = 199 , SPARC_INS_LDSW = 200 , SPARC_INS_LDUB = 201 , SPARC_INS_LDUH = 202 , SPARC_INS_LDX = 203 , SPARC_INS_LZCNT = 204 , SPARC_INS_MEMBAR = 205 , SPARC_INS_MOVDTOX = 206 , SPARC_INS_MOV = 207 , SPARC_INS_MOVRGEZ = 208 , SPARC_INS_MOVRGZ = 209 , SPARC_INS_MOVRLEZ = 210 , SPARC_INS_MOVRLZ = 211 , SPARC_INS_MOVRNZ = 212 , SPARC_INS_MOVRZ = 213 , SPARC_INS_MOVSTOSW = 214 , SPARC_INS_MOVSTOUW = 215 , SPARC_INS_MULX = 216 , SPARC_INS_NOP = 217 , SPARC_INS_ORCC = 218 , SPARC_INS_ORNCC = 219 , SPARC_INS_ORN = 220 , SPARC_INS_OR = 221 , SPARC_INS_PDIST = 222 , SPARC_INS_PDISTN = 223 , SPARC_INS_POPC = 224 , SPARC_INS_RD = 225 , SPARC_INS_RESTORE = 226 , SPARC_INS_RETT = 227 , SPARC_INS_SAVE = 228 , SPARC_INS_SDIVCC = 229 , SPARC_INS_SDIVX = 230 , SPARC_INS_SDIV = 231 , SPARC_INS_SETHI = 232 , SPARC_INS_SHUTDOWN = 233 , SPARC_INS_SIAM = 234 , SPARC_INS_SLLX = 235 , SPARC_INS_SLL = 236 , SPARC_INS_SMULCC = 237 , SPARC_INS_SMUL = 238 , SPARC_INS_SRAX = 239 , SPARC_INS_SRA = 240 , SPARC_INS_SRLX = 241 , SPARC_INS_SRL = 242 , SPARC_INS_STBAR = 243 , SPARC_INS_STB = 244 , SPARC_INS_STD = 245 , SPARC_INS_ST = 246 , SPARC_INS_STH = 247 , SPARC_INS_STQ = 248 , SPARC_INS_STX = 249 , SPARC_INS_SUBCC = 250 , SPARC_INS_SUBX = 251 , SPARC_INS_SUBXCC = 252 , SPARC_INS_SUB = 253 , SPARC_INS_SWAP = 254 , SPARC_INS_TADDCCTV = 255 , SPARC_INS_TADDCC = 256 , SPARC_INS_T = 257 , SPARC_INS_TSUBCCTV = 258 , SPARC_INS_TSUBCC = 259 , SPARC_INS_UDIVCC = 260 , SPARC_INS_UDIVX = 261 , SPARC_INS_UDIV = 262 , SPARC_INS_UMULCC = 263 , SPARC_INS_UMULXHI = 264 , SPARC_INS_UMUL = 265 , SPARC_INS_UNIMP = 266 , SPARC_INS_FCMPED = 267 , SPARC_INS_FCMPEQ = 268 , SPARC_INS_FCMPES = 269 , SPARC_INS_WR = 270 , SPARC_INS_XMULX = 271 , SPARC_INS_XMULXHI = 272 , SPARC_INS_XNORCC = 273 , SPARC_INS_XNOR = 274 , SPARC_INS_XORCC = 275 , SPARC_INS_XOR = 276 , SPARC_INS_RET = 277 , SPARC_INS_RETL = 278 , SPARC_INS_ENDING = 279 , } # [repr (u32)] # [doc = " Group of SPARC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn_group { # [doc = "< = CS_GRP_INVALID"] SPARC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SPARC_GRP_JUMP = 1 , SPARC_GRP_HARDQUAD = 128 , SPARC_GRP_V9 = 129 , SPARC_GRP_VIS = 130 , SPARC_GRP_VIS2 = 131 , SPARC_GRP_VIS3 = 132 , SPARC_GRP_32BIT = 133 , SPARC_GRP_64BIT = 134 , SPARC_GRP_ENDING = 135 , } # [repr (u32)] # [doc = " Enums corresponding to SystemZ condition codes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_cc { # [doc = "< invalid CC (default)"] SYSZ_CC_INVALID = 0 , SYSZ_CC_O = 1 , SYSZ_CC_H = 2 , SYSZ_CC_NLE = 3 , SYSZ_CC_L = 4 , SYSZ_CC_NHE = 5 , SYSZ_CC_LH = 6 , SYSZ_CC_NE = 7 , SYSZ_CC_E = 8 , SYSZ_CC_NLH = 9 , SYSZ_CC_HE = 10 , SYSZ_CC_NL = 11 , SYSZ_CC_LE = 12 , SYSZ_CC_NH = 13 , SYSZ_CC_NO = 14 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SYSZ_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SYSZ_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SYSZ_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SYSZ_OP_MEM = 3 , # [doc = "< Access register operand."] SYSZ_OP_ACREG = 64 , } # [repr (u32)] # [doc = " SystemZ registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_reg { SYSZ_REG_INVALID = 0 , SYSZ_REG_0 = 1 , SYSZ_REG_1 = 2 , SYSZ_REG_2 = 3 , SYSZ_REG_3 = 4 , SYSZ_REG_4 = 5 , SYSZ_REG_5 = 6 , SYSZ_REG_6 = 7 , SYSZ_REG_7 = 8 , SYSZ_REG_8 = 9 , SYSZ_REG_9 = 10 , SYSZ_REG_10 = 11 , SYSZ_REG_11 = 12 , SYSZ_REG_12 = 13 , SYSZ_REG_13 = 14 , SYSZ_REG_14 = 15 , SYSZ_REG_15 = 16 , SYSZ_REG_CC = 17 , SYSZ_REG_F0 = 18 , SYSZ_REG_F1 = 19 , SYSZ_REG_F2 = 20 , SYSZ_REG_F3 = 21 , SYSZ_REG_F4 = 22 , SYSZ_REG_F5 = 23 , SYSZ_REG_F6 = 24 , SYSZ_REG_F7 = 25 , SYSZ_REG_F8 = 26 , SYSZ_REG_F9 = 27 , SYSZ_REG_F10 = 28 , SYSZ_REG_F11 = 29 , SYSZ_REG_F12 = 30 , SYSZ_REG_F13 = 31 , SYSZ_REG_F14 = 32 , SYSZ_REG_F15 = 33 , SYSZ_REG_R0L = 34 , SYSZ_REG_A0 = 35 , SYSZ_REG_A1 = 36 , SYSZ_REG_A2 = 37 , SYSZ_REG_A3 = 38 , SYSZ_REG_A4 = 39 , SYSZ_REG_A5 = 40 , SYSZ_REG_A6 = 41 , SYSZ_REG_A7 = 42 , SYSZ_REG_A8 = 43 , SYSZ_REG_A9 = 44 , SYSZ_REG_A10 = 45 , SYSZ_REG_A11 = 46 , SYSZ_REG_A12 = 47 , SYSZ_REG_A13 = 48 , SYSZ_REG_A14 = 49 , SYSZ_REG_A15 = 50 , SYSZ_REG_C0 = 51 , SYSZ_REG_C1 = 52 , SYSZ_REG_C2 = 53 , SYSZ_REG_C3 = 54 , SYSZ_REG_C4 = 55 , SYSZ_REG_C5 = 56 , SYSZ_REG_C6 = 57 , SYSZ_REG_C7 = 58 , SYSZ_REG_C8 = 59 , SYSZ_REG_C9 = 60 , SYSZ_REG_C10 = 61 , SYSZ_REG_C11 = 62 , SYSZ_REG_C12 = 63 , SYSZ_REG_C13 = 64 , SYSZ_REG_C14 = 65 , SYSZ_REG_C15 = 66 , SYSZ_REG_V0 = 67 , SYSZ_REG_V1 = 68 , SYSZ_REG_V2 = 69 , SYSZ_REG_V3 = 70 , SYSZ_REG_V4 = 71 , SYSZ_REG_V5 = 72 , SYSZ_REG_V6 = 73 , SYSZ_REG_V7 = 74 , SYSZ_REG_V8 = 75 , SYSZ_REG_V9 = 76 , SYSZ_REG_V10 = 77 , SYSZ_REG_V11 = 78 , SYSZ_REG_V12 = 79 , SYSZ_REG_V13 = 80 , SYSZ_REG_V14 = 81 , SYSZ_REG_V15 = 82 , SYSZ_REG_V16 = 83 , SYSZ_REG_V17 = 84 , SYSZ_REG_V18 = 85 , SYSZ_REG_V19 = 86 , SYSZ_REG_V20 = 87 , SYSZ_REG_V21 = 88 , SYSZ_REG_V22 = 89 , SYSZ_REG_V23 = 90 , SYSZ_REG_V24 = 91 , SYSZ_REG_V25 = 92 , SYSZ_REG_V26 = 93 , SYSZ_REG_V27 = 94 , SYSZ_REG_V28 = 95 , SYSZ_REG_V29 = 96 , SYSZ_REG_V30 = 97 , SYSZ_REG_V31 = 98 , SYSZ_REG_F16 = 99 , SYSZ_REG_F17 = 100 , SYSZ_REG_F18 = 101 , SYSZ_REG_F19 = 102 , SYSZ_REG_F20 = 103 , SYSZ_REG_F21 = 104 , SYSZ_REG_F22 = 105 , SYSZ_REG_F23 = 106 , SYSZ_REG_F24 = 107 , SYSZ_REG_F25 = 108 , SYSZ_REG_F26 = 109 , SYSZ_REG_F27 = 110 , SYSZ_REG_F28 = 111 , SYSZ_REG_F29 = 112 , SYSZ_REG_F30 = 113 , SYSZ_REG_F31 = 114 , SYSZ_REG_F0Q = 115 , SYSZ_REG_F4Q = 116 , SYSZ_REG_ENDING = 117 , } # [doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sysz_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< BDLAddr operand"] pub length : u64 , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sysz_op_mem"] [:: std :: mem :: size_of :: < sysz_op_mem > () - 24usize] ; ["Alignment of sysz_op_mem"] [:: std :: mem :: align_of :: < sysz_op_mem > () - 8usize] ; ["Offset of field: sysz_op_mem::base"] [:: std :: mem :: offset_of ! (sysz_op_mem , base) - 0usize] ; ["Offset of field: sysz_op_mem::index"] [:: std :: mem :: offset_of ! (sysz_op_mem , index) - 1usize] ; ["Offset of field: sysz_op_mem::length"] [:: std :: mem :: offset_of ! (sysz_op_mem , length) - 8usize] ; ["Offset of field: sysz_op_mem::disp"] [:: std :: mem :: offset_of ! (sysz_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz_op { # [doc = "< operand type"] pub type_ : sysz_op_type , pub __bindgen_anon_1 : cs_sysz_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sysz_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sysz_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sysz_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sysz_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sysz_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op"] [:: std :: mem :: size_of :: < cs_sysz_op > () - 32usize] ; ["Alignment of cs_sysz_op"] [:: std :: mem :: align_of :: < cs_sysz_op > () - 8usize] ; ["Offset of field: cs_sysz_op::type_"] [:: std :: mem :: offset_of ! (cs_sysz_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz { # [doc = "< Code condition"] pub cc : sysz_cc , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sysz_op ; 6usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz"] [:: std :: mem :: size_of :: < cs_sysz > () - 200usize] ; ["Alignment of cs_sysz"] [:: std :: mem :: align_of :: < cs_sysz > () - 8usize] ; ["Offset of field: cs_sysz::cc"] [:: std :: mem :: offset_of ! (cs_sysz , cc) - 0usize] ; ["Offset of field: cs_sysz::op_count"] [:: std :: mem :: offset_of ! (cs_sysz , op_count) - 4usize] ; ["Offset of field: cs_sysz::operands"] [:: std :: mem :: offset_of ! (cs_sysz , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SystemZ instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn { SYSZ_INS_INVALID = 0 , SYSZ_INS_A = 1 , SYSZ_INS_ADB = 2 , SYSZ_INS_ADBR = 3 , SYSZ_INS_AEB = 4 , SYSZ_INS_AEBR = 5 , SYSZ_INS_AFI = 6 , SYSZ_INS_AG = 7 , SYSZ_INS_AGF = 8 , SYSZ_INS_AGFI = 9 , SYSZ_INS_AGFR = 10 , SYSZ_INS_AGHI = 11 , SYSZ_INS_AGHIK = 12 , SYSZ_INS_AGR = 13 , SYSZ_INS_AGRK = 14 , SYSZ_INS_AGSI = 15 , SYSZ_INS_AH = 16 , SYSZ_INS_AHI = 17 , SYSZ_INS_AHIK = 18 , SYSZ_INS_AHY = 19 , SYSZ_INS_AIH = 20 , SYSZ_INS_AL = 21 , SYSZ_INS_ALC = 22 , SYSZ_INS_ALCG = 23 , SYSZ_INS_ALCGR = 24 , SYSZ_INS_ALCR = 25 , SYSZ_INS_ALFI = 26 , SYSZ_INS_ALG = 27 , SYSZ_INS_ALGF = 28 , SYSZ_INS_ALGFI = 29 , SYSZ_INS_ALGFR = 30 , SYSZ_INS_ALGHSIK = 31 , SYSZ_INS_ALGR = 32 , SYSZ_INS_ALGRK = 33 , SYSZ_INS_ALHSIK = 34 , SYSZ_INS_ALR = 35 , SYSZ_INS_ALRK = 36 , SYSZ_INS_ALY = 37 , SYSZ_INS_AR = 38 , SYSZ_INS_ARK = 39 , SYSZ_INS_ASI = 40 , SYSZ_INS_AXBR = 41 , SYSZ_INS_AY = 42 , SYSZ_INS_BCR = 43 , SYSZ_INS_BRC = 44 , SYSZ_INS_BRCL = 45 , SYSZ_INS_CGIJ = 46 , SYSZ_INS_CGRJ = 47 , SYSZ_INS_CIJ = 48 , SYSZ_INS_CLGIJ = 49 , SYSZ_INS_CLGRJ = 50 , SYSZ_INS_CLIJ = 51 , SYSZ_INS_CLRJ = 52 , SYSZ_INS_CRJ = 53 , SYSZ_INS_BER = 54 , SYSZ_INS_JE = 55 , SYSZ_INS_JGE = 56 , SYSZ_INS_LOCE = 57 , SYSZ_INS_LOCGE = 58 , SYSZ_INS_LOCGRE = 59 , SYSZ_INS_LOCRE = 60 , SYSZ_INS_STOCE = 61 , SYSZ_INS_STOCGE = 62 , SYSZ_INS_BHR = 63 , SYSZ_INS_BHER = 64 , SYSZ_INS_JHE = 65 , SYSZ_INS_JGHE = 66 , SYSZ_INS_LOCHE = 67 , SYSZ_INS_LOCGHE = 68 , SYSZ_INS_LOCGRHE = 69 , SYSZ_INS_LOCRHE = 70 , SYSZ_INS_STOCHE = 71 , SYSZ_INS_STOCGHE = 72 , SYSZ_INS_JH = 73 , SYSZ_INS_JGH = 74 , SYSZ_INS_LOCH = 75 , SYSZ_INS_LOCGH = 76 , SYSZ_INS_LOCGRH = 77 , SYSZ_INS_LOCRH = 78 , SYSZ_INS_STOCH = 79 , SYSZ_INS_STOCGH = 80 , SYSZ_INS_CGIJNLH = 81 , SYSZ_INS_CGRJNLH = 82 , SYSZ_INS_CIJNLH = 83 , SYSZ_INS_CLGIJNLH = 84 , SYSZ_INS_CLGRJNLH = 85 , SYSZ_INS_CLIJNLH = 86 , SYSZ_INS_CLRJNLH = 87 , SYSZ_INS_CRJNLH = 88 , SYSZ_INS_CGIJE = 89 , SYSZ_INS_CGRJE = 90 , SYSZ_INS_CIJE = 91 , SYSZ_INS_CLGIJE = 92 , SYSZ_INS_CLGRJE = 93 , SYSZ_INS_CLIJE = 94 , SYSZ_INS_CLRJE = 95 , SYSZ_INS_CRJE = 96 , SYSZ_INS_CGIJNLE = 97 , SYSZ_INS_CGRJNLE = 98 , SYSZ_INS_CIJNLE = 99 , SYSZ_INS_CLGIJNLE = 100 , SYSZ_INS_CLGRJNLE = 101 , SYSZ_INS_CLIJNLE = 102 , SYSZ_INS_CLRJNLE = 103 , SYSZ_INS_CRJNLE = 104 , SYSZ_INS_CGIJH = 105 , SYSZ_INS_CGRJH = 106 , SYSZ_INS_CIJH = 107 , SYSZ_INS_CLGIJH = 108 , SYSZ_INS_CLGRJH = 109 , SYSZ_INS_CLIJH = 110 , SYSZ_INS_CLRJH = 111 , SYSZ_INS_CRJH = 112 , SYSZ_INS_CGIJNL = 113 , SYSZ_INS_CGRJNL = 114 , SYSZ_INS_CIJNL = 115 , SYSZ_INS_CLGIJNL = 116 , SYSZ_INS_CLGRJNL = 117 , SYSZ_INS_CLIJNL = 118 , SYSZ_INS_CLRJNL = 119 , SYSZ_INS_CRJNL = 120 , SYSZ_INS_CGIJHE = 121 , SYSZ_INS_CGRJHE = 122 , SYSZ_INS_CIJHE = 123 , SYSZ_INS_CLGIJHE = 124 , SYSZ_INS_CLGRJHE = 125 , SYSZ_INS_CLIJHE = 126 , SYSZ_INS_CLRJHE = 127 , SYSZ_INS_CRJHE = 128 , SYSZ_INS_CGIJNHE = 129 , SYSZ_INS_CGRJNHE = 130 , SYSZ_INS_CIJNHE = 131 , SYSZ_INS_CLGIJNHE = 132 , SYSZ_INS_CLGRJNHE = 133 , SYSZ_INS_CLIJNHE = 134 , SYSZ_INS_CLRJNHE = 135 , SYSZ_INS_CRJNHE = 136 , SYSZ_INS_CGIJL = 137 , SYSZ_INS_CGRJL = 138 , SYSZ_INS_CIJL = 139 , SYSZ_INS_CLGIJL = 140 , SYSZ_INS_CLGRJL = 141 , SYSZ_INS_CLIJL = 142 , SYSZ_INS_CLRJL = 143 , SYSZ_INS_CRJL = 144 , SYSZ_INS_CGIJNH = 145 , SYSZ_INS_CGRJNH = 146 , SYSZ_INS_CIJNH = 147 , SYSZ_INS_CLGIJNH = 148 , SYSZ_INS_CLGRJNH = 149 , SYSZ_INS_CLIJNH = 150 , SYSZ_INS_CLRJNH = 151 , SYSZ_INS_CRJNH = 152 , SYSZ_INS_CGIJLE = 153 , SYSZ_INS_CGRJLE = 154 , SYSZ_INS_CIJLE = 155 , SYSZ_INS_CLGIJLE = 156 , SYSZ_INS_CLGRJLE = 157 , SYSZ_INS_CLIJLE = 158 , SYSZ_INS_CLRJLE = 159 , SYSZ_INS_CRJLE = 160 , SYSZ_INS_CGIJNE = 161 , SYSZ_INS_CGRJNE = 162 , SYSZ_INS_CIJNE = 163 , SYSZ_INS_CLGIJNE = 164 , SYSZ_INS_CLGRJNE = 165 , SYSZ_INS_CLIJNE = 166 , SYSZ_INS_CLRJNE = 167 , SYSZ_INS_CRJNE = 168 , SYSZ_INS_CGIJLH = 169 , SYSZ_INS_CGRJLH = 170 , SYSZ_INS_CIJLH = 171 , SYSZ_INS_CLGIJLH = 172 , SYSZ_INS_CLGRJLH = 173 , SYSZ_INS_CLIJLH = 174 , SYSZ_INS_CLRJLH = 175 , SYSZ_INS_CRJLH = 176 , SYSZ_INS_BLR = 177 , SYSZ_INS_BLER = 178 , SYSZ_INS_JLE = 179 , SYSZ_INS_JGLE = 180 , SYSZ_INS_LOCLE = 181 , SYSZ_INS_LOCGLE = 182 , SYSZ_INS_LOCGRLE = 183 , SYSZ_INS_LOCRLE = 184 , SYSZ_INS_STOCLE = 185 , SYSZ_INS_STOCGLE = 186 , SYSZ_INS_BLHR = 187 , SYSZ_INS_JLH = 188 , SYSZ_INS_JGLH = 189 , SYSZ_INS_LOCLH = 190 , SYSZ_INS_LOCGLH = 191 , SYSZ_INS_LOCGRLH = 192 , SYSZ_INS_LOCRLH = 193 , SYSZ_INS_STOCLH = 194 , SYSZ_INS_STOCGLH = 195 , SYSZ_INS_JL = 196 , SYSZ_INS_JGL = 197 , SYSZ_INS_LOCL = 198 , SYSZ_INS_LOCGL = 199 , SYSZ_INS_LOCGRL = 200 , SYSZ_INS_LOCRL = 201 , SYSZ_INS_LOC = 202 , SYSZ_INS_LOCG = 203 , SYSZ_INS_LOCGR = 204 , SYSZ_INS_LOCR = 205 , SYSZ_INS_STOCL = 206 , SYSZ_INS_STOCGL = 207 , SYSZ_INS_BNER = 208 , SYSZ_INS_JNE = 209 , SYSZ_INS_JGNE = 210 , SYSZ_INS_LOCNE = 211 , SYSZ_INS_LOCGNE = 212 , SYSZ_INS_LOCGRNE = 213 , SYSZ_INS_LOCRNE = 214 , SYSZ_INS_STOCNE = 215 , SYSZ_INS_STOCGNE = 216 , SYSZ_INS_BNHR = 217 , SYSZ_INS_BNHER = 218 , SYSZ_INS_JNHE = 219 , SYSZ_INS_JGNHE = 220 , SYSZ_INS_LOCNHE = 221 , SYSZ_INS_LOCGNHE = 222 , SYSZ_INS_LOCGRNHE = 223 , SYSZ_INS_LOCRNHE = 224 , SYSZ_INS_STOCNHE = 225 , SYSZ_INS_STOCGNHE = 226 , SYSZ_INS_JNH = 227 , SYSZ_INS_JGNH = 228 , SYSZ_INS_LOCNH = 229 , SYSZ_INS_LOCGNH = 230 , SYSZ_INS_LOCGRNH = 231 , SYSZ_INS_LOCRNH = 232 , SYSZ_INS_STOCNH = 233 , SYSZ_INS_STOCGNH = 234 , SYSZ_INS_BNLR = 235 , SYSZ_INS_BNLER = 236 , SYSZ_INS_JNLE = 237 , SYSZ_INS_JGNLE = 238 , SYSZ_INS_LOCNLE = 239 , SYSZ_INS_LOCGNLE = 240 , SYSZ_INS_LOCGRNLE = 241 , SYSZ_INS_LOCRNLE = 242 , SYSZ_INS_STOCNLE = 243 , SYSZ_INS_STOCGNLE = 244 , SYSZ_INS_BNLHR = 245 , SYSZ_INS_JNLH = 246 , SYSZ_INS_JGNLH = 247 , SYSZ_INS_LOCNLH = 248 , SYSZ_INS_LOCGNLH = 249 , SYSZ_INS_LOCGRNLH = 250 , SYSZ_INS_LOCRNLH = 251 , SYSZ_INS_STOCNLH = 252 , SYSZ_INS_STOCGNLH = 253 , SYSZ_INS_JNL = 254 , SYSZ_INS_JGNL = 255 , SYSZ_INS_LOCNL = 256 , SYSZ_INS_LOCGNL = 257 , SYSZ_INS_LOCGRNL = 258 , SYSZ_INS_LOCRNL = 259 , SYSZ_INS_STOCNL = 260 , SYSZ_INS_STOCGNL = 261 , SYSZ_INS_BNOR = 262 , SYSZ_INS_JNO = 263 , SYSZ_INS_JGNO = 264 , SYSZ_INS_LOCNO = 265 , SYSZ_INS_LOCGNO = 266 , SYSZ_INS_LOCGRNO = 267 , SYSZ_INS_LOCRNO = 268 , SYSZ_INS_STOCNO = 269 , SYSZ_INS_STOCGNO = 270 , SYSZ_INS_BOR = 271 , SYSZ_INS_JO = 272 , SYSZ_INS_JGO = 273 , SYSZ_INS_LOCO = 274 , SYSZ_INS_LOCGO = 275 , SYSZ_INS_LOCGRO = 276 , SYSZ_INS_LOCRO = 277 , SYSZ_INS_STOCO = 278 , SYSZ_INS_STOCGO = 279 , SYSZ_INS_STOC = 280 , SYSZ_INS_STOCG = 281 , SYSZ_INS_BASR = 282 , SYSZ_INS_BR = 283 , SYSZ_INS_BRAS = 284 , SYSZ_INS_BRASL = 285 , SYSZ_INS_J = 286 , SYSZ_INS_JG = 287 , SYSZ_INS_BRCT = 288 , SYSZ_INS_BRCTG = 289 , SYSZ_INS_C = 290 , SYSZ_INS_CDB = 291 , SYSZ_INS_CDBR = 292 , SYSZ_INS_CDFBR = 293 , SYSZ_INS_CDGBR = 294 , SYSZ_INS_CDLFBR = 295 , SYSZ_INS_CDLGBR = 296 , SYSZ_INS_CEB = 297 , SYSZ_INS_CEBR = 298 , SYSZ_INS_CEFBR = 299 , SYSZ_INS_CEGBR = 300 , SYSZ_INS_CELFBR = 301 , SYSZ_INS_CELGBR = 302 , SYSZ_INS_CFDBR = 303 , SYSZ_INS_CFEBR = 304 , SYSZ_INS_CFI = 305 , SYSZ_INS_CFXBR = 306 , SYSZ_INS_CG = 307 , SYSZ_INS_CGDBR = 308 , SYSZ_INS_CGEBR = 309 , SYSZ_INS_CGF = 310 , SYSZ_INS_CGFI = 311 , SYSZ_INS_CGFR = 312 , SYSZ_INS_CGFRL = 313 , SYSZ_INS_CGH = 314 , SYSZ_INS_CGHI = 315 , SYSZ_INS_CGHRL = 316 , SYSZ_INS_CGHSI = 317 , SYSZ_INS_CGR = 318 , SYSZ_INS_CGRL = 319 , SYSZ_INS_CGXBR = 320 , SYSZ_INS_CH = 321 , SYSZ_INS_CHF = 322 , SYSZ_INS_CHHSI = 323 , SYSZ_INS_CHI = 324 , SYSZ_INS_CHRL = 325 , SYSZ_INS_CHSI = 326 , SYSZ_INS_CHY = 327 , SYSZ_INS_CIH = 328 , SYSZ_INS_CL = 329 , SYSZ_INS_CLC = 330 , SYSZ_INS_CLFDBR = 331 , SYSZ_INS_CLFEBR = 332 , SYSZ_INS_CLFHSI = 333 , SYSZ_INS_CLFI = 334 , SYSZ_INS_CLFXBR = 335 , SYSZ_INS_CLG = 336 , SYSZ_INS_CLGDBR = 337 , SYSZ_INS_CLGEBR = 338 , SYSZ_INS_CLGF = 339 , SYSZ_INS_CLGFI = 340 , SYSZ_INS_CLGFR = 341 , SYSZ_INS_CLGFRL = 342 , SYSZ_INS_CLGHRL = 343 , SYSZ_INS_CLGHSI = 344 , SYSZ_INS_CLGR = 345 , SYSZ_INS_CLGRL = 346 , SYSZ_INS_CLGXBR = 347 , SYSZ_INS_CLHF = 348 , SYSZ_INS_CLHHSI = 349 , SYSZ_INS_CLHRL = 350 , SYSZ_INS_CLI = 351 , SYSZ_INS_CLIH = 352 , SYSZ_INS_CLIY = 353 , SYSZ_INS_CLR = 354 , SYSZ_INS_CLRL = 355 , SYSZ_INS_CLST = 356 , SYSZ_INS_CLY = 357 , SYSZ_INS_CPSDR = 358 , SYSZ_INS_CR = 359 , SYSZ_INS_CRL = 360 , SYSZ_INS_CS = 361 , SYSZ_INS_CSG = 362 , SYSZ_INS_CSY = 363 , SYSZ_INS_CXBR = 364 , SYSZ_INS_CXFBR = 365 , SYSZ_INS_CXGBR = 366 , SYSZ_INS_CXLFBR = 367 , SYSZ_INS_CXLGBR = 368 , SYSZ_INS_CY = 369 , SYSZ_INS_DDB = 370 , SYSZ_INS_DDBR = 371 , SYSZ_INS_DEB = 372 , SYSZ_INS_DEBR = 373 , SYSZ_INS_DL = 374 , SYSZ_INS_DLG = 375 , SYSZ_INS_DLGR = 376 , SYSZ_INS_DLR = 377 , SYSZ_INS_DSG = 378 , SYSZ_INS_DSGF = 379 , SYSZ_INS_DSGFR = 380 , SYSZ_INS_DSGR = 381 , SYSZ_INS_DXBR = 382 , SYSZ_INS_EAR = 383 , SYSZ_INS_FIDBR = 384 , SYSZ_INS_FIDBRA = 385 , SYSZ_INS_FIEBR = 386 , SYSZ_INS_FIEBRA = 387 , SYSZ_INS_FIXBR = 388 , SYSZ_INS_FIXBRA = 389 , SYSZ_INS_FLOGR = 390 , SYSZ_INS_IC = 391 , SYSZ_INS_ICY = 392 , SYSZ_INS_IIHF = 393 , SYSZ_INS_IIHH = 394 , SYSZ_INS_IIHL = 395 , SYSZ_INS_IILF = 396 , SYSZ_INS_IILH = 397 , SYSZ_INS_IILL = 398 , SYSZ_INS_IPM = 399 , SYSZ_INS_L = 400 , SYSZ_INS_LA = 401 , SYSZ_INS_LAA = 402 , SYSZ_INS_LAAG = 403 , SYSZ_INS_LAAL = 404 , SYSZ_INS_LAALG = 405 , SYSZ_INS_LAN = 406 , SYSZ_INS_LANG = 407 , SYSZ_INS_LAO = 408 , SYSZ_INS_LAOG = 409 , SYSZ_INS_LARL = 410 , SYSZ_INS_LAX = 411 , SYSZ_INS_LAXG = 412 , SYSZ_INS_LAY = 413 , SYSZ_INS_LB = 414 , SYSZ_INS_LBH = 415 , SYSZ_INS_LBR = 416 , SYSZ_INS_LCDBR = 417 , SYSZ_INS_LCEBR = 418 , SYSZ_INS_LCGFR = 419 , SYSZ_INS_LCGR = 420 , SYSZ_INS_LCR = 421 , SYSZ_INS_LCXBR = 422 , SYSZ_INS_LD = 423 , SYSZ_INS_LDEB = 424 , SYSZ_INS_LDEBR = 425 , SYSZ_INS_LDGR = 426 , SYSZ_INS_LDR = 427 , SYSZ_INS_LDXBR = 428 , SYSZ_INS_LDXBRA = 429 , SYSZ_INS_LDY = 430 , SYSZ_INS_LE = 431 , SYSZ_INS_LEDBR = 432 , SYSZ_INS_LEDBRA = 433 , SYSZ_INS_LER = 434 , SYSZ_INS_LEXBR = 435 , SYSZ_INS_LEXBRA = 436 , SYSZ_INS_LEY = 437 , SYSZ_INS_LFH = 438 , SYSZ_INS_LG = 439 , SYSZ_INS_LGB = 440 , SYSZ_INS_LGBR = 441 , SYSZ_INS_LGDR = 442 , SYSZ_INS_LGF = 443 , SYSZ_INS_LGFI = 444 , SYSZ_INS_LGFR = 445 , SYSZ_INS_LGFRL = 446 , SYSZ_INS_LGH = 447 , SYSZ_INS_LGHI = 448 , SYSZ_INS_LGHR = 449 , SYSZ_INS_LGHRL = 450 , SYSZ_INS_LGR = 451 , SYSZ_INS_LGRL = 452 , SYSZ_INS_LH = 453 , SYSZ_INS_LHH = 454 , SYSZ_INS_LHI = 455 , SYSZ_INS_LHR = 456 , SYSZ_INS_LHRL = 457 , SYSZ_INS_LHY = 458 , SYSZ_INS_LLC = 459 , SYSZ_INS_LLCH = 460 , SYSZ_INS_LLCR = 461 , SYSZ_INS_LLGC = 462 , SYSZ_INS_LLGCR = 463 , SYSZ_INS_LLGF = 464 , SYSZ_INS_LLGFR = 465 , SYSZ_INS_LLGFRL = 466 , SYSZ_INS_LLGH = 467 , SYSZ_INS_LLGHR = 468 , SYSZ_INS_LLGHRL = 469 , SYSZ_INS_LLH = 470 , SYSZ_INS_LLHH = 471 , SYSZ_INS_LLHR = 472 , SYSZ_INS_LLHRL = 473 , SYSZ_INS_LLIHF = 474 , SYSZ_INS_LLIHH = 475 , SYSZ_INS_LLIHL = 476 , SYSZ_INS_LLILF = 477 , SYSZ_INS_LLILH = 478 , SYSZ_INS_LLILL = 479 , SYSZ_INS_LMG = 480 , SYSZ_INS_LNDBR = 481 , SYSZ_INS_LNEBR = 482 , SYSZ_INS_LNGFR = 483 , SYSZ_INS_LNGR = 484 , SYSZ_INS_LNR = 485 , SYSZ_INS_LNXBR = 486 , SYSZ_INS_LPDBR = 487 , SYSZ_INS_LPEBR = 488 , SYSZ_INS_LPGFR = 489 , SYSZ_INS_LPGR = 490 , SYSZ_INS_LPR = 491 , SYSZ_INS_LPXBR = 492 , SYSZ_INS_LR = 493 , SYSZ_INS_LRL = 494 , SYSZ_INS_LRV = 495 , SYSZ_INS_LRVG = 496 , SYSZ_INS_LRVGR = 497 , SYSZ_INS_LRVR = 498 , SYSZ_INS_LT = 499 , SYSZ_INS_LTDBR = 500 , SYSZ_INS_LTEBR = 501 , SYSZ_INS_LTG = 502 , SYSZ_INS_LTGF = 503 , SYSZ_INS_LTGFR = 504 , SYSZ_INS_LTGR = 505 , SYSZ_INS_LTR = 506 , SYSZ_INS_LTXBR = 507 , SYSZ_INS_LXDB = 508 , SYSZ_INS_LXDBR = 509 , SYSZ_INS_LXEB = 510 , SYSZ_INS_LXEBR = 511 , SYSZ_INS_LXR = 512 , SYSZ_INS_LY = 513 , SYSZ_INS_LZDR = 514 , SYSZ_INS_LZER = 515 , SYSZ_INS_LZXR = 516 , SYSZ_INS_MADB = 517 , SYSZ_INS_MADBR = 518 , SYSZ_INS_MAEB = 519 , SYSZ_INS_MAEBR = 520 , SYSZ_INS_MDB = 521 , SYSZ_INS_MDBR = 522 , SYSZ_INS_MDEB = 523 , SYSZ_INS_MDEBR = 524 , SYSZ_INS_MEEB = 525 , SYSZ_INS_MEEBR = 526 , SYSZ_INS_MGHI = 527 , SYSZ_INS_MH = 528 , SYSZ_INS_MHI = 529 , SYSZ_INS_MHY = 530 , SYSZ_INS_MLG = 531 , SYSZ_INS_MLGR = 532 , SYSZ_INS_MS = 533 , SYSZ_INS_MSDB = 534 , SYSZ_INS_MSDBR = 535 , SYSZ_INS_MSEB = 536 , SYSZ_INS_MSEBR = 537 , SYSZ_INS_MSFI = 538 , SYSZ_INS_MSG = 539 , SYSZ_INS_MSGF = 540 , SYSZ_INS_MSGFI = 541 , SYSZ_INS_MSGFR = 542 , SYSZ_INS_MSGR = 543 , SYSZ_INS_MSR = 544 , SYSZ_INS_MSY = 545 , SYSZ_INS_MVC = 546 , SYSZ_INS_MVGHI = 547 , SYSZ_INS_MVHHI = 548 , SYSZ_INS_MVHI = 549 , SYSZ_INS_MVI = 550 , SYSZ_INS_MVIY = 551 , SYSZ_INS_MVST = 552 , SYSZ_INS_MXBR = 553 , SYSZ_INS_MXDB = 554 , SYSZ_INS_MXDBR = 555 , SYSZ_INS_N = 556 , SYSZ_INS_NC = 557 , SYSZ_INS_NG = 558 , SYSZ_INS_NGR = 559 , SYSZ_INS_NGRK = 560 , SYSZ_INS_NI = 561 , SYSZ_INS_NIHF = 562 , SYSZ_INS_NIHH = 563 , SYSZ_INS_NIHL = 564 , SYSZ_INS_NILF = 565 , SYSZ_INS_NILH = 566 , SYSZ_INS_NILL = 567 , SYSZ_INS_NIY = 568 , SYSZ_INS_NR = 569 , SYSZ_INS_NRK = 570 , SYSZ_INS_NY = 571 , SYSZ_INS_O = 572 , SYSZ_INS_OC = 573 , SYSZ_INS_OG = 574 , SYSZ_INS_OGR = 575 , SYSZ_INS_OGRK = 576 , SYSZ_INS_OI = 577 , SYSZ_INS_OIHF = 578 , SYSZ_INS_OIHH = 579 , SYSZ_INS_OIHL = 580 , SYSZ_INS_OILF = 581 , SYSZ_INS_OILH = 582 , SYSZ_INS_OILL = 583 , SYSZ_INS_OIY = 584 , SYSZ_INS_OR = 585 , SYSZ_INS_ORK = 586 , SYSZ_INS_OY = 587 , SYSZ_INS_PFD = 588 , SYSZ_INS_PFDRL = 589 , SYSZ_INS_RISBG = 590 , SYSZ_INS_RISBHG = 591 , SYSZ_INS_RISBLG = 592 , SYSZ_INS_RLL = 593 , SYSZ_INS_RLLG = 594 , SYSZ_INS_RNSBG = 595 , SYSZ_INS_ROSBG = 596 , SYSZ_INS_RXSBG = 597 , SYSZ_INS_S = 598 , SYSZ_INS_SDB = 599 , SYSZ_INS_SDBR = 600 , SYSZ_INS_SEB = 601 , SYSZ_INS_SEBR = 602 , SYSZ_INS_SG = 603 , SYSZ_INS_SGF = 604 , SYSZ_INS_SGFR = 605 , SYSZ_INS_SGR = 606 , SYSZ_INS_SGRK = 607 , SYSZ_INS_SH = 608 , SYSZ_INS_SHY = 609 , SYSZ_INS_SL = 610 , SYSZ_INS_SLB = 611 , SYSZ_INS_SLBG = 612 , SYSZ_INS_SLBR = 613 , SYSZ_INS_SLFI = 614 , SYSZ_INS_SLG = 615 , SYSZ_INS_SLBGR = 616 , SYSZ_INS_SLGF = 617 , SYSZ_INS_SLGFI = 618 , SYSZ_INS_SLGFR = 619 , SYSZ_INS_SLGR = 620 , SYSZ_INS_SLGRK = 621 , SYSZ_INS_SLL = 622 , SYSZ_INS_SLLG = 623 , SYSZ_INS_SLLK = 624 , SYSZ_INS_SLR = 625 , SYSZ_INS_SLRK = 626 , SYSZ_INS_SLY = 627 , SYSZ_INS_SQDB = 628 , SYSZ_INS_SQDBR = 629 , SYSZ_INS_SQEB = 630 , SYSZ_INS_SQEBR = 631 , SYSZ_INS_SQXBR = 632 , SYSZ_INS_SR = 633 , SYSZ_INS_SRA = 634 , SYSZ_INS_SRAG = 635 , SYSZ_INS_SRAK = 636 , SYSZ_INS_SRK = 637 , SYSZ_INS_SRL = 638 , SYSZ_INS_SRLG = 639 , SYSZ_INS_SRLK = 640 , SYSZ_INS_SRST = 641 , SYSZ_INS_ST = 642 , SYSZ_INS_STC = 643 , SYSZ_INS_STCH = 644 , SYSZ_INS_STCY = 645 , SYSZ_INS_STD = 646 , SYSZ_INS_STDY = 647 , SYSZ_INS_STE = 648 , SYSZ_INS_STEY = 649 , SYSZ_INS_STFH = 650 , SYSZ_INS_STG = 651 , SYSZ_INS_STGRL = 652 , SYSZ_INS_STH = 653 , SYSZ_INS_STHH = 654 , SYSZ_INS_STHRL = 655 , SYSZ_INS_STHY = 656 , SYSZ_INS_STMG = 657 , SYSZ_INS_STRL = 658 , SYSZ_INS_STRV = 659 , SYSZ_INS_STRVG = 660 , SYSZ_INS_STY = 661 , SYSZ_INS_SXBR = 662 , SYSZ_INS_SY = 663 , SYSZ_INS_TM = 664 , SYSZ_INS_TMHH = 665 , SYSZ_INS_TMHL = 666 , SYSZ_INS_TMLH = 667 , SYSZ_INS_TMLL = 668 , SYSZ_INS_TMY = 669 , SYSZ_INS_X = 670 , SYSZ_INS_XC = 671 , SYSZ_INS_XG = 672 , SYSZ_INS_XGR = 673 , SYSZ_INS_XGRK = 674 , SYSZ_INS_XI = 675 , SYSZ_INS_XIHF = 676 , SYSZ_INS_XILF = 677 , SYSZ_INS_XIY = 678 , SYSZ_INS_XR = 679 , SYSZ_INS_XRK = 680 , SYSZ_INS_XY = 681 , SYSZ_INS_AD = 682 , SYSZ_INS_ADR = 683 , SYSZ_INS_ADTR = 684 , SYSZ_INS_ADTRA = 685 , SYSZ_INS_AE = 686 , SYSZ_INS_AER = 687 , SYSZ_INS_AGH = 688 , SYSZ_INS_AHHHR = 689 , SYSZ_INS_AHHLR = 690 , SYSZ_INS_ALGSI = 691 , SYSZ_INS_ALHHHR = 692 , SYSZ_INS_ALHHLR = 693 , SYSZ_INS_ALSI = 694 , SYSZ_INS_ALSIH = 695 , SYSZ_INS_ALSIHN = 696 , SYSZ_INS_AP = 697 , SYSZ_INS_AU = 698 , SYSZ_INS_AUR = 699 , SYSZ_INS_AW = 700 , SYSZ_INS_AWR = 701 , SYSZ_INS_AXR = 702 , SYSZ_INS_AXTR = 703 , SYSZ_INS_AXTRA = 704 , SYSZ_INS_B = 705 , SYSZ_INS_BAKR = 706 , SYSZ_INS_BAL = 707 , SYSZ_INS_BALR = 708 , SYSZ_INS_BAS = 709 , SYSZ_INS_BASSM = 710 , SYSZ_INS_BC = 711 , SYSZ_INS_BCT = 712 , SYSZ_INS_BCTG = 713 , SYSZ_INS_BCTGR = 714 , SYSZ_INS_BCTR = 715 , SYSZ_INS_BE = 716 , SYSZ_INS_BH = 717 , SYSZ_INS_BHE = 718 , SYSZ_INS_BI = 719 , SYSZ_INS_BIC = 720 , SYSZ_INS_BIE = 721 , SYSZ_INS_BIH = 722 , SYSZ_INS_BIHE = 723 , SYSZ_INS_BIL = 724 , SYSZ_INS_BILE = 725 , SYSZ_INS_BILH = 726 , SYSZ_INS_BIM = 727 , SYSZ_INS_BINE = 728 , SYSZ_INS_BINH = 729 , SYSZ_INS_BINHE = 730 , SYSZ_INS_BINL = 731 , SYSZ_INS_BINLE = 732 , SYSZ_INS_BINLH = 733 , SYSZ_INS_BINM = 734 , SYSZ_INS_BINO = 735 , SYSZ_INS_BINP = 736 , SYSZ_INS_BINZ = 737 , SYSZ_INS_BIO = 738 , SYSZ_INS_BIP = 739 , SYSZ_INS_BIZ = 740 , SYSZ_INS_BL = 741 , SYSZ_INS_BLE = 742 , SYSZ_INS_BLH = 743 , SYSZ_INS_BM = 744 , SYSZ_INS_BMR = 745 , SYSZ_INS_BNE = 746 , SYSZ_INS_BNH = 747 , SYSZ_INS_BNHE = 748 , SYSZ_INS_BNL = 749 , SYSZ_INS_BNLE = 750 , SYSZ_INS_BNLH = 751 , SYSZ_INS_BNM = 752 , SYSZ_INS_BNMR = 753 , SYSZ_INS_BNO = 754 , SYSZ_INS_BNP = 755 , SYSZ_INS_BNPR = 756 , SYSZ_INS_BNZ = 757 , SYSZ_INS_BNZR = 758 , SYSZ_INS_BO = 759 , SYSZ_INS_BP = 760 , SYSZ_INS_BPP = 761 , SYSZ_INS_BPR = 762 , SYSZ_INS_BPRP = 763 , SYSZ_INS_BRCTH = 764 , SYSZ_INS_BRXH = 765 , SYSZ_INS_BRXHG = 766 , SYSZ_INS_BRXLE = 767 , SYSZ_INS_BRXLG = 768 , SYSZ_INS_BSA = 769 , SYSZ_INS_BSG = 770 , SYSZ_INS_BSM = 771 , SYSZ_INS_BXH = 772 , SYSZ_INS_BXHG = 773 , SYSZ_INS_BXLE = 774 , SYSZ_INS_BXLEG = 775 , SYSZ_INS_BZ = 776 , SYSZ_INS_BZR = 777 , SYSZ_INS_CD = 778 , SYSZ_INS_CDFBRA = 779 , SYSZ_INS_CDFR = 780 , SYSZ_INS_CDFTR = 781 , SYSZ_INS_CDGBRA = 782 , SYSZ_INS_CDGR = 783 , SYSZ_INS_CDGTR = 784 , SYSZ_INS_CDGTRA = 785 , SYSZ_INS_CDLFTR = 786 , SYSZ_INS_CDLGTR = 787 , SYSZ_INS_CDPT = 788 , SYSZ_INS_CDR = 789 , SYSZ_INS_CDS = 790 , SYSZ_INS_CDSG = 791 , SYSZ_INS_CDSTR = 792 , SYSZ_INS_CDSY = 793 , SYSZ_INS_CDTR = 794 , SYSZ_INS_CDUTR = 795 , SYSZ_INS_CDZT = 796 , SYSZ_INS_CE = 797 , SYSZ_INS_CEDTR = 798 , SYSZ_INS_CEFBRA = 799 , SYSZ_INS_CEFR = 800 , SYSZ_INS_CEGBRA = 801 , SYSZ_INS_CEGR = 802 , SYSZ_INS_CER = 803 , SYSZ_INS_CEXTR = 804 , SYSZ_INS_CFC = 805 , SYSZ_INS_CFDBRA = 806 , SYSZ_INS_CFDR = 807 , SYSZ_INS_CFDTR = 808 , SYSZ_INS_CFEBRA = 809 , SYSZ_INS_CFER = 810 , SYSZ_INS_CFXBRA = 811 , SYSZ_INS_CFXR = 812 , SYSZ_INS_CFXTR = 813 , SYSZ_INS_CGDBRA = 814 , SYSZ_INS_CGDR = 815 , SYSZ_INS_CGDTR = 816 , SYSZ_INS_CGDTRA = 817 , SYSZ_INS_CGEBRA = 818 , SYSZ_INS_CGER = 819 , SYSZ_INS_CGIB = 820 , SYSZ_INS_CGIBE = 821 , SYSZ_INS_CGIBH = 822 , SYSZ_INS_CGIBHE = 823 , SYSZ_INS_CGIBL = 824 , SYSZ_INS_CGIBLE = 825 , SYSZ_INS_CGIBLH = 826 , SYSZ_INS_CGIBNE = 827 , SYSZ_INS_CGIBNH = 828 , SYSZ_INS_CGIBNHE = 829 , SYSZ_INS_CGIBNL = 830 , SYSZ_INS_CGIBNLE = 831 , SYSZ_INS_CGIBNLH = 832 , SYSZ_INS_CGIT = 833 , SYSZ_INS_CGITE = 834 , SYSZ_INS_CGITH = 835 , SYSZ_INS_CGITHE = 836 , SYSZ_INS_CGITL = 837 , SYSZ_INS_CGITLE = 838 , SYSZ_INS_CGITLH = 839 , SYSZ_INS_CGITNE = 840 , SYSZ_INS_CGITNH = 841 , SYSZ_INS_CGITNHE = 842 , SYSZ_INS_CGITNL = 843 , SYSZ_INS_CGITNLE = 844 , SYSZ_INS_CGITNLH = 845 , SYSZ_INS_CGRB = 846 , SYSZ_INS_CGRBE = 847 , SYSZ_INS_CGRBH = 848 , SYSZ_INS_CGRBHE = 849 , SYSZ_INS_CGRBL = 850 , SYSZ_INS_CGRBLE = 851 , SYSZ_INS_CGRBLH = 852 , SYSZ_INS_CGRBNE = 853 , SYSZ_INS_CGRBNH = 854 , SYSZ_INS_CGRBNHE = 855 , SYSZ_INS_CGRBNL = 856 , SYSZ_INS_CGRBNLE = 857 , SYSZ_INS_CGRBNLH = 858 , SYSZ_INS_CGRT = 859 , SYSZ_INS_CGRTE = 860 , SYSZ_INS_CGRTH = 861 , SYSZ_INS_CGRTHE = 862 , SYSZ_INS_CGRTL = 863 , SYSZ_INS_CGRTLE = 864 , SYSZ_INS_CGRTLH = 865 , SYSZ_INS_CGRTNE = 866 , SYSZ_INS_CGRTNH = 867 , SYSZ_INS_CGRTNHE = 868 , SYSZ_INS_CGRTNL = 869 , SYSZ_INS_CGRTNLE = 870 , SYSZ_INS_CGRTNLH = 871 , SYSZ_INS_CGXBRA = 872 , SYSZ_INS_CGXR = 873 , SYSZ_INS_CGXTR = 874 , SYSZ_INS_CGXTRA = 875 , SYSZ_INS_CHHR = 876 , SYSZ_INS_CHLR = 877 , SYSZ_INS_CIB = 878 , SYSZ_INS_CIBE = 879 , SYSZ_INS_CIBH = 880 , SYSZ_INS_CIBHE = 881 , SYSZ_INS_CIBL = 882 , SYSZ_INS_CIBLE = 883 , SYSZ_INS_CIBLH = 884 , SYSZ_INS_CIBNE = 885 , SYSZ_INS_CIBNH = 886 , SYSZ_INS_CIBNHE = 887 , SYSZ_INS_CIBNL = 888 , SYSZ_INS_CIBNLE = 889 , SYSZ_INS_CIBNLH = 890 , SYSZ_INS_CIT = 891 , SYSZ_INS_CITE = 892 , SYSZ_INS_CITH = 893 , SYSZ_INS_CITHE = 894 , SYSZ_INS_CITL = 895 , SYSZ_INS_CITLE = 896 , SYSZ_INS_CITLH = 897 , SYSZ_INS_CITNE = 898 , SYSZ_INS_CITNH = 899 , SYSZ_INS_CITNHE = 900 , SYSZ_INS_CITNL = 901 , SYSZ_INS_CITNLE = 902 , SYSZ_INS_CITNLH = 903 , SYSZ_INS_CKSM = 904 , SYSZ_INS_CLCL = 905 , SYSZ_INS_CLCLE = 906 , SYSZ_INS_CLCLU = 907 , SYSZ_INS_CLFDTR = 908 , SYSZ_INS_CLFIT = 909 , SYSZ_INS_CLFITE = 910 , SYSZ_INS_CLFITH = 911 , SYSZ_INS_CLFITHE = 912 , SYSZ_INS_CLFITL = 913 , SYSZ_INS_CLFITLE = 914 , SYSZ_INS_CLFITLH = 915 , SYSZ_INS_CLFITNE = 916 , SYSZ_INS_CLFITNH = 917 , SYSZ_INS_CLFITNHE = 918 , SYSZ_INS_CLFITNL = 919 , SYSZ_INS_CLFITNLE = 920 , SYSZ_INS_CLFITNLH = 921 , SYSZ_INS_CLFXTR = 922 , SYSZ_INS_CLGDTR = 923 , SYSZ_INS_CLGIB = 924 , SYSZ_INS_CLGIBE = 925 , SYSZ_INS_CLGIBH = 926 , SYSZ_INS_CLGIBHE = 927 , SYSZ_INS_CLGIBL = 928 , SYSZ_INS_CLGIBLE = 929 , SYSZ_INS_CLGIBLH = 930 , SYSZ_INS_CLGIBNE = 931 , SYSZ_INS_CLGIBNH = 932 , SYSZ_INS_CLGIBNHE = 933 , SYSZ_INS_CLGIBNL = 934 , SYSZ_INS_CLGIBNLE = 935 , SYSZ_INS_CLGIBNLH = 936 , SYSZ_INS_CLGIT = 937 , SYSZ_INS_CLGITE = 938 , SYSZ_INS_CLGITH = 939 , SYSZ_INS_CLGITHE = 940 , SYSZ_INS_CLGITL = 941 , SYSZ_INS_CLGITLE = 942 , SYSZ_INS_CLGITLH = 943 , SYSZ_INS_CLGITNE = 944 , SYSZ_INS_CLGITNH = 945 , SYSZ_INS_CLGITNHE = 946 , SYSZ_INS_CLGITNL = 947 , SYSZ_INS_CLGITNLE = 948 , SYSZ_INS_CLGITNLH = 949 , SYSZ_INS_CLGRB = 950 , SYSZ_INS_CLGRBE = 951 , SYSZ_INS_CLGRBH = 952 , SYSZ_INS_CLGRBHE = 953 , SYSZ_INS_CLGRBL = 954 , SYSZ_INS_CLGRBLE = 955 , SYSZ_INS_CLGRBLH = 956 , SYSZ_INS_CLGRBNE = 957 , SYSZ_INS_CLGRBNH = 958 , SYSZ_INS_CLGRBNHE = 959 , SYSZ_INS_CLGRBNL = 960 , SYSZ_INS_CLGRBNLE = 961 , SYSZ_INS_CLGRBNLH = 962 , SYSZ_INS_CLGRT = 963 , SYSZ_INS_CLGRTE = 964 , SYSZ_INS_CLGRTH = 965 , SYSZ_INS_CLGRTHE = 966 , SYSZ_INS_CLGRTL = 967 , SYSZ_INS_CLGRTLE = 968 , SYSZ_INS_CLGRTLH = 969 , SYSZ_INS_CLGRTNE = 970 , SYSZ_INS_CLGRTNH = 971 , SYSZ_INS_CLGRTNHE = 972 , SYSZ_INS_CLGRTNL = 973 , SYSZ_INS_CLGRTNLE = 974 , SYSZ_INS_CLGRTNLH = 975 , SYSZ_INS_CLGT = 976 , SYSZ_INS_CLGTE = 977 , SYSZ_INS_CLGTH = 978 , SYSZ_INS_CLGTHE = 979 , SYSZ_INS_CLGTL = 980 , SYSZ_INS_CLGTLE = 981 , SYSZ_INS_CLGTLH = 982 , SYSZ_INS_CLGTNE = 983 , SYSZ_INS_CLGTNH = 984 , SYSZ_INS_CLGTNHE = 985 , SYSZ_INS_CLGTNL = 986 , SYSZ_INS_CLGTNLE = 987 , SYSZ_INS_CLGTNLH = 988 , SYSZ_INS_CLGXTR = 989 , SYSZ_INS_CLHHR = 990 , SYSZ_INS_CLHLR = 991 , SYSZ_INS_CLIB = 992 , SYSZ_INS_CLIBE = 993 , SYSZ_INS_CLIBH = 994 , SYSZ_INS_CLIBHE = 995 , SYSZ_INS_CLIBL = 996 , SYSZ_INS_CLIBLE = 997 , SYSZ_INS_CLIBLH = 998 , SYSZ_INS_CLIBNE = 999 , SYSZ_INS_CLIBNH = 1000 , SYSZ_INS_CLIBNHE = 1001 , SYSZ_INS_CLIBNL = 1002 , SYSZ_INS_CLIBNLE = 1003 , SYSZ_INS_CLIBNLH = 1004 , SYSZ_INS_CLM = 1005 , SYSZ_INS_CLMH = 1006 , SYSZ_INS_CLMY = 1007 , SYSZ_INS_CLRB = 1008 , SYSZ_INS_CLRBE = 1009 , SYSZ_INS_CLRBH = 1010 , SYSZ_INS_CLRBHE = 1011 , SYSZ_INS_CLRBL = 1012 , SYSZ_INS_CLRBLE = 1013 , SYSZ_INS_CLRBLH = 1014 , SYSZ_INS_CLRBNE = 1015 , SYSZ_INS_CLRBNH = 1016 , SYSZ_INS_CLRBNHE = 1017 , SYSZ_INS_CLRBNL = 1018 , SYSZ_INS_CLRBNLE = 1019 , SYSZ_INS_CLRBNLH = 1020 , SYSZ_INS_CLRT = 1021 , SYSZ_INS_CLRTE = 1022 , SYSZ_INS_CLRTH = 1023 , SYSZ_INS_CLRTHE = 1024 , SYSZ_INS_CLRTL = 1025 , SYSZ_INS_CLRTLE = 1026 , SYSZ_INS_CLRTLH = 1027 , SYSZ_INS_CLRTNE = 1028 , SYSZ_INS_CLRTNH = 1029 , SYSZ_INS_CLRTNHE = 1030 , SYSZ_INS_CLRTNL = 1031 , SYSZ_INS_CLRTNLE = 1032 , SYSZ_INS_CLRTNLH = 1033 , SYSZ_INS_CLT = 1034 , SYSZ_INS_CLTE = 1035 , SYSZ_INS_CLTH = 1036 , SYSZ_INS_CLTHE = 1037 , SYSZ_INS_CLTL = 1038 , SYSZ_INS_CLTLE = 1039 , SYSZ_INS_CLTLH = 1040 , SYSZ_INS_CLTNE = 1041 , SYSZ_INS_CLTNH = 1042 , SYSZ_INS_CLTNHE = 1043 , SYSZ_INS_CLTNL = 1044 , SYSZ_INS_CLTNLE = 1045 , SYSZ_INS_CLTNLH = 1046 , SYSZ_INS_CMPSC = 1047 , SYSZ_INS_CP = 1048 , SYSZ_INS_CPDT = 1049 , SYSZ_INS_CPXT = 1050 , SYSZ_INS_CPYA = 1051 , SYSZ_INS_CRB = 1052 , SYSZ_INS_CRBE = 1053 , SYSZ_INS_CRBH = 1054 , SYSZ_INS_CRBHE = 1055 , SYSZ_INS_CRBL = 1056 , SYSZ_INS_CRBLE = 1057 , SYSZ_INS_CRBLH = 1058 , SYSZ_INS_CRBNE = 1059 , SYSZ_INS_CRBNH = 1060 , SYSZ_INS_CRBNHE = 1061 , SYSZ_INS_CRBNL = 1062 , SYSZ_INS_CRBNLE = 1063 , SYSZ_INS_CRBNLH = 1064 , SYSZ_INS_CRDTE = 1065 , SYSZ_INS_CRT = 1066 , SYSZ_INS_CRTE = 1067 , SYSZ_INS_CRTH = 1068 , SYSZ_INS_CRTHE = 1069 , SYSZ_INS_CRTL = 1070 , SYSZ_INS_CRTLE = 1071 , SYSZ_INS_CRTLH = 1072 , SYSZ_INS_CRTNE = 1073 , SYSZ_INS_CRTNH = 1074 , SYSZ_INS_CRTNHE = 1075 , SYSZ_INS_CRTNL = 1076 , SYSZ_INS_CRTNLE = 1077 , SYSZ_INS_CRTNLH = 1078 , SYSZ_INS_CSCH = 1079 , SYSZ_INS_CSDTR = 1080 , SYSZ_INS_CSP = 1081 , SYSZ_INS_CSPG = 1082 , SYSZ_INS_CSST = 1083 , SYSZ_INS_CSXTR = 1084 , SYSZ_INS_CU12 = 1085 , SYSZ_INS_CU14 = 1086 , SYSZ_INS_CU21 = 1087 , SYSZ_INS_CU24 = 1088 , SYSZ_INS_CU41 = 1089 , SYSZ_INS_CU42 = 1090 , SYSZ_INS_CUDTR = 1091 , SYSZ_INS_CUSE = 1092 , SYSZ_INS_CUTFU = 1093 , SYSZ_INS_CUUTF = 1094 , SYSZ_INS_CUXTR = 1095 , SYSZ_INS_CVB = 1096 , SYSZ_INS_CVBG = 1097 , SYSZ_INS_CVBY = 1098 , SYSZ_INS_CVD = 1099 , SYSZ_INS_CVDG = 1100 , SYSZ_INS_CVDY = 1101 , SYSZ_INS_CXFBRA = 1102 , SYSZ_INS_CXFR = 1103 , SYSZ_INS_CXFTR = 1104 , SYSZ_INS_CXGBRA = 1105 , SYSZ_INS_CXGR = 1106 , SYSZ_INS_CXGTR = 1107 , SYSZ_INS_CXGTRA = 1108 , SYSZ_INS_CXLFTR = 1109 , SYSZ_INS_CXLGTR = 1110 , SYSZ_INS_CXPT = 1111 , SYSZ_INS_CXR = 1112 , SYSZ_INS_CXSTR = 1113 , SYSZ_INS_CXTR = 1114 , SYSZ_INS_CXUTR = 1115 , SYSZ_INS_CXZT = 1116 , SYSZ_INS_CZDT = 1117 , SYSZ_INS_CZXT = 1118 , SYSZ_INS_D = 1119 , SYSZ_INS_DD = 1120 , SYSZ_INS_DDR = 1121 , SYSZ_INS_DDTR = 1122 , SYSZ_INS_DDTRA = 1123 , SYSZ_INS_DE = 1124 , SYSZ_INS_DER = 1125 , SYSZ_INS_DIAG = 1126 , SYSZ_INS_DIDBR = 1127 , SYSZ_INS_DIEBR = 1128 , SYSZ_INS_DP = 1129 , SYSZ_INS_DR = 1130 , SYSZ_INS_DXR = 1131 , SYSZ_INS_DXTR = 1132 , SYSZ_INS_DXTRA = 1133 , SYSZ_INS_ECAG = 1134 , SYSZ_INS_ECCTR = 1135 , SYSZ_INS_ECPGA = 1136 , SYSZ_INS_ECTG = 1137 , SYSZ_INS_ED = 1138 , SYSZ_INS_EDMK = 1139 , SYSZ_INS_EEDTR = 1140 , SYSZ_INS_EEXTR = 1141 , SYSZ_INS_EFPC = 1142 , SYSZ_INS_EPAIR = 1143 , SYSZ_INS_EPAR = 1144 , SYSZ_INS_EPCTR = 1145 , SYSZ_INS_EPSW = 1146 , SYSZ_INS_EREG = 1147 , SYSZ_INS_EREGG = 1148 , SYSZ_INS_ESAIR = 1149 , SYSZ_INS_ESAR = 1150 , SYSZ_INS_ESDTR = 1151 , SYSZ_INS_ESEA = 1152 , SYSZ_INS_ESTA = 1153 , SYSZ_INS_ESXTR = 1154 , SYSZ_INS_ETND = 1155 , SYSZ_INS_EX = 1156 , SYSZ_INS_EXRL = 1157 , SYSZ_INS_FIDR = 1158 , SYSZ_INS_FIDTR = 1159 , SYSZ_INS_FIER = 1160 , SYSZ_INS_FIXR = 1161 , SYSZ_INS_FIXTR = 1162 , SYSZ_INS_HDR = 1163 , SYSZ_INS_HER = 1164 , SYSZ_INS_HSCH = 1165 , SYSZ_INS_IAC = 1166 , SYSZ_INS_ICM = 1167 , SYSZ_INS_ICMH = 1168 , SYSZ_INS_ICMY = 1169 , SYSZ_INS_IDTE = 1170 , SYSZ_INS_IEDTR = 1171 , SYSZ_INS_IEXTR = 1172 , SYSZ_INS_IPK = 1173 , SYSZ_INS_IPTE = 1174 , SYSZ_INS_IRBM = 1175 , SYSZ_INS_ISKE = 1176 , SYSZ_INS_IVSK = 1177 , SYSZ_INS_JGM = 1178 , SYSZ_INS_JGNM = 1179 , SYSZ_INS_JGNP = 1180 , SYSZ_INS_JGNZ = 1181 , SYSZ_INS_JGP = 1182 , SYSZ_INS_JGZ = 1183 , SYSZ_INS_JM = 1184 , SYSZ_INS_JNM = 1185 , SYSZ_INS_JNP = 1186 , SYSZ_INS_JNZ = 1187 , SYSZ_INS_JP = 1188 , SYSZ_INS_JZ = 1189 , SYSZ_INS_KDB = 1190 , SYSZ_INS_KDBR = 1191 , SYSZ_INS_KDTR = 1192 , SYSZ_INS_KEB = 1193 , SYSZ_INS_KEBR = 1194 , SYSZ_INS_KIMD = 1195 , SYSZ_INS_KLMD = 1196 , SYSZ_INS_KM = 1197 , SYSZ_INS_KMA = 1198 , SYSZ_INS_KMAC = 1199 , SYSZ_INS_KMC = 1200 , SYSZ_INS_KMCTR = 1201 , SYSZ_INS_KMF = 1202 , SYSZ_INS_KMO = 1203 , SYSZ_INS_KXBR = 1204 , SYSZ_INS_KXTR = 1205 , SYSZ_INS_LAE = 1206 , SYSZ_INS_LAEY = 1207 , SYSZ_INS_LAM = 1208 , SYSZ_INS_LAMY = 1209 , SYSZ_INS_LASP = 1210 , SYSZ_INS_LAT = 1211 , SYSZ_INS_LCBB = 1212 , SYSZ_INS_LCCTL = 1213 , SYSZ_INS_LCDFR = 1214 , SYSZ_INS_LCDR = 1215 , SYSZ_INS_LCER = 1216 , SYSZ_INS_LCTL = 1217 , SYSZ_INS_LCTLG = 1218 , SYSZ_INS_LCXR = 1219 , SYSZ_INS_LDE = 1220 , SYSZ_INS_LDER = 1221 , SYSZ_INS_LDETR = 1222 , SYSZ_INS_LDXR = 1223 , SYSZ_INS_LDXTR = 1224 , SYSZ_INS_LEDR = 1225 , SYSZ_INS_LEDTR = 1226 , SYSZ_INS_LEXR = 1227 , SYSZ_INS_LFAS = 1228 , SYSZ_INS_LFHAT = 1229 , SYSZ_INS_LFPC = 1230 , SYSZ_INS_LGAT = 1231 , SYSZ_INS_LGG = 1232 , SYSZ_INS_LGSC = 1233 , SYSZ_INS_LLGFAT = 1234 , SYSZ_INS_LLGFSG = 1235 , SYSZ_INS_LLGT = 1236 , SYSZ_INS_LLGTAT = 1237 , SYSZ_INS_LLGTR = 1238 , SYSZ_INS_LLZRGF = 1239 , SYSZ_INS_LM = 1240 , SYSZ_INS_LMD = 1241 , SYSZ_INS_LMH = 1242 , SYSZ_INS_LMY = 1243 , SYSZ_INS_LNDFR = 1244 , SYSZ_INS_LNDR = 1245 , SYSZ_INS_LNER = 1246 , SYSZ_INS_LNXR = 1247 , SYSZ_INS_LOCFH = 1248 , SYSZ_INS_LOCFHE = 1249 , SYSZ_INS_LOCFHH = 1250 , SYSZ_INS_LOCFHHE = 1251 , SYSZ_INS_LOCFHL = 1252 , SYSZ_INS_LOCFHLE = 1253 , SYSZ_INS_LOCFHLH = 1254 , SYSZ_INS_LOCFHM = 1255 , SYSZ_INS_LOCFHNE = 1256 , SYSZ_INS_LOCFHNH = 1257 , SYSZ_INS_LOCFHNHE = 1258 , SYSZ_INS_LOCFHNL = 1259 , SYSZ_INS_LOCFHNLE = 1260 , SYSZ_INS_LOCFHNLH = 1261 , SYSZ_INS_LOCFHNM = 1262 , SYSZ_INS_LOCFHNO = 1263 , SYSZ_INS_LOCFHNP = 1264 , SYSZ_INS_LOCFHNZ = 1265 , SYSZ_INS_LOCFHO = 1266 , SYSZ_INS_LOCFHP = 1267 , SYSZ_INS_LOCFHR = 1268 , SYSZ_INS_LOCFHRE = 1269 , SYSZ_INS_LOCFHRH = 1270 , SYSZ_INS_LOCFHRHE = 1271 , SYSZ_INS_LOCFHRL = 1272 , SYSZ_INS_LOCFHRLE = 1273 , SYSZ_INS_LOCFHRLH = 1274 , SYSZ_INS_LOCFHRM = 1275 , SYSZ_INS_LOCFHRNE = 1276 , SYSZ_INS_LOCFHRNH = 1277 , SYSZ_INS_LOCFHRNHE = 1278 , SYSZ_INS_LOCFHRNL = 1279 , SYSZ_INS_LOCFHRNLE = 1280 , SYSZ_INS_LOCFHRNLH = 1281 , SYSZ_INS_LOCFHRNM = 1282 , SYSZ_INS_LOCFHRNO = 1283 , SYSZ_INS_LOCFHRNP = 1284 , SYSZ_INS_LOCFHRNZ = 1285 , SYSZ_INS_LOCFHRO = 1286 , SYSZ_INS_LOCFHRP = 1287 , SYSZ_INS_LOCFHRZ = 1288 , SYSZ_INS_LOCFHZ = 1289 , SYSZ_INS_LOCGHI = 1290 , SYSZ_INS_LOCGHIE = 1291 , SYSZ_INS_LOCGHIH = 1292 , SYSZ_INS_LOCGHIHE = 1293 , SYSZ_INS_LOCGHIL = 1294 , SYSZ_INS_LOCGHILE = 1295 , SYSZ_INS_LOCGHILH = 1296 , SYSZ_INS_LOCGHIM = 1297 , SYSZ_INS_LOCGHINE = 1298 , SYSZ_INS_LOCGHINH = 1299 , SYSZ_INS_LOCGHINHE = 1300 , SYSZ_INS_LOCGHINL = 1301 , SYSZ_INS_LOCGHINLE = 1302 , SYSZ_INS_LOCGHINLH = 1303 , SYSZ_INS_LOCGHINM = 1304 , SYSZ_INS_LOCGHINO = 1305 , SYSZ_INS_LOCGHINP = 1306 , SYSZ_INS_LOCGHINZ = 1307 , SYSZ_INS_LOCGHIO = 1308 , SYSZ_INS_LOCGHIP = 1309 , SYSZ_INS_LOCGHIZ = 1310 , SYSZ_INS_LOCGM = 1311 , SYSZ_INS_LOCGNM = 1312 , SYSZ_INS_LOCGNP = 1313 , SYSZ_INS_LOCGNZ = 1314 , SYSZ_INS_LOCGP = 1315 , SYSZ_INS_LOCGRM = 1316 , SYSZ_INS_LOCGRNM = 1317 , SYSZ_INS_LOCGRNP = 1318 , SYSZ_INS_LOCGRNZ = 1319 , SYSZ_INS_LOCGRP = 1320 , SYSZ_INS_LOCGRZ = 1321 , SYSZ_INS_LOCGZ = 1322 , SYSZ_INS_LOCHHI = 1323 , SYSZ_INS_LOCHHIE = 1324 , SYSZ_INS_LOCHHIH = 1325 , SYSZ_INS_LOCHHIHE = 1326 , SYSZ_INS_LOCHHIL = 1327 , SYSZ_INS_LOCHHILE = 1328 , SYSZ_INS_LOCHHILH = 1329 , SYSZ_INS_LOCHHIM = 1330 , SYSZ_INS_LOCHHINE = 1331 , SYSZ_INS_LOCHHINH = 1332 , SYSZ_INS_LOCHHINHE = 1333 , SYSZ_INS_LOCHHINL = 1334 , SYSZ_INS_LOCHHINLE = 1335 , SYSZ_INS_LOCHHINLH = 1336 , SYSZ_INS_LOCHHINM = 1337 , SYSZ_INS_LOCHHINO = 1338 , SYSZ_INS_LOCHHINP = 1339 , SYSZ_INS_LOCHHINZ = 1340 , SYSZ_INS_LOCHHIO = 1341 , SYSZ_INS_LOCHHIP = 1342 , SYSZ_INS_LOCHHIZ = 1343 , SYSZ_INS_LOCHI = 1344 , SYSZ_INS_LOCHIE = 1345 , SYSZ_INS_LOCHIH = 1346 , SYSZ_INS_LOCHIHE = 1347 , SYSZ_INS_LOCHIL = 1348 , SYSZ_INS_LOCHILE = 1349 , SYSZ_INS_LOCHILH = 1350 , SYSZ_INS_LOCHIM = 1351 , SYSZ_INS_LOCHINE = 1352 , SYSZ_INS_LOCHINH = 1353 , SYSZ_INS_LOCHINHE = 1354 , SYSZ_INS_LOCHINL = 1355 , SYSZ_INS_LOCHINLE = 1356 , SYSZ_INS_LOCHINLH = 1357 , SYSZ_INS_LOCHINM = 1358 , SYSZ_INS_LOCHINO = 1359 , SYSZ_INS_LOCHINP = 1360 , SYSZ_INS_LOCHINZ = 1361 , SYSZ_INS_LOCHIO = 1362 , SYSZ_INS_LOCHIP = 1363 , SYSZ_INS_LOCHIZ = 1364 , SYSZ_INS_LOCM = 1365 , SYSZ_INS_LOCNM = 1366 , SYSZ_INS_LOCNP = 1367 , SYSZ_INS_LOCNZ = 1368 , SYSZ_INS_LOCP = 1369 , SYSZ_INS_LOCRM = 1370 , SYSZ_INS_LOCRNM = 1371 , SYSZ_INS_LOCRNP = 1372 , SYSZ_INS_LOCRNZ = 1373 , SYSZ_INS_LOCRP = 1374 , SYSZ_INS_LOCRZ = 1375 , SYSZ_INS_LOCZ = 1376 , SYSZ_INS_LPCTL = 1377 , SYSZ_INS_LPD = 1378 , SYSZ_INS_LPDFR = 1379 , SYSZ_INS_LPDG = 1380 , SYSZ_INS_LPDR = 1381 , SYSZ_INS_LPER = 1382 , SYSZ_INS_LPP = 1383 , SYSZ_INS_LPQ = 1384 , SYSZ_INS_LPSW = 1385 , SYSZ_INS_LPSWE = 1386 , SYSZ_INS_LPTEA = 1387 , SYSZ_INS_LPXR = 1388 , SYSZ_INS_LRA = 1389 , SYSZ_INS_LRAG = 1390 , SYSZ_INS_LRAY = 1391 , SYSZ_INS_LRDR = 1392 , SYSZ_INS_LRER = 1393 , SYSZ_INS_LRVH = 1394 , SYSZ_INS_LSCTL = 1395 , SYSZ_INS_LTDR = 1396 , SYSZ_INS_LTDTR = 1397 , SYSZ_INS_LTER = 1398 , SYSZ_INS_LTXR = 1399 , SYSZ_INS_LTXTR = 1400 , SYSZ_INS_LURA = 1401 , SYSZ_INS_LURAG = 1402 , SYSZ_INS_LXD = 1403 , SYSZ_INS_LXDR = 1404 , SYSZ_INS_LXDTR = 1405 , SYSZ_INS_LXE = 1406 , SYSZ_INS_LXER = 1407 , SYSZ_INS_LZRF = 1408 , SYSZ_INS_LZRG = 1409 , SYSZ_INS_M = 1410 , SYSZ_INS_MAD = 1411 , SYSZ_INS_MADR = 1412 , SYSZ_INS_MAE = 1413 , SYSZ_INS_MAER = 1414 , SYSZ_INS_MAY = 1415 , SYSZ_INS_MAYH = 1416 , SYSZ_INS_MAYHR = 1417 , SYSZ_INS_MAYL = 1418 , SYSZ_INS_MAYLR = 1419 , SYSZ_INS_MAYR = 1420 , SYSZ_INS_MC = 1421 , SYSZ_INS_MD = 1422 , SYSZ_INS_MDE = 1423 , SYSZ_INS_MDER = 1424 , SYSZ_INS_MDR = 1425 , SYSZ_INS_MDTR = 1426 , SYSZ_INS_MDTRA = 1427 , SYSZ_INS_ME = 1428 , SYSZ_INS_MEE = 1429 , SYSZ_INS_MEER = 1430 , SYSZ_INS_MER = 1431 , SYSZ_INS_MFY = 1432 , SYSZ_INS_MG = 1433 , SYSZ_INS_MGH = 1434 , SYSZ_INS_MGRK = 1435 , SYSZ_INS_ML = 1436 , SYSZ_INS_MLR = 1437 , SYSZ_INS_MP = 1438 , SYSZ_INS_MR = 1439 , SYSZ_INS_MSC = 1440 , SYSZ_INS_MSCH = 1441 , SYSZ_INS_MSD = 1442 , SYSZ_INS_MSDR = 1443 , SYSZ_INS_MSE = 1444 , SYSZ_INS_MSER = 1445 , SYSZ_INS_MSGC = 1446 , SYSZ_INS_MSGRKC = 1447 , SYSZ_INS_MSRKC = 1448 , SYSZ_INS_MSTA = 1449 , SYSZ_INS_MVCDK = 1450 , SYSZ_INS_MVCIN = 1451 , SYSZ_INS_MVCK = 1452 , SYSZ_INS_MVCL = 1453 , SYSZ_INS_MVCLE = 1454 , SYSZ_INS_MVCLU = 1455 , SYSZ_INS_MVCOS = 1456 , SYSZ_INS_MVCP = 1457 , SYSZ_INS_MVCS = 1458 , SYSZ_INS_MVCSK = 1459 , SYSZ_INS_MVN = 1460 , SYSZ_INS_MVO = 1461 , SYSZ_INS_MVPG = 1462 , SYSZ_INS_MVZ = 1463 , SYSZ_INS_MXD = 1464 , SYSZ_INS_MXDR = 1465 , SYSZ_INS_MXR = 1466 , SYSZ_INS_MXTR = 1467 , SYSZ_INS_MXTRA = 1468 , SYSZ_INS_MY = 1469 , SYSZ_INS_MYH = 1470 , SYSZ_INS_MYHR = 1471 , SYSZ_INS_MYL = 1472 , SYSZ_INS_MYLR = 1473 , SYSZ_INS_MYR = 1474 , SYSZ_INS_NIAI = 1475 , SYSZ_INS_NTSTG = 1476 , SYSZ_INS_PACK = 1477 , SYSZ_INS_PALB = 1478 , SYSZ_INS_PC = 1479 , SYSZ_INS_PCC = 1480 , SYSZ_INS_PCKMO = 1481 , SYSZ_INS_PFMF = 1482 , SYSZ_INS_PFPO = 1483 , SYSZ_INS_PGIN = 1484 , SYSZ_INS_PGOUT = 1485 , SYSZ_INS_PKA = 1486 , SYSZ_INS_PKU = 1487 , SYSZ_INS_PLO = 1488 , SYSZ_INS_POPCNT = 1489 , SYSZ_INS_PPA = 1490 , SYSZ_INS_PPNO = 1491 , SYSZ_INS_PR = 1492 , SYSZ_INS_PRNO = 1493 , SYSZ_INS_PT = 1494 , SYSZ_INS_PTF = 1495 , SYSZ_INS_PTFF = 1496 , SYSZ_INS_PTI = 1497 , SYSZ_INS_PTLB = 1498 , SYSZ_INS_QADTR = 1499 , SYSZ_INS_QAXTR = 1500 , SYSZ_INS_QCTRI = 1501 , SYSZ_INS_QSI = 1502 , SYSZ_INS_RCHP = 1503 , SYSZ_INS_RISBGN = 1504 , SYSZ_INS_RP = 1505 , SYSZ_INS_RRBE = 1506 , SYSZ_INS_RRBM = 1507 , SYSZ_INS_RRDTR = 1508 , SYSZ_INS_RRXTR = 1509 , SYSZ_INS_RSCH = 1510 , SYSZ_INS_SAC = 1511 , SYSZ_INS_SACF = 1512 , SYSZ_INS_SAL = 1513 , SYSZ_INS_SAM24 = 1514 , SYSZ_INS_SAM31 = 1515 , SYSZ_INS_SAM64 = 1516 , SYSZ_INS_SAR = 1517 , SYSZ_INS_SCCTR = 1518 , SYSZ_INS_SCHM = 1519 , SYSZ_INS_SCK = 1520 , SYSZ_INS_SCKC = 1521 , SYSZ_INS_SCKPF = 1522 , SYSZ_INS_SD = 1523 , SYSZ_INS_SDR = 1524 , SYSZ_INS_SDTR = 1525 , SYSZ_INS_SDTRA = 1526 , SYSZ_INS_SE = 1527 , SYSZ_INS_SER = 1528 , SYSZ_INS_SFASR = 1529 , SYSZ_INS_SFPC = 1530 , SYSZ_INS_SGH = 1531 , SYSZ_INS_SHHHR = 1532 , SYSZ_INS_SHHLR = 1533 , SYSZ_INS_SIE = 1534 , SYSZ_INS_SIGA = 1535 , SYSZ_INS_SIGP = 1536 , SYSZ_INS_SLA = 1537 , SYSZ_INS_SLAG = 1538 , SYSZ_INS_SLAK = 1539 , SYSZ_INS_SLDA = 1540 , SYSZ_INS_SLDL = 1541 , SYSZ_INS_SLDT = 1542 , SYSZ_INS_SLHHHR = 1543 , SYSZ_INS_SLHHLR = 1544 , SYSZ_INS_SLXT = 1545 , SYSZ_INS_SP = 1546 , SYSZ_INS_SPCTR = 1547 , SYSZ_INS_SPKA = 1548 , SYSZ_INS_SPM = 1549 , SYSZ_INS_SPT = 1550 , SYSZ_INS_SPX = 1551 , SYSZ_INS_SQD = 1552 , SYSZ_INS_SQDR = 1553 , SYSZ_INS_SQE = 1554 , SYSZ_INS_SQER = 1555 , SYSZ_INS_SQXR = 1556 , SYSZ_INS_SRDA = 1557 , SYSZ_INS_SRDL = 1558 , SYSZ_INS_SRDT = 1559 , SYSZ_INS_SRNM = 1560 , SYSZ_INS_SRNMB = 1561 , SYSZ_INS_SRNMT = 1562 , SYSZ_INS_SRP = 1563 , SYSZ_INS_SRSTU = 1564 , SYSZ_INS_SRXT = 1565 , SYSZ_INS_SSAIR = 1566 , SYSZ_INS_SSAR = 1567 , SYSZ_INS_SSCH = 1568 , SYSZ_INS_SSKE = 1569 , SYSZ_INS_SSM = 1570 , SYSZ_INS_STAM = 1571 , SYSZ_INS_STAMY = 1572 , SYSZ_INS_STAP = 1573 , SYSZ_INS_STCK = 1574 , SYSZ_INS_STCKC = 1575 , SYSZ_INS_STCKE = 1576 , SYSZ_INS_STCKF = 1577 , SYSZ_INS_STCM = 1578 , SYSZ_INS_STCMH = 1579 , SYSZ_INS_STCMY = 1580 , SYSZ_INS_STCPS = 1581 , SYSZ_INS_STCRW = 1582 , SYSZ_INS_STCTG = 1583 , SYSZ_INS_STCTL = 1584 , SYSZ_INS_STFL = 1585 , SYSZ_INS_STFLE = 1586 , SYSZ_INS_STFPC = 1587 , SYSZ_INS_STGSC = 1588 , SYSZ_INS_STIDP = 1589 , SYSZ_INS_STM = 1590 , SYSZ_INS_STMH = 1591 , SYSZ_INS_STMY = 1592 , SYSZ_INS_STNSM = 1593 , SYSZ_INS_STOCFH = 1594 , SYSZ_INS_STOCFHE = 1595 , SYSZ_INS_STOCFHH = 1596 , SYSZ_INS_STOCFHHE = 1597 , SYSZ_INS_STOCFHL = 1598 , SYSZ_INS_STOCFHLE = 1599 , SYSZ_INS_STOCFHLH = 1600 , SYSZ_INS_STOCFHM = 1601 , SYSZ_INS_STOCFHNE = 1602 , SYSZ_INS_STOCFHNH = 1603 , SYSZ_INS_STOCFHNHE = 1604 , SYSZ_INS_STOCFHNL = 1605 , SYSZ_INS_STOCFHNLE = 1606 , SYSZ_INS_STOCFHNLH = 1607 , SYSZ_INS_STOCFHNM = 1608 , SYSZ_INS_STOCFHNO = 1609 , SYSZ_INS_STOCFHNP = 1610 , SYSZ_INS_STOCFHNZ = 1611 , SYSZ_INS_STOCFHO = 1612 , SYSZ_INS_STOCFHP = 1613 , SYSZ_INS_STOCFHZ = 1614 , SYSZ_INS_STOCGM = 1615 , SYSZ_INS_STOCGNM = 1616 , SYSZ_INS_STOCGNP = 1617 , SYSZ_INS_STOCGNZ = 1618 , SYSZ_INS_STOCGP = 1619 , SYSZ_INS_STOCGZ = 1620 , SYSZ_INS_STOCM = 1621 , SYSZ_INS_STOCNM = 1622 , SYSZ_INS_STOCNP = 1623 , SYSZ_INS_STOCNZ = 1624 , SYSZ_INS_STOCP = 1625 , SYSZ_INS_STOCZ = 1626 , SYSZ_INS_STOSM = 1627 , SYSZ_INS_STPQ = 1628 , SYSZ_INS_STPT = 1629 , SYSZ_INS_STPX = 1630 , SYSZ_INS_STRAG = 1631 , SYSZ_INS_STRVH = 1632 , SYSZ_INS_STSCH = 1633 , SYSZ_INS_STSI = 1634 , SYSZ_INS_STURA = 1635 , SYSZ_INS_STURG = 1636 , SYSZ_INS_SU = 1637 , SYSZ_INS_SUR = 1638 , SYSZ_INS_SVC = 1639 , SYSZ_INS_SW = 1640 , SYSZ_INS_SWR = 1641 , SYSZ_INS_SXR = 1642 , SYSZ_INS_SXTR = 1643 , SYSZ_INS_SXTRA = 1644 , SYSZ_INS_TABORT = 1645 , SYSZ_INS_TAM = 1646 , SYSZ_INS_TAR = 1647 , SYSZ_INS_TB = 1648 , SYSZ_INS_TBDR = 1649 , SYSZ_INS_TBEDR = 1650 , SYSZ_INS_TBEGIN = 1651 , SYSZ_INS_TBEGINC = 1652 , SYSZ_INS_TCDB = 1653 , SYSZ_INS_TCEB = 1654 , SYSZ_INS_TCXB = 1655 , SYSZ_INS_TDCDT = 1656 , SYSZ_INS_TDCET = 1657 , SYSZ_INS_TDCXT = 1658 , SYSZ_INS_TDGDT = 1659 , SYSZ_INS_TDGET = 1660 , SYSZ_INS_TDGXT = 1661 , SYSZ_INS_TEND = 1662 , SYSZ_INS_THDER = 1663 , SYSZ_INS_THDR = 1664 , SYSZ_INS_TP = 1665 , SYSZ_INS_TPI = 1666 , SYSZ_INS_TPROT = 1667 , SYSZ_INS_TR = 1668 , SYSZ_INS_TRACE = 1669 , SYSZ_INS_TRACG = 1670 , SYSZ_INS_TRAP2 = 1671 , SYSZ_INS_TRAP4 = 1672 , SYSZ_INS_TRE = 1673 , SYSZ_INS_TROO = 1674 , SYSZ_INS_TROT = 1675 , SYSZ_INS_TRT = 1676 , SYSZ_INS_TRTE = 1677 , SYSZ_INS_TRTO = 1678 , SYSZ_INS_TRTR = 1679 , SYSZ_INS_TRTRE = 1680 , SYSZ_INS_TRTT = 1681 , SYSZ_INS_TS = 1682 , SYSZ_INS_TSCH = 1683 , SYSZ_INS_UNPK = 1684 , SYSZ_INS_UNPKA = 1685 , SYSZ_INS_UNPKU = 1686 , SYSZ_INS_UPT = 1687 , SYSZ_INS_VA = 1688 , SYSZ_INS_VAB = 1689 , SYSZ_INS_VAC = 1690 , SYSZ_INS_VACC = 1691 , SYSZ_INS_VACCB = 1692 , SYSZ_INS_VACCC = 1693 , SYSZ_INS_VACCCQ = 1694 , SYSZ_INS_VACCF = 1695 , SYSZ_INS_VACCG = 1696 , SYSZ_INS_VACCH = 1697 , SYSZ_INS_VACCQ = 1698 , SYSZ_INS_VACQ = 1699 , SYSZ_INS_VAF = 1700 , SYSZ_INS_VAG = 1701 , SYSZ_INS_VAH = 1702 , SYSZ_INS_VAP = 1703 , SYSZ_INS_VAQ = 1704 , SYSZ_INS_VAVG = 1705 , SYSZ_INS_VAVGB = 1706 , SYSZ_INS_VAVGF = 1707 , SYSZ_INS_VAVGG = 1708 , SYSZ_INS_VAVGH = 1709 , SYSZ_INS_VAVGL = 1710 , SYSZ_INS_VAVGLB = 1711 , SYSZ_INS_VAVGLF = 1712 , SYSZ_INS_VAVGLG = 1713 , SYSZ_INS_VAVGLH = 1714 , SYSZ_INS_VBPERM = 1715 , SYSZ_INS_VCDG = 1716 , SYSZ_INS_VCDGB = 1717 , SYSZ_INS_VCDLG = 1718 , SYSZ_INS_VCDLGB = 1719 , SYSZ_INS_VCEQ = 1720 , SYSZ_INS_VCEQB = 1721 , SYSZ_INS_VCEQBS = 1722 , SYSZ_INS_VCEQF = 1723 , SYSZ_INS_VCEQFS = 1724 , SYSZ_INS_VCEQG = 1725 , SYSZ_INS_VCEQGS = 1726 , SYSZ_INS_VCEQH = 1727 , SYSZ_INS_VCEQHS = 1728 , SYSZ_INS_VCGD = 1729 , SYSZ_INS_VCGDB = 1730 , SYSZ_INS_VCH = 1731 , SYSZ_INS_VCHB = 1732 , SYSZ_INS_VCHBS = 1733 , SYSZ_INS_VCHF = 1734 , SYSZ_INS_VCHFS = 1735 , SYSZ_INS_VCHG = 1736 , SYSZ_INS_VCHGS = 1737 , SYSZ_INS_VCHH = 1738 , SYSZ_INS_VCHHS = 1739 , SYSZ_INS_VCHL = 1740 , SYSZ_INS_VCHLB = 1741 , SYSZ_INS_VCHLBS = 1742 , SYSZ_INS_VCHLF = 1743 , SYSZ_INS_VCHLFS = 1744 , SYSZ_INS_VCHLG = 1745 , SYSZ_INS_VCHLGS = 1746 , SYSZ_INS_VCHLH = 1747 , SYSZ_INS_VCHLHS = 1748 , SYSZ_INS_VCKSM = 1749 , SYSZ_INS_VCLGD = 1750 , SYSZ_INS_VCLGDB = 1751 , SYSZ_INS_VCLZ = 1752 , SYSZ_INS_VCLZB = 1753 , SYSZ_INS_VCLZF = 1754 , SYSZ_INS_VCLZG = 1755 , SYSZ_INS_VCLZH = 1756 , SYSZ_INS_VCP = 1757 , SYSZ_INS_VCTZ = 1758 , SYSZ_INS_VCTZB = 1759 , SYSZ_INS_VCTZF = 1760 , SYSZ_INS_VCTZG = 1761 , SYSZ_INS_VCTZH = 1762 , SYSZ_INS_VCVB = 1763 , SYSZ_INS_VCVBG = 1764 , SYSZ_INS_VCVD = 1765 , SYSZ_INS_VCVDG = 1766 , SYSZ_INS_VDP = 1767 , SYSZ_INS_VEC = 1768 , SYSZ_INS_VECB = 1769 , SYSZ_INS_VECF = 1770 , SYSZ_INS_VECG = 1771 , SYSZ_INS_VECH = 1772 , SYSZ_INS_VECL = 1773 , SYSZ_INS_VECLB = 1774 , SYSZ_INS_VECLF = 1775 , SYSZ_INS_VECLG = 1776 , SYSZ_INS_VECLH = 1777 , SYSZ_INS_VERIM = 1778 , SYSZ_INS_VERIMB = 1779 , SYSZ_INS_VERIMF = 1780 , SYSZ_INS_VERIMG = 1781 , SYSZ_INS_VERIMH = 1782 , SYSZ_INS_VERLL = 1783 , SYSZ_INS_VERLLB = 1784 , SYSZ_INS_VERLLF = 1785 , SYSZ_INS_VERLLG = 1786 , SYSZ_INS_VERLLH = 1787 , SYSZ_INS_VERLLV = 1788 , SYSZ_INS_VERLLVB = 1789 , SYSZ_INS_VERLLVF = 1790 , SYSZ_INS_VERLLVG = 1791 , SYSZ_INS_VERLLVH = 1792 , SYSZ_INS_VESL = 1793 , SYSZ_INS_VESLB = 1794 , SYSZ_INS_VESLF = 1795 , SYSZ_INS_VESLG = 1796 , SYSZ_INS_VESLH = 1797 , SYSZ_INS_VESLV = 1798 , SYSZ_INS_VESLVB = 1799 , SYSZ_INS_VESLVF = 1800 , SYSZ_INS_VESLVG = 1801 , SYSZ_INS_VESLVH = 1802 , SYSZ_INS_VESRA = 1803 , SYSZ_INS_VESRAB = 1804 , SYSZ_INS_VESRAF = 1805 , SYSZ_INS_VESRAG = 1806 , SYSZ_INS_VESRAH = 1807 , SYSZ_INS_VESRAV = 1808 , SYSZ_INS_VESRAVB = 1809 , SYSZ_INS_VESRAVF = 1810 , SYSZ_INS_VESRAVG = 1811 , SYSZ_INS_VESRAVH = 1812 , SYSZ_INS_VESRL = 1813 , SYSZ_INS_VESRLB = 1814 , SYSZ_INS_VESRLF = 1815 , SYSZ_INS_VESRLG = 1816 , SYSZ_INS_VESRLH = 1817 , SYSZ_INS_VESRLV = 1818 , SYSZ_INS_VESRLVB = 1819 , SYSZ_INS_VESRLVF = 1820 , SYSZ_INS_VESRLVG = 1821 , SYSZ_INS_VESRLVH = 1822 , SYSZ_INS_VFA = 1823 , SYSZ_INS_VFADB = 1824 , SYSZ_INS_VFAE = 1825 , SYSZ_INS_VFAEB = 1826 , SYSZ_INS_VFAEBS = 1827 , SYSZ_INS_VFAEF = 1828 , SYSZ_INS_VFAEFS = 1829 , SYSZ_INS_VFAEH = 1830 , SYSZ_INS_VFAEHS = 1831 , SYSZ_INS_VFAEZB = 1832 , SYSZ_INS_VFAEZBS = 1833 , SYSZ_INS_VFAEZF = 1834 , SYSZ_INS_VFAEZFS = 1835 , SYSZ_INS_VFAEZH = 1836 , SYSZ_INS_VFAEZHS = 1837 , SYSZ_INS_VFASB = 1838 , SYSZ_INS_VFCE = 1839 , SYSZ_INS_VFCEDB = 1840 , SYSZ_INS_VFCEDBS = 1841 , SYSZ_INS_VFCESB = 1842 , SYSZ_INS_VFCESBS = 1843 , SYSZ_INS_VFCH = 1844 , SYSZ_INS_VFCHDB = 1845 , SYSZ_INS_VFCHDBS = 1846 , SYSZ_INS_VFCHE = 1847 , SYSZ_INS_VFCHEDB = 1848 , SYSZ_INS_VFCHEDBS = 1849 , SYSZ_INS_VFCHESB = 1850 , SYSZ_INS_VFCHESBS = 1851 , SYSZ_INS_VFCHSB = 1852 , SYSZ_INS_VFCHSBS = 1853 , SYSZ_INS_VFD = 1854 , SYSZ_INS_VFDDB = 1855 , SYSZ_INS_VFDSB = 1856 , SYSZ_INS_VFEE = 1857 , SYSZ_INS_VFEEB = 1858 , SYSZ_INS_VFEEBS = 1859 , SYSZ_INS_VFEEF = 1860 , SYSZ_INS_VFEEFS = 1861 , SYSZ_INS_VFEEH = 1862 , SYSZ_INS_VFEEHS = 1863 , SYSZ_INS_VFEEZB = 1864 , SYSZ_INS_VFEEZBS = 1865 , SYSZ_INS_VFEEZF = 1866 , SYSZ_INS_VFEEZFS = 1867 , SYSZ_INS_VFEEZH = 1868 , SYSZ_INS_VFEEZHS = 1869 , SYSZ_INS_VFENE = 1870 , SYSZ_INS_VFENEB = 1871 , SYSZ_INS_VFENEBS = 1872 , SYSZ_INS_VFENEF = 1873 , SYSZ_INS_VFENEFS = 1874 , SYSZ_INS_VFENEH = 1875 , SYSZ_INS_VFENEHS = 1876 , SYSZ_INS_VFENEZB = 1877 , SYSZ_INS_VFENEZBS = 1878 , SYSZ_INS_VFENEZF = 1879 , SYSZ_INS_VFENEZFS = 1880 , SYSZ_INS_VFENEZH = 1881 , SYSZ_INS_VFENEZHS = 1882 , SYSZ_INS_VFI = 1883 , SYSZ_INS_VFIDB = 1884 , SYSZ_INS_VFISB = 1885 , SYSZ_INS_VFKEDB = 1886 , SYSZ_INS_VFKEDBS = 1887 , SYSZ_INS_VFKESB = 1888 , SYSZ_INS_VFKESBS = 1889 , SYSZ_INS_VFKHDB = 1890 , SYSZ_INS_VFKHDBS = 1891 , SYSZ_INS_VFKHEDB = 1892 , SYSZ_INS_VFKHEDBS = 1893 , SYSZ_INS_VFKHESB = 1894 , SYSZ_INS_VFKHESBS = 1895 , SYSZ_INS_VFKHSB = 1896 , SYSZ_INS_VFKHSBS = 1897 , SYSZ_INS_VFLCDB = 1898 , SYSZ_INS_VFLCSB = 1899 , SYSZ_INS_VFLL = 1900 , SYSZ_INS_VFLLS = 1901 , SYSZ_INS_VFLNDB = 1902 , SYSZ_INS_VFLNSB = 1903 , SYSZ_INS_VFLPDB = 1904 , SYSZ_INS_VFLPSB = 1905 , SYSZ_INS_VFLR = 1906 , SYSZ_INS_VFLRD = 1907 , SYSZ_INS_VFM = 1908 , SYSZ_INS_VFMA = 1909 , SYSZ_INS_VFMADB = 1910 , SYSZ_INS_VFMASB = 1911 , SYSZ_INS_VFMAX = 1912 , SYSZ_INS_VFMAXDB = 1913 , SYSZ_INS_VFMAXSB = 1914 , SYSZ_INS_VFMDB = 1915 , SYSZ_INS_VFMIN = 1916 , SYSZ_INS_VFMINDB = 1917 , SYSZ_INS_VFMINSB = 1918 , SYSZ_INS_VFMS = 1919 , SYSZ_INS_VFMSB = 1920 , SYSZ_INS_VFMSDB = 1921 , SYSZ_INS_VFMSSB = 1922 , SYSZ_INS_VFNMA = 1923 , SYSZ_INS_VFNMADB = 1924 , SYSZ_INS_VFNMASB = 1925 , SYSZ_INS_VFNMS = 1926 , SYSZ_INS_VFNMSDB = 1927 , SYSZ_INS_VFNMSSB = 1928 , SYSZ_INS_VFPSO = 1929 , SYSZ_INS_VFPSODB = 1930 , SYSZ_INS_VFPSOSB = 1931 , SYSZ_INS_VFS = 1932 , SYSZ_INS_VFSDB = 1933 , SYSZ_INS_VFSQ = 1934 , SYSZ_INS_VFSQDB = 1935 , SYSZ_INS_VFSQSB = 1936 , SYSZ_INS_VFSSB = 1937 , SYSZ_INS_VFTCI = 1938 , SYSZ_INS_VFTCIDB = 1939 , SYSZ_INS_VFTCISB = 1940 , SYSZ_INS_VGBM = 1941 , SYSZ_INS_VGEF = 1942 , SYSZ_INS_VGEG = 1943 , SYSZ_INS_VGFM = 1944 , SYSZ_INS_VGFMA = 1945 , SYSZ_INS_VGFMAB = 1946 , SYSZ_INS_VGFMAF = 1947 , SYSZ_INS_VGFMAG = 1948 , SYSZ_INS_VGFMAH = 1949 , SYSZ_INS_VGFMB = 1950 , SYSZ_INS_VGFMF = 1951 , SYSZ_INS_VGFMG = 1952 , SYSZ_INS_VGFMH = 1953 , SYSZ_INS_VGM = 1954 , SYSZ_INS_VGMB = 1955 , SYSZ_INS_VGMF = 1956 , SYSZ_INS_VGMG = 1957 , SYSZ_INS_VGMH = 1958 , SYSZ_INS_VISTR = 1959 , SYSZ_INS_VISTRB = 1960 , SYSZ_INS_VISTRBS = 1961 , SYSZ_INS_VISTRF = 1962 , SYSZ_INS_VISTRFS = 1963 , SYSZ_INS_VISTRH = 1964 , SYSZ_INS_VISTRHS = 1965 , SYSZ_INS_VL = 1966 , SYSZ_INS_VLBB = 1967 , SYSZ_INS_VLC = 1968 , SYSZ_INS_VLCB = 1969 , SYSZ_INS_VLCF = 1970 , SYSZ_INS_VLCG = 1971 , SYSZ_INS_VLCH = 1972 , SYSZ_INS_VLDE = 1973 , SYSZ_INS_VLDEB = 1974 , SYSZ_INS_VLEB = 1975 , SYSZ_INS_VLED = 1976 , SYSZ_INS_VLEDB = 1977 , SYSZ_INS_VLEF = 1978 , SYSZ_INS_VLEG = 1979 , SYSZ_INS_VLEH = 1980 , SYSZ_INS_VLEIB = 1981 , SYSZ_INS_VLEIF = 1982 , SYSZ_INS_VLEIG = 1983 , SYSZ_INS_VLEIH = 1984 , SYSZ_INS_VLGV = 1985 , SYSZ_INS_VLGVB = 1986 , SYSZ_INS_VLGVF = 1987 , SYSZ_INS_VLGVG = 1988 , SYSZ_INS_VLGVH = 1989 , SYSZ_INS_VLIP = 1990 , SYSZ_INS_VLL = 1991 , SYSZ_INS_VLLEZ = 1992 , SYSZ_INS_VLLEZB = 1993 , SYSZ_INS_VLLEZF = 1994 , SYSZ_INS_VLLEZG = 1995 , SYSZ_INS_VLLEZH = 1996 , SYSZ_INS_VLLEZLF = 1997 , SYSZ_INS_VLM = 1998 , SYSZ_INS_VLP = 1999 , SYSZ_INS_VLPB = 2000 , SYSZ_INS_VLPF = 2001 , SYSZ_INS_VLPG = 2002 , SYSZ_INS_VLPH = 2003 , SYSZ_INS_VLR = 2004 , SYSZ_INS_VLREP = 2005 , SYSZ_INS_VLREPB = 2006 , SYSZ_INS_VLREPF = 2007 , SYSZ_INS_VLREPG = 2008 , SYSZ_INS_VLREPH = 2009 , SYSZ_INS_VLRL = 2010 , SYSZ_INS_VLRLR = 2011 , SYSZ_INS_VLVG = 2012 , SYSZ_INS_VLVGB = 2013 , SYSZ_INS_VLVGF = 2014 , SYSZ_INS_VLVGG = 2015 , SYSZ_INS_VLVGH = 2016 , SYSZ_INS_VLVGP = 2017 , SYSZ_INS_VMAE = 2018 , SYSZ_INS_VMAEB = 2019 , SYSZ_INS_VMAEF = 2020 , SYSZ_INS_VMAEH = 2021 , SYSZ_INS_VMAH = 2022 , SYSZ_INS_VMAHB = 2023 , SYSZ_INS_VMAHF = 2024 , SYSZ_INS_VMAHH = 2025 , SYSZ_INS_VMAL = 2026 , SYSZ_INS_VMALB = 2027 , SYSZ_INS_VMALE = 2028 , SYSZ_INS_VMALEB = 2029 , SYSZ_INS_VMALEF = 2030 , SYSZ_INS_VMALEH = 2031 , SYSZ_INS_VMALF = 2032 , SYSZ_INS_VMALH = 2033 , SYSZ_INS_VMALHB = 2034 , SYSZ_INS_VMALHF = 2035 , SYSZ_INS_VMALHH = 2036 , SYSZ_INS_VMALHW = 2037 , SYSZ_INS_VMALO = 2038 , SYSZ_INS_VMALOB = 2039 , SYSZ_INS_VMALOF = 2040 , SYSZ_INS_VMALOH = 2041 , SYSZ_INS_VMAO = 2042 , SYSZ_INS_VMAOB = 2043 , SYSZ_INS_VMAOF = 2044 , SYSZ_INS_VMAOH = 2045 , SYSZ_INS_VME = 2046 , SYSZ_INS_VMEB = 2047 , SYSZ_INS_VMEF = 2048 , SYSZ_INS_VMEH = 2049 , SYSZ_INS_VMH = 2050 , SYSZ_INS_VMHB = 2051 , SYSZ_INS_VMHF = 2052 , SYSZ_INS_VMHH = 2053 , SYSZ_INS_VML = 2054 , SYSZ_INS_VMLB = 2055 , SYSZ_INS_VMLE = 2056 , SYSZ_INS_VMLEB = 2057 , SYSZ_INS_VMLEF = 2058 , SYSZ_INS_VMLEH = 2059 , SYSZ_INS_VMLF = 2060 , SYSZ_INS_VMLH = 2061 , SYSZ_INS_VMLHB = 2062 , SYSZ_INS_VMLHF = 2063 , SYSZ_INS_VMLHH = 2064 , SYSZ_INS_VMLHW = 2065 , SYSZ_INS_VMLO = 2066 , SYSZ_INS_VMLOB = 2067 , SYSZ_INS_VMLOF = 2068 , SYSZ_INS_VMLOH = 2069 , SYSZ_INS_VMN = 2070 , SYSZ_INS_VMNB = 2071 , SYSZ_INS_VMNF = 2072 , SYSZ_INS_VMNG = 2073 , SYSZ_INS_VMNH = 2074 , SYSZ_INS_VMNL = 2075 , SYSZ_INS_VMNLB = 2076 , SYSZ_INS_VMNLF = 2077 , SYSZ_INS_VMNLG = 2078 , SYSZ_INS_VMNLH = 2079 , SYSZ_INS_VMO = 2080 , SYSZ_INS_VMOB = 2081 , SYSZ_INS_VMOF = 2082 , SYSZ_INS_VMOH = 2083 , SYSZ_INS_VMP = 2084 , SYSZ_INS_VMRH = 2085 , SYSZ_INS_VMRHB = 2086 , SYSZ_INS_VMRHF = 2087 , SYSZ_INS_VMRHG = 2088 , SYSZ_INS_VMRHH = 2089 , SYSZ_INS_VMRL = 2090 , SYSZ_INS_VMRLB = 2091 , SYSZ_INS_VMRLF = 2092 , SYSZ_INS_VMRLG = 2093 , SYSZ_INS_VMRLH = 2094 , SYSZ_INS_VMSL = 2095 , SYSZ_INS_VMSLG = 2096 , SYSZ_INS_VMSP = 2097 , SYSZ_INS_VMX = 2098 , SYSZ_INS_VMXB = 2099 , SYSZ_INS_VMXF = 2100 , SYSZ_INS_VMXG = 2101 , SYSZ_INS_VMXH = 2102 , SYSZ_INS_VMXL = 2103 , SYSZ_INS_VMXLB = 2104 , SYSZ_INS_VMXLF = 2105 , SYSZ_INS_VMXLG = 2106 , SYSZ_INS_VMXLH = 2107 , SYSZ_INS_VN = 2108 , SYSZ_INS_VNC = 2109 , SYSZ_INS_VNN = 2110 , SYSZ_INS_VNO = 2111 , SYSZ_INS_VNX = 2112 , SYSZ_INS_VO = 2113 , SYSZ_INS_VOC = 2114 , SYSZ_INS_VONE = 2115 , SYSZ_INS_VPDI = 2116 , SYSZ_INS_VPERM = 2117 , SYSZ_INS_VPK = 2118 , SYSZ_INS_VPKF = 2119 , SYSZ_INS_VPKG = 2120 , SYSZ_INS_VPKH = 2121 , SYSZ_INS_VPKLS = 2122 , SYSZ_INS_VPKLSF = 2123 , SYSZ_INS_VPKLSFS = 2124 , SYSZ_INS_VPKLSG = 2125 , SYSZ_INS_VPKLSGS = 2126 , SYSZ_INS_VPKLSH = 2127 , SYSZ_INS_VPKLSHS = 2128 , SYSZ_INS_VPKS = 2129 , SYSZ_INS_VPKSF = 2130 , SYSZ_INS_VPKSFS = 2131 , SYSZ_INS_VPKSG = 2132 , SYSZ_INS_VPKSGS = 2133 , SYSZ_INS_VPKSH = 2134 , SYSZ_INS_VPKSHS = 2135 , SYSZ_INS_VPKZ = 2136 , SYSZ_INS_VPOPCT = 2137 , SYSZ_INS_VPOPCTB = 2138 , SYSZ_INS_VPOPCTF = 2139 , SYSZ_INS_VPOPCTG = 2140 , SYSZ_INS_VPOPCTH = 2141 , SYSZ_INS_VPSOP = 2142 , SYSZ_INS_VREP = 2143 , SYSZ_INS_VREPB = 2144 , SYSZ_INS_VREPF = 2145 , SYSZ_INS_VREPG = 2146 , SYSZ_INS_VREPH = 2147 , SYSZ_INS_VREPI = 2148 , SYSZ_INS_VREPIB = 2149 , SYSZ_INS_VREPIF = 2150 , SYSZ_INS_VREPIG = 2151 , SYSZ_INS_VREPIH = 2152 , SYSZ_INS_VRP = 2153 , SYSZ_INS_VS = 2154 , SYSZ_INS_VSB = 2155 , SYSZ_INS_VSBCBI = 2156 , SYSZ_INS_VSBCBIQ = 2157 , SYSZ_INS_VSBI = 2158 , SYSZ_INS_VSBIQ = 2159 , SYSZ_INS_VSCBI = 2160 , SYSZ_INS_VSCBIB = 2161 , SYSZ_INS_VSCBIF = 2162 , SYSZ_INS_VSCBIG = 2163 , SYSZ_INS_VSCBIH = 2164 , SYSZ_INS_VSCBIQ = 2165 , SYSZ_INS_VSCEF = 2166 , SYSZ_INS_VSCEG = 2167 , SYSZ_INS_VSDP = 2168 , SYSZ_INS_VSEG = 2169 , SYSZ_INS_VSEGB = 2170 , SYSZ_INS_VSEGF = 2171 , SYSZ_INS_VSEGH = 2172 , SYSZ_INS_VSEL = 2173 , SYSZ_INS_VSF = 2174 , SYSZ_INS_VSG = 2175 , SYSZ_INS_VSH = 2176 , SYSZ_INS_VSL = 2177 , SYSZ_INS_VSLB = 2178 , SYSZ_INS_VSLDB = 2179 , SYSZ_INS_VSP = 2180 , SYSZ_INS_VSQ = 2181 , SYSZ_INS_VSRA = 2182 , SYSZ_INS_VSRAB = 2183 , SYSZ_INS_VSRL = 2184 , SYSZ_INS_VSRLB = 2185 , SYSZ_INS_VSRP = 2186 , SYSZ_INS_VST = 2187 , SYSZ_INS_VSTEB = 2188 , SYSZ_INS_VSTEF = 2189 , SYSZ_INS_VSTEG = 2190 , SYSZ_INS_VSTEH = 2191 , SYSZ_INS_VSTL = 2192 , SYSZ_INS_VSTM = 2193 , SYSZ_INS_VSTRC = 2194 , SYSZ_INS_VSTRCB = 2195 , SYSZ_INS_VSTRCBS = 2196 , SYSZ_INS_VSTRCF = 2197 , SYSZ_INS_VSTRCFS = 2198 , SYSZ_INS_VSTRCH = 2199 , SYSZ_INS_VSTRCHS = 2200 , SYSZ_INS_VSTRCZB = 2201 , SYSZ_INS_VSTRCZBS = 2202 , SYSZ_INS_VSTRCZF = 2203 , SYSZ_INS_VSTRCZFS = 2204 , SYSZ_INS_VSTRCZH = 2205 , SYSZ_INS_VSTRCZHS = 2206 , SYSZ_INS_VSTRL = 2207 , SYSZ_INS_VSTRLR = 2208 , SYSZ_INS_VSUM = 2209 , SYSZ_INS_VSUMB = 2210 , SYSZ_INS_VSUMG = 2211 , SYSZ_INS_VSUMGF = 2212 , SYSZ_INS_VSUMGH = 2213 , SYSZ_INS_VSUMH = 2214 , SYSZ_INS_VSUMQ = 2215 , SYSZ_INS_VSUMQF = 2216 , SYSZ_INS_VSUMQG = 2217 , SYSZ_INS_VTM = 2218 , SYSZ_INS_VTP = 2219 , SYSZ_INS_VUPH = 2220 , SYSZ_INS_VUPHB = 2221 , SYSZ_INS_VUPHF = 2222 , SYSZ_INS_VUPHH = 2223 , SYSZ_INS_VUPKZ = 2224 , SYSZ_INS_VUPL = 2225 , SYSZ_INS_VUPLB = 2226 , SYSZ_INS_VUPLF = 2227 , SYSZ_INS_VUPLH = 2228 , SYSZ_INS_VUPLHB = 2229 , SYSZ_INS_VUPLHF = 2230 , SYSZ_INS_VUPLHH = 2231 , SYSZ_INS_VUPLHW = 2232 , SYSZ_INS_VUPLL = 2233 , SYSZ_INS_VUPLLB = 2234 , SYSZ_INS_VUPLLF = 2235 , SYSZ_INS_VUPLLH = 2236 , SYSZ_INS_VX = 2237 , SYSZ_INS_VZERO = 2238 , SYSZ_INS_WCDGB = 2239 , SYSZ_INS_WCDLGB = 2240 , SYSZ_INS_WCGDB = 2241 , SYSZ_INS_WCLGDB = 2242 , SYSZ_INS_WFADB = 2243 , SYSZ_INS_WFASB = 2244 , SYSZ_INS_WFAXB = 2245 , SYSZ_INS_WFC = 2246 , SYSZ_INS_WFCDB = 2247 , SYSZ_INS_WFCEDB = 2248 , SYSZ_INS_WFCEDBS = 2249 , SYSZ_INS_WFCESB = 2250 , SYSZ_INS_WFCESBS = 2251 , SYSZ_INS_WFCEXB = 2252 , SYSZ_INS_WFCEXBS = 2253 , SYSZ_INS_WFCHDB = 2254 , SYSZ_INS_WFCHDBS = 2255 , SYSZ_INS_WFCHEDB = 2256 , SYSZ_INS_WFCHEDBS = 2257 , SYSZ_INS_WFCHESB = 2258 , SYSZ_INS_WFCHESBS = 2259 , SYSZ_INS_WFCHEXB = 2260 , SYSZ_INS_WFCHEXBS = 2261 , SYSZ_INS_WFCHSB = 2262 , SYSZ_INS_WFCHSBS = 2263 , SYSZ_INS_WFCHXB = 2264 , SYSZ_INS_WFCHXBS = 2265 , SYSZ_INS_WFCSB = 2266 , SYSZ_INS_WFCXB = 2267 , SYSZ_INS_WFDDB = 2268 , SYSZ_INS_WFDSB = 2269 , SYSZ_INS_WFDXB = 2270 , SYSZ_INS_WFIDB = 2271 , SYSZ_INS_WFISB = 2272 , SYSZ_INS_WFIXB = 2273 , SYSZ_INS_WFK = 2274 , SYSZ_INS_WFKDB = 2275 , SYSZ_INS_WFKEDB = 2276 , SYSZ_INS_WFKEDBS = 2277 , SYSZ_INS_WFKESB = 2278 , SYSZ_INS_WFKESBS = 2279 , SYSZ_INS_WFKEXB = 2280 , SYSZ_INS_WFKEXBS = 2281 , SYSZ_INS_WFKHDB = 2282 , SYSZ_INS_WFKHDBS = 2283 , SYSZ_INS_WFKHEDB = 2284 , SYSZ_INS_WFKHEDBS = 2285 , SYSZ_INS_WFKHESB = 2286 , SYSZ_INS_WFKHESBS = 2287 , SYSZ_INS_WFKHEXB = 2288 , SYSZ_INS_WFKHEXBS = 2289 , SYSZ_INS_WFKHSB = 2290 , SYSZ_INS_WFKHSBS = 2291 , SYSZ_INS_WFKHXB = 2292 , SYSZ_INS_WFKHXBS = 2293 , SYSZ_INS_WFKSB = 2294 , SYSZ_INS_WFKXB = 2295 , SYSZ_INS_WFLCDB = 2296 , SYSZ_INS_WFLCSB = 2297 , SYSZ_INS_WFLCXB = 2298 , SYSZ_INS_WFLLD = 2299 , SYSZ_INS_WFLLS = 2300 , SYSZ_INS_WFLNDB = 2301 , SYSZ_INS_WFLNSB = 2302 , SYSZ_INS_WFLNXB = 2303 , SYSZ_INS_WFLPDB = 2304 , SYSZ_INS_WFLPSB = 2305 , SYSZ_INS_WFLPXB = 2306 , SYSZ_INS_WFLRD = 2307 , SYSZ_INS_WFLRX = 2308 , SYSZ_INS_WFMADB = 2309 , SYSZ_INS_WFMASB = 2310 , SYSZ_INS_WFMAXB = 2311 , SYSZ_INS_WFMAXDB = 2312 , SYSZ_INS_WFMAXSB = 2313 , SYSZ_INS_WFMAXXB = 2314 , SYSZ_INS_WFMDB = 2315 , SYSZ_INS_WFMINDB = 2316 , SYSZ_INS_WFMINSB = 2317 , SYSZ_INS_WFMINXB = 2318 , SYSZ_INS_WFMSB = 2319 , SYSZ_INS_WFMSDB = 2320 , SYSZ_INS_WFMSSB = 2321 , SYSZ_INS_WFMSXB = 2322 , SYSZ_INS_WFMXB = 2323 , SYSZ_INS_WFNMADB = 2324 , SYSZ_INS_WFNMASB = 2325 , SYSZ_INS_WFNMAXB = 2326 , SYSZ_INS_WFNMSDB = 2327 , SYSZ_INS_WFNMSSB = 2328 , SYSZ_INS_WFNMSXB = 2329 , SYSZ_INS_WFPSODB = 2330 , SYSZ_INS_WFPSOSB = 2331 , SYSZ_INS_WFPSOXB = 2332 , SYSZ_INS_WFSDB = 2333 , SYSZ_INS_WFSQDB = 2334 , SYSZ_INS_WFSQSB = 2335 , SYSZ_INS_WFSQXB = 2336 , SYSZ_INS_WFSSB = 2337 , SYSZ_INS_WFSXB = 2338 , SYSZ_INS_WFTCIDB = 2339 , SYSZ_INS_WFTCISB = 2340 , SYSZ_INS_WFTCIXB = 2341 , SYSZ_INS_WLDEB = 2342 , SYSZ_INS_WLEDB = 2343 , SYSZ_INS_XSCH = 2344 , SYSZ_INS_ZAP = 2345 , SYSZ_INS_ENDING = 2346 , } # [repr (u32)] # [doc = " Group of SystemZ instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn_group { # [doc = "< = CS_GRP_INVALID"] SYSZ_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SYSZ_GRP_JUMP = 1 , SYSZ_GRP_DISTINCTOPS = 128 , SYSZ_GRP_FPEXTENSION = 129 , SYSZ_GRP_HIGHWORD = 130 , SYSZ_GRP_INTERLOCKEDACCESS1 = 131 , SYSZ_GRP_LOADSTOREONCOND = 132 , SYSZ_GRP_DFPPACKEDCONVERSION = 133 , SYSZ_GRP_DFPZONEDCONVERSION = 134 , SYSZ_GRP_ENHANCEDDAT2 = 135 , SYSZ_GRP_EXECUTIONHINT = 136 , SYSZ_GRP_GUARDEDSTORAGE = 137 , SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 , SYSZ_GRP_LOADANDTRAP = 139 , SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 , SYSZ_GRP_LOADSTOREONCOND2 = 141 , SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 , SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 , SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 , SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 , SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 , SYSZ_GRP_NOVECTOR = 149 , SYSZ_GRP_POPULATIONCOUNT = 150 , SYSZ_GRP_PROCESSORASSIST = 151 , SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 , SYSZ_GRP_TRANSACTIONALEXECUTION = 153 , SYSZ_GRP_VECTOR = 154 , SYSZ_GRP_VECTORENHANCEMENTS1 = 155 , SYSZ_GRP_VECTORPACKEDDECIMAL = 156 , SYSZ_GRP_ENDING = 157 , } # [repr (u32)] # [doc = " X86 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_reg { X86_REG_INVALID = 0 , X86_REG_AH = 1 , X86_REG_AL = 2 , X86_REG_AX = 3 , X86_REG_BH = 4 , X86_REG_BL = 5 , X86_REG_BP = 6 , X86_REG_BPL = 7 , X86_REG_BX = 8 , X86_REG_CH = 9 , X86_REG_CL = 10 , X86_REG_CS = 11 , X86_REG_CX = 12 , X86_REG_DH = 13 , X86_REG_DI = 14 , X86_REG_DIL = 15 , X86_REG_DL = 16 , X86_REG_DS = 17 , X86_REG_DX = 18 , X86_REG_EAX = 19 , X86_REG_EBP = 20 , X86_REG_EBX = 21 , X86_REG_ECX = 22 , X86_REG_EDI = 23 , X86_REG_EDX = 24 , X86_REG_EFLAGS = 25 , X86_REG_EIP = 26 , X86_REG_EIZ = 27 , X86_REG_ES = 28 , X86_REG_ESI = 29 , X86_REG_ESP = 30 , X86_REG_FPSW = 31 , X86_REG_FS = 32 , X86_REG_GS = 33 , X86_REG_IP = 34 , X86_REG_RAX = 35 , X86_REG_RBP = 36 , X86_REG_RBX = 37 , X86_REG_RCX = 38 , X86_REG_RDI = 39 , X86_REG_RDX = 40 , X86_REG_RIP = 41 , X86_REG_RIZ = 42 , X86_REG_RSI = 43 , X86_REG_RSP = 44 , X86_REG_SI = 45 , X86_REG_SIL = 46 , X86_REG_SP = 47 , X86_REG_SPL = 48 , X86_REG_SS = 49 , X86_REG_CR0 = 50 , X86_REG_CR1 = 51 , X86_REG_CR2 = 52 , X86_REG_CR3 = 53 , X86_REG_CR4 = 54 , X86_REG_CR5 = 55 , X86_REG_CR6 = 56 , X86_REG_CR7 = 57 , X86_REG_CR8 = 58 , X86_REG_CR9 = 59 , X86_REG_CR10 = 60 , X86_REG_CR11 = 61 , X86_REG_CR12 = 62 , X86_REG_CR13 = 63 , X86_REG_CR14 = 64 , X86_REG_CR15 = 65 , X86_REG_DR0 = 66 , X86_REG_DR1 = 67 , X86_REG_DR2 = 68 , X86_REG_DR3 = 69 , X86_REG_DR4 = 70 , X86_REG_DR5 = 71 , X86_REG_DR6 = 72 , X86_REG_DR7 = 73 , X86_REG_DR8 = 74 , X86_REG_DR9 = 75 , X86_REG_DR10 = 76 , X86_REG_DR11 = 77 , X86_REG_DR12 = 78 , X86_REG_DR13 = 79 , X86_REG_DR14 = 80 , X86_REG_DR15 = 81 , X86_REG_FP0 = 82 , X86_REG_FP1 = 83 , X86_REG_FP2 = 84 , X86_REG_FP3 = 85 , X86_REG_FP4 = 86 , X86_REG_FP5 = 87 , X86_REG_FP6 = 88 , X86_REG_FP7 = 89 , X86_REG_K0 = 90 , X86_REG_K1 = 91 , X86_REG_K2 = 92 , X86_REG_K3 = 93 , X86_REG_K4 = 94 , X86_REG_K5 = 95 , X86_REG_K6 = 96 , X86_REG_K7 = 97 , X86_REG_MM0 = 98 , X86_REG_MM1 = 99 , X86_REG_MM2 = 100 , X86_REG_MM3 = 101 , X86_REG_MM4 = 102 , X86_REG_MM5 = 103 , X86_REG_MM6 = 104 , X86_REG_MM7 = 105 , X86_REG_R8 = 106 , X86_REG_R9 = 107 , X86_REG_R10 = 108 , X86_REG_R11 = 109 , X86_REG_R12 = 110 , X86_REG_R13 = 111 , X86_REG_R14 = 112 , X86_REG_R15 = 113 , X86_REG_ST0 = 114 , X86_REG_ST1 = 115 , X86_REG_ST2 = 116 , X86_REG_ST3 = 117 , X86_REG_ST4 = 118 , X86_REG_ST5 = 119 , X86_REG_ST6 = 120 , X86_REG_ST7 = 121 , X86_REG_XMM0 = 122 , X86_REG_XMM1 = 123 , X86_REG_XMM2 = 124 , X86_REG_XMM3 = 125 , X86_REG_XMM4 = 126 , X86_REG_XMM5 = 127 , X86_REG_XMM6 = 128 , X86_REG_XMM7 = 129 , X86_REG_XMM8 = 130 , X86_REG_XMM9 = 131 , X86_REG_XMM10 = 132 , X86_REG_XMM11 = 133 , X86_REG_XMM12 = 134 , X86_REG_XMM13 = 135 , X86_REG_XMM14 = 136 , X86_REG_XMM15 = 137 , X86_REG_XMM16 = 138 , X86_REG_XMM17 = 139 , X86_REG_XMM18 = 140 , X86_REG_XMM19 = 141 , X86_REG_XMM20 = 142 , X86_REG_XMM21 = 143 , X86_REG_XMM22 = 144 , X86_REG_XMM23 = 145 , X86_REG_XMM24 = 146 , X86_REG_XMM25 = 147 , X86_REG_XMM26 = 148 , X86_REG_XMM27 = 149 , X86_REG_XMM28 = 150 , X86_REG_XMM29 = 151 , X86_REG_XMM30 = 152 , X86_REG_XMM31 = 153 , X86_REG_YMM0 = 154 , X86_REG_YMM1 = 155 , X86_REG_YMM2 = 156 , X86_REG_YMM3 = 157 , X86_REG_YMM4 = 158 , X86_REG_YMM5 = 159 , X86_REG_YMM6 = 160 , X86_REG_YMM7 = 161 , X86_REG_YMM8 = 162 , X86_REG_YMM9 = 163 , X86_REG_YMM10 = 164 , X86_REG_YMM11 = 165 , X86_REG_YMM12 = 166 , X86_REG_YMM13 = 167 , X86_REG_YMM14 = 168 , X86_REG_YMM15 = 169 , X86_REG_YMM16 = 170 , X86_REG_YMM17 = 171 , X86_REG_YMM18 = 172 , X86_REG_YMM19 = 173 , X86_REG_YMM20 = 174 , X86_REG_YMM21 = 175 , X86_REG_YMM22 = 176 , X86_REG_YMM23 = 177 , X86_REG_YMM24 = 178 , X86_REG_YMM25 = 179 , X86_REG_YMM26 = 180 , X86_REG_YMM27 = 181 , X86_REG_YMM28 = 182 , X86_REG_YMM29 = 183 , X86_REG_YMM30 = 184 , X86_REG_YMM31 = 185 , X86_REG_ZMM0 = 186 , X86_REG_ZMM1 = 187 , X86_REG_ZMM2 = 188 , X86_REG_ZMM3 = 189 , X86_REG_ZMM4 = 190 , X86_REG_ZMM5 = 191 , X86_REG_ZMM6 = 192 , X86_REG_ZMM7 = 193 , X86_REG_ZMM8 = 194 , X86_REG_ZMM9 = 195 , X86_REG_ZMM10 = 196 , X86_REG_ZMM11 = 197 , X86_REG_ZMM12 = 198 , X86_REG_ZMM13 = 199 , X86_REG_ZMM14 = 200 , X86_REG_ZMM15 = 201 , X86_REG_ZMM16 = 202 , X86_REG_ZMM17 = 203 , X86_REG_ZMM18 = 204 , X86_REG_ZMM19 = 205 , X86_REG_ZMM20 = 206 , X86_REG_ZMM21 = 207 , X86_REG_ZMM22 = 208 , X86_REG_ZMM23 = 209 , X86_REG_ZMM24 = 210 , X86_REG_ZMM25 = 211 , X86_REG_ZMM26 = 212 , X86_REG_ZMM27 = 213 , X86_REG_ZMM28 = 214 , X86_REG_ZMM29 = 215 , X86_REG_ZMM30 = 216 , X86_REG_ZMM31 = 217 , X86_REG_R8B = 218 , X86_REG_R9B = 219 , X86_REG_R10B = 220 , X86_REG_R11B = 221 , X86_REG_R12B = 222 , X86_REG_R13B = 223 , X86_REG_R14B = 224 , X86_REG_R15B = 225 , X86_REG_R8D = 226 , X86_REG_R9D = 227 , X86_REG_R10D = 228 , X86_REG_R11D = 229 , X86_REG_R12D = 230 , X86_REG_R13D = 231 , X86_REG_R14D = 232 , X86_REG_R15D = 233 , X86_REG_R8W = 234 , X86_REG_R9W = 235 , X86_REG_R10W = 236 , X86_REG_R11W = 237 , X86_REG_R12W = 238 , X86_REG_R13W = 239 , X86_REG_R14W = 240 , X86_REG_R15W = 241 , X86_REG_BND0 = 242 , X86_REG_BND1 = 243 , X86_REG_BND2 = 244 , X86_REG_BND3 = 245 , X86_REG_ENDING = 246 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] X86_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] X86_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] X86_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] X86_OP_MEM = 3 , } # [repr (u32)] # [doc = " XOP Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_xop_cc { # [doc = "< Uninitialized."] X86_XOP_CC_INVALID = 0 , X86_XOP_CC_LT = 1 , X86_XOP_CC_LE = 2 , X86_XOP_CC_GT = 3 , X86_XOP_CC_GE = 4 , X86_XOP_CC_EQ = 5 , X86_XOP_CC_NEQ = 6 , X86_XOP_CC_FALSE = 7 , X86_XOP_CC_TRUE = 8 , } # [repr (u32)] # [doc = " AVX broadcast type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_bcast { # [doc = "< Uninitialized."] X86_AVX_BCAST_INVALID = 0 , # [doc = "< AVX512 broadcast type {1to2}"] X86_AVX_BCAST_2 = 1 , # [doc = "< AVX512 broadcast type {1to4}"] X86_AVX_BCAST_4 = 2 , # [doc = "< AVX512 broadcast type {1to8}"] X86_AVX_BCAST_8 = 3 , # [doc = "< AVX512 broadcast type {1to16}"] X86_AVX_BCAST_16 = 4 , } # [repr (u32)] # [doc = " SSE Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_sse_cc { # [doc = "< Uninitialized."] X86_SSE_CC_INVALID = 0 , X86_SSE_CC_EQ = 1 , X86_SSE_CC_LT = 2 , X86_SSE_CC_LE = 3 , X86_SSE_CC_UNORD = 4 , X86_SSE_CC_NEQ = 5 , X86_SSE_CC_NLT = 6 , X86_SSE_CC_NLE = 7 , X86_SSE_CC_ORD = 8 , } # [repr (u32)] # [doc = " AVX Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_cc { # [doc = "< Uninitialized."] X86_AVX_CC_INVALID = 0 , X86_AVX_CC_EQ = 1 , X86_AVX_CC_LT = 2 , X86_AVX_CC_LE = 3 , X86_AVX_CC_UNORD = 4 , X86_AVX_CC_NEQ = 5 , X86_AVX_CC_NLT = 6 , X86_AVX_CC_NLE = 7 , X86_AVX_CC_ORD = 8 , X86_AVX_CC_EQ_UQ = 9 , X86_AVX_CC_NGE = 10 , X86_AVX_CC_NGT = 11 , X86_AVX_CC_FALSE = 12 , X86_AVX_CC_NEQ_OQ = 13 , X86_AVX_CC_GE = 14 , X86_AVX_CC_GT = 15 , X86_AVX_CC_TRUE = 16 , X86_AVX_CC_EQ_OS = 17 , X86_AVX_CC_LT_OQ = 18 , X86_AVX_CC_LE_OQ = 19 , X86_AVX_CC_UNORD_S = 20 , X86_AVX_CC_NEQ_US = 21 , X86_AVX_CC_NLT_UQ = 22 , X86_AVX_CC_NLE_UQ = 23 , X86_AVX_CC_ORD_S = 24 , X86_AVX_CC_EQ_US = 25 , X86_AVX_CC_NGE_UQ = 26 , X86_AVX_CC_NGT_UQ = 27 , X86_AVX_CC_FALSE_OS = 28 , X86_AVX_CC_NEQ_OS = 29 , X86_AVX_CC_GE_OQ = 30 , X86_AVX_CC_GT_OQ = 31 , X86_AVX_CC_TRUE_US = 32 , } # [repr (u32)] # [doc = " AVX static rounding mode type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_rm { # [doc = "< Uninitialized."] X86_AVX_RM_INVALID = 0 , # [doc = "< Round to nearest"] X86_AVX_RM_RN = 1 , # [doc = "< Round down"] X86_AVX_RM_RD = 2 , # [doc = "< Round up"] X86_AVX_RM_RU = 3 , # [doc = "< Round toward zero"] X86_AVX_RM_RZ = 4 , } impl x86_prefix { pub const X86_PREFIX_REPE : x86_prefix = x86_prefix :: X86_PREFIX_REP ; } # [repr (u32)] # [doc = " Instruction prefixes - to be used in cs_x86.prefix[]"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_prefix { # [doc = "< lock (cs_x86.prefix[0]"] X86_PREFIX_LOCK = 240 , # [doc = "< rep (cs_x86.prefix[0]"] X86_PREFIX_REP = 243 , # [doc = "< repne/repnz (cs_x86.prefix[0]"] X86_PREFIX_REPNE = 242 , # [doc = "< segment override CS (cs_x86.prefix[1]"] X86_PREFIX_CS = 46 , # [doc = "< segment override SS (cs_x86.prefix[1]"] X86_PREFIX_SS = 54 , # [doc = "< segment override DS (cs_x86.prefix[1]"] X86_PREFIX_DS = 62 , # [doc = "< segment override ES (cs_x86.prefix[1]"] X86_PREFIX_ES = 38 , # [doc = "< segment override FS (cs_x86.prefix[1]"] X86_PREFIX_FS = 100 , # [doc = "< segment override GS (cs_x86.prefix[1]"] X86_PREFIX_GS = 101 , # [doc = "< operand-size override (cs_x86.prefix[2]"] X86_PREFIX_OPSIZE = 102 , # [doc = "< address-size override (cs_x86.prefix[3]"] X86_PREFIX_ADDRSIZE = 103 , } # [doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct x86_op_mem { # [doc = "< segment register (or X86_REG_INVALID if irrelevant)"] pub segment : x86_reg , # [doc = "< base register (or X86_REG_INVALID if irrelevant)"] pub base : x86_reg , # [doc = "< index register (or X86_REG_INVALID if irrelevant)"] pub index : x86_reg , # [doc = "< scale for index register"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of x86_op_mem"] [:: std :: mem :: size_of :: < x86_op_mem > () - 24usize] ; ["Alignment of x86_op_mem"] [:: std :: mem :: align_of :: < x86_op_mem > () - 8usize] ; ["Offset of field: x86_op_mem::segment"] [:: std :: mem :: offset_of ! (x86_op_mem , segment) - 0usize] ; ["Offset of field: x86_op_mem::base"] [:: std :: mem :: offset_of ! (x86_op_mem , base) - 4usize] ; ["Offset of field: x86_op_mem::index"] [:: std :: mem :: offset_of ! (x86_op_mem , index) - 8usize] ; ["Offset of field: x86_op_mem::scale"] [:: std :: mem :: offset_of ! (x86_op_mem , scale) - 12usize] ; ["Offset of field: x86_op_mem::disp"] [:: std :: mem :: offset_of ! (x86_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86_op { # [doc = "< operand type"] pub type_ : x86_op_type , pub __bindgen_anon_1 : cs_x86_op__bindgen_ty_1 , # [doc = " size of this operand (in bytes)."] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " AVX broadcast type, or 0 if irrelevant"] pub avx_bcast : x86_avx_bcast , # [doc = " AVX zero opmask {z}"] pub avx_zero_opmask : bool , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : x86_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : x86_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op"] [:: std :: mem :: size_of :: < cs_x86_op > () - 48usize] ; ["Alignment of cs_x86_op"] [:: std :: mem :: align_of :: < cs_x86_op > () - 8usize] ; ["Offset of field: cs_x86_op::type_"] [:: std :: mem :: offset_of ! (cs_x86_op , type_) - 0usize] ; ["Offset of field: cs_x86_op::size"] [:: std :: mem :: offset_of ! (cs_x86_op , size) - 32usize] ; ["Offset of field: cs_x86_op::access"] [:: std :: mem :: offset_of ! (cs_x86_op , access) - 33usize] ; ["Offset of field: cs_x86_op::avx_bcast"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_bcast) - 36usize] ; ["Offset of field: cs_x86_op::avx_zero_opmask"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_zero_opmask) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask) } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_x86_encoding { # [doc = " ModR/M offset, or 0 when irrelevant"] pub modrm_offset : u8 , # [doc = " Displacement offset, or 0 when irrelevant."] pub disp_offset : u8 , pub disp_size : u8 , # [doc = " Immediate offset, or 0 when irrelevant."] pub imm_offset : u8 , pub imm_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_encoding"] [:: std :: mem :: size_of :: < cs_x86_encoding > () - 5usize] ; ["Alignment of cs_x86_encoding"] [:: std :: mem :: align_of :: < cs_x86_encoding > () - 1usize] ; ["Offset of field: cs_x86_encoding::modrm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , modrm_offset) - 0usize] ; ["Offset of field: cs_x86_encoding::disp_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_offset) - 1usize] ; ["Offset of field: cs_x86_encoding::disp_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_size) - 2usize] ; ["Offset of field: cs_x86_encoding::imm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_offset) - 3usize] ; ["Offset of field: cs_x86_encoding::imm_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_size) - 4usize] ; } ; # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86 { # [doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"] pub prefix : [u8 ; 4usize] , # [doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."] pub opcode : [u8 ; 4usize] , # [doc = " REX prefix: only a non-zero value is relevant for x86_64"] pub rex : u8 , # [doc = " Address size, which can be overridden with above prefix[5]."] pub addr_size : u8 , # [doc = " ModR/M byte"] pub modrm : u8 , # [doc = " SIB value, or 0 when irrelevant."] pub sib : u8 , # [doc = " Displacement value, valid if encoding.disp_offset != 0"] pub disp : i64 , # [doc = " SIB index register, or X86_REG_INVALID when irrelevant."] pub sib_index : x86_reg , # [doc = " SIB scale, only applicable if sib_index is valid."] pub sib_scale : i8 , # [doc = " SIB base register, or X86_REG_INVALID when irrelevant."] pub sib_base : x86_reg , # [doc = " XOP Code Condition"] pub xop_cc : x86_xop_cc , # [doc = " SSE Code Condition"] pub sse_cc : x86_sse_cc , # [doc = " AVX Code Condition"] pub avx_cc : x86_avx_cc , # [doc = " AVX Suppress all Exception"] pub avx_sae : bool , # [doc = " AVX static rounding mode"] pub avx_rm : x86_avx_rm , pub __bindgen_anon_1 : cs_x86__bindgen_ty_1 , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_x86_op ; 8usize] , # [doc = "< encoding information"] pub encoding : cs_x86_encoding , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86__bindgen_ty_1 { # [doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"] pub eflags : u64 , # [doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"] pub fpu_flags : u64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_x86__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86__bindgen_ty_1::eflags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , eflags) - 0usize] ; ["Offset of field: cs_x86__bindgen_ty_1::fpu_flags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , fpu_flags) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86"] [:: std :: mem :: size_of :: < cs_x86 > () - 464usize] ; ["Alignment of cs_x86"] [:: std :: mem :: align_of :: < cs_x86 > () - 8usize] ; ["Offset of field: cs_x86::prefix"] [:: std :: mem :: offset_of ! (cs_x86 , prefix) - 0usize] ; ["Offset of field: cs_x86::opcode"] [:: std :: mem :: offset_of ! (cs_x86 , opcode) - 4usize] ; ["Offset of field: cs_x86::rex"] [:: std :: mem :: offset_of ! (cs_x86 , rex) - 8usize] ; ["Offset of field: cs_x86::addr_size"] [:: std :: mem :: offset_of ! (cs_x86 , addr_size) - 9usize] ; ["Offset of field: cs_x86::modrm"] [:: std :: mem :: offset_of ! (cs_x86 , modrm) - 10usize] ; ["Offset of field: cs_x86::sib"] [:: std :: mem :: offset_of ! (cs_x86 , sib) - 11usize] ; ["Offset of field: cs_x86::disp"] [:: std :: mem :: offset_of ! (cs_x86 , disp) - 16usize] ; ["Offset of field: cs_x86::sib_index"] [:: std :: mem :: offset_of ! (cs_x86 , sib_index) - 24usize] ; ["Offset of field: cs_x86::sib_scale"] [:: std :: mem :: offset_of ! (cs_x86 , sib_scale) - 28usize] ; ["Offset of field: cs_x86::sib_base"] [:: std :: mem :: offset_of ! (cs_x86 , sib_base) - 32usize] ; ["Offset of field: cs_x86::xop_cc"] [:: std :: mem :: offset_of ! (cs_x86 , xop_cc) - 36usize] ; ["Offset of field: cs_x86::sse_cc"] [:: std :: mem :: offset_of ! (cs_x86 , sse_cc) - 40usize] ; ["Offset of field: cs_x86::avx_cc"] [:: std :: mem :: offset_of ! (cs_x86 , avx_cc) - 44usize] ; ["Offset of field: cs_x86::avx_sae"] [:: std :: mem :: offset_of ! (cs_x86 , avx_sae) - 48usize] ; ["Offset of field: cs_x86::avx_rm"] [:: std :: mem :: offset_of ! (cs_x86 , avx_rm) - 52usize] ; ["Offset of field: cs_x86::op_count"] [:: std :: mem :: offset_of ! (cs_x86 , op_count) - 64usize] ; ["Offset of field: cs_x86::operands"] [:: std :: mem :: offset_of ! (cs_x86 , operands) - 72usize] ; ["Offset of field: cs_x86::encoding"] [:: std :: mem :: offset_of ! (cs_x86 , encoding) - 456usize] ; } ; impl :: std :: fmt :: Debug for cs_x86 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding) } } # [repr (u32)] # [doc = " X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn { X86_INS_INVALID = 0 , X86_INS_AAA = 1 , X86_INS_AAD = 2 , X86_INS_AAM = 3 , X86_INS_AAS = 4 , X86_INS_FABS = 5 , X86_INS_ADC = 6 , X86_INS_ADCX = 7 , X86_INS_ADD = 8 , X86_INS_ADDPD = 9 , X86_INS_ADDPS = 10 , X86_INS_ADDSD = 11 , X86_INS_ADDSS = 12 , X86_INS_ADDSUBPD = 13 , X86_INS_ADDSUBPS = 14 , X86_INS_FADD = 15 , X86_INS_FIADD = 16 , X86_INS_ADOX = 17 , X86_INS_AESDECLAST = 18 , X86_INS_AESDEC = 19 , X86_INS_AESENCLAST = 20 , X86_INS_AESENC = 21 , X86_INS_AESIMC = 22 , X86_INS_AESKEYGENASSIST = 23 , X86_INS_AND = 24 , X86_INS_ANDN = 25 , X86_INS_ANDNPD = 26 , X86_INS_ANDNPS = 27 , X86_INS_ANDPD = 28 , X86_INS_ANDPS = 29 , X86_INS_ARPL = 30 , X86_INS_BEXTR = 31 , X86_INS_BLCFILL = 32 , X86_INS_BLCI = 33 , X86_INS_BLCIC = 34 , X86_INS_BLCMSK = 35 , X86_INS_BLCS = 36 , X86_INS_BLENDPD = 37 , X86_INS_BLENDPS = 38 , X86_INS_BLENDVPD = 39 , X86_INS_BLENDVPS = 40 , X86_INS_BLSFILL = 41 , X86_INS_BLSI = 42 , X86_INS_BLSIC = 43 , X86_INS_BLSMSK = 44 , X86_INS_BLSR = 45 , X86_INS_BNDCL = 46 , X86_INS_BNDCN = 47 , X86_INS_BNDCU = 48 , X86_INS_BNDLDX = 49 , X86_INS_BNDMK = 50 , X86_INS_BNDMOV = 51 , X86_INS_BNDSTX = 52 , X86_INS_BOUND = 53 , X86_INS_BSF = 54 , X86_INS_BSR = 55 , X86_INS_BSWAP = 56 , X86_INS_BT = 57 , X86_INS_BTC = 58 , X86_INS_BTR = 59 , X86_INS_BTS = 60 , X86_INS_BZHI = 61 , X86_INS_CALL = 62 , X86_INS_CBW = 63 , X86_INS_CDQ = 64 , X86_INS_CDQE = 65 , X86_INS_FCHS = 66 , X86_INS_CLAC = 67 , X86_INS_CLC = 68 , X86_INS_CLD = 69 , X86_INS_CLDEMOTE = 70 , X86_INS_CLFLUSH = 71 , X86_INS_CLFLUSHOPT = 72 , X86_INS_CLGI = 73 , X86_INS_CLI = 74 , X86_INS_CLRSSBSY = 75 , X86_INS_CLTS = 76 , X86_INS_CLWB = 77 , X86_INS_CLZERO = 78 , X86_INS_CMC = 79 , X86_INS_CMOVA = 80 , X86_INS_CMOVAE = 81 , X86_INS_CMOVB = 82 , X86_INS_CMOVBE = 83 , X86_INS_FCMOVBE = 84 , X86_INS_FCMOVB = 85 , X86_INS_CMOVE = 86 , X86_INS_FCMOVE = 87 , X86_INS_CMOVG = 88 , X86_INS_CMOVGE = 89 , X86_INS_CMOVL = 90 , X86_INS_CMOVLE = 91 , X86_INS_FCMOVNBE = 92 , X86_INS_FCMOVNB = 93 , X86_INS_CMOVNE = 94 , X86_INS_FCMOVNE = 95 , X86_INS_CMOVNO = 96 , X86_INS_CMOVNP = 97 , X86_INS_FCMOVNU = 98 , X86_INS_FCMOVNP = 99 , X86_INS_CMOVNS = 100 , X86_INS_CMOVO = 101 , X86_INS_CMOVP = 102 , X86_INS_FCMOVU = 103 , X86_INS_CMOVS = 104 , X86_INS_CMP = 105 , X86_INS_CMPPD = 106 , X86_INS_CMPPS = 107 , X86_INS_CMPSB = 108 , X86_INS_CMPSD = 109 , X86_INS_CMPSQ = 110 , X86_INS_CMPSS = 111 , X86_INS_CMPSW = 112 , X86_INS_CMPXCHG16B = 113 , X86_INS_CMPXCHG = 114 , X86_INS_CMPXCHG8B = 115 , X86_INS_COMISD = 116 , X86_INS_COMISS = 117 , X86_INS_FCOMP = 118 , X86_INS_FCOMPI = 119 , X86_INS_FCOMI = 120 , X86_INS_FCOM = 121 , X86_INS_FCOS = 122 , X86_INS_CPUID = 123 , X86_INS_CQO = 124 , X86_INS_CRC32 = 125 , X86_INS_CVTDQ2PD = 126 , X86_INS_CVTDQ2PS = 127 , X86_INS_CVTPD2DQ = 128 , X86_INS_CVTPD2PS = 129 , X86_INS_CVTPS2DQ = 130 , X86_INS_CVTPS2PD = 131 , X86_INS_CVTSD2SI = 132 , X86_INS_CVTSD2SS = 133 , X86_INS_CVTSI2SD = 134 , X86_INS_CVTSI2SS = 135 , X86_INS_CVTSS2SD = 136 , X86_INS_CVTSS2SI = 137 , X86_INS_CVTTPD2DQ = 138 , X86_INS_CVTTPS2DQ = 139 , X86_INS_CVTTSD2SI = 140 , X86_INS_CVTTSS2SI = 141 , X86_INS_CWD = 142 , X86_INS_CWDE = 143 , X86_INS_DAA = 144 , X86_INS_DAS = 145 , X86_INS_DATA16 = 146 , X86_INS_DEC = 147 , X86_INS_DIV = 148 , X86_INS_DIVPD = 149 , X86_INS_DIVPS = 150 , X86_INS_FDIVR = 151 , X86_INS_FIDIVR = 152 , X86_INS_FDIVRP = 153 , X86_INS_DIVSD = 154 , X86_INS_DIVSS = 155 , X86_INS_FDIV = 156 , X86_INS_FIDIV = 157 , X86_INS_FDIVP = 158 , X86_INS_DPPD = 159 , X86_INS_DPPS = 160 , X86_INS_ENCLS = 161 , X86_INS_ENCLU = 162 , X86_INS_ENCLV = 163 , X86_INS_ENDBR32 = 164 , X86_INS_ENDBR64 = 165 , X86_INS_ENTER = 166 , X86_INS_EXTRACTPS = 167 , X86_INS_EXTRQ = 168 , X86_INS_F2XM1 = 169 , X86_INS_LCALL = 170 , X86_INS_LJMP = 171 , X86_INS_JMP = 172 , X86_INS_FBLD = 173 , X86_INS_FBSTP = 174 , X86_INS_FCOMPP = 175 , X86_INS_FDECSTP = 176 , X86_INS_FDISI8087_NOP = 177 , X86_INS_FEMMS = 178 , X86_INS_FENI8087_NOP = 179 , X86_INS_FFREE = 180 , X86_INS_FFREEP = 181 , X86_INS_FICOM = 182 , X86_INS_FICOMP = 183 , X86_INS_FINCSTP = 184 , X86_INS_FLDCW = 185 , X86_INS_FLDENV = 186 , X86_INS_FLDL2E = 187 , X86_INS_FLDL2T = 188 , X86_INS_FLDLG2 = 189 , X86_INS_FLDLN2 = 190 , X86_INS_FLDPI = 191 , X86_INS_FNCLEX = 192 , X86_INS_FNINIT = 193 , X86_INS_FNOP = 194 , X86_INS_FNSTCW = 195 , X86_INS_FNSTSW = 196 , X86_INS_FPATAN = 197 , X86_INS_FSTPNCE = 198 , X86_INS_FPREM = 199 , X86_INS_FPREM1 = 200 , X86_INS_FPTAN = 201 , X86_INS_FRNDINT = 202 , X86_INS_FRSTOR = 203 , X86_INS_FNSAVE = 204 , X86_INS_FSCALE = 205 , X86_INS_FSETPM = 206 , X86_INS_FSINCOS = 207 , X86_INS_FNSTENV = 208 , X86_INS_FXAM = 209 , X86_INS_FXRSTOR = 210 , X86_INS_FXRSTOR64 = 211 , X86_INS_FXSAVE = 212 , X86_INS_FXSAVE64 = 213 , X86_INS_FXTRACT = 214 , X86_INS_FYL2X = 215 , X86_INS_FYL2XP1 = 216 , X86_INS_GETSEC = 217 , X86_INS_GF2P8AFFINEINVQB = 218 , X86_INS_GF2P8AFFINEQB = 219 , X86_INS_GF2P8MULB = 220 , X86_INS_HADDPD = 221 , X86_INS_HADDPS = 222 , X86_INS_HLT = 223 , X86_INS_HSUBPD = 224 , X86_INS_HSUBPS = 225 , X86_INS_IDIV = 226 , X86_INS_FILD = 227 , X86_INS_IMUL = 228 , X86_INS_IN = 229 , X86_INS_INC = 230 , X86_INS_INCSSPD = 231 , X86_INS_INCSSPQ = 232 , X86_INS_INSB = 233 , X86_INS_INSERTPS = 234 , X86_INS_INSERTQ = 235 , X86_INS_INSD = 236 , X86_INS_INSW = 237 , X86_INS_INT = 238 , X86_INS_INT1 = 239 , X86_INS_INT3 = 240 , X86_INS_INTO = 241 , X86_INS_INVD = 242 , X86_INS_INVEPT = 243 , X86_INS_INVLPG = 244 , X86_INS_INVLPGA = 245 , X86_INS_INVPCID = 246 , X86_INS_INVVPID = 247 , X86_INS_IRET = 248 , X86_INS_IRETD = 249 , X86_INS_IRETQ = 250 , X86_INS_FISTTP = 251 , X86_INS_FIST = 252 , X86_INS_FISTP = 253 , X86_INS_JAE = 254 , X86_INS_JA = 255 , X86_INS_JBE = 256 , X86_INS_JB = 257 , X86_INS_JCXZ = 258 , X86_INS_JECXZ = 259 , X86_INS_JE = 260 , X86_INS_JGE = 261 , X86_INS_JG = 262 , X86_INS_JLE = 263 , X86_INS_JL = 264 , X86_INS_JNE = 265 , X86_INS_JNO = 266 , X86_INS_JNP = 267 , X86_INS_JNS = 268 , X86_INS_JO = 269 , X86_INS_JP = 270 , X86_INS_JRCXZ = 271 , X86_INS_JS = 272 , X86_INS_KADDB = 273 , X86_INS_KADDD = 274 , X86_INS_KADDQ = 275 , X86_INS_KADDW = 276 , X86_INS_KANDB = 277 , X86_INS_KANDD = 278 , X86_INS_KANDNB = 279 , X86_INS_KANDND = 280 , X86_INS_KANDNQ = 281 , X86_INS_KANDNW = 282 , X86_INS_KANDQ = 283 , X86_INS_KANDW = 284 , X86_INS_KMOVB = 285 , X86_INS_KMOVD = 286 , X86_INS_KMOVQ = 287 , X86_INS_KMOVW = 288 , X86_INS_KNOTB = 289 , X86_INS_KNOTD = 290 , X86_INS_KNOTQ = 291 , X86_INS_KNOTW = 292 , X86_INS_KORB = 293 , X86_INS_KORD = 294 , X86_INS_KORQ = 295 , X86_INS_KORTESTB = 296 , X86_INS_KORTESTD = 297 , X86_INS_KORTESTQ = 298 , X86_INS_KORTESTW = 299 , X86_INS_KORW = 300 , X86_INS_KSHIFTLB = 301 , X86_INS_KSHIFTLD = 302 , X86_INS_KSHIFTLQ = 303 , X86_INS_KSHIFTLW = 304 , X86_INS_KSHIFTRB = 305 , X86_INS_KSHIFTRD = 306 , X86_INS_KSHIFTRQ = 307 , X86_INS_KSHIFTRW = 308 , X86_INS_KTESTB = 309 , X86_INS_KTESTD = 310 , X86_INS_KTESTQ = 311 , X86_INS_KTESTW = 312 , X86_INS_KUNPCKBW = 313 , X86_INS_KUNPCKDQ = 314 , X86_INS_KUNPCKWD = 315 , X86_INS_KXNORB = 316 , X86_INS_KXNORD = 317 , X86_INS_KXNORQ = 318 , X86_INS_KXNORW = 319 , X86_INS_KXORB = 320 , X86_INS_KXORD = 321 , X86_INS_KXORQ = 322 , X86_INS_KXORW = 323 , X86_INS_LAHF = 324 , X86_INS_LAR = 325 , X86_INS_LDDQU = 326 , X86_INS_LDMXCSR = 327 , X86_INS_LDS = 328 , X86_INS_FLDZ = 329 , X86_INS_FLD1 = 330 , X86_INS_FLD = 331 , X86_INS_LEA = 332 , X86_INS_LEAVE = 333 , X86_INS_LES = 334 , X86_INS_LFENCE = 335 , X86_INS_LFS = 336 , X86_INS_LGDT = 337 , X86_INS_LGS = 338 , X86_INS_LIDT = 339 , X86_INS_LLDT = 340 , X86_INS_LLWPCB = 341 , X86_INS_LMSW = 342 , X86_INS_LOCK = 343 , X86_INS_LODSB = 344 , X86_INS_LODSD = 345 , X86_INS_LODSQ = 346 , X86_INS_LODSW = 347 , X86_INS_LOOP = 348 , X86_INS_LOOPE = 349 , X86_INS_LOOPNE = 350 , X86_INS_RETF = 351 , X86_INS_RETFQ = 352 , X86_INS_LSL = 353 , X86_INS_LSS = 354 , X86_INS_LTR = 355 , X86_INS_LWPINS = 356 , X86_INS_LWPVAL = 357 , X86_INS_LZCNT = 358 , X86_INS_MASKMOVDQU = 359 , X86_INS_MAXPD = 360 , X86_INS_MAXPS = 361 , X86_INS_MAXSD = 362 , X86_INS_MAXSS = 363 , X86_INS_MFENCE = 364 , X86_INS_MINPD = 365 , X86_INS_MINPS = 366 , X86_INS_MINSD = 367 , X86_INS_MINSS = 368 , X86_INS_CVTPD2PI = 369 , X86_INS_CVTPI2PD = 370 , X86_INS_CVTPI2PS = 371 , X86_INS_CVTPS2PI = 372 , X86_INS_CVTTPD2PI = 373 , X86_INS_CVTTPS2PI = 374 , X86_INS_EMMS = 375 , X86_INS_MASKMOVQ = 376 , X86_INS_MOVD = 377 , X86_INS_MOVQ = 378 , X86_INS_MOVDQ2Q = 379 , X86_INS_MOVNTQ = 380 , X86_INS_MOVQ2DQ = 381 , X86_INS_PABSB = 382 , X86_INS_PABSD = 383 , X86_INS_PABSW = 384 , X86_INS_PACKSSDW = 385 , X86_INS_PACKSSWB = 386 , X86_INS_PACKUSWB = 387 , X86_INS_PADDB = 388 , X86_INS_PADDD = 389 , X86_INS_PADDQ = 390 , X86_INS_PADDSB = 391 , X86_INS_PADDSW = 392 , X86_INS_PADDUSB = 393 , X86_INS_PADDUSW = 394 , X86_INS_PADDW = 395 , X86_INS_PALIGNR = 396 , X86_INS_PANDN = 397 , X86_INS_PAND = 398 , X86_INS_PAVGB = 399 , X86_INS_PAVGW = 400 , X86_INS_PCMPEQB = 401 , X86_INS_PCMPEQD = 402 , X86_INS_PCMPEQW = 403 , X86_INS_PCMPGTB = 404 , X86_INS_PCMPGTD = 405 , X86_INS_PCMPGTW = 406 , X86_INS_PEXTRW = 407 , X86_INS_PHADDD = 408 , X86_INS_PHADDSW = 409 , X86_INS_PHADDW = 410 , X86_INS_PHSUBD = 411 , X86_INS_PHSUBSW = 412 , X86_INS_PHSUBW = 413 , X86_INS_PINSRW = 414 , X86_INS_PMADDUBSW = 415 , X86_INS_PMADDWD = 416 , X86_INS_PMAXSW = 417 , X86_INS_PMAXUB = 418 , X86_INS_PMINSW = 419 , X86_INS_PMINUB = 420 , X86_INS_PMOVMSKB = 421 , X86_INS_PMULHRSW = 422 , X86_INS_PMULHUW = 423 , X86_INS_PMULHW = 424 , X86_INS_PMULLW = 425 , X86_INS_PMULUDQ = 426 , X86_INS_POR = 427 , X86_INS_PSADBW = 428 , X86_INS_PSHUFB = 429 , X86_INS_PSHUFW = 430 , X86_INS_PSIGNB = 431 , X86_INS_PSIGND = 432 , X86_INS_PSIGNW = 433 , X86_INS_PSLLD = 434 , X86_INS_PSLLQ = 435 , X86_INS_PSLLW = 436 , X86_INS_PSRAD = 437 , X86_INS_PSRAW = 438 , X86_INS_PSRLD = 439 , X86_INS_PSRLQ = 440 , X86_INS_PSRLW = 441 , X86_INS_PSUBB = 442 , X86_INS_PSUBD = 443 , X86_INS_PSUBQ = 444 , X86_INS_PSUBSB = 445 , X86_INS_PSUBSW = 446 , X86_INS_PSUBUSB = 447 , X86_INS_PSUBUSW = 448 , X86_INS_PSUBW = 449 , X86_INS_PUNPCKHBW = 450 , X86_INS_PUNPCKHDQ = 451 , X86_INS_PUNPCKHWD = 452 , X86_INS_PUNPCKLBW = 453 , X86_INS_PUNPCKLDQ = 454 , X86_INS_PUNPCKLWD = 455 , X86_INS_PXOR = 456 , X86_INS_MONITORX = 457 , X86_INS_MONITOR = 458 , X86_INS_MONTMUL = 459 , X86_INS_MOV = 460 , X86_INS_MOVABS = 461 , X86_INS_MOVAPD = 462 , X86_INS_MOVAPS = 463 , X86_INS_MOVBE = 464 , X86_INS_MOVDDUP = 465 , X86_INS_MOVDIR64B = 466 , X86_INS_MOVDIRI = 467 , X86_INS_MOVDQA = 468 , X86_INS_MOVDQU = 469 , X86_INS_MOVHLPS = 470 , X86_INS_MOVHPD = 471 , X86_INS_MOVHPS = 472 , X86_INS_MOVLHPS = 473 , X86_INS_MOVLPD = 474 , X86_INS_MOVLPS = 475 , X86_INS_MOVMSKPD = 476 , X86_INS_MOVMSKPS = 477 , X86_INS_MOVNTDQA = 478 , X86_INS_MOVNTDQ = 479 , X86_INS_MOVNTI = 480 , X86_INS_MOVNTPD = 481 , X86_INS_MOVNTPS = 482 , X86_INS_MOVNTSD = 483 , X86_INS_MOVNTSS = 484 , X86_INS_MOVSB = 485 , X86_INS_MOVSD = 486 , X86_INS_MOVSHDUP = 487 , X86_INS_MOVSLDUP = 488 , X86_INS_MOVSQ = 489 , X86_INS_MOVSS = 490 , X86_INS_MOVSW = 491 , X86_INS_MOVSX = 492 , X86_INS_MOVSXD = 493 , X86_INS_MOVUPD = 494 , X86_INS_MOVUPS = 495 , X86_INS_MOVZX = 496 , X86_INS_MPSADBW = 497 , X86_INS_MUL = 498 , X86_INS_MULPD = 499 , X86_INS_MULPS = 500 , X86_INS_MULSD = 501 , X86_INS_MULSS = 502 , X86_INS_MULX = 503 , X86_INS_FMUL = 504 , X86_INS_FIMUL = 505 , X86_INS_FMULP = 506 , X86_INS_MWAITX = 507 , X86_INS_MWAIT = 508 , X86_INS_NEG = 509 , X86_INS_NOP = 510 , X86_INS_NOT = 511 , X86_INS_OR = 512 , X86_INS_ORPD = 513 , X86_INS_ORPS = 514 , X86_INS_OUT = 515 , X86_INS_OUTSB = 516 , X86_INS_OUTSD = 517 , X86_INS_OUTSW = 518 , X86_INS_PACKUSDW = 519 , X86_INS_PAUSE = 520 , X86_INS_PAVGUSB = 521 , X86_INS_PBLENDVB = 522 , X86_INS_PBLENDW = 523 , X86_INS_PCLMULQDQ = 524 , X86_INS_PCMPEQQ = 525 , X86_INS_PCMPESTRI = 526 , X86_INS_PCMPESTRM = 527 , X86_INS_PCMPGTQ = 528 , X86_INS_PCMPISTRI = 529 , X86_INS_PCMPISTRM = 530 , X86_INS_PCONFIG = 531 , X86_INS_PDEP = 532 , X86_INS_PEXT = 533 , X86_INS_PEXTRB = 534 , X86_INS_PEXTRD = 535 , X86_INS_PEXTRQ = 536 , X86_INS_PF2ID = 537 , X86_INS_PF2IW = 538 , X86_INS_PFACC = 539 , X86_INS_PFADD = 540 , X86_INS_PFCMPEQ = 541 , X86_INS_PFCMPGE = 542 , X86_INS_PFCMPGT = 543 , X86_INS_PFMAX = 544 , X86_INS_PFMIN = 545 , X86_INS_PFMUL = 546 , X86_INS_PFNACC = 547 , X86_INS_PFPNACC = 548 , X86_INS_PFRCPIT1 = 549 , X86_INS_PFRCPIT2 = 550 , X86_INS_PFRCP = 551 , X86_INS_PFRSQIT1 = 552 , X86_INS_PFRSQRT = 553 , X86_INS_PFSUBR = 554 , X86_INS_PFSUB = 555 , X86_INS_PHMINPOSUW = 556 , X86_INS_PI2FD = 557 , X86_INS_PI2FW = 558 , X86_INS_PINSRB = 559 , X86_INS_PINSRD = 560 , X86_INS_PINSRQ = 561 , X86_INS_PMAXSB = 562 , X86_INS_PMAXSD = 563 , X86_INS_PMAXUD = 564 , X86_INS_PMAXUW = 565 , X86_INS_PMINSB = 566 , X86_INS_PMINSD = 567 , X86_INS_PMINUD = 568 , X86_INS_PMINUW = 569 , X86_INS_PMOVSXBD = 570 , X86_INS_PMOVSXBQ = 571 , X86_INS_PMOVSXBW = 572 , X86_INS_PMOVSXDQ = 573 , X86_INS_PMOVSXWD = 574 , X86_INS_PMOVSXWQ = 575 , X86_INS_PMOVZXBD = 576 , X86_INS_PMOVZXBQ = 577 , X86_INS_PMOVZXBW = 578 , X86_INS_PMOVZXDQ = 579 , X86_INS_PMOVZXWD = 580 , X86_INS_PMOVZXWQ = 581 , X86_INS_PMULDQ = 582 , X86_INS_PMULHRW = 583 , X86_INS_PMULLD = 584 , X86_INS_POP = 585 , X86_INS_POPAW = 586 , X86_INS_POPAL = 587 , X86_INS_POPCNT = 588 , X86_INS_POPF = 589 , X86_INS_POPFD = 590 , X86_INS_POPFQ = 591 , X86_INS_PREFETCH = 592 , X86_INS_PREFETCHNTA = 593 , X86_INS_PREFETCHT0 = 594 , X86_INS_PREFETCHT1 = 595 , X86_INS_PREFETCHT2 = 596 , X86_INS_PREFETCHW = 597 , X86_INS_PREFETCHWT1 = 598 , X86_INS_PSHUFD = 599 , X86_INS_PSHUFHW = 600 , X86_INS_PSHUFLW = 601 , X86_INS_PSLLDQ = 602 , X86_INS_PSRLDQ = 603 , X86_INS_PSWAPD = 604 , X86_INS_PTEST = 605 , X86_INS_PTWRITE = 606 , X86_INS_PUNPCKHQDQ = 607 , X86_INS_PUNPCKLQDQ = 608 , X86_INS_PUSH = 609 , X86_INS_PUSHAW = 610 , X86_INS_PUSHAL = 611 , X86_INS_PUSHF = 612 , X86_INS_PUSHFD = 613 , X86_INS_PUSHFQ = 614 , X86_INS_RCL = 615 , X86_INS_RCPPS = 616 , X86_INS_RCPSS = 617 , X86_INS_RCR = 618 , X86_INS_RDFSBASE = 619 , X86_INS_RDGSBASE = 620 , X86_INS_RDMSR = 621 , X86_INS_RDPID = 622 , X86_INS_RDPKRU = 623 , X86_INS_RDPMC = 624 , X86_INS_RDRAND = 625 , X86_INS_RDSEED = 626 , X86_INS_RDSSPD = 627 , X86_INS_RDSSPQ = 628 , X86_INS_RDTSC = 629 , X86_INS_RDTSCP = 630 , X86_INS_REPNE = 631 , X86_INS_REP = 632 , X86_INS_RET = 633 , X86_INS_REX64 = 634 , X86_INS_ROL = 635 , X86_INS_ROR = 636 , X86_INS_RORX = 637 , X86_INS_ROUNDPD = 638 , X86_INS_ROUNDPS = 639 , X86_INS_ROUNDSD = 640 , X86_INS_ROUNDSS = 641 , X86_INS_RSM = 642 , X86_INS_RSQRTPS = 643 , X86_INS_RSQRTSS = 644 , X86_INS_RSTORSSP = 645 , X86_INS_SAHF = 646 , X86_INS_SAL = 647 , X86_INS_SALC = 648 , X86_INS_SAR = 649 , X86_INS_SARX = 650 , X86_INS_SAVEPREVSSP = 651 , X86_INS_SBB = 652 , X86_INS_SCASB = 653 , X86_INS_SCASD = 654 , X86_INS_SCASQ = 655 , X86_INS_SCASW = 656 , X86_INS_SETAE = 657 , X86_INS_SETA = 658 , X86_INS_SETBE = 659 , X86_INS_SETB = 660 , X86_INS_SETE = 661 , X86_INS_SETGE = 662 , X86_INS_SETG = 663 , X86_INS_SETLE = 664 , X86_INS_SETL = 665 , X86_INS_SETNE = 666 , X86_INS_SETNO = 667 , X86_INS_SETNP = 668 , X86_INS_SETNS = 669 , X86_INS_SETO = 670 , X86_INS_SETP = 671 , X86_INS_SETSSBSY = 672 , X86_INS_SETS = 673 , X86_INS_SFENCE = 674 , X86_INS_SGDT = 675 , X86_INS_SHA1MSG1 = 676 , X86_INS_SHA1MSG2 = 677 , X86_INS_SHA1NEXTE = 678 , X86_INS_SHA1RNDS4 = 679 , X86_INS_SHA256MSG1 = 680 , X86_INS_SHA256MSG2 = 681 , X86_INS_SHA256RNDS2 = 682 , X86_INS_SHL = 683 , X86_INS_SHLD = 684 , X86_INS_SHLX = 685 , X86_INS_SHR = 686 , X86_INS_SHRD = 687 , X86_INS_SHRX = 688 , X86_INS_SHUFPD = 689 , X86_INS_SHUFPS = 690 , X86_INS_SIDT = 691 , X86_INS_FSIN = 692 , X86_INS_SKINIT = 693 , X86_INS_SLDT = 694 , X86_INS_SLWPCB = 695 , X86_INS_SMSW = 696 , X86_INS_SQRTPD = 697 , X86_INS_SQRTPS = 698 , X86_INS_SQRTSD = 699 , X86_INS_SQRTSS = 700 , X86_INS_FSQRT = 701 , X86_INS_STAC = 702 , X86_INS_STC = 703 , X86_INS_STD = 704 , X86_INS_STGI = 705 , X86_INS_STI = 706 , X86_INS_STMXCSR = 707 , X86_INS_STOSB = 708 , X86_INS_STOSD = 709 , X86_INS_STOSQ = 710 , X86_INS_STOSW = 711 , X86_INS_STR = 712 , X86_INS_FST = 713 , X86_INS_FSTP = 714 , X86_INS_SUB = 715 , X86_INS_SUBPD = 716 , X86_INS_SUBPS = 717 , X86_INS_FSUBR = 718 , X86_INS_FISUBR = 719 , X86_INS_FSUBRP = 720 , X86_INS_SUBSD = 721 , X86_INS_SUBSS = 722 , X86_INS_FSUB = 723 , X86_INS_FISUB = 724 , X86_INS_FSUBP = 725 , X86_INS_SWAPGS = 726 , X86_INS_SYSCALL = 727 , X86_INS_SYSENTER = 728 , X86_INS_SYSEXIT = 729 , X86_INS_SYSEXITQ = 730 , X86_INS_SYSRET = 731 , X86_INS_SYSRETQ = 732 , X86_INS_T1MSKC = 733 , X86_INS_TEST = 734 , X86_INS_TPAUSE = 735 , X86_INS_FTST = 736 , X86_INS_TZCNT = 737 , X86_INS_TZMSK = 738 , X86_INS_UCOMISD = 739 , X86_INS_UCOMISS = 740 , X86_INS_FUCOMPI = 741 , X86_INS_FUCOMI = 742 , X86_INS_FUCOMPP = 743 , X86_INS_FUCOMP = 744 , X86_INS_FUCOM = 745 , X86_INS_UD0 = 746 , X86_INS_UD1 = 747 , X86_INS_UD2 = 748 , X86_INS_UMONITOR = 749 , X86_INS_UMWAIT = 750 , X86_INS_UNPCKHPD = 751 , X86_INS_UNPCKHPS = 752 , X86_INS_UNPCKLPD = 753 , X86_INS_UNPCKLPS = 754 , X86_INS_V4FMADDPS = 755 , X86_INS_V4FMADDSS = 756 , X86_INS_V4FNMADDPS = 757 , X86_INS_V4FNMADDSS = 758 , X86_INS_VADDPD = 759 , X86_INS_VADDPS = 760 , X86_INS_VADDSD = 761 , X86_INS_VADDSS = 762 , X86_INS_VADDSUBPD = 763 , X86_INS_VADDSUBPS = 764 , X86_INS_VAESDECLAST = 765 , X86_INS_VAESDEC = 766 , X86_INS_VAESENCLAST = 767 , X86_INS_VAESENC = 768 , X86_INS_VAESIMC = 769 , X86_INS_VAESKEYGENASSIST = 770 , X86_INS_VALIGND = 771 , X86_INS_VALIGNQ = 772 , X86_INS_VANDNPD = 773 , X86_INS_VANDNPS = 774 , X86_INS_VANDPD = 775 , X86_INS_VANDPS = 776 , X86_INS_VBLENDMPD = 777 , X86_INS_VBLENDMPS = 778 , X86_INS_VBLENDPD = 779 , X86_INS_VBLENDPS = 780 , X86_INS_VBLENDVPD = 781 , X86_INS_VBLENDVPS = 782 , X86_INS_VBROADCASTF128 = 783 , X86_INS_VBROADCASTF32X2 = 784 , X86_INS_VBROADCASTF32X4 = 785 , X86_INS_VBROADCASTF32X8 = 786 , X86_INS_VBROADCASTF64X2 = 787 , X86_INS_VBROADCASTF64X4 = 788 , X86_INS_VBROADCASTI128 = 789 , X86_INS_VBROADCASTI32X2 = 790 , X86_INS_VBROADCASTI32X4 = 791 , X86_INS_VBROADCASTI32X8 = 792 , X86_INS_VBROADCASTI64X2 = 793 , X86_INS_VBROADCASTI64X4 = 794 , X86_INS_VBROADCASTSD = 795 , X86_INS_VBROADCASTSS = 796 , X86_INS_VCMP = 797 , X86_INS_VCMPPD = 798 , X86_INS_VCMPPS = 799 , X86_INS_VCMPSD = 800 , X86_INS_VCMPSS = 801 , X86_INS_VCOMISD = 802 , X86_INS_VCOMISS = 803 , X86_INS_VCOMPRESSPD = 804 , X86_INS_VCOMPRESSPS = 805 , X86_INS_VCVTDQ2PD = 806 , X86_INS_VCVTDQ2PS = 807 , X86_INS_VCVTPD2DQ = 808 , X86_INS_VCVTPD2PS = 809 , X86_INS_VCVTPD2QQ = 810 , X86_INS_VCVTPD2UDQ = 811 , X86_INS_VCVTPD2UQQ = 812 , X86_INS_VCVTPH2PS = 813 , X86_INS_VCVTPS2DQ = 814 , X86_INS_VCVTPS2PD = 815 , X86_INS_VCVTPS2PH = 816 , X86_INS_VCVTPS2QQ = 817 , X86_INS_VCVTPS2UDQ = 818 , X86_INS_VCVTPS2UQQ = 819 , X86_INS_VCVTQQ2PD = 820 , X86_INS_VCVTQQ2PS = 821 , X86_INS_VCVTSD2SI = 822 , X86_INS_VCVTSD2SS = 823 , X86_INS_VCVTSD2USI = 824 , X86_INS_VCVTSI2SD = 825 , X86_INS_VCVTSI2SS = 826 , X86_INS_VCVTSS2SD = 827 , X86_INS_VCVTSS2SI = 828 , X86_INS_VCVTSS2USI = 829 , X86_INS_VCVTTPD2DQ = 830 , X86_INS_VCVTTPD2QQ = 831 , X86_INS_VCVTTPD2UDQ = 832 , X86_INS_VCVTTPD2UQQ = 833 , X86_INS_VCVTTPS2DQ = 834 , X86_INS_VCVTTPS2QQ = 835 , X86_INS_VCVTTPS2UDQ = 836 , X86_INS_VCVTTPS2UQQ = 837 , X86_INS_VCVTTSD2SI = 838 , X86_INS_VCVTTSD2USI = 839 , X86_INS_VCVTTSS2SI = 840 , X86_INS_VCVTTSS2USI = 841 , X86_INS_VCVTUDQ2PD = 842 , X86_INS_VCVTUDQ2PS = 843 , X86_INS_VCVTUQQ2PD = 844 , X86_INS_VCVTUQQ2PS = 845 , X86_INS_VCVTUSI2SD = 846 , X86_INS_VCVTUSI2SS = 847 , X86_INS_VDBPSADBW = 848 , X86_INS_VDIVPD = 849 , X86_INS_VDIVPS = 850 , X86_INS_VDIVSD = 851 , X86_INS_VDIVSS = 852 , X86_INS_VDPPD = 853 , X86_INS_VDPPS = 854 , X86_INS_VERR = 855 , X86_INS_VERW = 856 , X86_INS_VEXP2PD = 857 , X86_INS_VEXP2PS = 858 , X86_INS_VEXPANDPD = 859 , X86_INS_VEXPANDPS = 860 , X86_INS_VEXTRACTF128 = 861 , X86_INS_VEXTRACTF32X4 = 862 , X86_INS_VEXTRACTF32X8 = 863 , X86_INS_VEXTRACTF64X2 = 864 , X86_INS_VEXTRACTF64X4 = 865 , X86_INS_VEXTRACTI128 = 866 , X86_INS_VEXTRACTI32X4 = 867 , X86_INS_VEXTRACTI32X8 = 868 , X86_INS_VEXTRACTI64X2 = 869 , X86_INS_VEXTRACTI64X4 = 870 , X86_INS_VEXTRACTPS = 871 , X86_INS_VFIXUPIMMPD = 872 , X86_INS_VFIXUPIMMPS = 873 , X86_INS_VFIXUPIMMSD = 874 , X86_INS_VFIXUPIMMSS = 875 , X86_INS_VFMADD132PD = 876 , X86_INS_VFMADD132PS = 877 , X86_INS_VFMADD132SD = 878 , X86_INS_VFMADD132SS = 879 , X86_INS_VFMADD213PD = 880 , X86_INS_VFMADD213PS = 881 , X86_INS_VFMADD213SD = 882 , X86_INS_VFMADD213SS = 883 , X86_INS_VFMADD231PD = 884 , X86_INS_VFMADD231PS = 885 , X86_INS_VFMADD231SD = 886 , X86_INS_VFMADD231SS = 887 , X86_INS_VFMADDPD = 888 , X86_INS_VFMADDPS = 889 , X86_INS_VFMADDSD = 890 , X86_INS_VFMADDSS = 891 , X86_INS_VFMADDSUB132PD = 892 , X86_INS_VFMADDSUB132PS = 893 , X86_INS_VFMADDSUB213PD = 894 , X86_INS_VFMADDSUB213PS = 895 , X86_INS_VFMADDSUB231PD = 896 , X86_INS_VFMADDSUB231PS = 897 , X86_INS_VFMADDSUBPD = 898 , X86_INS_VFMADDSUBPS = 899 , X86_INS_VFMSUB132PD = 900 , X86_INS_VFMSUB132PS = 901 , X86_INS_VFMSUB132SD = 902 , X86_INS_VFMSUB132SS = 903 , X86_INS_VFMSUB213PD = 904 , X86_INS_VFMSUB213PS = 905 , X86_INS_VFMSUB213SD = 906 , X86_INS_VFMSUB213SS = 907 , X86_INS_VFMSUB231PD = 908 , X86_INS_VFMSUB231PS = 909 , X86_INS_VFMSUB231SD = 910 , X86_INS_VFMSUB231SS = 911 , X86_INS_VFMSUBADD132PD = 912 , X86_INS_VFMSUBADD132PS = 913 , X86_INS_VFMSUBADD213PD = 914 , X86_INS_VFMSUBADD213PS = 915 , X86_INS_VFMSUBADD231PD = 916 , X86_INS_VFMSUBADD231PS = 917 , X86_INS_VFMSUBADDPD = 918 , X86_INS_VFMSUBADDPS = 919 , X86_INS_VFMSUBPD = 920 , X86_INS_VFMSUBPS = 921 , X86_INS_VFMSUBSD = 922 , X86_INS_VFMSUBSS = 923 , X86_INS_VFNMADD132PD = 924 , X86_INS_VFNMADD132PS = 925 , X86_INS_VFNMADD132SD = 926 , X86_INS_VFNMADD132SS = 927 , X86_INS_VFNMADD213PD = 928 , X86_INS_VFNMADD213PS = 929 , X86_INS_VFNMADD213SD = 930 , X86_INS_VFNMADD213SS = 931 , X86_INS_VFNMADD231PD = 932 , X86_INS_VFNMADD231PS = 933 , X86_INS_VFNMADD231SD = 934 , X86_INS_VFNMADD231SS = 935 , X86_INS_VFNMADDPD = 936 , X86_INS_VFNMADDPS = 937 , X86_INS_VFNMADDSD = 938 , X86_INS_VFNMADDSS = 939 , X86_INS_VFNMSUB132PD = 940 , X86_INS_VFNMSUB132PS = 941 , X86_INS_VFNMSUB132SD = 942 , X86_INS_VFNMSUB132SS = 943 , X86_INS_VFNMSUB213PD = 944 , X86_INS_VFNMSUB213PS = 945 , X86_INS_VFNMSUB213SD = 946 , X86_INS_VFNMSUB213SS = 947 , X86_INS_VFNMSUB231PD = 948 , X86_INS_VFNMSUB231PS = 949 , X86_INS_VFNMSUB231SD = 950 , X86_INS_VFNMSUB231SS = 951 , X86_INS_VFNMSUBPD = 952 , X86_INS_VFNMSUBPS = 953 , X86_INS_VFNMSUBSD = 954 , X86_INS_VFNMSUBSS = 955 , X86_INS_VFPCLASSPD = 956 , X86_INS_VFPCLASSPS = 957 , X86_INS_VFPCLASSSD = 958 , X86_INS_VFPCLASSSS = 959 , X86_INS_VFRCZPD = 960 , X86_INS_VFRCZPS = 961 , X86_INS_VFRCZSD = 962 , X86_INS_VFRCZSS = 963 , X86_INS_VGATHERDPD = 964 , X86_INS_VGATHERDPS = 965 , X86_INS_VGATHERPF0DPD = 966 , X86_INS_VGATHERPF0DPS = 967 , X86_INS_VGATHERPF0QPD = 968 , X86_INS_VGATHERPF0QPS = 969 , X86_INS_VGATHERPF1DPD = 970 , X86_INS_VGATHERPF1DPS = 971 , X86_INS_VGATHERPF1QPD = 972 , X86_INS_VGATHERPF1QPS = 973 , X86_INS_VGATHERQPD = 974 , X86_INS_VGATHERQPS = 975 , X86_INS_VGETEXPPD = 976 , X86_INS_VGETEXPPS = 977 , X86_INS_VGETEXPSD = 978 , X86_INS_VGETEXPSS = 979 , X86_INS_VGETMANTPD = 980 , X86_INS_VGETMANTPS = 981 , X86_INS_VGETMANTSD = 982 , X86_INS_VGETMANTSS = 983 , X86_INS_VGF2P8AFFINEINVQB = 984 , X86_INS_VGF2P8AFFINEQB = 985 , X86_INS_VGF2P8MULB = 986 , X86_INS_VHADDPD = 987 , X86_INS_VHADDPS = 988 , X86_INS_VHSUBPD = 989 , X86_INS_VHSUBPS = 990 , X86_INS_VINSERTF128 = 991 , X86_INS_VINSERTF32X4 = 992 , X86_INS_VINSERTF32X8 = 993 , X86_INS_VINSERTF64X2 = 994 , X86_INS_VINSERTF64X4 = 995 , X86_INS_VINSERTI128 = 996 , X86_INS_VINSERTI32X4 = 997 , X86_INS_VINSERTI32X8 = 998 , X86_INS_VINSERTI64X2 = 999 , X86_INS_VINSERTI64X4 = 1000 , X86_INS_VINSERTPS = 1001 , X86_INS_VLDDQU = 1002 , X86_INS_VLDMXCSR = 1003 , X86_INS_VMASKMOVDQU = 1004 , X86_INS_VMASKMOVPD = 1005 , X86_INS_VMASKMOVPS = 1006 , X86_INS_VMAXPD = 1007 , X86_INS_VMAXPS = 1008 , X86_INS_VMAXSD = 1009 , X86_INS_VMAXSS = 1010 , X86_INS_VMCALL = 1011 , X86_INS_VMCLEAR = 1012 , X86_INS_VMFUNC = 1013 , X86_INS_VMINPD = 1014 , X86_INS_VMINPS = 1015 , X86_INS_VMINSD = 1016 , X86_INS_VMINSS = 1017 , X86_INS_VMLAUNCH = 1018 , X86_INS_VMLOAD = 1019 , X86_INS_VMMCALL = 1020 , X86_INS_VMOVQ = 1021 , X86_INS_VMOVAPD = 1022 , X86_INS_VMOVAPS = 1023 , X86_INS_VMOVDDUP = 1024 , X86_INS_VMOVD = 1025 , X86_INS_VMOVDQA32 = 1026 , X86_INS_VMOVDQA64 = 1027 , X86_INS_VMOVDQA = 1028 , X86_INS_VMOVDQU16 = 1029 , X86_INS_VMOVDQU32 = 1030 , X86_INS_VMOVDQU64 = 1031 , X86_INS_VMOVDQU8 = 1032 , X86_INS_VMOVDQU = 1033 , X86_INS_VMOVHLPS = 1034 , X86_INS_VMOVHPD = 1035 , X86_INS_VMOVHPS = 1036 , X86_INS_VMOVLHPS = 1037 , X86_INS_VMOVLPD = 1038 , X86_INS_VMOVLPS = 1039 , X86_INS_VMOVMSKPD = 1040 , X86_INS_VMOVMSKPS = 1041 , X86_INS_VMOVNTDQA = 1042 , X86_INS_VMOVNTDQ = 1043 , X86_INS_VMOVNTPD = 1044 , X86_INS_VMOVNTPS = 1045 , X86_INS_VMOVSD = 1046 , X86_INS_VMOVSHDUP = 1047 , X86_INS_VMOVSLDUP = 1048 , X86_INS_VMOVSS = 1049 , X86_INS_VMOVUPD = 1050 , X86_INS_VMOVUPS = 1051 , X86_INS_VMPSADBW = 1052 , X86_INS_VMPTRLD = 1053 , X86_INS_VMPTRST = 1054 , X86_INS_VMREAD = 1055 , X86_INS_VMRESUME = 1056 , X86_INS_VMRUN = 1057 , X86_INS_VMSAVE = 1058 , X86_INS_VMULPD = 1059 , X86_INS_VMULPS = 1060 , X86_INS_VMULSD = 1061 , X86_INS_VMULSS = 1062 , X86_INS_VMWRITE = 1063 , X86_INS_VMXOFF = 1064 , X86_INS_VMXON = 1065 , X86_INS_VORPD = 1066 , X86_INS_VORPS = 1067 , X86_INS_VP4DPWSSDS = 1068 , X86_INS_VP4DPWSSD = 1069 , X86_INS_VPABSB = 1070 , X86_INS_VPABSD = 1071 , X86_INS_VPABSQ = 1072 , X86_INS_VPABSW = 1073 , X86_INS_VPACKSSDW = 1074 , X86_INS_VPACKSSWB = 1075 , X86_INS_VPACKUSDW = 1076 , X86_INS_VPACKUSWB = 1077 , X86_INS_VPADDB = 1078 , X86_INS_VPADDD = 1079 , X86_INS_VPADDQ = 1080 , X86_INS_VPADDSB = 1081 , X86_INS_VPADDSW = 1082 , X86_INS_VPADDUSB = 1083 , X86_INS_VPADDUSW = 1084 , X86_INS_VPADDW = 1085 , X86_INS_VPALIGNR = 1086 , X86_INS_VPANDD = 1087 , X86_INS_VPANDND = 1088 , X86_INS_VPANDNQ = 1089 , X86_INS_VPANDN = 1090 , X86_INS_VPANDQ = 1091 , X86_INS_VPAND = 1092 , X86_INS_VPAVGB = 1093 , X86_INS_VPAVGW = 1094 , X86_INS_VPBLENDD = 1095 , X86_INS_VPBLENDMB = 1096 , X86_INS_VPBLENDMD = 1097 , X86_INS_VPBLENDMQ = 1098 , X86_INS_VPBLENDMW = 1099 , X86_INS_VPBLENDVB = 1100 , X86_INS_VPBLENDW = 1101 , X86_INS_VPBROADCASTB = 1102 , X86_INS_VPBROADCASTD = 1103 , X86_INS_VPBROADCASTMB2Q = 1104 , X86_INS_VPBROADCASTMW2D = 1105 , X86_INS_VPBROADCASTQ = 1106 , X86_INS_VPBROADCASTW = 1107 , X86_INS_VPCLMULQDQ = 1108 , X86_INS_VPCMOV = 1109 , X86_INS_VPCMP = 1110 , X86_INS_VPCMPB = 1111 , X86_INS_VPCMPD = 1112 , X86_INS_VPCMPEQB = 1113 , X86_INS_VPCMPEQD = 1114 , X86_INS_VPCMPEQQ = 1115 , X86_INS_VPCMPEQW = 1116 , X86_INS_VPCMPESTRI = 1117 , X86_INS_VPCMPESTRM = 1118 , X86_INS_VPCMPGTB = 1119 , X86_INS_VPCMPGTD = 1120 , X86_INS_VPCMPGTQ = 1121 , X86_INS_VPCMPGTW = 1122 , X86_INS_VPCMPISTRI = 1123 , X86_INS_VPCMPISTRM = 1124 , X86_INS_VPCMPQ = 1125 , X86_INS_VPCMPUB = 1126 , X86_INS_VPCMPUD = 1127 , X86_INS_VPCMPUQ = 1128 , X86_INS_VPCMPUW = 1129 , X86_INS_VPCMPW = 1130 , X86_INS_VPCOM = 1131 , X86_INS_VPCOMB = 1132 , X86_INS_VPCOMD = 1133 , X86_INS_VPCOMPRESSB = 1134 , X86_INS_VPCOMPRESSD = 1135 , X86_INS_VPCOMPRESSQ = 1136 , X86_INS_VPCOMPRESSW = 1137 , X86_INS_VPCOMQ = 1138 , X86_INS_VPCOMUB = 1139 , X86_INS_VPCOMUD = 1140 , X86_INS_VPCOMUQ = 1141 , X86_INS_VPCOMUW = 1142 , X86_INS_VPCOMW = 1143 , X86_INS_VPCONFLICTD = 1144 , X86_INS_VPCONFLICTQ = 1145 , X86_INS_VPDPBUSDS = 1146 , X86_INS_VPDPBUSD = 1147 , X86_INS_VPDPWSSDS = 1148 , X86_INS_VPDPWSSD = 1149 , X86_INS_VPERM2F128 = 1150 , X86_INS_VPERM2I128 = 1151 , X86_INS_VPERMB = 1152 , X86_INS_VPERMD = 1153 , X86_INS_VPERMI2B = 1154 , X86_INS_VPERMI2D = 1155 , X86_INS_VPERMI2PD = 1156 , X86_INS_VPERMI2PS = 1157 , X86_INS_VPERMI2Q = 1158 , X86_INS_VPERMI2W = 1159 , X86_INS_VPERMIL2PD = 1160 , X86_INS_VPERMILPD = 1161 , X86_INS_VPERMIL2PS = 1162 , X86_INS_VPERMILPS = 1163 , X86_INS_VPERMPD = 1164 , X86_INS_VPERMPS = 1165 , X86_INS_VPERMQ = 1166 , X86_INS_VPERMT2B = 1167 , X86_INS_VPERMT2D = 1168 , X86_INS_VPERMT2PD = 1169 , X86_INS_VPERMT2PS = 1170 , X86_INS_VPERMT2Q = 1171 , X86_INS_VPERMT2W = 1172 , X86_INS_VPERMW = 1173 , X86_INS_VPEXPANDB = 1174 , X86_INS_VPEXPANDD = 1175 , X86_INS_VPEXPANDQ = 1176 , X86_INS_VPEXPANDW = 1177 , X86_INS_VPEXTRB = 1178 , X86_INS_VPEXTRD = 1179 , X86_INS_VPEXTRQ = 1180 , X86_INS_VPEXTRW = 1181 , X86_INS_VPGATHERDD = 1182 , X86_INS_VPGATHERDQ = 1183 , X86_INS_VPGATHERQD = 1184 , X86_INS_VPGATHERQQ = 1185 , X86_INS_VPHADDBD = 1186 , X86_INS_VPHADDBQ = 1187 , X86_INS_VPHADDBW = 1188 , X86_INS_VPHADDDQ = 1189 , X86_INS_VPHADDD = 1190 , X86_INS_VPHADDSW = 1191 , X86_INS_VPHADDUBD = 1192 , X86_INS_VPHADDUBQ = 1193 , X86_INS_VPHADDUBW = 1194 , X86_INS_VPHADDUDQ = 1195 , X86_INS_VPHADDUWD = 1196 , X86_INS_VPHADDUWQ = 1197 , X86_INS_VPHADDWD = 1198 , X86_INS_VPHADDWQ = 1199 , X86_INS_VPHADDW = 1200 , X86_INS_VPHMINPOSUW = 1201 , X86_INS_VPHSUBBW = 1202 , X86_INS_VPHSUBDQ = 1203 , X86_INS_VPHSUBD = 1204 , X86_INS_VPHSUBSW = 1205 , X86_INS_VPHSUBWD = 1206 , X86_INS_VPHSUBW = 1207 , X86_INS_VPINSRB = 1208 , X86_INS_VPINSRD = 1209 , X86_INS_VPINSRQ = 1210 , X86_INS_VPINSRW = 1211 , X86_INS_VPLZCNTD = 1212 , X86_INS_VPLZCNTQ = 1213 , X86_INS_VPMACSDD = 1214 , X86_INS_VPMACSDQH = 1215 , X86_INS_VPMACSDQL = 1216 , X86_INS_VPMACSSDD = 1217 , X86_INS_VPMACSSDQH = 1218 , X86_INS_VPMACSSDQL = 1219 , X86_INS_VPMACSSWD = 1220 , X86_INS_VPMACSSWW = 1221 , X86_INS_VPMACSWD = 1222 , X86_INS_VPMACSWW = 1223 , X86_INS_VPMADCSSWD = 1224 , X86_INS_VPMADCSWD = 1225 , X86_INS_VPMADD52HUQ = 1226 , X86_INS_VPMADD52LUQ = 1227 , X86_INS_VPMADDUBSW = 1228 , X86_INS_VPMADDWD = 1229 , X86_INS_VPMASKMOVD = 1230 , X86_INS_VPMASKMOVQ = 1231 , X86_INS_VPMAXSB = 1232 , X86_INS_VPMAXSD = 1233 , X86_INS_VPMAXSQ = 1234 , X86_INS_VPMAXSW = 1235 , X86_INS_VPMAXUB = 1236 , X86_INS_VPMAXUD = 1237 , X86_INS_VPMAXUQ = 1238 , X86_INS_VPMAXUW = 1239 , X86_INS_VPMINSB = 1240 , X86_INS_VPMINSD = 1241 , X86_INS_VPMINSQ = 1242 , X86_INS_VPMINSW = 1243 , X86_INS_VPMINUB = 1244 , X86_INS_VPMINUD = 1245 , X86_INS_VPMINUQ = 1246 , X86_INS_VPMINUW = 1247 , X86_INS_VPMOVB2M = 1248 , X86_INS_VPMOVD2M = 1249 , X86_INS_VPMOVDB = 1250 , X86_INS_VPMOVDW = 1251 , X86_INS_VPMOVM2B = 1252 , X86_INS_VPMOVM2D = 1253 , X86_INS_VPMOVM2Q = 1254 , X86_INS_VPMOVM2W = 1255 , X86_INS_VPMOVMSKB = 1256 , X86_INS_VPMOVQ2M = 1257 , X86_INS_VPMOVQB = 1258 , X86_INS_VPMOVQD = 1259 , X86_INS_VPMOVQW = 1260 , X86_INS_VPMOVSDB = 1261 , X86_INS_VPMOVSDW = 1262 , X86_INS_VPMOVSQB = 1263 , X86_INS_VPMOVSQD = 1264 , X86_INS_VPMOVSQW = 1265 , X86_INS_VPMOVSWB = 1266 , X86_INS_VPMOVSXBD = 1267 , X86_INS_VPMOVSXBQ = 1268 , X86_INS_VPMOVSXBW = 1269 , X86_INS_VPMOVSXDQ = 1270 , X86_INS_VPMOVSXWD = 1271 , X86_INS_VPMOVSXWQ = 1272 , X86_INS_VPMOVUSDB = 1273 , X86_INS_VPMOVUSDW = 1274 , X86_INS_VPMOVUSQB = 1275 , X86_INS_VPMOVUSQD = 1276 , X86_INS_VPMOVUSQW = 1277 , X86_INS_VPMOVUSWB = 1278 , X86_INS_VPMOVW2M = 1279 , X86_INS_VPMOVWB = 1280 , X86_INS_VPMOVZXBD = 1281 , X86_INS_VPMOVZXBQ = 1282 , X86_INS_VPMOVZXBW = 1283 , X86_INS_VPMOVZXDQ = 1284 , X86_INS_VPMOVZXWD = 1285 , X86_INS_VPMOVZXWQ = 1286 , X86_INS_VPMULDQ = 1287 , X86_INS_VPMULHRSW = 1288 , X86_INS_VPMULHUW = 1289 , X86_INS_VPMULHW = 1290 , X86_INS_VPMULLD = 1291 , X86_INS_VPMULLQ = 1292 , X86_INS_VPMULLW = 1293 , X86_INS_VPMULTISHIFTQB = 1294 , X86_INS_VPMULUDQ = 1295 , X86_INS_VPOPCNTB = 1296 , X86_INS_VPOPCNTD = 1297 , X86_INS_VPOPCNTQ = 1298 , X86_INS_VPOPCNTW = 1299 , X86_INS_VPORD = 1300 , X86_INS_VPORQ = 1301 , X86_INS_VPOR = 1302 , X86_INS_VPPERM = 1303 , X86_INS_VPROLD = 1304 , X86_INS_VPROLQ = 1305 , X86_INS_VPROLVD = 1306 , X86_INS_VPROLVQ = 1307 , X86_INS_VPRORD = 1308 , X86_INS_VPRORQ = 1309 , X86_INS_VPRORVD = 1310 , X86_INS_VPRORVQ = 1311 , X86_INS_VPROTB = 1312 , X86_INS_VPROTD = 1313 , X86_INS_VPROTQ = 1314 , X86_INS_VPROTW = 1315 , X86_INS_VPSADBW = 1316 , X86_INS_VPSCATTERDD = 1317 , X86_INS_VPSCATTERDQ = 1318 , X86_INS_VPSCATTERQD = 1319 , X86_INS_VPSCATTERQQ = 1320 , X86_INS_VPSHAB = 1321 , X86_INS_VPSHAD = 1322 , X86_INS_VPSHAQ = 1323 , X86_INS_VPSHAW = 1324 , X86_INS_VPSHLB = 1325 , X86_INS_VPSHLDD = 1326 , X86_INS_VPSHLDQ = 1327 , X86_INS_VPSHLDVD = 1328 , X86_INS_VPSHLDVQ = 1329 , X86_INS_VPSHLDVW = 1330 , X86_INS_VPSHLDW = 1331 , X86_INS_VPSHLD = 1332 , X86_INS_VPSHLQ = 1333 , X86_INS_VPSHLW = 1334 , X86_INS_VPSHRDD = 1335 , X86_INS_VPSHRDQ = 1336 , X86_INS_VPSHRDVD = 1337 , X86_INS_VPSHRDVQ = 1338 , X86_INS_VPSHRDVW = 1339 , X86_INS_VPSHRDW = 1340 , X86_INS_VPSHUFBITQMB = 1341 , X86_INS_VPSHUFB = 1342 , X86_INS_VPSHUFD = 1343 , X86_INS_VPSHUFHW = 1344 , X86_INS_VPSHUFLW = 1345 , X86_INS_VPSIGNB = 1346 , X86_INS_VPSIGND = 1347 , X86_INS_VPSIGNW = 1348 , X86_INS_VPSLLDQ = 1349 , X86_INS_VPSLLD = 1350 , X86_INS_VPSLLQ = 1351 , X86_INS_VPSLLVD = 1352 , X86_INS_VPSLLVQ = 1353 , X86_INS_VPSLLVW = 1354 , X86_INS_VPSLLW = 1355 , X86_INS_VPSRAD = 1356 , X86_INS_VPSRAQ = 1357 , X86_INS_VPSRAVD = 1358 , X86_INS_VPSRAVQ = 1359 , X86_INS_VPSRAVW = 1360 , X86_INS_VPSRAW = 1361 , X86_INS_VPSRLDQ = 1362 , X86_INS_VPSRLD = 1363 , X86_INS_VPSRLQ = 1364 , X86_INS_VPSRLVD = 1365 , X86_INS_VPSRLVQ = 1366 , X86_INS_VPSRLVW = 1367 , X86_INS_VPSRLW = 1368 , X86_INS_VPSUBB = 1369 , X86_INS_VPSUBD = 1370 , X86_INS_VPSUBQ = 1371 , X86_INS_VPSUBSB = 1372 , X86_INS_VPSUBSW = 1373 , X86_INS_VPSUBUSB = 1374 , X86_INS_VPSUBUSW = 1375 , X86_INS_VPSUBW = 1376 , X86_INS_VPTERNLOGD = 1377 , X86_INS_VPTERNLOGQ = 1378 , X86_INS_VPTESTMB = 1379 , X86_INS_VPTESTMD = 1380 , X86_INS_VPTESTMQ = 1381 , X86_INS_VPTESTMW = 1382 , X86_INS_VPTESTNMB = 1383 , X86_INS_VPTESTNMD = 1384 , X86_INS_VPTESTNMQ = 1385 , X86_INS_VPTESTNMW = 1386 , X86_INS_VPTEST = 1387 , X86_INS_VPUNPCKHBW = 1388 , X86_INS_VPUNPCKHDQ = 1389 , X86_INS_VPUNPCKHQDQ = 1390 , X86_INS_VPUNPCKHWD = 1391 , X86_INS_VPUNPCKLBW = 1392 , X86_INS_VPUNPCKLDQ = 1393 , X86_INS_VPUNPCKLQDQ = 1394 , X86_INS_VPUNPCKLWD = 1395 , X86_INS_VPXORD = 1396 , X86_INS_VPXORQ = 1397 , X86_INS_VPXOR = 1398 , X86_INS_VRANGEPD = 1399 , X86_INS_VRANGEPS = 1400 , X86_INS_VRANGESD = 1401 , X86_INS_VRANGESS = 1402 , X86_INS_VRCP14PD = 1403 , X86_INS_VRCP14PS = 1404 , X86_INS_VRCP14SD = 1405 , X86_INS_VRCP14SS = 1406 , X86_INS_VRCP28PD = 1407 , X86_INS_VRCP28PS = 1408 , X86_INS_VRCP28SD = 1409 , X86_INS_VRCP28SS = 1410 , X86_INS_VRCPPS = 1411 , X86_INS_VRCPSS = 1412 , X86_INS_VREDUCEPD = 1413 , X86_INS_VREDUCEPS = 1414 , X86_INS_VREDUCESD = 1415 , X86_INS_VREDUCESS = 1416 , X86_INS_VRNDSCALEPD = 1417 , X86_INS_VRNDSCALEPS = 1418 , X86_INS_VRNDSCALESD = 1419 , X86_INS_VRNDSCALESS = 1420 , X86_INS_VROUNDPD = 1421 , X86_INS_VROUNDPS = 1422 , X86_INS_VROUNDSD = 1423 , X86_INS_VROUNDSS = 1424 , X86_INS_VRSQRT14PD = 1425 , X86_INS_VRSQRT14PS = 1426 , X86_INS_VRSQRT14SD = 1427 , X86_INS_VRSQRT14SS = 1428 , X86_INS_VRSQRT28PD = 1429 , X86_INS_VRSQRT28PS = 1430 , X86_INS_VRSQRT28SD = 1431 , X86_INS_VRSQRT28SS = 1432 , X86_INS_VRSQRTPS = 1433 , X86_INS_VRSQRTSS = 1434 , X86_INS_VSCALEFPD = 1435 , X86_INS_VSCALEFPS = 1436 , X86_INS_VSCALEFSD = 1437 , X86_INS_VSCALEFSS = 1438 , X86_INS_VSCATTERDPD = 1439 , X86_INS_VSCATTERDPS = 1440 , X86_INS_VSCATTERPF0DPD = 1441 , X86_INS_VSCATTERPF0DPS = 1442 , X86_INS_VSCATTERPF0QPD = 1443 , X86_INS_VSCATTERPF0QPS = 1444 , X86_INS_VSCATTERPF1DPD = 1445 , X86_INS_VSCATTERPF1DPS = 1446 , X86_INS_VSCATTERPF1QPD = 1447 , X86_INS_VSCATTERPF1QPS = 1448 , X86_INS_VSCATTERQPD = 1449 , X86_INS_VSCATTERQPS = 1450 , X86_INS_VSHUFF32X4 = 1451 , X86_INS_VSHUFF64X2 = 1452 , X86_INS_VSHUFI32X4 = 1453 , X86_INS_VSHUFI64X2 = 1454 , X86_INS_VSHUFPD = 1455 , X86_INS_VSHUFPS = 1456 , X86_INS_VSQRTPD = 1457 , X86_INS_VSQRTPS = 1458 , X86_INS_VSQRTSD = 1459 , X86_INS_VSQRTSS = 1460 , X86_INS_VSTMXCSR = 1461 , X86_INS_VSUBPD = 1462 , X86_INS_VSUBPS = 1463 , X86_INS_VSUBSD = 1464 , X86_INS_VSUBSS = 1465 , X86_INS_VTESTPD = 1466 , X86_INS_VTESTPS = 1467 , X86_INS_VUCOMISD = 1468 , X86_INS_VUCOMISS = 1469 , X86_INS_VUNPCKHPD = 1470 , X86_INS_VUNPCKHPS = 1471 , X86_INS_VUNPCKLPD = 1472 , X86_INS_VUNPCKLPS = 1473 , X86_INS_VXORPD = 1474 , X86_INS_VXORPS = 1475 , X86_INS_VZEROALL = 1476 , X86_INS_VZEROUPPER = 1477 , X86_INS_WAIT = 1478 , X86_INS_WBINVD = 1479 , X86_INS_WBNOINVD = 1480 , X86_INS_WRFSBASE = 1481 , X86_INS_WRGSBASE = 1482 , X86_INS_WRMSR = 1483 , X86_INS_WRPKRU = 1484 , X86_INS_WRSSD = 1485 , X86_INS_WRSSQ = 1486 , X86_INS_WRUSSD = 1487 , X86_INS_WRUSSQ = 1488 , X86_INS_XABORT = 1489 , X86_INS_XACQUIRE = 1490 , X86_INS_XADD = 1491 , X86_INS_XBEGIN = 1492 , X86_INS_XCHG = 1493 , X86_INS_FXCH = 1494 , X86_INS_XCRYPTCBC = 1495 , X86_INS_XCRYPTCFB = 1496 , X86_INS_XCRYPTCTR = 1497 , X86_INS_XCRYPTECB = 1498 , X86_INS_XCRYPTOFB = 1499 , X86_INS_XEND = 1500 , X86_INS_XGETBV = 1501 , X86_INS_XLATB = 1502 , X86_INS_XOR = 1503 , X86_INS_XORPD = 1504 , X86_INS_XORPS = 1505 , X86_INS_XRELEASE = 1506 , X86_INS_XRSTOR = 1507 , X86_INS_XRSTOR64 = 1508 , X86_INS_XRSTORS = 1509 , X86_INS_XRSTORS64 = 1510 , X86_INS_XSAVE = 1511 , X86_INS_XSAVE64 = 1512 , X86_INS_XSAVEC = 1513 , X86_INS_XSAVEC64 = 1514 , X86_INS_XSAVEOPT = 1515 , X86_INS_XSAVEOPT64 = 1516 , X86_INS_XSAVES = 1517 , X86_INS_XSAVES64 = 1518 , X86_INS_XSETBV = 1519 , X86_INS_XSHA1 = 1520 , X86_INS_XSHA256 = 1521 , X86_INS_XSTORE = 1522 , X86_INS_XTEST = 1523 , X86_INS_ENDING = 1524 , } # [repr (u32)] # [doc = " Group of X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn_group { # [doc = "< = CS_GRP_INVALID"] X86_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] X86_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] X86_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] X86_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] X86_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] X86_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] X86_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] X86_GRP_BRANCH_RELATIVE = 7 , # [doc = "< all virtualization instructions (VT-x + AMD-V)"] X86_GRP_VM = 128 , X86_GRP_3DNOW = 129 , X86_GRP_AES = 130 , X86_GRP_ADX = 131 , X86_GRP_AVX = 132 , X86_GRP_AVX2 = 133 , X86_GRP_AVX512 = 134 , X86_GRP_BMI = 135 , X86_GRP_BMI2 = 136 , X86_GRP_CMOV = 137 , X86_GRP_F16C = 138 , X86_GRP_FMA = 139 , X86_GRP_FMA4 = 140 , X86_GRP_FSGSBASE = 141 , X86_GRP_HLE = 142 , X86_GRP_MMX = 143 , X86_GRP_MODE32 = 144 , X86_GRP_MODE64 = 145 , X86_GRP_RTM = 146 , X86_GRP_SHA = 147 , X86_GRP_SSE1 = 148 , X86_GRP_SSE2 = 149 , X86_GRP_SSE3 = 150 , X86_GRP_SSE41 = 151 , X86_GRP_SSE42 = 152 , X86_GRP_SSE4A = 153 , X86_GRP_SSSE3 = 154 , X86_GRP_PCLMUL = 155 , X86_GRP_XOP = 156 , X86_GRP_CDI = 157 , X86_GRP_ERI = 158 , X86_GRP_TBM = 159 , X86_GRP_16BITMODE = 160 , X86_GRP_NOT64BITMODE = 161 , X86_GRP_SGX = 162 , X86_GRP_DQI = 163 , X86_GRP_BWI = 164 , X86_GRP_PFI = 165 , X86_GRP_VLX = 166 , X86_GRP_SMAP = 167 , X86_GRP_NOVLX = 168 , X86_GRP_FPU = 169 , X86_GRP_ENDING = 170 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] XCORE_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] XCORE_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] XCORE_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] XCORE_OP_MEM = 3 , } # [repr (u32)] # [doc = " XCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_reg { XCORE_REG_INVALID = 0 , XCORE_REG_CP = 1 , XCORE_REG_DP = 2 , XCORE_REG_LR = 3 , XCORE_REG_SP = 4 , XCORE_REG_R0 = 5 , XCORE_REG_R1 = 6 , XCORE_REG_R2 = 7 , XCORE_REG_R3 = 8 , XCORE_REG_R4 = 9 , XCORE_REG_R5 = 10 , XCORE_REG_R6 = 11 , XCORE_REG_R7 = 12 , XCORE_REG_R8 = 13 , XCORE_REG_R9 = 14 , XCORE_REG_R10 = 15 , XCORE_REG_R11 = 16 , # [doc = "< pc"] XCORE_REG_PC = 17 , # [doc = "< save pc"] XCORE_REG_SCP = 18 , XCORE_REG_SSR = 19 , XCORE_REG_ET = 20 , XCORE_REG_ED = 21 , XCORE_REG_SED = 22 , XCORE_REG_KEP = 23 , XCORE_REG_KSP = 24 , XCORE_REG_ID = 25 , XCORE_REG_ENDING = 26 , } # [doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct xcore_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , # [doc = "< +1: forward, -1: backward"] pub direct : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of xcore_op_mem"] [:: std :: mem :: size_of :: < xcore_op_mem > () - 12usize] ; ["Alignment of xcore_op_mem"] [:: std :: mem :: align_of :: < xcore_op_mem > () - 4usize] ; ["Offset of field: xcore_op_mem::base"] [:: std :: mem :: offset_of ! (xcore_op_mem , base) - 0usize] ; ["Offset of field: xcore_op_mem::index"] [:: std :: mem :: offset_of ! (xcore_op_mem , index) - 1usize] ; ["Offset of field: xcore_op_mem::disp"] [:: std :: mem :: offset_of ! (xcore_op_mem , disp) - 4usize] ; ["Offset of field: xcore_op_mem::direct"] [:: std :: mem :: offset_of ! (xcore_op_mem , direct) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore_op { # [doc = "< operand type"] pub type_ : xcore_op_type , pub __bindgen_anon_1 : cs_xcore_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_xcore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : xcore_reg , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : xcore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_xcore_op__bindgen_ty_1 > () - 12usize] ; ["Alignment of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_xcore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op"] [:: std :: mem :: size_of :: < cs_xcore_op > () - 16usize] ; ["Alignment of cs_xcore_op"] [:: std :: mem :: align_of :: < cs_xcore_op > () - 4usize] ; ["Offset of field: cs_xcore_op::type_"] [:: std :: mem :: offset_of ! (cs_xcore_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_xcore_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore"] [:: std :: mem :: size_of :: < cs_xcore > () - 132usize] ; ["Alignment of cs_xcore"] [:: std :: mem :: align_of :: < cs_xcore > () - 4usize] ; ["Offset of field: cs_xcore::op_count"] [:: std :: mem :: offset_of ! (cs_xcore , op_count) - 0usize] ; ["Offset of field: cs_xcore::operands"] [:: std :: mem :: offset_of ! (cs_xcore , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " XCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn { XCORE_INS_INVALID = 0 , XCORE_INS_ADD = 1 , XCORE_INS_ANDNOT = 2 , XCORE_INS_AND = 3 , XCORE_INS_ASHR = 4 , XCORE_INS_BAU = 5 , XCORE_INS_BITREV = 6 , XCORE_INS_BLA = 7 , XCORE_INS_BLAT = 8 , XCORE_INS_BL = 9 , XCORE_INS_BF = 10 , XCORE_INS_BT = 11 , XCORE_INS_BU = 12 , XCORE_INS_BRU = 13 , XCORE_INS_BYTEREV = 14 , XCORE_INS_CHKCT = 15 , XCORE_INS_CLRE = 16 , XCORE_INS_CLRPT = 17 , XCORE_INS_CLRSR = 18 , XCORE_INS_CLZ = 19 , XCORE_INS_CRC8 = 20 , XCORE_INS_CRC32 = 21 , XCORE_INS_DCALL = 22 , XCORE_INS_DENTSP = 23 , XCORE_INS_DGETREG = 24 , XCORE_INS_DIVS = 25 , XCORE_INS_DIVU = 26 , XCORE_INS_DRESTSP = 27 , XCORE_INS_DRET = 28 , XCORE_INS_ECALLF = 29 , XCORE_INS_ECALLT = 30 , XCORE_INS_EDU = 31 , XCORE_INS_EEF = 32 , XCORE_INS_EET = 33 , XCORE_INS_EEU = 34 , XCORE_INS_ENDIN = 35 , XCORE_INS_ENTSP = 36 , XCORE_INS_EQ = 37 , XCORE_INS_EXTDP = 38 , XCORE_INS_EXTSP = 39 , XCORE_INS_FREER = 40 , XCORE_INS_FREET = 41 , XCORE_INS_GETD = 42 , XCORE_INS_GET = 43 , XCORE_INS_GETN = 44 , XCORE_INS_GETR = 45 , XCORE_INS_GETSR = 46 , XCORE_INS_GETST = 47 , XCORE_INS_GETTS = 48 , XCORE_INS_INCT = 49 , XCORE_INS_INIT = 50 , XCORE_INS_INPW = 51 , XCORE_INS_INSHR = 52 , XCORE_INS_INT = 53 , XCORE_INS_IN = 54 , XCORE_INS_KCALL = 55 , XCORE_INS_KENTSP = 56 , XCORE_INS_KRESTSP = 57 , XCORE_INS_KRET = 58 , XCORE_INS_LADD = 59 , XCORE_INS_LD16S = 60 , XCORE_INS_LD8U = 61 , XCORE_INS_LDA16 = 62 , XCORE_INS_LDAP = 63 , XCORE_INS_LDAW = 64 , XCORE_INS_LDC = 65 , XCORE_INS_LDW = 66 , XCORE_INS_LDIVU = 67 , XCORE_INS_LMUL = 68 , XCORE_INS_LSS = 69 , XCORE_INS_LSUB = 70 , XCORE_INS_LSU = 71 , XCORE_INS_MACCS = 72 , XCORE_INS_MACCU = 73 , XCORE_INS_MJOIN = 74 , XCORE_INS_MKMSK = 75 , XCORE_INS_MSYNC = 76 , XCORE_INS_MUL = 77 , XCORE_INS_NEG = 78 , XCORE_INS_NOT = 79 , XCORE_INS_OR = 80 , XCORE_INS_OUTCT = 81 , XCORE_INS_OUTPW = 82 , XCORE_INS_OUTSHR = 83 , XCORE_INS_OUTT = 84 , XCORE_INS_OUT = 85 , XCORE_INS_PEEK = 86 , XCORE_INS_REMS = 87 , XCORE_INS_REMU = 88 , XCORE_INS_RETSP = 89 , XCORE_INS_SETCLK = 90 , XCORE_INS_SET = 91 , XCORE_INS_SETC = 92 , XCORE_INS_SETD = 93 , XCORE_INS_SETEV = 94 , XCORE_INS_SETN = 95 , XCORE_INS_SETPSC = 96 , XCORE_INS_SETPT = 97 , XCORE_INS_SETRDY = 98 , XCORE_INS_SETSR = 99 , XCORE_INS_SETTW = 100 , XCORE_INS_SETV = 101 , XCORE_INS_SEXT = 102 , XCORE_INS_SHL = 103 , XCORE_INS_SHR = 104 , XCORE_INS_SSYNC = 105 , XCORE_INS_ST16 = 106 , XCORE_INS_ST8 = 107 , XCORE_INS_STW = 108 , XCORE_INS_SUB = 109 , XCORE_INS_SYNCR = 110 , XCORE_INS_TESTCT = 111 , XCORE_INS_TESTLCL = 112 , XCORE_INS_TESTWCT = 113 , XCORE_INS_TSETMR = 114 , XCORE_INS_START = 115 , XCORE_INS_WAITEF = 116 , XCORE_INS_WAITET = 117 , XCORE_INS_WAITEU = 118 , XCORE_INS_XOR = 119 , XCORE_INS_ZEXT = 120 , XCORE_INS_ENDING = 121 , } # [repr (u32)] # [doc = " Group of XCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn_group { # [doc = "< = CS_GRP_INVALID"] XCORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] XCORE_GRP_JUMP = 1 , XCORE_GRP_ENDING = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] TMS320C64X_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] TMS320C64X_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] TMS320C64X_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] TMS320C64X_OP_MEM = 3 , # [doc = "< Register pair for double word ops"] TMS320C64X_OP_REGPAIR = 64 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0 , TMS320C64X_MEM_DISP_CONSTANT = 1 , TMS320C64X_MEM_DISP_REGISTER = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0 , TMS320C64X_MEM_DIR_FW = 1 , TMS320C64X_MEM_DIR_BW = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0 , TMS320C64X_MEM_MOD_NO = 1 , TMS320C64X_MEM_MOD_PRE = 2 , TMS320C64X_MEM_MOD_POST = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tms320c64x_op_mem { # [doc = "< base register"] pub base : :: std :: os :: raw :: c_uint , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_uint , # [doc = "< unit of base and offset register"] pub unit : :: std :: os :: raw :: c_uint , # [doc = "< offset scaled"] pub scaled : :: std :: os :: raw :: c_uint , # [doc = "< displacement type"] pub disptype : :: std :: os :: raw :: c_uint , # [doc = "< direction"] pub direction : :: std :: os :: raw :: c_uint , # [doc = "< modification"] pub modify : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tms320c64x_op_mem"] [:: std :: mem :: size_of :: < tms320c64x_op_mem > () - 28usize] ; ["Alignment of tms320c64x_op_mem"] [:: std :: mem :: align_of :: < tms320c64x_op_mem > () - 4usize] ; ["Offset of field: tms320c64x_op_mem::base"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , base) - 0usize] ; ["Offset of field: tms320c64x_op_mem::disp"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disp) - 4usize] ; ["Offset of field: tms320c64x_op_mem::unit"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , unit) - 8usize] ; ["Offset of field: tms320c64x_op_mem::scaled"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , scaled) - 12usize] ; ["Offset of field: tms320c64x_op_mem::disptype"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disptype) - 16usize] ; ["Offset of field: tms320c64x_op_mem::direction"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , direction) - 20usize] ; ["Offset of field: tms320c64x_op_mem::modify"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , modify) - 24usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x_op { # [doc = "< operand type"] pub type_ : tms320c64x_op_type , pub __bindgen_anon_1 : cs_tms320c64x_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tms320c64x_op__bindgen_ty_1 { # [doc = "< register value for REG operand or first register for REGPAIR operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tms320c64x_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 28usize] ; ["Alignment of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op"] [:: std :: mem :: size_of :: < cs_tms320c64x_op > () - 32usize] ; ["Alignment of cs_tms320c64x_op"] [:: std :: mem :: align_of :: < cs_tms320c64x_op > () - 4usize] ; ["Offset of field: cs_tms320c64x_op::type_"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x { pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tms320c64x_op ; 8usize] , pub condition : cs_tms320c64x__bindgen_ty_1 , pub funit : cs_tms320c64x__bindgen_ty_2 , pub parallel : :: std :: os :: raw :: c_uint , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub zero : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::zero"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , zero) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_2 { pub unit : :: std :: os :: raw :: c_uint , pub side : :: std :: os :: raw :: c_uint , pub crosspath : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_2 > () - 12usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_2 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::unit"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , unit) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::side"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , side) - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::crosspath"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , crosspath) - 8usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x"] [:: std :: mem :: size_of :: < cs_tms320c64x > () - 284usize] ; ["Alignment of cs_tms320c64x"] [:: std :: mem :: align_of :: < cs_tms320c64x > () - 4usize] ; ["Offset of field: cs_tms320c64x::op_count"] [:: std :: mem :: offset_of ! (cs_tms320c64x , op_count) - 0usize] ; ["Offset of field: cs_tms320c64x::operands"] [:: std :: mem :: offset_of ! (cs_tms320c64x , operands) - 4usize] ; ["Offset of field: cs_tms320c64x::condition"] [:: std :: mem :: offset_of ! (cs_tms320c64x , condition) - 260usize] ; ["Offset of field: cs_tms320c64x::funit"] [:: std :: mem :: offset_of ! (cs_tms320c64x , funit) - 268usize] ; ["Offset of field: cs_tms320c64x::parallel"] [:: std :: mem :: offset_of ! (cs_tms320c64x , parallel) - 280usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel) } } impl tms320c64x_reg { pub const TMS320C64X_REG_EFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ECR ; } impl tms320c64x_reg { pub const TMS320C64X_REG_IFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ISR ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0 , TMS320C64X_REG_AMR = 1 , TMS320C64X_REG_CSR = 2 , TMS320C64X_REG_DIER = 3 , TMS320C64X_REG_DNUM = 4 , TMS320C64X_REG_ECR = 5 , TMS320C64X_REG_GFPGFR = 6 , TMS320C64X_REG_GPLYA = 7 , TMS320C64X_REG_GPLYB = 8 , TMS320C64X_REG_ICR = 9 , TMS320C64X_REG_IER = 10 , TMS320C64X_REG_IERR = 11 , TMS320C64X_REG_ILC = 12 , TMS320C64X_REG_IRP = 13 , TMS320C64X_REG_ISR = 14 , TMS320C64X_REG_ISTP = 15 , TMS320C64X_REG_ITSR = 16 , TMS320C64X_REG_NRP = 17 , TMS320C64X_REG_NTSR = 18 , TMS320C64X_REG_REP = 19 , TMS320C64X_REG_RILC = 20 , TMS320C64X_REG_SSR = 21 , TMS320C64X_REG_TSCH = 22 , TMS320C64X_REG_TSCL = 23 , TMS320C64X_REG_TSR = 24 , TMS320C64X_REG_A0 = 25 , TMS320C64X_REG_A1 = 26 , TMS320C64X_REG_A2 = 27 , TMS320C64X_REG_A3 = 28 , TMS320C64X_REG_A4 = 29 , TMS320C64X_REG_A5 = 30 , TMS320C64X_REG_A6 = 31 , TMS320C64X_REG_A7 = 32 , TMS320C64X_REG_A8 = 33 , TMS320C64X_REG_A9 = 34 , TMS320C64X_REG_A10 = 35 , TMS320C64X_REG_A11 = 36 , TMS320C64X_REG_A12 = 37 , TMS320C64X_REG_A13 = 38 , TMS320C64X_REG_A14 = 39 , TMS320C64X_REG_A15 = 40 , TMS320C64X_REG_A16 = 41 , TMS320C64X_REG_A17 = 42 , TMS320C64X_REG_A18 = 43 , TMS320C64X_REG_A19 = 44 , TMS320C64X_REG_A20 = 45 , TMS320C64X_REG_A21 = 46 , TMS320C64X_REG_A22 = 47 , TMS320C64X_REG_A23 = 48 , TMS320C64X_REG_A24 = 49 , TMS320C64X_REG_A25 = 50 , TMS320C64X_REG_A26 = 51 , TMS320C64X_REG_A27 = 52 , TMS320C64X_REG_A28 = 53 , TMS320C64X_REG_A29 = 54 , TMS320C64X_REG_A30 = 55 , TMS320C64X_REG_A31 = 56 , TMS320C64X_REG_B0 = 57 , TMS320C64X_REG_B1 = 58 , TMS320C64X_REG_B2 = 59 , TMS320C64X_REG_B3 = 60 , TMS320C64X_REG_B4 = 61 , TMS320C64X_REG_B5 = 62 , TMS320C64X_REG_B6 = 63 , TMS320C64X_REG_B7 = 64 , TMS320C64X_REG_B8 = 65 , TMS320C64X_REG_B9 = 66 , TMS320C64X_REG_B10 = 67 , TMS320C64X_REG_B11 = 68 , TMS320C64X_REG_B12 = 69 , TMS320C64X_REG_B13 = 70 , TMS320C64X_REG_B14 = 71 , TMS320C64X_REG_B15 = 72 , TMS320C64X_REG_B16 = 73 , TMS320C64X_REG_B17 = 74 , TMS320C64X_REG_B18 = 75 , TMS320C64X_REG_B19 = 76 , TMS320C64X_REG_B20 = 77 , TMS320C64X_REG_B21 = 78 , TMS320C64X_REG_B22 = 79 , TMS320C64X_REG_B23 = 80 , TMS320C64X_REG_B24 = 81 , TMS320C64X_REG_B25 = 82 , TMS320C64X_REG_B26 = 83 , TMS320C64X_REG_B27 = 84 , TMS320C64X_REG_B28 = 85 , TMS320C64X_REG_B29 = 86 , TMS320C64X_REG_B30 = 87 , TMS320C64X_REG_B31 = 88 , TMS320C64X_REG_PCE1 = 89 , TMS320C64X_REG_ENDING = 90 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0 , TMS320C64X_INS_ABS = 1 , TMS320C64X_INS_ABS2 = 2 , TMS320C64X_INS_ADD = 3 , TMS320C64X_INS_ADD2 = 4 , TMS320C64X_INS_ADD4 = 5 , TMS320C64X_INS_ADDAB = 6 , TMS320C64X_INS_ADDAD = 7 , TMS320C64X_INS_ADDAH = 8 , TMS320C64X_INS_ADDAW = 9 , TMS320C64X_INS_ADDK = 10 , TMS320C64X_INS_ADDKPC = 11 , TMS320C64X_INS_ADDU = 12 , TMS320C64X_INS_AND = 13 , TMS320C64X_INS_ANDN = 14 , TMS320C64X_INS_AVG2 = 15 , TMS320C64X_INS_AVGU4 = 16 , TMS320C64X_INS_B = 17 , TMS320C64X_INS_BDEC = 18 , TMS320C64X_INS_BITC4 = 19 , TMS320C64X_INS_BNOP = 20 , TMS320C64X_INS_BPOS = 21 , TMS320C64X_INS_CLR = 22 , TMS320C64X_INS_CMPEQ = 23 , TMS320C64X_INS_CMPEQ2 = 24 , TMS320C64X_INS_CMPEQ4 = 25 , TMS320C64X_INS_CMPGT = 26 , TMS320C64X_INS_CMPGT2 = 27 , TMS320C64X_INS_CMPGTU4 = 28 , TMS320C64X_INS_CMPLT = 29 , TMS320C64X_INS_CMPLTU = 30 , TMS320C64X_INS_DEAL = 31 , TMS320C64X_INS_DOTP2 = 32 , TMS320C64X_INS_DOTPN2 = 33 , TMS320C64X_INS_DOTPNRSU2 = 34 , TMS320C64X_INS_DOTPRSU2 = 35 , TMS320C64X_INS_DOTPSU4 = 36 , TMS320C64X_INS_DOTPU4 = 37 , TMS320C64X_INS_EXT = 38 , TMS320C64X_INS_EXTU = 39 , TMS320C64X_INS_GMPGTU = 40 , TMS320C64X_INS_GMPY4 = 41 , TMS320C64X_INS_LDB = 42 , TMS320C64X_INS_LDBU = 43 , TMS320C64X_INS_LDDW = 44 , TMS320C64X_INS_LDH = 45 , TMS320C64X_INS_LDHU = 46 , TMS320C64X_INS_LDNDW = 47 , TMS320C64X_INS_LDNW = 48 , TMS320C64X_INS_LDW = 49 , TMS320C64X_INS_LMBD = 50 , TMS320C64X_INS_MAX2 = 51 , TMS320C64X_INS_MAXU4 = 52 , TMS320C64X_INS_MIN2 = 53 , TMS320C64X_INS_MINU4 = 54 , TMS320C64X_INS_MPY = 55 , TMS320C64X_INS_MPY2 = 56 , TMS320C64X_INS_MPYH = 57 , TMS320C64X_INS_MPYHI = 58 , TMS320C64X_INS_MPYHIR = 59 , TMS320C64X_INS_MPYHL = 60 , TMS320C64X_INS_MPYHLU = 61 , TMS320C64X_INS_MPYHSLU = 62 , TMS320C64X_INS_MPYHSU = 63 , TMS320C64X_INS_MPYHU = 64 , TMS320C64X_INS_MPYHULS = 65 , TMS320C64X_INS_MPYHUS = 66 , TMS320C64X_INS_MPYLH = 67 , TMS320C64X_INS_MPYLHU = 68 , TMS320C64X_INS_MPYLI = 69 , TMS320C64X_INS_MPYLIR = 70 , TMS320C64X_INS_MPYLSHU = 71 , TMS320C64X_INS_MPYLUHS = 72 , TMS320C64X_INS_MPYSU = 73 , TMS320C64X_INS_MPYSU4 = 74 , TMS320C64X_INS_MPYU = 75 , TMS320C64X_INS_MPYU4 = 76 , TMS320C64X_INS_MPYUS = 77 , TMS320C64X_INS_MVC = 78 , TMS320C64X_INS_MVD = 79 , TMS320C64X_INS_MVK = 80 , TMS320C64X_INS_MVKL = 81 , TMS320C64X_INS_MVKLH = 82 , TMS320C64X_INS_NOP = 83 , TMS320C64X_INS_NORM = 84 , TMS320C64X_INS_OR = 85 , TMS320C64X_INS_PACK2 = 86 , TMS320C64X_INS_PACKH2 = 87 , TMS320C64X_INS_PACKH4 = 88 , TMS320C64X_INS_PACKHL2 = 89 , TMS320C64X_INS_PACKL4 = 90 , TMS320C64X_INS_PACKLH2 = 91 , TMS320C64X_INS_ROTL = 92 , TMS320C64X_INS_SADD = 93 , TMS320C64X_INS_SADD2 = 94 , TMS320C64X_INS_SADDU4 = 95 , TMS320C64X_INS_SADDUS2 = 96 , TMS320C64X_INS_SAT = 97 , TMS320C64X_INS_SET = 98 , TMS320C64X_INS_SHFL = 99 , TMS320C64X_INS_SHL = 100 , TMS320C64X_INS_SHLMB = 101 , TMS320C64X_INS_SHR = 102 , TMS320C64X_INS_SHR2 = 103 , TMS320C64X_INS_SHRMB = 104 , TMS320C64X_INS_SHRU = 105 , TMS320C64X_INS_SHRU2 = 106 , TMS320C64X_INS_SMPY = 107 , TMS320C64X_INS_SMPY2 = 108 , TMS320C64X_INS_SMPYH = 109 , TMS320C64X_INS_SMPYHL = 110 , TMS320C64X_INS_SMPYLH = 111 , TMS320C64X_INS_SPACK2 = 112 , TMS320C64X_INS_SPACKU4 = 113 , TMS320C64X_INS_SSHL = 114 , TMS320C64X_INS_SSHVL = 115 , TMS320C64X_INS_SSHVR = 116 , TMS320C64X_INS_SSUB = 117 , TMS320C64X_INS_STB = 118 , TMS320C64X_INS_STDW = 119 , TMS320C64X_INS_STH = 120 , TMS320C64X_INS_STNDW = 121 , TMS320C64X_INS_STNW = 122 , TMS320C64X_INS_STW = 123 , TMS320C64X_INS_SUB = 124 , TMS320C64X_INS_SUB2 = 125 , TMS320C64X_INS_SUB4 = 126 , TMS320C64X_INS_SUBAB = 127 , TMS320C64X_INS_SUBABS4 = 128 , TMS320C64X_INS_SUBAH = 129 , TMS320C64X_INS_SUBAW = 130 , TMS320C64X_INS_SUBC = 131 , TMS320C64X_INS_SUBU = 132 , TMS320C64X_INS_SWAP4 = 133 , TMS320C64X_INS_UNPKHU4 = 134 , TMS320C64X_INS_UNPKLU4 = 135 , TMS320C64X_INS_XOR = 136 , TMS320C64X_INS_XPND2 = 137 , TMS320C64X_INS_XPND4 = 138 , TMS320C64X_INS_IDLE = 139 , TMS320C64X_INS_MV = 140 , TMS320C64X_INS_NEG = 141 , TMS320C64X_INS_NOT = 142 , TMS320C64X_INS_SWAP2 = 143 , TMS320C64X_INS_ZERO = 144 , TMS320C64X_INS_ENDING = 145 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn_group { # [doc = "< = CS_GRP_INVALID"] TMS320C64X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] TMS320C64X_GRP_JUMP = 1 , TMS320C64X_GRP_FUNIT_D = 128 , TMS320C64X_GRP_FUNIT_L = 129 , TMS320C64X_GRP_FUNIT_M = 130 , TMS320C64X_GRP_FUNIT_S = 131 , TMS320C64X_GRP_FUNIT_NO = 132 , TMS320C64X_GRP_ENDING = 133 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0 , TMS320C64X_FUNIT_D = 1 , TMS320C64X_FUNIT_L = 2 , TMS320C64X_FUNIT_M = 3 , TMS320C64X_FUNIT_S = 4 , TMS320C64X_FUNIT_NO = 5 , } # [repr (u32)] # [doc = " M680X registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_reg { M680X_REG_INVALID = 0 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_A = 1 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_B = 2 , # [doc = "< HD6309"] M680X_REG_E = 3 , # [doc = "< HD6309"] M680X_REG_F = 4 , # [doc = "< HD6309"] M680X_REG_0 = 5 , # [doc = "< M6801/3/9, HD6301/9"] M680X_REG_D = 6 , # [doc = "< HD6309"] M680X_REG_W = 7 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_CC = 8 , # [doc = "< M6809/M6309"] M680X_REG_DP = 9 , # [doc = "< M6309"] M680X_REG_MD = 10 , # [doc = "< M6808"] M680X_REG_HX = 11 , # [doc = "< M6808"] M680X_REG_H = 12 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_X = 13 , # [doc = "< M6809/M6309"] M680X_REG_Y = 14 , # [doc = "< M6809/M6309"] M680X_REG_S = 15 , # [doc = "< M6809/M6309"] M680X_REG_U = 16 , # [doc = "< M6309"] M680X_REG_V = 17 , # [doc = "< M6309"] M680X_REG_Q = 18 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_PC = 19 , # [doc = "< CPU12"] M680X_REG_TMP2 = 20 , # [doc = "< CPU12"] M680X_REG_TMP3 = 21 , # [doc = "< <-- mark the end of the list of registers"] M680X_REG_ENDING = 22 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M680X_OP_INVALID = 0 , # [doc = "< = Register operand."] M680X_OP_REGISTER = 1 , # [doc = "< = Immediate operand."] M680X_OP_IMMEDIATE = 2 , # [doc = "< = Indexed addressing operand."] M680X_OP_INDEXED = 3 , # [doc = "< = Extended addressing operand."] M680X_OP_EXTENDED = 4 , # [doc = "< = Direct addressing operand."] M680X_OP_DIRECT = 5 , # [doc = "< = Relative addressing operand."] M680X_OP_RELATIVE = 6 , # [doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."] M680X_OP_CONSTANT = 7 , } # [doc = " Instruction's operand referring to indexed addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_idx { # [doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"] pub base_reg : m680x_reg , # [doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"] pub offset_reg : m680x_reg , # [doc = "< 5-,8- or 16-bit offset. See also offset_bits."] pub offset : i16 , # [doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"] pub offset_addr : u16 , # [doc = "< offset width in bits for indexed addressing"] pub offset_bits : u8 , # [doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"] pub inc_dec : i8 , # [doc = "< 8-bit flags (see above)"] pub flags : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_idx"] [:: std :: mem :: size_of :: < m680x_op_idx > () - 16usize] ; ["Alignment of m680x_op_idx"] [:: std :: mem :: align_of :: < m680x_op_idx > () - 4usize] ; ["Offset of field: m680x_op_idx::base_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , base_reg) - 0usize] ; ["Offset of field: m680x_op_idx::offset_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_reg) - 4usize] ; ["Offset of field: m680x_op_idx::offset"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset) - 8usize] ; ["Offset of field: m680x_op_idx::offset_addr"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_addr) - 10usize] ; ["Offset of field: m680x_op_idx::offset_bits"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_bits) - 12usize] ; ["Offset of field: m680x_op_idx::inc_dec"] [:: std :: mem :: offset_of ! (m680x_op_idx , inc_dec) - 13usize] ; ["Offset of field: m680x_op_idx::flags"] [:: std :: mem :: offset_of ! (m680x_op_idx , flags) - 14usize] ; } ; # [doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_rel { # [doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."] pub address : u16 , # [doc = "< the offset/displacement value"] pub offset : i16 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_rel"] [:: std :: mem :: size_of :: < m680x_op_rel > () - 4usize] ; ["Alignment of m680x_op_rel"] [:: std :: mem :: align_of :: < m680x_op_rel > () - 2usize] ; ["Offset of field: m680x_op_rel::address"] [:: std :: mem :: offset_of ! (m680x_op_rel , address) - 0usize] ; ["Offset of field: m680x_op_rel::offset"] [:: std :: mem :: offset_of ! (m680x_op_rel , offset) - 2usize] ; } ; # [doc = " Instruction's operand referring to extended addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_ext { # [doc = "< The absolute address"] pub address : u16 , # [doc = "< true if extended indirect addressing"] pub indirect : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_ext"] [:: std :: mem :: size_of :: < m680x_op_ext > () - 4usize] ; ["Alignment of m680x_op_ext"] [:: std :: mem :: align_of :: < m680x_op_ext > () - 2usize] ; ["Offset of field: m680x_op_ext::address"] [:: std :: mem :: offset_of ! (m680x_op_ext , address) - 0usize] ; ["Offset of field: m680x_op_ext::indirect"] [:: std :: mem :: offset_of ! (m680x_op_ext , indirect) - 2usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x_op { pub type_ : m680x_op_type , pub __bindgen_anon_1 : cs_m680x_op__bindgen_ty_1 , # [doc = "< size of this operand (in bytes)"] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m680x_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< register value for REG operand"] pub reg : m680x_reg , # [doc = "< Indexed addressing operand"] pub idx : m680x_op_idx , # [doc = "< Relative address. operand (Bcc/LBcc)"] pub rel : m680x_op_rel , # [doc = "< Extended address"] pub ext : m680x_op_ext , # [doc = "<</ Direct address (lower 8-bit)"] pub direct_addr : u8 , # [doc = "< constant value (bit index, page nr.)"] pub const_val : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m680x_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m680x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::idx"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , idx) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::rel"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , rel) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , ext) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::direct_addr"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , direct_addr) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::const_val"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , const_val) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op"] [:: std :: mem :: size_of :: < cs_m680x_op > () - 24usize] ; ["Alignment of cs_m680x_op"] [:: std :: mem :: align_of :: < cs_m680x_op > () - 4usize] ; ["Offset of field: cs_m680x_op::type_"] [:: std :: mem :: offset_of ! (cs_m680x_op , type_) - 0usize] ; ["Offset of field: cs_m680x_op::size"] [:: std :: mem :: offset_of ! (cs_m680x_op , size) - 20usize] ; ["Offset of field: cs_m680x_op::access"] [:: std :: mem :: offset_of ! (cs_m680x_op , access) - 21usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access) } } # [repr (u32)] # [doc = " Group of M680X instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_group_type { M680X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M680X_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] M680X_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] M680X_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] M680X_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] M680X_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEDGE; not used"] M680X_GRP_PRIV = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M680X_GRP_BRAREL = 7 , M680X_GRP_ENDING = 8 , } # [doc = " The M680X instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x { # [doc = "< See: M680X instruction flags"] pub flags : u8 , # [doc = "< number of operands for the instruction or 0"] pub op_count : u8 , # [doc = "< operands for this insn."] pub operands : [cs_m680x_op ; 9usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x"] [:: std :: mem :: size_of :: < cs_m680x > () - 220usize] ; ["Alignment of cs_m680x"] [:: std :: mem :: align_of :: < cs_m680x > () - 4usize] ; ["Offset of field: cs_m680x::flags"] [:: std :: mem :: offset_of ! (cs_m680x , flags) - 0usize] ; ["Offset of field: cs_m680x::op_count"] [:: std :: mem :: offset_of ! (cs_m680x , op_count) - 1usize] ; ["Offset of field: cs_m680x::operands"] [:: std :: mem :: offset_of ! (cs_m680x , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " M680X instruction IDs"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_insn { M680X_INS_INVLD = 0 , # [doc = "< M6800/1/2/3"] M680X_INS_ABA = 1 , M680X_INS_ABX = 2 , M680X_INS_ABY = 3 , M680X_INS_ADC = 4 , M680X_INS_ADCA = 5 , M680X_INS_ADCB = 6 , M680X_INS_ADCD = 7 , M680X_INS_ADCR = 8 , M680X_INS_ADD = 9 , M680X_INS_ADDA = 10 , M680X_INS_ADDB = 11 , M680X_INS_ADDD = 12 , M680X_INS_ADDE = 13 , M680X_INS_ADDF = 14 , M680X_INS_ADDR = 15 , M680X_INS_ADDW = 16 , M680X_INS_AIM = 17 , M680X_INS_AIS = 18 , M680X_INS_AIX = 19 , M680X_INS_AND = 20 , M680X_INS_ANDA = 21 , M680X_INS_ANDB = 22 , M680X_INS_ANDCC = 23 , M680X_INS_ANDD = 24 , M680X_INS_ANDR = 25 , M680X_INS_ASL = 26 , M680X_INS_ASLA = 27 , M680X_INS_ASLB = 28 , # [doc = "< or LSLD"] M680X_INS_ASLD = 29 , M680X_INS_ASR = 30 , M680X_INS_ASRA = 31 , M680X_INS_ASRB = 32 , M680X_INS_ASRD = 33 , M680X_INS_ASRX = 34 , M680X_INS_BAND = 35 , # [doc = "< or BHS"] M680X_INS_BCC = 36 , M680X_INS_BCLR = 37 , # [doc = "< or BLO"] M680X_INS_BCS = 38 , M680X_INS_BEOR = 39 , M680X_INS_BEQ = 40 , M680X_INS_BGE = 41 , M680X_INS_BGND = 42 , M680X_INS_BGT = 43 , M680X_INS_BHCC = 44 , M680X_INS_BHCS = 45 , M680X_INS_BHI = 46 , M680X_INS_BIAND = 47 , M680X_INS_BIEOR = 48 , M680X_INS_BIH = 49 , M680X_INS_BIL = 50 , M680X_INS_BIOR = 51 , M680X_INS_BIT = 52 , M680X_INS_BITA = 53 , M680X_INS_BITB = 54 , M680X_INS_BITD = 55 , M680X_INS_BITMD = 56 , M680X_INS_BLE = 57 , M680X_INS_BLS = 58 , M680X_INS_BLT = 59 , M680X_INS_BMC = 60 , M680X_INS_BMI = 61 , M680X_INS_BMS = 62 , M680X_INS_BNE = 63 , M680X_INS_BOR = 64 , M680X_INS_BPL = 65 , M680X_INS_BRCLR = 66 , M680X_INS_BRSET = 67 , M680X_INS_BRA = 68 , M680X_INS_BRN = 69 , M680X_INS_BSET = 70 , M680X_INS_BSR = 71 , M680X_INS_BVC = 72 , M680X_INS_BVS = 73 , M680X_INS_CALL = 74 , # [doc = "< M6800/1/2/3"] M680X_INS_CBA = 75 , M680X_INS_CBEQ = 76 , M680X_INS_CBEQA = 77 , M680X_INS_CBEQX = 78 , # [doc = "< M6800/1/2/3"] M680X_INS_CLC = 79 , # [doc = "< M6800/1/2/3"] M680X_INS_CLI = 80 , M680X_INS_CLR = 81 , M680X_INS_CLRA = 82 , M680X_INS_CLRB = 83 , M680X_INS_CLRD = 84 , M680X_INS_CLRE = 85 , M680X_INS_CLRF = 86 , M680X_INS_CLRH = 87 , M680X_INS_CLRW = 88 , M680X_INS_CLRX = 89 , # [doc = "< M6800/1/2/3"] M680X_INS_CLV = 90 , M680X_INS_CMP = 91 , M680X_INS_CMPA = 92 , M680X_INS_CMPB = 93 , M680X_INS_CMPD = 94 , M680X_INS_CMPE = 95 , M680X_INS_CMPF = 96 , M680X_INS_CMPR = 97 , M680X_INS_CMPS = 98 , M680X_INS_CMPU = 99 , M680X_INS_CMPW = 100 , M680X_INS_CMPX = 101 , M680X_INS_CMPY = 102 , M680X_INS_COM = 103 , M680X_INS_COMA = 104 , M680X_INS_COMB = 105 , M680X_INS_COMD = 106 , M680X_INS_COME = 107 , M680X_INS_COMF = 108 , M680X_INS_COMW = 109 , M680X_INS_COMX = 110 , M680X_INS_CPD = 111 , M680X_INS_CPHX = 112 , M680X_INS_CPS = 113 , # [doc = "< M6800/1/2/3"] M680X_INS_CPX = 114 , M680X_INS_CPY = 115 , M680X_INS_CWAI = 116 , M680X_INS_DAA = 117 , M680X_INS_DBEQ = 118 , M680X_INS_DBNE = 119 , M680X_INS_DBNZ = 120 , M680X_INS_DBNZA = 121 , M680X_INS_DBNZX = 122 , M680X_INS_DEC = 123 , M680X_INS_DECA = 124 , M680X_INS_DECB = 125 , M680X_INS_DECD = 126 , M680X_INS_DECE = 127 , M680X_INS_DECF = 128 , M680X_INS_DECW = 129 , M680X_INS_DECX = 130 , # [doc = "< M6800/1/2/3"] M680X_INS_DES = 131 , # [doc = "< M6800/1/2/3"] M680X_INS_DEX = 132 , M680X_INS_DEY = 133 , M680X_INS_DIV = 134 , M680X_INS_DIVD = 135 , M680X_INS_DIVQ = 136 , M680X_INS_EDIV = 137 , M680X_INS_EDIVS = 138 , M680X_INS_EIM = 139 , M680X_INS_EMACS = 140 , M680X_INS_EMAXD = 141 , M680X_INS_EMAXM = 142 , M680X_INS_EMIND = 143 , M680X_INS_EMINM = 144 , M680X_INS_EMUL = 145 , M680X_INS_EMULS = 146 , M680X_INS_EOR = 147 , M680X_INS_EORA = 148 , M680X_INS_EORB = 149 , M680X_INS_EORD = 150 , M680X_INS_EORR = 151 , M680X_INS_ETBL = 152 , M680X_INS_EXG = 153 , M680X_INS_FDIV = 154 , M680X_INS_IBEQ = 155 , M680X_INS_IBNE = 156 , M680X_INS_IDIV = 157 , M680X_INS_IDIVS = 158 , M680X_INS_ILLGL = 159 , M680X_INS_INC = 160 , M680X_INS_INCA = 161 , M680X_INS_INCB = 162 , M680X_INS_INCD = 163 , M680X_INS_INCE = 164 , M680X_INS_INCF = 165 , M680X_INS_INCW = 166 , M680X_INS_INCX = 167 , # [doc = "< M6800/1/2/3"] M680X_INS_INS = 168 , # [doc = "< M6800/1/2/3"] M680X_INS_INX = 169 , M680X_INS_INY = 170 , M680X_INS_JMP = 171 , M680X_INS_JSR = 172 , # [doc = "< or LBHS"] M680X_INS_LBCC = 173 , # [doc = "< or LBLO"] M680X_INS_LBCS = 174 , M680X_INS_LBEQ = 175 , M680X_INS_LBGE = 176 , M680X_INS_LBGT = 177 , M680X_INS_LBHI = 178 , M680X_INS_LBLE = 179 , M680X_INS_LBLS = 180 , M680X_INS_LBLT = 181 , M680X_INS_LBMI = 182 , M680X_INS_LBNE = 183 , M680X_INS_LBPL = 184 , M680X_INS_LBRA = 185 , M680X_INS_LBRN = 186 , M680X_INS_LBSR = 187 , M680X_INS_LBVC = 188 , M680X_INS_LBVS = 189 , M680X_INS_LDA = 190 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAA = 191 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAB = 192 , M680X_INS_LDB = 193 , M680X_INS_LDBT = 194 , M680X_INS_LDD = 195 , M680X_INS_LDE = 196 , M680X_INS_LDF = 197 , M680X_INS_LDHX = 198 , M680X_INS_LDMD = 199 , M680X_INS_LDQ = 200 , M680X_INS_LDS = 201 , M680X_INS_LDU = 202 , M680X_INS_LDW = 203 , M680X_INS_LDX = 204 , M680X_INS_LDY = 205 , M680X_INS_LEAS = 206 , M680X_INS_LEAU = 207 , M680X_INS_LEAX = 208 , M680X_INS_LEAY = 209 , M680X_INS_LSL = 210 , M680X_INS_LSLA = 211 , M680X_INS_LSLB = 212 , M680X_INS_LSLD = 213 , M680X_INS_LSLX = 214 , M680X_INS_LSR = 215 , M680X_INS_LSRA = 216 , M680X_INS_LSRB = 217 , # [doc = "< or ASRD"] M680X_INS_LSRD = 218 , M680X_INS_LSRW = 219 , M680X_INS_LSRX = 220 , M680X_INS_MAXA = 221 , M680X_INS_MAXM = 222 , M680X_INS_MEM = 223 , M680X_INS_MINA = 224 , M680X_INS_MINM = 225 , M680X_INS_MOV = 226 , M680X_INS_MOVB = 227 , M680X_INS_MOVW = 228 , M680X_INS_MUL = 229 , M680X_INS_MULD = 230 , M680X_INS_NEG = 231 , M680X_INS_NEGA = 232 , M680X_INS_NEGB = 233 , M680X_INS_NEGD = 234 , M680X_INS_NEGX = 235 , M680X_INS_NOP = 236 , M680X_INS_NSA = 237 , M680X_INS_OIM = 238 , M680X_INS_ORA = 239 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAA = 240 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAB = 241 , M680X_INS_ORB = 242 , M680X_INS_ORCC = 243 , M680X_INS_ORD = 244 , M680X_INS_ORR = 245 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHA = 246 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHB = 247 , M680X_INS_PSHC = 248 , M680X_INS_PSHD = 249 , M680X_INS_PSHH = 250 , M680X_INS_PSHS = 251 , M680X_INS_PSHSW = 252 , M680X_INS_PSHU = 253 , M680X_INS_PSHUW = 254 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHX = 255 , M680X_INS_PSHY = 256 , # [doc = "< M6800/1/2/3"] M680X_INS_PULA = 257 , # [doc = "< M6800/1/2/3"] M680X_INS_PULB = 258 , M680X_INS_PULC = 259 , M680X_INS_PULD = 260 , M680X_INS_PULH = 261 , M680X_INS_PULS = 262 , M680X_INS_PULSW = 263 , M680X_INS_PULU = 264 , M680X_INS_PULUW = 265 , # [doc = "< M6800/1/2/3"] M680X_INS_PULX = 266 , M680X_INS_PULY = 267 , M680X_INS_REV = 268 , M680X_INS_REVW = 269 , M680X_INS_ROL = 270 , M680X_INS_ROLA = 271 , M680X_INS_ROLB = 272 , M680X_INS_ROLD = 273 , M680X_INS_ROLW = 274 , M680X_INS_ROLX = 275 , M680X_INS_ROR = 276 , M680X_INS_RORA = 277 , M680X_INS_RORB = 278 , M680X_INS_RORD = 279 , M680X_INS_RORW = 280 , M680X_INS_RORX = 281 , M680X_INS_RSP = 282 , M680X_INS_RTC = 283 , M680X_INS_RTI = 284 , M680X_INS_RTS = 285 , # [doc = "< M6800/1/2/3"] M680X_INS_SBA = 286 , M680X_INS_SBC = 287 , M680X_INS_SBCA = 288 , M680X_INS_SBCB = 289 , M680X_INS_SBCD = 290 , M680X_INS_SBCR = 291 , M680X_INS_SEC = 292 , M680X_INS_SEI = 293 , M680X_INS_SEV = 294 , M680X_INS_SEX = 295 , M680X_INS_SEXW = 296 , M680X_INS_SLP = 297 , M680X_INS_STA = 298 , # [doc = "< M6800/1/2/3"] M680X_INS_STAA = 299 , # [doc = "< M6800/1/2/3"] M680X_INS_STAB = 300 , M680X_INS_STB = 301 , M680X_INS_STBT = 302 , M680X_INS_STD = 303 , M680X_INS_STE = 304 , M680X_INS_STF = 305 , M680X_INS_STOP = 306 , M680X_INS_STHX = 307 , M680X_INS_STQ = 308 , M680X_INS_STS = 309 , M680X_INS_STU = 310 , M680X_INS_STW = 311 , M680X_INS_STX = 312 , M680X_INS_STY = 313 , M680X_INS_SUB = 314 , M680X_INS_SUBA = 315 , M680X_INS_SUBB = 316 , M680X_INS_SUBD = 317 , M680X_INS_SUBE = 318 , M680X_INS_SUBF = 319 , M680X_INS_SUBR = 320 , M680X_INS_SUBW = 321 , M680X_INS_SWI = 322 , M680X_INS_SWI2 = 323 , M680X_INS_SWI3 = 324 , M680X_INS_SYNC = 325 , # [doc = "< M6800/1/2/3"] M680X_INS_TAB = 326 , # [doc = "< M6800/1/2/3"] M680X_INS_TAP = 327 , M680X_INS_TAX = 328 , # [doc = "< M6800/1/2/3"] M680X_INS_TBA = 329 , M680X_INS_TBEQ = 330 , M680X_INS_TBL = 331 , M680X_INS_TBNE = 332 , M680X_INS_TEST = 333 , M680X_INS_TFM = 334 , M680X_INS_TFR = 335 , M680X_INS_TIM = 336 , # [doc = "< M6800/1/2/3"] M680X_INS_TPA = 337 , M680X_INS_TST = 338 , M680X_INS_TSTA = 339 , M680X_INS_TSTB = 340 , M680X_INS_TSTD = 341 , M680X_INS_TSTE = 342 , M680X_INS_TSTF = 343 , M680X_INS_TSTW = 344 , M680X_INS_TSTX = 345 , # [doc = "< M6800/1/2/3"] M680X_INS_TSX = 346 , M680X_INS_TSY = 347 , M680X_INS_TXA = 348 , # [doc = "< M6800/1/2/3"] M680X_INS_TXS = 349 , M680X_INS_TYS = 350 , # [doc = "< M6800/1/2/3"] M680X_INS_WAI = 351 , M680X_INS_WAIT = 352 , M680X_INS_WAV = 353 , M680X_INS_WAVR = 354 , # [doc = "< HD6301"] M680X_INS_XGDX = 355 , M680X_INS_XGDY = 356 , M680X_INS_ENDING = 357 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_evm { # [doc = "< number of items popped from the stack"] pub pop : :: std :: os :: raw :: c_uchar , # [doc = "< number of items pushed into the stack"] pub push : :: std :: os :: raw :: c_uchar , # [doc = "< gas fee for the instruction"] pub fee : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_evm"] [:: std :: mem :: size_of :: < cs_evm > () - 8usize] ; ["Alignment of cs_evm"] [:: std :: mem :: align_of :: < cs_evm > () - 4usize] ; ["Offset of field: cs_evm::pop"] [:: std :: mem :: offset_of ! (cs_evm , pop) - 0usize] ; ["Offset of field: cs_evm::push"] [:: std :: mem :: offset_of ! (cs_evm , push) - 1usize] ; ["Offset of field: cs_evm::fee"] [:: std :: mem :: offset_of ! (cs_evm , fee) - 4usize] ; } ; # [repr (u32)] # [doc = " EVM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn { EVM_INS_STOP = 0 , EVM_INS_ADD = 1 , EVM_INS_MUL = 2 , EVM_INS_SUB = 3 , EVM_INS_DIV = 4 , EVM_INS_SDIV = 5 , EVM_INS_MOD = 6 , EVM_INS_SMOD = 7 , EVM_INS_ADDMOD = 8 , EVM_INS_MULMOD = 9 , EVM_INS_EXP = 10 , EVM_INS_SIGNEXTEND = 11 , EVM_INS_LT = 16 , EVM_INS_GT = 17 , EVM_INS_SLT = 18 , EVM_INS_SGT = 19 , EVM_INS_EQ = 20 , EVM_INS_ISZERO = 21 , EVM_INS_AND = 22 , EVM_INS_OR = 23 , EVM_INS_XOR = 24 , EVM_INS_NOT = 25 , EVM_INS_BYTE = 26 , EVM_INS_SHA3 = 32 , EVM_INS_ADDRESS = 48 , EVM_INS_BALANCE = 49 , EVM_INS_ORIGIN = 50 , EVM_INS_CALLER = 51 , EVM_INS_CALLVALUE = 52 , EVM_INS_CALLDATALOAD = 53 , EVM_INS_CALLDATASIZE = 54 , EVM_INS_CALLDATACOPY = 55 , EVM_INS_CODESIZE = 56 , EVM_INS_CODECOPY = 57 , EVM_INS_GASPRICE = 58 , EVM_INS_EXTCODESIZE = 59 , EVM_INS_EXTCODECOPY = 60 , EVM_INS_RETURNDATASIZE = 61 , EVM_INS_RETURNDATACOPY = 62 , EVM_INS_BLOCKHASH = 64 , EVM_INS_COINBASE = 65 , EVM_INS_TIMESTAMP = 66 , EVM_INS_NUMBER = 67 , EVM_INS_DIFFICULTY = 68 , EVM_INS_GASLIMIT = 69 , EVM_INS_POP = 80 , EVM_INS_MLOAD = 81 , EVM_INS_MSTORE = 82 , EVM_INS_MSTORE8 = 83 , EVM_INS_SLOAD = 84 , EVM_INS_SSTORE = 85 , EVM_INS_JUMP = 86 , EVM_INS_JUMPI = 87 , EVM_INS_PC = 88 , EVM_INS_MSIZE = 89 , EVM_INS_GAS = 90 , EVM_INS_JUMPDEST = 91 , EVM_INS_PUSH1 = 96 , EVM_INS_PUSH2 = 97 , EVM_INS_PUSH3 = 98 , EVM_INS_PUSH4 = 99 , EVM_INS_PUSH5 = 100 , EVM_INS_PUSH6 = 101 , EVM_INS_PUSH7 = 102 , EVM_INS_PUSH8 = 103 , EVM_INS_PUSH9 = 104 , EVM_INS_PUSH10 = 105 , EVM_INS_PUSH11 = 106 , EVM_INS_PUSH12 = 107 , EVM_INS_PUSH13 = 108 , EVM_INS_PUSH14 = 109 , EVM_INS_PUSH15 = 110 , EVM_INS_PUSH16 = 111 , EVM_INS_PUSH17 = 112 , EVM_INS_PUSH18 = 113 , EVM_INS_PUSH19 = 114 , EVM_INS_PUSH20 = 115 , EVM_INS_PUSH21 = 116 , EVM_INS_PUSH22 = 117 , EVM_INS_PUSH23 = 118 , EVM_INS_PUSH24 = 119 , EVM_INS_PUSH25 = 120 , EVM_INS_PUSH26 = 121 , EVM_INS_PUSH27 = 122 , EVM_INS_PUSH28 = 123 , EVM_INS_PUSH29 = 124 , EVM_INS_PUSH30 = 125 , EVM_INS_PUSH31 = 126 , EVM_INS_PUSH32 = 127 , EVM_INS_DUP1 = 128 , EVM_INS_DUP2 = 129 , EVM_INS_DUP3 = 130 , EVM_INS_DUP4 = 131 , EVM_INS_DUP5 = 132 , EVM_INS_DUP6 = 133 , EVM_INS_DUP7 = 134 , EVM_INS_DUP8 = 135 , EVM_INS_DUP9 = 136 , EVM_INS_DUP10 = 137 , EVM_INS_DUP11 = 138 , EVM_INS_DUP12 = 139 , EVM_INS_DUP13 = 140 , EVM_INS_DUP14 = 141 , EVM_INS_DUP15 = 142 , EVM_INS_DUP16 = 143 , EVM_INS_SWAP1 = 144 , EVM_INS_SWAP2 = 145 , EVM_INS_SWAP3 = 146 , EVM_INS_SWAP4 = 147 , EVM_INS_SWAP5 = 148 , EVM_INS_SWAP6 = 149 , EVM_INS_SWAP7 = 150 , EVM_INS_SWAP8 = 151 , EVM_INS_SWAP9 = 152 , EVM_INS_SWAP10 = 153 , EVM_INS_SWAP11 = 154 , EVM_INS_SWAP12 = 155 , EVM_INS_SWAP13 = 156 , EVM_INS_SWAP14 = 157 , EVM_INS_SWAP15 = 158 , EVM_INS_SWAP16 = 159 , EVM_INS_LOG0 = 160 , EVM_INS_LOG1 = 161 , EVM_INS_LOG2 = 162 , EVM_INS_LOG3 = 163 , EVM_INS_LOG4 = 164 , EVM_INS_CREATE = 240 , EVM_INS_CALL = 241 , EVM_INS_CALLCODE = 242 , EVM_INS_RETURN = 243 , EVM_INS_DELEGATECALL = 244 , EVM_INS_CALLBLACKBOX = 245 , EVM_INS_STATICCALL = 250 , EVM_INS_REVERT = 253 , EVM_INS_SUICIDE = 255 , EVM_INS_INVALID = 512 , EVM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of EVM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn_group { # [doc = "< = CS_GRP_INVALID"] EVM_GRP_INVALID = 0 , # [doc = "< all jump instructions"] EVM_GRP_JUMP = 1 , # [doc = "< math instructions"] EVM_GRP_MATH = 8 , # [doc = "< instructions write to stack"] EVM_GRP_STACK_WRITE = 9 , # [doc = "< instructions read from stack"] EVM_GRP_STACK_READ = 10 , # [doc = "< instructions write to memory"] EVM_GRP_MEM_WRITE = 11 , # [doc = "< instructions read from memory"] EVM_GRP_MEM_READ = 12 , # [doc = "< instructions write to storage"] EVM_GRP_STORE_WRITE = 13 , # [doc = "< instructions read from storage"] EVM_GRP_STORE_READ = 14 , # [doc = "< instructions halt execution"] EVM_GRP_HALT = 15 , # [doc = "< <-- mark the end of the list of groups"] EVM_GRP_ENDING = 16 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_op_type { RISCV_OP_INVALID = 0 , RISCV_OP_REG = 1 , RISCV_OP_IMM = 2 , RISCV_OP_MEM = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct riscv_op_mem { pub base : :: std :: os :: raw :: c_uint , pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of riscv_op_mem"] [:: std :: mem :: size_of :: < riscv_op_mem > () - 16usize] ; ["Alignment of riscv_op_mem"] [:: std :: mem :: align_of :: < riscv_op_mem > () - 8usize] ; ["Offset of field: riscv_op_mem::base"] [:: std :: mem :: offset_of ! (riscv_op_mem , base) - 0usize] ; ["Offset of field: riscv_op_mem::disp"] [:: std :: mem :: offset_of ! (riscv_op_mem , disp) - 8usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv_op { pub type_ : riscv_op_type , pub __bindgen_anon_1 : cs_riscv_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_riscv_op__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub imm : i64 , pub mem : riscv_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_riscv_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_riscv_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op"] [:: std :: mem :: size_of :: < cs_riscv_op > () - 24usize] ; ["Alignment of cs_riscv_op"] [:: std :: mem :: align_of :: < cs_riscv_op > () - 8usize] ; ["Offset of field: cs_riscv_op::type_"] [:: std :: mem :: offset_of ! (cs_riscv_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv { pub need_effective_addr : bool , pub op_count : u8 , pub operands : [cs_riscv_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv"] [:: std :: mem :: size_of :: < cs_riscv > () - 200usize] ; ["Alignment of cs_riscv"] [:: std :: mem :: align_of :: < cs_riscv > () - 8usize] ; ["Offset of field: cs_riscv::need_effective_addr"] [:: std :: mem :: offset_of ! (cs_riscv , need_effective_addr) - 0usize] ; ["Offset of field: cs_riscv::op_count"] [:: std :: mem :: offset_of ! (cs_riscv , op_count) - 1usize] ; ["Offset of field: cs_riscv::operands"] [:: std :: mem :: offset_of ! (cs_riscv , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}" , self . need_effective_addr , self . op_count , self . operands) } } impl riscv_reg { pub const RISCV_REG_ZERO : riscv_reg = riscv_reg :: RISCV_REG_X0 ; } impl riscv_reg { pub const RISCV_REG_RA : riscv_reg = riscv_reg :: RISCV_REG_X1 ; } impl riscv_reg { pub const RISCV_REG_SP : riscv_reg = riscv_reg :: RISCV_REG_X2 ; } impl riscv_reg { pub const RISCV_REG_GP : riscv_reg = riscv_reg :: RISCV_REG_X3 ; } impl riscv_reg { pub const RISCV_REG_TP : riscv_reg = riscv_reg :: RISCV_REG_X4 ; } impl riscv_reg { pub const RISCV_REG_T0 : riscv_reg = riscv_reg :: RISCV_REG_X5 ; } impl riscv_reg { pub const RISCV_REG_T1 : riscv_reg = riscv_reg :: RISCV_REG_X6 ; } impl riscv_reg { pub const RISCV_REG_T2 : riscv_reg = riscv_reg :: RISCV_REG_X7 ; } impl riscv_reg { pub const RISCV_REG_S0 : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_FP : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_S1 : riscv_reg = riscv_reg :: RISCV_REG_X9 ; } impl riscv_reg { pub const RISCV_REG_A0 : riscv_reg = riscv_reg :: RISCV_REG_X10 ; } impl riscv_reg { pub const RISCV_REG_A1 : riscv_reg = riscv_reg :: RISCV_REG_X11 ; } impl riscv_reg { pub const RISCV_REG_A2 : riscv_reg = riscv_reg :: RISCV_REG_X12 ; } impl riscv_reg { pub const RISCV_REG_A3 : riscv_reg = riscv_reg :: RISCV_REG_X13 ; } impl riscv_reg { pub const RISCV_REG_A4 : riscv_reg = riscv_reg :: RISCV_REG_X14 ; } impl riscv_reg { pub const RISCV_REG_A5 : riscv_reg = riscv_reg :: RISCV_REG_X15 ; } impl riscv_reg { pub const RISCV_REG_A6 : riscv_reg = riscv_reg :: RISCV_REG_X16 ; } impl riscv_reg { pub const RISCV_REG_A7 : riscv_reg = riscv_reg :: RISCV_REG_X17 ; } impl riscv_reg { pub const RISCV_REG_S2 : riscv_reg = riscv_reg :: RISCV_REG_X18 ; } impl riscv_reg { pub const RISCV_REG_S3 : riscv_reg = riscv_reg :: RISCV_REG_X19 ; } impl riscv_reg { pub const RISCV_REG_S4 : riscv_reg = riscv_reg :: RISCV_REG_X20 ; } impl riscv_reg { pub const RISCV_REG_S5 : riscv_reg = riscv_reg :: RISCV_REG_X21 ; } impl riscv_reg { pub const RISCV_REG_S6 : riscv_reg = riscv_reg :: RISCV_REG_X22 ; } impl riscv_reg { pub const RISCV_REG_S7 : riscv_reg = riscv_reg :: RISCV_REG_X23 ; } impl riscv_reg { pub const RISCV_REG_S8 : riscv_reg = riscv_reg :: RISCV_REG_X24 ; } impl riscv_reg { pub const RISCV_REG_S9 : riscv_reg = riscv_reg :: RISCV_REG_X25 ; } impl riscv_reg { pub const RISCV_REG_S10 : riscv_reg = riscv_reg :: RISCV_REG_X26 ; } impl riscv_reg { pub const RISCV_REG_S11 : riscv_reg = riscv_reg :: RISCV_REG_X27 ; } impl riscv_reg { pub const RISCV_REG_T3 : riscv_reg = riscv_reg :: RISCV_REG_X28 ; } impl riscv_reg { pub const RISCV_REG_T4 : riscv_reg = riscv_reg :: RISCV_REG_X29 ; } impl riscv_reg { pub const RISCV_REG_T5 : riscv_reg = riscv_reg :: RISCV_REG_X30 ; } impl riscv_reg { pub const RISCV_REG_T6 : riscv_reg = riscv_reg :: RISCV_REG_X31 ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_reg { RISCV_REG_INVALID = 0 , RISCV_REG_X0 = 1 , RISCV_REG_X1 = 2 , RISCV_REG_X2 = 3 , RISCV_REG_X3 = 4 , RISCV_REG_X4 = 5 , RISCV_REG_X5 = 6 , RISCV_REG_X6 = 7 , RISCV_REG_X7 = 8 , RISCV_REG_X8 = 9 , RISCV_REG_X9 = 10 , RISCV_REG_X10 = 11 , RISCV_REG_X11 = 12 , RISCV_REG_X12 = 13 , RISCV_REG_X13 = 14 , RISCV_REG_X14 = 15 , RISCV_REG_X15 = 16 , RISCV_REG_X16 = 17 , RISCV_REG_X17 = 18 , RISCV_REG_X18 = 19 , RISCV_REG_X19 = 20 , RISCV_REG_X20 = 21 , RISCV_REG_X21 = 22 , RISCV_REG_X22 = 23 , RISCV_REG_X23 = 24 , RISCV_REG_X24 = 25 , RISCV_REG_X25 = 26 , RISCV_REG_X26 = 27 , RISCV_REG_X27 = 28 , RISCV_REG_X28 = 29 , RISCV_REG_X29 = 30 , RISCV_REG_X30 = 31 , RISCV_REG_X31 = 32 , RISCV_REG_F0_32 = 33 , RISCV_REG_F0_64 = 34 , RISCV_REG_F1_32 = 35 , RISCV_REG_F1_64 = 36 , RISCV_REG_F2_32 = 37 , RISCV_REG_F2_64 = 38 , RISCV_REG_F3_32 = 39 , RISCV_REG_F3_64 = 40 , RISCV_REG_F4_32 = 41 , RISCV_REG_F4_64 = 42 , RISCV_REG_F5_32 = 43 , RISCV_REG_F5_64 = 44 , RISCV_REG_F6_32 = 45 , RISCV_REG_F6_64 = 46 , RISCV_REG_F7_32 = 47 , RISCV_REG_F7_64 = 48 , RISCV_REG_F8_32 = 49 , RISCV_REG_F8_64 = 50 , RISCV_REG_F9_32 = 51 , RISCV_REG_F9_64 = 52 , RISCV_REG_F10_32 = 53 , RISCV_REG_F10_64 = 54 , RISCV_REG_F11_32 = 55 , RISCV_REG_F11_64 = 56 , RISCV_REG_F12_32 = 57 , RISCV_REG_F12_64 = 58 , RISCV_REG_F13_32 = 59 , RISCV_REG_F13_64 = 60 , RISCV_REG_F14_32 = 61 , RISCV_REG_F14_64 = 62 , RISCV_REG_F15_32 = 63 , RISCV_REG_F15_64 = 64 , RISCV_REG_F16_32 = 65 , RISCV_REG_F16_64 = 66 , RISCV_REG_F17_32 = 67 , RISCV_REG_F17_64 = 68 , RISCV_REG_F18_32 = 69 , RISCV_REG_F18_64 = 70 , RISCV_REG_F19_32 = 71 , RISCV_REG_F19_64 = 72 , RISCV_REG_F20_32 = 73 , RISCV_REG_F20_64 = 74 , RISCV_REG_F21_32 = 75 , RISCV_REG_F21_64 = 76 , RISCV_REG_F22_32 = 77 , RISCV_REG_F22_64 = 78 , RISCV_REG_F23_32 = 79 , RISCV_REG_F23_64 = 80 , RISCV_REG_F24_32 = 81 , RISCV_REG_F24_64 = 82 , RISCV_REG_F25_32 = 83 , RISCV_REG_F25_64 = 84 , RISCV_REG_F26_32 = 85 , RISCV_REG_F26_64 = 86 , RISCV_REG_F27_32 = 87 , RISCV_REG_F27_64 = 88 , RISCV_REG_F28_32 = 89 , RISCV_REG_F28_64 = 90 , RISCV_REG_F29_32 = 91 , RISCV_REG_F29_64 = 92 , RISCV_REG_F30_32 = 93 , RISCV_REG_F30_64 = 94 , RISCV_REG_F31_32 = 95 , RISCV_REG_F31_64 = 96 , RISCV_REG_ENDING = 97 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn { RISCV_INS_INVALID = 0 , RISCV_INS_ADD = 1 , RISCV_INS_ADDI = 2 , RISCV_INS_ADDIW = 3 , RISCV_INS_ADDW = 4 , RISCV_INS_AMOADD_D = 5 , RISCV_INS_AMOADD_D_AQ = 6 , RISCV_INS_AMOADD_D_AQ_RL = 7 , RISCV_INS_AMOADD_D_RL = 8 , RISCV_INS_AMOADD_W = 9 , RISCV_INS_AMOADD_W_AQ = 10 , RISCV_INS_AMOADD_W_AQ_RL = 11 , RISCV_INS_AMOADD_W_RL = 12 , RISCV_INS_AMOAND_D = 13 , RISCV_INS_AMOAND_D_AQ = 14 , RISCV_INS_AMOAND_D_AQ_RL = 15 , RISCV_INS_AMOAND_D_RL = 16 , RISCV_INS_AMOAND_W = 17 , RISCV_INS_AMOAND_W_AQ = 18 , RISCV_INS_AMOAND_W_AQ_RL = 19 , RISCV_INS_AMOAND_W_RL = 20 , RISCV_INS_AMOMAXU_D = 21 , RISCV_INS_AMOMAXU_D_AQ = 22 , RISCV_INS_AMOMAXU_D_AQ_RL = 23 , RISCV_INS_AMOMAXU_D_RL = 24 , RISCV_INS_AMOMAXU_W = 25 , RISCV_INS_AMOMAXU_W_AQ = 26 , RISCV_INS_AMOMAXU_W_AQ_RL = 27 , RISCV_INS_AMOMAXU_W_RL = 28 , RISCV_INS_AMOMAX_D = 29 , RISCV_INS_AMOMAX_D_AQ = 30 , RISCV_INS_AMOMAX_D_AQ_RL = 31 , RISCV_INS_AMOMAX_D_RL = 32 , RISCV_INS_AMOMAX_W = 33 , RISCV_INS_AMOMAX_W_AQ = 34 , RISCV_INS_AMOMAX_W_AQ_RL = 35 , RISCV_INS_AMOMAX_W_RL = 36 , RISCV_INS_AMOMINU_D = 37 , RISCV_INS_AMOMINU_D_AQ = 38 , RISCV_INS_AMOMINU_D_AQ_RL = 39 , RISCV_INS_AMOMINU_D_RL = 40 , RISCV_INS_AMOMINU_W = 41 , RISCV_INS_AMOMINU_W_AQ = 42 , RISCV_INS_AMOMINU_W_AQ_RL = 43 , RISCV_INS_AMOMINU_W_RL = 44 , RISCV_INS_AMOMIN_D = 45 , RISCV_INS_AMOMIN_D_AQ = 46 , RISCV_INS_AMOMIN_D_AQ_RL = 47 , RISCV_INS_AMOMIN_D_RL = 48 , RISCV_INS_AMOMIN_W = 49 , RISCV_INS_AMOMIN_W_AQ = 50 , RISCV_INS_AMOMIN_W_AQ_RL = 51 , RISCV_INS_AMOMIN_W_RL = 52 , RISCV_INS_AMOOR_D = 53 , RISCV_INS_AMOOR_D_AQ = 54 , RISCV_INS_AMOOR_D_AQ_RL = 55 , RISCV_INS_AMOOR_D_RL = 56 , RISCV_INS_AMOOR_W = 57 , RISCV_INS_AMOOR_W_AQ = 58 , RISCV_INS_AMOOR_W_AQ_RL = 59 , RISCV_INS_AMOOR_W_RL = 60 , RISCV_INS_AMOSWAP_D = 61 , RISCV_INS_AMOSWAP_D_AQ = 62 , RISCV_INS_AMOSWAP_D_AQ_RL = 63 , RISCV_INS_AMOSWAP_D_RL = 64 , RISCV_INS_AMOSWAP_W = 65 , RISCV_INS_AMOSWAP_W_AQ = 66 , RISCV_INS_AMOSWAP_W_AQ_RL = 67 , RISCV_INS_AMOSWAP_W_RL = 68 , RISCV_INS_AMOXOR_D = 69 , RISCV_INS_AMOXOR_D_AQ = 70 , RISCV_INS_AMOXOR_D_AQ_RL = 71 , RISCV_INS_AMOXOR_D_RL = 72 , RISCV_INS_AMOXOR_W = 73 , RISCV_INS_AMOXOR_W_AQ = 74 , RISCV_INS_AMOXOR_W_AQ_RL = 75 , RISCV_INS_AMOXOR_W_RL = 76 , RISCV_INS_AND = 77 , RISCV_INS_ANDI = 78 , RISCV_INS_AUIPC = 79 , RISCV_INS_BEQ = 80 , RISCV_INS_BGE = 81 , RISCV_INS_BGEU = 82 , RISCV_INS_BLT = 83 , RISCV_INS_BLTU = 84 , RISCV_INS_BNE = 85 , RISCV_INS_CSRRC = 86 , RISCV_INS_CSRRCI = 87 , RISCV_INS_CSRRS = 88 , RISCV_INS_CSRRSI = 89 , RISCV_INS_CSRRW = 90 , RISCV_INS_CSRRWI = 91 , RISCV_INS_C_ADD = 92 , RISCV_INS_C_ADDI = 93 , RISCV_INS_C_ADDI16SP = 94 , RISCV_INS_C_ADDI4SPN = 95 , RISCV_INS_C_ADDIW = 96 , RISCV_INS_C_ADDW = 97 , RISCV_INS_C_AND = 98 , RISCV_INS_C_ANDI = 99 , RISCV_INS_C_BEQZ = 100 , RISCV_INS_C_BNEZ = 101 , RISCV_INS_C_EBREAK = 102 , RISCV_INS_C_FLD = 103 , RISCV_INS_C_FLDSP = 104 , RISCV_INS_C_FLW = 105 , RISCV_INS_C_FLWSP = 106 , RISCV_INS_C_FSD = 107 , RISCV_INS_C_FSDSP = 108 , RISCV_INS_C_FSW = 109 , RISCV_INS_C_FSWSP = 110 , RISCV_INS_C_J = 111 , RISCV_INS_C_JAL = 112 , RISCV_INS_C_JALR = 113 , RISCV_INS_C_JR = 114 , RISCV_INS_C_LD = 115 , RISCV_INS_C_LDSP = 116 , RISCV_INS_C_LI = 117 , RISCV_INS_C_LUI = 118 , RISCV_INS_C_LW = 119 , RISCV_INS_C_LWSP = 120 , RISCV_INS_C_MV = 121 , RISCV_INS_C_NOP = 122 , RISCV_INS_C_OR = 123 , RISCV_INS_C_SD = 124 , RISCV_INS_C_SDSP = 125 , RISCV_INS_C_SLLI = 126 , RISCV_INS_C_SRAI = 127 , RISCV_INS_C_SRLI = 128 , RISCV_INS_C_SUB = 129 , RISCV_INS_C_SUBW = 130 , RISCV_INS_C_SW = 131 , RISCV_INS_C_SWSP = 132 , RISCV_INS_C_UNIMP = 133 , RISCV_INS_C_XOR = 134 , RISCV_INS_DIV = 135 , RISCV_INS_DIVU = 136 , RISCV_INS_DIVUW = 137 , RISCV_INS_DIVW = 138 , RISCV_INS_EBREAK = 139 , RISCV_INS_ECALL = 140 , RISCV_INS_FADD_D = 141 , RISCV_INS_FADD_S = 142 , RISCV_INS_FCLASS_D = 143 , RISCV_INS_FCLASS_S = 144 , RISCV_INS_FCVT_D_L = 145 , RISCV_INS_FCVT_D_LU = 146 , RISCV_INS_FCVT_D_S = 147 , RISCV_INS_FCVT_D_W = 148 , RISCV_INS_FCVT_D_WU = 149 , RISCV_INS_FCVT_LU_D = 150 , RISCV_INS_FCVT_LU_S = 151 , RISCV_INS_FCVT_L_D = 152 , RISCV_INS_FCVT_L_S = 153 , RISCV_INS_FCVT_S_D = 154 , RISCV_INS_FCVT_S_L = 155 , RISCV_INS_FCVT_S_LU = 156 , RISCV_INS_FCVT_S_W = 157 , RISCV_INS_FCVT_S_WU = 158 , RISCV_INS_FCVT_WU_D = 159 , RISCV_INS_FCVT_WU_S = 160 , RISCV_INS_FCVT_W_D = 161 , RISCV_INS_FCVT_W_S = 162 , RISCV_INS_FDIV_D = 163 , RISCV_INS_FDIV_S = 164 , RISCV_INS_FENCE = 165 , RISCV_INS_FENCE_I = 166 , RISCV_INS_FENCE_TSO = 167 , RISCV_INS_FEQ_D = 168 , RISCV_INS_FEQ_S = 169 , RISCV_INS_FLD = 170 , RISCV_INS_FLE_D = 171 , RISCV_INS_FLE_S = 172 , RISCV_INS_FLT_D = 173 , RISCV_INS_FLT_S = 174 , RISCV_INS_FLW = 175 , RISCV_INS_FMADD_D = 176 , RISCV_INS_FMADD_S = 177 , RISCV_INS_FMAX_D = 178 , RISCV_INS_FMAX_S = 179 , RISCV_INS_FMIN_D = 180 , RISCV_INS_FMIN_S = 181 , RISCV_INS_FMSUB_D = 182 , RISCV_INS_FMSUB_S = 183 , RISCV_INS_FMUL_D = 184 , RISCV_INS_FMUL_S = 185 , RISCV_INS_FMV_D_X = 186 , RISCV_INS_FMV_W_X = 187 , RISCV_INS_FMV_X_D = 188 , RISCV_INS_FMV_X_W = 189 , RISCV_INS_FNMADD_D = 190 , RISCV_INS_FNMADD_S = 191 , RISCV_INS_FNMSUB_D = 192 , RISCV_INS_FNMSUB_S = 193 , RISCV_INS_FSD = 194 , RISCV_INS_FSGNJN_D = 195 , RISCV_INS_FSGNJN_S = 196 , RISCV_INS_FSGNJX_D = 197 , RISCV_INS_FSGNJX_S = 198 , RISCV_INS_FSGNJ_D = 199 , RISCV_INS_FSGNJ_S = 200 , RISCV_INS_FSQRT_D = 201 , RISCV_INS_FSQRT_S = 202 , RISCV_INS_FSUB_D = 203 , RISCV_INS_FSUB_S = 204 , RISCV_INS_FSW = 205 , RISCV_INS_JAL = 206 , RISCV_INS_JALR = 207 , RISCV_INS_LB = 208 , RISCV_INS_LBU = 209 , RISCV_INS_LD = 210 , RISCV_INS_LH = 211 , RISCV_INS_LHU = 212 , RISCV_INS_LR_D = 213 , RISCV_INS_LR_D_AQ = 214 , RISCV_INS_LR_D_AQ_RL = 215 , RISCV_INS_LR_D_RL = 216 , RISCV_INS_LR_W = 217 , RISCV_INS_LR_W_AQ = 218 , RISCV_INS_LR_W_AQ_RL = 219 , RISCV_INS_LR_W_RL = 220 , RISCV_INS_LUI = 221 , RISCV_INS_LW = 222 , RISCV_INS_LWU = 223 , RISCV_INS_MRET = 224 , RISCV_INS_MUL = 225 , RISCV_INS_MULH = 226 , RISCV_INS_MULHSU = 227 , RISCV_INS_MULHU = 228 , RISCV_INS_MULW = 229 , RISCV_INS_OR = 230 , RISCV_INS_ORI = 231 , RISCV_INS_REM = 232 , RISCV_INS_REMU = 233 , RISCV_INS_REMUW = 234 , RISCV_INS_REMW = 235 , RISCV_INS_SB = 236 , RISCV_INS_SC_D = 237 , RISCV_INS_SC_D_AQ = 238 , RISCV_INS_SC_D_AQ_RL = 239 , RISCV_INS_SC_D_RL = 240 , RISCV_INS_SC_W = 241 , RISCV_INS_SC_W_AQ = 242 , RISCV_INS_SC_W_AQ_RL = 243 , RISCV_INS_SC_W_RL = 244 , RISCV_INS_SD = 245 , RISCV_INS_SFENCE_VMA = 246 , RISCV_INS_SH = 247 , RISCV_INS_SLL = 248 , RISCV_INS_SLLI = 249 , RISCV_INS_SLLIW = 250 , RISCV_INS_SLLW = 251 , RISCV_INS_SLT = 252 , RISCV_INS_SLTI = 253 , RISCV_INS_SLTIU = 254 , RISCV_INS_SLTU = 255 , RISCV_INS_SRA = 256 , RISCV_INS_SRAI = 257 , RISCV_INS_SRAIW = 258 , RISCV_INS_SRAW = 259 , RISCV_INS_SRET = 260 , RISCV_INS_SRL = 261 , RISCV_INS_SRLI = 262 , RISCV_INS_SRLIW = 263 , RISCV_INS_SRLW = 264 , RISCV_INS_SUB = 265 , RISCV_INS_SUBW = 266 , RISCV_INS_SW = 267 , RISCV_INS_UNIMP = 268 , RISCV_INS_URET = 269 , RISCV_INS_WFI = 270 , RISCV_INS_XOR = 271 , RISCV_INS_XORI = 272 , RISCV_INS_ENDING = 273 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn_group { # [doc = "< = CS_GRP_INVALID"] RISCV_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] RISCV_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] RISCV_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] RISCV_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] RISCV_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] RISCV_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] RISCV_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] RISCV_GRP_BRANCH_RELATIVE = 7 , RISCV_GRP_ISRV32 = 128 , RISCV_GRP_ISRV64 = 129 , RISCV_GRP_HASSTDEXTA = 130 , RISCV_GRP_HASSTDEXTC = 131 , RISCV_GRP_HASSTDEXTD = 132 , RISCV_GRP_HASSTDEXTF = 133 , RISCV_GRP_HASSTDEXTM = 134 , RISCV_GRP_ENDING = 135 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_op_type { WASM_OP_INVALID = 0 , WASM_OP_NONE = 1 , WASM_OP_INT7 = 2 , WASM_OP_VARUINT32 = 3 , WASM_OP_VARUINT64 = 4 , WASM_OP_UINT32 = 5 , WASM_OP_UINT64 = 6 , WASM_OP_IMM = 7 , WASM_OP_BRTABLE = 8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_wasm_brtable { pub length : u32 , pub address : u64 , pub default_target : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_brtable"] [:: std :: mem :: size_of :: < cs_wasm_brtable > () - 24usize] ; ["Alignment of cs_wasm_brtable"] [:: std :: mem :: align_of :: < cs_wasm_brtable > () - 8usize] ; ["Offset of field: cs_wasm_brtable::length"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , length) - 0usize] ; ["Offset of field: cs_wasm_brtable::address"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , address) - 8usize] ; ["Offset of field: cs_wasm_brtable::default_target"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , default_target) - 16usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm_op { pub type_ : wasm_op_type , pub size : u32 , pub __bindgen_anon_1 : cs_wasm_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_wasm_op__bindgen_ty_1 { pub int7 : i8 , pub varuint32 : u32 , pub varuint64 : u64 , pub uint32 : u32 , pub uint64 : u64 , pub immediate : [u32 ; 2usize] , pub brtable : cs_wasm_brtable , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_wasm_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_wasm_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::int7"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , int7) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::immediate"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , immediate) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::brtable"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , brtable) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op"] [:: std :: mem :: size_of :: < cs_wasm_op > () - 32usize] ; ["Alignment of cs_wasm_op"] [:: std :: mem :: align_of :: < cs_wasm_op > () - 8usize] ; ["Offset of field: cs_wasm_op::type_"] [:: std :: mem :: offset_of ! (cs_wasm_op , type_) - 0usize] ; ["Offset of field: cs_wasm_op::size"] [:: std :: mem :: offset_of ! (cs_wasm_op , size) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . size , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm { pub op_count : u8 , pub operands : [cs_wasm_op ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm"] [:: std :: mem :: size_of :: < cs_wasm > () - 72usize] ; ["Alignment of cs_wasm"] [:: std :: mem :: align_of :: < cs_wasm > () - 8usize] ; ["Offset of field: cs_wasm::op_count"] [:: std :: mem :: offset_of ! (cs_wasm , op_count) - 0usize] ; ["Offset of field: cs_wasm::operands"] [:: std :: mem :: offset_of ! (cs_wasm , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " WASM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn { WASM_INS_UNREACHABLE = 0 , WASM_INS_NOP = 1 , WASM_INS_BLOCK = 2 , WASM_INS_LOOP = 3 , WASM_INS_IF = 4 , WASM_INS_ELSE = 5 , WASM_INS_END = 11 , WASM_INS_BR = 12 , WASM_INS_BR_IF = 13 , WASM_INS_BR_TABLE = 14 , WASM_INS_RETURN = 15 , WASM_INS_CALL = 16 , WASM_INS_CALL_INDIRECT = 17 , WASM_INS_DROP = 26 , WASM_INS_SELECT = 27 , WASM_INS_GET_LOCAL = 32 , WASM_INS_SET_LOCAL = 33 , WASM_INS_TEE_LOCAL = 34 , WASM_INS_GET_GLOBAL = 35 , WASM_INS_SET_GLOBAL = 36 , WASM_INS_I32_LOAD = 40 , WASM_INS_I64_LOAD = 41 , WASM_INS_F32_LOAD = 42 , WASM_INS_F64_LOAD = 43 , WASM_INS_I32_LOAD8_S = 44 , WASM_INS_I32_LOAD8_U = 45 , WASM_INS_I32_LOAD16_S = 46 , WASM_INS_I32_LOAD16_U = 47 , WASM_INS_I64_LOAD8_S = 48 , WASM_INS_I64_LOAD8_U = 49 , WASM_INS_I64_LOAD16_S = 50 , WASM_INS_I64_LOAD16_U = 51 , WASM_INS_I64_LOAD32_S = 52 , WASM_INS_I64_LOAD32_U = 53 , WASM_INS_I32_STORE = 54 , WASM_INS_I64_STORE = 55 , WASM_INS_F32_STORE = 56 , WASM_INS_F64_STORE = 57 , WASM_INS_I32_STORE8 = 58 , WASM_INS_I32_STORE16 = 59 , WASM_INS_I64_STORE8 = 60 , WASM_INS_I64_STORE16 = 61 , WASM_INS_I64_STORE32 = 62 , WASM_INS_CURRENT_MEMORY = 63 , WASM_INS_GROW_MEMORY = 64 , WASM_INS_I32_CONST = 65 , WASM_INS_I64_CONST = 66 , WASM_INS_F32_CONST = 67 , WASM_INS_F64_CONST = 68 , WASM_INS_I32_EQZ = 69 , WASM_INS_I32_EQ = 70 , WASM_INS_I32_NE = 71 , WASM_INS_I32_LT_S = 72 , WASM_INS_I32_LT_U = 73 , WASM_INS_I32_GT_S = 74 , WASM_INS_I32_GT_U = 75 , WASM_INS_I32_LE_S = 76 , WASM_INS_I32_LE_U = 77 , WASM_INS_I32_GE_S = 78 , WASM_INS_I32_GE_U = 79 , WASM_INS_I64_EQZ = 80 , WASM_INS_I64_EQ = 81 , WASM_INS_I64_NE = 82 , WASM_INS_I64_LT_S = 83 , WASM_INS_I64_LT_U = 84 , WASN_INS_I64_GT_S = 85 , WASM_INS_I64_GT_U = 86 , WASM_INS_I64_LE_S = 87 , WASM_INS_I64_LE_U = 88 , WASM_INS_I64_GE_S = 89 , WASM_INS_I64_GE_U = 90 , WASM_INS_F32_EQ = 91 , WASM_INS_F32_NE = 92 , WASM_INS_F32_LT = 93 , WASM_INS_F32_GT = 94 , WASM_INS_F32_LE = 95 , WASM_INS_F32_GE = 96 , WASM_INS_F64_EQ = 97 , WASM_INS_F64_NE = 98 , WASM_INS_F64_LT = 99 , WASM_INS_F64_GT = 100 , WASM_INS_F64_LE = 101 , WASM_INS_F64_GE = 102 , WASM_INS_I32_CLZ = 103 , WASM_INS_I32_CTZ = 104 , WASM_INS_I32_POPCNT = 105 , WASM_INS_I32_ADD = 106 , WASM_INS_I32_SUB = 107 , WASM_INS_I32_MUL = 108 , WASM_INS_I32_DIV_S = 109 , WASM_INS_I32_DIV_U = 110 , WASM_INS_I32_REM_S = 111 , WASM_INS_I32_REM_U = 112 , WASM_INS_I32_AND = 113 , WASM_INS_I32_OR = 114 , WASM_INS_I32_XOR = 115 , WASM_INS_I32_SHL = 116 , WASM_INS_I32_SHR_S = 117 , WASM_INS_I32_SHR_U = 118 , WASM_INS_I32_ROTL = 119 , WASM_INS_I32_ROTR = 120 , WASM_INS_I64_CLZ = 121 , WASM_INS_I64_CTZ = 122 , WASM_INS_I64_POPCNT = 123 , WASM_INS_I64_ADD = 124 , WASM_INS_I64_SUB = 125 , WASM_INS_I64_MUL = 126 , WASM_INS_I64_DIV_S = 127 , WASM_INS_I64_DIV_U = 128 , WASM_INS_I64_REM_S = 129 , WASM_INS_I64_REM_U = 130 , WASM_INS_I64_AND = 131 , WASM_INS_I64_OR = 132 , WASM_INS_I64_XOR = 133 , WASM_INS_I64_SHL = 134 , WASM_INS_I64_SHR_S = 135 , WASM_INS_I64_SHR_U = 136 , WASM_INS_I64_ROTL = 137 , WASM_INS_I64_ROTR = 138 , WASM_INS_F32_ABS = 139 , WASM_INS_F32_NEG = 140 , WASM_INS_F32_CEIL = 141 , WASM_INS_F32_FLOOR = 142 , WASM_INS_F32_TRUNC = 143 , WASM_INS_F32_NEAREST = 144 , WASM_INS_F32_SQRT = 145 , WASM_INS_F32_ADD = 146 , WASM_INS_F32_SUB = 147 , WASM_INS_F32_MUL = 148 , WASM_INS_F32_DIV = 149 , WASM_INS_F32_MIN = 150 , WASM_INS_F32_MAX = 151 , WASM_INS_F32_COPYSIGN = 152 , WASM_INS_F64_ABS = 153 , WASM_INS_F64_NEG = 154 , WASM_INS_F64_CEIL = 155 , WASM_INS_F64_FLOOR = 156 , WASM_INS_F64_TRUNC = 157 , WASM_INS_F64_NEAREST = 158 , WASM_INS_F64_SQRT = 159 , WASM_INS_F64_ADD = 160 , WASM_INS_F64_SUB = 161 , WASM_INS_F64_MUL = 162 , WASM_INS_F64_DIV = 163 , WASM_INS_F64_MIN = 164 , WASM_INS_F64_MAX = 165 , WASM_INS_F64_COPYSIGN = 166 , WASM_INS_I32_WARP_I64 = 167 , WASP_INS_I32_TRUNC_S_F32 = 168 , WASM_INS_I32_TRUNC_U_F32 = 169 , WASM_INS_I32_TRUNC_S_F64 = 170 , WASM_INS_I32_TRUNC_U_F64 = 171 , WASM_INS_I64_EXTEND_S_I32 = 172 , WASM_INS_I64_EXTEND_U_I32 = 173 , WASM_INS_I64_TRUNC_S_F32 = 174 , WASM_INS_I64_TRUNC_U_F32 = 175 , WASM_INS_I64_TRUNC_S_F64 = 176 , WASM_INS_I64_TRUNC_U_F64 = 177 , WASM_INS_F32_CONVERT_S_I32 = 178 , WASM_INS_F32_CONVERT_U_I32 = 179 , WASM_INS_F32_CONVERT_S_I64 = 180 , WASM_INS_F32_CONVERT_U_I64 = 181 , WASM_INS_F32_DEMOTE_F64 = 182 , WASM_INS_F64_CONVERT_S_I32 = 183 , WASM_INS_F64_CONVERT_U_I32 = 184 , WASM_INS_F64_CONVERT_S_I64 = 185 , WASM_INS_F64_CONVERT_U_I64 = 186 , WASM_INS_F64_PROMOTE_F32 = 187 , WASM_INS_I32_REINTERPRET_F32 = 188 , WASM_INS_I64_REINTERPRET_F64 = 189 , WASM_INS_F32_REINTERPRET_I32 = 190 , WASM_INS_F64_REINTERPRET_I64 = 191 , WASM_INS_INVALID = 512 , WASM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of WASM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn_group { # [doc = "< = CS_GRP_INVALID"] WASM_GRP_INVALID = 0 , WASM_GRP_NUMBERIC = 8 , WASM_GRP_PARAMETRIC = 9 , WASM_GRP_VARIABLE = 10 , WASM_GRP_MEMORY = 11 , WASM_GRP_CONTROL = 12 , # [doc = "< <-- mark the end of the list of groups"] WASM_GRP_ENDING = 13 , } # [repr (u32)] # [doc = " MOS65XX registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_reg { MOS65XX_REG_INVALID = 0 , # [doc = "< accumulator"] MOS65XX_REG_ACC = 1 , # [doc = "< X index register"] MOS65XX_REG_X = 2 , # [doc = "< Y index register"] MOS65XX_REG_Y = 3 , # [doc = "< status register"] MOS65XX_REG_P = 4 , # [doc = "< stack pointer register"] MOS65XX_REG_SP = 5 , # [doc = "< direct page register"] MOS65XX_REG_DP = 6 , # [doc = "< data bank register"] MOS65XX_REG_B = 7 , # [doc = "< program bank register"] MOS65XX_REG_K = 8 , MOS65XX_REG_ENDING = 9 , } # [repr (u32)] # [doc = " MOS65XX Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_address_mode { # [doc = "< No address mode."] MOS65XX_AM_NONE = 0 , # [doc = "< implied addressing (no addressing mode)"] MOS65XX_AM_IMP = 1 , # [doc = "< accumulator addressing"] MOS65XX_AM_ACC = 2 , # [doc = "< 8/16 Bit immediate value"] MOS65XX_AM_IMM = 3 , # [doc = "< relative addressing used by branches"] MOS65XX_AM_REL = 4 , # [doc = "< interrupt addressing"] MOS65XX_AM_INT = 5 , # [doc = "< memory block addressing"] MOS65XX_AM_BLOCK = 6 , # [doc = "< zeropage addressing"] MOS65XX_AM_ZP = 7 , # [doc = "< indexed zeropage addressing by the X index register"] MOS65XX_AM_ZP_X = 8 , # [doc = "< indexed zeropage addressing by the Y index register"] MOS65XX_AM_ZP_Y = 9 , # [doc = "< zero page address, branch relative address"] MOS65XX_AM_ZP_REL = 10 , # [doc = "< indirect zeropage addressing"] MOS65XX_AM_ZP_IND = 11 , # [doc = "< indexed zeropage indirect addressing by the X index register"] MOS65XX_AM_ZP_X_IND = 12 , # [doc = "< indirect zeropage indexed addressing by the Y index register"] MOS65XX_AM_ZP_IND_Y = 13 , # [doc = "< zeropage indirect long addressing"] MOS65XX_AM_ZP_IND_LONG = 14 , # [doc = "< zeropage indirect long addressing indexed by Y register"] MOS65XX_AM_ZP_IND_LONG_Y = 15 , # [doc = "< absolute addressing"] MOS65XX_AM_ABS = 16 , # [doc = "< indexed absolute addressing by the X index register"] MOS65XX_AM_ABS_X = 17 , # [doc = "< indexed absolute addressing by the Y index register"] MOS65XX_AM_ABS_Y = 18 , # [doc = "< absolute indirect addressing"] MOS65XX_AM_ABS_IND = 19 , # [doc = "< indexed absolute indirect addressing by the X index register"] MOS65XX_AM_ABS_X_IND = 20 , # [doc = "< absolute indirect long addressing"] MOS65XX_AM_ABS_IND_LONG = 21 , # [doc = "< absolute long address mode"] MOS65XX_AM_ABS_LONG = 22 , # [doc = "< absolute long address mode, indexed by X register"] MOS65XX_AM_ABS_LONG_X = 23 , # [doc = "< stack relative addressing"] MOS65XX_AM_SR = 24 , # [doc = "< indirect stack relative addressing indexed by the Y index register"] MOS65XX_AM_SR_IND_Y = 25 , } # [repr (u32)] # [doc = " MOS65XX instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_insn { MOS65XX_INS_INVALID = 0 , MOS65XX_INS_ADC = 1 , MOS65XX_INS_AND = 2 , MOS65XX_INS_ASL = 3 , MOS65XX_INS_BBR = 4 , MOS65XX_INS_BBS = 5 , MOS65XX_INS_BCC = 6 , MOS65XX_INS_BCS = 7 , MOS65XX_INS_BEQ = 8 , MOS65XX_INS_BIT = 9 , MOS65XX_INS_BMI = 10 , MOS65XX_INS_BNE = 11 , MOS65XX_INS_BPL = 12 , MOS65XX_INS_BRA = 13 , MOS65XX_INS_BRK = 14 , MOS65XX_INS_BRL = 15 , MOS65XX_INS_BVC = 16 , MOS65XX_INS_BVS = 17 , MOS65XX_INS_CLC = 18 , MOS65XX_INS_CLD = 19 , MOS65XX_INS_CLI = 20 , MOS65XX_INS_CLV = 21 , MOS65XX_INS_CMP = 22 , MOS65XX_INS_COP = 23 , MOS65XX_INS_CPX = 24 , MOS65XX_INS_CPY = 25 , MOS65XX_INS_DEC = 26 , MOS65XX_INS_DEX = 27 , MOS65XX_INS_DEY = 28 , MOS65XX_INS_EOR = 29 , MOS65XX_INS_INC = 30 , MOS65XX_INS_INX = 31 , MOS65XX_INS_INY = 32 , MOS65XX_INS_JML = 33 , MOS65XX_INS_JMP = 34 , MOS65XX_INS_JSL = 35 , MOS65XX_INS_JSR = 36 , MOS65XX_INS_LDA = 37 , MOS65XX_INS_LDX = 38 , MOS65XX_INS_LDY = 39 , MOS65XX_INS_LSR = 40 , MOS65XX_INS_MVN = 41 , MOS65XX_INS_MVP = 42 , MOS65XX_INS_NOP = 43 , MOS65XX_INS_ORA = 44 , MOS65XX_INS_PEA = 45 , MOS65XX_INS_PEI = 46 , MOS65XX_INS_PER = 47 , MOS65XX_INS_PHA = 48 , MOS65XX_INS_PHB = 49 , MOS65XX_INS_PHD = 50 , MOS65XX_INS_PHK = 51 , MOS65XX_INS_PHP = 52 , MOS65XX_INS_PHX = 53 , MOS65XX_INS_PHY = 54 , MOS65XX_INS_PLA = 55 , MOS65XX_INS_PLB = 56 , MOS65XX_INS_PLD = 57 , MOS65XX_INS_PLP = 58 , MOS65XX_INS_PLX = 59 , MOS65XX_INS_PLY = 60 , MOS65XX_INS_REP = 61 , MOS65XX_INS_RMB = 62 , MOS65XX_INS_ROL = 63 , MOS65XX_INS_ROR = 64 , MOS65XX_INS_RTI = 65 , MOS65XX_INS_RTL = 66 , MOS65XX_INS_RTS = 67 , MOS65XX_INS_SBC = 68 , MOS65XX_INS_SEC = 69 , MOS65XX_INS_SED = 70 , MOS65XX_INS_SEI = 71 , MOS65XX_INS_SEP = 72 , MOS65XX_INS_SMB = 73 , MOS65XX_INS_STA = 74 , MOS65XX_INS_STP = 75 , MOS65XX_INS_STX = 76 , MOS65XX_INS_STY = 77 , MOS65XX_INS_STZ = 78 , MOS65XX_INS_TAX = 79 , MOS65XX_INS_TAY = 80 , MOS65XX_INS_TCD = 81 , MOS65XX_INS_TCS = 82 , MOS65XX_INS_TDC = 83 , MOS65XX_INS_TRB = 84 , MOS65XX_INS_TSB = 85 , MOS65XX_INS_TSC = 86 , MOS65XX_INS_TSX = 87 , MOS65XX_INS_TXA = 88 , MOS65XX_INS_TXS = 89 , MOS65XX_INS_TXY = 90 , MOS65XX_INS_TYA = 91 , MOS65XX_INS_TYX = 92 , MOS65XX_INS_WAI = 93 , MOS65XX_INS_WDM = 94 , MOS65XX_INS_XBA = 95 , MOS65XX_INS_XCE = 96 , MOS65XX_INS_ENDING = 97 , } # [repr (u32)] # [doc = " Group of MOS65XX instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_group_type { # [doc = "< CS_GRP_INVALID"] MOS65XX_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MOS65XX_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MOS65XX_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MOS65XX_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MOS65XX_GRP_BRANCH_RELATIVE = 6 , MOS65XX_GRP_ENDING = 7 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MOS65XX_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MOS65XX_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MOS65XX_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MOS65XX_OP_MEM = 3 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx_op { # [doc = "< operand type"] pub type_ : mos65xx_op_type , pub __bindgen_anon_1 : cs_mos65xx_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mos65xx_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : mos65xx_reg , # [doc = "< immediate value for IMM operand"] pub imm : u16 , # [doc = "< address for MEM operand"] pub mem : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Alignment of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op"] [:: std :: mem :: size_of :: < cs_mos65xx_op > () - 8usize] ; ["Alignment of cs_mos65xx_op"] [:: std :: mem :: align_of :: < cs_mos65xx_op > () - 4usize] ; ["Offset of field: cs_mos65xx_op::type_"] [:: std :: mem :: offset_of ! (cs_mos65xx_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The MOS65XX address mode and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx { pub am : mos65xx_address_mode , pub modifies_flags : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mos65xx_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx"] [:: std :: mem :: size_of :: < cs_mos65xx > () - 32usize] ; ["Alignment of cs_mos65xx"] [:: std :: mem :: align_of :: < cs_mos65xx > () - 4usize] ; ["Offset of field: cs_mos65xx::am"] [:: std :: mem :: offset_of ! (cs_mos65xx , am) - 0usize] ; ["Offset of field: cs_mos65xx::modifies_flags"] [:: std :: mem :: offset_of ! (cs_mos65xx , modifies_flags) - 4usize] ; ["Offset of field: cs_mos65xx::op_count"] [:: std :: mem :: offset_of ! (cs_mos65xx , op_count) - 5usize] ; ["Offset of field: cs_mos65xx::operands"] [:: std :: mem :: offset_of ! (cs_mos65xx , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . am , self . modifies_flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_op_type { BPF_OP_INVALID = 0 , BPF_OP_REG = 1 , BPF_OP_IMM = 2 , BPF_OP_OFF = 3 , BPF_OP_MEM = 4 , # [doc = "< M[k] in cBPF"] BPF_OP_MMEM = 5 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] BPF_OP_MSH = 6 , # [doc = "< cBPF's extension (not eBPF)"] BPF_OP_EXT = 7 , } # [repr (u32)] # [doc = " BPF registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_reg { BPF_REG_INVALID = 0 , BPF_REG_A = 1 , BPF_REG_X = 2 , BPF_REG_R0 = 3 , BPF_REG_R1 = 4 , BPF_REG_R2 = 5 , BPF_REG_R3 = 6 , BPF_REG_R4 = 7 , BPF_REG_R5 = 8 , BPF_REG_R6 = 9 , BPF_REG_R7 = 10 , BPF_REG_R8 = 11 , BPF_REG_R9 = 12 , BPF_REG_R10 = 13 , BPF_REG_ENDING = 14 , } # [doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct bpf_op_mem { # [doc = "< base register"] pub base : bpf_reg , # [doc = "< offset value"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of bpf_op_mem"] [:: std :: mem :: size_of :: < bpf_op_mem > () - 8usize] ; ["Alignment of bpf_op_mem"] [:: std :: mem :: align_of :: < bpf_op_mem > () - 4usize] ; ["Offset of field: bpf_op_mem::base"] [:: std :: mem :: offset_of ! (bpf_op_mem , base) - 0usize] ; ["Offset of field: bpf_op_mem::disp"] [:: std :: mem :: offset_of ! (bpf_op_mem , disp) - 4usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_ext_type { BPF_EXT_INVALID = 0 , BPF_EXT_LEN = 1 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf_op { pub type_ : bpf_op_type , pub __bindgen_anon_1 : cs_bpf_op__bindgen_ty_1 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_bpf_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : u8 , # [doc = "< immediate value IMM operand"] pub imm : u64 , # [doc = "< offset value, used in jump & call"] pub off : u32 , # [doc = "< base/disp value for MEM operand"] pub mem : bpf_op_mem , # [doc = "< M[k] in cBPF"] pub mmem : u32 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] pub msh : u32 , # [doc = "< cBPF's extension (not eBPF)"] pub ext : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::off"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , off) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mmem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mmem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::msh"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , msh) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , ext) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op"] [:: std :: mem :: size_of :: < cs_bpf_op > () - 24usize] ; ["Alignment of cs_bpf_op"] [:: std :: mem :: align_of :: < cs_bpf_op > () - 8usize] ; ["Offset of field: cs_bpf_op::type_"] [:: std :: mem :: offset_of ! (cs_bpf_op , type_) - 0usize] ; ["Offset of field: cs_bpf_op::access"] [:: std :: mem :: offset_of ! (cs_bpf_op , access) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf { pub op_count : u8 , pub operands : [cs_bpf_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf"] [:: std :: mem :: size_of :: < cs_bpf > () - 104usize] ; ["Alignment of cs_bpf"] [:: std :: mem :: align_of :: < cs_bpf > () - 8usize] ; ["Offset of field: cs_bpf::op_count"] [:: std :: mem :: offset_of ! (cs_bpf , op_count) - 0usize] ; ["Offset of field: cs_bpf::operands"] [:: std :: mem :: offset_of ! (cs_bpf , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } impl bpf_insn { pub const BPF_INS_LD : bpf_insn = bpf_insn :: BPF_INS_LDW ; } impl bpf_insn { pub const BPF_INS_LDX : bpf_insn = bpf_insn :: BPF_INS_LDXW ; } impl bpf_insn { pub const BPF_INS_ST : bpf_insn = bpf_insn :: BPF_INS_STW ; } impl bpf_insn { pub const BPF_INS_STX : bpf_insn = bpf_insn :: BPF_INS_STXW ; } # [repr (u32)] # [doc = " BPF instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn { BPF_INS_INVALID = 0 , BPF_INS_ADD = 1 , BPF_INS_SUB = 2 , BPF_INS_MUL = 3 , BPF_INS_DIV = 4 , BPF_INS_OR = 5 , BPF_INS_AND = 6 , BPF_INS_LSH = 7 , BPF_INS_RSH = 8 , BPF_INS_NEG = 9 , BPF_INS_MOD = 10 , BPF_INS_XOR = 11 , # [doc = "< eBPF only"] BPF_INS_MOV = 12 , # [doc = "< eBPF only"] BPF_INS_ARSH = 13 , BPF_INS_ADD64 = 14 , BPF_INS_SUB64 = 15 , BPF_INS_MUL64 = 16 , BPF_INS_DIV64 = 17 , BPF_INS_OR64 = 18 , BPF_INS_AND64 = 19 , BPF_INS_LSH64 = 20 , BPF_INS_RSH64 = 21 , BPF_INS_NEG64 = 22 , BPF_INS_MOD64 = 23 , BPF_INS_XOR64 = 24 , BPF_INS_MOV64 = 25 , BPF_INS_ARSH64 = 26 , BPF_INS_LE16 = 27 , BPF_INS_LE32 = 28 , BPF_INS_LE64 = 29 , BPF_INS_BE16 = 30 , BPF_INS_BE32 = 31 , BPF_INS_BE64 = 32 , # [doc = "< eBPF only"] BPF_INS_LDW = 33 , BPF_INS_LDH = 34 , BPF_INS_LDB = 35 , # [doc = "< eBPF only: load 64-bit imm"] BPF_INS_LDDW = 36 , # [doc = "< eBPF only"] BPF_INS_LDXW = 37 , # [doc = "< eBPF only"] BPF_INS_LDXH = 38 , # [doc = "< eBPF only"] BPF_INS_LDXB = 39 , # [doc = "< eBPF only"] BPF_INS_LDXDW = 40 , # [doc = "< eBPF only"] BPF_INS_STW = 41 , # [doc = "< eBPF only"] BPF_INS_STH = 42 , # [doc = "< eBPF only"] BPF_INS_STB = 43 , # [doc = "< eBPF only"] BPF_INS_STDW = 44 , # [doc = "< eBPF only"] BPF_INS_STXW = 45 , # [doc = "< eBPF only"] BPF_INS_STXH = 46 , # [doc = "< eBPF only"] BPF_INS_STXB = 47 , # [doc = "< eBPF only"] BPF_INS_STXDW = 48 , # [doc = "< eBPF only"] BPF_INS_XADDW = 49 , # [doc = "< eBPF only"] BPF_INS_XADDDW = 50 , BPF_INS_JMP = 51 , BPF_INS_JEQ = 52 , BPF_INS_JGT = 53 , BPF_INS_JGE = 54 , BPF_INS_JSET = 55 , # [doc = "< eBPF only"] BPF_INS_JNE = 56 , # [doc = "< eBPF only"] BPF_INS_JSGT = 57 , # [doc = "< eBPF only"] BPF_INS_JSGE = 58 , # [doc = "< eBPF only"] BPF_INS_CALL = 59 , # [doc = "< eBPF only"] BPF_INS_CALLX = 60 , # [doc = "< eBPF only"] BPF_INS_EXIT = 61 , # [doc = "< eBPF only"] BPF_INS_JLT = 62 , # [doc = "< eBPF only"] BPF_INS_JLE = 63 , # [doc = "< eBPF only"] BPF_INS_JSLT = 64 , # [doc = "< eBPF only"] BPF_INS_JSLE = 65 , BPF_INS_RET = 66 , BPF_INS_TAX = 67 , BPF_INS_TXA = 68 , BPF_INS_ENDING = 69 , } # [repr (u32)] # [doc = " Group of BPF instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn_group { # [doc = "< = CS_GRP_INVALID"] BPF_GRP_INVALID = 0 , BPF_GRP_LOAD = 1 , BPF_GRP_STORE = 2 , BPF_GRP_ALU = 3 , BPF_GRP_JUMP = 4 , # [doc = "< eBPF only"] BPF_GRP_CALL = 5 , BPF_GRP_RETURN = 6 , # [doc = "< cBPF only"] BPF_GRP_MISC = 7 , BPF_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " SH registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_reg { SH_REG_INVALID = 0 , SH_REG_R0 = 1 , SH_REG_R1 = 2 , SH_REG_R2 = 3 , SH_REG_R3 = 4 , SH_REG_R4 = 5 , SH_REG_R5 = 6 , SH_REG_R6 = 7 , SH_REG_R7 = 8 , SH_REG_R8 = 9 , SH_REG_R9 = 10 , SH_REG_R10 = 11 , SH_REG_R11 = 12 , SH_REG_R12 = 13 , SH_REG_R13 = 14 , SH_REG_R14 = 15 , SH_REG_R15 = 16 , SH_REG_R0_BANK = 17 , SH_REG_R1_BANK = 18 , SH_REG_R2_BANK = 19 , SH_REG_R3_BANK = 20 , SH_REG_R4_BANK = 21 , SH_REG_R5_BANK = 22 , SH_REG_R6_BANK = 23 , SH_REG_R7_BANK = 24 , SH_REG_FR0 = 25 , SH_REG_FR1 = 26 , SH_REG_FR2 = 27 , SH_REG_FR3 = 28 , SH_REG_FR4 = 29 , SH_REG_FR5 = 30 , SH_REG_FR6 = 31 , SH_REG_FR7 = 32 , SH_REG_FR8 = 33 , SH_REG_FR9 = 34 , SH_REG_FR10 = 35 , SH_REG_FR11 = 36 , SH_REG_FR12 = 37 , SH_REG_FR13 = 38 , SH_REG_FR14 = 39 , SH_REG_FR15 = 40 , SH_REG_DR0 = 41 , SH_REG_DR2 = 42 , SH_REG_DR4 = 43 , SH_REG_DR6 = 44 , SH_REG_DR8 = 45 , SH_REG_DR10 = 46 , SH_REG_DR12 = 47 , SH_REG_DR14 = 48 , SH_REG_XD0 = 49 , SH_REG_XD2 = 50 , SH_REG_XD4 = 51 , SH_REG_XD6 = 52 , SH_REG_XD8 = 53 , SH_REG_XD10 = 54 , SH_REG_XD12 = 55 , SH_REG_XD14 = 56 , SH_REG_XF0 = 57 , SH_REG_XF1 = 58 , SH_REG_XF2 = 59 , SH_REG_XF3 = 60 , SH_REG_XF4 = 61 , SH_REG_XF5 = 62 , SH_REG_XF6 = 63 , SH_REG_XF7 = 64 , SH_REG_XF8 = 65 , SH_REG_XF9 = 66 , SH_REG_XF10 = 67 , SH_REG_XF11 = 68 , SH_REG_XF12 = 69 , SH_REG_XF13 = 70 , SH_REG_XF14 = 71 , SH_REG_XF15 = 72 , SH_REG_FV0 = 73 , SH_REG_FV4 = 74 , SH_REG_FV8 = 75 , SH_REG_FV12 = 76 , SH_REG_XMATRX = 77 , SH_REG_PC = 78 , SH_REG_PR = 79 , SH_REG_MACH = 80 , SH_REG_MACL = 81 , SH_REG_SR = 82 , SH_REG_GBR = 83 , SH_REG_SSR = 84 , SH_REG_SPC = 85 , SH_REG_SGR = 86 , SH_REG_DBR = 87 , SH_REG_VBR = 88 , SH_REG_TBR = 89 , SH_REG_RS = 90 , SH_REG_RE = 91 , SH_REG_MOD = 92 , SH_REG_FPUL = 93 , SH_REG_FPSCR = 94 , SH_REG_DSP_X0 = 95 , SH_REG_DSP_X1 = 96 , SH_REG_DSP_Y0 = 97 , SH_REG_DSP_Y1 = 98 , SH_REG_DSP_A0 = 99 , SH_REG_DSP_A1 = 100 , SH_REG_DSP_A0G = 101 , SH_REG_DSP_A1G = 102 , SH_REG_DSP_M0 = 103 , SH_REG_DSP_M1 = 104 , SH_REG_DSP_DSR = 105 , SH_REG_DSP_RSV0 = 106 , SH_REG_DSP_RSV1 = 107 , SH_REG_DSP_RSV2 = 108 , SH_REG_DSP_RSV3 = 109 , SH_REG_DSP_RSV4 = 110 , SH_REG_DSP_RSV5 = 111 , SH_REG_DSP_RSV6 = 112 , SH_REG_DSP_RSV7 = 113 , SH_REG_DSP_RSV8 = 114 , SH_REG_DSP_RSV9 = 115 , SH_REG_DSP_RSVA = 116 , SH_REG_DSP_RSVB = 117 , SH_REG_DSP_RSVC = 118 , SH_REG_DSP_RSVD = 119 , SH_REG_DSP_RSVE = 120 , SH_REG_DSP_RSVF = 121 , SH_REG_ENDING = 122 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SH_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SH_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SH_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SH_OP_MEM = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_mem_type { SH_OP_MEM_INVALID = 0 , # [doc = " <= Invalid"] SH_OP_MEM_REG_IND = 1 , # [doc = " <= Register indirect"] SH_OP_MEM_REG_POST = 2 , # [doc = " <= Register post increment"] SH_OP_MEM_REG_PRE = 3 , # [doc = " <= Register pre decrement"] SH_OP_MEM_REG_DISP = 4 , # [doc = " <= displacement"] SH_OP_MEM_REG_R0 = 5 , # [doc = " <= R0 indexed"] SH_OP_MEM_GBR_DISP = 6 , # [doc = " <= GBR based displacement"] SH_OP_MEM_GBR_R0 = 7 , # [doc = " <= GBR based R0 indexed"] SH_OP_MEM_PCR = 8 , # [doc = " <= PC relative"] SH_OP_MEM_TBR_DISP = 9 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_mem { pub address : sh_op_mem_type , # [doc = " <= memory address"] pub reg : sh_reg , # [doc = " <= base register"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_mem"] [:: std :: mem :: size_of :: < sh_op_mem > () - 12usize] ; ["Alignment of sh_op_mem"] [:: std :: mem :: align_of :: < sh_op_mem > () - 4usize] ; ["Offset of field: sh_op_mem::address"] [:: std :: mem :: offset_of ! (sh_op_mem , address) - 0usize] ; ["Offset of field: sh_op_mem::reg"] [:: std :: mem :: offset_of ! (sh_op_mem , reg) - 4usize] ; ["Offset of field: sh_op_mem::disp"] [:: std :: mem :: offset_of ! (sh_op_mem , disp) - 8usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn_type { SH_INS_DSP_INVALID = 0 , SH_INS_DSP_DOUBLE = 1 , SH_INS_DSP_SINGLE = 2 , SH_INS_DSP_PARALLEL = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn { SH_INS_DSP_NOP = 1 , SH_INS_DSP_MOV = 2 , SH_INS_DSP_PSHL = 3 , SH_INS_DSP_PSHA = 4 , SH_INS_DSP_PMULS = 5 , SH_INS_DSP_PCLR_PMULS = 6 , SH_INS_DSP_PSUB_PMULS = 7 , SH_INS_DSP_PADD_PMULS = 8 , SH_INS_DSP_PSUBC = 9 , SH_INS_DSP_PADDC = 10 , SH_INS_DSP_PCMP = 11 , SH_INS_DSP_PABS = 12 , SH_INS_DSP_PRND = 13 , SH_INS_DSP_PSUB = 14 , SH_INS_DSP_PSUBr = 15 , SH_INS_DSP_PADD = 16 , SH_INS_DSP_PAND = 17 , SH_INS_DSP_PXOR = 18 , SH_INS_DSP_POR = 19 , SH_INS_DSP_PDEC = 20 , SH_INS_DSP_PINC = 21 , SH_INS_DSP_PCLR = 22 , SH_INS_DSP_PDMSB = 23 , SH_INS_DSP_PNEG = 24 , SH_INS_DSP_PCOPY = 25 , SH_INS_DSP_PSTS = 26 , SH_INS_DSP_PLDS = 27 , SH_INS_DSP_PSWAP = 28 , SH_INS_DSP_PWAD = 29 , SH_INS_DSP_PWSB = 30 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_operand { SH_OP_DSP_INVALID = 0 , SH_OP_DSP_REG_PRE = 1 , SH_OP_DSP_REG_IND = 2 , SH_OP_DSP_REG_POST = 3 , SH_OP_DSP_REG_INDEX = 4 , SH_OP_DSP_REG = 5 , SH_OP_DSP_IMM = 6 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_cc { SH_DSP_CC_INVALID = 0 , SH_DSP_CC_NONE = 1 , SH_DSP_CC_DCT = 2 , SH_DSP_CC_DCF = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_dsp { pub insn : sh_dsp_insn , pub operand : [sh_dsp_operand ; 2usize] , pub r : [sh_reg ; 6usize] , pub cc : sh_dsp_cc , pub imm : u8 , pub size : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_dsp"] [:: std :: mem :: size_of :: < sh_op_dsp > () - 48usize] ; ["Alignment of sh_op_dsp"] [:: std :: mem :: align_of :: < sh_op_dsp > () - 4usize] ; ["Offset of field: sh_op_dsp::insn"] [:: std :: mem :: offset_of ! (sh_op_dsp , insn) - 0usize] ; ["Offset of field: sh_op_dsp::operand"] [:: std :: mem :: offset_of ! (sh_op_dsp , operand) - 4usize] ; ["Offset of field: sh_op_dsp::r"] [:: std :: mem :: offset_of ! (sh_op_dsp , r) - 12usize] ; ["Offset of field: sh_op_dsp::cc"] [:: std :: mem :: offset_of ! (sh_op_dsp , cc) - 36usize] ; ["Offset of field: sh_op_dsp::imm"] [:: std :: mem :: offset_of ! (sh_op_dsp , imm) - 40usize] ; ["Offset of field: sh_op_dsp::size"] [:: std :: mem :: offset_of ! (sh_op_dsp , size) - 44usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh_op { pub type_ : sh_op_type , pub __bindgen_anon_1 : cs_sh_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sh_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< register value for REG operand"] pub reg : sh_reg , # [doc = "< data when operand is targeting memory"] pub mem : sh_op_mem , # [doc = "< dsp instruction"] pub dsp : sh_op_dsp , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sh_op__bindgen_ty_1 > () - 48usize] ; ["Alignment of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sh_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::dsp"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , dsp) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op"] [:: std :: mem :: size_of :: < cs_sh_op > () - 56usize] ; ["Alignment of cs_sh_op"] [:: std :: mem :: align_of :: < cs_sh_op > () - 8usize] ; ["Offset of field: cs_sh_op::type_"] [:: std :: mem :: offset_of ! (cs_sh_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (u32)] # [doc = " SH instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn { SH_INS_INVALID = 0 , SH_INS_ADD_r = 1 , SH_INS_ADD = 2 , SH_INS_ADDC = 3 , SH_INS_ADDV = 4 , SH_INS_AND = 5 , SH_INS_BAND = 6 , SH_INS_BANDNOT = 7 , SH_INS_BCLR = 8 , SH_INS_BF = 9 , SH_INS_BF_S = 10 , SH_INS_BLD = 11 , SH_INS_BLDNOT = 12 , SH_INS_BOR = 13 , SH_INS_BORNOT = 14 , SH_INS_BRA = 15 , SH_INS_BRAF = 16 , SH_INS_BSET = 17 , SH_INS_BSR = 18 , SH_INS_BSRF = 19 , SH_INS_BST = 20 , SH_INS_BT = 21 , SH_INS_BT_S = 22 , SH_INS_BXOR = 23 , SH_INS_CLIPS = 24 , SH_INS_CLIPU = 25 , SH_INS_CLRDMXY = 26 , SH_INS_CLRMAC = 27 , SH_INS_CLRS = 28 , SH_INS_CLRT = 29 , SH_INS_CMP_EQ = 30 , SH_INS_CMP_GE = 31 , SH_INS_CMP_GT = 32 , SH_INS_CMP_HI = 33 , SH_INS_CMP_HS = 34 , SH_INS_CMP_PL = 35 , SH_INS_CMP_PZ = 36 , SH_INS_CMP_STR = 37 , SH_INS_DIV0S = 38 , SH_INS_DIV0U = 39 , SH_INS_DIV1 = 40 , SH_INS_DIVS = 41 , SH_INS_DIVU = 42 , SH_INS_DMULS_L = 43 , SH_INS_DMULU_L = 44 , SH_INS_DT = 45 , SH_INS_EXTS_B = 46 , SH_INS_EXTS_W = 47 , SH_INS_EXTU_B = 48 , SH_INS_EXTU_W = 49 , SH_INS_FABS = 50 , SH_INS_FADD = 51 , SH_INS_FCMP_EQ = 52 , SH_INS_FCMP_GT = 53 , SH_INS_FCNVDS = 54 , SH_INS_FCNVSD = 55 , SH_INS_FDIV = 56 , SH_INS_FIPR = 57 , SH_INS_FLDI0 = 58 , SH_INS_FLDI1 = 59 , SH_INS_FLDS = 60 , SH_INS_FLOAT = 61 , SH_INS_FMAC = 62 , SH_INS_FMOV = 63 , SH_INS_FMUL = 64 , SH_INS_FNEG = 65 , SH_INS_FPCHG = 66 , SH_INS_FRCHG = 67 , SH_INS_FSCA = 68 , SH_INS_FSCHG = 69 , SH_INS_FSQRT = 70 , SH_INS_FSRRA = 71 , SH_INS_FSTS = 72 , SH_INS_FSUB = 73 , SH_INS_FTRC = 74 , SH_INS_FTRV = 75 , SH_INS_ICBI = 76 , SH_INS_JMP = 77 , SH_INS_JSR = 78 , SH_INS_JSR_N = 79 , SH_INS_LDBANK = 80 , SH_INS_LDC = 81 , SH_INS_LDRC = 82 , SH_INS_LDRE = 83 , SH_INS_LDRS = 84 , SH_INS_LDS = 85 , SH_INS_LDTLB = 86 , SH_INS_MAC_L = 87 , SH_INS_MAC_W = 88 , SH_INS_MOV = 89 , SH_INS_MOVA = 90 , SH_INS_MOVCA = 91 , SH_INS_MOVCO = 92 , SH_INS_MOVI20 = 93 , SH_INS_MOVI20S = 94 , SH_INS_MOVLI = 95 , SH_INS_MOVML = 96 , SH_INS_MOVMU = 97 , SH_INS_MOVRT = 98 , SH_INS_MOVT = 99 , SH_INS_MOVU = 100 , SH_INS_MOVUA = 101 , SH_INS_MUL_L = 102 , SH_INS_MULR = 103 , SH_INS_MULS_W = 104 , SH_INS_MULU_W = 105 , SH_INS_NEG = 106 , SH_INS_NEGC = 107 , SH_INS_NOP = 108 , SH_INS_NOT = 109 , SH_INS_NOTT = 110 , SH_INS_OCBI = 111 , SH_INS_OCBP = 112 , SH_INS_OCBWB = 113 , SH_INS_OR = 114 , SH_INS_PREF = 115 , SH_INS_PREFI = 116 , SH_INS_RESBANK = 117 , SH_INS_ROTCL = 118 , SH_INS_ROTCR = 119 , SH_INS_ROTL = 120 , SH_INS_ROTR = 121 , SH_INS_RTE = 122 , SH_INS_RTS = 123 , SH_INS_RTS_N = 124 , SH_INS_RTV_N = 125 , SH_INS_SETDMX = 126 , SH_INS_SETDMY = 127 , SH_INS_SETRC = 128 , SH_INS_SETS = 129 , SH_INS_SETT = 130 , SH_INS_SHAD = 131 , SH_INS_SHAL = 132 , SH_INS_SHAR = 133 , SH_INS_SHLD = 134 , SH_INS_SHLL = 135 , SH_INS_SHLL16 = 136 , SH_INS_SHLL2 = 137 , SH_INS_SHLL8 = 138 , SH_INS_SHLR = 139 , SH_INS_SHLR16 = 140 , SH_INS_SHLR2 = 141 , SH_INS_SHLR8 = 142 , SH_INS_SLEEP = 143 , SH_INS_STBANK = 144 , SH_INS_STC = 145 , SH_INS_STS = 146 , SH_INS_SUB = 147 , SH_INS_SUBC = 148 , SH_INS_SUBV = 149 , SH_INS_SWAP_B = 150 , SH_INS_SWAP_W = 151 , SH_INS_SYNCO = 152 , SH_INS_TAS = 153 , SH_INS_TRAPA = 154 , SH_INS_TST = 155 , SH_INS_XOR = 156 , SH_INS_XTRCT = 157 , SH_INS_DSP = 158 , SH_INS_ENDING = 159 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh { pub insn : sh_insn , pub size : u8 , pub op_count : u8 , pub operands : [cs_sh_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh"] [:: std :: mem :: size_of :: < cs_sh > () - 176usize] ; ["Alignment of cs_sh"] [:: std :: mem :: align_of :: < cs_sh > () - 8usize] ; ["Offset of field: cs_sh::insn"] [:: std :: mem :: offset_of ! (cs_sh , insn) - 0usize] ; ["Offset of field: cs_sh::size"] [:: std :: mem :: offset_of ! (cs_sh , size) - 4usize] ; ["Offset of field: cs_sh::op_count"] [:: std :: mem :: offset_of ! (cs_sh , op_count) - 5usize] ; ["Offset of field: cs_sh::operands"] [:: std :: mem :: offset_of ! (cs_sh , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sh { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh {{ insn: {:?}, size: {:?}, op_count: {:?}, operands: {:?} }}" , self . insn , self . size , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Group of SH instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn_group { # [doc = "< CS_GRUP_INVALID"] SH_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SH_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] SH_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] SH_GRP_INT = 3 , # [doc = "< = CS_GRP_RET"] SH_GRP_RET = 4 , # [doc = "< = CS_GRP_IRET"] SH_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] SH_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] SH_GRP_BRANCH_RELATIVE = 7 , SH_GRP_SH1 = 8 , SH_GRP_SH2 = 9 , SH_GRP_SH2E = 10 , SH_GRP_SH2DSP = 11 , SH_GRP_SH2A = 12 , SH_GRP_SH2AFPU = 13 , SH_GRP_SH3 = 14 , SH_GRP_SH3DSP = 15 , SH_GRP_SH4 = 16 , SH_GRP_SH4A = 17 , SH_GRP_ENDING = 18 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_op_type { # [doc = "< CS_OP_INVALID (Uninitialized)."] TRICORE_OP_INVALID = 0 , # [doc = "< CS_OP_REG (Register operand)."] TRICORE_OP_REG = 1 , # [doc = "< CS_OP_IMM (Immediate operand)."] TRICORE_OP_IMM = 2 , # [doc = "< CS_OP_MEM (Memory operand)."] TRICORE_OP_MEM = 3 , } # [doc = " Instruction's operand referring to memory\n This is associated with TRICORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tricore_op_mem { # [doc = "< base register"] pub base : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tricore_op_mem"] [:: std :: mem :: size_of :: < tricore_op_mem > () - 8usize] ; ["Alignment of tricore_op_mem"] [:: std :: mem :: align_of :: < tricore_op_mem > () - 4usize] ; ["Offset of field: tricore_op_mem::base"] [:: std :: mem :: offset_of ! (tricore_op_mem , base) - 0usize] ; ["Offset of field: tricore_op_mem::disp"] [:: std :: mem :: offset_of ! (tricore_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore_op { # [doc = "< operand type"] pub type_ : tricore_op_type , pub __bindgen_anon_1 : cs_tricore_op__bindgen_ty_1 , # [doc = "< How is this operand accessed? (READ, WRITE or READ|WRITE)"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tricore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tricore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tricore_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tricore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op"] [:: std :: mem :: size_of :: < cs_tricore_op > () - 16usize] ; ["Alignment of cs_tricore_op"] [:: std :: mem :: align_of :: < cs_tricore_op > () - 4usize] ; ["Offset of field: cs_tricore_op::type_"] [:: std :: mem :: offset_of ! (cs_tricore_op , type_) - 0usize] ; ["Offset of field: cs_tricore_op::access"] [:: std :: mem :: offset_of ! (cs_tricore_op , access) - 12usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore { # [doc = "< number of operands of this instruction."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tricore_op ; 8usize] , # [doc = "< whether the flags register is updated."] pub update_flags : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore"] [:: std :: mem :: size_of :: < cs_tricore > () - 136usize] ; ["Alignment of cs_tricore"] [:: std :: mem :: align_of :: < cs_tricore > () - 4usize] ; ["Offset of field: cs_tricore::op_count"] [:: std :: mem :: offset_of ! (cs_tricore , op_count) - 0usize] ; ["Offset of field: cs_tricore::operands"] [:: std :: mem :: offset_of ! (cs_tricore , operands) - 4usize] ; ["Offset of field: cs_tricore::update_flags"] [:: std :: mem :: offset_of ! (cs_tricore , update_flags) - 132usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore {{ op_count: {:?}, operands: {:?}, update_flags: {:?} }}" , self . op_count , self . operands , self . update_flags) } } # [repr (u32)] # [doc = " TriCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_reg { TRICORE_REG_INVALID = 0 , TRICORE_REG_FCX = 1 , TRICORE_REG_PC = 2 , TRICORE_REG_PCXI = 3 , TRICORE_REG_PSW = 4 , TRICORE_REG_A0 = 5 , TRICORE_REG_A1 = 6 , TRICORE_REG_A2 = 7 , TRICORE_REG_A3 = 8 , TRICORE_REG_A4 = 9 , TRICORE_REG_A5 = 10 , TRICORE_REG_A6 = 11 , TRICORE_REG_A7 = 12 , TRICORE_REG_A8 = 13 , TRICORE_REG_A9 = 14 , TRICORE_REG_A10 = 15 , TRICORE_REG_A11 = 16 , TRICORE_REG_A12 = 17 , TRICORE_REG_A13 = 18 , TRICORE_REG_A14 = 19 , TRICORE_REG_A15 = 20 , TRICORE_REG_D0 = 21 , TRICORE_REG_D1 = 22 , TRICORE_REG_D2 = 23 , TRICORE_REG_D3 = 24 , TRICORE_REG_D4 = 25 , TRICORE_REG_D5 = 26 , TRICORE_REG_D6 = 27 , TRICORE_REG_D7 = 28 , TRICORE_REG_D8 = 29 , TRICORE_REG_D9 = 30 , TRICORE_REG_D10 = 31 , TRICORE_REG_D11 = 32 , TRICORE_REG_D12 = 33 , TRICORE_REG_D13 = 34 , TRICORE_REG_D14 = 35 , TRICORE_REG_D15 = 36 , TRICORE_REG_E0 = 37 , TRICORE_REG_E2 = 38 , TRICORE_REG_E4 = 39 , TRICORE_REG_E6 = 40 , TRICORE_REG_E8 = 41 , TRICORE_REG_E10 = 42 , TRICORE_REG_E12 = 43 , TRICORE_REG_E14 = 44 , TRICORE_REG_P0 = 45 , TRICORE_REG_P2 = 46 , TRICORE_REG_P4 = 47 , TRICORE_REG_P6 = 48 , TRICORE_REG_P8 = 49 , TRICORE_REG_P10 = 50 , TRICORE_REG_P12 = 51 , TRICORE_REG_P14 = 52 , TRICORE_REG_A0_A1 = 53 , TRICORE_REG_A2_A3 = 54 , TRICORE_REG_A4_A5 = 55 , TRICORE_REG_A6_A7 = 56 , TRICORE_REG_A8_A9 = 57 , TRICORE_REG_A10_A11 = 58 , TRICORE_REG_A12_A13 = 59 , TRICORE_REG_A14_A15 = 60 , TRICORE_REG_ENDING = 61 , } # [repr (u32)] # [doc = " TriCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn { TRICORE_INS_INVALID = 0 , TRICORE_INS_XOR_T = 1 , TRICORE_INS_ABSDIFS_B = 2 , TRICORE_INS_ABSDIFS_H = 3 , TRICORE_INS_ABSDIFS = 4 , TRICORE_INS_ABSDIF_B = 5 , TRICORE_INS_ABSDIF_H = 6 , TRICORE_INS_ABSDIF = 7 , TRICORE_INS_ABSS_B = 8 , TRICORE_INS_ABSS_H = 9 , TRICORE_INS_ABSS = 10 , TRICORE_INS_ABS_B = 11 , TRICORE_INS_ABS_H = 12 , TRICORE_INS_ABS = 13 , TRICORE_INS_ADDC = 14 , TRICORE_INS_ADDIH_A = 15 , TRICORE_INS_ADDIH = 16 , TRICORE_INS_ADDI = 17 , TRICORE_INS_ADDSC_AT = 18 , TRICORE_INS_ADDSC_A = 19 , TRICORE_INS_ADDS_BU = 20 , TRICORE_INS_ADDS_B = 21 , TRICORE_INS_ADDS_H = 22 , TRICORE_INS_ADDS_HU = 23 , TRICORE_INS_ADDS_U = 24 , TRICORE_INS_ADDS = 25 , TRICORE_INS_ADDX = 26 , TRICORE_INS_ADD_A = 27 , TRICORE_INS_ADD_B = 28 , TRICORE_INS_ADD_F = 29 , TRICORE_INS_ADD_H = 30 , TRICORE_INS_ADD = 31 , TRICORE_INS_ANDN_T = 32 , TRICORE_INS_ANDN = 33 , TRICORE_INS_AND_ANDN_T = 34 , TRICORE_INS_AND_AND_T = 35 , TRICORE_INS_AND_EQ = 36 , TRICORE_INS_AND_GE_U = 37 , TRICORE_INS_AND_GE = 38 , TRICORE_INS_AND_LT_U = 39 , TRICORE_INS_AND_LT = 40 , TRICORE_INS_AND_NE = 41 , TRICORE_INS_AND_NOR_T = 42 , TRICORE_INS_AND_OR_T = 43 , TRICORE_INS_AND_T = 44 , TRICORE_INS_AND = 45 , TRICORE_INS_BISR = 46 , TRICORE_INS_BMERGE = 47 , TRICORE_INS_BSPLIT = 48 , TRICORE_INS_CACHEA_I = 49 , TRICORE_INS_CACHEA_WI = 50 , TRICORE_INS_CACHEA_W = 51 , TRICORE_INS_CACHEI_I = 52 , TRICORE_INS_CACHEI_WI = 53 , TRICORE_INS_CACHEI_W = 54 , TRICORE_INS_CADDN_A = 55 , TRICORE_INS_CADDN = 56 , TRICORE_INS_CADD_A = 57 , TRICORE_INS_CADD = 58 , TRICORE_INS_CALLA = 59 , TRICORE_INS_CALLI = 60 , TRICORE_INS_CALL = 61 , TRICORE_INS_CLO_B = 62 , TRICORE_INS_CLO_H = 63 , TRICORE_INS_CLO = 64 , TRICORE_INS_CLS_B = 65 , TRICORE_INS_CLS_H = 66 , TRICORE_INS_CLS = 67 , TRICORE_INS_CLZ_B = 68 , TRICORE_INS_CLZ_H = 69 , TRICORE_INS_CLZ = 70 , TRICORE_INS_CMOVN = 71 , TRICORE_INS_CMOV = 72 , TRICORE_INS_CMPSWAP_W = 73 , TRICORE_INS_CMP_F = 74 , TRICORE_INS_CRC32B_W = 75 , TRICORE_INS_CRC32L_W = 76 , TRICORE_INS_CRC32_B = 77 , TRICORE_INS_CRCN = 78 , TRICORE_INS_CSUBN_A = 79 , TRICORE_INS_CSUBN = 80 , TRICORE_INS_CSUB_A = 81 , TRICORE_INS_CSUB = 82 , TRICORE_INS_DEBUG = 83 , TRICORE_INS_DEXTR = 84 , TRICORE_INS_DIFSC_A = 85 , TRICORE_INS_DISABLE = 86 , TRICORE_INS_DIV_F = 87 , TRICORE_INS_DIV_U = 88 , TRICORE_INS_DIV = 89 , TRICORE_INS_DSYNC = 90 , TRICORE_INS_DVADJ = 91 , TRICORE_INS_DVINIT_BU = 92 , TRICORE_INS_DVINIT_B = 93 , TRICORE_INS_DVINIT_HU = 94 , TRICORE_INS_DVINIT_H = 95 , TRICORE_INS_DVINIT_U = 96 , TRICORE_INS_DVINIT = 97 , TRICORE_INS_DVSTEP_U = 98 , TRICORE_INS_DVSTEP = 99 , TRICORE_INS_ENABLE = 100 , TRICORE_INS_EQANY_B = 101 , TRICORE_INS_EQANY_H = 102 , TRICORE_INS_EQZ_A = 103 , TRICORE_INS_EQ_A = 104 , TRICORE_INS_EQ_B = 105 , TRICORE_INS_EQ_H = 106 , TRICORE_INS_EQ_W = 107 , TRICORE_INS_EQ = 108 , TRICORE_INS_EXTR_U = 109 , TRICORE_INS_EXTR = 110 , TRICORE_INS_FCALLA = 111 , TRICORE_INS_FCALLI = 112 , TRICORE_INS_FCALL = 113 , TRICORE_INS_FRET = 114 , TRICORE_INS_FTOHP = 115 , TRICORE_INS_FTOIZ = 116 , TRICORE_INS_FTOI = 117 , TRICORE_INS_FTOQ31Z = 118 , TRICORE_INS_FTOQ31 = 119 , TRICORE_INS_FTOUZ = 120 , TRICORE_INS_FTOU = 121 , TRICORE_INS_GE_A = 122 , TRICORE_INS_GE_U = 123 , TRICORE_INS_GE = 124 , TRICORE_INS_HPTOF = 125 , TRICORE_INS_IMASK = 126 , TRICORE_INS_INSERT = 127 , TRICORE_INS_INSN_T = 128 , TRICORE_INS_INS_T = 129 , TRICORE_INS_ISYNC = 130 , TRICORE_INS_ITOF = 131 , TRICORE_INS_IXMAX_U = 132 , TRICORE_INS_IXMAX = 133 , TRICORE_INS_IXMIN_U = 134 , TRICORE_INS_IXMIN = 135 , TRICORE_INS_JA = 136 , TRICORE_INS_JEQ_A = 137 , TRICORE_INS_JEQ = 138 , TRICORE_INS_JGEZ = 139 , TRICORE_INS_JGE_U = 140 , TRICORE_INS_JGE = 141 , TRICORE_INS_JGTZ = 142 , TRICORE_INS_JI = 143 , TRICORE_INS_JLA = 144 , TRICORE_INS_JLEZ = 145 , TRICORE_INS_JLI = 146 , TRICORE_INS_JLTZ = 147 , TRICORE_INS_JLT_U = 148 , TRICORE_INS_JLT = 149 , TRICORE_INS_JL = 150 , TRICORE_INS_JNED = 151 , TRICORE_INS_JNEI = 152 , TRICORE_INS_JNE_A = 153 , TRICORE_INS_JNE = 154 , TRICORE_INS_JNZ_A = 155 , TRICORE_INS_JNZ_T = 156 , TRICORE_INS_JNZ = 157 , TRICORE_INS_JZ_A = 158 , TRICORE_INS_JZ_T = 159 , TRICORE_INS_JZ = 160 , TRICORE_INS_J = 161 , TRICORE_INS_LDLCX = 162 , TRICORE_INS_LDMST = 163 , TRICORE_INS_LDUCX = 164 , TRICORE_INS_LD_A = 165 , TRICORE_INS_LD_BU = 166 , TRICORE_INS_LD_B = 167 , TRICORE_INS_LD_DA = 168 , TRICORE_INS_LD_D = 169 , TRICORE_INS_LD_HU = 170 , TRICORE_INS_LD_H = 171 , TRICORE_INS_LD_Q = 172 , TRICORE_INS_LD_W = 173 , TRICORE_INS_LEA = 174 , TRICORE_INS_LHA = 175 , TRICORE_INS_LOOPU = 176 , TRICORE_INS_LOOP = 177 , TRICORE_INS_LT_A = 178 , TRICORE_INS_LT_B = 179 , TRICORE_INS_LT_BU = 180 , TRICORE_INS_LT_H = 181 , TRICORE_INS_LT_HU = 182 , TRICORE_INS_LT_U = 183 , TRICORE_INS_LT_W = 184 , TRICORE_INS_LT_WU = 185 , TRICORE_INS_LT = 186 , TRICORE_INS_MADDMS_H = 187 , TRICORE_INS_MADDMS_U = 188 , TRICORE_INS_MADDMS = 189 , TRICORE_INS_MADDM_H = 190 , TRICORE_INS_MADDM_Q = 191 , TRICORE_INS_MADDM_U = 192 , TRICORE_INS_MADDM = 193 , TRICORE_INS_MADDRS_H = 194 , TRICORE_INS_MADDRS_Q = 195 , TRICORE_INS_MADDR_H = 196 , TRICORE_INS_MADDR_Q = 197 , TRICORE_INS_MADDSUMS_H = 198 , TRICORE_INS_MADDSUM_H = 199 , TRICORE_INS_MADDSURS_H = 200 , TRICORE_INS_MADDSUR_H = 201 , TRICORE_INS_MADDSUS_H = 202 , TRICORE_INS_MADDSU_H = 203 , TRICORE_INS_MADDS_H = 204 , TRICORE_INS_MADDS_Q = 205 , TRICORE_INS_MADDS_U = 206 , TRICORE_INS_MADDS = 207 , TRICORE_INS_MADD_F = 208 , TRICORE_INS_MADD_H = 209 , TRICORE_INS_MADD_Q = 210 , TRICORE_INS_MADD_U = 211 , TRICORE_INS_MADD = 212 , TRICORE_INS_MAX_B = 213 , TRICORE_INS_MAX_BU = 214 , TRICORE_INS_MAX_H = 215 , TRICORE_INS_MAX_HU = 216 , TRICORE_INS_MAX_U = 217 , TRICORE_INS_MAX = 218 , TRICORE_INS_MFCR = 219 , TRICORE_INS_MIN_B = 220 , TRICORE_INS_MIN_BU = 221 , TRICORE_INS_MIN_H = 222 , TRICORE_INS_MIN_HU = 223 , TRICORE_INS_MIN_U = 224 , TRICORE_INS_MIN = 225 , TRICORE_INS_MOVH_A = 226 , TRICORE_INS_MOVH = 227 , TRICORE_INS_MOVZ_A = 228 , TRICORE_INS_MOV_AA = 229 , TRICORE_INS_MOV_A = 230 , TRICORE_INS_MOV_D = 231 , TRICORE_INS_MOV_U = 232 , TRICORE_INS_MOV = 233 , TRICORE_INS_MSUBADMS_H = 234 , TRICORE_INS_MSUBADM_H = 235 , TRICORE_INS_MSUBADRS_H = 236 , TRICORE_INS_MSUBADR_H = 237 , TRICORE_INS_MSUBADS_H = 238 , TRICORE_INS_MSUBAD_H = 239 , TRICORE_INS_MSUBMS_H = 240 , TRICORE_INS_MSUBMS_U = 241 , TRICORE_INS_MSUBMS = 242 , TRICORE_INS_MSUBM_H = 243 , TRICORE_INS_MSUBM_Q = 244 , TRICORE_INS_MSUBM_U = 245 , TRICORE_INS_MSUBM = 246 , TRICORE_INS_MSUBRS_H = 247 , TRICORE_INS_MSUBRS_Q = 248 , TRICORE_INS_MSUBR_H = 249 , TRICORE_INS_MSUBR_Q = 250 , TRICORE_INS_MSUBS_H = 251 , TRICORE_INS_MSUBS_Q = 252 , TRICORE_INS_MSUBS_U = 253 , TRICORE_INS_MSUBS = 254 , TRICORE_INS_MSUB_F = 255 , TRICORE_INS_MSUB_H = 256 , TRICORE_INS_MSUB_Q = 257 , TRICORE_INS_MSUB_U = 258 , TRICORE_INS_MSUB = 259 , TRICORE_INS_MTCR = 260 , TRICORE_INS_MULMS_H = 261 , TRICORE_INS_MULM_H = 262 , TRICORE_INS_MULM_U = 263 , TRICORE_INS_MULM = 264 , TRICORE_INS_MULR_H = 265 , TRICORE_INS_MULR_Q = 266 , TRICORE_INS_MULS_U = 267 , TRICORE_INS_MULS = 268 , TRICORE_INS_MUL_F = 269 , TRICORE_INS_MUL_H = 270 , TRICORE_INS_MUL_Q = 271 , TRICORE_INS_MUL_U = 272 , TRICORE_INS_MUL = 273 , TRICORE_INS_NAND_T = 274 , TRICORE_INS_NAND = 275 , TRICORE_INS_NEZ_A = 276 , TRICORE_INS_NE_A = 277 , TRICORE_INS_NE = 278 , TRICORE_INS_NOP = 279 , TRICORE_INS_NOR_T = 280 , TRICORE_INS_NOR = 281 , TRICORE_INS_NOT = 282 , TRICORE_INS_ORN_T = 283 , TRICORE_INS_ORN = 284 , TRICORE_INS_OR_ANDN_T = 285 , TRICORE_INS_OR_AND_T = 286 , TRICORE_INS_OR_EQ = 287 , TRICORE_INS_OR_GE_U = 288 , TRICORE_INS_OR_GE = 289 , TRICORE_INS_OR_LT_U = 290 , TRICORE_INS_OR_LT = 291 , TRICORE_INS_OR_NE = 292 , TRICORE_INS_OR_NOR_T = 293 , TRICORE_INS_OR_OR_T = 294 , TRICORE_INS_OR_T = 295 , TRICORE_INS_OR = 296 , TRICORE_INS_PACK = 297 , TRICORE_INS_PARITY = 298 , TRICORE_INS_POPCNT_W = 299 , TRICORE_INS_Q31TOF = 300 , TRICORE_INS_QSEED_F = 301 , TRICORE_INS_RESTORE = 302 , TRICORE_INS_RET = 303 , TRICORE_INS_RFE = 304 , TRICORE_INS_RFM = 305 , TRICORE_INS_RSLCX = 306 , TRICORE_INS_RSTV = 307 , TRICORE_INS_RSUBS_U = 308 , TRICORE_INS_RSUBS = 309 , TRICORE_INS_RSUB = 310 , TRICORE_INS_SAT_BU = 311 , TRICORE_INS_SAT_B = 312 , TRICORE_INS_SAT_HU = 313 , TRICORE_INS_SAT_H = 314 , TRICORE_INS_SELN_A = 315 , TRICORE_INS_SELN = 316 , TRICORE_INS_SEL_A = 317 , TRICORE_INS_SEL = 318 , TRICORE_INS_SHAS = 319 , TRICORE_INS_SHA_B = 320 , TRICORE_INS_SHA_H = 321 , TRICORE_INS_SHA = 322 , TRICORE_INS_SHUFFLE = 323 , TRICORE_INS_SH_ANDN_T = 324 , TRICORE_INS_SH_AND_T = 325 , TRICORE_INS_SH_B = 326 , TRICORE_INS_SH_EQ = 327 , TRICORE_INS_SH_GE_U = 328 , TRICORE_INS_SH_GE = 329 , TRICORE_INS_SH_H = 330 , TRICORE_INS_SH_LT_U = 331 , TRICORE_INS_SH_LT = 332 , TRICORE_INS_SH_NAND_T = 333 , TRICORE_INS_SH_NE = 334 , TRICORE_INS_SH_NOR_T = 335 , TRICORE_INS_SH_ORN_T = 336 , TRICORE_INS_SH_OR_T = 337 , TRICORE_INS_SH_XNOR_T = 338 , TRICORE_INS_SH_XOR_T = 339 , TRICORE_INS_SH = 340 , TRICORE_INS_STLCX = 341 , TRICORE_INS_STUCX = 342 , TRICORE_INS_ST_A = 343 , TRICORE_INS_ST_B = 344 , TRICORE_INS_ST_DA = 345 , TRICORE_INS_ST_D = 346 , TRICORE_INS_ST_H = 347 , TRICORE_INS_ST_Q = 348 , TRICORE_INS_ST_T = 349 , TRICORE_INS_ST_W = 350 , TRICORE_INS_SUBC = 351 , TRICORE_INS_SUBSC_A = 352 , TRICORE_INS_SUBS_BU = 353 , TRICORE_INS_SUBS_B = 354 , TRICORE_INS_SUBS_HU = 355 , TRICORE_INS_SUBS_H = 356 , TRICORE_INS_SUBS_U = 357 , TRICORE_INS_SUBS = 358 , TRICORE_INS_SUBX = 359 , TRICORE_INS_SUB_A = 360 , TRICORE_INS_SUB_B = 361 , TRICORE_INS_SUB_F = 362 , TRICORE_INS_SUB_H = 363 , TRICORE_INS_SUB = 364 , TRICORE_INS_SVLCX = 365 , TRICORE_INS_SWAPMSK_W = 366 , TRICORE_INS_SWAP_A = 367 , TRICORE_INS_SWAP_W = 368 , TRICORE_INS_SYSCALL = 369 , TRICORE_INS_TLBDEMAP = 370 , TRICORE_INS_TLBFLUSH_A = 371 , TRICORE_INS_TLBFLUSH_B = 372 , TRICORE_INS_TLBMAP = 373 , TRICORE_INS_TLBPROBE_A = 374 , TRICORE_INS_TLBPROBE_I = 375 , TRICORE_INS_TRAPSV = 376 , TRICORE_INS_TRAPV = 377 , TRICORE_INS_UNPACK = 378 , TRICORE_INS_UPDFL = 379 , TRICORE_INS_UTOF = 380 , TRICORE_INS_WAIT = 381 , TRICORE_INS_XNOR_T = 382 , TRICORE_INS_XNOR = 383 , TRICORE_INS_XOR_EQ = 384 , TRICORE_INS_XOR_GE_U = 385 , TRICORE_INS_XOR_GE = 386 , TRICORE_INS_XOR_LT_U = 387 , TRICORE_INS_XOR_LT = 388 , TRICORE_INS_XOR_NE = 389 , TRICORE_INS_XOR = 390 , TRICORE_INS_ENDING = 391 , } # [repr (u32)] # [doc = " Group of TriCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn_group { # [doc = "< = CS_GRP_INVALID"] TRICORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_CALL"] TRICORE_GRP_CALL = 1 , # [doc = "< = CS_GRP_JUMP"] TRICORE_GRP_JUMP = 2 , # [doc = "< mark the end of the list of groups"] TRICORE_GRP_ENDING = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_feature_t { TRICORE_FEATURE_INVALID = 0 , TRICORE_FEATURE_HasV110 = 128 , TRICORE_FEATURE_HasV120_UP = 129 , TRICORE_FEATURE_HasV130_UP = 130 , TRICORE_FEATURE_HasV161 = 131 , TRICORE_FEATURE_HasV160_UP = 132 , TRICORE_FEATURE_HasV131_UP = 133 , TRICORE_FEATURE_HasV161_UP = 134 , TRICORE_FEATURE_HasV162 = 135 , TRICORE_FEATURE_HasV162_UP = 136 , # [doc = "< mark the end of the list of features"] TRICORE_FEATURE_ENDING = 137 , } pub use self :: tricore_feature_t as tricore_feature ; # [doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_detail { pub regs_read : [u16 ; 20usize] , # [doc = "< number of implicit registers read by this insn"] pub regs_read_count : u8 , pub regs_write : [u16 ; 20usize] , # [doc = "< number of implicit registers modified by this insn"] pub regs_write_count : u8 , # [doc = "< list of group this instruction belong to"] pub groups : [u8 ; 8usize] , # [doc = "< number of groups this insn belongs to"] pub groups_count : u8 , # [doc = "< Instruction has writeback operands."] pub writeback : bool , pub __bindgen_anon_1 : cs_detail__bindgen_ty_1 , } # [doc = " Architecture-specific instruction info"] # [repr (C)] # [derive (Copy , Clone)] pub union cs_detail__bindgen_ty_1 { # [doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"] pub x86 : cs_x86 , # [doc = "< ARM64 architecture (aka AArch64)"] pub arm64 : cs_arm64 , # [doc = "< ARM architecture (including Thumb/Thumb2)"] pub arm : cs_arm , # [doc = "< M68K architecture"] pub m68k : cs_m68k , # [doc = "< MIPS architecture"] pub mips : cs_mips , # [doc = "< PowerPC architecture"] pub ppc : cs_ppc , # [doc = "< Sparc architecture"] pub sparc : cs_sparc , # [doc = "< SystemZ architecture"] pub sysz : cs_sysz , # [doc = "< XCore architecture"] pub xcore : cs_xcore , # [doc = "< TMS320C64x architecture"] pub tms320c64x : cs_tms320c64x , # [doc = "< M680X architecture"] pub m680x : cs_m680x , # [doc = "< Ethereum architecture"] pub evm : cs_evm , # [doc = "< MOS65XX architecture (including MOS6502)"] pub mos65xx : cs_mos65xx , # [doc = "< Web Assembly architecture"] pub wasm : cs_wasm , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] pub bpf : cs_bpf , # [doc = "< RISCV architecture"] pub riscv : cs_riscv , # [doc = "< SH architecture"] pub sh : cs_sh , # [doc = "< TriCore architecture"] pub tricore : cs_tricore , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_detail__bindgen_ty_1 > () - 1768usize] ; ["Alignment of cs_detail__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_detail__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_detail__bindgen_ty_1::x86"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , x86) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm64"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm64) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m68k"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m68k) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mips"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mips) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::ppc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , ppc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sparc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sparc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sysz"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sysz) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::xcore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , xcore) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tms320c64x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tms320c64x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m680x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m680x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::evm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , evm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mos65xx"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mos65xx) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::wasm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , wasm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::bpf"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , bpf) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::riscv"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , riscv) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sh"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sh) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tricore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tricore) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_detail__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail"] [:: std :: mem :: size_of :: < cs_detail > () - 1864usize] ; ["Alignment of cs_detail"] [:: std :: mem :: align_of :: < cs_detail > () - 8usize] ; ["Offset of field: cs_detail::regs_read"] [:: std :: mem :: offset_of ! (cs_detail , regs_read) - 0usize] ; ["Offset of field: cs_detail::regs_read_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_read_count) - 40usize] ; ["Offset of field: cs_detail::regs_write"] [:: std :: mem :: offset_of ! (cs_detail , regs_write) - 42usize] ; ["Offset of field: cs_detail::regs_write_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_write_count) - 82usize] ; ["Offset of field: cs_detail::groups"] [:: std :: mem :: offset_of ! (cs_detail , groups) - 83usize] ; ["Offset of field: cs_detail::groups_count"] [:: std :: mem :: offset_of ! (cs_detail , groups_count) - 91usize] ; ["Offset of field: cs_detail::writeback"] [:: std :: mem :: offset_of ! (cs_detail , writeback) - 92usize] ; } ; impl :: std :: fmt :: Debug for cs_detail { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, writeback: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . writeback , self . __bindgen_anon_1) } } # [doc = " Detail information of disassembled instruction"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_insn { # [doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub address : u64 , # [doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub size : u16 , # [doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub bytes : [u8 ; 24usize] , # [doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub mnemonic : [:: std :: os :: raw :: c_char ; 32usize] , # [doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub op_str : [:: std :: os :: raw :: c_char ; 160usize] , # [doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."] pub detail : * mut cs_detail , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_insn"] [:: std :: mem :: size_of :: < cs_insn > () - 248usize] ; ["Alignment of cs_insn"] [:: std :: mem :: align_of :: < cs_insn > () - 8usize] ; ["Offset of field: cs_insn::id"] [:: std :: mem :: offset_of ! (cs_insn , id) - 0usize] ; ["Offset of field: cs_insn::address"] [:: std :: mem :: offset_of ! (cs_insn , address) - 8usize] ; ["Offset of field: cs_insn::size"] [:: std :: mem :: offset_of ! (cs_insn , size) - 16usize] ; ["Offset of field: cs_insn::bytes"] [:: std :: mem :: offset_of ! (cs_insn , bytes) - 18usize] ; ["Offset of field: cs_insn::mnemonic"] [:: std :: mem :: offset_of ! (cs_insn , mnemonic) - 42usize] ; ["Offset of field: cs_insn::op_str"] [:: std :: mem :: offset_of ! (cs_insn , op_str) - 74usize] ; ["Offset of field: cs_insn::detail"] [:: std :: mem :: offset_of ! (cs_insn , detail) - 240usize] ; } ; # [repr (u32)] # [doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_err { # [doc = "< No error: everything was fine"] CS_ERR_OK = 0 , # [doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"] CS_ERR_MEM = 1 , # [doc = "< Unsupported architecture: cs_open()"] CS_ERR_ARCH = 2 , # [doc = "< Invalid handle: cs_op_count(), cs_op_index()"] CS_ERR_HANDLE = 3 , # [doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"] CS_ERR_CSH = 4 , # [doc = "< Invalid/unsupported mode: cs_open()"] CS_ERR_MODE = 5 , # [doc = "< Invalid/unsupported option: cs_option()"] CS_ERR_OPTION = 6 , # [doc = "< Information is unavailable because detail option is OFF"] CS_ERR_DETAIL = 7 , # [doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"] CS_ERR_MEMSETUP = 8 , # [doc = "< Unsupported version (bindings)"] CS_ERR_VERSION = 9 , # [doc = "< Access irrelevant data in \"diet\" engine"] CS_ERR_DIET = 10 , # [doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"] CS_ERR_SKIPDATA = 11 , # [doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_ATT = 12 , # [doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_INTEL = 13 , # [doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_MASM = 14 , } unsafe extern "C" { # [doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."] pub fn cs_version (major : * mut :: std :: os :: raw :: c_int , minor : * mut :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_uint ; } unsafe extern "C" { # [doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."] pub fn cs_support (query : :: std :: os :: raw :: c_int) -> bool ; } unsafe extern "C" { # [doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_open (arch : cs_arch , mode : cs_mode , handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_close (handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"] pub fn cs_option (handle : csh , type_ : cs_opt_type , value : usize) -> cs_err ; } unsafe extern "C" { # [doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"] pub fn cs_errno (handle : csh) -> cs_err ; } unsafe extern "C" { # [doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"] pub fn cs_strerror (code : cs_err) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm (handle : csh , code : * const u8 , code_size : usize , address : u64 , count : usize , insn : * mut * mut cs_insn) -> usize ; } unsafe extern "C" { # [doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."] pub fn cs_free (insn : * mut cs_insn , count : usize) ; } unsafe extern "C" { # [doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"] pub fn cs_malloc (handle : csh) -> * mut cs_insn ; } unsafe extern "C" { # [doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm_iter (handle : csh , code : * mut * const u8 , size : * mut usize , address : * mut u64 , insn : * mut cs_insn) -> bool ; } unsafe extern "C" { # [doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."] pub fn cs_reg_name (handle : csh , reg_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."] pub fn cs_insn_name (handle : csh , insn_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."] pub fn cs_group_name (handle : csh , group_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."] pub fn cs_insn_group (handle : csh , insn : * const cs_insn , group_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."] pub fn cs_reg_read (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."] pub fn cs_reg_write (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."] pub fn cs_op_count (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."] pub fn cs_op_index (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint , position : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } # [doc = " Type of array to keep the list of registers"] pub type cs_regs = [u16 ; 64usize] ; unsafe extern "C" { # [doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_regs_access (handle : csh , insn : * const cs_insn , regs_read : * mut u16 , regs_read_count : * mut u8 , regs_write : * mut u16 , regs_write_count : * mut u8) -> cs_err ; } pub type __builtin_va_list = [__va_list_tag ; 1usize] ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __va_list_tag { pub gp_offset : :: std :: os :: raw :: c_uint , pub fp_offset : :: std :: os :: raw :: c_uint , pub overflow_arg_area : * mut :: std :: os :: raw :: c_void , pub reg_save_area : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __va_list_tag"] [:: std :: mem :: size_of :: < __va_list_tag > () - 24usize] ; ["Alignment of __va_list_tag"] [:: std :: mem :: align_of :: < __va_list_tag > () - 8usize] ; ["Offset of field: __va_list_tag::gp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , gp_offset) - 0usize] ; ["Offset of field: __va_list_tag::fp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , fp_offset) - 4usize] ; ["Offset of field: __va_list_tag::overflow_arg_area"] [:: std :: mem :: offset_of ! (__va_list_tag , overflow_arg_area) - 8usize] ; ["Offset of field: __va_list_tag::reg_save_area"] [:: std :: mem :: offset_of ! (__va_list_tag , reg_save_area) - 16usize] ; } ;
[INFO] [stdout] 3 + # [repr (C)] # [derive (Copy , Clone , Debug , Default , Eq , Hash , Ord , PartialEq , PartialOrd)] pub struct __BindgenBitfieldUnit < Storage > { storage : Storage , } impl < Storage > __BindgenBitfieldUnit < Storage > { # [inline] pub const fn new (storage : Storage) -> Self { Self { storage } } } impl < Storage > __BindgenBitfieldUnit < Storage > where Storage : AsRef < [u8] > + AsMut < [u8] >, { # [inline] fn extract_bit (byte : u8 , index : usize) -> bool { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; byte & mask == mask } # [inline] pub fn get_bit (& self , index : usize) -> bool { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = self . storage . as_ref () [byte_index] ; Self :: extract_bit (byte , index) } # [inline] pub unsafe fn raw_get_bit (this : * const Self , index : usize) -> bool { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { * (core :: ptr :: addr_of ! ((* this) . storage) as * const u8) . offset (byte_index as isize) } ; Self :: extract_bit (byte , index) } # [inline] fn change_bit (byte : u8 , index : usize , val : bool) -> u8 { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; if val { byte | mask } else { byte & ! mask } } # [inline] pub fn set_bit (& mut self , index : usize , val : bool) { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = & mut self . storage . as_mut () [byte_index] ; * byte = Self :: change_bit (* byte , index , val) ; } # [inline] pub unsafe fn raw_set_bit (this : * mut Self , index : usize , val : bool) { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { (core :: ptr :: addr_of_mut ! ((* this) . storage) as * mut u8) . offset (byte_index as isize) } ; unsafe { * byte = Self :: change_bit (* byte , index , val) } ; } # [inline] pub fn get (& self , bit_offset : usize , bit_width : u8) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if self . get_bit (i + bit_offset) { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub unsafe fn raw_get (this : * const Self , bit_offset : usize , bit_width : u8 ,) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if unsafe { Self :: raw_get_bit (this , i + bit_offset) } { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub fn set (& mut self , bit_offset : usize , bit_width : u8 , val : u64) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; self . set_bit (index + bit_offset , val_bit_is_set) ; } } # [inline] pub unsafe fn raw_set (this : * mut Self , bit_offset : usize , bit_width : u8 , val : u64 ,) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; unsafe { Self :: raw_set_bit (this , index + bit_offset , val_bit_is_set) } ; } } } # [derive (PartialEq , Copy , Clone , Hash , Debug , Default)] # [repr (C)] pub struct __BindgenComplex < T > { pub re : T , pub im : T } pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __GLIBC_USE_ISOC2Y : u32 = 0 ; pub const __GLIBC_USE_ISOC23 : u32 = 0 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 202405 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_XOPEN2K24 : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const __TIMESIZE : u32 = 64 ; pub const __USE_TIME_BITS64 : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_GETS : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_SCANF : u32 = 0 ; pub const __GLIBC_USE_C23_STRTOL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_60559_BFP__ : u32 = 201404 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_IEC_60559_COMPLEX__ : u32 = 201404 ; pub const __STDC_ISO_10646__ : u32 = 201706 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 43 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __glibc_c99_flexarr_available : u32 = 1 ; pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI : u32 = 0 ; pub const __HAVE_GENERIC_SELECTION : u32 = 1 ; pub const __GLIBC_USE_LIB_EXT2 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_TYPES_EXT : u32 = 0 ; pub const _STDLIB_H : u32 = 1 ; pub const WNOHANG : u32 = 1 ; pub const WUNTRACED : u32 = 2 ; pub const WSTOPPED : u32 = 2 ; pub const WEXITED : u32 = 4 ; pub const WCONTINUED : u32 = 8 ; pub const WNOWAIT : u32 = 16777216 ; pub const __WNOTHREAD : u32 = 536870912 ; pub const __WALL : u32 = 1073741824 ; pub const __WCLONE : u32 = 2147483648 ; pub const __W_CONTINUED : u32 = 65535 ; pub const __WCOREFLAG : u32 = 128 ; pub const __HAVE_FLOAT128 : u32 = 1 ; pub const __HAVE_DISTINCT_FLOAT128 : u32 = 1 ; pub const __HAVE_FLOAT64X : u32 = 1 ; pub const __HAVE_FLOAT64X_LONG_DOUBLE : u32 = 1 ; pub const __HAVE_FLOAT16 : u32 = 0 ; pub const __HAVE_FLOAT32 : u32 = 1 ; pub const __HAVE_FLOAT64 : u32 = 1 ; pub const __HAVE_FLOAT32X : u32 = 1 ; pub const __HAVE_FLOAT128X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT16 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT128X : u32 = 0 ; pub const __HAVE_FLOATN_NOT_TYPEDEF : u32 = 0 ; pub const __ldiv_t_defined : u32 = 1 ; pub const __lldiv_t_defined : u32 = 1 ; pub const RAND_MAX : u32 = 2147483647 ; pub const EXIT_FAILURE : u32 = 1 ; pub const EXIT_SUCCESS : u32 = 0 ; pub const _SYS_TYPES_H : u32 = 1 ; pub const _BITS_TYPES_H : u32 = 1 ; pub const _BITS_TYPESIZES_H : u32 = 1 ; pub const __OFF_T_MATCHES_OFF64_T : u32 = 1 ; pub const __INO_T_MATCHES_INO64_T : u32 = 1 ; pub const __RLIM_T_MATCHES_RLIM64_T : u32 = 1 ; pub const __STATFS_MATCHES_STATFS64 : u32 = 1 ; pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 : u32 = 1 ; pub const __FD_SETSIZE : u32 = 1024 ; pub const _BITS_TIME64_H : u32 = 1 ; pub const __clock_t_defined : u32 = 1 ; pub const __clockid_t_defined : u32 = 1 ; pub const __time_t_defined : u32 = 1 ; pub const __timer_t_defined : u32 = 1 ; pub const _BITS_STDINT_INTN_H : u32 = 1 ; pub const __BIT_TYPES_DEFINED__ : u32 = 1 ; pub const _ENDIAN_H : u32 = 1 ; pub const _BITS_ENDIAN_H : u32 = 1 ; pub const __LITTLE_ENDIAN : u32 = 1234 ; pub const __BIG_ENDIAN : u32 = 4321 ; pub const __PDP_ENDIAN : u32 = 3412 ; pub const _BITS_ENDIANNESS_H : u32 = 1 ; pub const __BYTE_ORDER : u32 = 1234 ; pub const __FLOAT_WORD_ORDER : u32 = 1234 ; pub const LITTLE_ENDIAN : u32 = 1234 ; pub const BIG_ENDIAN : u32 = 4321 ; pub const PDP_ENDIAN : u32 = 3412 ; pub const BYTE_ORDER : u32 = 1234 ; pub const _BITS_BYTESWAP_H : u32 = 1 ; pub const _BITS_UINTN_IDENTITY_H : u32 = 1 ; pub const _SYS_SELECT_H : u32 = 1 ; pub const __sigset_t_defined : u32 = 1 ; pub const __timeval_defined : u32 = 1 ; pub const _STRUCT_TIMESPEC : u32 = 1 ; pub const FD_SETSIZE : u32 = 1024 ; pub const _BITS_PTHREADTYPES_COMMON_H : u32 = 1 ; pub const _THREAD_SHARED_TYPES_H : u32 = 1 ; pub const _BITS_PTHREADTYPES_ARCH_H : u32 = 1 ; pub const __SIZEOF_PTHREAD_MUTEX_T : u32 = 40 ; pub const __SIZEOF_PTHREAD_ATTR_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_RWLOCK_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_BARRIER_T : u32 = 32 ; pub const __SIZEOF_PTHREAD_MUTEXATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_COND_T : u32 = 48 ; pub const __SIZEOF_PTHREAD_CONDATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_RWLOCKATTR_T : u32 = 8 ; pub const __SIZEOF_PTHREAD_BARRIERATTR_T : u32 = 4 ; pub const _THREAD_MUTEX_INTERNAL_H : u32 = 1 ; pub const __PTHREAD_MUTEX_HAVE_PREV : u32 = 1 ; pub const __have_pthread_attr_t : u32 = 1 ; pub const _ALLOCA_H : u32 = 1 ; pub const _STDIO_H : u32 = 1 ; pub const _____fpos_t_defined : u32 = 1 ; pub const ____mbstate_t_defined : u32 = 1 ; pub const _____fpos64_t_defined : u32 = 1 ; pub const ____FILE_defined : u32 = 1 ; pub const __FILE_defined : u32 = 1 ; pub const __struct_FILE_defined : u32 = 1 ; pub const _IO_EOF_SEEN : u32 = 16 ; pub const _IO_ERR_SEEN : u32 = 32 ; pub const _IO_USER_LOCK : u32 = 32768 ; pub const __cookie_io_functions_t_defined : u32 = 1 ; pub const _IOFBF : u32 = 0 ; pub const _IOLBF : u32 = 1 ; pub const _IONBF : u32 = 2 ; pub const BUFSIZ : u32 = 8192 ; pub const EOF : i32 = - 1 ; pub const SEEK_SET : u32 = 0 ; pub const SEEK_CUR : u32 = 1 ; pub const SEEK_END : u32 = 2 ; pub const P_tmpdir : & [u8 ; 5] = b"/tmp\0" ; pub const L_tmpnam : u32 = 20 ; pub const TMP_MAX : u32 = 238328 ; pub const _BITS_STDIO_LIM_H : u32 = 1 ; pub const FILENAME_MAX : u32 = 4096 ; pub const L_ctermid : u32 = 9 ; pub const FOPEN_MAX : u32 = 16 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const _INTTYPES_H : u32 = 1 ; pub const _STDINT_H : u32 = 1 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const _BITS_STDINT_UINTN_H : u32 = 1 ; pub const _BITS_STDINT_LEAST_H : u32 = 1 ; pub const INT8_MIN : i32 = - 128 ; pub const INT16_MIN : i32 = - 32768 ; pub const INT32_MIN : i32 = - 2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = - 128 ; pub const INT_LEAST16_MIN : i32 = - 32768 ; pub const INT_LEAST32_MIN : i32 = - 2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = - 128 ; pub const INT_FAST16_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST32_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = - 1 ; pub const UINT_FAST32_MAX : i32 = - 1 ; pub const INTPTR_MIN : i64 = - 9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = - 1 ; pub const PTRDIFF_MIN : i64 = - 9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = - 2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = - 1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const ____gwchar_t_defined : u32 = 1 ; pub const __PRI64_PREFIX : & [u8 ; 2] = b"l\0" ; pub const __PRIPTR_PREFIX : & [u8 ; 2] = b"l\0" ; pub const PRId8 : & [u8 ; 4] = b"hhd\0" ; pub const PRId16 : & [u8 ; 3] = b"hd\0" ; pub const PRId32 : & [u8 ; 2] = b"d\0" ; pub const PRId64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const PRIdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const PRIdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIi8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIi16 : & [u8 ; 3] = b"hi\0" ; pub const PRIi32 : & [u8 ; 2] = b"i\0" ; pub const PRIi64 : & [u8 ; 3] = b"li\0" ; pub const PRIiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const PRIiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const PRIiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiFAST16 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST32 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIo8 : & [u8 ; 4] = b"hho\0" ; pub const PRIo16 : & [u8 ; 3] = b"ho\0" ; pub const PRIo32 : & [u8 ; 2] = b"o\0" ; pub const PRIo64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const PRIoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const PRIoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIu8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIu16 : & [u8 ; 3] = b"hu\0" ; pub const PRIu32 : & [u8 ; 2] = b"u\0" ; pub const PRIu64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const PRIuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const PRIuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIx8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIx16 : & [u8 ; 3] = b"hx\0" ; pub const PRIx32 : & [u8 ; 2] = b"x\0" ; pub const PRIx64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const PRIxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const PRIxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIX8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIX16 : & [u8 ; 3] = b"hX\0" ; pub const PRIX32 : & [u8 ; 2] = b"X\0" ; pub const PRIX64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXLEAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXLEAST16 : & [u8 ; 3] = b"hX\0" ; pub const PRIXLEAST32 : & [u8 ; 2] = b"X\0" ; pub const PRIXLEAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXFAST16 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST32 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIdMAX : & [u8 ; 3] = b"ld\0" ; pub const PRIiMAX : & [u8 ; 3] = b"li\0" ; pub const PRIoMAX : & [u8 ; 3] = b"lo\0" ; pub const PRIuMAX : & [u8 ; 3] = b"lu\0" ; pub const PRIxMAX : & [u8 ; 3] = b"lx\0" ; pub const PRIXMAX : & [u8 ; 3] = b"lX\0" ; pub const PRIdPTR : & [u8 ; 3] = b"ld\0" ; pub const PRIiPTR : & [u8 ; 3] = b"li\0" ; pub const PRIoPTR : & [u8 ; 3] = b"lo\0" ; pub const PRIuPTR : & [u8 ; 3] = b"lu\0" ; pub const PRIxPTR : & [u8 ; 3] = b"lx\0" ; pub const PRIXPTR : & [u8 ; 3] = b"lX\0" ; pub const SCNd8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNd16 : & [u8 ; 3] = b"hd\0" ; pub const SCNd32 : & [u8 ; 2] = b"d\0" ; pub const SCNd64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const SCNdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const SCNdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNi8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNi16 : & [u8 ; 3] = b"hi\0" ; pub const SCNi32 : & [u8 ; 2] = b"i\0" ; pub const SCNi64 : & [u8 ; 3] = b"li\0" ; pub const SCNiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const SCNiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const SCNiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiFAST16 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST32 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNu8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNu16 : & [u8 ; 3] = b"hu\0" ; pub const SCNu32 : & [u8 ; 2] = b"u\0" ; pub const SCNu64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const SCNuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const SCNuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNo8 : & [u8 ; 4] = b"hho\0" ; pub const SCNo16 : & [u8 ; 3] = b"ho\0" ; pub const SCNo32 : & [u8 ; 2] = b"o\0" ; pub const SCNo64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const SCNoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const SCNoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNx8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNx16 : & [u8 ; 3] = b"hx\0" ; pub const SCNx32 : & [u8 ; 2] = b"x\0" ; pub const SCNx64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const SCNxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const SCNxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNdMAX : & [u8 ; 3] = b"ld\0" ; pub const SCNiMAX : & [u8 ; 3] = b"li\0" ; pub const SCNoMAX : & [u8 ; 3] = b"lo\0" ; pub const SCNuMAX : & [u8 ; 3] = b"lu\0" ; pub const SCNxMAX : & [u8 ; 3] = b"lx\0" ; pub const SCNdPTR : & [u8 ; 3] = b"ld\0" ; pub const SCNiPTR : & [u8 ; 3] = b"li\0" ; pub const SCNoPTR : & [u8 ; 3] = b"lo\0" ; pub const SCNuPTR : & [u8 ; 3] = b"lu\0" ; pub const SCNxPTR : & [u8 ; 3] = b"lx\0" ; pub const CS_API_MAJOR : u32 = 5 ; pub const CS_API_MINOR : u32 = 0 ; pub const CS_NEXT_VERSION : u32 = 5 ; pub const CS_VERSION_MAJOR : u32 = 5 ; pub const CS_VERSION_MINOR : u32 = 0 ; pub const CS_VERSION_EXTRA : u32 = 7 ; pub const CS_MNEMONIC_SIZE : u32 = 32 ; pub const M68K_OPERAND_COUNT : u32 = 4 ; pub const X86_EFLAGS_MODIFY_AF : u32 = 1 ; pub const X86_EFLAGS_MODIFY_CF : u32 = 2 ; pub const X86_EFLAGS_MODIFY_SF : u32 = 4 ; pub const X86_EFLAGS_MODIFY_ZF : u32 = 8 ; pub const X86_EFLAGS_MODIFY_PF : u32 = 16 ; pub const X86_EFLAGS_MODIFY_OF : u32 = 32 ; pub const X86_EFLAGS_MODIFY_TF : u32 = 64 ; pub const X86_EFLAGS_MODIFY_IF : u32 = 128 ; pub const X86_EFLAGS_MODIFY_DF : u32 = 256 ; pub const X86_EFLAGS_MODIFY_NT : u32 = 512 ; pub const X86_EFLAGS_MODIFY_RF : u32 = 1024 ; pub const X86_EFLAGS_PRIOR_OF : u32 = 2048 ; pub const X86_EFLAGS_PRIOR_SF : u32 = 4096 ; pub const X86_EFLAGS_PRIOR_ZF : u32 = 8192 ; pub const X86_EFLAGS_PRIOR_AF : u32 = 16384 ; pub const X86_EFLAGS_PRIOR_PF : u32 = 32768 ; pub const X86_EFLAGS_PRIOR_CF : u32 = 65536 ; pub const X86_EFLAGS_PRIOR_TF : u32 = 131072 ; pub const X86_EFLAGS_PRIOR_IF : u32 = 262144 ; pub const X86_EFLAGS_PRIOR_DF : u32 = 524288 ; pub const X86_EFLAGS_PRIOR_NT : u32 = 1048576 ; pub const X86_EFLAGS_RESET_OF : u32 = 2097152 ; pub const X86_EFLAGS_RESET_CF : u32 = 4194304 ; pub const X86_EFLAGS_RESET_DF : u32 = 8388608 ; pub const X86_EFLAGS_RESET_IF : u32 = 16777216 ; pub const X86_EFLAGS_RESET_SF : u32 = 33554432 ; pub const X86_EFLAGS_RESET_AF : u32 = 67108864 ; pub const X86_EFLAGS_RESET_TF : u32 = 134217728 ; pub const X86_EFLAGS_RESET_NT : u32 = 268435456 ; pub const X86_EFLAGS_RESET_PF : u32 = 536870912 ; pub const X86_EFLAGS_SET_CF : u32 = 1073741824 ; pub const X86_EFLAGS_SET_DF : u32 = 2147483648 ; pub const X86_EFLAGS_SET_IF : u64 = 4294967296 ; pub const X86_EFLAGS_TEST_OF : u64 = 8589934592 ; pub const X86_EFLAGS_TEST_SF : u64 = 17179869184 ; pub const X86_EFLAGS_TEST_ZF : u64 = 34359738368 ; pub const X86_EFLAGS_TEST_PF : u64 = 68719476736 ; pub const X86_EFLAGS_TEST_CF : u64 = 137438953472 ; pub const X86_EFLAGS_TEST_NT : u64 = 274877906944 ; pub const X86_EFLAGS_TEST_DF : u64 = 549755813888 ; pub const X86_EFLAGS_UNDEFINED_OF : u64 = 1099511627776 ; pub const X86_EFLAGS_UNDEFINED_SF : u64 = 2199023255552 ; pub const X86_EFLAGS_UNDEFINED_ZF : u64 = 4398046511104 ; pub const X86_EFLAGS_UNDEFINED_PF : u64 = 8796093022208 ; pub const X86_EFLAGS_UNDEFINED_AF : u64 = 17592186044416 ; pub const X86_EFLAGS_UNDEFINED_CF : u64 = 35184372088832 ; pub const X86_EFLAGS_RESET_RF : u64 = 70368744177664 ; pub const X86_EFLAGS_TEST_RF : u64 = 140737488355328 ; pub const X86_EFLAGS_TEST_IF : u64 = 281474976710656 ; pub const X86_EFLAGS_TEST_TF : u64 = 562949953421312 ; pub const X86_EFLAGS_TEST_AF : u64 = 1125899906842624 ; pub const X86_EFLAGS_RESET_ZF : u64 = 2251799813685248 ; pub const X86_EFLAGS_SET_OF : u64 = 4503599627370496 ; pub const X86_EFLAGS_SET_SF : u64 = 9007199254740992 ; pub const X86_EFLAGS_SET_ZF : u64 = 18014398509481984 ; pub const X86_EFLAGS_SET_AF : u64 = 36028797018963968 ; pub const X86_EFLAGS_SET_PF : u64 = 72057594037927936 ; pub const X86_EFLAGS_RESET_0F : u64 = 144115188075855872 ; pub const X86_EFLAGS_RESET_AC : u64 = 288230376151711744 ; pub const X86_FPU_FLAGS_MODIFY_C0 : u32 = 1 ; pub const X86_FPU_FLAGS_MODIFY_C1 : u32 = 2 ; pub const X86_FPU_FLAGS_MODIFY_C2 : u32 = 4 ; pub const X86_FPU_FLAGS_MODIFY_C3 : u32 = 8 ; pub const X86_FPU_FLAGS_RESET_C0 : u32 = 16 ; pub const X86_FPU_FLAGS_RESET_C1 : u32 = 32 ; pub const X86_FPU_FLAGS_RESET_C2 : u32 = 64 ; pub const X86_FPU_FLAGS_RESET_C3 : u32 = 128 ; pub const X86_FPU_FLAGS_SET_C0 : u32 = 256 ; pub const X86_FPU_FLAGS_SET_C1 : u32 = 512 ; pub const X86_FPU_FLAGS_SET_C2 : u32 = 1024 ; pub const X86_FPU_FLAGS_SET_C3 : u32 = 2048 ; pub const X86_FPU_FLAGS_UNDEFINED_C0 : u32 = 4096 ; pub const X86_FPU_FLAGS_UNDEFINED_C1 : u32 = 8192 ; pub const X86_FPU_FLAGS_UNDEFINED_C2 : u32 = 16384 ; pub const X86_FPU_FLAGS_UNDEFINED_C3 : u32 = 32768 ; pub const X86_FPU_FLAGS_TEST_C0 : u32 = 65536 ; pub const X86_FPU_FLAGS_TEST_C1 : u32 = 131072 ; pub const X86_FPU_FLAGS_TEST_C2 : u32 = 262144 ; pub const X86_FPU_FLAGS_TEST_C3 : u32 = 524288 ; pub const M680X_OPERAND_COUNT : u32 = 9 ; pub const M680X_OFFSET_NONE : u32 = 0 ; pub const M680X_OFFSET_BITS_5 : u32 = 5 ; pub const M680X_OFFSET_BITS_8 : u32 = 8 ; pub const M680X_OFFSET_BITS_9 : u32 = 9 ; pub const M680X_OFFSET_BITS_16 : u32 = 16 ; pub const M680X_IDX_INDIRECT : u32 = 1 ; pub const M680X_IDX_NO_COMMA : u32 = 2 ; pub const M680X_IDX_POST_INC_DEC : u32 = 4 ; pub const M680X_FIRST_OP_IN_MNEM : u32 = 1 ; pub const M680X_SECOND_OP_IN_MNEM : u32 = 2 ; pub const TRICORE_OP_COUNT : u32 = 8 ; pub const MAX_IMPL_W_REGS : u32 = 20 ; pub const MAX_IMPL_R_REGS : u32 = 20 ; pub const MAX_NUM_GROUPS : u32 = 8 ; pub type __gnuc_va_list = __builtin_va_list ; pub type va_list = __builtin_va_list ; pub type wchar_t = :: std :: os :: raw :: c_int ; pub type __cfloat128 = __BindgenComplex < u128 > ; pub type _Float128 = u128 ; pub type _Float32 = f32 ; pub type _Float64 = f64 ; pub type _Float32x = f64 ; pub type _Float64x = u128 ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct div_t { pub quot : :: std :: os :: raw :: c_int , pub rem : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of div_t"] [:: std :: mem :: size_of :: < div_t > () - 8usize] ; ["Alignment of div_t"] [:: std :: mem :: align_of :: < div_t > () - 4usize] ; ["Offset of field: div_t::quot"] [:: std :: mem :: offset_of ! (div_t , quot) - 0usize] ; ["Offset of field: div_t::rem"] [:: std :: mem :: offset_of ! (div_t , rem) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ldiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ldiv_t"] [:: std :: mem :: size_of :: < ldiv_t > () - 16usize] ; ["Alignment of ldiv_t"] [:: std :: mem :: align_of :: < ldiv_t > () - 8usize] ; ["Offset of field: ldiv_t::quot"] [:: std :: mem :: offset_of ! (ldiv_t , quot) - 0usize] ; ["Offset of field: ldiv_t::rem"] [:: std :: mem :: offset_of ! (ldiv_t , rem) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct lldiv_t { pub quot : :: std :: os :: raw :: c_longlong , pub rem : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of lldiv_t"] [:: std :: mem :: size_of :: < lldiv_t > () - 16usize] ; ["Alignment of lldiv_t"] [:: std :: mem :: align_of :: < lldiv_t > () - 8usize] ; ["Offset of field: lldiv_t::quot"] [:: std :: mem :: offset_of ! (lldiv_t , quot) - 0usize] ; ["Offset of field: lldiv_t::rem"] [:: std :: mem :: offset_of ! (lldiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn __ctype_get_mb_cur_max () -> usize ; } unsafe extern "C" { pub fn atof (__nptr : * const :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn atoi (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn atol (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn atoll (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtod (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn strtof (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f32 ; } unsafe extern "C" { pub fn strtold (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> u128 ; } unsafe extern "C" { pub fn strtol (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn strtoul (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn strtoq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtouq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn strtoll (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtoull (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn l64a (__n : :: std :: os :: raw :: c_long) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn a64l (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } pub type __u_char = :: std :: os :: raw :: c_uchar ; pub type __u_short = :: std :: os :: raw :: c_ushort ; pub type __u_int = :: std :: os :: raw :: c_uint ; pub type __u_long = :: std :: os :: raw :: c_ulong ; pub type __int8_t = :: std :: os :: raw :: c_schar ; pub type __uint8_t = :: std :: os :: raw :: c_uchar ; pub type __int16_t = :: std :: os :: raw :: c_short ; pub type __uint16_t = :: std :: os :: raw :: c_ushort ; pub type __int32_t = :: std :: os :: raw :: c_int ; pub type __uint32_t = :: std :: os :: raw :: c_uint ; pub type __int64_t = :: std :: os :: raw :: c_long ; pub type __uint64_t = :: std :: os :: raw :: c_ulong ; pub type __int_least8_t = __int8_t ; pub type __uint_least8_t = __uint8_t ; pub type __int_least16_t = __int16_t ; pub type __uint_least16_t = __uint16_t ; pub type __int_least32_t = __int32_t ; pub type __uint_least32_t = __uint32_t ; pub type __int_least64_t = __int64_t ; pub type __uint_least64_t = __uint64_t ; pub type __quad_t = :: std :: os :: raw :: c_long ; pub type __u_quad_t = :: std :: os :: raw :: c_ulong ; pub type __intmax_t = :: std :: os :: raw :: c_long ; pub type __uintmax_t = :: std :: os :: raw :: c_ulong ; pub type __dev_t = :: std :: os :: raw :: c_ulong ; pub type __uid_t = :: std :: os :: raw :: c_uint ; pub type __gid_t = :: std :: os :: raw :: c_uint ; pub type __ino_t = :: std :: os :: raw :: c_ulong ; pub type __ino64_t = :: std :: os :: raw :: c_ulong ; pub type __mode_t = :: std :: os :: raw :: c_uint ; pub type __nlink_t = :: std :: os :: raw :: c_ulong ; pub type __off_t = :: std :: os :: raw :: c_long ; pub type __off64_t = :: std :: os :: raw :: c_long ; pub type __pid_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __fsid_t { pub __val : [:: std :: os :: raw :: c_int ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __fsid_t"] [:: std :: mem :: size_of :: < __fsid_t > () - 8usize] ; ["Alignment of __fsid_t"] [:: std :: mem :: align_of :: < __fsid_t > () - 4usize] ; ["Offset of field: __fsid_t::__val"] [:: std :: mem :: offset_of ! (__fsid_t , __val) - 0usize] ; } ; pub type __clock_t = :: std :: os :: raw :: c_long ; pub type __rlim_t = :: std :: os :: raw :: c_ulong ; pub type __rlim64_t = :: std :: os :: raw :: c_ulong ; pub type __id_t = :: std :: os :: raw :: c_uint ; pub type __time_t = :: std :: os :: raw :: c_long ; pub type __useconds_t = :: std :: os :: raw :: c_uint ; pub type __suseconds_t = :: std :: os :: raw :: c_long ; pub type __suseconds64_t = :: std :: os :: raw :: c_long ; pub type __daddr_t = :: std :: os :: raw :: c_int ; pub type __key_t = :: std :: os :: raw :: c_int ; pub type __clockid_t = :: std :: os :: raw :: c_int ; pub type __timer_t = * mut :: std :: os :: raw :: c_void ; pub type __blksize_t = :: std :: os :: raw :: c_long ; pub type __blkcnt_t = :: std :: os :: raw :: c_long ; pub type __blkcnt64_t = :: std :: os :: raw :: c_long ; pub type __fsblkcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsblkcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsword_t = :: std :: os :: raw :: c_long ; pub type __ssize_t = :: std :: os :: raw :: c_long ; pub type __syscall_slong_t = :: std :: os :: raw :: c_long ; pub type __syscall_ulong_t = :: std :: os :: raw :: c_ulong ; pub type __loff_t = __off64_t ; pub type __caddr_t = * mut :: std :: os :: raw :: c_char ; pub type __intptr_t = :: std :: os :: raw :: c_long ; pub type __socklen_t = :: std :: os :: raw :: c_uint ; pub type __sig_atomic_t = :: std :: os :: raw :: c_int ; pub type u_char = __u_char ; pub type u_short = __u_short ; pub type u_int = __u_int ; pub type u_long = __u_long ; pub type quad_t = __quad_t ; pub type u_quad_t = __u_quad_t ; pub type fsid_t = __fsid_t ; pub type loff_t = __loff_t ; pub type ino_t = __ino_t ; pub type dev_t = __dev_t ; pub type gid_t = __gid_t ; pub type mode_t = __mode_t ; pub type nlink_t = __nlink_t ; pub type uid_t = __uid_t ; pub type off_t = __off_t ; pub type pid_t = __pid_t ; pub type id_t = __id_t ; pub type daddr_t = __daddr_t ; pub type caddr_t = __caddr_t ; pub type key_t = __key_t ; pub type clock_t = __clock_t ; pub type clockid_t = __clockid_t ; pub type time_t = __time_t ; pub type timer_t = __timer_t ; pub type ulong = :: std :: os :: raw :: c_ulong ; pub type ushort = :: std :: os :: raw :: c_ushort ; pub type uint = :: std :: os :: raw :: c_uint ; pub type u_int8_t = __uint8_t ; pub type u_int16_t = __uint16_t ; pub type u_int32_t = __uint32_t ; pub type u_int64_t = __uint64_t ; pub type register_t = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __sigset_t { pub __val : [:: std :: os :: raw :: c_ulong ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __sigset_t"] [:: std :: mem :: size_of :: < __sigset_t > () - 128usize] ; ["Alignment of __sigset_t"] [:: std :: mem :: align_of :: < __sigset_t > () - 8usize] ; ["Offset of field: __sigset_t::__val"] [:: std :: mem :: offset_of ! (__sigset_t , __val) - 0usize] ; } ; pub type sigset_t = __sigset_t ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timeval { pub tv_sec : __time_t , pub tv_usec : __suseconds_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timeval"] [:: std :: mem :: size_of :: < timeval > () - 16usize] ; ["Alignment of timeval"] [:: std :: mem :: align_of :: < timeval > () - 8usize] ; ["Offset of field: timeval::tv_sec"] [:: std :: mem :: offset_of ! (timeval , tv_sec) - 0usize] ; ["Offset of field: timeval::tv_usec"] [:: std :: mem :: offset_of ! (timeval , tv_usec) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timespec { pub tv_sec : __time_t , pub tv_nsec : __syscall_slong_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timespec"] [:: std :: mem :: size_of :: < timespec > () - 16usize] ; ["Alignment of timespec"] [:: std :: mem :: align_of :: < timespec > () - 8usize] ; ["Offset of field: timespec::tv_sec"] [:: std :: mem :: offset_of ! (timespec , tv_sec) - 0usize] ; ["Offset of field: timespec::tv_nsec"] [:: std :: mem :: offset_of ! (timespec , tv_nsec) - 8usize] ; } ; pub type suseconds_t = __suseconds_t ; pub type __fd_mask = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct fd_set { pub __fds_bits : [__fd_mask ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of fd_set"] [:: std :: mem :: size_of :: < fd_set > () - 128usize] ; ["Alignment of fd_set"] [:: std :: mem :: align_of :: < fd_set > () - 8usize] ; ["Offset of field: fd_set::__fds_bits"] [:: std :: mem :: offset_of ! (fd_set , __fds_bits) - 0usize] ; } ; pub type fd_mask = __fd_mask ; unsafe extern "C" { pub fn select (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * mut timeval) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pselect (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * const timespec , __sigmask : * const __sigset_t) -> :: std :: os :: raw :: c_int ; } pub type blksize_t = __blksize_t ; pub type blkcnt_t = __blkcnt_t ; pub type fsblkcnt_t = __fsblkcnt_t ; pub type fsfilcnt_t = __fsfilcnt_t ; # [repr (C)] # [derive (Copy , Clone)] pub union __atomic_wide_counter { pub __value64 : :: std :: os :: raw :: c_ulonglong , pub __value32 : __atomic_wide_counter__bindgen_ty_1 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __atomic_wide_counter__bindgen_ty_1 { pub __low : :: std :: os :: raw :: c_uint , pub __high : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: size_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 8usize] ; ["Alignment of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: align_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__low"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __low) - 0usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__high"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __high) - 4usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter"] [:: std :: mem :: size_of :: < __atomic_wide_counter > () - 8usize] ; ["Alignment of __atomic_wide_counter"] [:: std :: mem :: align_of :: < __atomic_wide_counter > () - 8usize] ; ["Offset of field: __atomic_wide_counter::__value64"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value64) - 0usize] ; ["Offset of field: __atomic_wide_counter::__value32"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value32) - 0usize] ; } ; impl :: std :: fmt :: Debug for __atomic_wide_counter { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__atomic_wide_counter {{ union }}") } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_list { pub __prev : * mut __pthread_internal_list , pub __next : * mut __pthread_internal_list , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_list"] [:: std :: mem :: size_of :: < __pthread_internal_list > () - 16usize] ; ["Alignment of __pthread_internal_list"] [:: std :: mem :: align_of :: < __pthread_internal_list > () - 8usize] ; ["Offset of field: __pthread_internal_list::__prev"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __prev) - 0usize] ; ["Offset of field: __pthread_internal_list::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __next) - 8usize] ; } ; pub type __pthread_list_t = __pthread_internal_list ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_slist { pub __next : * mut __pthread_internal_slist , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_slist"] [:: std :: mem :: size_of :: < __pthread_internal_slist > () - 8usize] ; ["Alignment of __pthread_internal_slist"] [:: std :: mem :: align_of :: < __pthread_internal_slist > () - 8usize] ; ["Offset of field: __pthread_internal_slist::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_slist , __next) - 0usize] ; } ; pub type __pthread_slist_t = __pthread_internal_slist ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_mutex_s { pub __lock : :: std :: os :: raw :: c_int , pub __count : :: std :: os :: raw :: c_uint , pub __owner : :: std :: os :: raw :: c_int , pub __nusers : :: std :: os :: raw :: c_uint , pub __kind : :: std :: os :: raw :: c_int , pub __spins : :: std :: os :: raw :: c_short , pub __unused : :: std :: os :: raw :: c_short , pub __list : __pthread_list_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_mutex_s"] [:: std :: mem :: size_of :: < __pthread_mutex_s > () - 40usize] ; ["Alignment of __pthread_mutex_s"] [:: std :: mem :: align_of :: < __pthread_mutex_s > () - 8usize] ; ["Offset of field: __pthread_mutex_s::__lock"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __lock) - 0usize] ; ["Offset of field: __pthread_mutex_s::__count"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __count) - 4usize] ; ["Offset of field: __pthread_mutex_s::__owner"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __owner) - 8usize] ; ["Offset of field: __pthread_mutex_s::__nusers"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __nusers) - 12usize] ; ["Offset of field: __pthread_mutex_s::__kind"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __kind) - 16usize] ; ["Offset of field: __pthread_mutex_s::__spins"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __spins) - 20usize] ; ["Offset of field: __pthread_mutex_s::__unused"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __unused) - 22usize] ; ["Offset of field: __pthread_mutex_s::__list"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __list) - 24usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_rwlock_arch_t { pub __readers : :: std :: os :: raw :: c_uint , pub __writers : :: std :: os :: raw :: c_uint , pub __wrphase_futex : :: std :: os :: raw :: c_uint , pub __writers_futex : :: std :: os :: raw :: c_uint , pub __pad3 : :: std :: os :: raw :: c_uint , pub __pad4 : :: std :: os :: raw :: c_uint , pub __cur_writer : :: std :: os :: raw :: c_int , pub __shared : :: std :: os :: raw :: c_int , pub __pad1 : :: std :: os :: raw :: c_ulong , pub __pad2 : :: std :: os :: raw :: c_ulong , pub __flags : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_rwlock_arch_t"] [:: std :: mem :: size_of :: < __pthread_rwlock_arch_t > () - 56usize] ; ["Alignment of __pthread_rwlock_arch_t"] [:: std :: mem :: align_of :: < __pthread_rwlock_arch_t > () - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__readers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __readers) - 0usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers) - 4usize] ; ["Offset of field: __pthread_rwlock_arch_t::__wrphase_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __wrphase_futex) - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers_futex) - 12usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad3"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad3) - 16usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad4"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad4) - 20usize] ; ["Offset of field: __pthread_rwlock_arch_t::__cur_writer"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __cur_writer) - 24usize] ; ["Offset of field: __pthread_rwlock_arch_t::__shared"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __shared) - 28usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad1"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad1) - 32usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad2"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad2) - 40usize] ; ["Offset of field: __pthread_rwlock_arch_t::__flags"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __flags) - 48usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct __pthread_cond_s { pub __wseq : __atomic_wide_counter , pub __g1_start : __atomic_wide_counter , pub __g_size : [:: std :: os :: raw :: c_uint ; 2usize] , pub __g1_orig_size : :: std :: os :: raw :: c_uint , pub __wrefs : :: std :: os :: raw :: c_uint , pub __g_signals : [:: std :: os :: raw :: c_uint ; 2usize] , pub __unused_initialized_1 : :: std :: os :: raw :: c_uint , pub __unused_initialized_2 : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_cond_s"] [:: std :: mem :: size_of :: < __pthread_cond_s > () - 48usize] ; ["Alignment of __pthread_cond_s"] [:: std :: mem :: align_of :: < __pthread_cond_s > () - 8usize] ; ["Offset of field: __pthread_cond_s::__wseq"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wseq) - 0usize] ; ["Offset of field: __pthread_cond_s::__g1_start"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_start) - 8usize] ; ["Offset of field: __pthread_cond_s::__g_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_size) - 16usize] ; ["Offset of field: __pthread_cond_s::__g1_orig_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_orig_size) - 24usize] ; ["Offset of field: __pthread_cond_s::__wrefs"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wrefs) - 28usize] ; ["Offset of field: __pthread_cond_s::__g_signals"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_signals) - 32usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_1"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_1) - 40usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_2"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_2) - 44usize] ; } ; impl :: std :: fmt :: Debug for __pthread_cond_s { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__pthread_cond_s {{ __wseq: {:?}, __g1_start: {:?}, __g_size: {:?}, __g1_orig_size: {:?}, __wrefs: {:?}, __g_signals: {:?}, __unused_initialized_1: {:?}, __unused_initialized_2: {:?} }}" , self . __wseq , self . __g1_start , self . __g_size , self . __g1_orig_size , self . __wrefs , self . __g_signals , self . __unused_initialized_1 , self . __unused_initialized_2) } } pub type __tss_t = :: std :: os :: raw :: c_uint ; pub type __thrd_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __once_flag { pub __data : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __once_flag"] [:: std :: mem :: size_of :: < __once_flag > () - 4usize] ; ["Alignment of __once_flag"] [:: std :: mem :: align_of :: < __once_flag > () - 4usize] ; ["Offset of field: __once_flag::__data"] [:: std :: mem :: offset_of ! (__once_flag , __data) - 0usize] ; } ; pub type pthread_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutexattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutexattr_t"] [:: std :: mem :: size_of :: < pthread_mutexattr_t > () - 4usize] ; ["Alignment of pthread_mutexattr_t"] [:: std :: mem :: align_of :: < pthread_mutexattr_t > () - 4usize] ; ["Offset of field: pthread_mutexattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __size) - 0usize] ; ["Offset of field: pthread_mutexattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutexattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutexattr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_condattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_condattr_t"] [:: std :: mem :: size_of :: < pthread_condattr_t > () - 4usize] ; ["Alignment of pthread_condattr_t"] [:: std :: mem :: align_of :: < pthread_condattr_t > () - 4usize] ; ["Offset of field: pthread_condattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __size) - 0usize] ; ["Offset of field: pthread_condattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_condattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_condattr_t {{ union }}") } } pub type pthread_key_t = :: std :: os :: raw :: c_uint ; pub type pthread_once_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_attr_t { pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_attr_t"] [:: std :: mem :: size_of :: < pthread_attr_t > () - 56usize] ; ["Alignment of pthread_attr_t"] [:: std :: mem :: align_of :: < pthread_attr_t > () - 8usize] ; ["Offset of field: pthread_attr_t::__size"] [:: std :: mem :: offset_of ! (pthread_attr_t , __size) - 0usize] ; ["Offset of field: pthread_attr_t::__align"] [:: std :: mem :: offset_of ! (pthread_attr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_attr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_attr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutex_t { pub __data : __pthread_mutex_s , pub __size : [:: std :: os :: raw :: c_char ; 40usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutex_t"] [:: std :: mem :: size_of :: < pthread_mutex_t > () - 40usize] ; ["Alignment of pthread_mutex_t"] [:: std :: mem :: align_of :: < pthread_mutex_t > () - 8usize] ; ["Offset of field: pthread_mutex_t::__data"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __data) - 0usize] ; ["Offset of field: pthread_mutex_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __size) - 0usize] ; ["Offset of field: pthread_mutex_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutex_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutex_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_cond_t { pub __data : __pthread_cond_s , pub __size : [:: std :: os :: raw :: c_char ; 48usize] , pub __align : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_cond_t"] [:: std :: mem :: size_of :: < pthread_cond_t > () - 48usize] ; ["Alignment of pthread_cond_t"] [:: std :: mem :: align_of :: < pthread_cond_t > () - 8usize] ; ["Offset of field: pthread_cond_t::__data"] [:: std :: mem :: offset_of ! (pthread_cond_t , __data) - 0usize] ; ["Offset of field: pthread_cond_t::__size"] [:: std :: mem :: offset_of ! (pthread_cond_t , __size) - 0usize] ; ["Offset of field: pthread_cond_t::__align"] [:: std :: mem :: offset_of ! (pthread_cond_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_cond_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_cond_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlock_t { pub __data : __pthread_rwlock_arch_t , pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlock_t"] [:: std :: mem :: size_of :: < pthread_rwlock_t > () - 56usize] ; ["Alignment of pthread_rwlock_t"] [:: std :: mem :: align_of :: < pthread_rwlock_t > () - 8usize] ; ["Offset of field: pthread_rwlock_t::__data"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __data) - 0usize] ; ["Offset of field: pthread_rwlock_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __size) - 0usize] ; ["Offset of field: pthread_rwlock_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlock_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlock_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlockattr_t { pub __size : [:: std :: os :: raw :: c_char ; 8usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlockattr_t"] [:: std :: mem :: size_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Alignment of pthread_rwlockattr_t"] [:: std :: mem :: align_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Offset of field: pthread_rwlockattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __size) - 0usize] ; ["Offset of field: pthread_rwlockattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlockattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlockattr_t {{ union }}") } } pub type pthread_spinlock_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrier_t { pub __size : [:: std :: os :: raw :: c_char ; 32usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrier_t"] [:: std :: mem :: size_of :: < pthread_barrier_t > () - 32usize] ; ["Alignment of pthread_barrier_t"] [:: std :: mem :: align_of :: < pthread_barrier_t > () - 8usize] ; ["Offset of field: pthread_barrier_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __size) - 0usize] ; ["Offset of field: pthread_barrier_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrier_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrier_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrierattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrierattr_t"] [:: std :: mem :: size_of :: < pthread_barrierattr_t > () - 4usize] ; ["Alignment of pthread_barrierattr_t"] [:: std :: mem :: align_of :: < pthread_barrierattr_t > () - 4usize] ; ["Offset of field: pthread_barrierattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __size) - 0usize] ; ["Offset of field: pthread_barrierattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrierattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrierattr_t {{ union }}") } } unsafe extern "C" { pub fn random () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srandom (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn initstate (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn setstate (__statebuf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct random_data { pub fptr : * mut i32 , pub rptr : * mut i32 , pub state : * mut i32 , pub rand_type : :: std :: os :: raw :: c_int , pub rand_deg : :: std :: os :: raw :: c_int , pub rand_sep : :: std :: os :: raw :: c_int , pub end_ptr : * mut i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of random_data"] [:: std :: mem :: size_of :: < random_data > () - 48usize] ; ["Alignment of random_data"] [:: std :: mem :: align_of :: < random_data > () - 8usize] ; ["Offset of field: random_data::fptr"] [:: std :: mem :: offset_of ! (random_data , fptr) - 0usize] ; ["Offset of field: random_data::rptr"] [:: std :: mem :: offset_of ! (random_data , rptr) - 8usize] ; ["Offset of field: random_data::state"] [:: std :: mem :: offset_of ! (random_data , state) - 16usize] ; ["Offset of field: random_data::rand_type"] [:: std :: mem :: offset_of ! (random_data , rand_type) - 24usize] ; ["Offset of field: random_data::rand_deg"] [:: std :: mem :: offset_of ! (random_data , rand_deg) - 28usize] ; ["Offset of field: random_data::rand_sep"] [:: std :: mem :: offset_of ! (random_data , rand_sep) - 32usize] ; ["Offset of field: random_data::end_ptr"] [:: std :: mem :: offset_of ! (random_data , end_ptr) - 40usize] ; } ; unsafe extern "C" { pub fn random_r (__buf : * mut random_data , __result : * mut i32) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srandom_r (__seed : :: std :: os :: raw :: c_uint , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn initstate_r (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setstate_r (__statebuf : * mut :: std :: os :: raw :: c_char , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rand () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn rand_r (__seed : * mut :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn drand48 () -> f64 ; } unsafe extern "C" { pub fn erand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> f64 ; } unsafe extern "C" { pub fn lrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn nrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn mrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn jrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srand48 (__seedval : :: std :: os :: raw :: c_long) ; } unsafe extern "C" { pub fn seed48 (__seed16v : * mut :: std :: os :: raw :: c_ushort) -> * mut :: std :: os :: raw :: c_ushort ; } unsafe extern "C" { pub fn lcong48 (__param : * mut :: std :: os :: raw :: c_ushort) ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct drand48_data { pub __x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __old_x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __c : :: std :: os :: raw :: c_ushort , pub __init : :: std :: os :: raw :: c_ushort , pub __a : :: std :: os :: raw :: c_ulonglong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of drand48_data"] [:: std :: mem :: size_of :: < drand48_data > () - 24usize] ; ["Alignment of drand48_data"] [:: std :: mem :: align_of :: < drand48_data > () - 8usize] ; ["Offset of field: drand48_data::__x"] [:: std :: mem :: offset_of ! (drand48_data , __x) - 0usize] ; ["Offset of field: drand48_data::__old_x"] [:: std :: mem :: offset_of ! (drand48_data , __old_x) - 6usize] ; ["Offset of field: drand48_data::__c"] [:: std :: mem :: offset_of ! (drand48_data , __c) - 12usize] ; ["Offset of field: drand48_data::__init"] [:: std :: mem :: offset_of ! (drand48_data , __init) - 14usize] ; ["Offset of field: drand48_data::__a"] [:: std :: mem :: offset_of ! (drand48_data , __a) - 16usize] ; } ; unsafe extern "C" { pub fn drand48_r (__buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn erand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn nrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn jrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand48_r (__seedval : :: std :: os :: raw :: c_long , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn seed48_r (__seed16v : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lcong48_r (__param : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn arc4random () -> __uint32_t ; } unsafe extern "C" { pub fn arc4random_buf (__buf : * mut :: std :: os :: raw :: c_void , __size : usize) ; } unsafe extern "C" { pub fn arc4random_uniform (__upper_bound : __uint32_t) -> __uint32_t ; } unsafe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn calloc (__nmemb : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn free (__ptr : * mut :: std :: os :: raw :: c_void) ; } unsafe extern "C" { pub fn reallocarray (__ptr : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn alloca (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn valloc (__size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn posix_memalign (__memptr : * mut * mut :: std :: os :: raw :: c_void , __alignment : usize , __size : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn aligned_alloc (__alignment : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn abort () -> ! ; } unsafe extern "C" { pub fn atexit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn at_quick_exit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn on_exit (__func : :: std :: option :: Option < unsafe extern "C" fn (__status : :: std :: os :: raw :: c_int , __arg : * mut :: std :: os :: raw :: c_void) > , __arg : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn quick_exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn _Exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn getenv (__name : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn putenv (__string : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setenv (__name : * const :: std :: os :: raw :: c_char , __value : * const :: std :: os :: raw :: c_char , __replace : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn unsetenv (__name : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearenv () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mktemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn mkstemp (__template : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkstemps (__template : * mut :: std :: os :: raw :: c_char , __suffixlen : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkdtemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn system (__command : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn realpath (__name : * const :: std :: os :: raw :: c_char , __resolved : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } pub type __compar_fn_t = :: std :: option :: Option < unsafe extern "C" fn (arg1 : * const :: std :: os :: raw :: c_void , arg2 : * const :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; unsafe extern "C" { pub fn bsearch (__key : * const :: std :: os :: raw :: c_void , __base : * const :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn qsort (__base : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) ; } unsafe extern "C" { pub fn abs (__x : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn labs (__x : :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn llabs (__x : :: std :: os :: raw :: c_longlong) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn div (__numer : :: std :: os :: raw :: c_int , __denom : :: std :: os :: raw :: c_int) -> div_t ; } unsafe extern "C" { pub fn ldiv (__numer : :: std :: os :: raw :: c_long , __denom : :: std :: os :: raw :: c_long) -> ldiv_t ; } unsafe extern "C" { pub fn lldiv (__numer : :: std :: os :: raw :: c_longlong , __denom : :: std :: os :: raw :: c_longlong) -> lldiv_t ; } unsafe extern "C" { pub fn ecvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn gcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qecvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qfcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qgcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn ecvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fcvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qecvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qfcvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mblen (__s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbtowc (__pwc : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn wctomb (__s : * mut :: std :: os :: raw :: c_char , __wchar : wchar_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbstowcs (__pwcs : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> usize ; } unsafe extern "C" { pub fn wcstombs (__s : * mut :: std :: os :: raw :: c_char , __pwcs : * const wchar_t , __n : usize) -> usize ; } unsafe extern "C" { pub fn rpmatch (__response : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getsubopt (__optionp : * mut * mut :: std :: os :: raw :: c_char , __tokens : * const * mut :: std :: os :: raw :: c_char , __valuep : * mut * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getloadavg (__loadavg : * mut f64 , __nelem : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } # [repr (C)] # [derive (Copy , Clone)] pub struct __mbstate_t { pub __count : :: std :: os :: raw :: c_int , pub __value : __mbstate_t__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union __mbstate_t__bindgen_ty_1 { pub __wch : :: std :: os :: raw :: c_uint , pub __wchb : [:: std :: os :: raw :: c_char ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: size_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Alignment of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: align_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wch"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wch) - 0usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wchb"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wchb) - 0usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t"] [:: std :: mem :: size_of :: < __mbstate_t > () - 8usize] ; ["Alignment of __mbstate_t"] [:: std :: mem :: align_of :: < __mbstate_t > () - 4usize] ; ["Offset of field: __mbstate_t::__count"] [:: std :: mem :: offset_of ! (__mbstate_t , __count) - 0usize] ; ["Offset of field: __mbstate_t::__value"] [:: std :: mem :: offset_of ! (__mbstate_t , __value) - 4usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t {{ __count: {:?}, __value: {:?} }}" , self . __count , self . __value) } } # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos_t { pub __pos : __off_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos_t"] [:: std :: mem :: size_of :: < _G_fpos_t > () - 16usize] ; ["Alignment of _G_fpos_t"] [:: std :: mem :: align_of :: < _G_fpos_t > () - 8usize] ; ["Offset of field: _G_fpos_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos_t , __pos) - 0usize] ; ["Offset of field: _G_fpos_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos_t = _G_fpos_t ; # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos64_t { pub __pos : __off64_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos64_t"] [:: std :: mem :: size_of :: < _G_fpos64_t > () - 16usize] ; ["Alignment of _G_fpos64_t"] [:: std :: mem :: align_of :: < _G_fpos64_t > () - 8usize] ; ["Offset of field: _G_fpos64_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __pos) - 0usize] ; ["Offset of field: _G_fpos64_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos64_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos64_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos64_t = _G_fpos64_t ; pub type __FILE = _IO_FILE ; pub type FILE = _IO_FILE ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_marker { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_codecvt { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_wide_data { _unused : [u8 ; 0] , } pub type _IO_lock_t = :: std :: os :: raw :: c_void ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_FILE { pub _flags : :: std :: os :: raw :: c_int , pub _IO_read_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_read_end : * mut :: std :: os :: raw :: c_char , pub _IO_read_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_write_end : * mut :: std :: os :: raw :: c_char , pub _IO_buf_base : * mut :: std :: os :: raw :: c_char , pub _IO_buf_end : * mut :: std :: os :: raw :: c_char , pub _IO_save_base : * mut :: std :: os :: raw :: c_char , pub _IO_backup_base : * mut :: std :: os :: raw :: c_char , pub _IO_save_end : * mut :: std :: os :: raw :: c_char , pub _markers : * mut _IO_marker , pub _chain : * mut _IO_FILE , pub _fileno : :: std :: os :: raw :: c_int , pub _bitfield_align_1 : [u32 ; 0] , pub _bitfield_1 : __BindgenBitfieldUnit < [u8 ; 3usize] > , pub _short_backupbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _old_offset : __off_t , pub _cur_column : :: std :: os :: raw :: c_ushort , pub _vtable_offset : :: std :: os :: raw :: c_schar , pub _shortbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _lock : * mut _IO_lock_t , pub _offset : __off64_t , pub _codecvt : * mut _IO_codecvt , pub _wide_data : * mut _IO_wide_data , pub _freeres_list : * mut _IO_FILE , pub _freeres_buf : * mut :: std :: os :: raw :: c_void , pub _prevchain : * mut * mut _IO_FILE , pub _mode : :: std :: os :: raw :: c_int , pub _unused3 : :: std :: os :: raw :: c_int , pub _total_written : __uint64_t , pub _unused2 : [:: std :: os :: raw :: c_char ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_FILE"] [:: std :: mem :: size_of :: < _IO_FILE > () - 216usize] ; ["Alignment of _IO_FILE"] [:: std :: mem :: align_of :: < _IO_FILE > () - 8usize] ; ["Offset of field: _IO_FILE::_flags"] [:: std :: mem :: offset_of ! (_IO_FILE , _flags) - 0usize] ; ["Offset of field: _IO_FILE::_IO_read_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_ptr) - 8usize] ; ["Offset of field: _IO_FILE::_IO_read_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_end) - 16usize] ; ["Offset of field: _IO_FILE::_IO_read_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_base) - 24usize] ; ["Offset of field: _IO_FILE::_IO_write_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_base) - 32usize] ; ["Offset of field: _IO_FILE::_IO_write_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_ptr) - 40usize] ; ["Offset of field: _IO_FILE::_IO_write_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_end) - 48usize] ; ["Offset of field: _IO_FILE::_IO_buf_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_base) - 56usize] ; ["Offset of field: _IO_FILE::_IO_buf_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_end) - 64usize] ; ["Offset of field: _IO_FILE::_IO_save_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_base) - 72usize] ; ["Offset of field: _IO_FILE::_IO_backup_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_backup_base) - 80usize] ; ["Offset of field: _IO_FILE::_IO_save_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_end) - 88usize] ; ["Offset of field: _IO_FILE::_markers"] [:: std :: mem :: offset_of ! (_IO_FILE , _markers) - 96usize] ; ["Offset of field: _IO_FILE::_chain"] [:: std :: mem :: offset_of ! (_IO_FILE , _chain) - 104usize] ; ["Offset of field: _IO_FILE::_fileno"] [:: std :: mem :: offset_of ! (_IO_FILE , _fileno) - 112usize] ; ["Offset of field: _IO_FILE::_short_backupbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _short_backupbuf) - 119usize] ; ["Offset of field: _IO_FILE::_old_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _old_offset) - 120usize] ; ["Offset of field: _IO_FILE::_cur_column"] [:: std :: mem :: offset_of ! (_IO_FILE , _cur_column) - 128usize] ; ["Offset of field: _IO_FILE::_vtable_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _vtable_offset) - 130usize] ; ["Offset of field: _IO_FILE::_shortbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _shortbuf) - 131usize] ; ["Offset of field: _IO_FILE::_lock"] [:: std :: mem :: offset_of ! (_IO_FILE , _lock) - 136usize] ; ["Offset of field: _IO_FILE::_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _offset) - 144usize] ; ["Offset of field: _IO_FILE::_codecvt"] [:: std :: mem :: offset_of ! (_IO_FILE , _codecvt) - 152usize] ; ["Offset of field: _IO_FILE::_wide_data"] [:: std :: mem :: offset_of ! (_IO_FILE , _wide_data) - 160usize] ; ["Offset of field: _IO_FILE::_freeres_list"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_list) - 168usize] ; ["Offset of field: _IO_FILE::_freeres_buf"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_buf) - 176usize] ; ["Offset of field: _IO_FILE::_prevchain"] [:: std :: mem :: offset_of ! (_IO_FILE , _prevchain) - 184usize] ; ["Offset of field: _IO_FILE::_mode"] [:: std :: mem :: offset_of ! (_IO_FILE , _mode) - 192usize] ; ["Offset of field: _IO_FILE::_unused3"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused3) - 196usize] ; ["Offset of field: _IO_FILE::_total_written"] [:: std :: mem :: offset_of ! (_IO_FILE , _total_written) - 200usize] ; ["Offset of field: _IO_FILE::_unused2"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused2) - 208usize] ; } ; impl _IO_FILE { # [inline] pub fn _flags2 (& self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set__flags2 (& mut self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = i32::cast_unsigned (val) ; self . _bitfield_1 . set (0usize , 24u8 , val as u64) } } # [inline] pub unsafe fn _flags2_raw (this : * const Self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } } # [inline] pub unsafe fn set__flags2_raw (this : * mut Self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_set (:: std :: ptr :: addr_of_mut ! ((* this) . _bitfield_1) , 0usize , 24u8 , val as u64 ,) } } # [inline] pub fn new_bitfield_1 (_flags2 : :: std :: os :: raw :: c_int) -> __BindgenBitfieldUnit < [u8 ; 3usize] > { let mut __bindgen_bitfield_unit : __BindgenBitfieldUnit < [u8 ; 3usize] > = Default :: default () ; __bindgen_bitfield_unit . set (0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_unit } } pub type cookie_read_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * mut :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_write_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * const :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_seek_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __pos : * mut __off64_t , __w : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int > ; pub type cookie_close_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_cookie_io_functions_t { pub read : cookie_read_function_t , pub write : cookie_write_function_t , pub seek : cookie_seek_function_t , pub close : cookie_close_function_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_cookie_io_functions_t"] [:: std :: mem :: size_of :: < _IO_cookie_io_functions_t > () - 32usize] ; ["Alignment of _IO_cookie_io_functions_t"] [:: std :: mem :: align_of :: < _IO_cookie_io_functions_t > () - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::read"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , read) - 0usize] ; ["Offset of field: _IO_cookie_io_functions_t::write"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , write) - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::seek"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , seek) - 16usize] ; ["Offset of field: _IO_cookie_io_functions_t::close"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , close) - 24usize] ; } ; pub type cookie_io_functions_t = _IO_cookie_io_functions_t ; pub type fpos_t = __fpos_t ; unsafe extern "C" { pub static mut stdin : * mut FILE ; } unsafe extern "C" { pub static mut stdout : * mut FILE ; } unsafe extern "C" { pub static mut stderr : * mut FILE ; } unsafe extern "C" { pub fn remove (__filename : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rename (__old : * const :: std :: os :: raw :: c_char , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn renameat (__oldfd : :: std :: os :: raw :: c_int , __old : * const :: std :: os :: raw :: c_char , __newfd : :: std :: os :: raw :: c_int , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn tmpfile () -> * mut FILE ; } unsafe extern "C" { pub fn tmpnam (arg1 : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tmpnam_r (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tempnam (__dir : * const :: std :: os :: raw :: c_char , __pfx : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fflush (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fflush_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn freopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> * mut FILE ; } unsafe extern "C" { pub fn fdopen (__fd : :: std :: os :: raw :: c_int , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn fopencookie (__magic_cookie : * mut :: std :: os :: raw :: c_void , __modes : * const :: std :: os :: raw :: c_char , __io_funcs : cookie_io_functions_t) -> * mut FILE ; } unsafe extern "C" { pub fn fmemopen (__s : * mut :: std :: os :: raw :: c_void , __len : usize , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn open_memstream (__bufloc : * mut * mut :: std :: os :: raw :: c_char , __sizeloc : * mut usize) -> * mut FILE ; } unsafe extern "C" { pub fn setbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn setvbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __modes : :: std :: os :: raw :: c_int , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setbuffer (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __size : usize) ; } unsafe extern "C" { pub fn setlinebuf (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fprintf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn printf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfprintf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vprintf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn snprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsnprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vasprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __f : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vdprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn dprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fscanf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn scanf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_fscanf"] pub fn fscanf1 (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_scanf"] pub fn scanf1 (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_sscanf"] pub fn sscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfscanf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vscanf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vfscanf"] pub fn vfscanf1 (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vscanf"] pub fn vscanf1 (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vsscanf"] pub fn vsscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar_unlocked () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar_unlocked (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getw (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putw (__w : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgets (__s : * mut :: std :: os :: raw :: c_char , __n : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn __getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getline (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn fputs (__s : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn puts (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ungetc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fread (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __stream : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fwrite (__ptr : * const :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __s : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fread_unlocked (__ptr : * mut :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fwrite_unlocked (__ptr : * const :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fseek (__stream : * mut FILE , __off : :: std :: os :: raw :: c_long , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftell (__stream : * mut FILE) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn rewind (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fseeko (__stream : * mut FILE , __off : __off_t , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftello (__stream : * mut FILE) -> __off_t ; } unsafe extern "C" { pub fn fgetpos (__stream : * mut FILE , __pos : * mut fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fsetpos (__stream : * mut FILE , __pos : * const fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr_unlocked (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn perror (__s : * const :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn fileno (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fileno_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn popen (__command : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn ctermid (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn flockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn ftrylockfile (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn funlockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn __uflow (arg1 : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __overflow (arg1 : * mut FILE , arg2 : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } pub type int_least8_t = __int_least8_t ; pub type int_least16_t = __int_least16_t ; pub type int_least32_t = __int_least32_t ; pub type int_least64_t = __int_least64_t ; pub type uint_least8_t = __uint_least8_t ; pub type uint_least16_t = __uint_least16_t ; pub type uint_least32_t = __uint_least32_t ; pub type uint_least64_t = __uint_least64_t ; pub type int_fast8_t = :: std :: os :: raw :: c_schar ; pub type int_fast16_t = :: std :: os :: raw :: c_long ; pub type int_fast32_t = :: std :: os :: raw :: c_long ; pub type int_fast64_t = :: std :: os :: raw :: c_long ; pub type uint_fast8_t = :: std :: os :: raw :: c_uchar ; pub type uint_fast16_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast32_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast64_t = :: std :: os :: raw :: c_ulong ; pub type intmax_t = __intmax_t ; pub type uintmax_t = __uintmax_t ; pub type __gwchar_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct imaxdiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of imaxdiv_t"] [:: std :: mem :: size_of :: < imaxdiv_t > () - 16usize] ; ["Alignment of imaxdiv_t"] [:: std :: mem :: align_of :: < imaxdiv_t > () - 8usize] ; ["Offset of field: imaxdiv_t::quot"] [:: std :: mem :: offset_of ! (imaxdiv_t , quot) - 0usize] ; ["Offset of field: imaxdiv_t::rem"] [:: std :: mem :: offset_of ! (imaxdiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn imaxabs (__n : intmax_t) -> intmax_t ; } unsafe extern "C" { pub fn imaxdiv (__numer : intmax_t , __denom : intmax_t) -> imaxdiv_t ; } unsafe extern "C" { pub fn strtoimax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn strtoumax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } unsafe extern "C" { pub fn wcstoimax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn wcstoumax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } pub type csh = usize ; # [repr (u32)] # [doc = " Architecture type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_arch { # [doc = "< ARM architecture (including Thumb, Thumb-2)"] CS_ARCH_ARM = 0 , # [doc = "< ARM-64, also called AArch64"] CS_ARCH_ARM64 = 1 , # [doc = "< Mips architecture"] CS_ARCH_MIPS = 2 , # [doc = "< X86 architecture (including x86 & x86-64)"] CS_ARCH_X86 = 3 , # [doc = "< PowerPC architecture"] CS_ARCH_PPC = 4 , # [doc = "< Sparc architecture"] CS_ARCH_SPARC = 5 , # [doc = "< SystemZ architecture"] CS_ARCH_SYSZ = 6 , # [doc = "< XCore architecture"] CS_ARCH_XCORE = 7 , # [doc = "< 68K architecture"] CS_ARCH_M68K = 8 , # [doc = "< TMS320C64x architecture"] CS_ARCH_TMS320C64X = 9 , # [doc = "< 680X architecture"] CS_ARCH_M680X = 10 , # [doc = "< Ethereum architecture"] CS_ARCH_EVM = 11 , # [doc = "< MOS65XX architecture (including MOS6502)"] CS_ARCH_MOS65XX = 12 , # [doc = "< WebAssembly architecture"] CS_ARCH_WASM = 13 , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] CS_ARCH_BPF = 14 , # [doc = "< RISCV architecture"] CS_ARCH_RISCV = 15 , # [doc = "< SH architecture"] CS_ARCH_SH = 16 , # [doc = "< TriCore architecture"] CS_ARCH_TRICORE = 17 , CS_ARCH_MAX = 18 , CS_ARCH_ALL = 65535 , } # [doc = "< little-endian mode (default mode)"] pub const cs_mode_CS_MODE_LITTLE_ENDIAN : cs_mode = 0 ; # [doc = "< 32-bit ARM"] pub const cs_mode_CS_MODE_ARM : cs_mode = 0 ; # [doc = "< 16-bit mode (X86)"] pub const cs_mode_CS_MODE_16 : cs_mode = 2 ; # [doc = "< 32-bit mode (X86)"] pub const cs_mode_CS_MODE_32 : cs_mode = 4 ; # [doc = "< 64-bit mode (X86, PPC)"] pub const cs_mode_CS_MODE_64 : cs_mode = 8 ; # [doc = "< ARM's Thumb mode, including Thumb-2"] pub const cs_mode_CS_MODE_THUMB : cs_mode = 16 ; # [doc = "< ARM's Cortex-M series"] pub const cs_mode_CS_MODE_MCLASS : cs_mode = 32 ; # [doc = "< ARMv8 A32 encodings for ARM"] pub const cs_mode_CS_MODE_V8 : cs_mode = 64 ; # [doc = "< MicroMips mode (MIPS)"] pub const cs_mode_CS_MODE_MICRO : cs_mode = 16 ; # [doc = "< Mips III ISA"] pub const cs_mode_CS_MODE_MIPS3 : cs_mode = 32 ; # [doc = "< Mips32r6 ISA"] pub const cs_mode_CS_MODE_MIPS32R6 : cs_mode = 64 ; # [doc = "< Mips II ISA"] pub const cs_mode_CS_MODE_MIPS2 : cs_mode = 128 ; # [doc = "< SparcV9 mode (Sparc)"] pub const cs_mode_CS_MODE_V9 : cs_mode = 16 ; # [doc = "< Quad Processing eXtensions mode (PPC)"] pub const cs_mode_CS_MODE_QPX : cs_mode = 16 ; # [doc = "< Signal Processing Engine mode (PPC)"] pub const cs_mode_CS_MODE_SPE : cs_mode = 32 ; # [doc = "< Book-E mode (PPC)"] pub const cs_mode_CS_MODE_BOOKE : cs_mode = 64 ; # [doc = "< Paired-singles mode (PPC)"] pub const cs_mode_CS_MODE_PS : cs_mode = 128 ; # [doc = "< M68K 68000 mode"] pub const cs_mode_CS_MODE_M68K_000 : cs_mode = 2 ; # [doc = "< M68K 68010 mode"] pub const cs_mode_CS_MODE_M68K_010 : cs_mode = 4 ; # [doc = "< M68K 68020 mode"] pub const cs_mode_CS_MODE_M68K_020 : cs_mode = 8 ; # [doc = "< M68K 68030 mode"] pub const cs_mode_CS_MODE_M68K_030 : cs_mode = 16 ; # [doc = "< M68K 68040 mode"] pub const cs_mode_CS_MODE_M68K_040 : cs_mode = 32 ; # [doc = "< M68K 68060 mode"] pub const cs_mode_CS_MODE_M68K_060 : cs_mode = 64 ; # [doc = "< big-endian mode"] pub const cs_mode_CS_MODE_BIG_ENDIAN : cs_mode = 2147483648 ; # [doc = "< Mips32 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS32 : cs_mode = 4 ; # [doc = "< Mips64 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS64 : cs_mode = 8 ; # [doc = "< M680X Hitachi 6301,6303 mode"] pub const cs_mode_CS_MODE_M680X_6301 : cs_mode = 2 ; # [doc = "< M680X Hitachi 6309 mode"] pub const cs_mode_CS_MODE_M680X_6309 : cs_mode = 4 ; # [doc = "< M680X Motorola 6800,6802 mode"] pub const cs_mode_CS_MODE_M680X_6800 : cs_mode = 8 ; # [doc = "< M680X Motorola 6801,6803 mode"] pub const cs_mode_CS_MODE_M680X_6801 : cs_mode = 16 ; # [doc = "< M680X Motorola/Freescale 6805 mode"] pub const cs_mode_CS_MODE_M680X_6805 : cs_mode = 32 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"] pub const cs_mode_CS_MODE_M680X_6808 : cs_mode = 64 ; # [doc = "< M680X Motorola 6809 mode"] pub const cs_mode_CS_MODE_M680X_6809 : cs_mode = 128 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"] pub const cs_mode_CS_MODE_M680X_6811 : cs_mode = 256 ; # [doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"] pub const cs_mode_CS_MODE_M680X_CPU12 : cs_mode = 512 ; # [doc = "< M680X Freescale/NXP HCS08 mode"] pub const cs_mode_CS_MODE_M680X_HCS08 : cs_mode = 1024 ; # [doc = "< Classic BPF mode (default)"] pub const cs_mode_CS_MODE_BPF_CLASSIC : cs_mode = 0 ; # [doc = "< Extended BPF mode"] pub const cs_mode_CS_MODE_BPF_EXTENDED : cs_mode = 1 ; # [doc = "< RISCV RV32G"] pub const cs_mode_CS_MODE_RISCV32 : cs_mode = 1 ; # [doc = "< RISCV RV64G"] pub const cs_mode_CS_MODE_RISCV64 : cs_mode = 2 ; # [doc = "< RISCV compressed instructure mode"] pub const cs_mode_CS_MODE_RISCVC : cs_mode = 4 ; # [doc = "< MOS65XXX MOS 6502"] pub const cs_mode_CS_MODE_MOS65XX_6502 : cs_mode = 2 ; # [doc = "< MOS65XXX WDC 65c02"] pub const cs_mode_CS_MODE_MOS65XX_65C02 : cs_mode = 4 ; # [doc = "< MOS65XXX WDC W65c02"] pub const cs_mode_CS_MODE_MOS65XX_W65C02 : cs_mode = 8 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m/x"] pub const cs_mode_CS_MODE_MOS65XX_65816 : cs_mode = 16 ; # [doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_M : cs_mode = 32 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_X : cs_mode = 64 ; pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_MX : cs_mode = 96 ; # [doc = "< SH2"] pub const cs_mode_CS_MODE_SH2 : cs_mode = 2 ; # [doc = "< SH2A"] pub const cs_mode_CS_MODE_SH2A : cs_mode = 4 ; # [doc = "< SH3"] pub const cs_mode_CS_MODE_SH3 : cs_mode = 8 ; # [doc = "< SH4"] pub const cs_mode_CS_MODE_SH4 : cs_mode = 16 ; # [doc = "< SH4A"] pub const cs_mode_CS_MODE_SH4A : cs_mode = 32 ; # [doc = "< w/ FPU"] pub const cs_mode_CS_MODE_SHFPU : cs_mode = 64 ; # [doc = "< w/ DSP"] pub const cs_mode_CS_MODE_SHDSP : cs_mode = 128 ; # [doc = "< Tricore 1.1"] pub const cs_mode_CS_MODE_TRICORE_110 : cs_mode = 2 ; # [doc = "< Tricore 1.2"] pub const cs_mode_CS_MODE_TRICORE_120 : cs_mode = 4 ; # [doc = "< Tricore 1.3"] pub const cs_mode_CS_MODE_TRICORE_130 : cs_mode = 8 ; # [doc = "< Tricore 1.3.1"] pub const cs_mode_CS_MODE_TRICORE_131 : cs_mode = 16 ; # [doc = "< Tricore 1.6"] pub const cs_mode_CS_MODE_TRICORE_160 : cs_mode = 32 ; # [doc = "< Tricore 1.6.1"] pub const cs_mode_CS_MODE_TRICORE_161 : cs_mode = 64 ; # [doc = "< Tricore 1.6.2"] pub const cs_mode_CS_MODE_TRICORE_162 : cs_mode = 128 ; # [doc = " Mode type"] pub type cs_mode = :: std :: os :: raw :: c_uint ; pub type cs_malloc_t = :: std :: option :: Option < unsafe extern "C" fn (size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_calloc_t = :: std :: option :: Option < unsafe extern "C" fn (nmemb : usize , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_realloc_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_free_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void) > ; pub type cs_vsnprintf_t = :: std :: option :: Option < unsafe extern "C" fn (str_ : * mut :: std :: os :: raw :: c_char , size : usize , format : * const :: std :: os :: raw :: c_char , ap : * mut __va_list_tag) -> :: std :: os :: raw :: c_int > ; # [doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mem { pub malloc : cs_malloc_t , pub calloc : cs_calloc_t , pub realloc : cs_realloc_t , pub free : cs_free_t , pub vsnprintf : cs_vsnprintf_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mem"] [:: std :: mem :: size_of :: < cs_opt_mem > () - 40usize] ; ["Alignment of cs_opt_mem"] [:: std :: mem :: align_of :: < cs_opt_mem > () - 8usize] ; ["Offset of field: cs_opt_mem::malloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , malloc) - 0usize] ; ["Offset of field: cs_opt_mem::calloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , calloc) - 8usize] ; ["Offset of field: cs_opt_mem::realloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , realloc) - 16usize] ; ["Offset of field: cs_opt_mem::free"] [:: std :: mem :: offset_of ! (cs_opt_mem , free) - 24usize] ; ["Offset of field: cs_opt_mem::vsnprintf"] [:: std :: mem :: offset_of ! (cs_opt_mem , vsnprintf) - 32usize] ; } ; # [doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mnem { # [doc = " ID of instruction to be customized."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Customized instruction mnemonic."] pub mnemonic : * const :: std :: os :: raw :: c_char , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mnem"] [:: std :: mem :: size_of :: < cs_opt_mnem > () - 16usize] ; ["Alignment of cs_opt_mnem"] [:: std :: mem :: align_of :: < cs_opt_mnem > () - 8usize] ; ["Offset of field: cs_opt_mnem::id"] [:: std :: mem :: offset_of ! (cs_opt_mnem , id) - 0usize] ; ["Offset of field: cs_opt_mnem::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_mnem , mnemonic) - 8usize] ; } ; # [repr (u32)] # [doc = " Runtime option for the disassembled engine"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_type { # [doc = "< No option specified"] CS_OPT_INVALID = 0 , # [doc = "< Assembly output syntax"] CS_OPT_SYNTAX = 1 , # [doc = "< Break down instruction structure into details"] CS_OPT_DETAIL = 2 , # [doc = "< Change engine's mode at run-time"] CS_OPT_MODE = 3 , # [doc = "< User-defined dynamic memory related functions"] CS_OPT_MEM = 4 , # [doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."] CS_OPT_SKIPDATA = 5 , # [doc = "< Setup user-defined function for SKIPDATA option"] CS_OPT_SKIPDATA_SETUP = 6 , # [doc = "< Customize instruction mnemonic"] CS_OPT_MNEMONIC = 7 , # [doc = "< print immediate operands in unsigned form"] CS_OPT_UNSIGNED = 8 , # [doc = "< ARM, prints branch immediates without offset."] CS_OPT_NO_BRANCH_OFFSET = 9 , } impl cs_opt_value { pub const CS_OPT_SYNTAX_DEFAULT : cs_opt_value = cs_opt_value :: CS_OPT_OFF ; } impl cs_opt_value { pub const CS_OPT_SYNTAX_NOREGNAME : cs_opt_value = cs_opt_value :: CS_OPT_ON ; } # [repr (u32)] # [doc = " Runtime option value (associated with option type above)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_value { # [doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."] CS_OPT_OFF = 0 , # [doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."] CS_OPT_ON = 3 , # [doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_INTEL = 1 , # [doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_ATT = 2 , # [doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_MASM = 4 , # [doc = "< MOS65XX use $ as hex prefix"] CS_OPT_SYNTAX_MOTOROLA = 5 , } # [repr (u32)] # [doc = " Common instruction operand types - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_op_type { # [doc = "< uninitialized/invalid operand."] CS_OP_INVALID = 0 , # [doc = "< Register operand."] CS_OP_REG = 1 , # [doc = "< Immediate operand."] CS_OP_IMM = 2 , # [doc = "< Memory operand. Can be ORed with another operand type."] CS_OP_MEM = 3 , # [doc = "< Floating-Point operand."] CS_OP_FP = 4 , } # [repr (u32)] # [doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_ac_type { # [doc = "< Uninitialized/invalid access type."] CS_AC_INVALID = 0 , # [doc = "< Operand read from memory or register."] CS_AC_READ = 1 , # [doc = "< Operand write to memory or register."] CS_AC_WRITE = 2 , } # [repr (u32)] # [doc = " Common instruction groups - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_group_type { # [doc = "< uninitialized/invalid group."] CS_GRP_INVALID = 0 , # [doc = "< all jump instructions (conditional+direct+indirect jumps)"] CS_GRP_JUMP = 1 , # [doc = "< all call instructions"] CS_GRP_CALL = 2 , # [doc = "< all return instructions"] CS_GRP_RET = 3 , # [doc = "< all interrupt instructions (int+syscall)"] CS_GRP_INT = 4 , # [doc = "< all interrupt return instructions"] CS_GRP_IRET = 5 , # [doc = "< all privileged instructions"] CS_GRP_PRIVILEGE = 6 , # [doc = "< all relative branching instructions"] CS_GRP_BRANCH_RELATIVE = 7 , } # [doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."] pub type cs_skipdata_cb_t = :: std :: option :: Option < unsafe extern "C" fn (code : * const u8 , code_size : usize , offset : usize , user_data : * mut :: std :: os :: raw :: c_void) -> usize > ; # [doc = " User-customized setup for SKIPDATA option"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_skipdata { # [doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."] pub mnemonic : * const :: std :: os :: raw :: c_char , # [doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes.\n TriCore: 2 bytes."] pub callback : cs_skipdata_cb_t , # [doc = " User-defined data to be passed to @callback function pointer."] pub user_data : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_skipdata"] [:: std :: mem :: size_of :: < cs_opt_skipdata > () - 24usize] ; ["Alignment of cs_opt_skipdata"] [:: std :: mem :: align_of :: < cs_opt_skipdata > () - 8usize] ; ["Offset of field: cs_opt_skipdata::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , mnemonic) - 0usize] ; ["Offset of field: cs_opt_skipdata::callback"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , callback) - 8usize] ; ["Offset of field: cs_opt_skipdata::user_data"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , user_data) - 16usize] ; } ; # [repr (u32)] # [doc = " ARM shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_shifter { ARM_SFT_INVALID = 0 , # [doc = "< shift with immediate const"] ARM_SFT_ASR = 1 , # [doc = "< shift with immediate const"] ARM_SFT_LSL = 2 , # [doc = "< shift with immediate const"] ARM_SFT_LSR = 3 , # [doc = "< shift with immediate const"] ARM_SFT_ROR = 4 , # [doc = "< shift with immediate const"] ARM_SFT_RRX = 5 , # [doc = "< shift with register"] ARM_SFT_ASR_REG = 6 , # [doc = "< shift with register"] ARM_SFT_LSL_REG = 7 , # [doc = "< shift with register"] ARM_SFT_LSR_REG = 8 , # [doc = "< shift with register"] ARM_SFT_ROR_REG = 9 , # [doc = "< shift with register"] ARM_SFT_RRX_REG = 10 , } # [repr (u32)] # [doc = " ARM condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cc { ARM_CC_INVALID = 0 , # [doc = "< Equal                      Equal"] ARM_CC_EQ = 1 , # [doc = "< Not equal                  Not equal, or unordered"] ARM_CC_NE = 2 , # [doc = "< Carry set                  >, ==, or unordered"] ARM_CC_HS = 3 , # [doc = "< Carry clear                Less than"] ARM_CC_LO = 4 , # [doc = "< Minus, negative            Less than"] ARM_CC_MI = 5 , # [doc = "< Plus, positive or zero     >, ==, or unordered"] ARM_CC_PL = 6 , # [doc = "< Overflow                   Unordered"] ARM_CC_VS = 7 , # [doc = "< No overflow                Not unordered"] ARM_CC_VC = 8 , # [doc = "< Unsigned higher            Greater than, or unordered"] ARM_CC_HI = 9 , # [doc = "< Unsigned lower or same     Less than or equal"] ARM_CC_LS = 10 , # [doc = "< Greater than or equal      Greater than or equal"] ARM_CC_GE = 11 , # [doc = "< Less than                  Less than, or unordered"] ARM_CC_LT = 12 , # [doc = "< Greater than               Greater than"] ARM_CC_GT = 13 , # [doc = "< Less than or equal         <, ==, or unordered"] ARM_CC_LE = 14 , # [doc = "< Always (unconditional)     Always (unconditional)"] ARM_CC_AL = 15 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_sysreg { # [doc = " Special registers for MSR"] ARM_SYSREG_INVALID = 0 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_C = 1 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_X = 2 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_S = 4 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_F = 8 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_C = 16 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_X = 32 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_S = 64 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_F = 128 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR = 256 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_G = 257 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQ = 258 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQG = 259 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR = 260 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_G = 261 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQG = 262 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQ = 263 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR = 264 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_G = 265 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQG = 266 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQ = 267 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR = 268 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_G = 269 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQG = 270 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQ = 271 , # [doc = " Special registers for MSR"] ARM_SYSREG_IPSR = 272 , # [doc = " Special registers for MSR"] ARM_SYSREG_EPSR = 273 , # [doc = " Special registers for MSR"] ARM_SYSREG_IEPSR = 274 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP = 275 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP = 276 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK = 277 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI = 278 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_MAX = 279 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK = 280 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL = 281 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM = 282 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM = 283 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP_NS = 284 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP_NS = 285 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM_NS = 286 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM_NS = 287 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK_NS = 288 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_NS = 289 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK_NS = 290 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL_NS = 291 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_NS = 292 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_USR = 293 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_USR = 294 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_USR = 295 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_USR = 296 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_USR = 297 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_USR = 298 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_USR = 299 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_FIQ = 300 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_FIQ = 301 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_FIQ = 302 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_FIQ = 303 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_FIQ = 304 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_FIQ = 305 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_FIQ = 306 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_IRQ = 307 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_IRQ = 308 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_SVC = 309 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_SVC = 310 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_ABT = 311 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_ABT = 312 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_UND = 313 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_UND = 314 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_MON = 315 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_MON = 316 , # [doc = " Special registers for MSR"] ARM_SYSREG_ELR_HYP = 317 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_HYP = 318 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_FIQ = 319 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_IRQ = 320 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_SVC = 321 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_ABT = 322 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_UND = 323 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_MON = 324 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_HYP = 325 , } # [repr (u32)] # [doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_mem_barrier { ARM_MB_INVALID = 0 , ARM_MB_RESERVED_0 = 1 , ARM_MB_OSHLD = 2 , ARM_MB_OSHST = 3 , ARM_MB_OSH = 4 , ARM_MB_RESERVED_4 = 5 , ARM_MB_NSHLD = 6 , ARM_MB_NSHST = 7 , ARM_MB_NSH = 8 , ARM_MB_RESERVED_8 = 9 , ARM_MB_ISHLD = 10 , ARM_MB_ISHST = 11 , ARM_MB_ISH = 12 , ARM_MB_RESERVED_12 = 13 , ARM_MB_LD = 14 , ARM_MB_ST = 15 , ARM_MB_SY = 16 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM_OP_FP = 4 , # [doc = "< C-Immediate (coprocessor registers)"] ARM_OP_CIMM = 64 , # [doc = "< P-Immediate (coprocessor registers)"] ARM_OP_PIMM = 65 , # [doc = "< operand for SETEND instruction"] ARM_OP_SETEND = 66 , # [doc = "< MSR/MRS special register operand"] ARM_OP_SYSREG = 67 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_setend_type { # [doc = "< Uninitialized."] ARM_SETEND_INVALID = 0 , # [doc = "< BE operand."] ARM_SETEND_BE = 1 , # [doc = "< LE operand"] ARM_SETEND_LE = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0 , ARM_CPSMODE_IE = 2 , ARM_CPSMODE_ID = 3 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0 , ARM_CPSFLAG_F = 1 , ARM_CPSFLAG_I = 2 , ARM_CPSFLAG_A = 4 , # [doc = "< no flag"] ARM_CPSFLAG_NONE = 16 , } # [repr (u32)] # [doc = " Data type for elements of vector instructions."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0 , ARM_VECTORDATA_I8 = 1 , ARM_VECTORDATA_I16 = 2 , ARM_VECTORDATA_I32 = 3 , ARM_VECTORDATA_I64 = 4 , ARM_VECTORDATA_S8 = 5 , ARM_VECTORDATA_S16 = 6 , ARM_VECTORDATA_S32 = 7 , ARM_VECTORDATA_S64 = 8 , ARM_VECTORDATA_U8 = 9 , ARM_VECTORDATA_U16 = 10 , ARM_VECTORDATA_U32 = 11 , ARM_VECTORDATA_U64 = 12 , ARM_VECTORDATA_P8 = 13 , ARM_VECTORDATA_F16 = 14 , ARM_VECTORDATA_F32 = 15 , ARM_VECTORDATA_F64 = 16 , ARM_VECTORDATA_F16F64 = 17 , ARM_VECTORDATA_F64F16 = 18 , ARM_VECTORDATA_F32F16 = 19 , ARM_VECTORDATA_F16F32 = 20 , ARM_VECTORDATA_F64F32 = 21 , ARM_VECTORDATA_F32F64 = 22 , ARM_VECTORDATA_S32F32 = 23 , ARM_VECTORDATA_U32F32 = 24 , ARM_VECTORDATA_F32S32 = 25 , ARM_VECTORDATA_F32U32 = 26 , ARM_VECTORDATA_F64S16 = 27 , ARM_VECTORDATA_F32S16 = 28 , ARM_VECTORDATA_F64S32 = 29 , ARM_VECTORDATA_S16F64 = 30 , ARM_VECTORDATA_S16F32 = 31 , ARM_VECTORDATA_S32F64 = 32 , ARM_VECTORDATA_U16F64 = 33 , ARM_VECTORDATA_U16F32 = 34 , ARM_VECTORDATA_U32F64 = 35 , ARM_VECTORDATA_F64U16 = 36 , ARM_VECTORDATA_F32U16 = 37 , ARM_VECTORDATA_F64U32 = 38 , ARM_VECTORDATA_F16U16 = 39 , ARM_VECTORDATA_U16F16 = 40 , ARM_VECTORDATA_F16U32 = 41 , ARM_VECTORDATA_U32F16 = 42 , } impl arm_reg { pub const ARM_REG_R13 : arm_reg = arm_reg :: ARM_REG_SP ; } impl arm_reg { pub const ARM_REG_R14 : arm_reg = arm_reg :: ARM_REG_LR ; } impl arm_reg { pub const ARM_REG_R15 : arm_reg = arm_reg :: ARM_REG_PC ; } impl arm_reg { pub const ARM_REG_SB : arm_reg = arm_reg :: ARM_REG_R9 ; } impl arm_reg { pub const ARM_REG_SL : arm_reg = arm_reg :: ARM_REG_R10 ; } impl arm_reg { pub const ARM_REG_FP : arm_reg = arm_reg :: ARM_REG_R11 ; } impl arm_reg { pub const ARM_REG_IP : arm_reg = arm_reg :: ARM_REG_R12 ; } # [repr (u32)] # [doc = " ARM registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_reg { ARM_REG_INVALID = 0 , ARM_REG_APSR = 1 , ARM_REG_APSR_NZCV = 2 , ARM_REG_CPSR = 3 , ARM_REG_FPEXC = 4 , ARM_REG_FPINST = 5 , ARM_REG_FPSCR = 6 , ARM_REG_FPSCR_NZCV = 7 , ARM_REG_FPSID = 8 , ARM_REG_ITSTATE = 9 , ARM_REG_LR = 10 , ARM_REG_PC = 11 , ARM_REG_SP = 12 , ARM_REG_SPSR = 13 , ARM_REG_D0 = 14 , ARM_REG_D1 = 15 , ARM_REG_D2 = 16 , ARM_REG_D3 = 17 , ARM_REG_D4 = 18 , ARM_REG_D5 = 19 , ARM_REG_D6 = 20 , ARM_REG_D7 = 21 , ARM_REG_D8 = 22 , ARM_REG_D9 = 23 , ARM_REG_D10 = 24 , ARM_REG_D11 = 25 , ARM_REG_D12 = 26 , ARM_REG_D13 = 27 , ARM_REG_D14 = 28 , ARM_REG_D15 = 29 , ARM_REG_D16 = 30 , ARM_REG_D17 = 31 , ARM_REG_D18 = 32 , ARM_REG_D19 = 33 , ARM_REG_D20 = 34 , ARM_REG_D21 = 35 , ARM_REG_D22 = 36 , ARM_REG_D23 = 37 , ARM_REG_D24 = 38 , ARM_REG_D25 = 39 , ARM_REG_D26 = 40 , ARM_REG_D27 = 41 , ARM_REG_D28 = 42 , ARM_REG_D29 = 43 , ARM_REG_D30 = 44 , ARM_REG_D31 = 45 , ARM_REG_FPINST2 = 46 , ARM_REG_MVFR0 = 47 , ARM_REG_MVFR1 = 48 , ARM_REG_MVFR2 = 49 , ARM_REG_Q0 = 50 , ARM_REG_Q1 = 51 , ARM_REG_Q2 = 52 , ARM_REG_Q3 = 53 , ARM_REG_Q4 = 54 , ARM_REG_Q5 = 55 , ARM_REG_Q6 = 56 , ARM_REG_Q7 = 57 , ARM_REG_Q8 = 58 , ARM_REG_Q9 = 59 , ARM_REG_Q10 = 60 , ARM_REG_Q11 = 61 , ARM_REG_Q12 = 62 , ARM_REG_Q13 = 63 , ARM_REG_Q14 = 64 , ARM_REG_Q15 = 65 , ARM_REG_R0 = 66 , ARM_REG_R1 = 67 , ARM_REG_R2 = 68 , ARM_REG_R3 = 69 , ARM_REG_R4 = 70 , ARM_REG_R5 = 71 , ARM_REG_R6 = 72 , ARM_REG_R7 = 73 , ARM_REG_R8 = 74 , ARM_REG_R9 = 75 , ARM_REG_R10 = 76 , ARM_REG_R11 = 77 , ARM_REG_R12 = 78 , ARM_REG_S0 = 79 , ARM_REG_S1 = 80 , ARM_REG_S2 = 81 , ARM_REG_S3 = 82 , ARM_REG_S4 = 83 , ARM_REG_S5 = 84 , ARM_REG_S6 = 85 , ARM_REG_S7 = 86 , ARM_REG_S8 = 87 , ARM_REG_S9 = 88 , ARM_REG_S10 = 89 , ARM_REG_S11 = 90 , ARM_REG_S12 = 91 , ARM_REG_S13 = 92 , ARM_REG_S14 = 93 , ARM_REG_S15 = 94 , ARM_REG_S16 = 95 , ARM_REG_S17 = 96 , ARM_REG_S18 = 97 , ARM_REG_S19 = 98 , ARM_REG_S20 = 99 , ARM_REG_S21 = 100 , ARM_REG_S22 = 101 , ARM_REG_S23 = 102 , ARM_REG_S24 = 103 , ARM_REG_S25 = 104 , ARM_REG_S26 = 105 , ARM_REG_S27 = 106 , ARM_REG_S28 = 107 , ARM_REG_S29 = 108 , ARM_REG_S30 = 109 , ARM_REG_S31 = 110 , ARM_REG_ENDING = 111 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm_op_mem { # [doc = "< base register"] pub base : arm_reg , # [doc = "< index register"] pub index : arm_reg , # [doc = "< scale for index register (can be 1, or -1)"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_int , # [doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"] pub lshift : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm_op_mem"] [:: std :: mem :: size_of :: < arm_op_mem > () - 20usize] ; ["Alignment of arm_op_mem"] [:: std :: mem :: align_of :: < arm_op_mem > () - 4usize] ; ["Offset of field: arm_op_mem::base"] [:: std :: mem :: offset_of ! (arm_op_mem , base) - 0usize] ; ["Offset of field: arm_op_mem::index"] [:: std :: mem :: offset_of ! (arm_op_mem , index) - 4usize] ; ["Offset of field: arm_op_mem::scale"] [:: std :: mem :: offset_of ! (arm_op_mem , scale) - 8usize] ; ["Offset of field: arm_op_mem::disp"] [:: std :: mem :: offset_of ! (arm_op_mem , disp) - 12usize] ; ["Offset of field: arm_op_mem::lshift"] [:: std :: mem :: offset_of ! (arm_op_mem , lshift) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm_op { # [doc = "< Vector Index for some vector operands (or -1 if irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , pub shift : cs_arm_op__bindgen_ty_1 , # [doc = "< operand type"] pub type_ : arm_op_type , pub __bindgen_anon_1 : cs_arm_op__bindgen_ty_2 , # [doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."] pub subtracted : bool , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"] pub neon_lane : i8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm_op__bindgen_ty_1 { pub type_ : arm_shifter , pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm_op__bindgen_ty_2 { # [doc = "< register value for REG/SYSREG operand"] pub reg : :: std :: os :: raw :: c_int , # [doc = "< immediate value for C-IMM, P-IMM or IMM operand"] pub imm : i32 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm_op_mem , # [doc = "< SETEND instruction's operand type"] pub setend : arm_setend_type , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_2 > () - 24usize] ; ["Alignment of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::setend"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , setend) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op"] [:: std :: mem :: size_of :: < cs_arm_op > () - 48usize] ; ["Alignment of cs_arm_op"] [:: std :: mem :: align_of :: < cs_arm_op > () - 8usize] ; ["Offset of field: cs_arm_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm_op , vector_index) - 0usize] ; ["Offset of field: cs_arm_op::shift"] [:: std :: mem :: offset_of ! (cs_arm_op , shift) - 4usize] ; ["Offset of field: cs_arm_op::type_"] [:: std :: mem :: offset_of ! (cs_arm_op , type_) - 12usize] ; ["Offset of field: cs_arm_op::subtracted"] [:: std :: mem :: offset_of ! (cs_arm_op , subtracted) - 40usize] ; ["Offset of field: cs_arm_op::access"] [:: std :: mem :: offset_of ! (cs_arm_op , access) - 41usize] ; ["Offset of field: cs_arm_op::neon_lane"] [:: std :: mem :: offset_of ! (cs_arm_op , neon_lane) - 42usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm { # [doc = "< User-mode registers to be loaded (for LDM/STM instructions)"] pub usermode : bool , # [doc = "< Scalar size for vector instructions"] pub vector_size : :: std :: os :: raw :: c_int , # [doc = "< Data type for elements of vector instructions"] pub vector_data : arm_vectordata_type , # [doc = "< CPS mode for CPS instruction"] pub cps_mode : arm_cpsmode_type , # [doc = "< CPS mode for CPS instruction"] pub cps_flag : arm_cpsflag_type , # [doc = "< conditional code for this insn"] pub cc : arm_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn write-back?"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = "< Option for some memory barrier instructions"] pub mem_barrier : arm_mem_barrier , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm_op ; 36usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm"] [:: std :: mem :: size_of :: < cs_arm > () - 1768usize] ; ["Alignment of cs_arm"] [:: std :: mem :: align_of :: < cs_arm > () - 8usize] ; ["Offset of field: cs_arm::usermode"] [:: std :: mem :: offset_of ! (cs_arm , usermode) - 0usize] ; ["Offset of field: cs_arm::vector_size"] [:: std :: mem :: offset_of ! (cs_arm , vector_size) - 4usize] ; ["Offset of field: cs_arm::vector_data"] [:: std :: mem :: offset_of ! (cs_arm , vector_data) - 8usize] ; ["Offset of field: cs_arm::cps_mode"] [:: std :: mem :: offset_of ! (cs_arm , cps_mode) - 12usize] ; ["Offset of field: cs_arm::cps_flag"] [:: std :: mem :: offset_of ! (cs_arm , cps_flag) - 16usize] ; ["Offset of field: cs_arm::cc"] [:: std :: mem :: offset_of ! (cs_arm , cc) - 20usize] ; ["Offset of field: cs_arm::update_flags"] [:: std :: mem :: offset_of ! (cs_arm , update_flags) - 24usize] ; ["Offset of field: cs_arm::writeback"] [:: std :: mem :: offset_of ! (cs_arm , writeback) - 25usize] ; ["Offset of field: cs_arm::post_index"] [:: std :: mem :: offset_of ! (cs_arm , post_index) - 26usize] ; ["Offset of field: cs_arm::mem_barrier"] [:: std :: mem :: offset_of ! (cs_arm , mem_barrier) - 28usize] ; ["Offset of field: cs_arm::op_count"] [:: std :: mem :: offset_of ! (cs_arm , op_count) - 32usize] ; ["Offset of field: cs_arm::operands"] [:: std :: mem :: offset_of ! (cs_arm , operands) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_arm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . post_index , self . mem_barrier , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn { ARM_INS_INVALID = 0 , ARM_INS_ADC = 1 , ARM_INS_ADD = 2 , ARM_INS_ADDW = 3 , ARM_INS_ADR = 4 , ARM_INS_AESD = 5 , ARM_INS_AESE = 6 , ARM_INS_AESIMC = 7 , ARM_INS_AESMC = 8 , ARM_INS_AND = 9 , ARM_INS_ASR = 10 , ARM_INS_B = 11 , ARM_INS_BFC = 12 , ARM_INS_BFI = 13 , ARM_INS_BIC = 14 , ARM_INS_BKPT = 15 , ARM_INS_BL = 16 , ARM_INS_BLX = 17 , ARM_INS_BLXNS = 18 , ARM_INS_BX = 19 , ARM_INS_BXJ = 20 , ARM_INS_BXNS = 21 , ARM_INS_CBNZ = 22 , ARM_INS_CBZ = 23 , ARM_INS_CDP = 24 , ARM_INS_CDP2 = 25 , ARM_INS_CLREX = 26 , ARM_INS_CLZ = 27 , ARM_INS_CMN = 28 , ARM_INS_CMP = 29 , ARM_INS_CPS = 30 , ARM_INS_CRC32B = 31 , ARM_INS_CRC32CB = 32 , ARM_INS_CRC32CH = 33 , ARM_INS_CRC32CW = 34 , ARM_INS_CRC32H = 35 , ARM_INS_CRC32W = 36 , ARM_INS_CSDB = 37 , ARM_INS_DBG = 38 , ARM_INS_DCPS1 = 39 , ARM_INS_DCPS2 = 40 , ARM_INS_DCPS3 = 41 , ARM_INS_DFB = 42 , ARM_INS_DMB = 43 , ARM_INS_DSB = 44 , ARM_INS_EOR = 45 , ARM_INS_ERET = 46 , ARM_INS_ESB = 47 , ARM_INS_FADDD = 48 , ARM_INS_FADDS = 49 , ARM_INS_FCMPZD = 50 , ARM_INS_FCMPZS = 51 , ARM_INS_FCONSTD = 52 , ARM_INS_FCONSTS = 53 , ARM_INS_FLDMDBX = 54 , ARM_INS_FLDMIAX = 55 , ARM_INS_FMDHR = 56 , ARM_INS_FMDLR = 57 , ARM_INS_FMSTAT = 58 , ARM_INS_FSTMDBX = 59 , ARM_INS_FSTMIAX = 60 , ARM_INS_FSUBD = 61 , ARM_INS_FSUBS = 62 , ARM_INS_HINT = 63 , ARM_INS_HLT = 64 , ARM_INS_HVC = 65 , ARM_INS_ISB = 66 , ARM_INS_IT = 67 , ARM_INS_LDA = 68 , ARM_INS_LDAB = 69 , ARM_INS_LDAEX = 70 , ARM_INS_LDAEXB = 71 , ARM_INS_LDAEXD = 72 , ARM_INS_LDAEXH = 73 , ARM_INS_LDAH = 74 , ARM_INS_LDC = 75 , ARM_INS_LDC2 = 76 , ARM_INS_LDC2L = 77 , ARM_INS_LDCL = 78 , ARM_INS_LDM = 79 , ARM_INS_LDMDA = 80 , ARM_INS_LDMDB = 81 , ARM_INS_LDMIB = 82 , ARM_INS_LDR = 83 , ARM_INS_LDRB = 84 , ARM_INS_LDRBT = 85 , ARM_INS_LDRD = 86 , ARM_INS_LDREX = 87 , ARM_INS_LDREXB = 88 , ARM_INS_LDREXD = 89 , ARM_INS_LDREXH = 90 , ARM_INS_LDRH = 91 , ARM_INS_LDRHT = 92 , ARM_INS_LDRSB = 93 , ARM_INS_LDRSBT = 94 , ARM_INS_LDRSH = 95 , ARM_INS_LDRSHT = 96 , ARM_INS_LDRT = 97 , ARM_INS_LSL = 98 , ARM_INS_LSR = 99 , ARM_INS_MCR = 100 , ARM_INS_MCR2 = 101 , ARM_INS_MCRR = 102 , ARM_INS_MCRR2 = 103 , ARM_INS_MLA = 104 , ARM_INS_MLS = 105 , ARM_INS_MOV = 106 , ARM_INS_MOVS = 107 , ARM_INS_MOVT = 108 , ARM_INS_MOVW = 109 , ARM_INS_MRC = 110 , ARM_INS_MRC2 = 111 , ARM_INS_MRRC = 112 , ARM_INS_MRRC2 = 113 , ARM_INS_MRS = 114 , ARM_INS_MSR = 115 , ARM_INS_MUL = 116 , ARM_INS_MVN = 117 , ARM_INS_NEG = 118 , ARM_INS_NOP = 119 , ARM_INS_ORN = 120 , ARM_INS_ORR = 121 , ARM_INS_PKHBT = 122 , ARM_INS_PKHTB = 123 , ARM_INS_PLD = 124 , ARM_INS_PLDW = 125 , ARM_INS_PLI = 126 , ARM_INS_POP = 127 , ARM_INS_PUSH = 128 , ARM_INS_QADD = 129 , ARM_INS_QADD16 = 130 , ARM_INS_QADD8 = 131 , ARM_INS_QASX = 132 , ARM_INS_QDADD = 133 , ARM_INS_QDSUB = 134 , ARM_INS_QSAX = 135 , ARM_INS_QSUB = 136 , ARM_INS_QSUB16 = 137 , ARM_INS_QSUB8 = 138 , ARM_INS_RBIT = 139 , ARM_INS_REV = 140 , ARM_INS_REV16 = 141 , ARM_INS_REVSH = 142 , ARM_INS_RFEDA = 143 , ARM_INS_RFEDB = 144 , ARM_INS_RFEIA = 145 , ARM_INS_RFEIB = 146 , ARM_INS_ROR = 147 , ARM_INS_RRX = 148 , ARM_INS_RSB = 149 , ARM_INS_RSC = 150 , ARM_INS_SADD16 = 151 , ARM_INS_SADD8 = 152 , ARM_INS_SASX = 153 , ARM_INS_SBC = 154 , ARM_INS_SBFX = 155 , ARM_INS_SDIV = 156 , ARM_INS_SEL = 157 , ARM_INS_SETEND = 158 , ARM_INS_SETPAN = 159 , ARM_INS_SEV = 160 , ARM_INS_SEVL = 161 , ARM_INS_SG = 162 , ARM_INS_SHA1C = 163 , ARM_INS_SHA1H = 164 , ARM_INS_SHA1M = 165 , ARM_INS_SHA1P = 166 , ARM_INS_SHA1SU0 = 167 , ARM_INS_SHA1SU1 = 168 , ARM_INS_SHA256H = 169 , ARM_INS_SHA256H2 = 170 , ARM_INS_SHA256SU0 = 171 , ARM_INS_SHA256SU1 = 172 , ARM_INS_SHADD16 = 173 , ARM_INS_SHADD8 = 174 , ARM_INS_SHASX = 175 , ARM_INS_SHSAX = 176 , ARM_INS_SHSUB16 = 177 , ARM_INS_SHSUB8 = 178 , ARM_INS_SMC = 179 , ARM_INS_SMLABB = 180 , ARM_INS_SMLABT = 181 , ARM_INS_SMLAD = 182 , ARM_INS_SMLADX = 183 , ARM_INS_SMLAL = 184 , ARM_INS_SMLALBB = 185 , ARM_INS_SMLALBT = 186 , ARM_INS_SMLALD = 187 , ARM_INS_SMLALDX = 188 , ARM_INS_SMLALTB = 189 , ARM_INS_SMLALTT = 190 , ARM_INS_SMLATB = 191 , ARM_INS_SMLATT = 192 , ARM_INS_SMLAWB = 193 , ARM_INS_SMLAWT = 194 , ARM_INS_SMLSD = 195 , ARM_INS_SMLSDX = 196 , ARM_INS_SMLSLD = 197 , ARM_INS_SMLSLDX = 198 , ARM_INS_SMMLA = 199 , ARM_INS_SMMLAR = 200 , ARM_INS_SMMLS = 201 , ARM_INS_SMMLSR = 202 , ARM_INS_SMMUL = 203 , ARM_INS_SMMULR = 204 , ARM_INS_SMUAD = 205 , ARM_INS_SMUADX = 206 , ARM_INS_SMULBB = 207 , ARM_INS_SMULBT = 208 , ARM_INS_SMULL = 209 , ARM_INS_SMULTB = 210 , ARM_INS_SMULTT = 211 , ARM_INS_SMULWB = 212 , ARM_INS_SMULWT = 213 , ARM_INS_SMUSD = 214 , ARM_INS_SMUSDX = 215 , ARM_INS_SRSDA = 216 , ARM_INS_SRSDB = 217 , ARM_INS_SRSIA = 218 , ARM_INS_SRSIB = 219 , ARM_INS_SSAT = 220 , ARM_INS_SSAT16 = 221 , ARM_INS_SSAX = 222 , ARM_INS_SSUB16 = 223 , ARM_INS_SSUB8 = 224 , ARM_INS_STC = 225 , ARM_INS_STC2 = 226 , ARM_INS_STC2L = 227 , ARM_INS_STCL = 228 , ARM_INS_STL = 229 , ARM_INS_STLB = 230 , ARM_INS_STLEX = 231 , ARM_INS_STLEXB = 232 , ARM_INS_STLEXD = 233 , ARM_INS_STLEXH = 234 , ARM_INS_STLH = 235 , ARM_INS_STM = 236 , ARM_INS_STMDA = 237 , ARM_INS_STMDB = 238 , ARM_INS_STMIB = 239 , ARM_INS_STR = 240 , ARM_INS_STRB = 241 , ARM_INS_STRBT = 242 , ARM_INS_STRD = 243 , ARM_INS_STREX = 244 , ARM_INS_STREXB = 245 , ARM_INS_STREXD = 246 , ARM_INS_STREXH = 247 , ARM_INS_STRH = 248 , ARM_INS_STRHT = 249 , ARM_INS_STRT = 250 , ARM_INS_SUB = 251 , ARM_INS_SUBS = 252 , ARM_INS_SUBW = 253 , ARM_INS_SVC = 254 , ARM_INS_SWP = 255 , ARM_INS_SWPB = 256 , ARM_INS_SXTAB = 257 , ARM_INS_SXTAB16 = 258 , ARM_INS_SXTAH = 259 , ARM_INS_SXTB = 260 , ARM_INS_SXTB16 = 261 , ARM_INS_SXTH = 262 , ARM_INS_TBB = 263 , ARM_INS_TBH = 264 , ARM_INS_TEQ = 265 , ARM_INS_TRAP = 266 , ARM_INS_TSB = 267 , ARM_INS_TST = 268 , ARM_INS_TT = 269 , ARM_INS_TTA = 270 , ARM_INS_TTAT = 271 , ARM_INS_TTT = 272 , ARM_INS_UADD16 = 273 , ARM_INS_UADD8 = 274 , ARM_INS_UASX = 275 , ARM_INS_UBFX = 276 , ARM_INS_UDF = 277 , ARM_INS_UDIV = 278 , ARM_INS_UHADD16 = 279 , ARM_INS_UHADD8 = 280 , ARM_INS_UHASX = 281 , ARM_INS_UHSAX = 282 , ARM_INS_UHSUB16 = 283 , ARM_INS_UHSUB8 = 284 , ARM_INS_UMAAL = 285 , ARM_INS_UMLAL = 286 , ARM_INS_UMULL = 287 , ARM_INS_UQADD16 = 288 , ARM_INS_UQADD8 = 289 , ARM_INS_UQASX = 290 , ARM_INS_UQSAX = 291 , ARM_INS_UQSUB16 = 292 , ARM_INS_UQSUB8 = 293 , ARM_INS_USAD8 = 294 , ARM_INS_USADA8 = 295 , ARM_INS_USAT = 296 , ARM_INS_USAT16 = 297 , ARM_INS_USAX = 298 , ARM_INS_USUB16 = 299 , ARM_INS_USUB8 = 300 , ARM_INS_UXTAB = 301 , ARM_INS_UXTAB16 = 302 , ARM_INS_UXTAH = 303 , ARM_INS_UXTB = 304 , ARM_INS_UXTB16 = 305 , ARM_INS_UXTH = 306 , ARM_INS_VABA = 307 , ARM_INS_VABAL = 308 , ARM_INS_VABD = 309 , ARM_INS_VABDL = 310 , ARM_INS_VABS = 311 , ARM_INS_VACGE = 312 , ARM_INS_VACGT = 313 , ARM_INS_VACLE = 314 , ARM_INS_VACLT = 315 , ARM_INS_VADD = 316 , ARM_INS_VADDHN = 317 , ARM_INS_VADDL = 318 , ARM_INS_VADDW = 319 , ARM_INS_VAND = 320 , ARM_INS_VBIC = 321 , ARM_INS_VBIF = 322 , ARM_INS_VBIT = 323 , ARM_INS_VBSL = 324 , ARM_INS_VCADD = 325 , ARM_INS_VCEQ = 326 , ARM_INS_VCGE = 327 , ARM_INS_VCGT = 328 , ARM_INS_VCLE = 329 , ARM_INS_VCLS = 330 , ARM_INS_VCLT = 331 , ARM_INS_VCLZ = 332 , ARM_INS_VCMLA = 333 , ARM_INS_VCMP = 334 , ARM_INS_VCMPE = 335 , ARM_INS_VCNT = 336 , ARM_INS_VCVT = 337 , ARM_INS_VCVTA = 338 , ARM_INS_VCVTB = 339 , ARM_INS_VCVTM = 340 , ARM_INS_VCVTN = 341 , ARM_INS_VCVTP = 342 , ARM_INS_VCVTR = 343 , ARM_INS_VCVTT = 344 , ARM_INS_VDIV = 345 , ARM_INS_VDUP = 346 , ARM_INS_VEOR = 347 , ARM_INS_VEXT = 348 , ARM_INS_VFMA = 349 , ARM_INS_VFMS = 350 , ARM_INS_VFNMA = 351 , ARM_INS_VFNMS = 352 , ARM_INS_VHADD = 353 , ARM_INS_VHSUB = 354 , ARM_INS_VINS = 355 , ARM_INS_VJCVT = 356 , ARM_INS_VLD1 = 357 , ARM_INS_VLD2 = 358 , ARM_INS_VLD3 = 359 , ARM_INS_VLD4 = 360 , ARM_INS_VLDMDB = 361 , ARM_INS_VLDMIA = 362 , ARM_INS_VLDR = 363 , ARM_INS_VLLDM = 364 , ARM_INS_VLSTM = 365 , ARM_INS_VMAX = 366 , ARM_INS_VMAXNM = 367 , ARM_INS_VMIN = 368 , ARM_INS_VMINNM = 369 , ARM_INS_VMLA = 370 , ARM_INS_VMLAL = 371 , ARM_INS_VMLS = 372 , ARM_INS_VMLSL = 373 , ARM_INS_VMOV = 374 , ARM_INS_VMOVL = 375 , ARM_INS_VMOVN = 376 , ARM_INS_VMOVX = 377 , ARM_INS_VMRS = 378 , ARM_INS_VMSR = 379 , ARM_INS_VMUL = 380 , ARM_INS_VMULL = 381 , ARM_INS_VMVN = 382 , ARM_INS_VNEG = 383 , ARM_INS_VNMLA = 384 , ARM_INS_VNMLS = 385 , ARM_INS_VNMUL = 386 , ARM_INS_VORN = 387 , ARM_INS_VORR = 388 , ARM_INS_VPADAL = 389 , ARM_INS_VPADD = 390 , ARM_INS_VPADDL = 391 , ARM_INS_VPMAX = 392 , ARM_INS_VPMIN = 393 , ARM_INS_VPOP = 394 , ARM_INS_VPUSH = 395 , ARM_INS_VQABS = 396 , ARM_INS_VQADD = 397 , ARM_INS_VQDMLAL = 398 , ARM_INS_VQDMLSL = 399 , ARM_INS_VQDMULH = 400 , ARM_INS_VQDMULL = 401 , ARM_INS_VQMOVN = 402 , ARM_INS_VQMOVUN = 403 , ARM_INS_VQNEG = 404 , ARM_INS_VQRDMLAH = 405 , ARM_INS_VQRDMLSH = 406 , ARM_INS_VQRDMULH = 407 , ARM_INS_VQRSHL = 408 , ARM_INS_VQRSHRN = 409 , ARM_INS_VQRSHRUN = 410 , ARM_INS_VQSHL = 411 , ARM_INS_VQSHLU = 412 , ARM_INS_VQSHRN = 413 , ARM_INS_VQSHRUN = 414 , ARM_INS_VQSUB = 415 , ARM_INS_VRADDHN = 416 , ARM_INS_VRECPE = 417 , ARM_INS_VRECPS = 418 , ARM_INS_VREV16 = 419 , ARM_INS_VREV32 = 420 , ARM_INS_VREV64 = 421 , ARM_INS_VRHADD = 422 , ARM_INS_VRINTA = 423 , ARM_INS_VRINTM = 424 , ARM_INS_VRINTN = 425 , ARM_INS_VRINTP = 426 , ARM_INS_VRINTR = 427 , ARM_INS_VRINTX = 428 , ARM_INS_VRINTZ = 429 , ARM_INS_VRSHL = 430 , ARM_INS_VRSHR = 431 , ARM_INS_VRSHRN = 432 , ARM_INS_VRSQRTE = 433 , ARM_INS_VRSQRTS = 434 , ARM_INS_VRSRA = 435 , ARM_INS_VRSUBHN = 436 , ARM_INS_VSDOT = 437 , ARM_INS_VSELEQ = 438 , ARM_INS_VSELGE = 439 , ARM_INS_VSELGT = 440 , ARM_INS_VSELVS = 441 , ARM_INS_VSHL = 442 , ARM_INS_VSHLL = 443 , ARM_INS_VSHR = 444 , ARM_INS_VSHRN = 445 , ARM_INS_VSLI = 446 , ARM_INS_VSQRT = 447 , ARM_INS_VSRA = 448 , ARM_INS_VSRI = 449 , ARM_INS_VST1 = 450 , ARM_INS_VST2 = 451 , ARM_INS_VST3 = 452 , ARM_INS_VST4 = 453 , ARM_INS_VSTMDB = 454 , ARM_INS_VSTMIA = 455 , ARM_INS_VSTR = 456 , ARM_INS_VSUB = 457 , ARM_INS_VSUBHN = 458 , ARM_INS_VSUBL = 459 , ARM_INS_VSUBW = 460 , ARM_INS_VSWP = 461 , ARM_INS_VTBL = 462 , ARM_INS_VTBX = 463 , ARM_INS_VTRN = 464 , ARM_INS_VTST = 465 , ARM_INS_VUDOT = 466 , ARM_INS_VUZP = 467 , ARM_INS_VZIP = 468 , ARM_INS_WFE = 469 , ARM_INS_WFI = 470 , ARM_INS_YIELD = 471 , ARM_INS_ENDING = 472 , } # [repr (u32)] # [doc = " Group of ARM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] ARM_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] ARM_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM_GRP_BRANCH_RELATIVE = 7 , ARM_GRP_CRYPTO = 128 , ARM_GRP_DATABARRIER = 129 , ARM_GRP_DIVIDE = 130 , ARM_GRP_FPARMV8 = 131 , ARM_GRP_MULTPRO = 132 , ARM_GRP_NEON = 133 , ARM_GRP_T2EXTRACTPACK = 134 , ARM_GRP_THUMB2DSP = 135 , ARM_GRP_TRUSTZONE = 136 , ARM_GRP_V4T = 137 , ARM_GRP_V5T = 138 , ARM_GRP_V5TE = 139 , ARM_GRP_V6 = 140 , ARM_GRP_V6T2 = 141 , ARM_GRP_V7 = 142 , ARM_GRP_V8 = 143 , ARM_GRP_VFP2 = 144 , ARM_GRP_VFP3 = 145 , ARM_GRP_VFP4 = 146 , ARM_GRP_ARM = 147 , ARM_GRP_MCLASS = 148 , ARM_GRP_NOTMCLASS = 149 , ARM_GRP_THUMB = 150 , ARM_GRP_THUMB1ONLY = 151 , ARM_GRP_THUMB2 = 152 , ARM_GRP_PREV8 = 153 , ARM_GRP_FPVMLX = 154 , ARM_GRP_MULOPS = 155 , ARM_GRP_CRC = 156 , ARM_GRP_DPVFP = 157 , ARM_GRP_V6M = 158 , ARM_GRP_VIRTUALIZATION = 159 , ARM_GRP_ENDING = 160 , } # [repr (u32)] # [doc = " ARM64 shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_shifter { ARM64_SFT_INVALID = 0 , ARM64_SFT_LSL = 1 , ARM64_SFT_MSL = 2 , ARM64_SFT_LSR = 3 , ARM64_SFT_ASR = 4 , ARM64_SFT_ROR = 5 , } # [repr (u32)] # [doc = " ARM64 extender type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_extender { ARM64_EXT_INVALID = 0 , ARM64_EXT_UXTB = 1 , ARM64_EXT_UXTH = 2 , ARM64_EXT_UXTW = 3 , ARM64_EXT_UXTX = 4 , ARM64_EXT_SXTB = 5 , ARM64_EXT_SXTH = 6 , ARM64_EXT_SXTW = 7 , ARM64_EXT_SXTX = 8 , } # [repr (u32)] # [doc = " ARM64 condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_cc { ARM64_CC_INVALID = 0 , # [doc = "< Equal"] ARM64_CC_EQ = 1 , # [doc = "< Not equal:                 Not equal, or unordered"] ARM64_CC_NE = 2 , # [doc = "< Unsigned higher or same:   >, ==, or unordered"] ARM64_CC_HS = 3 , # [doc = "< Unsigned lower or same:    Less than"] ARM64_CC_LO = 4 , # [doc = "< Minus, negative:           Less than"] ARM64_CC_MI = 5 , # [doc = "< Plus, positive or zero:    >, ==, or unordered"] ARM64_CC_PL = 6 , # [doc = "< Overflow:                  Unordered"] ARM64_CC_VS = 7 , # [doc = "< No overflow:               Ordered"] ARM64_CC_VC = 8 , # [doc = "< Unsigned higher:           Greater than, or unordered"] ARM64_CC_HI = 9 , # [doc = "< Unsigned lower or same:    Less than or equal"] ARM64_CC_LS = 10 , # [doc = "< Greater than or equal:     Greater than or equal"] ARM64_CC_GE = 11 , # [doc = "< Less than:                 Less than, or unordered"] ARM64_CC_LT = 12 , # [doc = "< Signed greater than:       Greater than"] ARM64_CC_GT = 13 , # [doc = "< Signed less than or equal: <, ==, or unordered"] ARM64_CC_LE = 14 , # [doc = "< Always (unconditional):    Always (unconditional)"] ARM64_CC_AL = 15 , # [doc = "< Always (unconditional):   Always (unconditional)"] ARM64_CC_NV = 16 , } impl arm64_sysreg { pub const ARM64_SYSREG_DBGDTRTX_EL0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_DBGDTRRX_EL0 ; } impl arm64_sysreg { pub const ARM64_SYSREG_TRCEXTINSELR0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TRCEXTINSELR ; } impl arm64_sysreg { pub const ARM64_SYSREG_VSCTLR_EL2 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TTBR0_EL2 ; } # [repr (u32)] # [doc = " System registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sysreg { ARM64_SYSREG_INVALID = 0 , ARM64_SYSREG_ACCDATA_EL1 = 50821 , ARM64_SYSREG_ACTLR_EL1 = 49281 , ARM64_SYSREG_ACTLR_EL2 = 57473 , ARM64_SYSREG_ACTLR_EL3 = 61569 , ARM64_SYSREG_AFSR0_EL1 = 49800 , ARM64_SYSREG_AFSR0_EL12 = 60040 , ARM64_SYSREG_AFSR0_EL2 = 57992 , ARM64_SYSREG_AFSR0_EL3 = 62088 , ARM64_SYSREG_AFSR1_EL1 = 49801 , ARM64_SYSREG_AFSR1_EL12 = 60041 , ARM64_SYSREG_AFSR1_EL2 = 57993 , ARM64_SYSREG_AFSR1_EL3 = 62089 , ARM64_SYSREG_AIDR_EL1 = 51207 , ARM64_SYSREG_AMAIR_EL1 = 50456 , ARM64_SYSREG_AMAIR_EL12 = 60696 , ARM64_SYSREG_AMAIR_EL2 = 58648 , ARM64_SYSREG_AMAIR_EL3 = 62744 , ARM64_SYSREG_AMCFGR_EL0 = 56977 , ARM64_SYSREG_AMCGCR_EL0 = 56978 , ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980 , ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984 , ARM64_SYSREG_AMCNTENSET0_EL0 = 56981 , ARM64_SYSREG_AMCNTENSET1_EL0 = 56985 , ARM64_SYSREG_AMCR_EL0 = 56976 , ARM64_SYSREG_AMEVCNTR00_EL0 = 56992 , ARM64_SYSREG_AMEVCNTR01_EL0 = 56993 , ARM64_SYSREG_AMEVCNTR02_EL0 = 56994 , ARM64_SYSREG_AMEVCNTR03_EL0 = 56995 , ARM64_SYSREG_AMEVCNTR10_EL0 = 57056 , ARM64_SYSREG_AMEVCNTR110_EL0 = 57066 , ARM64_SYSREG_AMEVCNTR111_EL0 = 57067 , ARM64_SYSREG_AMEVCNTR112_EL0 = 57068 , ARM64_SYSREG_AMEVCNTR113_EL0 = 57069 , ARM64_SYSREG_AMEVCNTR114_EL0 = 57070 , ARM64_SYSREG_AMEVCNTR115_EL0 = 57071 , ARM64_SYSREG_AMEVCNTR11_EL0 = 57057 , ARM64_SYSREG_AMEVCNTR12_EL0 = 57058 , ARM64_SYSREG_AMEVCNTR13_EL0 = 57059 , ARM64_SYSREG_AMEVCNTR14_EL0 = 57060 , ARM64_SYSREG_AMEVCNTR15_EL0 = 57061 , ARM64_SYSREG_AMEVCNTR16_EL0 = 57062 , ARM64_SYSREG_AMEVCNTR17_EL0 = 57063 , ARM64_SYSREG_AMEVCNTR18_EL0 = 57064 , ARM64_SYSREG_AMEVCNTR19_EL0 = 57065 , ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 59072 , ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 59082 , ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 59083 , ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 59084 , ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 59085 , ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 59086 , ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 59087 , ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 59073 , ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 59074 , ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 59075 , ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 59076 , ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 59077 , ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 59078 , ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 59079 , ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 59080 , ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 59081 , ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 59088 , ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 59098 , ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 59099 , ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 59100 , ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 59101 , ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 59102 , ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 59103 , ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 59089 , ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 59090 , ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 59091 , ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 59092 , ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 59093 , ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 59094 , ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 59095 , ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 59096 , ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 59097 , ARM64_SYSREG_AMEVTYPER00_EL0 = 57008 , ARM64_SYSREG_AMEVTYPER01_EL0 = 57009 , ARM64_SYSREG_AMEVTYPER02_EL0 = 57010 , ARM64_SYSREG_AMEVTYPER03_EL0 = 57011 , ARM64_SYSREG_AMEVTYPER10_EL0 = 57072 , ARM64_SYSREG_AMEVTYPER110_EL0 = 57082 , ARM64_SYSREG_AMEVTYPER111_EL0 = 57083 , ARM64_SYSREG_AMEVTYPER112_EL0 = 57084 , ARM64_SYSREG_AMEVTYPER113_EL0 = 57085 , ARM64_SYSREG_AMEVTYPER114_EL0 = 57086 , ARM64_SYSREG_AMEVTYPER115_EL0 = 57087 , ARM64_SYSREG_AMEVTYPER11_EL0 = 57073 , ARM64_SYSREG_AMEVTYPER12_EL0 = 57074 , ARM64_SYSREG_AMEVTYPER13_EL0 = 57075 , ARM64_SYSREG_AMEVTYPER14_EL0 = 57076 , ARM64_SYSREG_AMEVTYPER15_EL0 = 57077 , ARM64_SYSREG_AMEVTYPER16_EL0 = 57078 , ARM64_SYSREG_AMEVTYPER17_EL0 = 57079 , ARM64_SYSREG_AMEVTYPER18_EL0 = 57080 , ARM64_SYSREG_AMEVTYPER19_EL0 = 57081 , ARM64_SYSREG_AMUSERENR_EL0 = 56979 , ARM64_SYSREG_APDAKEYHI_EL1 = 49425 , ARM64_SYSREG_APDAKEYLO_EL1 = 49424 , ARM64_SYSREG_APDBKEYHI_EL1 = 49427 , ARM64_SYSREG_APDBKEYLO_EL1 = 49426 , ARM64_SYSREG_APGAKEYHI_EL1 = 49433 , ARM64_SYSREG_APGAKEYLO_EL1 = 49432 , ARM64_SYSREG_APIAKEYHI_EL1 = 49417 , ARM64_SYSREG_APIAKEYLO_EL1 = 49416 , ARM64_SYSREG_APIBKEYHI_EL1 = 49419 , ARM64_SYSREG_APIBKEYLO_EL1 = 49418 , ARM64_SYSREG_BRBCR_EL1 = 35968 , ARM64_SYSREG_BRBCR_EL12 = 44160 , ARM64_SYSREG_BRBCR_EL2 = 42112 , ARM64_SYSREG_BRBFCR_EL1 = 35969 , ARM64_SYSREG_BRBIDR0_EL1 = 35984 , ARM64_SYSREG_BRBINF0_EL1 = 35840 , ARM64_SYSREG_BRBINF10_EL1 = 35920 , ARM64_SYSREG_BRBINF11_EL1 = 35928 , ARM64_SYSREG_BRBINF12_EL1 = 35936 , ARM64_SYSREG_BRBINF13_EL1 = 35944 , ARM64_SYSREG_BRBINF14_EL1 = 35952 , ARM64_SYSREG_BRBINF15_EL1 = 35960 , ARM64_SYSREG_BRBINF16_EL1 = 35844 , ARM64_SYSREG_BRBINF17_EL1 = 35852 , ARM64_SYSREG_BRBINF18_EL1 = 35860 , ARM64_SYSREG_BRBINF19_EL1 = 35868 , ARM64_SYSREG_BRBINF1_EL1 = 35848 , ARM64_SYSREG_BRBINF20_EL1 = 35876 , ARM64_SYSREG_BRBINF21_EL1 = 35884 , ARM64_SYSREG_BRBINF22_EL1 = 35892 , ARM64_SYSREG_BRBINF23_EL1 = 35900 , ARM64_SYSREG_BRBINF24_EL1 = 35908 , ARM64_SYSREG_BRBINF25_EL1 = 35916 , ARM64_SYSREG_BRBINF26_EL1 = 35924 , ARM64_SYSREG_BRBINF27_EL1 = 35932 , ARM64_SYSREG_BRBINF28_EL1 = 35940 , ARM64_SYSREG_BRBINF29_EL1 = 35948 , ARM64_SYSREG_BRBINF2_EL1 = 35856 , ARM64_SYSREG_BRBINF30_EL1 = 35956 , ARM64_SYSREG_BRBINF31_EL1 = 35964 , ARM64_SYSREG_BRBINF3_EL1 = 35864 , ARM64_SYSREG_BRBINF4_EL1 = 35872 , ARM64_SYSREG_BRBINF5_EL1 = 35880 , ARM64_SYSREG_BRBINF6_EL1 = 35888 , ARM64_SYSREG_BRBINF7_EL1 = 35896 , ARM64_SYSREG_BRBINF8_EL1 = 35904 , ARM64_SYSREG_BRBINF9_EL1 = 35912 , ARM64_SYSREG_BRBINFINJ_EL1 = 35976 , ARM64_SYSREG_BRBSRC0_EL1 = 35841 , ARM64_SYSREG_BRBSRC10_EL1 = 35921 , ARM64_SYSREG_BRBSRC11_EL1 = 35929 , ARM64_SYSREG_BRBSRC12_EL1 = 35937 , ARM64_SYSREG_BRBSRC13_EL1 = 35945 , ARM64_SYSREG_BRBSRC14_EL1 = 35953 , ARM64_SYSREG_BRBSRC15_EL1 = 35961 , ARM64_SYSREG_BRBSRC16_EL1 = 35845 , ARM64_SYSREG_BRBSRC17_EL1 = 35853 , ARM64_SYSREG_BRBSRC18_EL1 = 35861 , ARM64_SYSREG_BRBSRC19_EL1 = 35869 , ARM64_SYSREG_BRBSRC1_EL1 = 35849 , ARM64_SYSREG_BRBSRC20_EL1 = 35877 , ARM64_SYSREG_BRBSRC21_EL1 = 35885 , ARM64_SYSREG_BRBSRC22_EL1 = 35893 , ARM64_SYSREG_BRBSRC23_EL1 = 35901 , ARM64_SYSREG_BRBSRC24_EL1 = 35909 , ARM64_SYSREG_BRBSRC25_EL1 = 35917 , ARM64_SYSREG_BRBSRC26_EL1 = 35925 , ARM64_SYSREG_BRBSRC27_EL1 = 35933 , ARM64_SYSREG_BRBSRC28_EL1 = 35941 , ARM64_SYSREG_BRBSRC29_EL1 = 35949 , ARM64_SYSREG_BRBSRC2_EL1 = 35857 , ARM64_SYSREG_BRBSRC30_EL1 = 35957 , ARM64_SYSREG_BRBSRC31_EL1 = 35965 , ARM64_SYSREG_BRBSRC3_EL1 = 35865 , ARM64_SYSREG_BRBSRC4_EL1 = 35873 , ARM64_SYSREG_BRBSRC5_EL1 = 35881 , ARM64_SYSREG_BRBSRC6_EL1 = 35889 , ARM64_SYSREG_BRBSRC7_EL1 = 35897 , ARM64_SYSREG_BRBSRC8_EL1 = 35905 , ARM64_SYSREG_BRBSRC9_EL1 = 35913 , ARM64_SYSREG_BRBSRCINJ_EL1 = 35977 , ARM64_SYSREG_BRBTGT0_EL1 = 35842 , ARM64_SYSREG_BRBTGT10_EL1 = 35922 , ARM64_SYSREG_BRBTGT11_EL1 = 35930 , ARM64_SYSREG_BRBTGT12_EL1 = 35938 , ARM64_SYSREG_BRBTGT13_EL1 = 35946 , ARM64_SYSREG_BRBTGT14_EL1 = 35954 , ARM64_SYSREG_BRBTGT15_EL1 = 35962 , ARM64_SYSREG_BRBTGT16_EL1 = 35846 , ARM64_SYSREG_BRBTGT17_EL1 = 35854 , ARM64_SYSREG_BRBTGT18_EL1 = 35862 , ARM64_SYSREG_BRBTGT19_EL1 = 35870 , ARM64_SYSREG_BRBTGT1_EL1 = 35850 , ARM64_SYSREG_BRBTGT20_EL1 = 35878 , ARM64_SYSREG_BRBTGT21_EL1 = 35886 , ARM64_SYSREG_BRBTGT22_EL1 = 35894 , ARM64_SYSREG_BRBTGT23_EL1 = 35902 , ARM64_SYSREG_BRBTGT24_EL1 = 35910 , ARM64_SYSREG_BRBTGT25_EL1 = 35918 , ARM64_SYSREG_BRBTGT26_EL1 = 35926 , ARM64_SYSREG_BRBTGT27_EL1 = 35934 , ARM64_SYSREG_BRBTGT28_EL1 = 35942 , ARM64_SYSREG_BRBTGT29_EL1 = 35950 , ARM64_SYSREG_BRBTGT2_EL1 = 35858 , ARM64_SYSREG_BRBTGT30_EL1 = 35958 , ARM64_SYSREG_BRBTGT31_EL1 = 35966 , ARM64_SYSREG_BRBTGT3_EL1 = 35866 , ARM64_SYSREG_BRBTGT4_EL1 = 35874 , ARM64_SYSREG_BRBTGT5_EL1 = 35882 , ARM64_SYSREG_BRBTGT6_EL1 = 35890 , ARM64_SYSREG_BRBTGT7_EL1 = 35898 , ARM64_SYSREG_BRBTGT8_EL1 = 35906 , ARM64_SYSREG_BRBTGT9_EL1 = 35914 , ARM64_SYSREG_BRBTGTINJ_EL1 = 35978 , ARM64_SYSREG_BRBTS_EL1 = 35970 , ARM64_SYSREG_CCSIDR2_EL1 = 51202 , ARM64_SYSREG_CCSIDR_EL1 = 51200 , ARM64_SYSREG_CLIDR_EL1 = 51201 , ARM64_SYSREG_CNTFRQ_EL0 = 57088 , ARM64_SYSREG_CNTHCTL_EL2 = 59144 , ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177 , ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178 , ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176 , ARM64_SYSREG_CNTHP_CTL_EL2 = 59153 , ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154 , ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152 , ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169 , ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170 , ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168 , ARM64_SYSREG_CNTHV_CTL_EL2 = 59161 , ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162 , ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160 , ARM64_SYSREG_CNTISCALE_EL2 = 59141 , ARM64_SYSREG_CNTKCTL_EL1 = 50952 , ARM64_SYSREG_CNTKCTL_EL12 = 61192 , ARM64_SYSREG_CNTPCTSS_EL0 = 57093 , ARM64_SYSREG_CNTPCT_EL0 = 57089 , ARM64_SYSREG_CNTPOFF_EL2 = 59142 , ARM64_SYSREG_CNTPS_CTL_EL1 = 65297 , ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298 , ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296 , ARM64_SYSREG_CNTP_CTL_EL0 = 57105 , ARM64_SYSREG_CNTP_CTL_EL02 = 61201 , ARM64_SYSREG_CNTP_CVAL_EL0 = 57106 , ARM64_SYSREG_CNTP_CVAL_EL02 = 61202 , ARM64_SYSREG_CNTP_TVAL_EL0 = 57104 , ARM64_SYSREG_CNTP_TVAL_EL02 = 61200 , ARM64_SYSREG_CNTSCALE_EL2 = 59140 , ARM64_SYSREG_CNTVCTSS_EL0 = 57094 , ARM64_SYSREG_CNTVCT_EL0 = 57090 , ARM64_SYSREG_CNTVFRQ_EL2 = 59143 , ARM64_SYSREG_CNTVOFF_EL2 = 59139 , ARM64_SYSREG_CNTV_CTL_EL0 = 57113 , ARM64_SYSREG_CNTV_CTL_EL02 = 61209 , ARM64_SYSREG_CNTV_CVAL_EL0 = 57114 , ARM64_SYSREG_CNTV_CVAL_EL02 = 61210 , ARM64_SYSREG_CNTV_TVAL_EL0 = 57112 , ARM64_SYSREG_CNTV_TVAL_EL02 = 61208 , ARM64_SYSREG_CONTEXTIDR_EL1 = 50817 , ARM64_SYSREG_CONTEXTIDR_EL12 = 61057 , ARM64_SYSREG_CONTEXTIDR_EL2 = 59009 , ARM64_SYSREG_CPACR_EL1 = 49282 , ARM64_SYSREG_CPACR_EL12 = 59522 , ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424 , ARM64_SYSREG_CPTR_EL2 = 57482 , ARM64_SYSREG_CPTR_EL3 = 61578 , ARM64_SYSREG_CSSELR_EL1 = 53248 , ARM64_SYSREG_CTR_EL0 = 55297 , ARM64_SYSREG_CURRENTEL = 49682 , ARM64_SYSREG_DACR32_EL2 = 57728 , ARM64_SYSREG_DAIF = 55825 , ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782 , ARM64_SYSREG_DBGBCR0_EL1 = 32773 , ARM64_SYSREG_DBGBCR10_EL1 = 32853 , ARM64_SYSREG_DBGBCR11_EL1 = 32861 , ARM64_SYSREG_DBGBCR12_EL1 = 32869 , ARM64_SYSREG_DBGBCR13_EL1 = 32877 , ARM64_SYSREG_DBGBCR14_EL1 = 32885 , ARM64_SYSREG_DBGBCR15_EL1 = 32893 , ARM64_SYSREG_DBGBCR1_EL1 = 32781 , ARM64_SYSREG_DBGBCR2_EL1 = 32789 , ARM64_SYSREG_DBGBCR3_EL1 = 32797 , ARM64_SYSREG_DBGBCR4_EL1 = 32805 , ARM64_SYSREG_DBGBCR5_EL1 = 32813 , ARM64_SYSREG_DBGBCR6_EL1 = 32821 , ARM64_SYSREG_DBGBCR7_EL1 = 32829 , ARM64_SYSREG_DBGBCR8_EL1 = 32837 , ARM64_SYSREG_DBGBCR9_EL1 = 32845 , ARM64_SYSREG_DBGBVR0_EL1 = 32772 , ARM64_SYSREG_DBGBVR10_EL1 = 32852 , ARM64_SYSREG_DBGBVR11_EL1 = 32860 , ARM64_SYSREG_DBGBVR12_EL1 = 32868 , ARM64_SYSREG_DBGBVR13_EL1 = 32876 , ARM64_SYSREG_DBGBVR14_EL1 = 32884 , ARM64_SYSREG_DBGBVR15_EL1 = 32892 , ARM64_SYSREG_DBGBVR1_EL1 = 32780 , ARM64_SYSREG_DBGBVR2_EL1 = 32788 , ARM64_SYSREG_DBGBVR3_EL1 = 32796 , ARM64_SYSREG_DBGBVR4_EL1 = 32804 , ARM64_SYSREG_DBGBVR5_EL1 = 32812 , ARM64_SYSREG_DBGBVR6_EL1 = 32820 , ARM64_SYSREG_DBGBVR7_EL1 = 32828 , ARM64_SYSREG_DBGBVR8_EL1 = 32836 , ARM64_SYSREG_DBGBVR9_EL1 = 32844 , ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742 , ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734 , ARM64_SYSREG_DBGDTRRX_EL0 = 38952 , ARM64_SYSREG_DBGDTR_EL0 = 38944 , ARM64_SYSREG_DBGPRCR_EL1 = 32932 , ARM64_SYSREG_DBGVCR32_EL2 = 41016 , ARM64_SYSREG_DBGWCR0_EL1 = 32775 , ARM64_SYSREG_DBGWCR10_EL1 = 32855 , ARM64_SYSREG_DBGWCR11_EL1 = 32863 , ARM64_SYSREG_DBGWCR12_EL1 = 32871 , ARM64_SYSREG_DBGWCR13_EL1 = 32879 , ARM64_SYSREG_DBGWCR14_EL1 = 32887 , ARM64_SYSREG_DBGWCR15_EL1 = 32895 , ARM64_SYSREG_DBGWCR1_EL1 = 32783 , ARM64_SYSREG_DBGWCR2_EL1 = 32791 , ARM64_SYSREG_DBGWCR3_EL1 = 32799 , ARM64_SYSREG_DBGWCR4_EL1 = 32807 , ARM64_SYSREG_DBGWCR5_EL1 = 32815 , ARM64_SYSREG_DBGWCR6_EL1 = 32823 , ARM64_SYSREG_DBGWCR7_EL1 = 32831 , ARM64_SYSREG_DBGWCR8_EL1 = 32839 , ARM64_SYSREG_DBGWCR9_EL1 = 32847 , ARM64_SYSREG_DBGWVR0_EL1 = 32774 , ARM64_SYSREG_DBGWVR10_EL1 = 32854 , ARM64_SYSREG_DBGWVR11_EL1 = 32862 , ARM64_SYSREG_DBGWVR12_EL1 = 32870 , ARM64_SYSREG_DBGWVR13_EL1 = 32878 , ARM64_SYSREG_DBGWVR14_EL1 = 32886 , ARM64_SYSREG_DBGWVR15_EL1 = 32894 , ARM64_SYSREG_DBGWVR1_EL1 = 32782 , ARM64_SYSREG_DBGWVR2_EL1 = 32790 , ARM64_SYSREG_DBGWVR3_EL1 = 32798 , ARM64_SYSREG_DBGWVR4_EL1 = 32806 , ARM64_SYSREG_DBGWVR5_EL1 = 32814 , ARM64_SYSREG_DBGWVR6_EL1 = 32822 , ARM64_SYSREG_DBGWVR7_EL1 = 32830 , ARM64_SYSREG_DBGWVR8_EL1 = 32838 , ARM64_SYSREG_DBGWVR9_EL1 = 32846 , ARM64_SYSREG_DCZID_EL0 = 55303 , ARM64_SYSREG_DISR_EL1 = 50697 , ARM64_SYSREG_DIT = 55829 , ARM64_SYSREG_DLR_EL0 = 55849 , ARM64_SYSREG_DSPSR_EL0 = 55848 , ARM64_SYSREG_ELR_EL1 = 49665 , ARM64_SYSREG_ELR_EL12 = 59905 , ARM64_SYSREG_ELR_EL2 = 57857 , ARM64_SYSREG_ELR_EL3 = 61953 , ARM64_SYSREG_ERRIDR_EL1 = 49816 , ARM64_SYSREG_ERRSELR_EL1 = 49817 , ARM64_SYSREG_ERXADDR_EL1 = 49827 , ARM64_SYSREG_ERXCTLR_EL1 = 49825 , ARM64_SYSREG_ERXFR_EL1 = 49824 , ARM64_SYSREG_ERXMISC0_EL1 = 49832 , ARM64_SYSREG_ERXMISC1_EL1 = 49833 , ARM64_SYSREG_ERXMISC2_EL1 = 49834 , ARM64_SYSREG_ERXMISC3_EL1 = 49835 , ARM64_SYSREG_ERXPFGCDN_EL1 = 49830 , ARM64_SYSREG_ERXPFGCTL_EL1 = 49829 , ARM64_SYSREG_ERXPFGF_EL1 = 49828 , ARM64_SYSREG_ERXSTATUS_EL1 = 49826 , ARM64_SYSREG_ESR_EL1 = 49808 , ARM64_SYSREG_ESR_EL12 = 60048 , ARM64_SYSREG_ESR_EL2 = 58000 , ARM64_SYSREG_ESR_EL3 = 62096 , ARM64_SYSREG_FAR_EL1 = 49920 , ARM64_SYSREG_FAR_EL12 = 60160 , ARM64_SYSREG_FAR_EL2 = 58112 , ARM64_SYSREG_FAR_EL3 = 62208 , ARM64_SYSREG_FPCR = 55840 , ARM64_SYSREG_FPEXC32_EL2 = 58008 , ARM64_SYSREG_FPSR = 55841 , ARM64_SYSREG_GCR_EL1 = 49286 , ARM64_SYSREG_GMID_EL1 = 51204 , ARM64_SYSREG_GPCCR_EL3 = 61710 , ARM64_SYSREG_GPTBR_EL3 = 61708 , ARM64_SYSREG_HACR_EL2 = 57487 , ARM64_SYSREG_HCRX_EL2 = 57490 , ARM64_SYSREG_HCR_EL2 = 57480 , ARM64_SYSREG_HDFGRTR_EL2 = 57740 , ARM64_SYSREG_HDFGWTR_EL2 = 57741 , ARM64_SYSREG_HFGITR_EL2 = 57486 , ARM64_SYSREG_HFGRTR_EL2 = 57484 , ARM64_SYSREG_HFGWTR_EL2 = 57485 , ARM64_SYSREG_HPFAR_EL2 = 58116 , ARM64_SYSREG_HSTR_EL2 = 57483 , ARM64_SYSREG_ICC_AP0R0_EL1 = 50756 , ARM64_SYSREG_ICC_AP0R1_EL1 = 50757 , ARM64_SYSREG_ICC_AP0R2_EL1 = 50758 , ARM64_SYSREG_ICC_AP0R3_EL1 = 50759 , ARM64_SYSREG_ICC_AP1R0_EL1 = 50760 , ARM64_SYSREG_ICC_AP1R1_EL1 = 50761 , ARM64_SYSREG_ICC_AP1R2_EL1 = 50762 , ARM64_SYSREG_ICC_AP1R3_EL1 = 50763 , ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782 , ARM64_SYSREG_ICC_BPR0_EL1 = 50755 , ARM64_SYSREG_ICC_BPR1_EL1 = 50787 , ARM64_SYSREG_ICC_CTLR_EL1 = 50788 , ARM64_SYSREG_ICC_CTLR_EL3 = 63076 , ARM64_SYSREG_ICC_DIR_EL1 = 50777 , ARM64_SYSREG_ICC_EOIR0_EL1 = 50753 , ARM64_SYSREG_ICC_EOIR1_EL1 = 50785 , ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754 , ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786 , ARM64_SYSREG_ICC_IAR0_EL1 = 50752 , ARM64_SYSREG_ICC_IAR1_EL1 = 50784 , ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790 , ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791 , ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079 , ARM64_SYSREG_ICC_PMR_EL1 = 49712 , ARM64_SYSREG_ICC_RPR_EL1 = 50779 , ARM64_SYSREG_ICC_SGI0R_EL1 = 50783 , ARM64_SYSREG_ICC_SGI1R_EL1 = 50781 , ARM64_SYSREG_ICC_SRE_EL1 = 50789 , ARM64_SYSREG_ICC_SRE_EL2 = 58957 , ARM64_SYSREG_ICC_SRE_EL3 = 63077 , ARM64_SYSREG_ICH_AP0R0_EL2 = 58944 , ARM64_SYSREG_ICH_AP0R1_EL2 = 58945 , ARM64_SYSREG_ICH_AP0R2_EL2 = 58946 , ARM64_SYSREG_ICH_AP0R3_EL2 = 58947 , ARM64_SYSREG_ICH_AP1R0_EL2 = 58952 , ARM64_SYSREG_ICH_AP1R1_EL2 = 58953 , ARM64_SYSREG_ICH_AP1R2_EL2 = 58954 , ARM64_SYSREG_ICH_AP1R3_EL2 = 58955 , ARM64_SYSREG_ICH_EISR_EL2 = 58971 , ARM64_SYSREG_ICH_ELRSR_EL2 = 58973 , ARM64_SYSREG_ICH_HCR_EL2 = 58968 , ARM64_SYSREG_ICH_LR0_EL2 = 58976 , ARM64_SYSREG_ICH_LR10_EL2 = 58986 , ARM64_SYSREG_ICH_LR11_EL2 = 58987 , ARM64_SYSREG_ICH_LR12_EL2 = 58988 , ARM64_SYSREG_ICH_LR13_EL2 = 58989 , ARM64_SYSREG_ICH_LR14_EL2 = 58990 , ARM64_SYSREG_ICH_LR15_EL2 = 58991 , ARM64_SYSREG_ICH_LR1_EL2 = 58977 , ARM64_SYSREG_ICH_LR2_EL2 = 58978 , ARM64_SYSREG_ICH_LR3_EL2 = 58979 , ARM64_SYSREG_ICH_LR4_EL2 = 58980 , ARM64_SYSREG_ICH_LR5_EL2 = 58981 , ARM64_SYSREG_ICH_LR6_EL2 = 58982 , ARM64_SYSREG_ICH_LR7_EL2 = 58983 , ARM64_SYSREG_ICH_LR8_EL2 = 58984 , ARM64_SYSREG_ICH_LR9_EL2 = 58985 , ARM64_SYSREG_ICH_MISR_EL2 = 58970 , ARM64_SYSREG_ICH_VMCR_EL2 = 58975 , ARM64_SYSREG_ICH_VTR_EL2 = 58969 , ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196 , ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197 , ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192 , ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193 , ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200 , ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201 , ARM64_SYSREG_ID_AA64ISAR2_EL1 = 49202 , ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208 , ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209 , ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210 , ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184 , ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185 , ARM64_SYSREG_ID_AA64SMFR0_EL1 = 49189 , ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188 , ARM64_SYSREG_ID_AFR0_EL1 = 49163 , ARM64_SYSREG_ID_DFR0_EL1 = 49162 , ARM64_SYSREG_ID_ISAR0_EL1 = 49168 , ARM64_SYSREG_ID_ISAR1_EL1 = 49169 , ARM64_SYSREG_ID_ISAR2_EL1 = 49170 , ARM64_SYSREG_ID_ISAR3_EL1 = 49171 , ARM64_SYSREG_ID_ISAR4_EL1 = 49172 , ARM64_SYSREG_ID_ISAR5_EL1 = 49173 , ARM64_SYSREG_ID_ISAR6_EL1 = 49175 , ARM64_SYSREG_ID_MMFR0_EL1 = 49164 , ARM64_SYSREG_ID_MMFR1_EL1 = 49165 , ARM64_SYSREG_ID_MMFR2_EL1 = 49166 , ARM64_SYSREG_ID_MMFR3_EL1 = 49167 , ARM64_SYSREG_ID_MMFR4_EL1 = 49174 , ARM64_SYSREG_ID_MMFR5_EL1 = 49182 , ARM64_SYSREG_ID_PFR0_EL1 = 49160 , ARM64_SYSREG_ID_PFR1_EL1 = 49161 , ARM64_SYSREG_ID_PFR2_EL1 = 49180 , ARM64_SYSREG_IFSR32_EL2 = 57985 , ARM64_SYSREG_ISR_EL1 = 50696 , ARM64_SYSREG_LORC_EL1 = 50467 , ARM64_SYSREG_LOREA_EL1 = 50465 , ARM64_SYSREG_LORID_EL1 = 50471 , ARM64_SYSREG_LORN_EL1 = 50466 , ARM64_SYSREG_LORSA_EL1 = 50464 , ARM64_SYSREG_MAIR_EL1 = 50448 , ARM64_SYSREG_MAIR_EL12 = 60688 , ARM64_SYSREG_MAIR_EL2 = 58640 , ARM64_SYSREG_MAIR_EL3 = 62736 , ARM64_SYSREG_MDCCINT_EL1 = 32784 , ARM64_SYSREG_MDCCSR_EL0 = 38920 , ARM64_SYSREG_MDCR_EL2 = 57481 , ARM64_SYSREG_MDCR_EL3 = 61593 , ARM64_SYSREG_MDRAR_EL1 = 32896 , ARM64_SYSREG_MDSCR_EL1 = 32786 , ARM64_SYSREG_MFAR_EL3 = 62213 , ARM64_SYSREG_MIDR_EL1 = 49152 , ARM64_SYSREG_MPAM0_EL1 = 50473 , ARM64_SYSREG_MPAM1_EL1 = 50472 , ARM64_SYSREG_MPAM1_EL12 = 60712 , ARM64_SYSREG_MPAM2_EL2 = 58664 , ARM64_SYSREG_MPAM3_EL3 = 62760 , ARM64_SYSREG_MPAMHCR_EL2 = 58656 , ARM64_SYSREG_MPAMIDR_EL1 = 50468 , ARM64_SYSREG_MPAMSM_EL1 = 50475 , ARM64_SYSREG_MPAMVPM0_EL2 = 58672 , ARM64_SYSREG_MPAMVPM1_EL2 = 58673 , ARM64_SYSREG_MPAMVPM2_EL2 = 58674 , ARM64_SYSREG_MPAMVPM3_EL2 = 58675 , ARM64_SYSREG_MPAMVPM4_EL2 = 58676 , ARM64_SYSREG_MPAMVPM5_EL2 = 58677 , ARM64_SYSREG_MPAMVPM6_EL2 = 58678 , ARM64_SYSREG_MPAMVPM7_EL2 = 58679 , ARM64_SYSREG_MPAMVPMV_EL2 = 58657 , ARM64_SYSREG_MPIDR_EL1 = 49157 , ARM64_SYSREG_MPUIR_EL1 = 49156 , ARM64_SYSREG_MPUIR_EL2 = 57348 , ARM64_SYSREG_MVFR0_EL1 = 49176 , ARM64_SYSREG_MVFR1_EL1 = 49177 , ARM64_SYSREG_MVFR2_EL1 = 49178 , ARM64_SYSREG_NZCV = 55824 , ARM64_SYSREG_OSDLR_EL1 = 32924 , ARM64_SYSREG_OSDTRRX_EL1 = 32770 , ARM64_SYSREG_OSDTRTX_EL1 = 32794 , ARM64_SYSREG_OSECCR_EL1 = 32818 , ARM64_SYSREG_OSLAR_EL1 = 32900 , ARM64_SYSREG_OSLSR_EL1 = 32908 , ARM64_SYSREG_PAN = 49683 , ARM64_SYSREG_PAR_EL1 = 50080 , ARM64_SYSREG_PMBIDR_EL1 = 50391 , ARM64_SYSREG_PMBLIMITR_EL1 = 50384 , ARM64_SYSREG_PMBPTR_EL1 = 50385 , ARM64_SYSREG_PMBSR_EL1 = 50387 , ARM64_SYSREG_PMCCFILTR_EL0 = 57215 , ARM64_SYSREG_PMCCNTR_EL0 = 56552 , ARM64_SYSREG_PMCEID0_EL0 = 56550 , ARM64_SYSREG_PMCEID1_EL0 = 56551 , ARM64_SYSREG_PMCNTENCLR_EL0 = 56546 , ARM64_SYSREG_PMCNTENSET_EL0 = 56545 , ARM64_SYSREG_PMCR_EL0 = 56544 , ARM64_SYSREG_PMEVCNTR0_EL0 = 57152 , ARM64_SYSREG_PMEVCNTR10_EL0 = 57162 , ARM64_SYSREG_PMEVCNTR11_EL0 = 57163 , ARM64_SYSREG_PMEVCNTR12_EL0 = 57164 , ARM64_SYSREG_PMEVCNTR13_EL0 = 57165 , ARM64_SYSREG_PMEVCNTR14_EL0 = 57166 , ARM64_SYSREG_PMEVCNTR15_EL0 = 57167 , ARM64_SYSREG_PMEVCNTR16_EL0 = 57168 , ARM64_SYSREG_PMEVCNTR17_EL0 = 57169 , ARM64_SYSREG_PMEVCNTR18_EL0 = 57170 , ARM64_SYSREG_PMEVCNTR19_EL0 = 57171 , ARM64_SYSREG_PMEVCNTR1_EL0 = 57153 , ARM64_SYSREG_PMEVCNTR20_EL0 = 57172 , ARM64_SYSREG_PMEVCNTR21_EL0 = 57173 , ARM64_SYSREG_PMEVCNTR22_EL0 = 57174 , ARM64_SYSREG_PMEVCNTR23_EL0 = 57175 , ARM64_SYSREG_PMEVCNTR24_EL0 = 57176 , ARM64_SYSREG_PMEVCNTR25_EL0 = 57177 , ARM64_SYSREG_PMEVCNTR26_EL0 = 57178 , ARM64_SYSREG_PMEVCNTR27_EL0 = 57179 , ARM64_SYSREG_PMEVCNTR28_EL0 = 57180 , ARM64_SYSREG_PMEVCNTR29_EL0 = 57181 , ARM64_SYSREG_PMEVCNTR2_EL0 = 57154 , ARM64_SYSREG_PMEVCNTR30_EL0 = 57182 , ARM64_SYSREG_PMEVCNTR3_EL0 = 57155 , ARM64_SYSREG_PMEVCNTR4_EL0 = 57156 , ARM64_SYSREG_PMEVCNTR5_EL0 = 57157 , ARM64_SYSREG_PMEVCNTR6_EL0 = 57158 , ARM64_SYSREG_PMEVCNTR7_EL0 = 57159 , ARM64_SYSREG_PMEVCNTR8_EL0 = 57160 , ARM64_SYSREG_PMEVCNTR9_EL0 = 57161 , ARM64_SYSREG_PMEVTYPER0_EL0 = 57184 , ARM64_SYSREG_PMEVTYPER10_EL0 = 57194 , ARM64_SYSREG_PMEVTYPER11_EL0 = 57195 , ARM64_SYSREG_PMEVTYPER12_EL0 = 57196 , ARM64_SYSREG_PMEVTYPER13_EL0 = 57197 , ARM64_SYSREG_PMEVTYPER14_EL0 = 57198 , ARM64_SYSREG_PMEVTYPER15_EL0 = 57199 , ARM64_SYSREG_PMEVTYPER16_EL0 = 57200 , ARM64_SYSREG_PMEVTYPER17_EL0 = 57201 , ARM64_SYSREG_PMEVTYPER18_EL0 = 57202 , ARM64_SYSREG_PMEVTYPER19_EL0 = 57203 , ARM64_SYSREG_PMEVTYPER1_EL0 = 57185 , ARM64_SYSREG_PMEVTYPER20_EL0 = 57204 , ARM64_SYSREG_PMEVTYPER21_EL0 = 57205 , ARM64_SYSREG_PMEVTYPER22_EL0 = 57206 , ARM64_SYSREG_PMEVTYPER23_EL0 = 57207 , ARM64_SYSREG_PMEVTYPER24_EL0 = 57208 , ARM64_SYSREG_PMEVTYPER25_EL0 = 57209 , ARM64_SYSREG_PMEVTYPER26_EL0 = 57210 , ARM64_SYSREG_PMEVTYPER27_EL0 = 57211 , ARM64_SYSREG_PMEVTYPER28_EL0 = 57212 , ARM64_SYSREG_PMEVTYPER29_EL0 = 57213 , ARM64_SYSREG_PMEVTYPER2_EL0 = 57186 , ARM64_SYSREG_PMEVTYPER30_EL0 = 57214 , ARM64_SYSREG_PMEVTYPER3_EL0 = 57187 , ARM64_SYSREG_PMEVTYPER4_EL0 = 57188 , ARM64_SYSREG_PMEVTYPER5_EL0 = 57189 , ARM64_SYSREG_PMEVTYPER6_EL0 = 57190 , ARM64_SYSREG_PMEVTYPER7_EL0 = 57191 , ARM64_SYSREG_PMEVTYPER8_EL0 = 57192 , ARM64_SYSREG_PMEVTYPER9_EL0 = 57193 , ARM64_SYSREG_PMINTENCLR_EL1 = 50418 , ARM64_SYSREG_PMINTENSET_EL1 = 50417 , ARM64_SYSREG_PMMIR_EL1 = 50422 , ARM64_SYSREG_PMOVSCLR_EL0 = 56547 , ARM64_SYSREG_PMOVSSET_EL0 = 56563 , ARM64_SYSREG_PMSCR_EL1 = 50376 , ARM64_SYSREG_PMSCR_EL12 = 60616 , ARM64_SYSREG_PMSCR_EL2 = 58568 , ARM64_SYSREG_PMSELR_EL0 = 56549 , ARM64_SYSREG_PMSEVFR_EL1 = 50381 , ARM64_SYSREG_PMSFCR_EL1 = 50380 , ARM64_SYSREG_PMSICR_EL1 = 50378 , ARM64_SYSREG_PMSIDR_EL1 = 50383 , ARM64_SYSREG_PMSIRR_EL1 = 50379 , ARM64_SYSREG_PMSLATFR_EL1 = 50382 , ARM64_SYSREG_PMSNEVFR_EL1 = 50377 , ARM64_SYSREG_PMSWINC_EL0 = 56548 , ARM64_SYSREG_PMUSERENR_EL0 = 56560 , ARM64_SYSREG_PMXEVCNTR_EL0 = 56554 , ARM64_SYSREG_PMXEVTYPER_EL0 = 56553 , ARM64_SYSREG_PRBAR10_EL1 = 50024 , ARM64_SYSREG_PRBAR10_EL2 = 58216 , ARM64_SYSREG_PRBAR11_EL1 = 50028 , ARM64_SYSREG_PRBAR11_EL2 = 58220 , ARM64_SYSREG_PRBAR12_EL1 = 50032 , ARM64_SYSREG_PRBAR12_EL2 = 58224 , ARM64_SYSREG_PRBAR13_EL1 = 50036 , ARM64_SYSREG_PRBAR13_EL2 = 58228 , ARM64_SYSREG_PRBAR14_EL1 = 50040 , ARM64_SYSREG_PRBAR14_EL2 = 58232 , ARM64_SYSREG_PRBAR15_EL1 = 50044 , ARM64_SYSREG_PRBAR15_EL2 = 58236 , ARM64_SYSREG_PRBAR1_EL1 = 49988 , ARM64_SYSREG_PRBAR1_EL2 = 58180 , ARM64_SYSREG_PRBAR2_EL1 = 49992 , ARM64_SYSREG_PRBAR2_EL2 = 58184 , ARM64_SYSREG_PRBAR3_EL1 = 49996 , ARM64_SYSREG_PRBAR3_EL2 = 58188 , ARM64_SYSREG_PRBAR4_EL1 = 50000 , ARM64_SYSREG_PRBAR4_EL2 = 58192 , ARM64_SYSREG_PRBAR5_EL1 = 50004 , ARM64_SYSREG_PRBAR5_EL2 = 58196 , ARM64_SYSREG_PRBAR6_EL1 = 50008 , ARM64_SYSREG_PRBAR6_EL2 = 58200 , ARM64_SYSREG_PRBAR7_EL1 = 50012 , ARM64_SYSREG_PRBAR7_EL2 = 58204 , ARM64_SYSREG_PRBAR8_EL1 = 50016 , ARM64_SYSREG_PRBAR8_EL2 = 58208 , ARM64_SYSREG_PRBAR9_EL1 = 50020 , ARM64_SYSREG_PRBAR9_EL2 = 58212 , ARM64_SYSREG_PRBAR_EL1 = 49984 , ARM64_SYSREG_PRBAR_EL2 = 58176 , ARM64_SYSREG_PRENR_EL1 = 49929 , ARM64_SYSREG_PRENR_EL2 = 58121 , ARM64_SYSREG_PRLAR10_EL1 = 50025 , ARM64_SYSREG_PRLAR10_EL2 = 58217 , ARM64_SYSREG_PRLAR11_EL1 = 50029 , ARM64_SYSREG_PRLAR11_EL2 = 58221 , ARM64_SYSREG_PRLAR12_EL1 = 50033 , ARM64_SYSREG_PRLAR12_EL2 = 58225 , ARM64_SYSREG_PRLAR13_EL1 = 50037 , ARM64_SYSREG_PRLAR13_EL2 = 58229 , ARM64_SYSREG_PRLAR14_EL1 = 50041 , ARM64_SYSREG_PRLAR14_EL2 = 58233 , ARM64_SYSREG_PRLAR15_EL1 = 50045 , ARM64_SYSREG_PRLAR15_EL2 = 58237 , ARM64_SYSREG_PRLAR1_EL1 = 49989 , ARM64_SYSREG_PRLAR1_EL2 = 58181 , ARM64_SYSREG_PRLAR2_EL1 = 49993 , ARM64_SYSREG_PRLAR2_EL2 = 58185 , ARM64_SYSREG_PRLAR3_EL1 = 49997 , ARM64_SYSREG_PRLAR3_EL2 = 58189 , ARM64_SYSREG_PRLAR4_EL1 = 50001 , ARM64_SYSREG_PRLAR4_EL2 = 58193 , ARM64_SYSREG_PRLAR5_EL1 = 50005 , ARM64_SYSREG_PRLAR5_EL2 = 58197 , ARM64_SYSREG_PRLAR6_EL1 = 50009 , ARM64_SYSREG_PRLAR6_EL2 = 58201 , ARM64_SYSREG_PRLAR7_EL1 = 50013 , ARM64_SYSREG_PRLAR7_EL2 = 58205 , ARM64_SYSREG_PRLAR8_EL1 = 50017 , ARM64_SYSREG_PRLAR8_EL2 = 58209 , ARM64_SYSREG_PRLAR9_EL1 = 50021 , ARM64_SYSREG_PRLAR9_EL2 = 58213 , ARM64_SYSREG_PRLAR_EL1 = 49985 , ARM64_SYSREG_PRLAR_EL2 = 58177 , ARM64_SYSREG_PRSELR_EL1 = 49937 , ARM64_SYSREG_PRSELR_EL2 = 58129 , ARM64_SYSREG_REVIDR_EL1 = 49158 , ARM64_SYSREG_RGSR_EL1 = 49285 , ARM64_SYSREG_RMR_EL1 = 50690 , ARM64_SYSREG_RMR_EL2 = 58882 , ARM64_SYSREG_RMR_EL3 = 62978 , ARM64_SYSREG_RNDR = 55584 , ARM64_SYSREG_RNDRRS = 55585 , ARM64_SYSREG_RVBAR_EL1 = 50689 , ARM64_SYSREG_RVBAR_EL2 = 58881 , ARM64_SYSREG_RVBAR_EL3 = 62977 , ARM64_SYSREG_SCR_EL3 = 61576 , ARM64_SYSREG_SCTLR_EL1 = 49280 , ARM64_SYSREG_SCTLR_EL12 = 59520 , ARM64_SYSREG_SCTLR_EL2 = 57472 , ARM64_SYSREG_SCTLR_EL3 = 61568 , ARM64_SYSREG_SCXTNUM_EL0 = 56967 , ARM64_SYSREG_SCXTNUM_EL1 = 50823 , ARM64_SYSREG_SCXTNUM_EL12 = 61063 , ARM64_SYSREG_SCXTNUM_EL2 = 59015 , ARM64_SYSREG_SCXTNUM_EL3 = 63111 , ARM64_SYSREG_SDER32_EL2 = 57497 , ARM64_SYSREG_SDER32_EL3 = 61577 , ARM64_SYSREG_SMCR_EL1 = 49302 , ARM64_SYSREG_SMCR_EL12 = 59542 , ARM64_SYSREG_SMCR_EL2 = 57494 , ARM64_SYSREG_SMCR_EL3 = 61590 , ARM64_SYSREG_SMIDR_EL1 = 51206 , ARM64_SYSREG_SMPRIMAP_EL2 = 57493 , ARM64_SYSREG_SMPRI_EL1 = 49300 , ARM64_SYSREG_SPSEL = 49680 , ARM64_SYSREG_SPSR_ABT = 57881 , ARM64_SYSREG_SPSR_EL1 = 49664 , ARM64_SYSREG_SPSR_EL12 = 59904 , ARM64_SYSREG_SPSR_EL2 = 57856 , ARM64_SYSREG_SPSR_EL3 = 61952 , ARM64_SYSREG_SPSR_FIQ = 57883 , ARM64_SYSREG_SPSR_IRQ = 57880 , ARM64_SYSREG_SPSR_UND = 57882 , ARM64_SYSREG_SP_EL0 = 49672 , ARM64_SYSREG_SP_EL1 = 57864 , ARM64_SYSREG_SP_EL2 = 61960 , ARM64_SYSREG_SSBS = 55830 , ARM64_SYSREG_SVCR = 55826 , ARM64_SYSREG_TCO = 55831 , ARM64_SYSREG_TCR_EL1 = 49410 , ARM64_SYSREG_TCR_EL12 = 59650 , ARM64_SYSREG_TCR_EL2 = 57602 , ARM64_SYSREG_TCR_EL3 = 61698 , ARM64_SYSREG_TEECR32_EL1 = 36864 , ARM64_SYSREG_TEEHBR32_EL1 = 36992 , ARM64_SYSREG_TFSRE0_EL1 = 49841 , ARM64_SYSREG_TFSR_EL1 = 49840 , ARM64_SYSREG_TFSR_EL12 = 60080 , ARM64_SYSREG_TFSR_EL2 = 58032 , ARM64_SYSREG_TFSR_EL3 = 62128 , ARM64_SYSREG_TPIDR2_EL0 = 56965 , ARM64_SYSREG_TPIDRRO_EL0 = 56963 , ARM64_SYSREG_TPIDR_EL0 = 56962 , ARM64_SYSREG_TPIDR_EL1 = 50820 , ARM64_SYSREG_TPIDR_EL2 = 59010 , ARM64_SYSREG_TPIDR_EL3 = 63106 , ARM64_SYSREG_TRBBASER_EL1 = 50394 , ARM64_SYSREG_TRBIDR_EL1 = 50399 , ARM64_SYSREG_TRBLIMITR_EL1 = 50392 , ARM64_SYSREG_TRBMAR_EL1 = 50396 , ARM64_SYSREG_TRBPTR_EL1 = 50393 , ARM64_SYSREG_TRBSR_EL1 = 50395 , ARM64_SYSREG_TRBTRG_EL1 = 50398 , ARM64_SYSREG_TRCACATR0 = 35074 , ARM64_SYSREG_TRCACATR1 = 35090 , ARM64_SYSREG_TRCACATR10 = 35107 , ARM64_SYSREG_TRCACATR11 = 35123 , ARM64_SYSREG_TRCACATR12 = 35139 , ARM64_SYSREG_TRCACATR13 = 35155 , ARM64_SYSREG_TRCACATR14 = 35171 , ARM64_SYSREG_TRCACATR15 = 35187 , ARM64_SYSREG_TRCACATR2 = 35106 , ARM64_SYSREG_TRCACATR3 = 35122 , ARM64_SYSREG_TRCACATR4 = 35138 , ARM64_SYSREG_TRCACATR5 = 35154 , ARM64_SYSREG_TRCACATR6 = 35170 , ARM64_SYSREG_TRCACATR7 = 35186 , ARM64_SYSREG_TRCACATR8 = 35075 , ARM64_SYSREG_TRCACATR9 = 35091 , ARM64_SYSREG_TRCACVR0 = 35072 , ARM64_SYSREG_TRCACVR1 = 35088 , ARM64_SYSREG_TRCACVR10 = 35105 , ARM64_SYSREG_TRCACVR11 = 35121 , ARM64_SYSREG_TRCACVR12 = 35137 , ARM64_SYSREG_TRCACVR13 = 35153 , ARM64_SYSREG_TRCACVR14 = 35169 , ARM64_SYSREG_TRCACVR15 = 35185 , ARM64_SYSREG_TRCACVR2 = 35104 , ARM64_SYSREG_TRCACVR3 = 35120 , ARM64_SYSREG_TRCACVR4 = 35136 , ARM64_SYSREG_TRCACVR5 = 35152 , ARM64_SYSREG_TRCACVR6 = 35168 , ARM64_SYSREG_TRCACVR7 = 35184 , ARM64_SYSREG_TRCACVR8 = 35073 , ARM64_SYSREG_TRCACVR9 = 35089 , ARM64_SYSREG_TRCAUTHSTATUS = 35830 , ARM64_SYSREG_TRCAUXCTLR = 34864 , ARM64_SYSREG_TRCBBCTLR = 34936 , ARM64_SYSREG_TRCCCCTLR = 34928 , ARM64_SYSREG_TRCCIDCCTLR0 = 35202 , ARM64_SYSREG_TRCCIDCCTLR1 = 35210 , ARM64_SYSREG_TRCCIDCVR0 = 35200 , ARM64_SYSREG_TRCCIDCVR1 = 35216 , ARM64_SYSREG_TRCCIDCVR2 = 35232 , ARM64_SYSREG_TRCCIDCVR3 = 35248 , ARM64_SYSREG_TRCCIDCVR4 = 35264 , ARM64_SYSREG_TRCCIDCVR5 = 35280 , ARM64_SYSREG_TRCCIDCVR6 = 35296 , ARM64_SYSREG_TRCCIDCVR7 = 35312 , ARM64_SYSREG_TRCCIDR0 = 35815 , ARM64_SYSREG_TRCCIDR1 = 35823 , ARM64_SYSREG_TRCCIDR2 = 35831 , ARM64_SYSREG_TRCCIDR3 = 35839 , ARM64_SYSREG_TRCCLAIMCLR = 35790 , ARM64_SYSREG_TRCCLAIMSET = 35782 , ARM64_SYSREG_TRCCNTCTLR0 = 34853 , ARM64_SYSREG_TRCCNTCTLR1 = 34861 , ARM64_SYSREG_TRCCNTCTLR2 = 34869 , ARM64_SYSREG_TRCCNTCTLR3 = 34877 , ARM64_SYSREG_TRCCNTRLDVR0 = 34821 , ARM64_SYSREG_TRCCNTRLDVR1 = 34829 , ARM64_SYSREG_TRCCNTRLDVR2 = 34837 , ARM64_SYSREG_TRCCNTRLDVR3 = 34845 , ARM64_SYSREG_TRCCNTVR0 = 34885 , ARM64_SYSREG_TRCCNTVR1 = 34893 , ARM64_SYSREG_TRCCNTVR2 = 34901 , ARM64_SYSREG_TRCCNTVR3 = 34909 , ARM64_SYSREG_TRCCONFIGR = 34848 , ARM64_SYSREG_TRCDEVAFF0 = 35798 , ARM64_SYSREG_TRCDEVAFF1 = 35806 , ARM64_SYSREG_TRCDEVARCH = 35838 , ARM64_SYSREG_TRCDEVID = 35735 , ARM64_SYSREG_TRCDEVTYPE = 35743 , ARM64_SYSREG_TRCDVCMR0 = 35078 , ARM64_SYSREG_TRCDVCMR1 = 35110 , ARM64_SYSREG_TRCDVCMR2 = 35142 , ARM64_SYSREG_TRCDVCMR3 = 35174 , ARM64_SYSREG_TRCDVCMR4 = 35079 , ARM64_SYSREG_TRCDVCMR5 = 35111 , ARM64_SYSREG_TRCDVCMR6 = 35143 , ARM64_SYSREG_TRCDVCMR7 = 35175 , ARM64_SYSREG_TRCDVCVR0 = 35076 , ARM64_SYSREG_TRCDVCVR1 = 35108 , ARM64_SYSREG_TRCDVCVR2 = 35140 , ARM64_SYSREG_TRCDVCVR3 = 35172 , ARM64_SYSREG_TRCDVCVR4 = 35077 , ARM64_SYSREG_TRCDVCVR5 = 35109 , ARM64_SYSREG_TRCDVCVR6 = 35141 , ARM64_SYSREG_TRCDVCVR7 = 35173 , ARM64_SYSREG_TRCEVENTCTL0R = 34880 , ARM64_SYSREG_TRCEVENTCTL1R = 34888 , ARM64_SYSREG_TRCEXTINSELR = 34884 , ARM64_SYSREG_TRCEXTINSELR1 = 34892 , ARM64_SYSREG_TRCEXTINSELR2 = 34900 , ARM64_SYSREG_TRCEXTINSELR3 = 34908 , ARM64_SYSREG_TRCIDR0 = 34887 , ARM64_SYSREG_TRCIDR1 = 34895 , ARM64_SYSREG_TRCIDR10 = 34838 , ARM64_SYSREG_TRCIDR11 = 34846 , ARM64_SYSREG_TRCIDR12 = 34854 , ARM64_SYSREG_TRCIDR13 = 34862 , ARM64_SYSREG_TRCIDR2 = 34903 , ARM64_SYSREG_TRCIDR3 = 34911 , ARM64_SYSREG_TRCIDR4 = 34919 , ARM64_SYSREG_TRCIDR5 = 34927 , ARM64_SYSREG_TRCIDR6 = 34935 , ARM64_SYSREG_TRCIDR7 = 34943 , ARM64_SYSREG_TRCIDR8 = 34822 , ARM64_SYSREG_TRCIDR9 = 34830 , ARM64_SYSREG_TRCIMSPEC0 = 34823 , ARM64_SYSREG_TRCIMSPEC1 = 34831 , ARM64_SYSREG_TRCIMSPEC2 = 34839 , ARM64_SYSREG_TRCIMSPEC3 = 34847 , ARM64_SYSREG_TRCIMSPEC4 = 34855 , ARM64_SYSREG_TRCIMSPEC5 = 34863 , ARM64_SYSREG_TRCIMSPEC6 = 34871 , ARM64_SYSREG_TRCIMSPEC7 = 34879 , ARM64_SYSREG_TRCITCTRL = 35716 , ARM64_SYSREG_TRCLAR = 35814 , ARM64_SYSREG_TRCLSR = 35822 , ARM64_SYSREG_TRCOSLAR = 34948 , ARM64_SYSREG_TRCOSLSR = 34956 , ARM64_SYSREG_TRCPDCR = 34980 , ARM64_SYSREG_TRCPDSR = 34988 , ARM64_SYSREG_TRCPIDR0 = 35783 , ARM64_SYSREG_TRCPIDR1 = 35791 , ARM64_SYSREG_TRCPIDR2 = 35799 , ARM64_SYSREG_TRCPIDR3 = 35807 , ARM64_SYSREG_TRCPIDR4 = 35751 , ARM64_SYSREG_TRCPIDR5 = 35759 , ARM64_SYSREG_TRCPIDR6 = 35767 , ARM64_SYSREG_TRCPIDR7 = 35775 , ARM64_SYSREG_TRCPRGCTLR = 34824 , ARM64_SYSREG_TRCPROCSELR = 34832 , ARM64_SYSREG_TRCQCTLR = 34825 , ARM64_SYSREG_TRCRSCTLR10 = 35024 , ARM64_SYSREG_TRCRSCTLR11 = 35032 , ARM64_SYSREG_TRCRSCTLR12 = 35040 , ARM64_SYSREG_TRCRSCTLR13 = 35048 , ARM64_SYSREG_TRCRSCTLR14 = 35056 , ARM64_SYSREG_TRCRSCTLR15 = 35064 , ARM64_SYSREG_TRCRSCTLR16 = 34945 , ARM64_SYSREG_TRCRSCTLR17 = 34953 , ARM64_SYSREG_TRCRSCTLR18 = 34961 , ARM64_SYSREG_TRCRSCTLR19 = 34969 , ARM64_SYSREG_TRCRSCTLR2 = 34960 , ARM64_SYSREG_TRCRSCTLR20 = 34977 , ARM64_SYSREG_TRCRSCTLR21 = 34985 , ARM64_SYSREG_TRCRSCTLR22 = 34993 , ARM64_SYSREG_TRCRSCTLR23 = 35001 , ARM64_SYSREG_TRCRSCTLR24 = 35009 , ARM64_SYSREG_TRCRSCTLR25 = 35017 , ARM64_SYSREG_TRCRSCTLR26 = 35025 , ARM64_SYSREG_TRCRSCTLR27 = 35033 , ARM64_SYSREG_TRCRSCTLR28 = 35041 , ARM64_SYSREG_TRCRSCTLR29 = 35049 , ARM64_SYSREG_TRCRSCTLR3 = 34968 , ARM64_SYSREG_TRCRSCTLR30 = 35057 , ARM64_SYSREG_TRCRSCTLR31 = 35065 , ARM64_SYSREG_TRCRSCTLR4 = 34976 , ARM64_SYSREG_TRCRSCTLR5 = 34984 , ARM64_SYSREG_TRCRSCTLR6 = 34992 , ARM64_SYSREG_TRCRSCTLR7 = 35000 , ARM64_SYSREG_TRCRSCTLR8 = 35008 , ARM64_SYSREG_TRCRSCTLR9 = 35016 , ARM64_SYSREG_TRCRSR = 34896 , ARM64_SYSREG_TRCSEQEVR0 = 34820 , ARM64_SYSREG_TRCSEQEVR1 = 34828 , ARM64_SYSREG_TRCSEQEVR2 = 34836 , ARM64_SYSREG_TRCSEQRSTEVR = 34868 , ARM64_SYSREG_TRCSEQSTR = 34876 , ARM64_SYSREG_TRCSSCCR0 = 34946 , ARM64_SYSREG_TRCSSCCR1 = 34954 , ARM64_SYSREG_TRCSSCCR2 = 34962 , ARM64_SYSREG_TRCSSCCR3 = 34970 , ARM64_SYSREG_TRCSSCCR4 = 34978 , ARM64_SYSREG_TRCSSCCR5 = 34986 , ARM64_SYSREG_TRCSSCCR6 = 34994 , ARM64_SYSREG_TRCSSCCR7 = 35002 , ARM64_SYSREG_TRCSSCSR0 = 35010 , ARM64_SYSREG_TRCSSCSR1 = 35018 , ARM64_SYSREG_TRCSSCSR2 = 35026 , ARM64_SYSREG_TRCSSCSR3 = 35034 , ARM64_SYSREG_TRCSSCSR4 = 35042 , ARM64_SYSREG_TRCSSCSR5 = 35050 , ARM64_SYSREG_TRCSSCSR6 = 35058 , ARM64_SYSREG_TRCSSCSR7 = 35066 , ARM64_SYSREG_TRCSSPCICR0 = 34947 , ARM64_SYSREG_TRCSSPCICR1 = 34955 , ARM64_SYSREG_TRCSSPCICR2 = 34963 , ARM64_SYSREG_TRCSSPCICR3 = 34971 , ARM64_SYSREG_TRCSSPCICR4 = 34979 , ARM64_SYSREG_TRCSSPCICR5 = 34987 , ARM64_SYSREG_TRCSSPCICR6 = 34995 , ARM64_SYSREG_TRCSSPCICR7 = 35003 , ARM64_SYSREG_TRCSTALLCTLR = 34904 , ARM64_SYSREG_TRCSTATR = 34840 , ARM64_SYSREG_TRCSYNCPR = 34920 , ARM64_SYSREG_TRCTRACEIDR = 34817 , ARM64_SYSREG_TRCTSCTLR = 34912 , ARM64_SYSREG_TRCVDARCCTLR = 34898 , ARM64_SYSREG_TRCVDCTLR = 34882 , ARM64_SYSREG_TRCVDSACCTLR = 34890 , ARM64_SYSREG_TRCVICTLR = 34818 , ARM64_SYSREG_TRCVIIECTLR = 34826 , ARM64_SYSREG_TRCVIPCSSCTLR = 34842 , ARM64_SYSREG_TRCVISSCTLR = 34834 , ARM64_SYSREG_TRCVMIDCCTLR0 = 35218 , ARM64_SYSREG_TRCVMIDCCTLR1 = 35226 , ARM64_SYSREG_TRCVMIDCVR0 = 35201 , ARM64_SYSREG_TRCVMIDCVR1 = 35217 , ARM64_SYSREG_TRCVMIDCVR2 = 35233 , ARM64_SYSREG_TRCVMIDCVR3 = 35249 , ARM64_SYSREG_TRCVMIDCVR4 = 35265 , ARM64_SYSREG_TRCVMIDCVR5 = 35281 , ARM64_SYSREG_TRCVMIDCVR6 = 35297 , ARM64_SYSREG_TRCVMIDCVR7 = 35313 , ARM64_SYSREG_TRFCR_EL1 = 49297 , ARM64_SYSREG_TRFCR_EL12 = 59537 , ARM64_SYSREG_TRFCR_EL2 = 57489 , ARM64_SYSREG_TTBR0_EL1 = 49408 , ARM64_SYSREG_TTBR0_EL12 = 59648 , ARM64_SYSREG_TTBR0_EL2 = 57600 , ARM64_SYSREG_TTBR0_EL3 = 61696 , ARM64_SYSREG_TTBR1_EL1 = 49409 , ARM64_SYSREG_TTBR1_EL12 = 59649 , ARM64_SYSREG_TTBR1_EL2 = 57601 , ARM64_SYSREG_UAO = 49684 , ARM64_SYSREG_VBAR_EL1 = 50688 , ARM64_SYSREG_VBAR_EL12 = 60928 , ARM64_SYSREG_VBAR_EL2 = 58880 , ARM64_SYSREG_VBAR_EL3 = 62976 , ARM64_SYSREG_VDISR_EL2 = 58889 , ARM64_SYSREG_VMPIDR_EL2 = 57349 , ARM64_SYSREG_VNCR_EL2 = 57616 , ARM64_SYSREG_VPIDR_EL2 = 57344 , ARM64_SYSREG_VSESR_EL2 = 58003 , ARM64_SYSREG_VSTCR_EL2 = 57650 , ARM64_SYSREG_VSTTBR_EL2 = 57648 , ARM64_SYSREG_VTCR_EL2 = 57610 , ARM64_SYSREG_VTTBR_EL2 = 57608 , ARM64_SYSREG_ZCR_EL1 = 49296 , ARM64_SYSREG_ZCR_EL12 = 59536 , ARM64_SYSREG_ZCR_EL2 = 57488 , ARM64_SYSREG_ZCR_EL3 = 61584 , } # [repr (u32)] # [doc = " System PState Field (MSR instruction)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_pstate { ARM64_PSTATE_INVALID = 0 , ARM64_PSTATE_SPSEL = 5 , ARM64_PSTATE_DAIFSET = 30 , ARM64_PSTATE_DAIFCLR = 31 , ARM64_PSTATE_PAN = 4 , ARM64_PSTATE_UAO = 3 , ARM64_PSTATE_DIT = 26 , } # [repr (u32)] # [doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_vas { ARM64_VAS_INVALID = 0 , ARM64_VAS_16B = 1 , ARM64_VAS_8B = 2 , ARM64_VAS_4B = 3 , ARM64_VAS_1B = 4 , ARM64_VAS_8H = 5 , ARM64_VAS_4H = 6 , ARM64_VAS_2H = 7 , ARM64_VAS_1H = 8 , ARM64_VAS_4S = 9 , ARM64_VAS_2S = 10 , ARM64_VAS_1S = 11 , ARM64_VAS_2D = 12 , ARM64_VAS_1D = 13 , ARM64_VAS_1Q = 14 , } # [repr (u32)] # [doc = " Memory barrier operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0 , ARM64_BARRIER_OSHLD = 1 , ARM64_BARRIER_OSHST = 2 , ARM64_BARRIER_OSH = 3 , ARM64_BARRIER_NSHLD = 5 , ARM64_BARRIER_NSHST = 6 , ARM64_BARRIER_NSH = 7 , ARM64_BARRIER_ISHLD = 9 , ARM64_BARRIER_ISHST = 10 , ARM64_BARRIER_ISH = 11 , ARM64_BARRIER_LD = 13 , ARM64_BARRIER_ST = 14 , ARM64_BARRIER_SY = 15 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM64_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM64_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM64_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM64_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM64_OP_FP = 4 , # [doc = "< C-Immediate"] ARM64_OP_CIMM = 64 , # [doc = "< MRS register operand."] ARM64_OP_REG_MRS = 65 , # [doc = "< MSR register operand."] ARM64_OP_REG_MSR = 66 , # [doc = "< PState operand."] ARM64_OP_PSTATE = 67 , # [doc = "< SYS operand for IC/DC/AT/TLBI instructions."] ARM64_OP_SYS = 68 , # [doc = "< SVCR operand for MSR SVCR instructions."] ARM64_OP_SVCR = 69 , # [doc = "< Prefetch operand (PRFM)."] ARM64_OP_PREFETCH = 70 , # [doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."] ARM64_OP_BARRIER = 71 , # [doc = "< SME instruction operand with with index."] ARM64_OP_SME_INDEX = 72 , } # [repr (u32)] # [doc = " SYS operands (IC/DC/AC/TLBI)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sys_op { ARM64_SYS_INVALID = 0 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1 = 1 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1IS = 2 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1ISNXS = 3 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1NXS = 4 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OS = 5 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OSNXS = 6 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2 = 7 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2IS = 8 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2ISNXS = 9 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2NXS = 10 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OS = 11 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OSNXS = 12 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3 = 13 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3IS = 14 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3ISNXS = 15 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3NXS = 16 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OS = 17 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OSNXS = 18 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1 = 19 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1IS = 20 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1ISNXS = 21 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1NXS = 22 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OS = 23 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OSNXS = 24 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1 = 25 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1IS = 26 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1ISNXS = 27 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1NXS = 28 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OS = 29 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OSNXS = 30 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1 = 31 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1IS = 32 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1ISNXS = 33 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1NXS = 34 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OS = 35 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OSNXS = 36 , # [doc = " TLBI operations"] ARM64_TLBI_PAALL = 37 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLNXS = 38 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOS = 39 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOSNXS = 40 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1 = 41 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1IS = 42 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1ISNXS = 43 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1NXS = 44 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OS = 45 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OSNXS = 46 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1 = 47 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1IS = 48 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1ISNXS = 49 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1NXS = 50 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OS = 51 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OSNXS = 52 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOS = 53 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOSNXS = 54 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOS = 55 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOSNXS = 56 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1 = 57 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1IS = 58 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1ISNXS = 59 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1NXS = 60 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OS = 61 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OSNXS = 62 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1 = 63 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1IS = 64 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1ISNXS = 65 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1NXS = 66 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OS = 67 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OSNXS = 68 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1 = 69 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1IS = 70 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1ISNXS = 71 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1NXS = 72 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OS = 73 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OSNXS = 74 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2 = 75 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2IS = 76 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2ISNXS = 77 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2NXS = 78 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OS = 79 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OSNXS = 80 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3 = 81 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3IS = 82 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3ISNXS = 83 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3NXS = 84 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OS = 85 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OSNXS = 86 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1 = 87 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1IS = 88 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1ISNXS = 89 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1NXS = 90 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OS = 91 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OSNXS = 92 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2 = 93 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2IS = 94 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2ISNXS = 95 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2NXS = 96 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OS = 97 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OSNXS = 98 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3 = 99 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3IS = 100 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3ISNXS = 101 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3NXS = 102 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OS = 103 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OSNXS = 104 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1 = 105 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1IS = 106 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1ISNXS = 107 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1NXS = 108 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OS = 109 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OSNXS = 110 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1 = 111 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1IS = 112 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1ISNXS = 113 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1NXS = 114 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OS = 115 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OSNXS = 116 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1 = 117 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1IS = 118 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1ISNXS = 119 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1NXS = 120 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OS = 121 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OSNXS = 122 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2 = 123 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2IS = 124 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2ISNXS = 125 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2NXS = 126 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OS = 127 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OSNXS = 128 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3 = 129 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3IS = 130 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3ISNXS = 131 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3NXS = 132 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OS = 133 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OSNXS = 134 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1 = 135 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1IS = 136 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1ISNXS = 137 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1NXS = 138 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OS = 139 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OSNXS = 140 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2 = 141 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2IS = 142 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2ISNXS = 143 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2NXS = 144 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OS = 145 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OSNXS = 146 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3 = 147 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3IS = 148 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3ISNXS = 149 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3NXS = 150 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OS = 151 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OSNXS = 152 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1 = 153 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1IS = 154 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1ISNXS = 155 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1NXS = 156 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OS = 157 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OSNXS = 158 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1 = 159 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1IS = 160 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1ISNXS = 161 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1NXS = 162 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OS = 163 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OSNXS = 164 , # [doc = " AT operations"] ARM64_AT_S1E1R = 165 , # [doc = " AT operations"] ARM64_AT_S1E2R = 166 , # [doc = " AT operations"] ARM64_AT_S1E3R = 167 , # [doc = " AT operations"] ARM64_AT_S1E1W = 168 , # [doc = " AT operations"] ARM64_AT_S1E2W = 169 , # [doc = " AT operations"] ARM64_AT_S1E3W = 170 , # [doc = " AT operations"] ARM64_AT_S1E0R = 171 , # [doc = " AT operations"] ARM64_AT_S1E0W = 172 , # [doc = " AT operations"] ARM64_AT_S12E1R = 173 , # [doc = " AT operations"] ARM64_AT_S12E1W = 174 , # [doc = " AT operations"] ARM64_AT_S12E0R = 175 , # [doc = " AT operations"] ARM64_AT_S12E0W = 176 , # [doc = " AT operations"] ARM64_AT_S1E1RP = 177 , # [doc = " AT operations"] ARM64_AT_S1E1WP = 178 , # [doc = " DC operations"] ARM64_DC_CGDSW = 179 , # [doc = " DC operations"] ARM64_DC_CGDVAC = 180 , # [doc = " DC operations"] ARM64_DC_CGDVADP = 181 , # [doc = " DC operations"] ARM64_DC_CGDVAP = 182 , # [doc = " DC operations"] ARM64_DC_CGSW = 183 , # [doc = " DC operations"] ARM64_DC_CGVAC = 184 , # [doc = " DC operations"] ARM64_DC_CGVADP = 185 , # [doc = " DC operations"] ARM64_DC_CGVAP = 186 , # [doc = " DC operations"] ARM64_DC_CIGDSW = 187 , # [doc = " DC operations"] ARM64_DC_CIGDVAC = 188 , # [doc = " DC operations"] ARM64_DC_CIGSW = 189 , # [doc = " DC operations"] ARM64_DC_CIGVAC = 190 , # [doc = " DC operations"] ARM64_DC_CISW = 191 , # [doc = " DC operations"] ARM64_DC_CIVAC = 192 , # [doc = " DC operations"] ARM64_DC_CSW = 193 , # [doc = " DC operations"] ARM64_DC_CVAC = 194 , # [doc = " DC operations"] ARM64_DC_CVADP = 195 , # [doc = " DC operations"] ARM64_DC_CVAP = 196 , # [doc = " DC operations"] ARM64_DC_CVAU = 197 , # [doc = " DC operations"] ARM64_DC_GVA = 198 , # [doc = " DC operations"] ARM64_DC_GZVA = 199 , # [doc = " DC operations"] ARM64_DC_IGDSW = 200 , # [doc = " DC operations"] ARM64_DC_IGDVAC = 201 , # [doc = " DC operations"] ARM64_DC_IGSW = 202 , # [doc = " DC operations"] ARM64_DC_IGVAC = 203 , # [doc = " DC operations"] ARM64_DC_ISW = 204 , # [doc = " DC operations"] ARM64_DC_IVAC = 205 , # [doc = " DC operations"] ARM64_DC_ZVA = 206 , # [doc = " IC operations"] ARM64_IC_IALLUIS = 207 , # [doc = " IC operations"] ARM64_IC_IALLU = 208 , # [doc = " IC operations"] ARM64_IC_IVAU = 209 , } # [repr (u32)] # [doc = " SVCR operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_svcr_op { ARM64_SVCR_INVALID = 0 , ARM64_SVCR_SVCRSM = 1 , ARM64_SVCR_SVCRSMZA = 3 , ARM64_SVCR_SVCRZA = 2 , } # [repr (u32)] # [doc = " Prefetch operations (PRFM)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0 , ARM64_PRFM_PLDL1KEEP = 1 , ARM64_PRFM_PLDL1STRM = 2 , ARM64_PRFM_PLDL2KEEP = 3 , ARM64_PRFM_PLDL2STRM = 4 , ARM64_PRFM_PLDL3KEEP = 5 , ARM64_PRFM_PLDL3STRM = 6 , ARM64_PRFM_PLIL1KEEP = 9 , ARM64_PRFM_PLIL1STRM = 10 , ARM64_PRFM_PLIL2KEEP = 11 , ARM64_PRFM_PLIL2STRM = 12 , ARM64_PRFM_PLIL3KEEP = 13 , ARM64_PRFM_PLIL3STRM = 14 , ARM64_PRFM_PSTL1KEEP = 17 , ARM64_PRFM_PSTL1STRM = 18 , ARM64_PRFM_PSTL2KEEP = 19 , ARM64_PRFM_PSTL2STRM = 20 , ARM64_PRFM_PSTL3KEEP = 21 , ARM64_PRFM_PSTL3STRM = 22 , } impl arm64_reg { pub const ARM64_REG_IP0 : arm64_reg = arm64_reg :: ARM64_REG_X16 ; } impl arm64_reg { pub const ARM64_REG_IP1 : arm64_reg = arm64_reg :: ARM64_REG_X17 ; } impl arm64_reg { pub const ARM64_REG_X29 : arm64_reg = arm64_reg :: ARM64_REG_FP ; } impl arm64_reg { pub const ARM64_REG_X30 : arm64_reg = arm64_reg :: ARM64_REG_LR ; } # [repr (u32)] # [doc = " ARM64 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_reg { ARM64_REG_INVALID = 0 , ARM64_REG_FFR = 1 , ARM64_REG_FP = 2 , ARM64_REG_LR = 3 , ARM64_REG_NZCV = 4 , ARM64_REG_SP = 5 , ARM64_REG_VG = 6 , ARM64_REG_WSP = 7 , ARM64_REG_WZR = 8 , ARM64_REG_XZR = 9 , ARM64_REG_ZA = 10 , ARM64_REG_B0 = 11 , ARM64_REG_B1 = 12 , ARM64_REG_B2 = 13 , ARM64_REG_B3 = 14 , ARM64_REG_B4 = 15 , ARM64_REG_B5 = 16 , ARM64_REG_B6 = 17 , ARM64_REG_B7 = 18 , ARM64_REG_B8 = 19 , ARM64_REG_B9 = 20 , ARM64_REG_B10 = 21 , ARM64_REG_B11 = 22 , ARM64_REG_B12 = 23 , ARM64_REG_B13 = 24 , ARM64_REG_B14 = 25 , ARM64_REG_B15 = 26 , ARM64_REG_B16 = 27 , ARM64_REG_B17 = 28 , ARM64_REG_B18 = 29 , ARM64_REG_B19 = 30 , ARM64_REG_B20 = 31 , ARM64_REG_B21 = 32 , ARM64_REG_B22 = 33 , ARM64_REG_B23 = 34 , ARM64_REG_B24 = 35 , ARM64_REG_B25 = 36 , ARM64_REG_B26 = 37 , ARM64_REG_B27 = 38 , ARM64_REG_B28 = 39 , ARM64_REG_B29 = 40 , ARM64_REG_B30 = 41 , ARM64_REG_B31 = 42 , ARM64_REG_D0 = 43 , ARM64_REG_D1 = 44 , ARM64_REG_D2 = 45 , ARM64_REG_D3 = 46 , ARM64_REG_D4 = 47 , ARM64_REG_D5 = 48 , ARM64_REG_D6 = 49 , ARM64_REG_D7 = 50 , ARM64_REG_D8 = 51 , ARM64_REG_D9 = 52 , ARM64_REG_D10 = 53 , ARM64_REG_D11 = 54 , ARM64_REG_D12 = 55 , ARM64_REG_D13 = 56 , ARM64_REG_D14 = 57 , ARM64_REG_D15 = 58 , ARM64_REG_D16 = 59 , ARM64_REG_D17 = 60 , ARM64_REG_D18 = 61 , ARM64_REG_D19 = 62 , ARM64_REG_D20 = 63 , ARM64_REG_D21 = 64 , ARM64_REG_D22 = 65 , ARM64_REG_D23 = 66 , ARM64_REG_D24 = 67 , ARM64_REG_D25 = 68 , ARM64_REG_D26 = 69 , ARM64_REG_D27 = 70 , ARM64_REG_D28 = 71 , ARM64_REG_D29 = 72 , ARM64_REG_D30 = 73 , ARM64_REG_D31 = 74 , ARM64_REG_H0 = 75 , ARM64_REG_H1 = 76 , ARM64_REG_H2 = 77 , ARM64_REG_H3 = 78 , ARM64_REG_H4 = 79 , ARM64_REG_H5 = 80 , ARM64_REG_H6 = 81 , ARM64_REG_H7 = 82 , ARM64_REG_H8 = 83 , ARM64_REG_H9 = 84 , ARM64_REG_H10 = 85 , ARM64_REG_H11 = 86 , ARM64_REG_H12 = 87 , ARM64_REG_H13 = 88 , ARM64_REG_H14 = 89 , ARM64_REG_H15 = 90 , ARM64_REG_H16 = 91 , ARM64_REG_H17 = 92 , ARM64_REG_H18 = 93 , ARM64_REG_H19 = 94 , ARM64_REG_H20 = 95 , ARM64_REG_H21 = 96 , ARM64_REG_H22 = 97 , ARM64_REG_H23 = 98 , ARM64_REG_H24 = 99 , ARM64_REG_H25 = 100 , ARM64_REG_H26 = 101 , ARM64_REG_H27 = 102 , ARM64_REG_H28 = 103 , ARM64_REG_H29 = 104 , ARM64_REG_H30 = 105 , ARM64_REG_H31 = 106 , ARM64_REG_P0 = 107 , ARM64_REG_P1 = 108 , ARM64_REG_P2 = 109 , ARM64_REG_P3 = 110 , ARM64_REG_P4 = 111 , ARM64_REG_P5 = 112 , ARM64_REG_P6 = 113 , ARM64_REG_P7 = 114 , ARM64_REG_P8 = 115 , ARM64_REG_P9 = 116 , ARM64_REG_P10 = 117 , ARM64_REG_P11 = 118 , ARM64_REG_P12 = 119 , ARM64_REG_P13 = 120 , ARM64_REG_P14 = 121 , ARM64_REG_P15 = 122 , ARM64_REG_Q0 = 123 , ARM64_REG_Q1 = 124 , ARM64_REG_Q2 = 125 , ARM64_REG_Q3 = 126 , ARM64_REG_Q4 = 127 , ARM64_REG_Q5 = 128 , ARM64_REG_Q6 = 129 , ARM64_REG_Q7 = 130 , ARM64_REG_Q8 = 131 , ARM64_REG_Q9 = 132 , ARM64_REG_Q10 = 133 , ARM64_REG_Q11 = 134 , ARM64_REG_Q12 = 135 , ARM64_REG_Q13 = 136 , ARM64_REG_Q14 = 137 , ARM64_REG_Q15 = 138 , ARM64_REG_Q16 = 139 , ARM64_REG_Q17 = 140 , ARM64_REG_Q18 = 141 , ARM64_REG_Q19 = 142 , ARM64_REG_Q20 = 143 , ARM64_REG_Q21 = 144 , ARM64_REG_Q22 = 145 , ARM64_REG_Q23 = 146 , ARM64_REG_Q24 = 147 , ARM64_REG_Q25 = 148 , ARM64_REG_Q26 = 149 , ARM64_REG_Q27 = 150 , ARM64_REG_Q28 = 151 , ARM64_REG_Q29 = 152 , ARM64_REG_Q30 = 153 , ARM64_REG_Q31 = 154 , ARM64_REG_S0 = 155 , ARM64_REG_S1 = 156 , ARM64_REG_S2 = 157 , ARM64_REG_S3 = 158 , ARM64_REG_S4 = 159 , ARM64_REG_S5 = 160 , ARM64_REG_S6 = 161 , ARM64_REG_S7 = 162 , ARM64_REG_S8 = 163 , ARM64_REG_S9 = 164 , ARM64_REG_S10 = 165 , ARM64_REG_S11 = 166 , ARM64_REG_S12 = 167 , ARM64_REG_S13 = 168 , ARM64_REG_S14 = 169 , ARM64_REG_S15 = 170 , ARM64_REG_S16 = 171 , ARM64_REG_S17 = 172 , ARM64_REG_S18 = 173 , ARM64_REG_S19 = 174 , ARM64_REG_S20 = 175 , ARM64_REG_S21 = 176 , ARM64_REG_S22 = 177 , ARM64_REG_S23 = 178 , ARM64_REG_S24 = 179 , ARM64_REG_S25 = 180 , ARM64_REG_S26 = 181 , ARM64_REG_S27 = 182 , ARM64_REG_S28 = 183 , ARM64_REG_S29 = 184 , ARM64_REG_S30 = 185 , ARM64_REG_S31 = 186 , ARM64_REG_W0 = 187 , ARM64_REG_W1 = 188 , ARM64_REG_W2 = 189 , ARM64_REG_W3 = 190 , ARM64_REG_W4 = 191 , ARM64_REG_W5 = 192 , ARM64_REG_W6 = 193 , ARM64_REG_W7 = 194 , ARM64_REG_W8 = 195 , ARM64_REG_W9 = 196 , ARM64_REG_W10 = 197 , ARM64_REG_W11 = 198 , ARM64_REG_W12 = 199 , ARM64_REG_W13 = 200 , ARM64_REG_W14 = 201 , ARM64_REG_W15 = 202 , ARM64_REG_W16 = 203 , ARM64_REG_W17 = 204 , ARM64_REG_W18 = 205 , ARM64_REG_W19 = 206 , ARM64_REG_W20 = 207 , ARM64_REG_W21 = 208 , ARM64_REG_W22 = 209 , ARM64_REG_W23 = 210 , ARM64_REG_W24 = 211 , ARM64_REG_W25 = 212 , ARM64_REG_W26 = 213 , ARM64_REG_W27 = 214 , ARM64_REG_W28 = 215 , ARM64_REG_W29 = 216 , ARM64_REG_W30 = 217 , ARM64_REG_X0 = 218 , ARM64_REG_X1 = 219 , ARM64_REG_X2 = 220 , ARM64_REG_X3 = 221 , ARM64_REG_X4 = 222 , ARM64_REG_X5 = 223 , ARM64_REG_X6 = 224 , ARM64_REG_X7 = 225 , ARM64_REG_X8 = 226 , ARM64_REG_X9 = 227 , ARM64_REG_X10 = 228 , ARM64_REG_X11 = 229 , ARM64_REG_X12 = 230 , ARM64_REG_X13 = 231 , ARM64_REG_X14 = 232 , ARM64_REG_X15 = 233 , ARM64_REG_X16 = 234 , ARM64_REG_X17 = 235 , ARM64_REG_X18 = 236 , ARM64_REG_X19 = 237 , ARM64_REG_X20 = 238 , ARM64_REG_X21 = 239 , ARM64_REG_X22 = 240 , ARM64_REG_X23 = 241 , ARM64_REG_X24 = 242 , ARM64_REG_X25 = 243 , ARM64_REG_X26 = 244 , ARM64_REG_X27 = 245 , ARM64_REG_X28 = 246 , ARM64_REG_Z0 = 247 , ARM64_REG_Z1 = 248 , ARM64_REG_Z2 = 249 , ARM64_REG_Z3 = 250 , ARM64_REG_Z4 = 251 , ARM64_REG_Z5 = 252 , ARM64_REG_Z6 = 253 , ARM64_REG_Z7 = 254 , ARM64_REG_Z8 = 255 , ARM64_REG_Z9 = 256 , ARM64_REG_Z10 = 257 , ARM64_REG_Z11 = 258 , ARM64_REG_Z12 = 259 , ARM64_REG_Z13 = 260 , ARM64_REG_Z14 = 261 , ARM64_REG_Z15 = 262 , ARM64_REG_Z16 = 263 , ARM64_REG_Z17 = 264 , ARM64_REG_Z18 = 265 , ARM64_REG_Z19 = 266 , ARM64_REG_Z20 = 267 , ARM64_REG_Z21 = 268 , ARM64_REG_Z22 = 269 , ARM64_REG_Z23 = 270 , ARM64_REG_Z24 = 271 , ARM64_REG_Z25 = 272 , ARM64_REG_Z26 = 273 , ARM64_REG_Z27 = 274 , ARM64_REG_Z28 = 275 , ARM64_REG_Z29 = 276 , ARM64_REG_Z30 = 277 , ARM64_REG_Z31 = 278 , ARM64_REG_ZAB0 = 279 , ARM64_REG_ZAD0 = 280 , ARM64_REG_ZAD1 = 281 , ARM64_REG_ZAD2 = 282 , ARM64_REG_ZAD3 = 283 , ARM64_REG_ZAD4 = 284 , ARM64_REG_ZAD5 = 285 , ARM64_REG_ZAD6 = 286 , ARM64_REG_ZAD7 = 287 , ARM64_REG_ZAH0 = 288 , ARM64_REG_ZAH1 = 289 , ARM64_REG_ZAQ0 = 290 , ARM64_REG_ZAQ1 = 291 , ARM64_REG_ZAQ2 = 292 , ARM64_REG_ZAQ3 = 293 , ARM64_REG_ZAQ4 = 294 , ARM64_REG_ZAQ5 = 295 , ARM64_REG_ZAQ6 = 296 , ARM64_REG_ZAQ7 = 297 , ARM64_REG_ZAQ8 = 298 , ARM64_REG_ZAQ9 = 299 , ARM64_REG_ZAQ10 = 300 , ARM64_REG_ZAQ11 = 301 , ARM64_REG_ZAQ12 = 302 , ARM64_REG_ZAQ13 = 303 , ARM64_REG_ZAQ14 = 304 , ARM64_REG_ZAQ15 = 305 , ARM64_REG_ZAS0 = 306 , ARM64_REG_ZAS1 = 307 , ARM64_REG_ZAS2 = 308 , ARM64_REG_ZAS3 = 309 , ARM64_REG_V0 = 310 , ARM64_REG_V1 = 311 , ARM64_REG_V2 = 312 , ARM64_REG_V3 = 313 , ARM64_REG_V4 = 314 , ARM64_REG_V5 = 315 , ARM64_REG_V6 = 316 , ARM64_REG_V7 = 317 , ARM64_REG_V8 = 318 , ARM64_REG_V9 = 319 , ARM64_REG_V10 = 320 , ARM64_REG_V11 = 321 , ARM64_REG_V12 = 322 , ARM64_REG_V13 = 323 , ARM64_REG_V14 = 324 , ARM64_REG_V15 = 325 , ARM64_REG_V16 = 326 , ARM64_REG_V17 = 327 , ARM64_REG_V18 = 328 , ARM64_REG_V19 = 329 , ARM64_REG_V20 = 330 , ARM64_REG_V21 = 331 , ARM64_REG_V22 = 332 , ARM64_REG_V23 = 333 , ARM64_REG_V24 = 334 , ARM64_REG_V25 = 335 , ARM64_REG_V26 = 336 , ARM64_REG_V27 = 337 , ARM64_REG_V28 = 338 , ARM64_REG_V29 = 339 , ARM64_REG_V30 = 340 , ARM64_REG_V31 = 341 , ARM64_REG_ENDING = 342 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_mem { # [doc = "< base register"] pub base : arm64_reg , # [doc = "< index register"] pub index : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_mem"] [:: std :: mem :: size_of :: < arm64_op_mem > () - 12usize] ; ["Alignment of arm64_op_mem"] [:: std :: mem :: align_of :: < arm64_op_mem > () - 4usize] ; ["Offset of field: arm64_op_mem::base"] [:: std :: mem :: offset_of ! (arm64_op_mem , base) - 0usize] ; ["Offset of field: arm64_op_mem::index"] [:: std :: mem :: offset_of ! (arm64_op_mem , index) - 4usize] ; ["Offset of field: arm64_op_mem::disp"] [:: std :: mem :: offset_of ! (arm64_op_mem , disp) - 8usize] ; } ; # [doc = " SME Instruction's operand has index\n This is associated with ARM64_OP_SME_INDEX operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_sme_index { # [doc = "< register being indexed"] pub reg : arm64_reg , # [doc = "< base register"] pub base : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_sme_index"] [:: std :: mem :: size_of :: < arm64_op_sme_index > () - 12usize] ; ["Alignment of arm64_op_sme_index"] [:: std :: mem :: align_of :: < arm64_op_sme_index > () - 4usize] ; ["Offset of field: arm64_op_sme_index::reg"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , reg) - 0usize] ; ["Offset of field: arm64_op_sme_index::base"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , base) - 4usize] ; ["Offset of field: arm64_op_sme_index::disp"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64_op { # [doc = "< Vector Index for some vector operands (or -1 if\n< irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , # [doc = "< Vector Arrangement Specifier"] pub vas : arm64_vas , pub shift : cs_arm64_op__bindgen_ty_1 , # [doc = "< extender type of this operand"] pub ext : arm64_extender , # [doc = "< operand type"] pub type_ : arm64_op_type , # [doc = "< MSR/MRS SVCR instruction variant."] pub svcr : arm64_svcr_op , pub __bindgen_anon_1 : cs_arm64_op__bindgen_ty_2 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm64_op__bindgen_ty_1 { # [doc = "< shifter type of this operand"] pub type_ : arm64_shifter , # [doc = "< shifter value of this operand"] pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm64_op__bindgen_ty_2 { # [doc = "< register value for REG operand"] pub reg : arm64_reg , # [doc = "< immediate value, or index for C-IMM or IMM operand"] pub imm : i64 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm64_op_mem , # [doc = "< PState field of MSR instruction."] pub pstate : arm64_pstate , # [doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op,\n< arm64_dc_op, arm64_at_op, arm64_tlbi_op)"] pub sys : arm64_sys_op , # [doc = "< PRFM operation."] pub prefetch : arm64_prefetch_op , # [doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."] pub barrier : arm64_barrier_op , # [doc = "< base/disp value for matrix tile slice\n< instructions."] pub sme_index : arm64_op_sme_index , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_2 > () - 16usize] ; ["Alignment of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::pstate"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , pstate) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sys"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sys) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::prefetch"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , prefetch) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::barrier"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , barrier) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sme_index"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sme_index) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op"] [:: std :: mem :: size_of :: < cs_arm64_op > () - 56usize] ; ["Alignment of cs_arm64_op"] [:: std :: mem :: align_of :: < cs_arm64_op > () - 8usize] ; ["Offset of field: cs_arm64_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm64_op , vector_index) - 0usize] ; ["Offset of field: cs_arm64_op::vas"] [:: std :: mem :: offset_of ! (cs_arm64_op , vas) - 4usize] ; ["Offset of field: cs_arm64_op::shift"] [:: std :: mem :: offset_of ! (cs_arm64_op , shift) - 8usize] ; ["Offset of field: cs_arm64_op::ext"] [:: std :: mem :: offset_of ! (cs_arm64_op , ext) - 16usize] ; ["Offset of field: cs_arm64_op::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op , type_) - 20usize] ; ["Offset of field: cs_arm64_op::svcr"] [:: std :: mem :: offset_of ! (cs_arm64_op , svcr) - 24usize] ; ["Offset of field: cs_arm64_op::access"] [:: std :: mem :: offset_of ! (cs_arm64_op , access) - 48usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, svcr: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . svcr , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64 { # [doc = "< conditional code for this insn"] pub cc : arm64_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn request writeback? 'True' means 'yes'"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm64_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64"] [:: std :: mem :: size_of :: < cs_arm64 > () - 456usize] ; ["Alignment of cs_arm64"] [:: std :: mem :: align_of :: < cs_arm64 > () - 8usize] ; ["Offset of field: cs_arm64::cc"] [:: std :: mem :: offset_of ! (cs_arm64 , cc) - 0usize] ; ["Offset of field: cs_arm64::update_flags"] [:: std :: mem :: offset_of ! (cs_arm64 , update_flags) - 4usize] ; ["Offset of field: cs_arm64::writeback"] [:: std :: mem :: offset_of ! (cs_arm64 , writeback) - 5usize] ; ["Offset of field: cs_arm64::post_index"] [:: std :: mem :: offset_of ! (cs_arm64 , post_index) - 6usize] ; ["Offset of field: cs_arm64::op_count"] [:: std :: mem :: offset_of ! (cs_arm64 , op_count) - 7usize] ; ["Offset of field: cs_arm64::operands"] [:: std :: mem :: offset_of ! (cs_arm64 , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . post_index , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM64 instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn { ARM64_INS_INVALID = 0 , ARM64_INS_ABS = 1 , ARM64_INS_ADC = 2 , ARM64_INS_ADCLB = 3 , ARM64_INS_ADCLT = 4 , ARM64_INS_ADCS = 5 , ARM64_INS_ADD = 6 , ARM64_INS_ADDG = 7 , ARM64_INS_ADDHA = 8 , ARM64_INS_ADDHN = 9 , ARM64_INS_ADDHN2 = 10 , ARM64_INS_ADDHNB = 11 , ARM64_INS_ADDHNT = 12 , ARM64_INS_ADDP = 13 , ARM64_INS_ADDPL = 14 , ARM64_INS_ADDS = 15 , ARM64_INS_ADDV = 16 , ARM64_INS_ADDVA = 17 , ARM64_INS_ADDVL = 18 , ARM64_INS_ADR = 19 , ARM64_INS_ADRP = 20 , ARM64_INS_AESD = 21 , ARM64_INS_AESE = 22 , ARM64_INS_AESIMC = 23 , ARM64_INS_AESMC = 24 , ARM64_INS_AND = 25 , ARM64_INS_ANDS = 26 , ARM64_INS_ANDV = 27 , ARM64_INS_ASR = 28 , ARM64_INS_ASRD = 29 , ARM64_INS_ASRR = 30 , ARM64_INS_ASRV = 31 , ARM64_INS_AUTDA = 32 , ARM64_INS_AUTDB = 33 , ARM64_INS_AUTDZA = 34 , ARM64_INS_AUTDZB = 35 , ARM64_INS_AUTIA = 36 , ARM64_INS_AUTIA1716 = 37 , ARM64_INS_AUTIASP = 38 , ARM64_INS_AUTIAZ = 39 , ARM64_INS_AUTIB = 40 , ARM64_INS_AUTIB1716 = 41 , ARM64_INS_AUTIBSP = 42 , ARM64_INS_AUTIBZ = 43 , ARM64_INS_AUTIZA = 44 , ARM64_INS_AUTIZB = 45 , ARM64_INS_AXFLAG = 46 , ARM64_INS_B = 47 , ARM64_INS_BC = 48 , ARM64_INS_BCAX = 49 , ARM64_INS_BDEP = 50 , ARM64_INS_BEXT = 51 , ARM64_INS_BFCVT = 52 , ARM64_INS_BFCVTN = 53 , ARM64_INS_BFCVTN2 = 54 , ARM64_INS_BFCVTNT = 55 , ARM64_INS_BFDOT = 56 , ARM64_INS_BFM = 57 , ARM64_INS_BFMLALB = 58 , ARM64_INS_BFMLALT = 59 , ARM64_INS_BFMMLA = 60 , ARM64_INS_BFMOPA = 61 , ARM64_INS_BFMOPS = 62 , ARM64_INS_BGRP = 63 , ARM64_INS_BIC = 64 , ARM64_INS_BICS = 65 , ARM64_INS_BIF = 66 , ARM64_INS_BIT = 67 , ARM64_INS_BL = 68 , ARM64_INS_BLR = 69 , ARM64_INS_BLRAA = 70 , ARM64_INS_BLRAAZ = 71 , ARM64_INS_BLRAB = 72 , ARM64_INS_BLRABZ = 73 , ARM64_INS_BR = 74 , ARM64_INS_BRAA = 75 , ARM64_INS_BRAAZ = 76 , ARM64_INS_BRAB = 77 , ARM64_INS_BRABZ = 78 , ARM64_INS_BRB = 79 , ARM64_INS_BRK = 80 , ARM64_INS_BRKA = 81 , ARM64_INS_BRKAS = 82 , ARM64_INS_BRKB = 83 , ARM64_INS_BRKBS = 84 , ARM64_INS_BRKN = 85 , ARM64_INS_BRKNS = 86 , ARM64_INS_BRKPA = 87 , ARM64_INS_BRKPAS = 88 , ARM64_INS_BRKPB = 89 , ARM64_INS_BRKPBS = 90 , ARM64_INS_BSL = 91 , ARM64_INS_BSL1N = 92 , ARM64_INS_BSL2N = 93 , ARM64_INS_BTI = 94 , ARM64_INS_CADD = 95 , ARM64_INS_CAS = 96 , ARM64_INS_CASA = 97 , ARM64_INS_CASAB = 98 , ARM64_INS_CASAH = 99 , ARM64_INS_CASAL = 100 , ARM64_INS_CASALB = 101 , ARM64_INS_CASALH = 102 , ARM64_INS_CASB = 103 , ARM64_INS_CASH = 104 , ARM64_INS_CASL = 105 , ARM64_INS_CASLB = 106 , ARM64_INS_CASLH = 107 , ARM64_INS_CASP = 108 , ARM64_INS_CASPA = 109 , ARM64_INS_CASPAL = 110 , ARM64_INS_CASPL = 111 , ARM64_INS_CBNZ = 112 , ARM64_INS_CBZ = 113 , ARM64_INS_CCMN = 114 , ARM64_INS_CCMP = 115 , ARM64_INS_CDOT = 116 , ARM64_INS_CFINV = 117 , ARM64_INS_CINC = 118 , ARM64_INS_CINV = 119 , ARM64_INS_CLASTA = 120 , ARM64_INS_CLASTB = 121 , ARM64_INS_CLREX = 122 , ARM64_INS_CLS = 123 , ARM64_INS_CLZ = 124 , ARM64_INS_CMEQ = 125 , ARM64_INS_CMGE = 126 , ARM64_INS_CMGT = 127 , ARM64_INS_CMHI = 128 , ARM64_INS_CMHS = 129 , ARM64_INS_CMLA = 130 , ARM64_INS_CMLE = 131 , ARM64_INS_CMLO = 132 , ARM64_INS_CMLS = 133 , ARM64_INS_CMLT = 134 , ARM64_INS_CMN = 135 , ARM64_INS_CMP = 136 , ARM64_INS_CMPEQ = 137 , ARM64_INS_CMPGE = 138 , ARM64_INS_CMPGT = 139 , ARM64_INS_CMPHI = 140 , ARM64_INS_CMPHS = 141 , ARM64_INS_CMPLE = 142 , ARM64_INS_CMPLO = 143 , ARM64_INS_CMPLS = 144 , ARM64_INS_CMPLT = 145 , ARM64_INS_CMPNE = 146 , ARM64_INS_CMPP = 147 , ARM64_INS_CMTST = 148 , ARM64_INS_CNEG = 149 , ARM64_INS_CNOT = 150 , ARM64_INS_CNT = 151 , ARM64_INS_CNTB = 152 , ARM64_INS_CNTD = 153 , ARM64_INS_CNTH = 154 , ARM64_INS_CNTP = 155 , ARM64_INS_CNTW = 156 , ARM64_INS_COMPACT = 157 , ARM64_INS_CPY = 158 , ARM64_INS_CPYE = 159 , ARM64_INS_CPYEN = 160 , ARM64_INS_CPYERN = 161 , ARM64_INS_CPYERT = 162 , ARM64_INS_CPYERTN = 163 , ARM64_INS_CPYERTRN = 164 , ARM64_INS_CPYERTWN = 165 , ARM64_INS_CPYET = 166 , ARM64_INS_CPYETN = 167 , ARM64_INS_CPYETRN = 168 , ARM64_INS_CPYETWN = 169 , ARM64_INS_CPYEWN = 170 , ARM64_INS_CPYEWT = 171 , ARM64_INS_CPYEWTN = 172 , ARM64_INS_CPYEWTRN = 173 , ARM64_INS_CPYEWTWN = 174 , ARM64_INS_CPYFE = 175 , ARM64_INS_CPYFEN = 176 , ARM64_INS_CPYFERN = 177 , ARM64_INS_CPYFERT = 178 , ARM64_INS_CPYFERTN = 179 , ARM64_INS_CPYFERTRN = 180 , ARM64_INS_CPYFERTWN = 181 , ARM64_INS_CPYFET = 182 , ARM64_INS_CPYFETN = 183 , ARM64_INS_CPYFETRN = 184 , ARM64_INS_CPYFETWN = 185 , ARM64_INS_CPYFEWN = 186 , ARM64_INS_CPYFEWT = 187 , ARM64_INS_CPYFEWTN = 188 , ARM64_INS_CPYFEWTRN = 189 , ARM64_INS_CPYFEWTWN = 190 , ARM64_INS_CPYFM = 191 , ARM64_INS_CPYFMN = 192 , ARM64_INS_CPYFMRN = 193 , ARM64_INS_CPYFMRT = 194 , ARM64_INS_CPYFMRTN = 195 , ARM64_INS_CPYFMRTRN = 196 , ARM64_INS_CPYFMRTWN = 197 , ARM64_INS_CPYFMT = 198 , ARM64_INS_CPYFMTN = 199 , ARM64_INS_CPYFMTRN = 200 , ARM64_INS_CPYFMTWN = 201 , ARM64_INS_CPYFMWN = 202 , ARM64_INS_CPYFMWT = 203 , ARM64_INS_CPYFMWTN = 204 , ARM64_INS_CPYFMWTRN = 205 , ARM64_INS_CPYFMWTWN = 206 , ARM64_INS_CPYFP = 207 , ARM64_INS_CPYFPN = 208 , ARM64_INS_CPYFPRN = 209 , ARM64_INS_CPYFPRT = 210 , ARM64_INS_CPYFPRTN = 211 , ARM64_INS_CPYFPRTRN = 212 , ARM64_INS_CPYFPRTWN = 213 , ARM64_INS_CPYFPT = 214 , ARM64_INS_CPYFPTN = 215 , ARM64_INS_CPYFPTRN = 216 , ARM64_INS_CPYFPTWN = 217 , ARM64_INS_CPYFPWN = 218 , ARM64_INS_CPYFPWT = 219 , ARM64_INS_CPYFPWTN = 220 , ARM64_INS_CPYFPWTRN = 221 , ARM64_INS_CPYFPWTWN = 222 , ARM64_INS_CPYM = 223 , ARM64_INS_CPYMN = 224 , ARM64_INS_CPYMRN = 225 , ARM64_INS_CPYMRT = 226 , ARM64_INS_CPYMRTN = 227 , ARM64_INS_CPYMRTRN = 228 , ARM64_INS_CPYMRTWN = 229 , ARM64_INS_CPYMT = 230 , ARM64_INS_CPYMTN = 231 , ARM64_INS_CPYMTRN = 232 , ARM64_INS_CPYMTWN = 233 , ARM64_INS_CPYMWN = 234 , ARM64_INS_CPYMWT = 235 , ARM64_INS_CPYMWTN = 236 , ARM64_INS_CPYMWTRN = 237 , ARM64_INS_CPYMWTWN = 238 , ARM64_INS_CPYP = 239 , ARM64_INS_CPYPN = 240 , ARM64_INS_CPYPRN = 241 , ARM64_INS_CPYPRT = 242 , ARM64_INS_CPYPRTN = 243 , ARM64_INS_CPYPRTRN = 244 , ARM64_INS_CPYPRTWN = 245 , ARM64_INS_CPYPT = 246 , ARM64_INS_CPYPTN = 247 , ARM64_INS_CPYPTRN = 248 , ARM64_INS_CPYPTWN = 249 , ARM64_INS_CPYPWN = 250 , ARM64_INS_CPYPWT = 251 , ARM64_INS_CPYPWTN = 252 , ARM64_INS_CPYPWTRN = 253 , ARM64_INS_CPYPWTWN = 254 , ARM64_INS_CRC32B = 255 , ARM64_INS_CRC32CB = 256 , ARM64_INS_CRC32CH = 257 , ARM64_INS_CRC32CW = 258 , ARM64_INS_CRC32CX = 259 , ARM64_INS_CRC32H = 260 , ARM64_INS_CRC32W = 261 , ARM64_INS_CRC32X = 262 , ARM64_INS_CSDB = 263 , ARM64_INS_CSEL = 264 , ARM64_INS_CSET = 265 , ARM64_INS_CSETM = 266 , ARM64_INS_CSINC = 267 , ARM64_INS_CSINV = 268 , ARM64_INS_CSNEG = 269 , ARM64_INS_CTERMEQ = 270 , ARM64_INS_CTERMNE = 271 , ARM64_INS_DCPS1 = 272 , ARM64_INS_DCPS2 = 273 , ARM64_INS_DCPS3 = 274 , ARM64_INS_DECB = 275 , ARM64_INS_DECD = 276 , ARM64_INS_DECH = 277 , ARM64_INS_DECP = 278 , ARM64_INS_DECW = 279 , ARM64_INS_DFB = 280 , ARM64_INS_DGH = 281 , ARM64_INS_DMB = 282 , ARM64_INS_DRPS = 283 , ARM64_INS_DSB = 284 , ARM64_INS_DUP = 285 , ARM64_INS_DUPM = 286 , ARM64_INS_EON = 287 , ARM64_INS_EOR = 288 , ARM64_INS_EOR3 = 289 , ARM64_INS_EORBT = 290 , ARM64_INS_EORS = 291 , ARM64_INS_EORTB = 292 , ARM64_INS_EORV = 293 , ARM64_INS_ERET = 294 , ARM64_INS_ERETAA = 295 , ARM64_INS_ERETAB = 296 , ARM64_INS_ESB = 297 , ARM64_INS_EXT = 298 , ARM64_INS_EXTR = 299 , ARM64_INS_FABD = 300 , ARM64_INS_FABS = 301 , ARM64_INS_FACGE = 302 , ARM64_INS_FACGT = 303 , ARM64_INS_FACLE = 304 , ARM64_INS_FACLT = 305 , ARM64_INS_FADD = 306 , ARM64_INS_FADDA = 307 , ARM64_INS_FADDP = 308 , ARM64_INS_FADDV = 309 , ARM64_INS_FCADD = 310 , ARM64_INS_FCCMP = 311 , ARM64_INS_FCCMPE = 312 , ARM64_INS_FCMEQ = 313 , ARM64_INS_FCMGE = 314 , ARM64_INS_FCMGT = 315 , ARM64_INS_FCMLA = 316 , ARM64_INS_FCMLE = 317 , ARM64_INS_FCMLT = 318 , ARM64_INS_FCMNE = 319 , ARM64_INS_FCMP = 320 , ARM64_INS_FCMPE = 321 , ARM64_INS_FCMUO = 322 , ARM64_INS_FCPY = 323 , ARM64_INS_FCSEL = 324 , ARM64_INS_FCVT = 325 , ARM64_INS_FCVTAS = 326 , ARM64_INS_FCVTAU = 327 , ARM64_INS_FCVTL = 328 , ARM64_INS_FCVTL2 = 329 , ARM64_INS_FCVTLT = 330 , ARM64_INS_FCVTMS = 331 , ARM64_INS_FCVTMU = 332 , ARM64_INS_FCVTN = 333 , ARM64_INS_FCVTN2 = 334 , ARM64_INS_FCVTNS = 335 , ARM64_INS_FCVTNT = 336 , ARM64_INS_FCVTNU = 337 , ARM64_INS_FCVTPS = 338 , ARM64_INS_FCVTPU = 339 , ARM64_INS_FCVTX = 340 , ARM64_INS_FCVTXN = 341 , ARM64_INS_FCVTXN2 = 342 , ARM64_INS_FCVTXNT = 343 , ARM64_INS_FCVTZS = 344 , ARM64_INS_FCVTZU = 345 , ARM64_INS_FDIV = 346 , ARM64_INS_FDIVR = 347 , ARM64_INS_FDUP = 348 , ARM64_INS_FEXPA = 349 , ARM64_INS_FJCVTZS = 350 , ARM64_INS_FLOGB = 351 , ARM64_INS_FMAD = 352 , ARM64_INS_FMADD = 353 , ARM64_INS_FMAX = 354 , ARM64_INS_FMAXNM = 355 , ARM64_INS_FMAXNMP = 356 , ARM64_INS_FMAXNMV = 357 , ARM64_INS_FMAXP = 358 , ARM64_INS_FMAXV = 359 , ARM64_INS_FMIN = 360 , ARM64_INS_FMINNM = 361 , ARM64_INS_FMINNMP = 362 , ARM64_INS_FMINNMV = 363 , ARM64_INS_FMINP = 364 , ARM64_INS_FMINV = 365 , ARM64_INS_FMLA = 366 , ARM64_INS_FMLAL = 367 , ARM64_INS_FMLAL2 = 368 , ARM64_INS_FMLALB = 369 , ARM64_INS_FMLALT = 370 , ARM64_INS_FMLS = 371 , ARM64_INS_FMLSL = 372 , ARM64_INS_FMLSL2 = 373 , ARM64_INS_FMLSLB = 374 , ARM64_INS_FMLSLT = 375 , ARM64_INS_FMMLA = 376 , ARM64_INS_FMOPA = 377 , ARM64_INS_FMOPS = 378 , ARM64_INS_FMOV = 379 , ARM64_INS_FMSB = 380 , ARM64_INS_FMSUB = 381 , ARM64_INS_FMUL = 382 , ARM64_INS_FMULX = 383 , ARM64_INS_FNEG = 384 , ARM64_INS_FNMAD = 385 , ARM64_INS_FNMADD = 386 , ARM64_INS_FNMLA = 387 , ARM64_INS_FNMLS = 388 , ARM64_INS_FNMSB = 389 , ARM64_INS_FNMSUB = 390 , ARM64_INS_FNMUL = 391 , ARM64_INS_FRECPE = 392 , ARM64_INS_FRECPS = 393 , ARM64_INS_FRECPX = 394 , ARM64_INS_FRINT32X = 395 , ARM64_INS_FRINT32Z = 396 , ARM64_INS_FRINT64X = 397 , ARM64_INS_FRINT64Z = 398 , ARM64_INS_FRINTA = 399 , ARM64_INS_FRINTI = 400 , ARM64_INS_FRINTM = 401 , ARM64_INS_FRINTN = 402 , ARM64_INS_FRINTP = 403 , ARM64_INS_FRINTX = 404 , ARM64_INS_FRINTZ = 405 , ARM64_INS_FRSQRTE = 406 , ARM64_INS_FRSQRTS = 407 , ARM64_INS_FSCALE = 408 , ARM64_INS_FSQRT = 409 , ARM64_INS_FSUB = 410 , ARM64_INS_FSUBR = 411 , ARM64_INS_FTMAD = 412 , ARM64_INS_FTSMUL = 413 , ARM64_INS_FTSSEL = 414 , ARM64_INS_GMI = 415 , ARM64_INS_HINT = 416 , ARM64_INS_HISTCNT = 417 , ARM64_INS_HISTSEG = 418 , ARM64_INS_HLT = 419 , ARM64_INS_HVC = 420 , ARM64_INS_INCB = 421 , ARM64_INS_INCD = 422 , ARM64_INS_INCH = 423 , ARM64_INS_INCP = 424 , ARM64_INS_INCW = 425 , ARM64_INS_INDEX = 426 , ARM64_INS_INS = 427 , ARM64_INS_INSR = 428 , ARM64_INS_IRG = 429 , ARM64_INS_ISB = 430 , ARM64_INS_LASTA = 431 , ARM64_INS_LASTB = 432 , ARM64_INS_LD1 = 433 , ARM64_INS_LD1B = 434 , ARM64_INS_LD1D = 435 , ARM64_INS_LD1H = 436 , ARM64_INS_LD1Q = 437 , ARM64_INS_LD1R = 438 , ARM64_INS_LD1RB = 439 , ARM64_INS_LD1RD = 440 , ARM64_INS_LD1RH = 441 , ARM64_INS_LD1ROB = 442 , ARM64_INS_LD1ROD = 443 , ARM64_INS_LD1ROH = 444 , ARM64_INS_LD1ROW = 445 , ARM64_INS_LD1RQB = 446 , ARM64_INS_LD1RQD = 447 , ARM64_INS_LD1RQH = 448 , ARM64_INS_LD1RQW = 449 , ARM64_INS_LD1RSB = 450 , ARM64_INS_LD1RSH = 451 , ARM64_INS_LD1RSW = 452 , ARM64_INS_LD1RW = 453 , ARM64_INS_LD1SB = 454 , ARM64_INS_LD1SH = 455 , ARM64_INS_LD1SW = 456 , ARM64_INS_LD1W = 457 , ARM64_INS_LD2 = 458 , ARM64_INS_LD2B = 459 , ARM64_INS_LD2D = 460 , ARM64_INS_LD2H = 461 , ARM64_INS_LD2R = 462 , ARM64_INS_LD2W = 463 , ARM64_INS_LD3 = 464 , ARM64_INS_LD3B = 465 , ARM64_INS_LD3D = 466 , ARM64_INS_LD3H = 467 , ARM64_INS_LD3R = 468 , ARM64_INS_LD3W = 469 , ARM64_INS_LD4 = 470 , ARM64_INS_LD4B = 471 , ARM64_INS_LD4D = 472 , ARM64_INS_LD4H = 473 , ARM64_INS_LD4R = 474 , ARM64_INS_LD4W = 475 , ARM64_INS_LD64B = 476 , ARM64_INS_LDADD = 477 , ARM64_INS_LDADDA = 478 , ARM64_INS_LDADDAB = 479 , ARM64_INS_LDADDAH = 480 , ARM64_INS_LDADDAL = 481 , ARM64_INS_LDADDALB = 482 , ARM64_INS_LDADDALH = 483 , ARM64_INS_LDADDB = 484 , ARM64_INS_LDADDH = 485 , ARM64_INS_LDADDL = 486 , ARM64_INS_LDADDLB = 487 , ARM64_INS_LDADDLH = 488 , ARM64_INS_LDAPR = 489 , ARM64_INS_LDAPRB = 490 , ARM64_INS_LDAPRH = 491 , ARM64_INS_LDAPUR = 492 , ARM64_INS_LDAPURB = 493 , ARM64_INS_LDAPURH = 494 , ARM64_INS_LDAPURSB = 495 , ARM64_INS_LDAPURSH = 496 , ARM64_INS_LDAPURSW = 497 , ARM64_INS_LDAR = 498 , ARM64_INS_LDARB = 499 , ARM64_INS_LDARH = 500 , ARM64_INS_LDAXP = 501 , ARM64_INS_LDAXR = 502 , ARM64_INS_LDAXRB = 503 , ARM64_INS_LDAXRH = 504 , ARM64_INS_LDCLR = 505 , ARM64_INS_LDCLRA = 506 , ARM64_INS_LDCLRAB = 507 , ARM64_INS_LDCLRAH = 508 , ARM64_INS_LDCLRAL = 509 , ARM64_INS_LDCLRALB = 510 , ARM64_INS_LDCLRALH = 511 , ARM64_INS_LDCLRB = 512 , ARM64_INS_LDCLRH = 513 , ARM64_INS_LDCLRL = 514 , ARM64_INS_LDCLRLB = 515 , ARM64_INS_LDCLRLH = 516 , ARM64_INS_LDEOR = 517 , ARM64_INS_LDEORA = 518 , ARM64_INS_LDEORAB = 519 , ARM64_INS_LDEORAH = 520 , ARM64_INS_LDEORAL = 521 , ARM64_INS_LDEORALB = 522 , ARM64_INS_LDEORALH = 523 , ARM64_INS_LDEORB = 524 , ARM64_INS_LDEORH = 525 , ARM64_INS_LDEORL = 526 , ARM64_INS_LDEORLB = 527 , ARM64_INS_LDEORLH = 528 , ARM64_INS_LDFF1B = 529 , ARM64_INS_LDFF1D = 530 , ARM64_INS_LDFF1H = 531 , ARM64_INS_LDFF1SB = 532 , ARM64_INS_LDFF1SH = 533 , ARM64_INS_LDFF1SW = 534 , ARM64_INS_LDFF1W = 535 , ARM64_INS_LDG = 536 , ARM64_INS_LDGM = 537 , ARM64_INS_LDLAR = 538 , ARM64_INS_LDLARB = 539 , ARM64_INS_LDLARH = 540 , ARM64_INS_LDNF1B = 541 , ARM64_INS_LDNF1D = 542 , ARM64_INS_LDNF1H = 543 , ARM64_INS_LDNF1SB = 544 , ARM64_INS_LDNF1SH = 545 , ARM64_INS_LDNF1SW = 546 , ARM64_INS_LDNF1W = 547 , ARM64_INS_LDNP = 548 , ARM64_INS_LDNT1B = 549 , ARM64_INS_LDNT1D = 550 , ARM64_INS_LDNT1H = 551 , ARM64_INS_LDNT1SB = 552 , ARM64_INS_LDNT1SH = 553 , ARM64_INS_LDNT1SW = 554 , ARM64_INS_LDNT1W = 555 , ARM64_INS_LDP = 556 , ARM64_INS_LDPSW = 557 , ARM64_INS_LDR = 558 , ARM64_INS_LDRAA = 559 , ARM64_INS_LDRAB = 560 , ARM64_INS_LDRB = 561 , ARM64_INS_LDRH = 562 , ARM64_INS_LDRSB = 563 , ARM64_INS_LDRSH = 564 , ARM64_INS_LDRSW = 565 , ARM64_INS_LDSET = 566 , ARM64_INS_LDSETA = 567 , ARM64_INS_LDSETAB = 568 , ARM64_INS_LDSETAH = 569 , ARM64_INS_LDSETAL = 570 , ARM64_INS_LDSETALB = 571 , ARM64_INS_LDSETALH = 572 , ARM64_INS_LDSETB = 573 , ARM64_INS_LDSETH = 574 , ARM64_INS_LDSETL = 575 , ARM64_INS_LDSETLB = 576 , ARM64_INS_LDSETLH = 577 , ARM64_INS_LDSMAX = 578 , ARM64_INS_LDSMAXA = 579 , ARM64_INS_LDSMAXAB = 580 , ARM64_INS_LDSMAXAH = 581 , ARM64_INS_LDSMAXAL = 582 , ARM64_INS_LDSMAXALB = 583 , ARM64_INS_LDSMAXALH = 584 , ARM64_INS_LDSMAXB = 585 , ARM64_INS_LDSMAXH = 586 , ARM64_INS_LDSMAXL = 587 , ARM64_INS_LDSMAXLB = 588 , ARM64_INS_LDSMAXLH = 589 , ARM64_INS_LDSMIN = 590 , ARM64_INS_LDSMINA = 591 , ARM64_INS_LDSMINAB = 592 , ARM64_INS_LDSMINAH = 593 , ARM64_INS_LDSMINAL = 594 , ARM64_INS_LDSMINALB = 595 , ARM64_INS_LDSMINALH = 596 , ARM64_INS_LDSMINB = 597 , ARM64_INS_LDSMINH = 598 , ARM64_INS_LDSMINL = 599 , ARM64_INS_LDSMINLB = 600 , ARM64_INS_LDSMINLH = 601 , ARM64_INS_LDTR = 602 , ARM64_INS_LDTRB = 603 , ARM64_INS_LDTRH = 604 , ARM64_INS_LDTRSB = 605 , ARM64_INS_LDTRSH = 606 , ARM64_INS_LDTRSW = 607 , ARM64_INS_LDUMAX = 608 , ARM64_INS_LDUMAXA = 609 , ARM64_INS_LDUMAXAB = 610 , ARM64_INS_LDUMAXAH = 611 , ARM64_INS_LDUMAXAL = 612 , ARM64_INS_LDUMAXALB = 613 , ARM64_INS_LDUMAXALH = 614 , ARM64_INS_LDUMAXB = 615 , ARM64_INS_LDUMAXH = 616 , ARM64_INS_LDUMAXL = 617 , ARM64_INS_LDUMAXLB = 618 , ARM64_INS_LDUMAXLH = 619 , ARM64_INS_LDUMIN = 620 , ARM64_INS_LDUMINA = 621 , ARM64_INS_LDUMINAB = 622 , ARM64_INS_LDUMINAH = 623 , ARM64_INS_LDUMINAL = 624 , ARM64_INS_LDUMINALB = 625 , ARM64_INS_LDUMINALH = 626 , ARM64_INS_LDUMINB = 627 , ARM64_INS_LDUMINH = 628 , ARM64_INS_LDUMINL = 629 , ARM64_INS_LDUMINLB = 630 , ARM64_INS_LDUMINLH = 631 , ARM64_INS_LDUR = 632 , ARM64_INS_LDURB = 633 , ARM64_INS_LDURH = 634 , ARM64_INS_LDURSB = 635 , ARM64_INS_LDURSH = 636 , ARM64_INS_LDURSW = 637 , ARM64_INS_LDXP = 638 , ARM64_INS_LDXR = 639 , ARM64_INS_LDXRB = 640 , ARM64_INS_LDXRH = 641 , ARM64_INS_LSL = 642 , ARM64_INS_LSLR = 643 , ARM64_INS_LSLV = 644 , ARM64_INS_LSR = 645 , ARM64_INS_LSRR = 646 , ARM64_INS_LSRV = 647 , ARM64_INS_MAD = 648 , ARM64_INS_MADD = 649 , ARM64_INS_MATCH = 650 , ARM64_INS_MLA = 651 , ARM64_INS_MLS = 652 , ARM64_INS_MNEG = 653 , ARM64_INS_MOV = 654 , ARM64_INS_MOVA = 655 , ARM64_INS_MOVI = 656 , ARM64_INS_MOVK = 657 , ARM64_INS_MOVN = 658 , ARM64_INS_MOVPRFX = 659 , ARM64_INS_MOVS = 660 , ARM64_INS_MOVZ = 661 , ARM64_INS_MRS = 662 , ARM64_INS_MSB = 663 , ARM64_INS_MSR = 664 , ARM64_INS_MSUB = 665 , ARM64_INS_MUL = 666 , ARM64_INS_MVN = 667 , ARM64_INS_MVNI = 668 , ARM64_INS_NAND = 669 , ARM64_INS_NANDS = 670 , ARM64_INS_NBSL = 671 , ARM64_INS_NEG = 672 , ARM64_INS_NEGS = 673 , ARM64_INS_NGC = 674 , ARM64_INS_NGCS = 675 , ARM64_INS_NMATCH = 676 , ARM64_INS_NOP = 677 , ARM64_INS_NOR = 678 , ARM64_INS_NORS = 679 , ARM64_INS_NOT = 680 , ARM64_INS_NOTS = 681 , ARM64_INS_ORN = 682 , ARM64_INS_ORNS = 683 , ARM64_INS_ORR = 684 , ARM64_INS_ORRS = 685 , ARM64_INS_ORV = 686 , ARM64_INS_PACDA = 687 , ARM64_INS_PACDB = 688 , ARM64_INS_PACDZA = 689 , ARM64_INS_PACDZB = 690 , ARM64_INS_PACGA = 691 , ARM64_INS_PACIA = 692 , ARM64_INS_PACIA1716 = 693 , ARM64_INS_PACIASP = 694 , ARM64_INS_PACIAZ = 695 , ARM64_INS_PACIB = 696 , ARM64_INS_PACIB1716 = 697 , ARM64_INS_PACIBSP = 698 , ARM64_INS_PACIBZ = 699 , ARM64_INS_PACIZA = 700 , ARM64_INS_PACIZB = 701 , ARM64_INS_PFALSE = 702 , ARM64_INS_PFIRST = 703 , ARM64_INS_PMUL = 704 , ARM64_INS_PMULL = 705 , ARM64_INS_PMULL2 = 706 , ARM64_INS_PMULLB = 707 , ARM64_INS_PMULLT = 708 , ARM64_INS_PNEXT = 709 , ARM64_INS_PRFB = 710 , ARM64_INS_PRFD = 711 , ARM64_INS_PRFH = 712 , ARM64_INS_PRFM = 713 , ARM64_INS_PRFUM = 714 , ARM64_INS_PRFW = 715 , ARM64_INS_PSB = 716 , ARM64_INS_PSEL = 717 , ARM64_INS_PSSBB = 718 , ARM64_INS_PTEST = 719 , ARM64_INS_PTRUE = 720 , ARM64_INS_PTRUES = 721 , ARM64_INS_PUNPKHI = 722 , ARM64_INS_PUNPKLO = 723 , ARM64_INS_RADDHN = 724 , ARM64_INS_RADDHN2 = 725 , ARM64_INS_RADDHNB = 726 , ARM64_INS_RADDHNT = 727 , ARM64_INS_RAX1 = 728 , ARM64_INS_RBIT = 729 , ARM64_INS_RDFFR = 730 , ARM64_INS_RDFFRS = 731 , ARM64_INS_RDVL = 732 , ARM64_INS_RET = 733 , ARM64_INS_RETAA = 734 , ARM64_INS_RETAB = 735 , ARM64_INS_REV = 736 , ARM64_INS_REV16 = 737 , ARM64_INS_REV32 = 738 , ARM64_INS_REV64 = 739 , ARM64_INS_REVB = 740 , ARM64_INS_REVD = 741 , ARM64_INS_REVH = 742 , ARM64_INS_REVW = 743 , ARM64_INS_RMIF = 744 , ARM64_INS_ROR = 745 , ARM64_INS_RORV = 746 , ARM64_INS_RSHRN = 747 , ARM64_INS_RSHRN2 = 748 , ARM64_INS_RSHRNB = 749 , ARM64_INS_RSHRNT = 750 , ARM64_INS_RSUBHN = 751 , ARM64_INS_RSUBHN2 = 752 , ARM64_INS_RSUBHNB = 753 , ARM64_INS_RSUBHNT = 754 , ARM64_INS_SABA = 755 , ARM64_INS_SABAL = 756 , ARM64_INS_SABAL2 = 757 , ARM64_INS_SABALB = 758 , ARM64_INS_SABALT = 759 , ARM64_INS_SABD = 760 , ARM64_INS_SABDL = 761 , ARM64_INS_SABDL2 = 762 , ARM64_INS_SABDLB = 763 , ARM64_INS_SABDLT = 764 , ARM64_INS_SADALP = 765 , ARM64_INS_SADDL = 766 , ARM64_INS_SADDL2 = 767 , ARM64_INS_SADDLB = 768 , ARM64_INS_SADDLBT = 769 , ARM64_INS_SADDLP = 770 , ARM64_INS_SADDLT = 771 , ARM64_INS_SADDLV = 772 , ARM64_INS_SADDV = 773 , ARM64_INS_SADDW = 774 , ARM64_INS_SADDW2 = 775 , ARM64_INS_SADDWB = 776 , ARM64_INS_SADDWT = 777 , ARM64_INS_SB = 778 , ARM64_INS_SBC = 779 , ARM64_INS_SBCLB = 780 , ARM64_INS_SBCLT = 781 , ARM64_INS_SBCS = 782 , ARM64_INS_SBFM = 783 , ARM64_INS_SCLAMP = 784 , ARM64_INS_SCVTF = 785 , ARM64_INS_SDIV = 786 , ARM64_INS_SDIVR = 787 , ARM64_INS_SDOT = 788 , ARM64_INS_SEL = 789 , ARM64_INS_SETE = 790 , ARM64_INS_SETEN = 791 , ARM64_INS_SETET = 792 , ARM64_INS_SETETN = 793 , ARM64_INS_SETF16 = 794 , ARM64_INS_SETF8 = 795 , ARM64_INS_SETFFR = 796 , ARM64_INS_SETGE = 797 , ARM64_INS_SETGEN = 798 , ARM64_INS_SETGET = 799 , ARM64_INS_SETGETN = 800 , ARM64_INS_SETGM = 801 , ARM64_INS_SETGMN = 802 , ARM64_INS_SETGMT = 803 , ARM64_INS_SETGMTN = 804 , ARM64_INS_SETGP = 805 , ARM64_INS_SETGPN = 806 , ARM64_INS_SETGPT = 807 , ARM64_INS_SETGPTN = 808 , ARM64_INS_SETM = 809 , ARM64_INS_SETMN = 810 , ARM64_INS_SETMT = 811 , ARM64_INS_SETMTN = 812 , ARM64_INS_SETP = 813 , ARM64_INS_SETPN = 814 , ARM64_INS_SETPT = 815 , ARM64_INS_SETPTN = 816 , ARM64_INS_SEV = 817 , ARM64_INS_SEVL = 818 , ARM64_INS_SHA1C = 819 , ARM64_INS_SHA1H = 820 , ARM64_INS_SHA1M = 821 , ARM64_INS_SHA1P = 822 , ARM64_INS_SHA1SU0 = 823 , ARM64_INS_SHA1SU1 = 824 , ARM64_INS_SHA256H = 825 , ARM64_INS_SHA256H2 = 826 , ARM64_INS_SHA256SU0 = 827 , ARM64_INS_SHA256SU1 = 828 , ARM64_INS_SHA512H = 829 , ARM64_INS_SHA512H2 = 830 , ARM64_INS_SHA512SU0 = 831 , ARM64_INS_SHA512SU1 = 832 , ARM64_INS_SHADD = 833 , ARM64_INS_SHL = 834 , ARM64_INS_SHLL = 835 , ARM64_INS_SHLL2 = 836 , ARM64_INS_SHRN = 837 , ARM64_INS_SHRN2 = 838 , ARM64_INS_SHRNB = 839 , ARM64_INS_SHRNT = 840 , ARM64_INS_SHSUB = 841 , ARM64_INS_SHSUBR = 842 , ARM64_INS_SLI = 843 , ARM64_INS_SM3PARTW1 = 844 , ARM64_INS_SM3PARTW2 = 845 , ARM64_INS_SM3SS1 = 846 , ARM64_INS_SM3TT1A = 847 , ARM64_INS_SM3TT1B = 848 , ARM64_INS_SM3TT2A = 849 , ARM64_INS_SM3TT2B = 850 , ARM64_INS_SM4E = 851 , ARM64_INS_SM4EKEY = 852 , ARM64_INS_SMADDL = 853 , ARM64_INS_SMAX = 854 , ARM64_INS_SMAXP = 855 , ARM64_INS_SMAXV = 856 , ARM64_INS_SMC = 857 , ARM64_INS_SMIN = 858 , ARM64_INS_SMINP = 859 , ARM64_INS_SMINV = 860 , ARM64_INS_SMLAL = 861 , ARM64_INS_SMLAL2 = 862 , ARM64_INS_SMLALB = 863 , ARM64_INS_SMLALT = 864 , ARM64_INS_SMLSL = 865 , ARM64_INS_SMLSL2 = 866 , ARM64_INS_SMLSLB = 867 , ARM64_INS_SMLSLT = 868 , ARM64_INS_SMMLA = 869 , ARM64_INS_SMNEGL = 870 , ARM64_INS_SMOPA = 871 , ARM64_INS_SMOPS = 872 , ARM64_INS_SMOV = 873 , ARM64_INS_SMSTART = 874 , ARM64_INS_SMSTOP = 875 , ARM64_INS_SMSUBL = 876 , ARM64_INS_SMULH = 877 , ARM64_INS_SMULL = 878 , ARM64_INS_SMULL2 = 879 , ARM64_INS_SMULLB = 880 , ARM64_INS_SMULLT = 881 , ARM64_INS_SPLICE = 882 , ARM64_INS_SQABS = 883 , ARM64_INS_SQADD = 884 , ARM64_INS_SQCADD = 885 , ARM64_INS_SQDECB = 886 , ARM64_INS_SQDECD = 887 , ARM64_INS_SQDECH = 888 , ARM64_INS_SQDECP = 889 , ARM64_INS_SQDECW = 890 , ARM64_INS_SQDMLAL = 891 , ARM64_INS_SQDMLAL2 = 892 , ARM64_INS_SQDMLALB = 893 , ARM64_INS_SQDMLALBT = 894 , ARM64_INS_SQDMLALT = 895 , ARM64_INS_SQDMLSL = 896 , ARM64_INS_SQDMLSL2 = 897 , ARM64_INS_SQDMLSLB = 898 , ARM64_INS_SQDMLSLBT = 899 , ARM64_INS_SQDMLSLT = 900 , ARM64_INS_SQDMULH = 901 , ARM64_INS_SQDMULL = 902 , ARM64_INS_SQDMULL2 = 903 , ARM64_INS_SQDMULLB = 904 , ARM64_INS_SQDMULLT = 905 , ARM64_INS_SQINCB = 906 , ARM64_INS_SQINCD = 907 , ARM64_INS_SQINCH = 908 , ARM64_INS_SQINCP = 909 , ARM64_INS_SQINCW = 910 , ARM64_INS_SQNEG = 911 , ARM64_INS_SQRDCMLAH = 912 , ARM64_INS_SQRDMLAH = 913 , ARM64_INS_SQRDMLSH = 914 , ARM64_INS_SQRDMULH = 915 , ARM64_INS_SQRSHL = 916 , ARM64_INS_SQRSHLR = 917 , ARM64_INS_SQRSHRN = 918 , ARM64_INS_SQRSHRN2 = 919 , ARM64_INS_SQRSHRNB = 920 , ARM64_INS_SQRSHRNT = 921 , ARM64_INS_SQRSHRUN = 922 , ARM64_INS_SQRSHRUN2 = 923 , ARM64_INS_SQRSHRUNB = 924 , ARM64_INS_SQRSHRUNT = 925 , ARM64_INS_SQSHL = 926 , ARM64_INS_SQSHLR = 927 , ARM64_INS_SQSHLU = 928 , ARM64_INS_SQSHRN = 929 , ARM64_INS_SQSHRN2 = 930 , ARM64_INS_SQSHRNB = 931 , ARM64_INS_SQSHRNT = 932 , ARM64_INS_SQSHRUN = 933 , ARM64_INS_SQSHRUN2 = 934 , ARM64_INS_SQSHRUNB = 935 , ARM64_INS_SQSHRUNT = 936 , ARM64_INS_SQSUB = 937 , ARM64_INS_SQSUBR = 938 , ARM64_INS_SQXTN = 939 , ARM64_INS_SQXTN2 = 940 , ARM64_INS_SQXTNB = 941 , ARM64_INS_SQXTNT = 942 , ARM64_INS_SQXTUN = 943 , ARM64_INS_SQXTUN2 = 944 , ARM64_INS_SQXTUNB = 945 , ARM64_INS_SQXTUNT = 946 , ARM64_INS_SRHADD = 947 , ARM64_INS_SRI = 948 , ARM64_INS_SRSHL = 949 , ARM64_INS_SRSHLR = 950 , ARM64_INS_SRSHR = 951 , ARM64_INS_SRSRA = 952 , ARM64_INS_SSBB = 953 , ARM64_INS_SSHL = 954 , ARM64_INS_SSHLL = 955 , ARM64_INS_SSHLL2 = 956 , ARM64_INS_SSHLLB = 957 , ARM64_INS_SSHLLT = 958 , ARM64_INS_SSHR = 959 , ARM64_INS_SSRA = 960 , ARM64_INS_SSUBL = 961 , ARM64_INS_SSUBL2 = 962 , ARM64_INS_SSUBLB = 963 , ARM64_INS_SSUBLBT = 964 , ARM64_INS_SSUBLT = 965 , ARM64_INS_SSUBLTB = 966 , ARM64_INS_SSUBW = 967 , ARM64_INS_SSUBW2 = 968 , ARM64_INS_SSUBWB = 969 , ARM64_INS_SSUBWT = 970 , ARM64_INS_ST1 = 971 , ARM64_INS_ST1B = 972 , ARM64_INS_ST1D = 973 , ARM64_INS_ST1H = 974 , ARM64_INS_ST1Q = 975 , ARM64_INS_ST1W = 976 , ARM64_INS_ST2 = 977 , ARM64_INS_ST2B = 978 , ARM64_INS_ST2D = 979 , ARM64_INS_ST2G = 980 , ARM64_INS_ST2H = 981 , ARM64_INS_ST2W = 982 , ARM64_INS_ST3 = 983 , ARM64_INS_ST3B = 984 , ARM64_INS_ST3D = 985 , ARM64_INS_ST3H = 986 , ARM64_INS_ST3W = 987 , ARM64_INS_ST4 = 988 , ARM64_INS_ST4B = 989 , ARM64_INS_ST4D = 990 , ARM64_INS_ST4H = 991 , ARM64_INS_ST4W = 992 , ARM64_INS_ST64B = 993 , ARM64_INS_ST64BV = 994 , ARM64_INS_ST64BV0 = 995 , ARM64_INS_STADD = 996 , ARM64_INS_STADDB = 997 , ARM64_INS_STADDH = 998 , ARM64_INS_STADDL = 999 , ARM64_INS_STADDLB = 1000 , ARM64_INS_STADDLH = 1001 , ARM64_INS_STCLR = 1002 , ARM64_INS_STCLRB = 1003 , ARM64_INS_STCLRH = 1004 , ARM64_INS_STCLRL = 1005 , ARM64_INS_STCLRLB = 1006 , ARM64_INS_STCLRLH = 1007 , ARM64_INS_STEOR = 1008 , ARM64_INS_STEORB = 1009 , ARM64_INS_STEORH = 1010 , ARM64_INS_STEORL = 1011 , ARM64_INS_STEORLB = 1012 , ARM64_INS_STEORLH = 1013 , ARM64_INS_STG = 1014 , ARM64_INS_STGM = 1015 , ARM64_INS_STGP = 1016 , ARM64_INS_STLLR = 1017 , ARM64_INS_STLLRB = 1018 , ARM64_INS_STLLRH = 1019 , ARM64_INS_STLR = 1020 , ARM64_INS_STLRB = 1021 , ARM64_INS_STLRH = 1022 , ARM64_INS_STLUR = 1023 , ARM64_INS_STLURB = 1024 , ARM64_INS_STLURH = 1025 , ARM64_INS_STLXP = 1026 , ARM64_INS_STLXR = 1027 , ARM64_INS_STLXRB = 1028 , ARM64_INS_STLXRH = 1029 , ARM64_INS_STNP = 1030 , ARM64_INS_STNT1B = 1031 , ARM64_INS_STNT1D = 1032 , ARM64_INS_STNT1H = 1033 , ARM64_INS_STNT1W = 1034 , ARM64_INS_STP = 1035 , ARM64_INS_STR = 1036 , ARM64_INS_STRB = 1037 , ARM64_INS_STRH = 1038 , ARM64_INS_STSET = 1039 , ARM64_INS_STSETB = 1040 , ARM64_INS_STSETH = 1041 , ARM64_INS_STSETL = 1042 , ARM64_INS_STSETLB = 1043 , ARM64_INS_STSETLH = 1044 , ARM64_INS_STSMAX = 1045 , ARM64_INS_STSMAXB = 1046 , ARM64_INS_STSMAXH = 1047 , ARM64_INS_STSMAXL = 1048 , ARM64_INS_STSMAXLB = 1049 , ARM64_INS_STSMAXLH = 1050 , ARM64_INS_STSMIN = 1051 , ARM64_INS_STSMINB = 1052 , ARM64_INS_STSMINH = 1053 , ARM64_INS_STSMINL = 1054 , ARM64_INS_STSMINLB = 1055 , ARM64_INS_STSMINLH = 1056 , ARM64_INS_STTR = 1057 , ARM64_INS_STTRB = 1058 , ARM64_INS_STTRH = 1059 , ARM64_INS_STUMAX = 1060 , ARM64_INS_STUMAXB = 1061 , ARM64_INS_STUMAXH = 1062 , ARM64_INS_STUMAXL = 1063 , ARM64_INS_STUMAXLB = 1064 , ARM64_INS_STUMAXLH = 1065 , ARM64_INS_STUMIN = 1066 , ARM64_INS_STUMINB = 1067 , ARM64_INS_STUMINH = 1068 , ARM64_INS_STUMINL = 1069 , ARM64_INS_STUMINLB = 1070 , ARM64_INS_STUMINLH = 1071 , ARM64_INS_STUR = 1072 , ARM64_INS_STURB = 1073 , ARM64_INS_STURH = 1074 , ARM64_INS_STXP = 1075 , ARM64_INS_STXR = 1076 , ARM64_INS_STXRB = 1077 , ARM64_INS_STXRH = 1078 , ARM64_INS_STZ2G = 1079 , ARM64_INS_STZG = 1080 , ARM64_INS_STZGM = 1081 , ARM64_INS_SUB = 1082 , ARM64_INS_SUBG = 1083 , ARM64_INS_SUBHN = 1084 , ARM64_INS_SUBHN2 = 1085 , ARM64_INS_SUBHNB = 1086 , ARM64_INS_SUBHNT = 1087 , ARM64_INS_SUBP = 1088 , ARM64_INS_SUBPS = 1089 , ARM64_INS_SUBR = 1090 , ARM64_INS_SUBS = 1091 , ARM64_INS_SUDOT = 1092 , ARM64_INS_SUMOPA = 1093 , ARM64_INS_SUMOPS = 1094 , ARM64_INS_SUNPKHI = 1095 , ARM64_INS_SUNPKLO = 1096 , ARM64_INS_SUQADD = 1097 , ARM64_INS_SVC = 1098 , ARM64_INS_SWP = 1099 , ARM64_INS_SWPA = 1100 , ARM64_INS_SWPAB = 1101 , ARM64_INS_SWPAH = 1102 , ARM64_INS_SWPAL = 1103 , ARM64_INS_SWPALB = 1104 , ARM64_INS_SWPALH = 1105 , ARM64_INS_SWPB = 1106 , ARM64_INS_SWPH = 1107 , ARM64_INS_SWPL = 1108 , ARM64_INS_SWPLB = 1109 , ARM64_INS_SWPLH = 1110 , ARM64_INS_SXTB = 1111 , ARM64_INS_SXTH = 1112 , ARM64_INS_SXTL = 1113 , ARM64_INS_SXTL2 = 1114 , ARM64_INS_SXTW = 1115 , ARM64_INS_SYS = 1116 , ARM64_INS_SYSL = 1117 , ARM64_INS_TBL = 1118 , ARM64_INS_TBNZ = 1119 , ARM64_INS_TBX = 1120 , ARM64_INS_TBZ = 1121 , ARM64_INS_TCANCEL = 1122 , ARM64_INS_TCOMMIT = 1123 , ARM64_INS_TRN1 = 1124 , ARM64_INS_TRN2 = 1125 , ARM64_INS_TSB = 1126 , ARM64_INS_TST = 1127 , ARM64_INS_TSTART = 1128 , ARM64_INS_TTEST = 1129 , ARM64_INS_UABA = 1130 , ARM64_INS_UABAL = 1131 , ARM64_INS_UABAL2 = 1132 , ARM64_INS_UABALB = 1133 , ARM64_INS_UABALT = 1134 , ARM64_INS_UABD = 1135 , ARM64_INS_UABDL = 1136 , ARM64_INS_UABDL2 = 1137 , ARM64_INS_UABDLB = 1138 , ARM64_INS_UABDLT = 1139 , ARM64_INS_UADALP = 1140 , ARM64_INS_UADDL = 1141 , ARM64_INS_UADDL2 = 1142 , ARM64_INS_UADDLB = 1143 , ARM64_INS_UADDLP = 1144 , ARM64_INS_UADDLT = 1145 , ARM64_INS_UADDLV = 1146 , ARM64_INS_UADDV = 1147 , ARM64_INS_UADDW = 1148 , ARM64_INS_UADDW2 = 1149 , ARM64_INS_UADDWB = 1150 , ARM64_INS_UADDWT = 1151 , ARM64_INS_UBFM = 1152 , ARM64_INS_UCLAMP = 1153 , ARM64_INS_UCVTF = 1154 , ARM64_INS_UDF = 1155 , ARM64_INS_UDIV = 1156 , ARM64_INS_UDIVR = 1157 , ARM64_INS_UDOT = 1158 , ARM64_INS_UHADD = 1159 , ARM64_INS_UHSUB = 1160 , ARM64_INS_UHSUBR = 1161 , ARM64_INS_UMADDL = 1162 , ARM64_INS_UMAX = 1163 , ARM64_INS_UMAXP = 1164 , ARM64_INS_UMAXV = 1165 , ARM64_INS_UMIN = 1166 , ARM64_INS_UMINP = 1167 , ARM64_INS_UMINV = 1168 , ARM64_INS_UMLAL = 1169 , ARM64_INS_UMLAL2 = 1170 , ARM64_INS_UMLALB = 1171 , ARM64_INS_UMLALT = 1172 , ARM64_INS_UMLSL = 1173 , ARM64_INS_UMLSL2 = 1174 , ARM64_INS_UMLSLB = 1175 , ARM64_INS_UMLSLT = 1176 , ARM64_INS_UMMLA = 1177 , ARM64_INS_UMNEGL = 1178 , ARM64_INS_UMOPA = 1179 , ARM64_INS_UMOPS = 1180 , ARM64_INS_UMOV = 1181 , ARM64_INS_UMSUBL = 1182 , ARM64_INS_UMULH = 1183 , ARM64_INS_UMULL = 1184 , ARM64_INS_UMULL2 = 1185 , ARM64_INS_UMULLB = 1186 , ARM64_INS_UMULLT = 1187 , ARM64_INS_UQADD = 1188 , ARM64_INS_UQDECB = 1189 , ARM64_INS_UQDECD = 1190 , ARM64_INS_UQDECH = 1191 , ARM64_INS_UQDECP = 1192 , ARM64_INS_UQDECW = 1193 , ARM64_INS_UQINCB = 1194 , ARM64_INS_UQINCD = 1195 , ARM64_INS_UQINCH = 1196 , ARM64_INS_UQINCP = 1197 , ARM64_INS_UQINCW = 1198 , ARM64_INS_UQRSHL = 1199 , ARM64_INS_UQRSHLR = 1200 , ARM64_INS_UQRSHRN = 1201 , ARM64_INS_UQRSHRN2 = 1202 , ARM64_INS_UQRSHRNB = 1203 , ARM64_INS_UQRSHRNT = 1204 , ARM64_INS_UQSHL = 1205 , ARM64_INS_UQSHLR = 1206 , ARM64_INS_UQSHRN = 1207 , ARM64_INS_UQSHRN2 = 1208 , ARM64_INS_UQSHRNB = 1209 , ARM64_INS_UQSHRNT = 1210 , ARM64_INS_UQSUB = 1211 , ARM64_INS_UQSUBR = 1212 , ARM64_INS_UQXTN = 1213 , ARM64_INS_UQXTN2 = 1214 , ARM64_INS_UQXTNB = 1215 , ARM64_INS_UQXTNT = 1216 , ARM64_INS_URECPE = 1217 , ARM64_INS_URHADD = 1218 , ARM64_INS_URSHL = 1219 , ARM64_INS_URSHLR = 1220 , ARM64_INS_URSHR = 1221 , ARM64_INS_URSQRTE = 1222 , ARM64_INS_URSRA = 1223 , ARM64_INS_USDOT = 1224 , ARM64_INS_USHL = 1225 , ARM64_INS_USHLL = 1226 , ARM64_INS_USHLL2 = 1227 , ARM64_INS_USHLLB = 1228 , ARM64_INS_USHLLT = 1229 , ARM64_INS_USHR = 1230 , ARM64_INS_USMMLA = 1231 , ARM64_INS_USMOPA = 1232 , ARM64_INS_USMOPS = 1233 , ARM64_INS_USQADD = 1234 , ARM64_INS_USRA = 1235 , ARM64_INS_USUBL = 1236 , ARM64_INS_USUBL2 = 1237 , ARM64_INS_USUBLB = 1238 , ARM64_INS_USUBLT = 1239 , ARM64_INS_USUBW = 1240 , ARM64_INS_USUBW2 = 1241 , ARM64_INS_USUBWB = 1242 , ARM64_INS_USUBWT = 1243 , ARM64_INS_UUNPKHI = 1244 , ARM64_INS_UUNPKLO = 1245 , ARM64_INS_UXTB = 1246 , ARM64_INS_UXTH = 1247 , ARM64_INS_UXTL = 1248 , ARM64_INS_UXTL2 = 1249 , ARM64_INS_UXTW = 1250 , ARM64_INS_UZP1 = 1251 , ARM64_INS_UZP2 = 1252 , ARM64_INS_WFE = 1253 , ARM64_INS_WFET = 1254 , ARM64_INS_WFI = 1255 , ARM64_INS_WFIT = 1256 , ARM64_INS_WHILEGE = 1257 , ARM64_INS_WHILEGT = 1258 , ARM64_INS_WHILEHI = 1259 , ARM64_INS_WHILEHS = 1260 , ARM64_INS_WHILELE = 1261 , ARM64_INS_WHILELO = 1262 , ARM64_INS_WHILELS = 1263 , ARM64_INS_WHILELT = 1264 , ARM64_INS_WHILERW = 1265 , ARM64_INS_WHILEWR = 1266 , ARM64_INS_WRFFR = 1267 , ARM64_INS_XAFLAG = 1268 , ARM64_INS_XAR = 1269 , ARM64_INS_XPACD = 1270 , ARM64_INS_XPACI = 1271 , ARM64_INS_XPACLRI = 1272 , ARM64_INS_XTN = 1273 , ARM64_INS_XTN2 = 1274 , ARM64_INS_YIELD = 1275 , ARM64_INS_ZERO = 1276 , ARM64_INS_ZIP1 = 1277 , ARM64_INS_ZIP2 = 1278 , ARM64_INS_SBFIZ = 1279 , ARM64_INS_UBFIZ = 1280 , ARM64_INS_SBFX = 1281 , ARM64_INS_UBFX = 1282 , ARM64_INS_BFI = 1283 , ARM64_INS_BFXIL = 1284 , ARM64_INS_IC = 1285 , ARM64_INS_DC = 1286 , ARM64_INS_AT = 1287 , ARM64_INS_TLBI = 1288 , ARM64_INS_ENDING = 1289 , } # [repr (u32)] # [doc = " Group of ARM64 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM64_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM64_GRP_JUMP = 1 , ARM64_GRP_CALL = 2 , ARM64_GRP_RET = 3 , ARM64_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM64_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM64_GRP_BRANCH_RELATIVE = 7 , ARM64_GRP_PAC = 8 , ARM64_GRP_CRYPTO = 128 , ARM64_GRP_FPARMV8 = 129 , ARM64_GRP_NEON = 130 , ARM64_GRP_CRC = 131 , ARM64_GRP_AES = 132 , ARM64_GRP_DOTPROD = 133 , ARM64_GRP_FULLFP16 = 134 , ARM64_GRP_LSE = 135 , ARM64_GRP_RCPC = 136 , ARM64_GRP_RDM = 137 , ARM64_GRP_SHA2 = 138 , ARM64_GRP_SHA3 = 139 , ARM64_GRP_SM4 = 140 , ARM64_GRP_SVE = 141 , ARM64_GRP_SVE2 = 142 , ARM64_GRP_SVE2AES = 143 , ARM64_GRP_SVE2BitPerm = 144 , ARM64_GRP_SVE2SHA3 = 145 , ARM64_GRP_SVE2SM4 = 146 , ARM64_GRP_SME = 147 , ARM64_GRP_SMEF64 = 148 , ARM64_GRP_SMEI64 = 149 , ARM64_GRP_MatMulFP32 = 150 , ARM64_GRP_MatMulFP64 = 151 , ARM64_GRP_MatMulInt8 = 152 , ARM64_GRP_V8_1A = 153 , ARM64_GRP_V8_3A = 154 , ARM64_GRP_V8_4A = 155 , ARM64_GRP_ENDING = 156 , } # [repr (u32)] # [doc = " M68K registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_reg { M68K_REG_INVALID = 0 , M68K_REG_D0 = 1 , M68K_REG_D1 = 2 , M68K_REG_D2 = 3 , M68K_REG_D3 = 4 , M68K_REG_D4 = 5 , M68K_REG_D5 = 6 , M68K_REG_D6 = 7 , M68K_REG_D7 = 8 , M68K_REG_A0 = 9 , M68K_REG_A1 = 10 , M68K_REG_A2 = 11 , M68K_REG_A3 = 12 , M68K_REG_A4 = 13 , M68K_REG_A5 = 14 , M68K_REG_A6 = 15 , M68K_REG_A7 = 16 , M68K_REG_FP0 = 17 , M68K_REG_FP1 = 18 , M68K_REG_FP2 = 19 , M68K_REG_FP3 = 20 , M68K_REG_FP4 = 21 , M68K_REG_FP5 = 22 , M68K_REG_FP6 = 23 , M68K_REG_FP7 = 24 , M68K_REG_PC = 25 , M68K_REG_SR = 26 , M68K_REG_CCR = 27 , M68K_REG_SFC = 28 , M68K_REG_DFC = 29 , M68K_REG_USP = 30 , M68K_REG_VBR = 31 , M68K_REG_CACR = 32 , M68K_REG_CAAR = 33 , M68K_REG_MSP = 34 , M68K_REG_ISP = 35 , M68K_REG_TC = 36 , M68K_REG_ITT0 = 37 , M68K_REG_ITT1 = 38 , M68K_REG_DTT0 = 39 , M68K_REG_DTT1 = 40 , M68K_REG_MMUSR = 41 , M68K_REG_URP = 42 , M68K_REG_SRP = 43 , M68K_REG_FPCR = 44 , M68K_REG_FPSR = 45 , M68K_REG_FPIAR = 46 , M68K_REG_ENDING = 47 , } # [repr (u32)] # [doc = " M68K Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_address_mode { # [doc = "< No address mode."] M68K_AM_NONE = 0 , # [doc = "< Register Direct - Data"] M68K_AM_REG_DIRECT_DATA = 1 , # [doc = "< Register Direct - Address"] M68K_AM_REG_DIRECT_ADDR = 2 , # [doc = "< Register Indirect - Address"] M68K_AM_REGI_ADDR = 3 , # [doc = "< Register Indirect - Address with Postincrement"] M68K_AM_REGI_ADDR_POST_INC = 4 , # [doc = "< Register Indirect - Address with Predecrement"] M68K_AM_REGI_ADDR_PRE_DEC = 5 , # [doc = "< Register Indirect - Address with Displacement"] M68K_AM_REGI_ADDR_DISP = 6 , # [doc = "< Address Register Indirect With Index- 8-bit displacement"] M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 , # [doc = "< Address Register Indirect With Index- Base displacement"] M68K_AM_AREGI_INDEX_BASE_DISP = 8 , # [doc = "< Memory indirect - Postindex"] M68K_AM_MEMI_POST_INDEX = 9 , # [doc = "< Memory indirect - Preindex"] M68K_AM_MEMI_PRE_INDEX = 10 , # [doc = "< Program Counter Indirect - with Displacement"] M68K_AM_PCI_DISP = 11 , # [doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"] M68K_AM_PCI_INDEX_8_BIT_DISP = 12 , # [doc = "< Program Counter Indirect with Index - with Base Displacement"] M68K_AM_PCI_INDEX_BASE_DISP = 13 , # [doc = "< Program Counter Memory Indirect - Postindexed"] M68K_AM_PC_MEMI_POST_INDEX = 14 , # [doc = "< Program Counter Memory Indirect - Preindexed"] M68K_AM_PC_MEMI_PRE_INDEX = 15 , # [doc = "< Absolute Data Addressing  - Short"] M68K_AM_ABSOLUTE_DATA_SHORT = 16 , # [doc = "< Absolute Data Addressing  - Long"] M68K_AM_ABSOLUTE_DATA_LONG = 17 , # [doc = "< Immediate value"] M68K_AM_IMMEDIATE = 18 , # [doc = "< Address as displacement from (PC+2) used by branches"] M68K_AM_BRANCH_DISPLACEMENT = 19 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] M68K_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] M68K_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] M68K_OP_MEM = 3 , # [doc = "< single precision Floating-Point operand"] M68K_OP_FP_SINGLE = 4 , # [doc = "< double precision Floating-Point operand"] M68K_OP_FP_DOUBLE = 5 , # [doc = "< Register bits move"] M68K_OP_REG_BITS = 6 , # [doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"] M68K_OP_REG_PAIR = 7 , # [doc = "< Branch displacement"] M68K_OP_BR_DISP = 8 , } # [doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_mem { # [doc = "< base register (or M68K_REG_INVALID if irrelevant)"] pub base_reg : m68k_reg , # [doc = "< index register (or M68K_REG_INVALID if irrelevant)"] pub index_reg : m68k_reg , # [doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"] pub in_base_reg : m68k_reg , # [doc = "< indirect displacement"] pub in_disp : u32 , # [doc = "< other displacement"] pub out_disp : u32 , # [doc = "< displacement value"] pub disp : i16 , # [doc = "< scale for index register"] pub scale : u8 , # [doc = "< set to true if the two values below should be used"] pub bitfield : u8 , # [doc = "< used for bf* instructions"] pub width : u8 , # [doc = "< used for bf* instructions"] pub offset : u8 , # [doc = "< 0 = w, 1 = l"] pub index_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_mem"] [:: std :: mem :: size_of :: < m68k_op_mem > () - 28usize] ; ["Alignment of m68k_op_mem"] [:: std :: mem :: align_of :: < m68k_op_mem > () - 4usize] ; ["Offset of field: m68k_op_mem::base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , base_reg) - 0usize] ; ["Offset of field: m68k_op_mem::index_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_reg) - 4usize] ; ["Offset of field: m68k_op_mem::in_base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_base_reg) - 8usize] ; ["Offset of field: m68k_op_mem::in_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_disp) - 12usize] ; ["Offset of field: m68k_op_mem::out_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , out_disp) - 16usize] ; ["Offset of field: m68k_op_mem::disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , disp) - 20usize] ; ["Offset of field: m68k_op_mem::scale"] [:: std :: mem :: offset_of ! (m68k_op_mem , scale) - 22usize] ; ["Offset of field: m68k_op_mem::bitfield"] [:: std :: mem :: offset_of ! (m68k_op_mem , bitfield) - 23usize] ; ["Offset of field: m68k_op_mem::width"] [:: std :: mem :: offset_of ! (m68k_op_mem , width) - 24usize] ; ["Offset of field: m68k_op_mem::offset"] [:: std :: mem :: offset_of ! (m68k_op_mem , offset) - 25usize] ; ["Offset of field: m68k_op_mem::index_size"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_size) - 26usize] ; } ; # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_br_disp_size { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_BR_DISP_SIZE_INVALID = 0 , # [doc = "< signed 8-bit displacement"] M68K_OP_BR_DISP_SIZE_BYTE = 1 , # [doc = "< signed 16-bit displacement"] M68K_OP_BR_DISP_SIZE_WORD = 2 , # [doc = "< signed 32-bit displacement"] M68K_OP_BR_DISP_SIZE_LONG = 4 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_br_disp { # [doc = "< displacement value"] pub disp : i32 , # [doc = "< Size from m68k_op_br_disp_size type above"] pub disp_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_br_disp"] [:: std :: mem :: size_of :: < m68k_op_br_disp > () - 8usize] ; ["Alignment of m68k_op_br_disp"] [:: std :: mem :: align_of :: < m68k_op_br_disp > () - 4usize] ; ["Offset of field: m68k_op_br_disp::disp"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp) - 0usize] ; ["Offset of field: m68k_op_br_disp::disp_size"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp_size) - 4usize] ; } ; # [doc = " Register pair in one operand."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_m68k_op_reg_pair { pub reg_0 : m68k_reg , pub reg_1 : m68k_reg , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op_reg_pair"] [:: std :: mem :: size_of :: < cs_m68k_op_reg_pair > () - 8usize] ; ["Alignment of cs_m68k_op_reg_pair"] [:: std :: mem :: align_of :: < cs_m68k_op_reg_pair > () - 4usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_0"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_0) - 0usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_1"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_1) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k_op { pub __bindgen_anon_1 : cs_m68k_op__bindgen_ty_1 , # [doc = "< data when operand is targeting memory"] pub mem : m68k_op_mem , # [doc = "< data when operand is a branch displacement"] pub br_disp : m68k_op_br_disp , # [doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"] pub register_bits : u32 , pub type_ : m68k_op_type , # [doc = "< M68K addressing mode for this op"] pub address_mode : m68k_address_mode , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m68k_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< double imm"] pub dimm : f64 , # [doc = "< float imm"] pub simm : f32 , # [doc = "< register value for REG operand"] pub reg : m68k_reg , # [doc = "< register pair in one operand"] pub reg_pair : cs_m68k_op_reg_pair , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::dimm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , dimm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::simm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , simm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg_pair"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg_pair) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op"] [:: std :: mem :: size_of :: < cs_m68k_op > () - 56usize] ; ["Alignment of cs_m68k_op"] [:: std :: mem :: align_of :: < cs_m68k_op > () - 8usize] ; ["Offset of field: cs_m68k_op::mem"] [:: std :: mem :: offset_of ! (cs_m68k_op , mem) - 8usize] ; ["Offset of field: cs_m68k_op::br_disp"] [:: std :: mem :: offset_of ! (cs_m68k_op , br_disp) - 36usize] ; ["Offset of field: cs_m68k_op::register_bits"] [:: std :: mem :: offset_of ! (cs_m68k_op , register_bits) - 44usize] ; ["Offset of field: cs_m68k_op::type_"] [:: std :: mem :: offset_of ! (cs_m68k_op , type_) - 48usize] ; ["Offset of field: cs_m68k_op::address_mode"] [:: std :: mem :: offset_of ! (cs_m68k_op , address_mode) - 52usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode) } } # [repr (u32)] # [doc = " Operation size of the CPU instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_cpu_size { # [doc = "< unsized or unspecified"] M68K_CPU_SIZE_NONE = 0 , # [doc = "< 1 byte in size"] M68K_CPU_SIZE_BYTE = 1 , # [doc = "< 2 bytes in size"] M68K_CPU_SIZE_WORD = 2 , # [doc = "< 4 bytes in size"] M68K_CPU_SIZE_LONG = 4 , } # [repr (u32)] # [doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_fpu_size { # [doc = "< unsized like fsave/frestore"] M68K_FPU_SIZE_NONE = 0 , # [doc = "< 4 byte in size (single float)"] M68K_FPU_SIZE_SINGLE = 4 , # [doc = "< 8 byte in size (double)"] M68K_FPU_SIZE_DOUBLE = 8 , # [doc = "< 12 byte in size (extended real format)"] M68K_FPU_SIZE_EXTENDED = 12 , } # [repr (u32)] # [doc = " Type of size that is being used for the current instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0 , M68K_SIZE_TYPE_CPU = 1 , M68K_SIZE_TYPE_FPU = 2 , } # [doc = " Operation size of the current instruction (NOT the actually size of instruction)"] # [repr (C)] # [derive (Copy , Clone)] pub struct m68k_op_size { pub type_ : m68k_size_type , pub __bindgen_anon_1 : m68k_op_size__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union m68k_op_size__bindgen_ty_1 { pub cpu_size : m68k_cpu_size , pub fpu_size : m68k_fpu_size , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: size_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Alignment of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: align_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::cpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , cpu_size) - 0usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::fpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , fpu_size) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size"] [:: std :: mem :: size_of :: < m68k_op_size > () - 8usize] ; ["Alignment of m68k_op_size"] [:: std :: mem :: align_of :: < m68k_op_size > () - 4usize] ; ["Offset of field: m68k_op_size::type_"] [:: std :: mem :: offset_of ! (m68k_op_size , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The M68K instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k { # [doc = "< operands for this instruction."] pub operands : [cs_m68k_op ; 4usize] , # [doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"] pub op_size : m68k_op_size , # [doc = "< number of operands for the instruction"] pub op_count : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k"] [:: std :: mem :: size_of :: < cs_m68k > () - 240usize] ; ["Alignment of cs_m68k"] [:: std :: mem :: align_of :: < cs_m68k > () - 8usize] ; ["Offset of field: cs_m68k::operands"] [:: std :: mem :: offset_of ! (cs_m68k , operands) - 0usize] ; ["Offset of field: cs_m68k::op_size"] [:: std :: mem :: offset_of ! (cs_m68k , op_size) - 224usize] ; ["Offset of field: cs_m68k::op_count"] [:: std :: mem :: offset_of ! (cs_m68k , op_count) - 232usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}" , self . operands , self . op_size , self . op_count) } } # [repr (u32)] # [doc = " M68K instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_insn { M68K_INS_INVALID = 0 , M68K_INS_ABCD = 1 , M68K_INS_ADD = 2 , M68K_INS_ADDA = 3 , M68K_INS_ADDI = 4 , M68K_INS_ADDQ = 5 , M68K_INS_ADDX = 6 , M68K_INS_AND = 7 , M68K_INS_ANDI = 8 , M68K_INS_ASL = 9 , M68K_INS_ASR = 10 , M68K_INS_BHS = 11 , M68K_INS_BLO = 12 , M68K_INS_BHI = 13 , M68K_INS_BLS = 14 , M68K_INS_BCC = 15 , M68K_INS_BCS = 16 , M68K_INS_BNE = 17 , M68K_INS_BEQ = 18 , M68K_INS_BVC = 19 , M68K_INS_BVS = 20 , M68K_INS_BPL = 21 , M68K_INS_BMI = 22 , M68K_INS_BGE = 23 , M68K_INS_BLT = 24 , M68K_INS_BGT = 25 , M68K_INS_BLE = 26 , M68K_INS_BRA = 27 , M68K_INS_BSR = 28 , M68K_INS_BCHG = 29 , M68K_INS_BCLR = 30 , M68K_INS_BSET = 31 , M68K_INS_BTST = 32 , M68K_INS_BFCHG = 33 , M68K_INS_BFCLR = 34 , M68K_INS_BFEXTS = 35 , M68K_INS_BFEXTU = 36 , M68K_INS_BFFFO = 37 , M68K_INS_BFINS = 38 , M68K_INS_BFSET = 39 , M68K_INS_BFTST = 40 , M68K_INS_BKPT = 41 , M68K_INS_CALLM = 42 , M68K_INS_CAS = 43 , M68K_INS_CAS2 = 44 , M68K_INS_CHK = 45 , M68K_INS_CHK2 = 46 , M68K_INS_CLR = 47 , M68K_INS_CMP = 48 , M68K_INS_CMPA = 49 , M68K_INS_CMPI = 50 , M68K_INS_CMPM = 51 , M68K_INS_CMP2 = 52 , M68K_INS_CINVL = 53 , M68K_INS_CINVP = 54 , M68K_INS_CINVA = 55 , M68K_INS_CPUSHL = 56 , M68K_INS_CPUSHP = 57 , M68K_INS_CPUSHA = 58 , M68K_INS_DBT = 59 , M68K_INS_DBF = 60 , M68K_INS_DBHI = 61 , M68K_INS_DBLS = 62 , M68K_INS_DBCC = 63 , M68K_INS_DBCS = 64 , M68K_INS_DBNE = 65 , M68K_INS_DBEQ = 66 , M68K_INS_DBVC = 67 , M68K_INS_DBVS = 68 , M68K_INS_DBPL = 69 , M68K_INS_DBMI = 70 , M68K_INS_DBGE = 71 , M68K_INS_DBLT = 72 , M68K_INS_DBGT = 73 , M68K_INS_DBLE = 74 , M68K_INS_DBRA = 75 , M68K_INS_DIVS = 76 , M68K_INS_DIVSL = 77 , M68K_INS_DIVU = 78 , M68K_INS_DIVUL = 79 , M68K_INS_EOR = 80 , M68K_INS_EORI = 81 , M68K_INS_EXG = 82 , M68K_INS_EXT = 83 , M68K_INS_EXTB = 84 , M68K_INS_FABS = 85 , M68K_INS_FSABS = 86 , M68K_INS_FDABS = 87 , M68K_INS_FACOS = 88 , M68K_INS_FADD = 89 , M68K_INS_FSADD = 90 , M68K_INS_FDADD = 91 , M68K_INS_FASIN = 92 , M68K_INS_FATAN = 93 , M68K_INS_FATANH = 94 , M68K_INS_FBF = 95 , M68K_INS_FBEQ = 96 , M68K_INS_FBOGT = 97 , M68K_INS_FBOGE = 98 , M68K_INS_FBOLT = 99 , M68K_INS_FBOLE = 100 , M68K_INS_FBOGL = 101 , M68K_INS_FBOR = 102 , M68K_INS_FBUN = 103 , M68K_INS_FBUEQ = 104 , M68K_INS_FBUGT = 105 , M68K_INS_FBUGE = 106 , M68K_INS_FBULT = 107 , M68K_INS_FBULE = 108 , M68K_INS_FBNE = 109 , M68K_INS_FBT = 110 , M68K_INS_FBSF = 111 , M68K_INS_FBSEQ = 112 , M68K_INS_FBGT = 113 , M68K_INS_FBGE = 114 , M68K_INS_FBLT = 115 , M68K_INS_FBLE = 116 , M68K_INS_FBGL = 117 , M68K_INS_FBGLE = 118 , M68K_INS_FBNGLE = 119 , M68K_INS_FBNGL = 120 , M68K_INS_FBNLE = 121 , M68K_INS_FBNLT = 122 , M68K_INS_FBNGE = 123 , M68K_INS_FBNGT = 124 , M68K_INS_FBSNE = 125 , M68K_INS_FBST = 126 , M68K_INS_FCMP = 127 , M68K_INS_FCOS = 128 , M68K_INS_FCOSH = 129 , M68K_INS_FDBF = 130 , M68K_INS_FDBEQ = 131 , M68K_INS_FDBOGT = 132 , M68K_INS_FDBOGE = 133 , M68K_INS_FDBOLT = 134 , M68K_INS_FDBOLE = 135 , M68K_INS_FDBOGL = 136 , M68K_INS_FDBOR = 137 , M68K_INS_FDBUN = 138 , M68K_INS_FDBUEQ = 139 , M68K_INS_FDBUGT = 140 , M68K_INS_FDBUGE = 141 , M68K_INS_FDBULT = 142 , M68K_INS_FDBULE = 143 , M68K_INS_FDBNE = 144 , M68K_INS_FDBT = 145 , M68K_INS_FDBSF = 146 , M68K_INS_FDBSEQ = 147 , M68K_INS_FDBGT = 148 , M68K_INS_FDBGE = 149 , M68K_INS_FDBLT = 150 , M68K_INS_FDBLE = 151 , M68K_INS_FDBGL = 152 , M68K_INS_FDBGLE = 153 , M68K_INS_FDBNGLE = 154 , M68K_INS_FDBNGL = 155 , M68K_INS_FDBNLE = 156 , M68K_INS_FDBNLT = 157 , M68K_INS_FDBNGE = 158 , M68K_INS_FDBNGT = 159 , M68K_INS_FDBSNE = 160 , M68K_INS_FDBST = 161 , M68K_INS_FDIV = 162 , M68K_INS_FSDIV = 163 , M68K_INS_FDDIV = 164 , M68K_INS_FETOX = 165 , M68K_INS_FETOXM1 = 166 , M68K_INS_FGETEXP = 167 , M68K_INS_FGETMAN = 168 , M68K_INS_FINT = 169 , M68K_INS_FINTRZ = 170 , M68K_INS_FLOG10 = 171 , M68K_INS_FLOG2 = 172 , M68K_INS_FLOGN = 173 , M68K_INS_FLOGNP1 = 174 , M68K_INS_FMOD = 175 , M68K_INS_FMOVE = 176 , M68K_INS_FSMOVE = 177 , M68K_INS_FDMOVE = 178 , M68K_INS_FMOVECR = 179 , M68K_INS_FMOVEM = 180 , M68K_INS_FMUL = 181 , M68K_INS_FSMUL = 182 , M68K_INS_FDMUL = 183 , M68K_INS_FNEG = 184 , M68K_INS_FSNEG = 185 , M68K_INS_FDNEG = 186 , M68K_INS_FNOP = 187 , M68K_INS_FREM = 188 , M68K_INS_FRESTORE = 189 , M68K_INS_FSAVE = 190 , M68K_INS_FSCALE = 191 , M68K_INS_FSGLDIV = 192 , M68K_INS_FSGLMUL = 193 , M68K_INS_FSIN = 194 , M68K_INS_FSINCOS = 195 , M68K_INS_FSINH = 196 , M68K_INS_FSQRT = 197 , M68K_INS_FSSQRT = 198 , M68K_INS_FDSQRT = 199 , M68K_INS_FSF = 200 , M68K_INS_FSBEQ = 201 , M68K_INS_FSOGT = 202 , M68K_INS_FSOGE = 203 , M68K_INS_FSOLT = 204 , M68K_INS_FSOLE = 205 , M68K_INS_FSOGL = 206 , M68K_INS_FSOR = 207 , M68K_INS_FSUN = 208 , M68K_INS_FSUEQ = 209 , M68K_INS_FSUGT = 210 , M68K_INS_FSUGE = 211 , M68K_INS_FSULT = 212 , M68K_INS_FSULE = 213 , M68K_INS_FSNE = 214 , M68K_INS_FST = 215 , M68K_INS_FSSF = 216 , M68K_INS_FSSEQ = 217 , M68K_INS_FSGT = 218 , M68K_INS_FSGE = 219 , M68K_INS_FSLT = 220 , M68K_INS_FSLE = 221 , M68K_INS_FSGL = 222 , M68K_INS_FSGLE = 223 , M68K_INS_FSNGLE = 224 , M68K_INS_FSNGL = 225 , M68K_INS_FSNLE = 226 , M68K_INS_FSNLT = 227 , M68K_INS_FSNGE = 228 , M68K_INS_FSNGT = 229 , M68K_INS_FSSNE = 230 , M68K_INS_FSST = 231 , M68K_INS_FSUB = 232 , M68K_INS_FSSUB = 233 , M68K_INS_FDSUB = 234 , M68K_INS_FTAN = 235 , M68K_INS_FTANH = 236 , M68K_INS_FTENTOX = 237 , M68K_INS_FTRAPF = 238 , M68K_INS_FTRAPEQ = 239 , M68K_INS_FTRAPOGT = 240 , M68K_INS_FTRAPOGE = 241 , M68K_INS_FTRAPOLT = 242 , M68K_INS_FTRAPOLE = 243 , M68K_INS_FTRAPOGL = 244 , M68K_INS_FTRAPOR = 245 , M68K_INS_FTRAPUN = 246 , M68K_INS_FTRAPUEQ = 247 , M68K_INS_FTRAPUGT = 248 , M68K_INS_FTRAPUGE = 249 , M68K_INS_FTRAPULT = 250 , M68K_INS_FTRAPULE = 251 , M68K_INS_FTRAPNE = 252 , M68K_INS_FTRAPT = 253 , M68K_INS_FTRAPSF = 254 , M68K_INS_FTRAPSEQ = 255 , M68K_INS_FTRAPGT = 256 , M68K_INS_FTRAPGE = 257 , M68K_INS_FTRAPLT = 258 , M68K_INS_FTRAPLE = 259 , M68K_INS_FTRAPGL = 260 , M68K_INS_FTRAPGLE = 261 , M68K_INS_FTRAPNGLE = 262 , M68K_INS_FTRAPNGL = 263 , M68K_INS_FTRAPNLE = 264 , M68K_INS_FTRAPNLT = 265 , M68K_INS_FTRAPNGE = 266 , M68K_INS_FTRAPNGT = 267 , M68K_INS_FTRAPSNE = 268 , M68K_INS_FTRAPST = 269 , M68K_INS_FTST = 270 , M68K_INS_FTWOTOX = 271 , M68K_INS_HALT = 272 , M68K_INS_ILLEGAL = 273 , M68K_INS_JMP = 274 , M68K_INS_JSR = 275 , M68K_INS_LEA = 276 , M68K_INS_LINK = 277 , M68K_INS_LPSTOP = 278 , M68K_INS_LSL = 279 , M68K_INS_LSR = 280 , M68K_INS_MOVE = 281 , M68K_INS_MOVEA = 282 , M68K_INS_MOVEC = 283 , M68K_INS_MOVEM = 284 , M68K_INS_MOVEP = 285 , M68K_INS_MOVEQ = 286 , M68K_INS_MOVES = 287 , M68K_INS_MOVE16 = 288 , M68K_INS_MULS = 289 , M68K_INS_MULU = 290 , M68K_INS_NBCD = 291 , M68K_INS_NEG = 292 , M68K_INS_NEGX = 293 , M68K_INS_NOP = 294 , M68K_INS_NOT = 295 , M68K_INS_OR = 296 , M68K_INS_ORI = 297 , M68K_INS_PACK = 298 , M68K_INS_PEA = 299 , M68K_INS_PFLUSH = 300 , M68K_INS_PFLUSHA = 301 , M68K_INS_PFLUSHAN = 302 , M68K_INS_PFLUSHN = 303 , M68K_INS_PLOADR = 304 , M68K_INS_PLOADW = 305 , M68K_INS_PLPAR = 306 , M68K_INS_PLPAW = 307 , M68K_INS_PMOVE = 308 , M68K_INS_PMOVEFD = 309 , M68K_INS_PTESTR = 310 , M68K_INS_PTESTW = 311 , M68K_INS_PULSE = 312 , M68K_INS_REMS = 313 , M68K_INS_REMU = 314 , M68K_INS_RESET = 315 , M68K_INS_ROL = 316 , M68K_INS_ROR = 317 , M68K_INS_ROXL = 318 , M68K_INS_ROXR = 319 , M68K_INS_RTD = 320 , M68K_INS_RTE = 321 , M68K_INS_RTM = 322 , M68K_INS_RTR = 323 , M68K_INS_RTS = 324 , M68K_INS_SBCD = 325 , M68K_INS_ST = 326 , M68K_INS_SF = 327 , M68K_INS_SHI = 328 , M68K_INS_SLS = 329 , M68K_INS_SCC = 330 , M68K_INS_SHS = 331 , M68K_INS_SCS = 332 , M68K_INS_SLO = 333 , M68K_INS_SNE = 334 , M68K_INS_SEQ = 335 , M68K_INS_SVC = 336 , M68K_INS_SVS = 337 , M68K_INS_SPL = 338 , M68K_INS_SMI = 339 , M68K_INS_SGE = 340 , M68K_INS_SLT = 341 , M68K_INS_SGT = 342 , M68K_INS_SLE = 343 , M68K_INS_STOP = 344 , M68K_INS_SUB = 345 , M68K_INS_SUBA = 346 , M68K_INS_SUBI = 347 , M68K_INS_SUBQ = 348 , M68K_INS_SUBX = 349 , M68K_INS_SWAP = 350 , M68K_INS_TAS = 351 , M68K_INS_TRAP = 352 , M68K_INS_TRAPV = 353 , M68K_INS_TRAPT = 354 , M68K_INS_TRAPF = 355 , M68K_INS_TRAPHI = 356 , M68K_INS_TRAPLS = 357 , M68K_INS_TRAPCC = 358 , M68K_INS_TRAPHS = 359 , M68K_INS_TRAPCS = 360 , M68K_INS_TRAPLO = 361 , M68K_INS_TRAPNE = 362 , M68K_INS_TRAPEQ = 363 , M68K_INS_TRAPVC = 364 , M68K_INS_TRAPVS = 365 , M68K_INS_TRAPPL = 366 , M68K_INS_TRAPMI = 367 , M68K_INS_TRAPGE = 368 , M68K_INS_TRAPLT = 369 , M68K_INS_TRAPGT = 370 , M68K_INS_TRAPLE = 371 , M68K_INS_TST = 372 , M68K_INS_UNLK = 373 , M68K_INS_UNPK = 374 , M68K_INS_ENDING = 375 , } # [repr (u32)] # [doc = " Group of M68K instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_group_type { # [doc = "< CS_GRUP_INVALID"] M68K_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M68K_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] M68K_GRP_RET = 3 , # [doc = "< = CS_GRP_IRET"] M68K_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M68K_GRP_BRANCH_RELATIVE = 7 , M68K_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MIPS_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MIPS_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MIPS_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MIPS_OP_MEM = 3 , } impl mips_reg { pub const MIPS_REG_ZERO : mips_reg = mips_reg :: MIPS_REG_0 ; } impl mips_reg { pub const MIPS_REG_AT : mips_reg = mips_reg :: MIPS_REG_1 ; } impl mips_reg { pub const MIPS_REG_V0 : mips_reg = mips_reg :: MIPS_REG_2 ; } impl mips_reg { pub const MIPS_REG_V1 : mips_reg = mips_reg :: MIPS_REG_3 ; } impl mips_reg { pub const MIPS_REG_A0 : mips_reg = mips_reg :: MIPS_REG_4 ; } impl mips_reg { pub const MIPS_REG_A1 : mips_reg = mips_reg :: MIPS_REG_5 ; } impl mips_reg { pub const MIPS_REG_A2 : mips_reg = mips_reg :: MIPS_REG_6 ; } impl mips_reg { pub const MIPS_REG_A3 : mips_reg = mips_reg :: MIPS_REG_7 ; } impl mips_reg { pub const MIPS_REG_T0 : mips_reg = mips_reg :: MIPS_REG_8 ; } impl mips_reg { pub const MIPS_REG_T1 : mips_reg = mips_reg :: MIPS_REG_9 ; } impl mips_reg { pub const MIPS_REG_T2 : mips_reg = mips_reg :: MIPS_REG_10 ; } impl mips_reg { pub const MIPS_REG_T3 : mips_reg = mips_reg :: MIPS_REG_11 ; } impl mips_reg { pub const MIPS_REG_T4 : mips_reg = mips_reg :: MIPS_REG_12 ; } impl mips_reg { pub const MIPS_REG_T5 : mips_reg = mips_reg :: MIPS_REG_13 ; } impl mips_reg { pub const MIPS_REG_T6 : mips_reg = mips_reg :: MIPS_REG_14 ; } impl mips_reg { pub const MIPS_REG_T7 : mips_reg = mips_reg :: MIPS_REG_15 ; } impl mips_reg { pub const MIPS_REG_S0 : mips_reg = mips_reg :: MIPS_REG_16 ; } impl mips_reg { pub const MIPS_REG_S1 : mips_reg = mips_reg :: MIPS_REG_17 ; } impl mips_reg { pub const MIPS_REG_S2 : mips_reg = mips_reg :: MIPS_REG_18 ; } impl mips_reg { pub const MIPS_REG_S3 : mips_reg = mips_reg :: MIPS_REG_19 ; } impl mips_reg { pub const MIPS_REG_S4 : mips_reg = mips_reg :: MIPS_REG_20 ; } impl mips_reg { pub const MIPS_REG_S5 : mips_reg = mips_reg :: MIPS_REG_21 ; } impl mips_reg { pub const MIPS_REG_S6 : mips_reg = mips_reg :: MIPS_REG_22 ; } impl mips_reg { pub const MIPS_REG_S7 : mips_reg = mips_reg :: MIPS_REG_23 ; } impl mips_reg { pub const MIPS_REG_T8 : mips_reg = mips_reg :: MIPS_REG_24 ; } impl mips_reg { pub const MIPS_REG_T9 : mips_reg = mips_reg :: MIPS_REG_25 ; } impl mips_reg { pub const MIPS_REG_K0 : mips_reg = mips_reg :: MIPS_REG_26 ; } impl mips_reg { pub const MIPS_REG_K1 : mips_reg = mips_reg :: MIPS_REG_27 ; } impl mips_reg { pub const MIPS_REG_GP : mips_reg = mips_reg :: MIPS_REG_28 ; } impl mips_reg { pub const MIPS_REG_SP : mips_reg = mips_reg :: MIPS_REG_29 ; } impl mips_reg { pub const MIPS_REG_FP : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_S8 : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_RA : mips_reg = mips_reg :: MIPS_REG_31 ; } impl mips_reg { pub const MIPS_REG_HI0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_HI1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_HI2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_HI3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } impl mips_reg { pub const MIPS_REG_LO0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_LO1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_LO2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_LO3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } # [repr (u32)] # [doc = " MIPS registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_reg { MIPS_REG_INVALID = 0 , MIPS_REG_PC = 1 , MIPS_REG_0 = 2 , MIPS_REG_1 = 3 , MIPS_REG_2 = 4 , MIPS_REG_3 = 5 , MIPS_REG_4 = 6 , MIPS_REG_5 = 7 , MIPS_REG_6 = 8 , MIPS_REG_7 = 9 , MIPS_REG_8 = 10 , MIPS_REG_9 = 11 , MIPS_REG_10 = 12 , MIPS_REG_11 = 13 , MIPS_REG_12 = 14 , MIPS_REG_13 = 15 , MIPS_REG_14 = 16 , MIPS_REG_15 = 17 , MIPS_REG_16 = 18 , MIPS_REG_17 = 19 , MIPS_REG_18 = 20 , MIPS_REG_19 = 21 , MIPS_REG_20 = 22 , MIPS_REG_21 = 23 , MIPS_REG_22 = 24 , MIPS_REG_23 = 25 , MIPS_REG_24 = 26 , MIPS_REG_25 = 27 , MIPS_REG_26 = 28 , MIPS_REG_27 = 29 , MIPS_REG_28 = 30 , MIPS_REG_29 = 31 , MIPS_REG_30 = 32 , MIPS_REG_31 = 33 , MIPS_REG_DSPCCOND = 34 , MIPS_REG_DSPCARRY = 35 , MIPS_REG_DSPEFI = 36 , MIPS_REG_DSPOUTFLAG = 37 , MIPS_REG_DSPOUTFLAG16_19 = 38 , MIPS_REG_DSPOUTFLAG20 = 39 , MIPS_REG_DSPOUTFLAG21 = 40 , MIPS_REG_DSPOUTFLAG22 = 41 , MIPS_REG_DSPOUTFLAG23 = 42 , MIPS_REG_DSPPOS = 43 , MIPS_REG_DSPSCOUNT = 44 , MIPS_REG_AC0 = 45 , MIPS_REG_AC1 = 46 , MIPS_REG_AC2 = 47 , MIPS_REG_AC3 = 48 , MIPS_REG_CC0 = 49 , MIPS_REG_CC1 = 50 , MIPS_REG_CC2 = 51 , MIPS_REG_CC3 = 52 , MIPS_REG_CC4 = 53 , MIPS_REG_CC5 = 54 , MIPS_REG_CC6 = 55 , MIPS_REG_CC7 = 56 , MIPS_REG_F0 = 57 , MIPS_REG_F1 = 58 , MIPS_REG_F2 = 59 , MIPS_REG_F3 = 60 , MIPS_REG_F4 = 61 , MIPS_REG_F5 = 62 , MIPS_REG_F6 = 63 , MIPS_REG_F7 = 64 , MIPS_REG_F8 = 65 , MIPS_REG_F9 = 66 , MIPS_REG_F10 = 67 , MIPS_REG_F11 = 68 , MIPS_REG_F12 = 69 , MIPS_REG_F13 = 70 , MIPS_REG_F14 = 71 , MIPS_REG_F15 = 72 , MIPS_REG_F16 = 73 , MIPS_REG_F17 = 74 , MIPS_REG_F18 = 75 , MIPS_REG_F19 = 76 , MIPS_REG_F20 = 77 , MIPS_REG_F21 = 78 , MIPS_REG_F22 = 79 , MIPS_REG_F23 = 80 , MIPS_REG_F24 = 81 , MIPS_REG_F25 = 82 , MIPS_REG_F26 = 83 , MIPS_REG_F27 = 84 , MIPS_REG_F28 = 85 , MIPS_REG_F29 = 86 , MIPS_REG_F30 = 87 , MIPS_REG_F31 = 88 , MIPS_REG_FCC0 = 89 , MIPS_REG_FCC1 = 90 , MIPS_REG_FCC2 = 91 , MIPS_REG_FCC3 = 92 , MIPS_REG_FCC4 = 93 , MIPS_REG_FCC5 = 94 , MIPS_REG_FCC6 = 95 , MIPS_REG_FCC7 = 96 , MIPS_REG_W0 = 97 , MIPS_REG_W1 = 98 , MIPS_REG_W2 = 99 , MIPS_REG_W3 = 100 , MIPS_REG_W4 = 101 , MIPS_REG_W5 = 102 , MIPS_REG_W6 = 103 , MIPS_REG_W7 = 104 , MIPS_REG_W8 = 105 , MIPS_REG_W9 = 106 , MIPS_REG_W10 = 107 , MIPS_REG_W11 = 108 , MIPS_REG_W12 = 109 , MIPS_REG_W13 = 110 , MIPS_REG_W14 = 111 , MIPS_REG_W15 = 112 , MIPS_REG_W16 = 113 , MIPS_REG_W17 = 114 , MIPS_REG_W18 = 115 , MIPS_REG_W19 = 116 , MIPS_REG_W20 = 117 , MIPS_REG_W21 = 118 , MIPS_REG_W22 = 119 , MIPS_REG_W23 = 120 , MIPS_REG_W24 = 121 , MIPS_REG_W25 = 122 , MIPS_REG_W26 = 123 , MIPS_REG_W27 = 124 , MIPS_REG_W28 = 125 , MIPS_REG_W29 = 126 , MIPS_REG_W30 = 127 , MIPS_REG_W31 = 128 , MIPS_REG_HI = 129 , MIPS_REG_LO = 130 , MIPS_REG_P0 = 131 , MIPS_REG_P1 = 132 , MIPS_REG_P2 = 133 , MIPS_REG_MPL0 = 134 , MIPS_REG_MPL1 = 135 , MIPS_REG_MPL2 = 136 , MIPS_REG_ENDING = 137 , } # [doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct mips_op_mem { # [doc = "< base register"] pub base : mips_reg , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of mips_op_mem"] [:: std :: mem :: size_of :: < mips_op_mem > () - 16usize] ; ["Alignment of mips_op_mem"] [:: std :: mem :: align_of :: < mips_op_mem > () - 8usize] ; ["Offset of field: mips_op_mem::base"] [:: std :: mem :: offset_of ! (mips_op_mem , base) - 0usize] ; ["Offset of field: mips_op_mem::disp"] [:: std :: mem :: offset_of ! (mips_op_mem , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips_op { # [doc = "< operand type"] pub type_ : mips_op_type , pub __bindgen_anon_1 : cs_mips_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mips_op__bindgen_ty_1 { # [doc = "< register id for REG operand"] pub reg : mips_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : mips_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mips_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mips_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op"] [:: std :: mem :: size_of :: < cs_mips_op > () - 24usize] ; ["Alignment of cs_mips_op"] [:: std :: mem :: align_of :: < cs_mips_op > () - 8usize] ; ["Offset of field: cs_mips_op::type_"] [:: std :: mem :: offset_of ! (cs_mips_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mips_op ; 10usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips"] [:: std :: mem :: size_of :: < cs_mips > () - 248usize] ; ["Alignment of cs_mips"] [:: std :: mem :: align_of :: < cs_mips > () - 8usize] ; ["Offset of field: cs_mips::op_count"] [:: std :: mem :: offset_of ! (cs_mips , op_count) - 0usize] ; ["Offset of field: cs_mips::operands"] [:: std :: mem :: offset_of ! (cs_mips , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mips { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " MIPS instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn { MIPS_INS_INVALID = 0 , MIPS_INS_ABSQ_S = 1 , MIPS_INS_ADD = 2 , MIPS_INS_ADDIUPC = 3 , MIPS_INS_ADDIUR1SP = 4 , MIPS_INS_ADDIUR2 = 5 , MIPS_INS_ADDIUS5 = 6 , MIPS_INS_ADDIUSP = 7 , MIPS_INS_ADDQH = 8 , MIPS_INS_ADDQH_R = 9 , MIPS_INS_ADDQ = 10 , MIPS_INS_ADDQ_S = 11 , MIPS_INS_ADDSC = 12 , MIPS_INS_ADDS_A = 13 , MIPS_INS_ADDS_S = 14 , MIPS_INS_ADDS_U = 15 , MIPS_INS_ADDU16 = 16 , MIPS_INS_ADDUH = 17 , MIPS_INS_ADDUH_R = 18 , MIPS_INS_ADDU = 19 , MIPS_INS_ADDU_S = 20 , MIPS_INS_ADDVI = 21 , MIPS_INS_ADDV = 22 , MIPS_INS_ADDWC = 23 , MIPS_INS_ADD_A = 24 , MIPS_INS_ADDI = 25 , MIPS_INS_ADDIU = 26 , MIPS_INS_ALIGN = 27 , MIPS_INS_ALUIPC = 28 , MIPS_INS_AND = 29 , MIPS_INS_AND16 = 30 , MIPS_INS_ANDI16 = 31 , MIPS_INS_ANDI = 32 , MIPS_INS_APPEND = 33 , MIPS_INS_ASUB_S = 34 , MIPS_INS_ASUB_U = 35 , MIPS_INS_AUI = 36 , MIPS_INS_AUIPC = 37 , MIPS_INS_AVER_S = 38 , MIPS_INS_AVER_U = 39 , MIPS_INS_AVE_S = 40 , MIPS_INS_AVE_U = 41 , MIPS_INS_B16 = 42 , MIPS_INS_BADDU = 43 , MIPS_INS_BAL = 44 , MIPS_INS_BALC = 45 , MIPS_INS_BALIGN = 46 , MIPS_INS_BBIT0 = 47 , MIPS_INS_BBIT032 = 48 , MIPS_INS_BBIT1 = 49 , MIPS_INS_BBIT132 = 50 , MIPS_INS_BC = 51 , MIPS_INS_BC0F = 52 , MIPS_INS_BC0FL = 53 , MIPS_INS_BC0T = 54 , MIPS_INS_BC0TL = 55 , MIPS_INS_BC1EQZ = 56 , MIPS_INS_BC1F = 57 , MIPS_INS_BC1FL = 58 , MIPS_INS_BC1NEZ = 59 , MIPS_INS_BC1T = 60 , MIPS_INS_BC1TL = 61 , MIPS_INS_BC2EQZ = 62 , MIPS_INS_BC2F = 63 , MIPS_INS_BC2FL = 64 , MIPS_INS_BC2NEZ = 65 , MIPS_INS_BC2T = 66 , MIPS_INS_BC2TL = 67 , MIPS_INS_BC3F = 68 , MIPS_INS_BC3FL = 69 , MIPS_INS_BC3T = 70 , MIPS_INS_BC3TL = 71 , MIPS_INS_BCLRI = 72 , MIPS_INS_BCLR = 73 , MIPS_INS_BEQ = 74 , MIPS_INS_BEQC = 75 , MIPS_INS_BEQL = 76 , MIPS_INS_BEQZ16 = 77 , MIPS_INS_BEQZALC = 78 , MIPS_INS_BEQZC = 79 , MIPS_INS_BGEC = 80 , MIPS_INS_BGEUC = 81 , MIPS_INS_BGEZ = 82 , MIPS_INS_BGEZAL = 83 , MIPS_INS_BGEZALC = 84 , MIPS_INS_BGEZALL = 85 , MIPS_INS_BGEZALS = 86 , MIPS_INS_BGEZC = 87 , MIPS_INS_BGEZL = 88 , MIPS_INS_BGTZ = 89 , MIPS_INS_BGTZALC = 90 , MIPS_INS_BGTZC = 91 , MIPS_INS_BGTZL = 92 , MIPS_INS_BINSLI = 93 , MIPS_INS_BINSL = 94 , MIPS_INS_BINSRI = 95 , MIPS_INS_BINSR = 96 , MIPS_INS_BITREV = 97 , MIPS_INS_BITSWAP = 98 , MIPS_INS_BLEZ = 99 , MIPS_INS_BLEZALC = 100 , MIPS_INS_BLEZC = 101 , MIPS_INS_BLEZL = 102 , MIPS_INS_BLTC = 103 , MIPS_INS_BLTUC = 104 , MIPS_INS_BLTZ = 105 , MIPS_INS_BLTZAL = 106 , MIPS_INS_BLTZALC = 107 , MIPS_INS_BLTZALL = 108 , MIPS_INS_BLTZALS = 109 , MIPS_INS_BLTZC = 110 , MIPS_INS_BLTZL = 111 , MIPS_INS_BMNZI = 112 , MIPS_INS_BMNZ = 113 , MIPS_INS_BMZI = 114 , MIPS_INS_BMZ = 115 , MIPS_INS_BNE = 116 , MIPS_INS_BNEC = 117 , MIPS_INS_BNEGI = 118 , MIPS_INS_BNEG = 119 , MIPS_INS_BNEL = 120 , MIPS_INS_BNEZ16 = 121 , MIPS_INS_BNEZALC = 122 , MIPS_INS_BNEZC = 123 , MIPS_INS_BNVC = 124 , MIPS_INS_BNZ = 125 , MIPS_INS_BOVC = 126 , MIPS_INS_BPOSGE32 = 127 , MIPS_INS_BREAK = 128 , MIPS_INS_BREAK16 = 129 , MIPS_INS_BSELI = 130 , MIPS_INS_BSEL = 131 , MIPS_INS_BSETI = 132 , MIPS_INS_BSET = 133 , MIPS_INS_BZ = 134 , MIPS_INS_BEQZ = 135 , MIPS_INS_B = 136 , MIPS_INS_BNEZ = 137 , MIPS_INS_BTEQZ = 138 , MIPS_INS_BTNEZ = 139 , MIPS_INS_CACHE = 140 , MIPS_INS_CEIL = 141 , MIPS_INS_CEQI = 142 , MIPS_INS_CEQ = 143 , MIPS_INS_CFC1 = 144 , MIPS_INS_CFCMSA = 145 , MIPS_INS_CINS = 146 , MIPS_INS_CINS32 = 147 , MIPS_INS_CLASS = 148 , MIPS_INS_CLEI_S = 149 , MIPS_INS_CLEI_U = 150 , MIPS_INS_CLE_S = 151 , MIPS_INS_CLE_U = 152 , MIPS_INS_CLO = 153 , MIPS_INS_CLTI_S = 154 , MIPS_INS_CLTI_U = 155 , MIPS_INS_CLT_S = 156 , MIPS_INS_CLT_U = 157 , MIPS_INS_CLZ = 158 , MIPS_INS_CMPGDU = 159 , MIPS_INS_CMPGU = 160 , MIPS_INS_CMPU = 161 , MIPS_INS_CMP = 162 , MIPS_INS_COPY_S = 163 , MIPS_INS_COPY_U = 164 , MIPS_INS_CTC1 = 165 , MIPS_INS_CTCMSA = 166 , MIPS_INS_CVT = 167 , MIPS_INS_C = 168 , MIPS_INS_CMPI = 169 , MIPS_INS_DADD = 170 , MIPS_INS_DADDI = 171 , MIPS_INS_DADDIU = 172 , MIPS_INS_DADDU = 173 , MIPS_INS_DAHI = 174 , MIPS_INS_DALIGN = 175 , MIPS_INS_DATI = 176 , MIPS_INS_DAUI = 177 , MIPS_INS_DBITSWAP = 178 , MIPS_INS_DCLO = 179 , MIPS_INS_DCLZ = 180 , MIPS_INS_DDIV = 181 , MIPS_INS_DDIVU = 182 , MIPS_INS_DERET = 183 , MIPS_INS_DEXT = 184 , MIPS_INS_DEXTM = 185 , MIPS_INS_DEXTU = 186 , MIPS_INS_DI = 187 , MIPS_INS_DINS = 188 , MIPS_INS_DINSM = 189 , MIPS_INS_DINSU = 190 , MIPS_INS_DIV = 191 , MIPS_INS_DIVU = 192 , MIPS_INS_DIV_S = 193 , MIPS_INS_DIV_U = 194 , MIPS_INS_DLSA = 195 , MIPS_INS_DMFC0 = 196 , MIPS_INS_DMFC1 = 197 , MIPS_INS_DMFC2 = 198 , MIPS_INS_DMOD = 199 , MIPS_INS_DMODU = 200 , MIPS_INS_DMTC0 = 201 , MIPS_INS_DMTC1 = 202 , MIPS_INS_DMTC2 = 203 , MIPS_INS_DMUH = 204 , MIPS_INS_DMUHU = 205 , MIPS_INS_DMUL = 206 , MIPS_INS_DMULT = 207 , MIPS_INS_DMULTU = 208 , MIPS_INS_DMULU = 209 , MIPS_INS_DOTP_S = 210 , MIPS_INS_DOTP_U = 211 , MIPS_INS_DPADD_S = 212 , MIPS_INS_DPADD_U = 213 , MIPS_INS_DPAQX_SA = 214 , MIPS_INS_DPAQX_S = 215 , MIPS_INS_DPAQ_SA = 216 , MIPS_INS_DPAQ_S = 217 , MIPS_INS_DPAU = 218 , MIPS_INS_DPAX = 219 , MIPS_INS_DPA = 220 , MIPS_INS_DPOP = 221 , MIPS_INS_DPSQX_SA = 222 , MIPS_INS_DPSQX_S = 223 , MIPS_INS_DPSQ_SA = 224 , MIPS_INS_DPSQ_S = 225 , MIPS_INS_DPSUB_S = 226 , MIPS_INS_DPSUB_U = 227 , MIPS_INS_DPSU = 228 , MIPS_INS_DPSX = 229 , MIPS_INS_DPS = 230 , MIPS_INS_DROTR = 231 , MIPS_INS_DROTR32 = 232 , MIPS_INS_DROTRV = 233 , MIPS_INS_DSBH = 234 , MIPS_INS_DSHD = 235 , MIPS_INS_DSLL = 236 , MIPS_INS_DSLL32 = 237 , MIPS_INS_DSLLV = 238 , MIPS_INS_DSRA = 239 , MIPS_INS_DSRA32 = 240 , MIPS_INS_DSRAV = 241 , MIPS_INS_DSRL = 242 , MIPS_INS_DSRL32 = 243 , MIPS_INS_DSRLV = 244 , MIPS_INS_DSUB = 245 , MIPS_INS_DSUBU = 246 , MIPS_INS_EHB = 247 , MIPS_INS_EI = 248 , MIPS_INS_ERET = 249 , MIPS_INS_EXT = 250 , MIPS_INS_EXTP = 251 , MIPS_INS_EXTPDP = 252 , MIPS_INS_EXTPDPV = 253 , MIPS_INS_EXTPV = 254 , MIPS_INS_EXTRV_RS = 255 , MIPS_INS_EXTRV_R = 256 , MIPS_INS_EXTRV_S = 257 , MIPS_INS_EXTRV = 258 , MIPS_INS_EXTR_RS = 259 , MIPS_INS_EXTR_R = 260 , MIPS_INS_EXTR_S = 261 , MIPS_INS_EXTR = 262 , MIPS_INS_EXTS = 263 , MIPS_INS_EXTS32 = 264 , MIPS_INS_ABS = 265 , MIPS_INS_FADD = 266 , MIPS_INS_FCAF = 267 , MIPS_INS_FCEQ = 268 , MIPS_INS_FCLASS = 269 , MIPS_INS_FCLE = 270 , MIPS_INS_FCLT = 271 , MIPS_INS_FCNE = 272 , MIPS_INS_FCOR = 273 , MIPS_INS_FCUEQ = 274 , MIPS_INS_FCULE = 275 , MIPS_INS_FCULT = 276 , MIPS_INS_FCUNE = 277 , MIPS_INS_FCUN = 278 , MIPS_INS_FDIV = 279 , MIPS_INS_FEXDO = 280 , MIPS_INS_FEXP2 = 281 , MIPS_INS_FEXUPL = 282 , MIPS_INS_FEXUPR = 283 , MIPS_INS_FFINT_S = 284 , MIPS_INS_FFINT_U = 285 , MIPS_INS_FFQL = 286 , MIPS_INS_FFQR = 287 , MIPS_INS_FILL = 288 , MIPS_INS_FLOG2 = 289 , MIPS_INS_FLOOR = 290 , MIPS_INS_FMADD = 291 , MIPS_INS_FMAX_A = 292 , MIPS_INS_FMAX = 293 , MIPS_INS_FMIN_A = 294 , MIPS_INS_FMIN = 295 , MIPS_INS_MOV = 296 , MIPS_INS_FMSUB = 297 , MIPS_INS_FMUL = 298 , MIPS_INS_MUL = 299 , MIPS_INS_NEG = 300 , MIPS_INS_FRCP = 301 , MIPS_INS_FRINT = 302 , MIPS_INS_FRSQRT = 303 , MIPS_INS_FSAF = 304 , MIPS_INS_FSEQ = 305 , MIPS_INS_FSLE = 306 , MIPS_INS_FSLT = 307 , MIPS_INS_FSNE = 308 , MIPS_INS_FSOR = 309 , MIPS_INS_FSQRT = 310 , MIPS_INS_SQRT = 311 , MIPS_INS_FSUB = 312 , MIPS_INS_SUB = 313 , MIPS_INS_FSUEQ = 314 , MIPS_INS_FSULE = 315 , MIPS_INS_FSULT = 316 , MIPS_INS_FSUNE = 317 , MIPS_INS_FSUN = 318 , MIPS_INS_FTINT_S = 319 , MIPS_INS_FTINT_U = 320 , MIPS_INS_FTQ = 321 , MIPS_INS_FTRUNC_S = 322 , MIPS_INS_FTRUNC_U = 323 , MIPS_INS_HADD_S = 324 , MIPS_INS_HADD_U = 325 , MIPS_INS_HSUB_S = 326 , MIPS_INS_HSUB_U = 327 , MIPS_INS_ILVEV = 328 , MIPS_INS_ILVL = 329 , MIPS_INS_ILVOD = 330 , MIPS_INS_ILVR = 331 , MIPS_INS_INS = 332 , MIPS_INS_INSERT = 333 , MIPS_INS_INSV = 334 , MIPS_INS_INSVE = 335 , MIPS_INS_J = 336 , MIPS_INS_JAL = 337 , MIPS_INS_JALR = 338 , MIPS_INS_JALRS16 = 339 , MIPS_INS_JALRS = 340 , MIPS_INS_JALS = 341 , MIPS_INS_JALX = 342 , MIPS_INS_JIALC = 343 , MIPS_INS_JIC = 344 , MIPS_INS_JR = 345 , MIPS_INS_JR16 = 346 , MIPS_INS_JRADDIUSP = 347 , MIPS_INS_JRC = 348 , MIPS_INS_JALRC = 349 , MIPS_INS_LB = 350 , MIPS_INS_LBU16 = 351 , MIPS_INS_LBUX = 352 , MIPS_INS_LBU = 353 , MIPS_INS_LD = 354 , MIPS_INS_LDC1 = 355 , MIPS_INS_LDC2 = 356 , MIPS_INS_LDC3 = 357 , MIPS_INS_LDI = 358 , MIPS_INS_LDL = 359 , MIPS_INS_LDPC = 360 , MIPS_INS_LDR = 361 , MIPS_INS_LDXC1 = 362 , MIPS_INS_LH = 363 , MIPS_INS_LHU16 = 364 , MIPS_INS_LHX = 365 , MIPS_INS_LHU = 366 , MIPS_INS_LI16 = 367 , MIPS_INS_LL = 368 , MIPS_INS_LLD = 369 , MIPS_INS_LSA = 370 , MIPS_INS_LUXC1 = 371 , MIPS_INS_LUI = 372 , MIPS_INS_LW = 373 , MIPS_INS_LW16 = 374 , MIPS_INS_LWC1 = 375 , MIPS_INS_LWC2 = 376 , MIPS_INS_LWC3 = 377 , MIPS_INS_LWL = 378 , MIPS_INS_LWM16 = 379 , MIPS_INS_LWM32 = 380 , MIPS_INS_LWPC = 381 , MIPS_INS_LWP = 382 , MIPS_INS_LWR = 383 , MIPS_INS_LWUPC = 384 , MIPS_INS_LWU = 385 , MIPS_INS_LWX = 386 , MIPS_INS_LWXC1 = 387 , MIPS_INS_LWXS = 388 , MIPS_INS_LI = 389 , MIPS_INS_MADD = 390 , MIPS_INS_MADDF = 391 , MIPS_INS_MADDR_Q = 392 , MIPS_INS_MADDU = 393 , MIPS_INS_MADDV = 394 , MIPS_INS_MADD_Q = 395 , MIPS_INS_MAQ_SA = 396 , MIPS_INS_MAQ_S = 397 , MIPS_INS_MAXA = 398 , MIPS_INS_MAXI_S = 399 , MIPS_INS_MAXI_U = 400 , MIPS_INS_MAX_A = 401 , MIPS_INS_MAX = 402 , MIPS_INS_MAX_S = 403 , MIPS_INS_MAX_U = 404 , MIPS_INS_MFC0 = 405 , MIPS_INS_MFC1 = 406 , MIPS_INS_MFC2 = 407 , MIPS_INS_MFHC1 = 408 , MIPS_INS_MFHI = 409 , MIPS_INS_MFLO = 410 , MIPS_INS_MINA = 411 , MIPS_INS_MINI_S = 412 , MIPS_INS_MINI_U = 413 , MIPS_INS_MIN_A = 414 , MIPS_INS_MIN = 415 , MIPS_INS_MIN_S = 416 , MIPS_INS_MIN_U = 417 , MIPS_INS_MOD = 418 , MIPS_INS_MODSUB = 419 , MIPS_INS_MODU = 420 , MIPS_INS_MOD_S = 421 , MIPS_INS_MOD_U = 422 , MIPS_INS_MOVE = 423 , MIPS_INS_MOVEP = 424 , MIPS_INS_MOVF = 425 , MIPS_INS_MOVN = 426 , MIPS_INS_MOVT = 427 , MIPS_INS_MOVZ = 428 , MIPS_INS_MSUB = 429 , MIPS_INS_MSUBF = 430 , MIPS_INS_MSUBR_Q = 431 , MIPS_INS_MSUBU = 432 , MIPS_INS_MSUBV = 433 , MIPS_INS_MSUB_Q = 434 , MIPS_INS_MTC0 = 435 , MIPS_INS_MTC1 = 436 , MIPS_INS_MTC2 = 437 , MIPS_INS_MTHC1 = 438 , MIPS_INS_MTHI = 439 , MIPS_INS_MTHLIP = 440 , MIPS_INS_MTLO = 441 , MIPS_INS_MTM0 = 442 , MIPS_INS_MTM1 = 443 , MIPS_INS_MTM2 = 444 , MIPS_INS_MTP0 = 445 , MIPS_INS_MTP1 = 446 , MIPS_INS_MTP2 = 447 , MIPS_INS_MUH = 448 , MIPS_INS_MUHU = 449 , MIPS_INS_MULEQ_S = 450 , MIPS_INS_MULEU_S = 451 , MIPS_INS_MULQ_RS = 452 , MIPS_INS_MULQ_S = 453 , MIPS_INS_MULR_Q = 454 , MIPS_INS_MULSAQ_S = 455 , MIPS_INS_MULSA = 456 , MIPS_INS_MULT = 457 , MIPS_INS_MULTU = 458 , MIPS_INS_MULU = 459 , MIPS_INS_MULV = 460 , MIPS_INS_MUL_Q = 461 , MIPS_INS_MUL_S = 462 , MIPS_INS_NLOC = 463 , MIPS_INS_NLZC = 464 , MIPS_INS_NMADD = 465 , MIPS_INS_NMSUB = 466 , MIPS_INS_NOR = 467 , MIPS_INS_NORI = 468 , MIPS_INS_NOT16 = 469 , MIPS_INS_NOT = 470 , MIPS_INS_OR = 471 , MIPS_INS_OR16 = 472 , MIPS_INS_ORI = 473 , MIPS_INS_PACKRL = 474 , MIPS_INS_PAUSE = 475 , MIPS_INS_PCKEV = 476 , MIPS_INS_PCKOD = 477 , MIPS_INS_PCNT = 478 , MIPS_INS_PICK = 479 , MIPS_INS_POP = 480 , MIPS_INS_PRECEQU = 481 , MIPS_INS_PRECEQ = 482 , MIPS_INS_PRECEU = 483 , MIPS_INS_PRECRQU_S = 484 , MIPS_INS_PRECRQ = 485 , MIPS_INS_PRECRQ_RS = 486 , MIPS_INS_PRECR = 487 , MIPS_INS_PRECR_SRA = 488 , MIPS_INS_PRECR_SRA_R = 489 , MIPS_INS_PREF = 490 , MIPS_INS_PREPEND = 491 , MIPS_INS_RADDU = 492 , MIPS_INS_RDDSP = 493 , MIPS_INS_RDHWR = 494 , MIPS_INS_REPLV = 495 , MIPS_INS_REPL = 496 , MIPS_INS_RINT = 497 , MIPS_INS_ROTR = 498 , MIPS_INS_ROTRV = 499 , MIPS_INS_ROUND = 500 , MIPS_INS_SAT_S = 501 , MIPS_INS_SAT_U = 502 , MIPS_INS_SB = 503 , MIPS_INS_SB16 = 504 , MIPS_INS_SC = 505 , MIPS_INS_SCD = 506 , MIPS_INS_SD = 507 , MIPS_INS_SDBBP = 508 , MIPS_INS_SDBBP16 = 509 , MIPS_INS_SDC1 = 510 , MIPS_INS_SDC2 = 511 , MIPS_INS_SDC3 = 512 , MIPS_INS_SDL = 513 , MIPS_INS_SDR = 514 , MIPS_INS_SDXC1 = 515 , MIPS_INS_SEB = 516 , MIPS_INS_SEH = 517 , MIPS_INS_SELEQZ = 518 , MIPS_INS_SELNEZ = 519 , MIPS_INS_SEL = 520 , MIPS_INS_SEQ = 521 , MIPS_INS_SEQI = 522 , MIPS_INS_SH = 523 , MIPS_INS_SH16 = 524 , MIPS_INS_SHF = 525 , MIPS_INS_SHILO = 526 , MIPS_INS_SHILOV = 527 , MIPS_INS_SHLLV = 528 , MIPS_INS_SHLLV_S = 529 , MIPS_INS_SHLL = 530 , MIPS_INS_SHLL_S = 531 , MIPS_INS_SHRAV = 532 , MIPS_INS_SHRAV_R = 533 , MIPS_INS_SHRA = 534 , MIPS_INS_SHRA_R = 535 , MIPS_INS_SHRLV = 536 , MIPS_INS_SHRL = 537 , MIPS_INS_SLDI = 538 , MIPS_INS_SLD = 539 , MIPS_INS_SLL = 540 , MIPS_INS_SLL16 = 541 , MIPS_INS_SLLI = 542 , MIPS_INS_SLLV = 543 , MIPS_INS_SLT = 544 , MIPS_INS_SLTI = 545 , MIPS_INS_SLTIU = 546 , MIPS_INS_SLTU = 547 , MIPS_INS_SNE = 548 , MIPS_INS_SNEI = 549 , MIPS_INS_SPLATI = 550 , MIPS_INS_SPLAT = 551 , MIPS_INS_SRA = 552 , MIPS_INS_SRAI = 553 , MIPS_INS_SRARI = 554 , MIPS_INS_SRAR = 555 , MIPS_INS_SRAV = 556 , MIPS_INS_SRL = 557 , MIPS_INS_SRL16 = 558 , MIPS_INS_SRLI = 559 , MIPS_INS_SRLRI = 560 , MIPS_INS_SRLR = 561 , MIPS_INS_SRLV = 562 , MIPS_INS_SSNOP = 563 , MIPS_INS_ST = 564 , MIPS_INS_SUBQH = 565 , MIPS_INS_SUBQH_R = 566 , MIPS_INS_SUBQ = 567 , MIPS_INS_SUBQ_S = 568 , MIPS_INS_SUBSUS_U = 569 , MIPS_INS_SUBSUU_S = 570 , MIPS_INS_SUBS_S = 571 , MIPS_INS_SUBS_U = 572 , MIPS_INS_SUBU16 = 573 , MIPS_INS_SUBUH = 574 , MIPS_INS_SUBUH_R = 575 , MIPS_INS_SUBU = 576 , MIPS_INS_SUBU_S = 577 , MIPS_INS_SUBVI = 578 , MIPS_INS_SUBV = 579 , MIPS_INS_SUXC1 = 580 , MIPS_INS_SW = 581 , MIPS_INS_SW16 = 582 , MIPS_INS_SWC1 = 583 , MIPS_INS_SWC2 = 584 , MIPS_INS_SWC3 = 585 , MIPS_INS_SWL = 586 , MIPS_INS_SWM16 = 587 , MIPS_INS_SWM32 = 588 , MIPS_INS_SWP = 589 , MIPS_INS_SWR = 590 , MIPS_INS_SWXC1 = 591 , MIPS_INS_SYNC = 592 , MIPS_INS_SYNCI = 593 , MIPS_INS_SYSCALL = 594 , MIPS_INS_TEQ = 595 , MIPS_INS_TEQI = 596 , MIPS_INS_TGE = 597 , MIPS_INS_TGEI = 598 , MIPS_INS_TGEIU = 599 , MIPS_INS_TGEU = 600 , MIPS_INS_TLBP = 601 , MIPS_INS_TLBR = 602 , MIPS_INS_TLBWI = 603 , MIPS_INS_TLBWR = 604 , MIPS_INS_TLT = 605 , MIPS_INS_TLTI = 606 , MIPS_INS_TLTIU = 607 , MIPS_INS_TLTU = 608 , MIPS_INS_TNE = 609 , MIPS_INS_TNEI = 610 , MIPS_INS_TRUNC = 611 , MIPS_INS_V3MULU = 612 , MIPS_INS_VMM0 = 613 , MIPS_INS_VMULU = 614 , MIPS_INS_VSHF = 615 , MIPS_INS_WAIT = 616 , MIPS_INS_WRDSP = 617 , MIPS_INS_WSBH = 618 , MIPS_INS_XOR = 619 , MIPS_INS_XOR16 = 620 , MIPS_INS_XORI = 621 , MIPS_INS_NOP = 622 , MIPS_INS_NEGU = 623 , MIPS_INS_JALR_HB = 624 , MIPS_INS_JR_HB = 625 , MIPS_INS_ENDING = 626 , } # [repr (u32)] # [doc = " Group of MIPS instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn_group { # [doc = "< = CS_GRP_INVALID"] MIPS_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MIPS_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] MIPS_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MIPS_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MIPS_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MIPS_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] MIPS_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MIPS_GRP_BRANCH_RELATIVE = 7 , MIPS_GRP_BITCOUNT = 128 , MIPS_GRP_DSP = 129 , MIPS_GRP_DSPR2 = 130 , MIPS_GRP_FPIDX = 131 , MIPS_GRP_MSA = 132 , MIPS_GRP_MIPS32R2 = 133 , MIPS_GRP_MIPS64 = 134 , MIPS_GRP_MIPS64R2 = 135 , MIPS_GRP_SEINREG = 136 , MIPS_GRP_STDENC = 137 , MIPS_GRP_SWAP = 138 , MIPS_GRP_MICROMIPS = 139 , MIPS_GRP_MIPS16MODE = 140 , MIPS_GRP_FP64BIT = 141 , MIPS_GRP_NONANSFPMATH = 142 , MIPS_GRP_NOTFP64BIT = 143 , MIPS_GRP_NOTINMICROMIPS = 144 , MIPS_GRP_NOTNACL = 145 , MIPS_GRP_NOTMIPS32R6 = 146 , MIPS_GRP_NOTMIPS64R6 = 147 , MIPS_GRP_CNMIPS = 148 , MIPS_GRP_MIPS32 = 149 , MIPS_GRP_MIPS32R6 = 150 , MIPS_GRP_MIPS64R6 = 151 , MIPS_GRP_MIPS2 = 152 , MIPS_GRP_MIPS3 = 153 , MIPS_GRP_MIPS3_32 = 154 , MIPS_GRP_MIPS3_32R2 = 155 , MIPS_GRP_MIPS4_32 = 156 , MIPS_GRP_MIPS4_32R2 = 157 , MIPS_GRP_MIPS5_32R2 = 158 , MIPS_GRP_GP32BIT = 159 , MIPS_GRP_GP64BIT = 160 , MIPS_GRP_ENDING = 161 , } # [repr (u32)] # [doc = " PPC branch codes for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bc { PPC_BC_INVALID = 0 , PPC_BC_LT = 12 , PPC_BC_LE = 36 , PPC_BC_EQ = 76 , PPC_BC_GE = 4 , PPC_BC_GT = 44 , PPC_BC_NE = 68 , PPC_BC_UN = 108 , PPC_BC_NU = 100 , # [doc = "< summary overflow"] PPC_BC_SO = 140 , # [doc = "< not summary overflow"] PPC_BC_NS = 132 , } # [repr (u32)] # [doc = " PPC branch hint for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bh { # [doc = "< no hint"] PPC_BH_INVALID = 0 , # [doc = "< PLUS hint"] PPC_BH_PLUS = 1 , # [doc = "< MINUS hint"] PPC_BH_MINUS = 2 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] PPC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] PPC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] PPC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] PPC_OP_MEM = 3 , # [doc = "< Condition Register field"] PPC_OP_CRX = 64 , } # [repr (u32)] # [doc = " PPC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_reg { PPC_REG_INVALID = 0 , PPC_REG_CARRY = 2 , PPC_REG_CTR = 3 , PPC_REG_LR = 5 , PPC_REG_RM = 6 , PPC_REG_VRSAVE = 8 , PPC_REG_XER = 9 , PPC_REG_ZERO = 10 , PPC_REG_CR0 = 12 , PPC_REG_CR1 = 13 , PPC_REG_CR2 = 14 , PPC_REG_CR3 = 15 , PPC_REG_CR4 = 16 , PPC_REG_CR5 = 17 , PPC_REG_CR6 = 18 , PPC_REG_CR7 = 19 , PPC_REG_CTR8 = 20 , PPC_REG_F0 = 21 , PPC_REG_F1 = 22 , PPC_REG_F2 = 23 , PPC_REG_F3 = 24 , PPC_REG_F4 = 25 , PPC_REG_F5 = 26 , PPC_REG_F6 = 27 , PPC_REG_F7 = 28 , PPC_REG_F8 = 29 , PPC_REG_F9 = 30 , PPC_REG_F10 = 31 , PPC_REG_F11 = 32 , PPC_REG_F12 = 33 , PPC_REG_F13 = 34 , PPC_REG_F14 = 35 , PPC_REG_F15 = 36 , PPC_REG_F16 = 37 , PPC_REG_F17 = 38 , PPC_REG_F18 = 39 , PPC_REG_F19 = 40 , PPC_REG_F20 = 41 , PPC_REG_F21 = 42 , PPC_REG_F22 = 43 , PPC_REG_F23 = 44 , PPC_REG_F24 = 45 , PPC_REG_F25 = 46 , PPC_REG_F26 = 47 , PPC_REG_F27 = 48 , PPC_REG_F28 = 49 , PPC_REG_F29 = 50 , PPC_REG_F30 = 51 , PPC_REG_F31 = 52 , PPC_REG_LR8 = 54 , PPC_REG_Q0 = 55 , PPC_REG_Q1 = 56 , PPC_REG_Q2 = 57 , PPC_REG_Q3 = 58 , PPC_REG_Q4 = 59 , PPC_REG_Q5 = 60 , PPC_REG_Q6 = 61 , PPC_REG_Q7 = 62 , PPC_REG_Q8 = 63 , PPC_REG_Q9 = 64 , PPC_REG_Q10 = 65 , PPC_REG_Q11 = 66 , PPC_REG_Q12 = 67 , PPC_REG_Q13 = 68 , PPC_REG_Q14 = 69 , PPC_REG_Q15 = 70 , PPC_REG_Q16 = 71 , PPC_REG_Q17 = 72 , PPC_REG_Q18 = 73 , PPC_REG_Q19 = 74 , PPC_REG_Q20 = 75 , PPC_REG_Q21 = 76 , PPC_REG_Q22 = 77 , PPC_REG_Q23 = 78 , PPC_REG_Q24 = 79 , PPC_REG_Q25 = 80 , PPC_REG_Q26 = 81 , PPC_REG_Q27 = 82 , PPC_REG_Q28 = 83 , PPC_REG_Q29 = 84 , PPC_REG_Q30 = 85 , PPC_REG_Q31 = 86 , PPC_REG_R0 = 87 , PPC_REG_R1 = 88 , PPC_REG_R2 = 89 , PPC_REG_R3 = 90 , PPC_REG_R4 = 91 , PPC_REG_R5 = 92 , PPC_REG_R6 = 93 , PPC_REG_R7 = 94 , PPC_REG_R8 = 95 , PPC_REG_R9 = 96 , PPC_REG_R10 = 97 , PPC_REG_R11 = 98 , PPC_REG_R12 = 99 , PPC_REG_R13 = 100 , PPC_REG_R14 = 101 , PPC_REG_R15 = 102 , PPC_REG_R16 = 103 , PPC_REG_R17 = 104 , PPC_REG_R18 = 105 , PPC_REG_R19 = 106 , PPC_REG_R20 = 107 , PPC_REG_R21 = 108 , PPC_REG_R22 = 109 , PPC_REG_R23 = 110 , PPC_REG_R24 = 111 , PPC_REG_R25 = 112 , PPC_REG_R26 = 113 , PPC_REG_R27 = 114 , PPC_REG_R28 = 115 , PPC_REG_R29 = 116 , PPC_REG_R30 = 117 , PPC_REG_R31 = 118 , PPC_REG_V0 = 151 , PPC_REG_V1 = 152 , PPC_REG_V2 = 153 , PPC_REG_V3 = 154 , PPC_REG_V4 = 155 , PPC_REG_V5 = 156 , PPC_REG_V6 = 157 , PPC_REG_V7 = 158 , PPC_REG_V8 = 159 , PPC_REG_V9 = 160 , PPC_REG_V10 = 161 , PPC_REG_V11 = 162 , PPC_REG_V12 = 163 , PPC_REG_V13 = 164 , PPC_REG_V14 = 165 , PPC_REG_V15 = 166 , PPC_REG_V16 = 167 , PPC_REG_V17 = 168 , PPC_REG_V18 = 169 , PPC_REG_V19 = 170 , PPC_REG_V20 = 171 , PPC_REG_V21 = 172 , PPC_REG_V22 = 173 , PPC_REG_V23 = 174 , PPC_REG_V24 = 175 , PPC_REG_V25 = 176 , PPC_REG_V26 = 177 , PPC_REG_V27 = 178 , PPC_REG_V28 = 179 , PPC_REG_V29 = 180 , PPC_REG_V30 = 181 , PPC_REG_V31 = 182 , PPC_REG_VS0 = 215 , PPC_REG_VS1 = 216 , PPC_REG_VS2 = 217 , PPC_REG_VS3 = 218 , PPC_REG_VS4 = 219 , PPC_REG_VS5 = 220 , PPC_REG_VS6 = 221 , PPC_REG_VS7 = 222 , PPC_REG_VS8 = 223 , PPC_REG_VS9 = 224 , PPC_REG_VS10 = 225 , PPC_REG_VS11 = 226 , PPC_REG_VS12 = 227 , PPC_REG_VS13 = 228 , PPC_REG_VS14 = 229 , PPC_REG_VS15 = 230 , PPC_REG_VS16 = 231 , PPC_REG_VS17 = 232 , PPC_REG_VS18 = 233 , PPC_REG_VS19 = 234 , PPC_REG_VS20 = 235 , PPC_REG_VS21 = 236 , PPC_REG_VS22 = 237 , PPC_REG_VS23 = 238 , PPC_REG_VS24 = 239 , PPC_REG_VS25 = 240 , PPC_REG_VS26 = 241 , PPC_REG_VS27 = 242 , PPC_REG_VS28 = 243 , PPC_REG_VS29 = 244 , PPC_REG_VS30 = 245 , PPC_REG_VS31 = 246 , PPC_REG_VS32 = 247 , PPC_REG_VS33 = 248 , PPC_REG_VS34 = 249 , PPC_REG_VS35 = 250 , PPC_REG_VS36 = 251 , PPC_REG_VS37 = 252 , PPC_REG_VS38 = 253 , PPC_REG_VS39 = 254 , PPC_REG_VS40 = 255 , PPC_REG_VS41 = 256 , PPC_REG_VS42 = 257 , PPC_REG_VS43 = 258 , PPC_REG_VS44 = 259 , PPC_REG_VS45 = 260 , PPC_REG_VS46 = 261 , PPC_REG_VS47 = 262 , PPC_REG_VS48 = 263 , PPC_REG_VS49 = 264 , PPC_REG_VS50 = 265 , PPC_REG_VS51 = 266 , PPC_REG_VS52 = 267 , PPC_REG_VS53 = 268 , PPC_REG_VS54 = 269 , PPC_REG_VS55 = 270 , PPC_REG_VS56 = 271 , PPC_REG_VS57 = 272 , PPC_REG_VS58 = 273 , PPC_REG_VS59 = 274 , PPC_REG_VS60 = 275 , PPC_REG_VS61 = 276 , PPC_REG_VS62 = 277 , PPC_REG_VS63 = 278 , PPC_REG_CR0EQ = 312 , PPC_REG_CR1EQ = 313 , PPC_REG_CR2EQ = 314 , PPC_REG_CR3EQ = 315 , PPC_REG_CR4EQ = 316 , PPC_REG_CR5EQ = 317 , PPC_REG_CR6EQ = 318 , PPC_REG_CR7EQ = 319 , PPC_REG_CR0GT = 320 , PPC_REG_CR1GT = 321 , PPC_REG_CR2GT = 322 , PPC_REG_CR3GT = 323 , PPC_REG_CR4GT = 324 , PPC_REG_CR5GT = 325 , PPC_REG_CR6GT = 326 , PPC_REG_CR7GT = 327 , PPC_REG_CR0LT = 328 , PPC_REG_CR1LT = 329 , PPC_REG_CR2LT = 330 , PPC_REG_CR3LT = 331 , PPC_REG_CR4LT = 332 , PPC_REG_CR5LT = 333 , PPC_REG_CR6LT = 334 , PPC_REG_CR7LT = 335 , PPC_REG_CR0UN = 336 , PPC_REG_CR1UN = 337 , PPC_REG_CR2UN = 338 , PPC_REG_CR3UN = 339 , PPC_REG_CR4UN = 340 , PPC_REG_CR5UN = 341 , PPC_REG_CR6UN = 342 , PPC_REG_CR7UN = 343 , PPC_REG_ENDING = 344 , } # [doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_mem { # [doc = "< base register"] pub base : ppc_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_mem"] [:: std :: mem :: size_of :: < ppc_op_mem > () - 8usize] ; ["Alignment of ppc_op_mem"] [:: std :: mem :: align_of :: < ppc_op_mem > () - 4usize] ; ["Offset of field: ppc_op_mem::base"] [:: std :: mem :: offset_of ! (ppc_op_mem , base) - 0usize] ; ["Offset of field: ppc_op_mem::disp"] [:: std :: mem :: offset_of ! (ppc_op_mem , disp) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_crx { pub scale : :: std :: os :: raw :: c_uint , pub reg : ppc_reg , pub cond : ppc_bc , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_crx"] [:: std :: mem :: size_of :: < ppc_op_crx > () - 12usize] ; ["Alignment of ppc_op_crx"] [:: std :: mem :: align_of :: < ppc_op_crx > () - 4usize] ; ["Offset of field: ppc_op_crx::scale"] [:: std :: mem :: offset_of ! (ppc_op_crx , scale) - 0usize] ; ["Offset of field: ppc_op_crx::reg"] [:: std :: mem :: offset_of ! (ppc_op_crx , reg) - 4usize] ; ["Offset of field: ppc_op_crx::cond"] [:: std :: mem :: offset_of ! (ppc_op_crx , cond) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc_op { # [doc = "< operand type"] pub type_ : ppc_op_type , pub __bindgen_anon_1 : cs_ppc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_ppc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : ppc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : ppc_op_mem , # [doc = "< operand with condition register"] pub crx : ppc_op_crx , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_ppc_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_ppc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::crx"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , crx) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op"] [:: std :: mem :: size_of :: < cs_ppc_op > () - 24usize] ; ["Alignment of cs_ppc_op"] [:: std :: mem :: align_of :: < cs_ppc_op > () - 8usize] ; ["Offset of field: cs_ppc_op::type_"] [:: std :: mem :: offset_of ! (cs_ppc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc { # [doc = " branch code for branch instructions"] pub bc : ppc_bc , # [doc = " branch hint for branch instructions"] pub bh : ppc_bh , # [doc = " if update_cr0 = True, then this 'dot' insn updates CR0"] pub update_cr0 : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_ppc_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc"] [:: std :: mem :: size_of :: < cs_ppc > () - 208usize] ; ["Alignment of cs_ppc"] [:: std :: mem :: align_of :: < cs_ppc > () - 8usize] ; ["Offset of field: cs_ppc::bc"] [:: std :: mem :: offset_of ! (cs_ppc , bc) - 0usize] ; ["Offset of field: cs_ppc::bh"] [:: std :: mem :: offset_of ! (cs_ppc , bh) - 4usize] ; ["Offset of field: cs_ppc::update_cr0"] [:: std :: mem :: offset_of ! (cs_ppc , update_cr0) - 8usize] ; ["Offset of field: cs_ppc::op_count"] [:: std :: mem :: offset_of ! (cs_ppc , op_count) - 9usize] ; ["Offset of field: cs_ppc::operands"] [:: std :: mem :: offset_of ! (cs_ppc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}" , self . bc , self . bh , self . update_cr0 , self . op_count , self . operands) } } # [repr (u32)] # [doc = " PPC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn { PPC_INS_INVALID = 0 , PPC_INS_ADD = 1 , PPC_INS_ADDC = 2 , PPC_INS_ADDE = 3 , PPC_INS_ADDI = 4 , PPC_INS_ADDIC = 5 , PPC_INS_ADDIS = 6 , PPC_INS_ADDME = 7 , PPC_INS_ADDPCIS = 8 , PPC_INS_ADDZE = 9 , PPC_INS_AND = 10 , PPC_INS_ANDC = 11 , PPC_INS_ANDI = 12 , PPC_INS_ANDIS = 13 , PPC_INS_ATTN = 14 , PPC_INS_B = 15 , PPC_INS_BA = 16 , PPC_INS_BC = 17 , PPC_INS_BCA = 18 , PPC_INS_BCCTR = 19 , PPC_INS_BCCTRL = 20 , PPC_INS_BCDCFN = 21 , PPC_INS_BCDCFSQ = 22 , PPC_INS_BCDCFZ = 23 , PPC_INS_BCDCPSGN = 24 , PPC_INS_BCDCTN = 25 , PPC_INS_BCDCTSQ = 26 , PPC_INS_BCDCTZ = 27 , PPC_INS_BCDS = 28 , PPC_INS_BCDSETSGN = 29 , PPC_INS_BCDSR = 30 , PPC_INS_BCDTRUNC = 31 , PPC_INS_BCDUS = 32 , PPC_INS_BCDUTRUNC = 33 , PPC_INS_BCL = 34 , PPC_INS_BCLA = 35 , PPC_INS_BCLR = 36 , PPC_INS_BCLRL = 37 , PPC_INS_BCTR = 38 , PPC_INS_BCTRL = 39 , PPC_INS_BDNZ = 40 , PPC_INS_BDNZA = 41 , PPC_INS_BDNZF = 42 , PPC_INS_BDNZFA = 43 , PPC_INS_BDNZFL = 44 , PPC_INS_BDNZFLA = 45 , PPC_INS_BDNZFLR = 46 , PPC_INS_BDNZFLRL = 47 , PPC_INS_BDNZL = 48 , PPC_INS_BDNZLA = 49 , PPC_INS_BDNZLR = 50 , PPC_INS_BDNZLRL = 51 , PPC_INS_BDNZT = 52 , PPC_INS_BDNZTA = 53 , PPC_INS_BDNZTL = 54 , PPC_INS_BDNZTLA = 55 , PPC_INS_BDNZTLR = 56 , PPC_INS_BDNZTLRL = 57 , PPC_INS_BDZ = 58 , PPC_INS_BDZA = 59 , PPC_INS_BDZF = 60 , PPC_INS_BDZFA = 61 , PPC_INS_BDZFL = 62 , PPC_INS_BDZFLA = 63 , PPC_INS_BDZFLR = 64 , PPC_INS_BDZFLRL = 65 , PPC_INS_BDZL = 66 , PPC_INS_BDZLA = 67 , PPC_INS_BDZLR = 68 , PPC_INS_BDZLRL = 69 , PPC_INS_BDZT = 70 , PPC_INS_BDZTA = 71 , PPC_INS_BDZTL = 72 , PPC_INS_BDZTLA = 73 , PPC_INS_BDZTLR = 74 , PPC_INS_BDZTLRL = 75 , PPC_INS_BEQ = 76 , PPC_INS_BEQA = 77 , PPC_INS_BEQCTR = 78 , PPC_INS_BEQCTRL = 79 , PPC_INS_BEQL = 80 , PPC_INS_BEQLA = 81 , PPC_INS_BEQLR = 82 , PPC_INS_BEQLRL = 83 , PPC_INS_BF = 84 , PPC_INS_BFA = 85 , PPC_INS_BFCTR = 86 , PPC_INS_BFCTRL = 87 , PPC_INS_BFL = 88 , PPC_INS_BFLA = 89 , PPC_INS_BFLR = 90 , PPC_INS_BFLRL = 91 , PPC_INS_BGE = 92 , PPC_INS_BGEA = 93 , PPC_INS_BGECTR = 94 , PPC_INS_BGECTRL = 95 , PPC_INS_BGEL = 96 , PPC_INS_BGELA = 97 , PPC_INS_BGELR = 98 , PPC_INS_BGELRL = 99 , PPC_INS_BGT = 100 , PPC_INS_BGTA = 101 , PPC_INS_BGTCTR = 102 , PPC_INS_BGTCTRL = 103 , PPC_INS_BGTL = 104 , PPC_INS_BGTLA = 105 , PPC_INS_BGTLR = 106 , PPC_INS_BGTLRL = 107 , PPC_INS_BL = 108 , PPC_INS_BLA = 109 , PPC_INS_BLE = 110 , PPC_INS_BLEA = 111 , PPC_INS_BLECTR = 112 , PPC_INS_BLECTRL = 113 , PPC_INS_BLEL = 114 , PPC_INS_BLELA = 115 , PPC_INS_BLELR = 116 , PPC_INS_BLELRL = 117 , PPC_INS_BLR = 118 , PPC_INS_BLRL = 119 , PPC_INS_BLT = 120 , PPC_INS_BLTA = 121 , PPC_INS_BLTCTR = 122 , PPC_INS_BLTCTRL = 123 , PPC_INS_BLTL = 124 , PPC_INS_BLTLA = 125 , PPC_INS_BLTLR = 126 , PPC_INS_BLTLRL = 127 , PPC_INS_BNE = 128 , PPC_INS_BNEA = 129 , PPC_INS_BNECTR = 130 , PPC_INS_BNECTRL = 131 , PPC_INS_BNEL = 132 , PPC_INS_BNELA = 133 , PPC_INS_BNELR = 134 , PPC_INS_BNELRL = 135 , PPC_INS_BNG = 136 , PPC_INS_BNGA = 137 , PPC_INS_BNGCTR = 138 , PPC_INS_BNGCTRL = 139 , PPC_INS_BNGL = 140 , PPC_INS_BNGLA = 141 , PPC_INS_BNGLR = 142 , PPC_INS_BNGLRL = 143 , PPC_INS_BNL = 144 , PPC_INS_BNLA = 145 , PPC_INS_BNLCTR = 146 , PPC_INS_BNLCTRL = 147 , PPC_INS_BNLL = 148 , PPC_INS_BNLLA = 149 , PPC_INS_BNLLR = 150 , PPC_INS_BNLLRL = 151 , PPC_INS_BNS = 152 , PPC_INS_BNSA = 153 , PPC_INS_BNSCTR = 154 , PPC_INS_BNSCTRL = 155 , PPC_INS_BNSL = 156 , PPC_INS_BNSLA = 157 , PPC_INS_BNSLR = 158 , PPC_INS_BNSLRL = 159 , PPC_INS_BNU = 160 , PPC_INS_BNUA = 161 , PPC_INS_BNUCTR = 162 , PPC_INS_BNUCTRL = 163 , PPC_INS_BNUL = 164 , PPC_INS_BNULA = 165 , PPC_INS_BNULR = 166 , PPC_INS_BNULRL = 167 , PPC_INS_BPERMD = 168 , PPC_INS_BRINC = 169 , PPC_INS_BSO = 170 , PPC_INS_BSOA = 171 , PPC_INS_BSOCTR = 172 , PPC_INS_BSOCTRL = 173 , PPC_INS_BSOL = 174 , PPC_INS_BSOLA = 175 , PPC_INS_BSOLR = 176 , PPC_INS_BSOLRL = 177 , PPC_INS_BT = 178 , PPC_INS_BTA = 179 , PPC_INS_BTCTR = 180 , PPC_INS_BTCTRL = 181 , PPC_INS_BTL = 182 , PPC_INS_BTLA = 183 , PPC_INS_BTLR = 184 , PPC_INS_BTLRL = 185 , PPC_INS_BUN = 186 , PPC_INS_BUNA = 187 , PPC_INS_BUNCTR = 188 , PPC_INS_BUNCTRL = 189 , PPC_INS_BUNL = 190 , PPC_INS_BUNLA = 191 , PPC_INS_BUNLR = 192 , PPC_INS_BUNLRL = 193 , PPC_INS_CLRBHRB = 194 , PPC_INS_CLRLDI = 195 , PPC_INS_CLRLSLDI = 196 , PPC_INS_CLRLSLWI = 197 , PPC_INS_CLRLWI = 198 , PPC_INS_CLRRDI = 199 , PPC_INS_CLRRWI = 200 , PPC_INS_CMP = 201 , PPC_INS_CMPB = 202 , PPC_INS_CMPD = 203 , PPC_INS_CMPDI = 204 , PPC_INS_CMPEQB = 205 , PPC_INS_CMPI = 206 , PPC_INS_CMPL = 207 , PPC_INS_CMPLD = 208 , PPC_INS_CMPLDI = 209 , PPC_INS_CMPLI = 210 , PPC_INS_CMPLW = 211 , PPC_INS_CMPLWI = 212 , PPC_INS_CMPRB = 213 , PPC_INS_CMPW = 214 , PPC_INS_CMPWI = 215 , PPC_INS_CNTLZD = 216 , PPC_INS_CNTLZW = 217 , PPC_INS_CNTTZD = 218 , PPC_INS_CNTTZW = 219 , PPC_INS_COPY = 220 , PPC_INS_COPY_FIRST = 221 , PPC_INS_CP_ABORT = 222 , PPC_INS_CRAND = 223 , PPC_INS_CRANDC = 224 , PPC_INS_CRCLR = 225 , PPC_INS_CREQV = 226 , PPC_INS_CRMOVE = 227 , PPC_INS_CRNAND = 228 , PPC_INS_CRNOR = 229 , PPC_INS_CRNOT = 230 , PPC_INS_CROR = 231 , PPC_INS_CRORC = 232 , PPC_INS_CRSET = 233 , PPC_INS_CRXOR = 234 , PPC_INS_DARN = 235 , PPC_INS_DCBA = 236 , PPC_INS_DCBF = 237 , PPC_INS_DCBFEP = 238 , PPC_INS_DCBFL = 239 , PPC_INS_DCBFLP = 240 , PPC_INS_DCBI = 241 , PPC_INS_DCBST = 242 , PPC_INS_DCBSTEP = 243 , PPC_INS_DCBT = 244 , PPC_INS_DCBTCT = 245 , PPC_INS_DCBTDS = 246 , PPC_INS_DCBTEP = 247 , PPC_INS_DCBTST = 248 , PPC_INS_DCBTSTCT = 249 , PPC_INS_DCBTSTDS = 250 , PPC_INS_DCBTSTEP = 251 , PPC_INS_DCBTSTT = 252 , PPC_INS_DCBTT = 253 , PPC_INS_DCBZ = 254 , PPC_INS_DCBZEP = 255 , PPC_INS_DCBZL = 256 , PPC_INS_DCBZLEP = 257 , PPC_INS_DCCCI = 258 , PPC_INS_DCI = 259 , PPC_INS_DIVD = 260 , PPC_INS_DIVDE = 261 , PPC_INS_DIVDEU = 262 , PPC_INS_DIVDU = 263 , PPC_INS_DIVW = 264 , PPC_INS_DIVWE = 265 , PPC_INS_DIVWEU = 266 , PPC_INS_DIVWU = 267 , PPC_INS_DSS = 268 , PPC_INS_DSSALL = 269 , PPC_INS_DST = 270 , PPC_INS_DSTST = 271 , PPC_INS_DSTSTT = 272 , PPC_INS_DSTT = 273 , PPC_INS_EFDABS = 274 , PPC_INS_EFDADD = 275 , PPC_INS_EFDCFS = 276 , PPC_INS_EFDCFSF = 277 , PPC_INS_EFDCFSI = 278 , PPC_INS_EFDCFSID = 279 , PPC_INS_EFDCFUF = 280 , PPC_INS_EFDCFUI = 281 , PPC_INS_EFDCFUID = 282 , PPC_INS_EFDCMPEQ = 283 , PPC_INS_EFDCMPGT = 284 , PPC_INS_EFDCMPLT = 285 , PPC_INS_EFDCTSF = 286 , PPC_INS_EFDCTSI = 287 , PPC_INS_EFDCTSIDZ = 288 , PPC_INS_EFDCTSIZ = 289 , PPC_INS_EFDCTUF = 290 , PPC_INS_EFDCTUI = 291 , PPC_INS_EFDCTUIDZ = 292 , PPC_INS_EFDCTUIZ = 293 , PPC_INS_EFDDIV = 294 , PPC_INS_EFDMUL = 295 , PPC_INS_EFDNABS = 296 , PPC_INS_EFDNEG = 297 , PPC_INS_EFDSUB = 298 , PPC_INS_EFDTSTEQ = 299 , PPC_INS_EFDTSTGT = 300 , PPC_INS_EFDTSTLT = 301 , PPC_INS_EFSABS = 302 , PPC_INS_EFSADD = 303 , PPC_INS_EFSCFD = 304 , PPC_INS_EFSCFSF = 305 , PPC_INS_EFSCFSI = 306 , PPC_INS_EFSCFUF = 307 , PPC_INS_EFSCFUI = 308 , PPC_INS_EFSCMPEQ = 309 , PPC_INS_EFSCMPGT = 310 , PPC_INS_EFSCMPLT = 311 , PPC_INS_EFSCTSF = 312 , PPC_INS_EFSCTSI = 313 , PPC_INS_EFSCTSIZ = 314 , PPC_INS_EFSCTUF = 315 , PPC_INS_EFSCTUI = 316 , PPC_INS_EFSCTUIZ = 317 , PPC_INS_EFSDIV = 318 , PPC_INS_EFSMUL = 319 , PPC_INS_EFSNABS = 320 , PPC_INS_EFSNEG = 321 , PPC_INS_EFSSUB = 322 , PPC_INS_EFSTSTEQ = 323 , PPC_INS_EFSTSTGT = 324 , PPC_INS_EFSTSTLT = 325 , PPC_INS_EIEIO = 326 , PPC_INS_EQV = 327 , PPC_INS_EVABS = 328 , PPC_INS_EVADDIW = 329 , PPC_INS_EVADDSMIAAW = 330 , PPC_INS_EVADDSSIAAW = 331 , PPC_INS_EVADDUMIAAW = 332 , PPC_INS_EVADDUSIAAW = 333 , PPC_INS_EVADDW = 334 , PPC_INS_EVAND = 335 , PPC_INS_EVANDC = 336 , PPC_INS_EVCMPEQ = 337 , PPC_INS_EVCMPGTS = 338 , PPC_INS_EVCMPGTU = 339 , PPC_INS_EVCMPLTS = 340 , PPC_INS_EVCMPLTU = 341 , PPC_INS_EVCNTLSW = 342 , PPC_INS_EVCNTLZW = 343 , PPC_INS_EVDIVWS = 344 , PPC_INS_EVDIVWU = 345 , PPC_INS_EVEQV = 346 , PPC_INS_EVEXTSB = 347 , PPC_INS_EVEXTSH = 348 , PPC_INS_EVFSABS = 349 , PPC_INS_EVFSADD = 350 , PPC_INS_EVFSCFSF = 351 , PPC_INS_EVFSCFSI = 352 , PPC_INS_EVFSCFUF = 353 , PPC_INS_EVFSCFUI = 354 , PPC_INS_EVFSCMPEQ = 355 , PPC_INS_EVFSCMPGT = 356 , PPC_INS_EVFSCMPLT = 357 , PPC_INS_EVFSCTSF = 358 , PPC_INS_EVFSCTSI = 359 , PPC_INS_EVFSCTSIZ = 360 , PPC_INS_EVFSCTUI = 361 , PPC_INS_EVFSDIV = 362 , PPC_INS_EVFSMUL = 363 , PPC_INS_EVFSNABS = 364 , PPC_INS_EVFSNEG = 365 , PPC_INS_EVFSSUB = 366 , PPC_INS_EVFSTSTEQ = 367 , PPC_INS_EVFSTSTGT = 368 , PPC_INS_EVFSTSTLT = 369 , PPC_INS_EVLDD = 370 , PPC_INS_EVLDDX = 371 , PPC_INS_EVLDH = 372 , PPC_INS_EVLDHX = 373 , PPC_INS_EVLDW = 374 , PPC_INS_EVLDWX = 375 , PPC_INS_EVLHHESPLAT = 376 , PPC_INS_EVLHHESPLATX = 377 , PPC_INS_EVLHHOSSPLAT = 378 , PPC_INS_EVLHHOSSPLATX = 379 , PPC_INS_EVLHHOUSPLAT = 380 , PPC_INS_EVLHHOUSPLATX = 381 , PPC_INS_EVLWHE = 382 , PPC_INS_EVLWHEX = 383 , PPC_INS_EVLWHOS = 384 , PPC_INS_EVLWHOSX = 385 , PPC_INS_EVLWHOU = 386 , PPC_INS_EVLWHOUX = 387 , PPC_INS_EVLWHSPLAT = 388 , PPC_INS_EVLWHSPLATX = 389 , PPC_INS_EVLWWSPLAT = 390 , PPC_INS_EVLWWSPLATX = 391 , PPC_INS_EVMERGEHI = 392 , PPC_INS_EVMERGEHILO = 393 , PPC_INS_EVMERGELO = 394 , PPC_INS_EVMERGELOHI = 395 , PPC_INS_EVMHEGSMFAA = 396 , PPC_INS_EVMHEGSMFAN = 397 , PPC_INS_EVMHEGSMIAA = 398 , PPC_INS_EVMHEGSMIAN = 399 , PPC_INS_EVMHEGUMIAA = 400 , PPC_INS_EVMHEGUMIAN = 401 , PPC_INS_EVMHESMF = 402 , PPC_INS_EVMHESMFA = 403 , PPC_INS_EVMHESMFAAW = 404 , PPC_INS_EVMHESMFANW = 405 , PPC_INS_EVMHESMI = 406 , PPC_INS_EVMHESMIA = 407 , PPC_INS_EVMHESMIAAW = 408 , PPC_INS_EVMHESMIANW = 409 , PPC_INS_EVMHESSF = 410 , PPC_INS_EVMHESSFA = 411 , PPC_INS_EVMHESSFAAW = 412 , PPC_INS_EVMHESSFANW = 413 , PPC_INS_EVMHESSIAAW = 414 , PPC_INS_EVMHESSIANW = 415 , PPC_INS_EVMHEUMI = 416 , PPC_INS_EVMHEUMIA = 417 , PPC_INS_EVMHEUMIAAW = 418 , PPC_INS_EVMHEUMIANW = 419 , PPC_INS_EVMHEUSIAAW = 420 , PPC_INS_EVMHEUSIANW = 421 , PPC_INS_EVMHOGSMFAA = 422 , PPC_INS_EVMHOGSMFAN = 423 , PPC_INS_EVMHOGSMIAA = 424 , PPC_INS_EVMHOGSMIAN = 425 , PPC_INS_EVMHOGUMIAA = 426 , PPC_INS_EVMHOGUMIAN = 427 , PPC_INS_EVMHOSMF = 428 , PPC_INS_EVMHOSMFA = 429 , PPC_INS_EVMHOSMFAAW = 430 , PPC_INS_EVMHOSMFANW = 431 , PPC_INS_EVMHOSMI = 432 , PPC_INS_EVMHOSMIA = 433 , PPC_INS_EVMHOSMIAAW = 434 , PPC_INS_EVMHOSMIANW = 435 , PPC_INS_EVMHOSSF = 436 , PPC_INS_EVMHOSSFA = 437 , PPC_INS_EVMHOSSFAAW = 438 , PPC_INS_EVMHOSSFANW = 439 , PPC_INS_EVMHOSSIAAW = 440 , PPC_INS_EVMHOSSIANW = 441 , PPC_INS_EVMHOUMI = 442 , PPC_INS_EVMHOUMIA = 443 , PPC_INS_EVMHOUMIAAW = 444 , PPC_INS_EVMHOUMIANW = 445 , PPC_INS_EVMHOUSIAAW = 446 , PPC_INS_EVMHOUSIANW = 447 , PPC_INS_EVMRA = 448 , PPC_INS_EVMWHSMF = 449 , PPC_INS_EVMWHSMFA = 450 , PPC_INS_EVMWHSMI = 451 , PPC_INS_EVMWHSMIA = 452 , PPC_INS_EVMWHSSF = 453 , PPC_INS_EVMWHSSFA = 454 , PPC_INS_EVMWHUMI = 455 , PPC_INS_EVMWHUMIA = 456 , PPC_INS_EVMWLSMIAAW = 457 , PPC_INS_EVMWLSMIANW = 458 , PPC_INS_EVMWLSSIAAW = 459 , PPC_INS_EVMWLSSIANW = 460 , PPC_INS_EVMWLUMI = 461 , PPC_INS_EVMWLUMIA = 462 , PPC_INS_EVMWLUMIAAW = 463 , PPC_INS_EVMWLUMIANW = 464 , PPC_INS_EVMWLUSIAAW = 465 , PPC_INS_EVMWLUSIANW = 466 , PPC_INS_EVMWSMF = 467 , PPC_INS_EVMWSMFA = 468 , PPC_INS_EVMWSMFAA = 469 , PPC_INS_EVMWSMFAN = 470 , PPC_INS_EVMWSMI = 471 , PPC_INS_EVMWSMIA = 472 , PPC_INS_EVMWSMIAA = 473 , PPC_INS_EVMWSMIAN = 474 , PPC_INS_EVMWSSF = 475 , PPC_INS_EVMWSSFA = 476 , PPC_INS_EVMWSSFAA = 477 , PPC_INS_EVMWSSFAN = 478 , PPC_INS_EVMWUMI = 479 , PPC_INS_EVMWUMIA = 480 , PPC_INS_EVMWUMIAA = 481 , PPC_INS_EVMWUMIAN = 482 , PPC_INS_EVNAND = 483 , PPC_INS_EVNEG = 484 , PPC_INS_EVNOR = 485 , PPC_INS_EVOR = 486 , PPC_INS_EVORC = 487 , PPC_INS_EVRLW = 488 , PPC_INS_EVRLWI = 489 , PPC_INS_EVRNDW = 490 , PPC_INS_EVSEL = 491 , PPC_INS_EVSLW = 492 , PPC_INS_EVSLWI = 493 , PPC_INS_EVSPLATFI = 494 , PPC_INS_EVSPLATI = 495 , PPC_INS_EVSRWIS = 496 , PPC_INS_EVSRWIU = 497 , PPC_INS_EVSRWS = 498 , PPC_INS_EVSRWU = 499 , PPC_INS_EVSTDD = 500 , PPC_INS_EVSTDDX = 501 , PPC_INS_EVSTDH = 502 , PPC_INS_EVSTDHX = 503 , PPC_INS_EVSTDW = 504 , PPC_INS_EVSTDWX = 505 , PPC_INS_EVSTWHE = 506 , PPC_INS_EVSTWHEX = 507 , PPC_INS_EVSTWHO = 508 , PPC_INS_EVSTWHOX = 509 , PPC_INS_EVSTWWE = 510 , PPC_INS_EVSTWWEX = 511 , PPC_INS_EVSTWWO = 512 , PPC_INS_EVSTWWOX = 513 , PPC_INS_EVSUBFSMIAAW = 514 , PPC_INS_EVSUBFSSIAAW = 515 , PPC_INS_EVSUBFUMIAAW = 516 , PPC_INS_EVSUBFUSIAAW = 517 , PPC_INS_EVSUBFW = 518 , PPC_INS_EVSUBIFW = 519 , PPC_INS_EVXOR = 520 , PPC_INS_EXTLDI = 521 , PPC_INS_EXTLWI = 522 , PPC_INS_EXTRDI = 523 , PPC_INS_EXTRWI = 524 , PPC_INS_EXTSB = 525 , PPC_INS_EXTSH = 526 , PPC_INS_EXTSW = 527 , PPC_INS_EXTSWSLI = 528 , PPC_INS_FABS = 529 , PPC_INS_FADD = 530 , PPC_INS_FADDS = 531 , PPC_INS_FCFID = 532 , PPC_INS_FCFIDS = 533 , PPC_INS_FCFIDU = 534 , PPC_INS_FCFIDUS = 535 , PPC_INS_FCMPU = 536 , PPC_INS_FCPSGN = 537 , PPC_INS_FCTID = 538 , PPC_INS_FCTIDU = 539 , PPC_INS_FCTIDUZ = 540 , PPC_INS_FCTIDZ = 541 , PPC_INS_FCTIW = 542 , PPC_INS_FCTIWU = 543 , PPC_INS_FCTIWUZ = 544 , PPC_INS_FCTIWZ = 545 , PPC_INS_FDIV = 546 , PPC_INS_FDIVS = 547 , PPC_INS_FMADD = 548 , PPC_INS_FMADDS = 549 , PPC_INS_FMR = 550 , PPC_INS_FMSUB = 551 , PPC_INS_FMSUBS = 552 , PPC_INS_FMUL = 553 , PPC_INS_FMULS = 554 , PPC_INS_FNABS = 555 , PPC_INS_FNEG = 556 , PPC_INS_FNMADD = 557 , PPC_INS_FNMADDS = 558 , PPC_INS_FNMSUB = 559 , PPC_INS_FNMSUBS = 560 , PPC_INS_FRE = 561 , PPC_INS_FRES = 562 , PPC_INS_FRIM = 563 , PPC_INS_FRIN = 564 , PPC_INS_FRIP = 565 , PPC_INS_FRIZ = 566 , PPC_INS_FRSP = 567 , PPC_INS_FRSQRTE = 568 , PPC_INS_FRSQRTES = 569 , PPC_INS_FSEL = 570 , PPC_INS_FSQRT = 571 , PPC_INS_FSQRTS = 572 , PPC_INS_FSUB = 573 , PPC_INS_FSUBS = 574 , PPC_INS_FTDIV = 575 , PPC_INS_FTSQRT = 576 , PPC_INS_HRFID = 577 , PPC_INS_ICBI = 578 , PPC_INS_ICBIEP = 579 , PPC_INS_ICBLC = 580 , PPC_INS_ICBLQ = 581 , PPC_INS_ICBT = 582 , PPC_INS_ICBTLS = 583 , PPC_INS_ICCCI = 584 , PPC_INS_ICI = 585 , PPC_INS_INSLWI = 586 , PPC_INS_INSRDI = 587 , PPC_INS_INSRWI = 588 , PPC_INS_ISEL = 589 , PPC_INS_ISYNC = 590 , PPC_INS_LA = 591 , PPC_INS_LBARX = 592 , PPC_INS_LBEPX = 593 , PPC_INS_LBZ = 594 , PPC_INS_LBZCIX = 595 , PPC_INS_LBZU = 596 , PPC_INS_LBZUX = 597 , PPC_INS_LBZX = 598 , PPC_INS_LD = 599 , PPC_INS_LDARX = 600 , PPC_INS_LDAT = 601 , PPC_INS_LDBRX = 602 , PPC_INS_LDCIX = 603 , PPC_INS_LDMX = 604 , PPC_INS_LDU = 605 , PPC_INS_LDUX = 606 , PPC_INS_LDX = 607 , PPC_INS_LFD = 608 , PPC_INS_LFDEPX = 609 , PPC_INS_LFDU = 610 , PPC_INS_LFDUX = 611 , PPC_INS_LFDX = 612 , PPC_INS_LFIWAX = 613 , PPC_INS_LFIWZX = 614 , PPC_INS_LFS = 615 , PPC_INS_LFSU = 616 , PPC_INS_LFSUX = 617 , PPC_INS_LFSX = 618 , PPC_INS_LHA = 619 , PPC_INS_LHARX = 620 , PPC_INS_LHAU = 621 , PPC_INS_LHAUX = 622 , PPC_INS_LHAX = 623 , PPC_INS_LHBRX = 624 , PPC_INS_LHEPX = 625 , PPC_INS_LHZ = 626 , PPC_INS_LHZCIX = 627 , PPC_INS_LHZU = 628 , PPC_INS_LHZUX = 629 , PPC_INS_LHZX = 630 , PPC_INS_LI = 631 , PPC_INS_LIS = 632 , PPC_INS_LMW = 633 , PPC_INS_LNIA = 634 , PPC_INS_LSWI = 635 , PPC_INS_LVEBX = 636 , PPC_INS_LVEHX = 637 , PPC_INS_LVEWX = 638 , PPC_INS_LVSL = 639 , PPC_INS_LVSR = 640 , PPC_INS_LVX = 641 , PPC_INS_LVXL = 642 , PPC_INS_LWA = 643 , PPC_INS_LWARX = 644 , PPC_INS_LWAT = 645 , PPC_INS_LWAUX = 646 , PPC_INS_LWAX = 647 , PPC_INS_LWBRX = 648 , PPC_INS_LWEPX = 649 , PPC_INS_LWSYNC = 650 , PPC_INS_LWZ = 651 , PPC_INS_LWZCIX = 652 , PPC_INS_LWZU = 653 , PPC_INS_LWZUX = 654 , PPC_INS_LWZX = 655 , PPC_INS_LXSD = 656 , PPC_INS_LXSDX = 657 , PPC_INS_LXSIBZX = 658 , PPC_INS_LXSIHZX = 659 , PPC_INS_LXSIWAX = 660 , PPC_INS_LXSIWZX = 661 , PPC_INS_LXSSP = 662 , PPC_INS_LXSSPX = 663 , PPC_INS_LXV = 664 , PPC_INS_LXVB16X = 665 , PPC_INS_LXVD2X = 666 , PPC_INS_LXVDSX = 667 , PPC_INS_LXVH8X = 668 , PPC_INS_LXVL = 669 , PPC_INS_LXVLL = 670 , PPC_INS_LXVW4X = 671 , PPC_INS_LXVWSX = 672 , PPC_INS_LXVX = 673 , PPC_INS_MADDHD = 674 , PPC_INS_MADDHDU = 675 , PPC_INS_MADDLD = 676 , PPC_INS_MBAR = 677 , PPC_INS_MCRF = 678 , PPC_INS_MCRFS = 679 , PPC_INS_MCRXRX = 680 , PPC_INS_MFAMR = 681 , PPC_INS_MFASR = 682 , PPC_INS_MFBHRBE = 683 , PPC_INS_MFBR0 = 684 , PPC_INS_MFBR1 = 685 , PPC_INS_MFBR2 = 686 , PPC_INS_MFBR3 = 687 , PPC_INS_MFBR4 = 688 , PPC_INS_MFBR5 = 689 , PPC_INS_MFBR6 = 690 , PPC_INS_MFBR7 = 691 , PPC_INS_MFCFAR = 692 , PPC_INS_MFCR = 693 , PPC_INS_MFCTR = 694 , PPC_INS_MFDAR = 695 , PPC_INS_MFDBATL = 696 , PPC_INS_MFDBATU = 697 , PPC_INS_MFDCCR = 698 , PPC_INS_MFDCR = 699 , PPC_INS_MFDEAR = 700 , PPC_INS_MFDEC = 701 , PPC_INS_MFDSCR = 702 , PPC_INS_MFDSISR = 703 , PPC_INS_MFESR = 704 , PPC_INS_MFFPRD = 705 , PPC_INS_MFFS = 706 , PPC_INS_MFFSCDRN = 707 , PPC_INS_MFFSCDRNI = 708 , PPC_INS_MFFSCE = 709 , PPC_INS_MFFSCRN = 710 , PPC_INS_MFFSCRNI = 711 , PPC_INS_MFFSL = 712 , PPC_INS_MFIBATL = 713 , PPC_INS_MFIBATU = 714 , PPC_INS_MFICCR = 715 , PPC_INS_MFLR = 716 , PPC_INS_MFMSR = 717 , PPC_INS_MFOCRF = 718 , PPC_INS_MFPID = 719 , PPC_INS_MFPMR = 720 , PPC_INS_MFPVR = 721 , PPC_INS_MFRTCL = 722 , PPC_INS_MFRTCU = 723 , PPC_INS_MFSDR1 = 724 , PPC_INS_MFSPEFSCR = 725 , PPC_INS_MFSPR = 726 , PPC_INS_MFSPRG = 727 , PPC_INS_MFSPRG0 = 728 , PPC_INS_MFSPRG1 = 729 , PPC_INS_MFSPRG2 = 730 , PPC_INS_MFSPRG3 = 731 , PPC_INS_MFSPRG4 = 732 , PPC_INS_MFSPRG5 = 733 , PPC_INS_MFSPRG6 = 734 , PPC_INS_MFSPRG7 = 735 , PPC_INS_MFSR = 736 , PPC_INS_MFSRIN = 737 , PPC_INS_MFSRR0 = 738 , PPC_INS_MFSRR1 = 739 , PPC_INS_MFSRR2 = 740 , PPC_INS_MFSRR3 = 741 , PPC_INS_MFTB = 742 , PPC_INS_MFTBHI = 743 , PPC_INS_MFTBL = 744 , PPC_INS_MFTBLO = 745 , PPC_INS_MFTBU = 746 , PPC_INS_MFTCR = 747 , PPC_INS_MFVRD = 748 , PPC_INS_MFVRSAVE = 749 , PPC_INS_MFVSCR = 750 , PPC_INS_MFVSRD = 751 , PPC_INS_MFVSRLD = 752 , PPC_INS_MFVSRWZ = 753 , PPC_INS_MFXER = 754 , PPC_INS_MODSD = 755 , PPC_INS_MODSW = 756 , PPC_INS_MODUD = 757 , PPC_INS_MODUW = 758 , PPC_INS_MR = 759 , PPC_INS_MSGSYNC = 760 , PPC_INS_MSYNC = 761 , PPC_INS_MTAMR = 762 , PPC_INS_MTASR = 763 , PPC_INS_MTBR0 = 764 , PPC_INS_MTBR1 = 765 , PPC_INS_MTBR2 = 766 , PPC_INS_MTBR3 = 767 , PPC_INS_MTBR4 = 768 , PPC_INS_MTBR5 = 769 , PPC_INS_MTBR6 = 770 , PPC_INS_MTBR7 = 771 , PPC_INS_MTCFAR = 772 , PPC_INS_MTCR = 773 , PPC_INS_MTCRF = 774 , PPC_INS_MTCTR = 775 , PPC_INS_MTDAR = 776 , PPC_INS_MTDBATL = 777 , PPC_INS_MTDBATU = 778 , PPC_INS_MTDCCR = 779 , PPC_INS_MTDCR = 780 , PPC_INS_MTDEAR = 781 , PPC_INS_MTDEC = 782 , PPC_INS_MTDSCR = 783 , PPC_INS_MTDSISR = 784 , PPC_INS_MTESR = 785 , PPC_INS_MTFSB0 = 786 , PPC_INS_MTFSB1 = 787 , PPC_INS_MTFSF = 788 , PPC_INS_MTFSFI = 789 , PPC_INS_MTIBATL = 790 , PPC_INS_MTIBATU = 791 , PPC_INS_MTICCR = 792 , PPC_INS_MTLR = 793 , PPC_INS_MTMSR = 794 , PPC_INS_MTMSRD = 795 , PPC_INS_MTOCRF = 796 , PPC_INS_MTPID = 797 , PPC_INS_MTPMR = 798 , PPC_INS_MTSDR1 = 799 , PPC_INS_MTSPEFSCR = 800 , PPC_INS_MTSPR = 801 , PPC_INS_MTSPRG = 802 , PPC_INS_MTSPRG0 = 803 , PPC_INS_MTSPRG1 = 804 , PPC_INS_MTSPRG2 = 805 , PPC_INS_MTSPRG3 = 806 , PPC_INS_MTSPRG4 = 807 , PPC_INS_MTSPRG5 = 808 , PPC_INS_MTSPRG6 = 809 , PPC_INS_MTSPRG7 = 810 , PPC_INS_MTSR = 811 , PPC_INS_MTSRIN = 812 , PPC_INS_MTSRR0 = 813 , PPC_INS_MTSRR1 = 814 , PPC_INS_MTSRR2 = 815 , PPC_INS_MTSRR3 = 816 , PPC_INS_MTTBHI = 817 , PPC_INS_MTTBL = 818 , PPC_INS_MTTBLO = 819 , PPC_INS_MTTBU = 820 , PPC_INS_MTTCR = 821 , PPC_INS_MTVRSAVE = 822 , PPC_INS_MTVSCR = 823 , PPC_INS_MTVSRD = 824 , PPC_INS_MTVSRDD = 825 , PPC_INS_MTVSRWA = 826 , PPC_INS_MTVSRWS = 827 , PPC_INS_MTVSRWZ = 828 , PPC_INS_MTXER = 829 , PPC_INS_MULHD = 830 , PPC_INS_MULHDU = 831 , PPC_INS_MULHW = 832 , PPC_INS_MULHWU = 833 , PPC_INS_MULLD = 834 , PPC_INS_MULLI = 835 , PPC_INS_MULLW = 836 , PPC_INS_NAND = 837 , PPC_INS_NAP = 838 , PPC_INS_NEG = 839 , PPC_INS_NOP = 840 , PPC_INS_NOR = 841 , PPC_INS_NOT = 842 , PPC_INS_OR = 843 , PPC_INS_ORC = 844 , PPC_INS_ORI = 845 , PPC_INS_ORIS = 846 , PPC_INS_PASTE = 847 , PPC_INS_PASTE_LAST = 848 , PPC_INS_POPCNTB = 849 , PPC_INS_POPCNTD = 850 , PPC_INS_POPCNTW = 851 , PPC_INS_PTESYNC = 852 , PPC_INS_QVALIGNI = 853 , PPC_INS_QVESPLATI = 854 , PPC_INS_QVFABS = 855 , PPC_INS_QVFADD = 856 , PPC_INS_QVFADDS = 857 , PPC_INS_QVFAND = 858 , PPC_INS_QVFANDC = 859 , PPC_INS_QVFCFID = 860 , PPC_INS_QVFCFIDS = 861 , PPC_INS_QVFCFIDU = 862 , PPC_INS_QVFCFIDUS = 863 , PPC_INS_QVFCLR = 864 , PPC_INS_QVFCMPEQ = 865 , PPC_INS_QVFCMPGT = 866 , PPC_INS_QVFCMPLT = 867 , PPC_INS_QVFCPSGN = 868 , PPC_INS_QVFCTFB = 869 , PPC_INS_QVFCTID = 870 , PPC_INS_QVFCTIDU = 871 , PPC_INS_QVFCTIDUZ = 872 , PPC_INS_QVFCTIDZ = 873 , PPC_INS_QVFCTIW = 874 , PPC_INS_QVFCTIWU = 875 , PPC_INS_QVFCTIWUZ = 876 , PPC_INS_QVFCTIWZ = 877 , PPC_INS_QVFEQU = 878 , PPC_INS_QVFLOGICAL = 879 , PPC_INS_QVFMADD = 880 , PPC_INS_QVFMADDS = 881 , PPC_INS_QVFMR = 882 , PPC_INS_QVFMSUB = 883 , PPC_INS_QVFMSUBS = 884 , PPC_INS_QVFMUL = 885 , PPC_INS_QVFMULS = 886 , PPC_INS_QVFNABS = 887 , PPC_INS_QVFNAND = 888 , PPC_INS_QVFNEG = 889 , PPC_INS_QVFNMADD = 890 , PPC_INS_QVFNMADDS = 891 , PPC_INS_QVFNMSUB = 892 , PPC_INS_QVFNMSUBS = 893 , PPC_INS_QVFNOR = 894 , PPC_INS_QVFNOT = 895 , PPC_INS_QVFOR = 896 , PPC_INS_QVFORC = 897 , PPC_INS_QVFPERM = 898 , PPC_INS_QVFRE = 899 , PPC_INS_QVFRES = 900 , PPC_INS_QVFRIM = 901 , PPC_INS_QVFRIN = 902 , PPC_INS_QVFRIP = 903 , PPC_INS_QVFRIZ = 904 , PPC_INS_QVFRSP = 905 , PPC_INS_QVFRSQRTE = 906 , PPC_INS_QVFRSQRTES = 907 , PPC_INS_QVFSEL = 908 , PPC_INS_QVFSET = 909 , PPC_INS_QVFSUB = 910 , PPC_INS_QVFSUBS = 911 , PPC_INS_QVFTSTNAN = 912 , PPC_INS_QVFXMADD = 913 , PPC_INS_QVFXMADDS = 914 , PPC_INS_QVFXMUL = 915 , PPC_INS_QVFXMULS = 916 , PPC_INS_QVFXOR = 917 , PPC_INS_QVFXXCPNMADD = 918 , PPC_INS_QVFXXCPNMADDS = 919 , PPC_INS_QVFXXMADD = 920 , PPC_INS_QVFXXMADDS = 921 , PPC_INS_QVFXXNPMADD = 922 , PPC_INS_QVFXXNPMADDS = 923 , PPC_INS_QVGPCI = 924 , PPC_INS_QVLFCDUX = 925 , PPC_INS_QVLFCDUXA = 926 , PPC_INS_QVLFCDX = 927 , PPC_INS_QVLFCDXA = 928 , PPC_INS_QVLFCSUX = 929 , PPC_INS_QVLFCSUXA = 930 , PPC_INS_QVLFCSX = 931 , PPC_INS_QVLFCSXA = 932 , PPC_INS_QVLFDUX = 933 , PPC_INS_QVLFDUXA = 934 , PPC_INS_QVLFDX = 935 , PPC_INS_QVLFDXA = 936 , PPC_INS_QVLFIWAX = 937 , PPC_INS_QVLFIWAXA = 938 , PPC_INS_QVLFIWZX = 939 , PPC_INS_QVLFIWZXA = 940 , PPC_INS_QVLFSUX = 941 , PPC_INS_QVLFSUXA = 942 , PPC_INS_QVLFSX = 943 , PPC_INS_QVLFSXA = 944 , PPC_INS_QVLPCLDX = 945 , PPC_INS_QVLPCLSX = 946 , PPC_INS_QVLPCRDX = 947 , PPC_INS_QVLPCRSX = 948 , PPC_INS_QVSTFCDUX = 949 , PPC_INS_QVSTFCDUXA = 950 , PPC_INS_QVSTFCDUXI = 951 , PPC_INS_QVSTFCDUXIA = 952 , PPC_INS_QVSTFCDX = 953 , PPC_INS_QVSTFCDXA = 954 , PPC_INS_QVSTFCDXI = 955 , PPC_INS_QVSTFCDXIA = 956 , PPC_INS_QVSTFCSUX = 957 , PPC_INS_QVSTFCSUXA = 958 , PPC_INS_QVSTFCSUXI = 959 , PPC_INS_QVSTFCSUXIA = 960 , PPC_INS_QVSTFCSX = 961 , PPC_INS_QVSTFCSXA = 962 , PPC_INS_QVSTFCSXI = 963 , PPC_INS_QVSTFCSXIA = 964 , PPC_INS_QVSTFDUX = 965 , PPC_INS_QVSTFDUXA = 966 , PPC_INS_QVSTFDUXI = 967 , PPC_INS_QVSTFDUXIA = 968 , PPC_INS_QVSTFDX = 969 , PPC_INS_QVSTFDXA = 970 , PPC_INS_QVSTFDXI = 971 , PPC_INS_QVSTFDXIA = 972 , PPC_INS_QVSTFIWX = 973 , PPC_INS_QVSTFIWXA = 974 , PPC_INS_QVSTFSUX = 975 , PPC_INS_QVSTFSUXA = 976 , PPC_INS_QVSTFSUXI = 977 , PPC_INS_QVSTFSUXIA = 978 , PPC_INS_QVSTFSX = 979 , PPC_INS_QVSTFSXA = 980 , PPC_INS_QVSTFSXI = 981 , PPC_INS_QVSTFSXIA = 982 , PPC_INS_RFCI = 983 , PPC_INS_RFDI = 984 , PPC_INS_RFEBB = 985 , PPC_INS_RFI = 986 , PPC_INS_RFID = 987 , PPC_INS_RFMCI = 988 , PPC_INS_RLDCL = 989 , PPC_INS_RLDCR = 990 , PPC_INS_RLDIC = 991 , PPC_INS_RLDICL = 992 , PPC_INS_RLDICR = 993 , PPC_INS_RLDIMI = 994 , PPC_INS_RLWIMI = 995 , PPC_INS_RLWINM = 996 , PPC_INS_RLWNM = 997 , PPC_INS_ROTLD = 998 , PPC_INS_ROTLDI = 999 , PPC_INS_ROTLW = 1000 , PPC_INS_ROTLWI = 1001 , PPC_INS_ROTRDI = 1002 , PPC_INS_ROTRWI = 1003 , PPC_INS_SC = 1004 , PPC_INS_SETB = 1005 , PPC_INS_SLBIA = 1006 , PPC_INS_SLBIE = 1007 , PPC_INS_SLBIEG = 1008 , PPC_INS_SLBMFEE = 1009 , PPC_INS_SLBMFEV = 1010 , PPC_INS_SLBMTE = 1011 , PPC_INS_SLBSYNC = 1012 , PPC_INS_SLD = 1013 , PPC_INS_SLDI = 1014 , PPC_INS_SLW = 1015 , PPC_INS_SLWI = 1016 , PPC_INS_SRAD = 1017 , PPC_INS_SRADI = 1018 , PPC_INS_SRAW = 1019 , PPC_INS_SRAWI = 1020 , PPC_INS_SRD = 1021 , PPC_INS_SRDI = 1022 , PPC_INS_SRW = 1023 , PPC_INS_SRWI = 1024 , PPC_INS_STB = 1025 , PPC_INS_STBCIX = 1026 , PPC_INS_STBCX = 1027 , PPC_INS_STBEPX = 1028 , PPC_INS_STBU = 1029 , PPC_INS_STBUX = 1030 , PPC_INS_STBX = 1031 , PPC_INS_STD = 1032 , PPC_INS_STDAT = 1033 , PPC_INS_STDBRX = 1034 , PPC_INS_STDCIX = 1035 , PPC_INS_STDCX = 1036 , PPC_INS_STDU = 1037 , PPC_INS_STDUX = 1038 , PPC_INS_STDX = 1039 , PPC_INS_STFD = 1040 , PPC_INS_STFDEPX = 1041 , PPC_INS_STFDU = 1042 , PPC_INS_STFDUX = 1043 , PPC_INS_STFDX = 1044 , PPC_INS_STFIWX = 1045 , PPC_INS_STFS = 1046 , PPC_INS_STFSU = 1047 , PPC_INS_STFSUX = 1048 , PPC_INS_STFSX = 1049 , PPC_INS_STH = 1050 , PPC_INS_STHBRX = 1051 , PPC_INS_STHCIX = 1052 , PPC_INS_STHCX = 1053 , PPC_INS_STHEPX = 1054 , PPC_INS_STHU = 1055 , PPC_INS_STHUX = 1056 , PPC_INS_STHX = 1057 , PPC_INS_STMW = 1058 , PPC_INS_STOP = 1059 , PPC_INS_STSWI = 1060 , PPC_INS_STVEBX = 1061 , PPC_INS_STVEHX = 1062 , PPC_INS_STVEWX = 1063 , PPC_INS_STVX = 1064 , PPC_INS_STVXL = 1065 , PPC_INS_STW = 1066 , PPC_INS_STWAT = 1067 , PPC_INS_STWBRX = 1068 , PPC_INS_STWCIX = 1069 , PPC_INS_STWCX = 1070 , PPC_INS_STWEPX = 1071 , PPC_INS_STWU = 1072 , PPC_INS_STWUX = 1073 , PPC_INS_STWX = 1074 , PPC_INS_STXSD = 1075 , PPC_INS_STXSDX = 1076 , PPC_INS_STXSIBX = 1077 , PPC_INS_STXSIHX = 1078 , PPC_INS_STXSIWX = 1079 , PPC_INS_STXSSP = 1080 , PPC_INS_STXSSPX = 1081 , PPC_INS_STXV = 1082 , PPC_INS_STXVB16X = 1083 , PPC_INS_STXVD2X = 1084 , PPC_INS_STXVH8X = 1085 , PPC_INS_STXVL = 1086 , PPC_INS_STXVLL = 1087 , PPC_INS_STXVW4X = 1088 , PPC_INS_STXVX = 1089 , PPC_INS_SUB = 1090 , PPC_INS_SUBC = 1091 , PPC_INS_SUBF = 1092 , PPC_INS_SUBFC = 1093 , PPC_INS_SUBFE = 1094 , PPC_INS_SUBFIC = 1095 , PPC_INS_SUBFME = 1096 , PPC_INS_SUBFZE = 1097 , PPC_INS_SUBI = 1098 , PPC_INS_SUBIC = 1099 , PPC_INS_SUBIS = 1100 , PPC_INS_SUBPCIS = 1101 , PPC_INS_SYNC = 1102 , PPC_INS_TABORT = 1103 , PPC_INS_TABORTDC = 1104 , PPC_INS_TABORTDCI = 1105 , PPC_INS_TABORTWC = 1106 , PPC_INS_TABORTWCI = 1107 , PPC_INS_TBEGIN = 1108 , PPC_INS_TCHECK = 1109 , PPC_INS_TD = 1110 , PPC_INS_TDEQ = 1111 , PPC_INS_TDEQI = 1112 , PPC_INS_TDGE = 1113 , PPC_INS_TDGEI = 1114 , PPC_INS_TDGT = 1115 , PPC_INS_TDGTI = 1116 , PPC_INS_TDI = 1117 , PPC_INS_TDLE = 1118 , PPC_INS_TDLEI = 1119 , PPC_INS_TDLGE = 1120 , PPC_INS_TDLGEI = 1121 , PPC_INS_TDLGT = 1122 , PPC_INS_TDLGTI = 1123 , PPC_INS_TDLLE = 1124 , PPC_INS_TDLLEI = 1125 , PPC_INS_TDLLT = 1126 , PPC_INS_TDLLTI = 1127 , PPC_INS_TDLNG = 1128 , PPC_INS_TDLNGI = 1129 , PPC_INS_TDLNL = 1130 , PPC_INS_TDLNLI = 1131 , PPC_INS_TDLT = 1132 , PPC_INS_TDLTI = 1133 , PPC_INS_TDNE = 1134 , PPC_INS_TDNEI = 1135 , PPC_INS_TDNG = 1136 , PPC_INS_TDNGI = 1137 , PPC_INS_TDNL = 1138 , PPC_INS_TDNLI = 1139 , PPC_INS_TDU = 1140 , PPC_INS_TDUI = 1141 , PPC_INS_TEND = 1142 , PPC_INS_TLBIA = 1143 , PPC_INS_TLBIE = 1144 , PPC_INS_TLBIEL = 1145 , PPC_INS_TLBIVAX = 1146 , PPC_INS_TLBLD = 1147 , PPC_INS_TLBLI = 1148 , PPC_INS_TLBRE = 1149 , PPC_INS_TLBREHI = 1150 , PPC_INS_TLBRELO = 1151 , PPC_INS_TLBSX = 1152 , PPC_INS_TLBSYNC = 1153 , PPC_INS_TLBWE = 1154 , PPC_INS_TLBWEHI = 1155 , PPC_INS_TLBWELO = 1156 , PPC_INS_TRAP = 1157 , PPC_INS_TRECHKPT = 1158 , PPC_INS_TRECLAIM = 1159 , PPC_INS_TSR = 1160 , PPC_INS_TW = 1161 , PPC_INS_TWEQ = 1162 , PPC_INS_TWEQI = 1163 , PPC_INS_TWGE = 1164 , PPC_INS_TWGEI = 1165 , PPC_INS_TWGT = 1166 , PPC_INS_TWGTI = 1167 , PPC_INS_TWI = 1168 , PPC_INS_TWLE = 1169 , PPC_INS_TWLEI = 1170 , PPC_INS_TWLGE = 1171 , PPC_INS_TWLGEI = 1172 , PPC_INS_TWLGT = 1173 , PPC_INS_TWLGTI = 1174 , PPC_INS_TWLLE = 1175 , PPC_INS_TWLLEI = 1176 , PPC_INS_TWLLT = 1177 , PPC_INS_TWLLTI = 1178 , PPC_INS_TWLNG = 1179 , PPC_INS_TWLNGI = 1180 , PPC_INS_TWLNL = 1181 , PPC_INS_TWLNLI = 1182 , PPC_INS_TWLT = 1183 , PPC_INS_TWLTI = 1184 , PPC_INS_TWNE = 1185 , PPC_INS_TWNEI = 1186 , PPC_INS_TWNG = 1187 , PPC_INS_TWNGI = 1188 , PPC_INS_TWNL = 1189 , PPC_INS_TWNLI = 1190 , PPC_INS_TWU = 1191 , PPC_INS_TWUI = 1192 , PPC_INS_VABSDUB = 1193 , PPC_INS_VABSDUH = 1194 , PPC_INS_VABSDUW = 1195 , PPC_INS_VADDCUQ = 1196 , PPC_INS_VADDCUW = 1197 , PPC_INS_VADDECUQ = 1198 , PPC_INS_VADDEUQM = 1199 , PPC_INS_VADDFP = 1200 , PPC_INS_VADDSBS = 1201 , PPC_INS_VADDSHS = 1202 , PPC_INS_VADDSWS = 1203 , PPC_INS_VADDUBM = 1204 , PPC_INS_VADDUBS = 1205 , PPC_INS_VADDUDM = 1206 , PPC_INS_VADDUHM = 1207 , PPC_INS_VADDUHS = 1208 , PPC_INS_VADDUQM = 1209 , PPC_INS_VADDUWM = 1210 , PPC_INS_VADDUWS = 1211 , PPC_INS_VAND = 1212 , PPC_INS_VANDC = 1213 , PPC_INS_VAVGSB = 1214 , PPC_INS_VAVGSH = 1215 , PPC_INS_VAVGSW = 1216 , PPC_INS_VAVGUB = 1217 , PPC_INS_VAVGUH = 1218 , PPC_INS_VAVGUW = 1219 , PPC_INS_VBPERMD = 1220 , PPC_INS_VBPERMQ = 1221 , PPC_INS_VCFSX = 1222 , PPC_INS_VCFUX = 1223 , PPC_INS_VCIPHER = 1224 , PPC_INS_VCIPHERLAST = 1225 , PPC_INS_VCLZB = 1226 , PPC_INS_VCLZD = 1227 , PPC_INS_VCLZH = 1228 , PPC_INS_VCLZLSBB = 1229 , PPC_INS_VCLZW = 1230 , PPC_INS_VCMPBFP = 1231 , PPC_INS_VCMPEQFP = 1232 , PPC_INS_VCMPEQUB = 1233 , PPC_INS_VCMPEQUD = 1234 , PPC_INS_VCMPEQUH = 1235 , PPC_INS_VCMPEQUW = 1236 , PPC_INS_VCMPGEFP = 1237 , PPC_INS_VCMPGTFP = 1238 , PPC_INS_VCMPGTSB = 1239 , PPC_INS_VCMPGTSD = 1240 , PPC_INS_VCMPGTSH = 1241 , PPC_INS_VCMPGTSW = 1242 , PPC_INS_VCMPGTUB = 1243 , PPC_INS_VCMPGTUD = 1244 , PPC_INS_VCMPGTUH = 1245 , PPC_INS_VCMPGTUW = 1246 , PPC_INS_VCMPNEB = 1247 , PPC_INS_VCMPNEH = 1248 , PPC_INS_VCMPNEW = 1249 , PPC_INS_VCMPNEZB = 1250 , PPC_INS_VCMPNEZH = 1251 , PPC_INS_VCMPNEZW = 1252 , PPC_INS_VCTSXS = 1253 , PPC_INS_VCTUXS = 1254 , PPC_INS_VCTZB = 1255 , PPC_INS_VCTZD = 1256 , PPC_INS_VCTZH = 1257 , PPC_INS_VCTZLSBB = 1258 , PPC_INS_VCTZW = 1259 , PPC_INS_VEQV = 1260 , PPC_INS_VEXPTEFP = 1261 , PPC_INS_VEXTRACTD = 1262 , PPC_INS_VEXTRACTUB = 1263 , PPC_INS_VEXTRACTUH = 1264 , PPC_INS_VEXTRACTUW = 1265 , PPC_INS_VEXTSB2D = 1266 , PPC_INS_VEXTSB2W = 1267 , PPC_INS_VEXTSH2D = 1268 , PPC_INS_VEXTSH2W = 1269 , PPC_INS_VEXTSW2D = 1270 , PPC_INS_VEXTUBLX = 1271 , PPC_INS_VEXTUBRX = 1272 , PPC_INS_VEXTUHLX = 1273 , PPC_INS_VEXTUHRX = 1274 , PPC_INS_VEXTUWLX = 1275 , PPC_INS_VEXTUWRX = 1276 , PPC_INS_VGBBD = 1277 , PPC_INS_VINSERTB = 1278 , PPC_INS_VINSERTD = 1279 , PPC_INS_VINSERTH = 1280 , PPC_INS_VINSERTW = 1281 , PPC_INS_VLOGEFP = 1282 , PPC_INS_VMADDFP = 1283 , PPC_INS_VMAXFP = 1284 , PPC_INS_VMAXSB = 1285 , PPC_INS_VMAXSD = 1286 , PPC_INS_VMAXSH = 1287 , PPC_INS_VMAXSW = 1288 , PPC_INS_VMAXUB = 1289 , PPC_INS_VMAXUD = 1290 , PPC_INS_VMAXUH = 1291 , PPC_INS_VMAXUW = 1292 , PPC_INS_VMHADDSHS = 1293 , PPC_INS_VMHRADDSHS = 1294 , PPC_INS_VMINFP = 1295 , PPC_INS_VMINSB = 1296 , PPC_INS_VMINSD = 1297 , PPC_INS_VMINSH = 1298 , PPC_INS_VMINSW = 1299 , PPC_INS_VMINUB = 1300 , PPC_INS_VMINUD = 1301 , PPC_INS_VMINUH = 1302 , PPC_INS_VMINUW = 1303 , PPC_INS_VMLADDUHM = 1304 , PPC_INS_VMR = 1305 , PPC_INS_VMRGEW = 1306 , PPC_INS_VMRGHB = 1307 , PPC_INS_VMRGHH = 1308 , PPC_INS_VMRGHW = 1309 , PPC_INS_VMRGLB = 1310 , PPC_INS_VMRGLH = 1311 , PPC_INS_VMRGLW = 1312 , PPC_INS_VMRGOW = 1313 , PPC_INS_VMSUMMBM = 1314 , PPC_INS_VMSUMSHM = 1315 , PPC_INS_VMSUMSHS = 1316 , PPC_INS_VMSUMUBM = 1317 , PPC_INS_VMSUMUHM = 1318 , PPC_INS_VMSUMUHS = 1319 , PPC_INS_VMUL10CUQ = 1320 , PPC_INS_VMUL10ECUQ = 1321 , PPC_INS_VMUL10EUQ = 1322 , PPC_INS_VMUL10UQ = 1323 , PPC_INS_VMULESB = 1324 , PPC_INS_VMULESH = 1325 , PPC_INS_VMULESW = 1326 , PPC_INS_VMULEUB = 1327 , PPC_INS_VMULEUH = 1328 , PPC_INS_VMULEUW = 1329 , PPC_INS_VMULOSB = 1330 , PPC_INS_VMULOSH = 1331 , PPC_INS_VMULOSW = 1332 , PPC_INS_VMULOUB = 1333 , PPC_INS_VMULOUH = 1334 , PPC_INS_VMULOUW = 1335 , PPC_INS_VMULUWM = 1336 , PPC_INS_VNAND = 1337 , PPC_INS_VNCIPHER = 1338 , PPC_INS_VNCIPHERLAST = 1339 , PPC_INS_VNEGD = 1340 , PPC_INS_VNEGW = 1341 , PPC_INS_VNMSUBFP = 1342 , PPC_INS_VNOR = 1343 , PPC_INS_VNOT = 1344 , PPC_INS_VOR = 1345 , PPC_INS_VORC = 1346 , PPC_INS_VPERM = 1347 , PPC_INS_VPERMR = 1348 , PPC_INS_VPERMXOR = 1349 , PPC_INS_VPKPX = 1350 , PPC_INS_VPKSDSS = 1351 , PPC_INS_VPKSDUS = 1352 , PPC_INS_VPKSHSS = 1353 , PPC_INS_VPKSHUS = 1354 , PPC_INS_VPKSWSS = 1355 , PPC_INS_VPKSWUS = 1356 , PPC_INS_VPKUDUM = 1357 , PPC_INS_VPKUDUS = 1358 , PPC_INS_VPKUHUM = 1359 , PPC_INS_VPKUHUS = 1360 , PPC_INS_VPKUWUM = 1361 , PPC_INS_VPKUWUS = 1362 , PPC_INS_VPMSUMB = 1363 , PPC_INS_VPMSUMD = 1364 , PPC_INS_VPMSUMH = 1365 , PPC_INS_VPMSUMW = 1366 , PPC_INS_VPOPCNTB = 1367 , PPC_INS_VPOPCNTD = 1368 , PPC_INS_VPOPCNTH = 1369 , PPC_INS_VPOPCNTW = 1370 , PPC_INS_VPRTYBD = 1371 , PPC_INS_VPRTYBQ = 1372 , PPC_INS_VPRTYBW = 1373 , PPC_INS_VREFP = 1374 , PPC_INS_VRFIM = 1375 , PPC_INS_VRFIN = 1376 , PPC_INS_VRFIP = 1377 , PPC_INS_VRFIZ = 1378 , PPC_INS_VRLB = 1379 , PPC_INS_VRLD = 1380 , PPC_INS_VRLDMI = 1381 , PPC_INS_VRLDNM = 1382 , PPC_INS_VRLH = 1383 , PPC_INS_VRLW = 1384 , PPC_INS_VRLWMI = 1385 , PPC_INS_VRLWNM = 1386 , PPC_INS_VRSQRTEFP = 1387 , PPC_INS_VSBOX = 1388 , PPC_INS_VSEL = 1389 , PPC_INS_VSHASIGMAD = 1390 , PPC_INS_VSHASIGMAW = 1391 , PPC_INS_VSL = 1392 , PPC_INS_VSLB = 1393 , PPC_INS_VSLD = 1394 , PPC_INS_VSLDOI = 1395 , PPC_INS_VSLH = 1396 , PPC_INS_VSLO = 1397 , PPC_INS_VSLV = 1398 , PPC_INS_VSLW = 1399 , PPC_INS_VSPLTB = 1400 , PPC_INS_VSPLTH = 1401 , PPC_INS_VSPLTISB = 1402 , PPC_INS_VSPLTISH = 1403 , PPC_INS_VSPLTISW = 1404 , PPC_INS_VSPLTW = 1405 , PPC_INS_VSR = 1406 , PPC_INS_VSRAB = 1407 , PPC_INS_VSRAD = 1408 , PPC_INS_VSRAH = 1409 , PPC_INS_VSRAW = 1410 , PPC_INS_VSRB = 1411 , PPC_INS_VSRD = 1412 , PPC_INS_VSRH = 1413 , PPC_INS_VSRO = 1414 , PPC_INS_VSRV = 1415 , PPC_INS_VSRW = 1416 , PPC_INS_VSUBCUQ = 1417 , PPC_INS_VSUBCUW = 1418 , PPC_INS_VSUBECUQ = 1419 , PPC_INS_VSUBEUQM = 1420 , PPC_INS_VSUBFP = 1421 , PPC_INS_VSUBSBS = 1422 , PPC_INS_VSUBSHS = 1423 , PPC_INS_VSUBSWS = 1424 , PPC_INS_VSUBUBM = 1425 , PPC_INS_VSUBUBS = 1426 , PPC_INS_VSUBUDM = 1427 , PPC_INS_VSUBUHM = 1428 , PPC_INS_VSUBUHS = 1429 , PPC_INS_VSUBUQM = 1430 , PPC_INS_VSUBUWM = 1431 , PPC_INS_VSUBUWS = 1432 , PPC_INS_VSUM2SWS = 1433 , PPC_INS_VSUM4SBS = 1434 , PPC_INS_VSUM4SHS = 1435 , PPC_INS_VSUM4UBS = 1436 , PPC_INS_VSUMSWS = 1437 , PPC_INS_VUPKHPX = 1438 , PPC_INS_VUPKHSB = 1439 , PPC_INS_VUPKHSH = 1440 , PPC_INS_VUPKHSW = 1441 , PPC_INS_VUPKLPX = 1442 , PPC_INS_VUPKLSB = 1443 , PPC_INS_VUPKLSH = 1444 , PPC_INS_VUPKLSW = 1445 , PPC_INS_VXOR = 1446 , PPC_INS_WAIT = 1447 , PPC_INS_WAITIMPL = 1448 , PPC_INS_WAITRSV = 1449 , PPC_INS_WRTEE = 1450 , PPC_INS_WRTEEI = 1451 , PPC_INS_XNOP = 1452 , PPC_INS_XOR = 1453 , PPC_INS_XORI = 1454 , PPC_INS_XORIS = 1455 , PPC_INS_XSABSDP = 1456 , PPC_INS_XSABSQP = 1457 , PPC_INS_XSADDDP = 1458 , PPC_INS_XSADDQP = 1459 , PPC_INS_XSADDQPO = 1460 , PPC_INS_XSADDSP = 1461 , PPC_INS_XSCMPEQDP = 1462 , PPC_INS_XSCMPEXPDP = 1463 , PPC_INS_XSCMPEXPQP = 1464 , PPC_INS_XSCMPGEDP = 1465 , PPC_INS_XSCMPGTDP = 1466 , PPC_INS_XSCMPODP = 1467 , PPC_INS_XSCMPOQP = 1468 , PPC_INS_XSCMPUDP = 1469 , PPC_INS_XSCMPUQP = 1470 , PPC_INS_XSCPSGNDP = 1471 , PPC_INS_XSCPSGNQP = 1472 , PPC_INS_XSCVDPHP = 1473 , PPC_INS_XSCVDPQP = 1474 , PPC_INS_XSCVDPSP = 1475 , PPC_INS_XSCVDPSPN = 1476 , PPC_INS_XSCVDPSXDS = 1477 , PPC_INS_XSCVDPSXWS = 1478 , PPC_INS_XSCVDPUXDS = 1479 , PPC_INS_XSCVDPUXWS = 1480 , PPC_INS_XSCVHPDP = 1481 , PPC_INS_XSCVQPDP = 1482 , PPC_INS_XSCVQPDPO = 1483 , PPC_INS_XSCVQPSDZ = 1484 , PPC_INS_XSCVQPSWZ = 1485 , PPC_INS_XSCVQPUDZ = 1486 , PPC_INS_XSCVQPUWZ = 1487 , PPC_INS_XSCVSDQP = 1488 , PPC_INS_XSCVSPDP = 1489 , PPC_INS_XSCVSPDPN = 1490 , PPC_INS_XSCVSXDDP = 1491 , PPC_INS_XSCVSXDSP = 1492 , PPC_INS_XSCVUDQP = 1493 , PPC_INS_XSCVUXDDP = 1494 , PPC_INS_XSCVUXDSP = 1495 , PPC_INS_XSDIVDP = 1496 , PPC_INS_XSDIVQP = 1497 , PPC_INS_XSDIVQPO = 1498 , PPC_INS_XSDIVSP = 1499 , PPC_INS_XSIEXPDP = 1500 , PPC_INS_XSIEXPQP = 1501 , PPC_INS_XSMADDADP = 1502 , PPC_INS_XSMADDASP = 1503 , PPC_INS_XSMADDMDP = 1504 , PPC_INS_XSMADDMSP = 1505 , PPC_INS_XSMADDQP = 1506 , PPC_INS_XSMADDQPO = 1507 , PPC_INS_XSMAXCDP = 1508 , PPC_INS_XSMAXDP = 1509 , PPC_INS_XSMAXJDP = 1510 , PPC_INS_XSMINCDP = 1511 , PPC_INS_XSMINDP = 1512 , PPC_INS_XSMINJDP = 1513 , PPC_INS_XSMSUBADP = 1514 , PPC_INS_XSMSUBASP = 1515 , PPC_INS_XSMSUBMDP = 1516 , PPC_INS_XSMSUBMSP = 1517 , PPC_INS_XSMSUBQP = 1518 , PPC_INS_XSMSUBQPO = 1519 , PPC_INS_XSMULDP = 1520 , PPC_INS_XSMULQP = 1521 , PPC_INS_XSMULQPO = 1522 , PPC_INS_XSMULSP = 1523 , PPC_INS_XSNABSDP = 1524 , PPC_INS_XSNABSQP = 1525 , PPC_INS_XSNEGDP = 1526 , PPC_INS_XSNEGQP = 1527 , PPC_INS_XSNMADDADP = 1528 , PPC_INS_XSNMADDASP = 1529 , PPC_INS_XSNMADDMDP = 1530 , PPC_INS_XSNMADDMSP = 1531 , PPC_INS_XSNMADDQP = 1532 , PPC_INS_XSNMADDQPO = 1533 , PPC_INS_XSNMSUBADP = 1534 , PPC_INS_XSNMSUBASP = 1535 , PPC_INS_XSNMSUBMDP = 1536 , PPC_INS_XSNMSUBMSP = 1537 , PPC_INS_XSNMSUBQP = 1538 , PPC_INS_XSNMSUBQPO = 1539 , PPC_INS_XSRDPI = 1540 , PPC_INS_XSRDPIC = 1541 , PPC_INS_XSRDPIM = 1542 , PPC_INS_XSRDPIP = 1543 , PPC_INS_XSRDPIZ = 1544 , PPC_INS_XSREDP = 1545 , PPC_INS_XSRESP = 1546 , PPC_INS_XSRQPI = 1547 , PPC_INS_XSRQPIX = 1548 , PPC_INS_XSRQPXP = 1549 , PPC_INS_XSRSP = 1550 , PPC_INS_XSRSQRTEDP = 1551 , PPC_INS_XSRSQRTESP = 1552 , PPC_INS_XSSQRTDP = 1553 , PPC_INS_XSSQRTQP = 1554 , PPC_INS_XSSQRTQPO = 1555 , PPC_INS_XSSQRTSP = 1556 , PPC_INS_XSSUBDP = 1557 , PPC_INS_XSSUBQP = 1558 , PPC_INS_XSSUBQPO = 1559 , PPC_INS_XSSUBSP = 1560 , PPC_INS_XSTDIVDP = 1561 , PPC_INS_XSTSQRTDP = 1562 , PPC_INS_XSTSTDCDP = 1563 , PPC_INS_XSTSTDCQP = 1564 , PPC_INS_XSTSTDCSP = 1565 , PPC_INS_XSXEXPDP = 1566 , PPC_INS_XSXEXPQP = 1567 , PPC_INS_XSXSIGDP = 1568 , PPC_INS_XSXSIGQP = 1569 , PPC_INS_XVABSDP = 1570 , PPC_INS_XVABSSP = 1571 , PPC_INS_XVADDDP = 1572 , PPC_INS_XVADDSP = 1573 , PPC_INS_XVCMPEQDP = 1574 , PPC_INS_XVCMPEQSP = 1575 , PPC_INS_XVCMPGEDP = 1576 , PPC_INS_XVCMPGESP = 1577 , PPC_INS_XVCMPGTDP = 1578 , PPC_INS_XVCMPGTSP = 1579 , PPC_INS_XVCPSGNDP = 1580 , PPC_INS_XVCPSGNSP = 1581 , PPC_INS_XVCVDPSP = 1582 , PPC_INS_XVCVDPSXDS = 1583 , PPC_INS_XVCVDPSXWS = 1584 , PPC_INS_XVCVDPUXDS = 1585 , PPC_INS_XVCVDPUXWS = 1586 , PPC_INS_XVCVHPSP = 1587 , PPC_INS_XVCVSPDP = 1588 , PPC_INS_XVCVSPHP = 1589 , PPC_INS_XVCVSPSXDS = 1590 , PPC_INS_XVCVSPSXWS = 1591 , PPC_INS_XVCVSPUXDS = 1592 , PPC_INS_XVCVSPUXWS = 1593 , PPC_INS_XVCVSXDDP = 1594 , PPC_INS_XVCVSXDSP = 1595 , PPC_INS_XVCVSXWDP = 1596 , PPC_INS_XVCVSXWSP = 1597 , PPC_INS_XVCVUXDDP = 1598 , PPC_INS_XVCVUXDSP = 1599 , PPC_INS_XVCVUXWDP = 1600 , PPC_INS_XVCVUXWSP = 1601 , PPC_INS_XVDIVDP = 1602 , PPC_INS_XVDIVSP = 1603 , PPC_INS_XVIEXPDP = 1604 , PPC_INS_XVIEXPSP = 1605 , PPC_INS_XVMADDADP = 1606 , PPC_INS_XVMADDASP = 1607 , PPC_INS_XVMADDMDP = 1608 , PPC_INS_XVMADDMSP = 1609 , PPC_INS_XVMAXDP = 1610 , PPC_INS_XVMAXSP = 1611 , PPC_INS_XVMINDP = 1612 , PPC_INS_XVMINSP = 1613 , PPC_INS_XVMOVDP = 1614 , PPC_INS_XVMOVSP = 1615 , PPC_INS_XVMSUBADP = 1616 , PPC_INS_XVMSUBASP = 1617 , PPC_INS_XVMSUBMDP = 1618 , PPC_INS_XVMSUBMSP = 1619 , PPC_INS_XVMULDP = 1620 , PPC_INS_XVMULSP = 1621 , PPC_INS_XVNABSDP = 1622 , PPC_INS_XVNABSSP = 1623 , PPC_INS_XVNEGDP = 1624 , PPC_INS_XVNEGSP = 1625 , PPC_INS_XVNMADDADP = 1626 , PPC_INS_XVNMADDASP = 1627 , PPC_INS_XVNMADDMDP = 1628 , PPC_INS_XVNMADDMSP = 1629 , PPC_INS_XVNMSUBADP = 1630 , PPC_INS_XVNMSUBASP = 1631 , PPC_INS_XVNMSUBMDP = 1632 , PPC_INS_XVNMSUBMSP = 1633 , PPC_INS_XVRDPI = 1634 , PPC_INS_XVRDPIC = 1635 , PPC_INS_XVRDPIM = 1636 , PPC_INS_XVRDPIP = 1637 , PPC_INS_XVRDPIZ = 1638 , PPC_INS_XVREDP = 1639 , PPC_INS_XVRESP = 1640 , PPC_INS_XVRSPI = 1641 , PPC_INS_XVRSPIC = 1642 , PPC_INS_XVRSPIM = 1643 , PPC_INS_XVRSPIP = 1644 , PPC_INS_XVRSPIZ = 1645 , PPC_INS_XVRSQRTEDP = 1646 , PPC_INS_XVRSQRTESP = 1647 , PPC_INS_XVSQRTDP = 1648 , PPC_INS_XVSQRTSP = 1649 , PPC_INS_XVSUBDP = 1650 , PPC_INS_XVSUBSP = 1651 , PPC_INS_XVTDIVDP = 1652 , PPC_INS_XVTDIVSP = 1653 , PPC_INS_XVTSQRTDP = 1654 , PPC_INS_XVTSQRTSP = 1655 , PPC_INS_XVTSTDCDP = 1656 , PPC_INS_XVTSTDCSP = 1657 , PPC_INS_XVXEXPDP = 1658 , PPC_INS_XVXEXPSP = 1659 , PPC_INS_XVXSIGDP = 1660 , PPC_INS_XVXSIGSP = 1661 , PPC_INS_XXBRD = 1662 , PPC_INS_XXBRH = 1663 , PPC_INS_XXBRQ = 1664 , PPC_INS_XXBRW = 1665 , PPC_INS_XXEXTRACTUW = 1666 , PPC_INS_XXINSERTW = 1667 , PPC_INS_XXLAND = 1668 , PPC_INS_XXLANDC = 1669 , PPC_INS_XXLEQV = 1670 , PPC_INS_XXLNAND = 1671 , PPC_INS_XXLNOR = 1672 , PPC_INS_XXLOR = 1673 , PPC_INS_XXLORC = 1674 , PPC_INS_XXLXOR = 1675 , PPC_INS_XXMRGHD = 1676 , PPC_INS_XXMRGHW = 1677 , PPC_INS_XXMRGLD = 1678 , PPC_INS_XXMRGLW = 1679 , PPC_INS_XXPERM = 1680 , PPC_INS_XXPERMDI = 1681 , PPC_INS_XXPERMR = 1682 , PPC_INS_XXSEL = 1683 , PPC_INS_XXSLDWI = 1684 , PPC_INS_XXSPLTD = 1685 , PPC_INS_XXSPLTIB = 1686 , PPC_INS_XXSPLTW = 1687 , PPC_INS_XXSWAPD = 1688 , PPC_INS_DCBZ_L = 1689 , PPC_INS_PSQ_L = 1690 , PPC_INS_PSQ_LU = 1691 , PPC_INS_PSQ_LUX = 1692 , PPC_INS_PSQ_LX = 1693 , PPC_INS_PSQ_ST = 1694 , PPC_INS_PSQ_STU = 1695 , PPC_INS_PSQ_STUX = 1696 , PPC_INS_PSQ_STX = 1697 , PPC_INS_PS_ABS = 1698 , PPC_INS_PS_ADD = 1699 , PPC_INS_PS_CMPO0 = 1700 , PPC_INS_PS_CMPO1 = 1701 , PPC_INS_PS_CMPU0 = 1702 , PPC_INS_PS_CMPU1 = 1703 , PPC_INS_PS_DIV = 1704 , PPC_INS_PS_MADD = 1705 , PPC_INS_PS_MADDS0 = 1706 , PPC_INS_PS_MADDS1 = 1707 , PPC_INS_PS_MERGE00 = 1708 , PPC_INS_PS_MERGE01 = 1709 , PPC_INS_PS_MERGE10 = 1710 , PPC_INS_PS_MERGE11 = 1711 , PPC_INS_PS_MR = 1712 , PPC_INS_PS_MSUB = 1713 , PPC_INS_PS_MUL = 1714 , PPC_INS_PS_MULS0 = 1715 , PPC_INS_PS_MULS1 = 1716 , PPC_INS_PS_NABS = 1717 , PPC_INS_PS_NEG = 1718 , PPC_INS_PS_NMADD = 1719 , PPC_INS_PS_NMSUB = 1720 , PPC_INS_PS_RES = 1721 , PPC_INS_PS_RSQRTE = 1722 , PPC_INS_PS_SEL = 1723 , PPC_INS_PS_SUB = 1724 , PPC_INS_PS_SUM0 = 1725 , PPC_INS_PS_SUM1 = 1726 , PPC_INS_ENDING = 1727 , } # [repr (u32)] # [doc = " Group of PPC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn_group { # [doc = "< = CS_GRP_INVALID"] PPC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] PPC_GRP_JUMP = 1 , PPC_GRP_ALTIVEC = 128 , PPC_GRP_MODE32 = 129 , PPC_GRP_MODE64 = 130 , PPC_GRP_BOOKE = 131 , PPC_GRP_NOTBOOKE = 132 , PPC_GRP_SPE = 133 , PPC_GRP_VSX = 134 , PPC_GRP_E500 = 135 , PPC_GRP_PPC4XX = 136 , PPC_GRP_PPC6XX = 137 , PPC_GRP_ICBT = 138 , PPC_GRP_P8ALTIVEC = 139 , PPC_GRP_P8VECTOR = 140 , PPC_GRP_QPX = 141 , PPC_GRP_PS = 142 , PPC_GRP_ENDING = 143 , } # [repr (u32)] # [doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_cc { # [doc = "< invalid CC (default)"] SPARC_CC_INVALID = 0 , # [doc = "< Always"] SPARC_CC_ICC_A = 264 , # [doc = "< Never"] SPARC_CC_ICC_N = 256 , # [doc = "< Not Equal"] SPARC_CC_ICC_NE = 265 , # [doc = "< Equal"] SPARC_CC_ICC_E = 257 , # [doc = "< Greater"] SPARC_CC_ICC_G = 266 , # [doc = "< Less or Equal"] SPARC_CC_ICC_LE = 258 , # [doc = "< Greater or Equal"] SPARC_CC_ICC_GE = 267 , # [doc = "< Less"] SPARC_CC_ICC_L = 259 , # [doc = "< Greater Unsigned"] SPARC_CC_ICC_GU = 268 , # [doc = "< Less or Equal Unsigned"] SPARC_CC_ICC_LEU = 260 , # [doc = "< Carry Clear/Great or Equal Unsigned"] SPARC_CC_ICC_CC = 269 , # [doc = "< Carry Set/Less Unsigned"] SPARC_CC_ICC_CS = 261 , # [doc = "< Positive"] SPARC_CC_ICC_POS = 270 , # [doc = "< Negative"] SPARC_CC_ICC_NEG = 262 , # [doc = "< Overflow Clear"] SPARC_CC_ICC_VC = 271 , # [doc = "< Overflow Set"] SPARC_CC_ICC_VS = 263 , # [doc = "< Always"] SPARC_CC_FCC_A = 280 , # [doc = "< Never"] SPARC_CC_FCC_N = 272 , # [doc = "< Unordered"] SPARC_CC_FCC_U = 279 , # [doc = "< Greater"] SPARC_CC_FCC_G = 278 , # [doc = "< Unordered or Greater"] SPARC_CC_FCC_UG = 277 , # [doc = "< Less"] SPARC_CC_FCC_L = 276 , # [doc = "< Unordered or Less"] SPARC_CC_FCC_UL = 275 , # [doc = "< Less or Greater"] SPARC_CC_FCC_LG = 274 , # [doc = "< Not Equal"] SPARC_CC_FCC_NE = 273 , # [doc = "< Equal"] SPARC_CC_FCC_E = 281 , # [doc = "< Unordered or Equal"] SPARC_CC_FCC_UE = 282 , # [doc = "< Greater or Equal"] SPARC_CC_FCC_GE = 283 , # [doc = "< Unordered or Greater or Equal"] SPARC_CC_FCC_UGE = 284 , # [doc = "< Less or Equal"] SPARC_CC_FCC_LE = 285 , # [doc = "< Unordered or Less or Equal"] SPARC_CC_FCC_ULE = 286 , # [doc = "< Ordered"] SPARC_CC_FCC_O = 287 , } # [repr (u32)] # [doc = " Branch hint"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_hint { # [doc = "< no hint"] SPARC_HINT_INVALID = 0 , # [doc = "< annul delay slot instruction"] SPARC_HINT_A = 1 , # [doc = "< branch taken"] SPARC_HINT_PT = 2 , # [doc = "< branch NOT taken"] SPARC_HINT_PN = 4 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SPARC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SPARC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SPARC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SPARC_OP_MEM = 3 , } impl sparc_reg { pub const SPARC_REG_O6 : sparc_reg = sparc_reg :: SPARC_REG_SP ; } impl sparc_reg { pub const SPARC_REG_I6 : sparc_reg = sparc_reg :: SPARC_REG_FP ; } # [repr (u32)] # [doc = " SPARC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_reg { SPARC_REG_INVALID = 0 , SPARC_REG_F0 = 1 , SPARC_REG_F1 = 2 , SPARC_REG_F2 = 3 , SPARC_REG_F3 = 4 , SPARC_REG_F4 = 5 , SPARC_REG_F5 = 6 , SPARC_REG_F6 = 7 , SPARC_REG_F7 = 8 , SPARC_REG_F8 = 9 , SPARC_REG_F9 = 10 , SPARC_REG_F10 = 11 , SPARC_REG_F11 = 12 , SPARC_REG_F12 = 13 , SPARC_REG_F13 = 14 , SPARC_REG_F14 = 15 , SPARC_REG_F15 = 16 , SPARC_REG_F16 = 17 , SPARC_REG_F17 = 18 , SPARC_REG_F18 = 19 , SPARC_REG_F19 = 20 , SPARC_REG_F20 = 21 , SPARC_REG_F21 = 22 , SPARC_REG_F22 = 23 , SPARC_REG_F23 = 24 , SPARC_REG_F24 = 25 , SPARC_REG_F25 = 26 , SPARC_REG_F26 = 27 , SPARC_REG_F27 = 28 , SPARC_REG_F28 = 29 , SPARC_REG_F29 = 30 , SPARC_REG_F30 = 31 , SPARC_REG_F31 = 32 , SPARC_REG_F32 = 33 , SPARC_REG_F34 = 34 , SPARC_REG_F36 = 35 , SPARC_REG_F38 = 36 , SPARC_REG_F40 = 37 , SPARC_REG_F42 = 38 , SPARC_REG_F44 = 39 , SPARC_REG_F46 = 40 , SPARC_REG_F48 = 41 , SPARC_REG_F50 = 42 , SPARC_REG_F52 = 43 , SPARC_REG_F54 = 44 , SPARC_REG_F56 = 45 , SPARC_REG_F58 = 46 , SPARC_REG_F60 = 47 , SPARC_REG_F62 = 48 , SPARC_REG_FCC0 = 49 , SPARC_REG_FCC1 = 50 , SPARC_REG_FCC2 = 51 , SPARC_REG_FCC3 = 52 , SPARC_REG_FP = 53 , SPARC_REG_G0 = 54 , SPARC_REG_G1 = 55 , SPARC_REG_G2 = 56 , SPARC_REG_G3 = 57 , SPARC_REG_G4 = 58 , SPARC_REG_G5 = 59 , SPARC_REG_G6 = 60 , SPARC_REG_G7 = 61 , SPARC_REG_I0 = 62 , SPARC_REG_I1 = 63 , SPARC_REG_I2 = 64 , SPARC_REG_I3 = 65 , SPARC_REG_I4 = 66 , SPARC_REG_I5 = 67 , SPARC_REG_I7 = 68 , SPARC_REG_ICC = 69 , SPARC_REG_L0 = 70 , SPARC_REG_L1 = 71 , SPARC_REG_L2 = 72 , SPARC_REG_L3 = 73 , SPARC_REG_L4 = 74 , SPARC_REG_L5 = 75 , SPARC_REG_L6 = 76 , SPARC_REG_L7 = 77 , SPARC_REG_O0 = 78 , SPARC_REG_O1 = 79 , SPARC_REG_O2 = 80 , SPARC_REG_O3 = 81 , SPARC_REG_O4 = 82 , SPARC_REG_O5 = 83 , SPARC_REG_O7 = 84 , SPARC_REG_SP = 85 , SPARC_REG_Y = 86 , SPARC_REG_XCC = 87 , SPARC_REG_ENDING = 88 , } # [doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sparc_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sparc_op_mem"] [:: std :: mem :: size_of :: < sparc_op_mem > () - 8usize] ; ["Alignment of sparc_op_mem"] [:: std :: mem :: align_of :: < sparc_op_mem > () - 4usize] ; ["Offset of field: sparc_op_mem::base"] [:: std :: mem :: offset_of ! (sparc_op_mem , base) - 0usize] ; ["Offset of field: sparc_op_mem::index"] [:: std :: mem :: offset_of ! (sparc_op_mem , index) - 1usize] ; ["Offset of field: sparc_op_mem::disp"] [:: std :: mem :: offset_of ! (sparc_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc_op { # [doc = "< operand type"] pub type_ : sparc_op_type , pub __bindgen_anon_1 : cs_sparc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sparc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sparc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sparc_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op"] [:: std :: mem :: size_of :: < cs_sparc_op > () - 16usize] ; ["Alignment of cs_sparc_op"] [:: std :: mem :: align_of :: < cs_sparc_op > () - 8usize] ; ["Offset of field: cs_sparc_op::type_"] [:: std :: mem :: offset_of ! (cs_sparc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc { # [doc = "< code condition for this insn"] pub cc : sparc_cc , # [doc = "< branch hint: encoding as bitwise OR of sparc_hint."] pub hint : sparc_hint , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sparc_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc"] [:: std :: mem :: size_of :: < cs_sparc > () - 80usize] ; ["Alignment of cs_sparc"] [:: std :: mem :: align_of :: < cs_sparc > () - 8usize] ; ["Offset of field: cs_sparc::cc"] [:: std :: mem :: offset_of ! (cs_sparc , cc) - 0usize] ; ["Offset of field: cs_sparc::hint"] [:: std :: mem :: offset_of ! (cs_sparc , hint) - 4usize] ; ["Offset of field: cs_sparc::op_count"] [:: std :: mem :: offset_of ! (cs_sparc , op_count) - 8usize] ; ["Offset of field: cs_sparc::operands"] [:: std :: mem :: offset_of ! (cs_sparc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . hint , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SPARC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn { SPARC_INS_INVALID = 0 , SPARC_INS_ADDCC = 1 , SPARC_INS_ADDX = 2 , SPARC_INS_ADDXCC = 3 , SPARC_INS_ADDXC = 4 , SPARC_INS_ADDXCCC = 5 , SPARC_INS_ADD = 6 , SPARC_INS_ALIGNADDR = 7 , SPARC_INS_ALIGNADDRL = 8 , SPARC_INS_ANDCC = 9 , SPARC_INS_ANDNCC = 10 , SPARC_INS_ANDN = 11 , SPARC_INS_AND = 12 , SPARC_INS_ARRAY16 = 13 , SPARC_INS_ARRAY32 = 14 , SPARC_INS_ARRAY8 = 15 , SPARC_INS_B = 16 , SPARC_INS_JMP = 17 , SPARC_INS_BMASK = 18 , SPARC_INS_FB = 19 , SPARC_INS_BRGEZ = 20 , SPARC_INS_BRGZ = 21 , SPARC_INS_BRLEZ = 22 , SPARC_INS_BRLZ = 23 , SPARC_INS_BRNZ = 24 , SPARC_INS_BRZ = 25 , SPARC_INS_BSHUFFLE = 26 , SPARC_INS_CALL = 27 , SPARC_INS_CASX = 28 , SPARC_INS_CAS = 29 , SPARC_INS_CMASK16 = 30 , SPARC_INS_CMASK32 = 31 , SPARC_INS_CMASK8 = 32 , SPARC_INS_CMP = 33 , SPARC_INS_EDGE16 = 34 , SPARC_INS_EDGE16L = 35 , SPARC_INS_EDGE16LN = 36 , SPARC_INS_EDGE16N = 37 , SPARC_INS_EDGE32 = 38 , SPARC_INS_EDGE32L = 39 , SPARC_INS_EDGE32LN = 40 , SPARC_INS_EDGE32N = 41 , SPARC_INS_EDGE8 = 42 , SPARC_INS_EDGE8L = 43 , SPARC_INS_EDGE8LN = 44 , SPARC_INS_EDGE8N = 45 , SPARC_INS_FABSD = 46 , SPARC_INS_FABSQ = 47 , SPARC_INS_FABSS = 48 , SPARC_INS_FADDD = 49 , SPARC_INS_FADDQ = 50 , SPARC_INS_FADDS = 51 , SPARC_INS_FALIGNDATA = 52 , SPARC_INS_FAND = 53 , SPARC_INS_FANDNOT1 = 54 , SPARC_INS_FANDNOT1S = 55 , SPARC_INS_FANDNOT2 = 56 , SPARC_INS_FANDNOT2S = 57 , SPARC_INS_FANDS = 58 , SPARC_INS_FCHKSM16 = 59 , SPARC_INS_FCMPD = 60 , SPARC_INS_FCMPEQ16 = 61 , SPARC_INS_FCMPEQ32 = 62 , SPARC_INS_FCMPGT16 = 63 , SPARC_INS_FCMPGT32 = 64 , SPARC_INS_FCMPLE16 = 65 , SPARC_INS_FCMPLE32 = 66 , SPARC_INS_FCMPNE16 = 67 , SPARC_INS_FCMPNE32 = 68 , SPARC_INS_FCMPQ = 69 , SPARC_INS_FCMPS = 70 , SPARC_INS_FDIVD = 71 , SPARC_INS_FDIVQ = 72 , SPARC_INS_FDIVS = 73 , SPARC_INS_FDMULQ = 74 , SPARC_INS_FDTOI = 75 , SPARC_INS_FDTOQ = 76 , SPARC_INS_FDTOS = 77 , SPARC_INS_FDTOX = 78 , SPARC_INS_FEXPAND = 79 , SPARC_INS_FHADDD = 80 , SPARC_INS_FHADDS = 81 , SPARC_INS_FHSUBD = 82 , SPARC_INS_FHSUBS = 83 , SPARC_INS_FITOD = 84 , SPARC_INS_FITOQ = 85 , SPARC_INS_FITOS = 86 , SPARC_INS_FLCMPD = 87 , SPARC_INS_FLCMPS = 88 , SPARC_INS_FLUSHW = 89 , SPARC_INS_FMEAN16 = 90 , SPARC_INS_FMOVD = 91 , SPARC_INS_FMOVQ = 92 , SPARC_INS_FMOVRDGEZ = 93 , SPARC_INS_FMOVRQGEZ = 94 , SPARC_INS_FMOVRSGEZ = 95 , SPARC_INS_FMOVRDGZ = 96 , SPARC_INS_FMOVRQGZ = 97 , SPARC_INS_FMOVRSGZ = 98 , SPARC_INS_FMOVRDLEZ = 99 , SPARC_INS_FMOVRQLEZ = 100 , SPARC_INS_FMOVRSLEZ = 101 , SPARC_INS_FMOVRDLZ = 102 , SPARC_INS_FMOVRQLZ = 103 , SPARC_INS_FMOVRSLZ = 104 , SPARC_INS_FMOVRDNZ = 105 , SPARC_INS_FMOVRQNZ = 106 , SPARC_INS_FMOVRSNZ = 107 , SPARC_INS_FMOVRDZ = 108 , SPARC_INS_FMOVRQZ = 109 , SPARC_INS_FMOVRSZ = 110 , SPARC_INS_FMOVS = 111 , SPARC_INS_FMUL8SUX16 = 112 , SPARC_INS_FMUL8ULX16 = 113 , SPARC_INS_FMUL8X16 = 114 , SPARC_INS_FMUL8X16AL = 115 , SPARC_INS_FMUL8X16AU = 116 , SPARC_INS_FMULD = 117 , SPARC_INS_FMULD8SUX16 = 118 , SPARC_INS_FMULD8ULX16 = 119 , SPARC_INS_FMULQ = 120 , SPARC_INS_FMULS = 121 , SPARC_INS_FNADDD = 122 , SPARC_INS_FNADDS = 123 , SPARC_INS_FNAND = 124 , SPARC_INS_FNANDS = 125 , SPARC_INS_FNEGD = 126 , SPARC_INS_FNEGQ = 127 , SPARC_INS_FNEGS = 128 , SPARC_INS_FNHADDD = 129 , SPARC_INS_FNHADDS = 130 , SPARC_INS_FNOR = 131 , SPARC_INS_FNORS = 132 , SPARC_INS_FNOT1 = 133 , SPARC_INS_FNOT1S = 134 , SPARC_INS_FNOT2 = 135 , SPARC_INS_FNOT2S = 136 , SPARC_INS_FONE = 137 , SPARC_INS_FONES = 138 , SPARC_INS_FOR = 139 , SPARC_INS_FORNOT1 = 140 , SPARC_INS_FORNOT1S = 141 , SPARC_INS_FORNOT2 = 142 , SPARC_INS_FORNOT2S = 143 , SPARC_INS_FORS = 144 , SPARC_INS_FPACK16 = 145 , SPARC_INS_FPACK32 = 146 , SPARC_INS_FPACKFIX = 147 , SPARC_INS_FPADD16 = 148 , SPARC_INS_FPADD16S = 149 , SPARC_INS_FPADD32 = 150 , SPARC_INS_FPADD32S = 151 , SPARC_INS_FPADD64 = 152 , SPARC_INS_FPMERGE = 153 , SPARC_INS_FPSUB16 = 154 , SPARC_INS_FPSUB16S = 155 , SPARC_INS_FPSUB32 = 156 , SPARC_INS_FPSUB32S = 157 , SPARC_INS_FQTOD = 158 , SPARC_INS_FQTOI = 159 , SPARC_INS_FQTOS = 160 , SPARC_INS_FQTOX = 161 , SPARC_INS_FSLAS16 = 162 , SPARC_INS_FSLAS32 = 163 , SPARC_INS_FSLL16 = 164 , SPARC_INS_FSLL32 = 165 , SPARC_INS_FSMULD = 166 , SPARC_INS_FSQRTD = 167 , SPARC_INS_FSQRTQ = 168 , SPARC_INS_FSQRTS = 169 , SPARC_INS_FSRA16 = 170 , SPARC_INS_FSRA32 = 171 , SPARC_INS_FSRC1 = 172 , SPARC_INS_FSRC1S = 173 , SPARC_INS_FSRC2 = 174 , SPARC_INS_FSRC2S = 175 , SPARC_INS_FSRL16 = 176 , SPARC_INS_FSRL32 = 177 , SPARC_INS_FSTOD = 178 , SPARC_INS_FSTOI = 179 , SPARC_INS_FSTOQ = 180 , SPARC_INS_FSTOX = 181 , SPARC_INS_FSUBD = 182 , SPARC_INS_FSUBQ = 183 , SPARC_INS_FSUBS = 184 , SPARC_INS_FXNOR = 185 , SPARC_INS_FXNORS = 186 , SPARC_INS_FXOR = 187 , SPARC_INS_FXORS = 188 , SPARC_INS_FXTOD = 189 , SPARC_INS_FXTOQ = 190 , SPARC_INS_FXTOS = 191 , SPARC_INS_FZERO = 192 , SPARC_INS_FZEROS = 193 , SPARC_INS_JMPL = 194 , SPARC_INS_LDD = 195 , SPARC_INS_LD = 196 , SPARC_INS_LDQ = 197 , SPARC_INS_LDSB = 198 , SPARC_INS_LDSH = 199 , SPARC_INS_LDSW = 200 , SPARC_INS_LDUB = 201 , SPARC_INS_LDUH = 202 , SPARC_INS_LDX = 203 , SPARC_INS_LZCNT = 204 , SPARC_INS_MEMBAR = 205 , SPARC_INS_MOVDTOX = 206 , SPARC_INS_MOV = 207 , SPARC_INS_MOVRGEZ = 208 , SPARC_INS_MOVRGZ = 209 , SPARC_INS_MOVRLEZ = 210 , SPARC_INS_MOVRLZ = 211 , SPARC_INS_MOVRNZ = 212 , SPARC_INS_MOVRZ = 213 , SPARC_INS_MOVSTOSW = 214 , SPARC_INS_MOVSTOUW = 215 , SPARC_INS_MULX = 216 , SPARC_INS_NOP = 217 , SPARC_INS_ORCC = 218 , SPARC_INS_ORNCC = 219 , SPARC_INS_ORN = 220 , SPARC_INS_OR = 221 , SPARC_INS_PDIST = 222 , SPARC_INS_PDISTN = 223 , SPARC_INS_POPC = 224 , SPARC_INS_RD = 225 , SPARC_INS_RESTORE = 226 , SPARC_INS_RETT = 227 , SPARC_INS_SAVE = 228 , SPARC_INS_SDIVCC = 229 , SPARC_INS_SDIVX = 230 , SPARC_INS_SDIV = 231 , SPARC_INS_SETHI = 232 , SPARC_INS_SHUTDOWN = 233 , SPARC_INS_SIAM = 234 , SPARC_INS_SLLX = 235 , SPARC_INS_SLL = 236 , SPARC_INS_SMULCC = 237 , SPARC_INS_SMUL = 238 , SPARC_INS_SRAX = 239 , SPARC_INS_SRA = 240 , SPARC_INS_SRLX = 241 , SPARC_INS_SRL = 242 , SPARC_INS_STBAR = 243 , SPARC_INS_STB = 244 , SPARC_INS_STD = 245 , SPARC_INS_ST = 246 , SPARC_INS_STH = 247 , SPARC_INS_STQ = 248 , SPARC_INS_STX = 249 , SPARC_INS_SUBCC = 250 , SPARC_INS_SUBX = 251 , SPARC_INS_SUBXCC = 252 , SPARC_INS_SUB = 253 , SPARC_INS_SWAP = 254 , SPARC_INS_TADDCCTV = 255 , SPARC_INS_TADDCC = 256 , SPARC_INS_T = 257 , SPARC_INS_TSUBCCTV = 258 , SPARC_INS_TSUBCC = 259 , SPARC_INS_UDIVCC = 260 , SPARC_INS_UDIVX = 261 , SPARC_INS_UDIV = 262 , SPARC_INS_UMULCC = 263 , SPARC_INS_UMULXHI = 264 , SPARC_INS_UMUL = 265 , SPARC_INS_UNIMP = 266 , SPARC_INS_FCMPED = 267 , SPARC_INS_FCMPEQ = 268 , SPARC_INS_FCMPES = 269 , SPARC_INS_WR = 270 , SPARC_INS_XMULX = 271 , SPARC_INS_XMULXHI = 272 , SPARC_INS_XNORCC = 273 , SPARC_INS_XNOR = 274 , SPARC_INS_XORCC = 275 , SPARC_INS_XOR = 276 , SPARC_INS_RET = 277 , SPARC_INS_RETL = 278 , SPARC_INS_ENDING = 279 , } # [repr (u32)] # [doc = " Group of SPARC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn_group { # [doc = "< = CS_GRP_INVALID"] SPARC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SPARC_GRP_JUMP = 1 , SPARC_GRP_HARDQUAD = 128 , SPARC_GRP_V9 = 129 , SPARC_GRP_VIS = 130 , SPARC_GRP_VIS2 = 131 , SPARC_GRP_VIS3 = 132 , SPARC_GRP_32BIT = 133 , SPARC_GRP_64BIT = 134 , SPARC_GRP_ENDING = 135 , } # [repr (u32)] # [doc = " Enums corresponding to SystemZ condition codes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_cc { # [doc = "< invalid CC (default)"] SYSZ_CC_INVALID = 0 , SYSZ_CC_O = 1 , SYSZ_CC_H = 2 , SYSZ_CC_NLE = 3 , SYSZ_CC_L = 4 , SYSZ_CC_NHE = 5 , SYSZ_CC_LH = 6 , SYSZ_CC_NE = 7 , SYSZ_CC_E = 8 , SYSZ_CC_NLH = 9 , SYSZ_CC_HE = 10 , SYSZ_CC_NL = 11 , SYSZ_CC_LE = 12 , SYSZ_CC_NH = 13 , SYSZ_CC_NO = 14 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SYSZ_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SYSZ_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SYSZ_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SYSZ_OP_MEM = 3 , # [doc = "< Access register operand."] SYSZ_OP_ACREG = 64 , } # [repr (u32)] # [doc = " SystemZ registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_reg { SYSZ_REG_INVALID = 0 , SYSZ_REG_0 = 1 , SYSZ_REG_1 = 2 , SYSZ_REG_2 = 3 , SYSZ_REG_3 = 4 , SYSZ_REG_4 = 5 , SYSZ_REG_5 = 6 , SYSZ_REG_6 = 7 , SYSZ_REG_7 = 8 , SYSZ_REG_8 = 9 , SYSZ_REG_9 = 10 , SYSZ_REG_10 = 11 , SYSZ_REG_11 = 12 , SYSZ_REG_12 = 13 , SYSZ_REG_13 = 14 , SYSZ_REG_14 = 15 , SYSZ_REG_15 = 16 , SYSZ_REG_CC = 17 , SYSZ_REG_F0 = 18 , SYSZ_REG_F1 = 19 , SYSZ_REG_F2 = 20 , SYSZ_REG_F3 = 21 , SYSZ_REG_F4 = 22 , SYSZ_REG_F5 = 23 , SYSZ_REG_F6 = 24 , SYSZ_REG_F7 = 25 , SYSZ_REG_F8 = 26 , SYSZ_REG_F9 = 27 , SYSZ_REG_F10 = 28 , SYSZ_REG_F11 = 29 , SYSZ_REG_F12 = 30 , SYSZ_REG_F13 = 31 , SYSZ_REG_F14 = 32 , SYSZ_REG_F15 = 33 , SYSZ_REG_R0L = 34 , SYSZ_REG_A0 = 35 , SYSZ_REG_A1 = 36 , SYSZ_REG_A2 = 37 , SYSZ_REG_A3 = 38 , SYSZ_REG_A4 = 39 , SYSZ_REG_A5 = 40 , SYSZ_REG_A6 = 41 , SYSZ_REG_A7 = 42 , SYSZ_REG_A8 = 43 , SYSZ_REG_A9 = 44 , SYSZ_REG_A10 = 45 , SYSZ_REG_A11 = 46 , SYSZ_REG_A12 = 47 , SYSZ_REG_A13 = 48 , SYSZ_REG_A14 = 49 , SYSZ_REG_A15 = 50 , SYSZ_REG_C0 = 51 , SYSZ_REG_C1 = 52 , SYSZ_REG_C2 = 53 , SYSZ_REG_C3 = 54 , SYSZ_REG_C4 = 55 , SYSZ_REG_C5 = 56 , SYSZ_REG_C6 = 57 , SYSZ_REG_C7 = 58 , SYSZ_REG_C8 = 59 , SYSZ_REG_C9 = 60 , SYSZ_REG_C10 = 61 , SYSZ_REG_C11 = 62 , SYSZ_REG_C12 = 63 , SYSZ_REG_C13 = 64 , SYSZ_REG_C14 = 65 , SYSZ_REG_C15 = 66 , SYSZ_REG_V0 = 67 , SYSZ_REG_V1 = 68 , SYSZ_REG_V2 = 69 , SYSZ_REG_V3 = 70 , SYSZ_REG_V4 = 71 , SYSZ_REG_V5 = 72 , SYSZ_REG_V6 = 73 , SYSZ_REG_V7 = 74 , SYSZ_REG_V8 = 75 , SYSZ_REG_V9 = 76 , SYSZ_REG_V10 = 77 , SYSZ_REG_V11 = 78 , SYSZ_REG_V12 = 79 , SYSZ_REG_V13 = 80 , SYSZ_REG_V14 = 81 , SYSZ_REG_V15 = 82 , SYSZ_REG_V16 = 83 , SYSZ_REG_V17 = 84 , SYSZ_REG_V18 = 85 , SYSZ_REG_V19 = 86 , SYSZ_REG_V20 = 87 , SYSZ_REG_V21 = 88 , SYSZ_REG_V22 = 89 , SYSZ_REG_V23 = 90 , SYSZ_REG_V24 = 91 , SYSZ_REG_V25 = 92 , SYSZ_REG_V26 = 93 , SYSZ_REG_V27 = 94 , SYSZ_REG_V28 = 95 , SYSZ_REG_V29 = 96 , SYSZ_REG_V30 = 97 , SYSZ_REG_V31 = 98 , SYSZ_REG_F16 = 99 , SYSZ_REG_F17 = 100 , SYSZ_REG_F18 = 101 , SYSZ_REG_F19 = 102 , SYSZ_REG_F20 = 103 , SYSZ_REG_F21 = 104 , SYSZ_REG_F22 = 105 , SYSZ_REG_F23 = 106 , SYSZ_REG_F24 = 107 , SYSZ_REG_F25 = 108 , SYSZ_REG_F26 = 109 , SYSZ_REG_F27 = 110 , SYSZ_REG_F28 = 111 , SYSZ_REG_F29 = 112 , SYSZ_REG_F30 = 113 , SYSZ_REG_F31 = 114 , SYSZ_REG_F0Q = 115 , SYSZ_REG_F4Q = 116 , SYSZ_REG_ENDING = 117 , } # [doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sysz_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< BDLAddr operand"] pub length : u64 , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sysz_op_mem"] [:: std :: mem :: size_of :: < sysz_op_mem > () - 24usize] ; ["Alignment of sysz_op_mem"] [:: std :: mem :: align_of :: < sysz_op_mem > () - 8usize] ; ["Offset of field: sysz_op_mem::base"] [:: std :: mem :: offset_of ! (sysz_op_mem , base) - 0usize] ; ["Offset of field: sysz_op_mem::index"] [:: std :: mem :: offset_of ! (sysz_op_mem , index) - 1usize] ; ["Offset of field: sysz_op_mem::length"] [:: std :: mem :: offset_of ! (sysz_op_mem , length) - 8usize] ; ["Offset of field: sysz_op_mem::disp"] [:: std :: mem :: offset_of ! (sysz_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz_op { # [doc = "< operand type"] pub type_ : sysz_op_type , pub __bindgen_anon_1 : cs_sysz_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sysz_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sysz_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sysz_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sysz_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sysz_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op"] [:: std :: mem :: size_of :: < cs_sysz_op > () - 32usize] ; ["Alignment of cs_sysz_op"] [:: std :: mem :: align_of :: < cs_sysz_op > () - 8usize] ; ["Offset of field: cs_sysz_op::type_"] [:: std :: mem :: offset_of ! (cs_sysz_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz { # [doc = "< Code condition"] pub cc : sysz_cc , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sysz_op ; 6usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz"] [:: std :: mem :: size_of :: < cs_sysz > () - 200usize] ; ["Alignment of cs_sysz"] [:: std :: mem :: align_of :: < cs_sysz > () - 8usize] ; ["Offset of field: cs_sysz::cc"] [:: std :: mem :: offset_of ! (cs_sysz , cc) - 0usize] ; ["Offset of field: cs_sysz::op_count"] [:: std :: mem :: offset_of ! (cs_sysz , op_count) - 4usize] ; ["Offset of field: cs_sysz::operands"] [:: std :: mem :: offset_of ! (cs_sysz , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SystemZ instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn { SYSZ_INS_INVALID = 0 , SYSZ_INS_A = 1 , SYSZ_INS_ADB = 2 , SYSZ_INS_ADBR = 3 , SYSZ_INS_AEB = 4 , SYSZ_INS_AEBR = 5 , SYSZ_INS_AFI = 6 , SYSZ_INS_AG = 7 , SYSZ_INS_AGF = 8 , SYSZ_INS_AGFI = 9 , SYSZ_INS_AGFR = 10 , SYSZ_INS_AGHI = 11 , SYSZ_INS_AGHIK = 12 , SYSZ_INS_AGR = 13 , SYSZ_INS_AGRK = 14 , SYSZ_INS_AGSI = 15 , SYSZ_INS_AH = 16 , SYSZ_INS_AHI = 17 , SYSZ_INS_AHIK = 18 , SYSZ_INS_AHY = 19 , SYSZ_INS_AIH = 20 , SYSZ_INS_AL = 21 , SYSZ_INS_ALC = 22 , SYSZ_INS_ALCG = 23 , SYSZ_INS_ALCGR = 24 , SYSZ_INS_ALCR = 25 , SYSZ_INS_ALFI = 26 , SYSZ_INS_ALG = 27 , SYSZ_INS_ALGF = 28 , SYSZ_INS_ALGFI = 29 , SYSZ_INS_ALGFR = 30 , SYSZ_INS_ALGHSIK = 31 , SYSZ_INS_ALGR = 32 , SYSZ_INS_ALGRK = 33 , SYSZ_INS_ALHSIK = 34 , SYSZ_INS_ALR = 35 , SYSZ_INS_ALRK = 36 , SYSZ_INS_ALY = 37 , SYSZ_INS_AR = 38 , SYSZ_INS_ARK = 39 , SYSZ_INS_ASI = 40 , SYSZ_INS_AXBR = 41 , SYSZ_INS_AY = 42 , SYSZ_INS_BCR = 43 , SYSZ_INS_BRC = 44 , SYSZ_INS_BRCL = 45 , SYSZ_INS_CGIJ = 46 , SYSZ_INS_CGRJ = 47 , SYSZ_INS_CIJ = 48 , SYSZ_INS_CLGIJ = 49 , SYSZ_INS_CLGRJ = 50 , SYSZ_INS_CLIJ = 51 , SYSZ_INS_CLRJ = 52 , SYSZ_INS_CRJ = 53 , SYSZ_INS_BER = 54 , SYSZ_INS_JE = 55 , SYSZ_INS_JGE = 56 , SYSZ_INS_LOCE = 57 , SYSZ_INS_LOCGE = 58 , SYSZ_INS_LOCGRE = 59 , SYSZ_INS_LOCRE = 60 , SYSZ_INS_STOCE = 61 , SYSZ_INS_STOCGE = 62 , SYSZ_INS_BHR = 63 , SYSZ_INS_BHER = 64 , SYSZ_INS_JHE = 65 , SYSZ_INS_JGHE = 66 , SYSZ_INS_LOCHE = 67 , SYSZ_INS_LOCGHE = 68 , SYSZ_INS_LOCGRHE = 69 , SYSZ_INS_LOCRHE = 70 , SYSZ_INS_STOCHE = 71 , SYSZ_INS_STOCGHE = 72 , SYSZ_INS_JH = 73 , SYSZ_INS_JGH = 74 , SYSZ_INS_LOCH = 75 , SYSZ_INS_LOCGH = 76 , SYSZ_INS_LOCGRH = 77 , SYSZ_INS_LOCRH = 78 , SYSZ_INS_STOCH = 79 , SYSZ_INS_STOCGH = 80 , SYSZ_INS_CGIJNLH = 81 , SYSZ_INS_CGRJNLH = 82 , SYSZ_INS_CIJNLH = 83 , SYSZ_INS_CLGIJNLH = 84 , SYSZ_INS_CLGRJNLH = 85 , SYSZ_INS_CLIJNLH = 86 , SYSZ_INS_CLRJNLH = 87 , SYSZ_INS_CRJNLH = 88 , SYSZ_INS_CGIJE = 89 , SYSZ_INS_CGRJE = 90 , SYSZ_INS_CIJE = 91 , SYSZ_INS_CLGIJE = 92 , SYSZ_INS_CLGRJE = 93 , SYSZ_INS_CLIJE = 94 , SYSZ_INS_CLRJE = 95 , SYSZ_INS_CRJE = 96 , SYSZ_INS_CGIJNLE = 97 , SYSZ_INS_CGRJNLE = 98 , SYSZ_INS_CIJNLE = 99 , SYSZ_INS_CLGIJNLE = 100 , SYSZ_INS_CLGRJNLE = 101 , SYSZ_INS_CLIJNLE = 102 , SYSZ_INS_CLRJNLE = 103 , SYSZ_INS_CRJNLE = 104 , SYSZ_INS_CGIJH = 105 , SYSZ_INS_CGRJH = 106 , SYSZ_INS_CIJH = 107 , SYSZ_INS_CLGIJH = 108 , SYSZ_INS_CLGRJH = 109 , SYSZ_INS_CLIJH = 110 , SYSZ_INS_CLRJH = 111 , SYSZ_INS_CRJH = 112 , SYSZ_INS_CGIJNL = 113 , SYSZ_INS_CGRJNL = 114 , SYSZ_INS_CIJNL = 115 , SYSZ_INS_CLGIJNL = 116 , SYSZ_INS_CLGRJNL = 117 , SYSZ_INS_CLIJNL = 118 , SYSZ_INS_CLRJNL = 119 , SYSZ_INS_CRJNL = 120 , SYSZ_INS_CGIJHE = 121 , SYSZ_INS_CGRJHE = 122 , SYSZ_INS_CIJHE = 123 , SYSZ_INS_CLGIJHE = 124 , SYSZ_INS_CLGRJHE = 125 , SYSZ_INS_CLIJHE = 126 , SYSZ_INS_CLRJHE = 127 , SYSZ_INS_CRJHE = 128 , SYSZ_INS_CGIJNHE = 129 , SYSZ_INS_CGRJNHE = 130 , SYSZ_INS_CIJNHE = 131 , SYSZ_INS_CLGIJNHE = 132 , SYSZ_INS_CLGRJNHE = 133 , SYSZ_INS_CLIJNHE = 134 , SYSZ_INS_CLRJNHE = 135 , SYSZ_INS_CRJNHE = 136 , SYSZ_INS_CGIJL = 137 , SYSZ_INS_CGRJL = 138 , SYSZ_INS_CIJL = 139 , SYSZ_INS_CLGIJL = 140 , SYSZ_INS_CLGRJL = 141 , SYSZ_INS_CLIJL = 142 , SYSZ_INS_CLRJL = 143 , SYSZ_INS_CRJL = 144 , SYSZ_INS_CGIJNH = 145 , SYSZ_INS_CGRJNH = 146 , SYSZ_INS_CIJNH = 147 , SYSZ_INS_CLGIJNH = 148 , SYSZ_INS_CLGRJNH = 149 , SYSZ_INS_CLIJNH = 150 , SYSZ_INS_CLRJNH = 151 , SYSZ_INS_CRJNH = 152 , SYSZ_INS_CGIJLE = 153 , SYSZ_INS_CGRJLE = 154 , SYSZ_INS_CIJLE = 155 , SYSZ_INS_CLGIJLE = 156 , SYSZ_INS_CLGRJLE = 157 , SYSZ_INS_CLIJLE = 158 , SYSZ_INS_CLRJLE = 159 , SYSZ_INS_CRJLE = 160 , SYSZ_INS_CGIJNE = 161 , SYSZ_INS_CGRJNE = 162 , SYSZ_INS_CIJNE = 163 , SYSZ_INS_CLGIJNE = 164 , SYSZ_INS_CLGRJNE = 165 , SYSZ_INS_CLIJNE = 166 , SYSZ_INS_CLRJNE = 167 , SYSZ_INS_CRJNE = 168 , SYSZ_INS_CGIJLH = 169 , SYSZ_INS_CGRJLH = 170 , SYSZ_INS_CIJLH = 171 , SYSZ_INS_CLGIJLH = 172 , SYSZ_INS_CLGRJLH = 173 , SYSZ_INS_CLIJLH = 174 , SYSZ_INS_CLRJLH = 175 , SYSZ_INS_CRJLH = 176 , SYSZ_INS_BLR = 177 , SYSZ_INS_BLER = 178 , SYSZ_INS_JLE = 179 , SYSZ_INS_JGLE = 180 , SYSZ_INS_LOCLE = 181 , SYSZ_INS_LOCGLE = 182 , SYSZ_INS_LOCGRLE = 183 , SYSZ_INS_LOCRLE = 184 , SYSZ_INS_STOCLE = 185 , SYSZ_INS_STOCGLE = 186 , SYSZ_INS_BLHR = 187 , SYSZ_INS_JLH = 188 , SYSZ_INS_JGLH = 189 , SYSZ_INS_LOCLH = 190 , SYSZ_INS_LOCGLH = 191 , SYSZ_INS_LOCGRLH = 192 , SYSZ_INS_LOCRLH = 193 , SYSZ_INS_STOCLH = 194 , SYSZ_INS_STOCGLH = 195 , SYSZ_INS_JL = 196 , SYSZ_INS_JGL = 197 , SYSZ_INS_LOCL = 198 , SYSZ_INS_LOCGL = 199 , SYSZ_INS_LOCGRL = 200 , SYSZ_INS_LOCRL = 201 , SYSZ_INS_LOC = 202 , SYSZ_INS_LOCG = 203 , SYSZ_INS_LOCGR = 204 , SYSZ_INS_LOCR = 205 , SYSZ_INS_STOCL = 206 , SYSZ_INS_STOCGL = 207 , SYSZ_INS_BNER = 208 , SYSZ_INS_JNE = 209 , SYSZ_INS_JGNE = 210 , SYSZ_INS_LOCNE = 211 , SYSZ_INS_LOCGNE = 212 , SYSZ_INS_LOCGRNE = 213 , SYSZ_INS_LOCRNE = 214 , SYSZ_INS_STOCNE = 215 , SYSZ_INS_STOCGNE = 216 , SYSZ_INS_BNHR = 217 , SYSZ_INS_BNHER = 218 , SYSZ_INS_JNHE = 219 , SYSZ_INS_JGNHE = 220 , SYSZ_INS_LOCNHE = 221 , SYSZ_INS_LOCGNHE = 222 , SYSZ_INS_LOCGRNHE = 223 , SYSZ_INS_LOCRNHE = 224 , SYSZ_INS_STOCNHE = 225 , SYSZ_INS_STOCGNHE = 226 , SYSZ_INS_JNH = 227 , SYSZ_INS_JGNH = 228 , SYSZ_INS_LOCNH = 229 , SYSZ_INS_LOCGNH = 230 , SYSZ_INS_LOCGRNH = 231 , SYSZ_INS_LOCRNH = 232 , SYSZ_INS_STOCNH = 233 , SYSZ_INS_STOCGNH = 234 , SYSZ_INS_BNLR = 235 , SYSZ_INS_BNLER = 236 , SYSZ_INS_JNLE = 237 , SYSZ_INS_JGNLE = 238 , SYSZ_INS_LOCNLE = 239 , SYSZ_INS_LOCGNLE = 240 , SYSZ_INS_LOCGRNLE = 241 , SYSZ_INS_LOCRNLE = 242 , SYSZ_INS_STOCNLE = 243 , SYSZ_INS_STOCGNLE = 244 , SYSZ_INS_BNLHR = 245 , SYSZ_INS_JNLH = 246 , SYSZ_INS_JGNLH = 247 , SYSZ_INS_LOCNLH = 248 , SYSZ_INS_LOCGNLH = 249 , SYSZ_INS_LOCGRNLH = 250 , SYSZ_INS_LOCRNLH = 251 , SYSZ_INS_STOCNLH = 252 , SYSZ_INS_STOCGNLH = 253 , SYSZ_INS_JNL = 254 , SYSZ_INS_JGNL = 255 , SYSZ_INS_LOCNL = 256 , SYSZ_INS_LOCGNL = 257 , SYSZ_INS_LOCGRNL = 258 , SYSZ_INS_LOCRNL = 259 , SYSZ_INS_STOCNL = 260 , SYSZ_INS_STOCGNL = 261 , SYSZ_INS_BNOR = 262 , SYSZ_INS_JNO = 263 , SYSZ_INS_JGNO = 264 , SYSZ_INS_LOCNO = 265 , SYSZ_INS_LOCGNO = 266 , SYSZ_INS_LOCGRNO = 267 , SYSZ_INS_LOCRNO = 268 , SYSZ_INS_STOCNO = 269 , SYSZ_INS_STOCGNO = 270 , SYSZ_INS_BOR = 271 , SYSZ_INS_JO = 272 , SYSZ_INS_JGO = 273 , SYSZ_INS_LOCO = 274 , SYSZ_INS_LOCGO = 275 , SYSZ_INS_LOCGRO = 276 , SYSZ_INS_LOCRO = 277 , SYSZ_INS_STOCO = 278 , SYSZ_INS_STOCGO = 279 , SYSZ_INS_STOC = 280 , SYSZ_INS_STOCG = 281 , SYSZ_INS_BASR = 282 , SYSZ_INS_BR = 283 , SYSZ_INS_BRAS = 284 , SYSZ_INS_BRASL = 285 , SYSZ_INS_J = 286 , SYSZ_INS_JG = 287 , SYSZ_INS_BRCT = 288 , SYSZ_INS_BRCTG = 289 , SYSZ_INS_C = 290 , SYSZ_INS_CDB = 291 , SYSZ_INS_CDBR = 292 , SYSZ_INS_CDFBR = 293 , SYSZ_INS_CDGBR = 294 , SYSZ_INS_CDLFBR = 295 , SYSZ_INS_CDLGBR = 296 , SYSZ_INS_CEB = 297 , SYSZ_INS_CEBR = 298 , SYSZ_INS_CEFBR = 299 , SYSZ_INS_CEGBR = 300 , SYSZ_INS_CELFBR = 301 , SYSZ_INS_CELGBR = 302 , SYSZ_INS_CFDBR = 303 , SYSZ_INS_CFEBR = 304 , SYSZ_INS_CFI = 305 , SYSZ_INS_CFXBR = 306 , SYSZ_INS_CG = 307 , SYSZ_INS_CGDBR = 308 , SYSZ_INS_CGEBR = 309 , SYSZ_INS_CGF = 310 , SYSZ_INS_CGFI = 311 , SYSZ_INS_CGFR = 312 , SYSZ_INS_CGFRL = 313 , SYSZ_INS_CGH = 314 , SYSZ_INS_CGHI = 315 , SYSZ_INS_CGHRL = 316 , SYSZ_INS_CGHSI = 317 , SYSZ_INS_CGR = 318 , SYSZ_INS_CGRL = 319 , SYSZ_INS_CGXBR = 320 , SYSZ_INS_CH = 321 , SYSZ_INS_CHF = 322 , SYSZ_INS_CHHSI = 323 , SYSZ_INS_CHI = 324 , SYSZ_INS_CHRL = 325 , SYSZ_INS_CHSI = 326 , SYSZ_INS_CHY = 327 , SYSZ_INS_CIH = 328 , SYSZ_INS_CL = 329 , SYSZ_INS_CLC = 330 , SYSZ_INS_CLFDBR = 331 , SYSZ_INS_CLFEBR = 332 , SYSZ_INS_CLFHSI = 333 , SYSZ_INS_CLFI = 334 , SYSZ_INS_CLFXBR = 335 , SYSZ_INS_CLG = 336 , SYSZ_INS_CLGDBR = 337 , SYSZ_INS_CLGEBR = 338 , SYSZ_INS_CLGF = 339 , SYSZ_INS_CLGFI = 340 , SYSZ_INS_CLGFR = 341 , SYSZ_INS_CLGFRL = 342 , SYSZ_INS_CLGHRL = 343 , SYSZ_INS_CLGHSI = 344 , SYSZ_INS_CLGR = 345 , SYSZ_INS_CLGRL = 346 , SYSZ_INS_CLGXBR = 347 , SYSZ_INS_CLHF = 348 , SYSZ_INS_CLHHSI = 349 , SYSZ_INS_CLHRL = 350 , SYSZ_INS_CLI = 351 , SYSZ_INS_CLIH = 352 , SYSZ_INS_CLIY = 353 , SYSZ_INS_CLR = 354 , SYSZ_INS_CLRL = 355 , SYSZ_INS_CLST = 356 , SYSZ_INS_CLY = 357 , SYSZ_INS_CPSDR = 358 , SYSZ_INS_CR = 359 , SYSZ_INS_CRL = 360 , SYSZ_INS_CS = 361 , SYSZ_INS_CSG = 362 , SYSZ_INS_CSY = 363 , SYSZ_INS_CXBR = 364 , SYSZ_INS_CXFBR = 365 , SYSZ_INS_CXGBR = 366 , SYSZ_INS_CXLFBR = 367 , SYSZ_INS_CXLGBR = 368 , SYSZ_INS_CY = 369 , SYSZ_INS_DDB = 370 , SYSZ_INS_DDBR = 371 , SYSZ_INS_DEB = 372 , SYSZ_INS_DEBR = 373 , SYSZ_INS_DL = 374 , SYSZ_INS_DLG = 375 , SYSZ_INS_DLGR = 376 , SYSZ_INS_DLR = 377 , SYSZ_INS_DSG = 378 , SYSZ_INS_DSGF = 379 , SYSZ_INS_DSGFR = 380 , SYSZ_INS_DSGR = 381 , SYSZ_INS_DXBR = 382 , SYSZ_INS_EAR = 383 , SYSZ_INS_FIDBR = 384 , SYSZ_INS_FIDBRA = 385 , SYSZ_INS_FIEBR = 386 , SYSZ_INS_FIEBRA = 387 , SYSZ_INS_FIXBR = 388 , SYSZ_INS_FIXBRA = 389 , SYSZ_INS_FLOGR = 390 , SYSZ_INS_IC = 391 , SYSZ_INS_ICY = 392 , SYSZ_INS_IIHF = 393 , SYSZ_INS_IIHH = 394 , SYSZ_INS_IIHL = 395 , SYSZ_INS_IILF = 396 , SYSZ_INS_IILH = 397 , SYSZ_INS_IILL = 398 , SYSZ_INS_IPM = 399 , SYSZ_INS_L = 400 , SYSZ_INS_LA = 401 , SYSZ_INS_LAA = 402 , SYSZ_INS_LAAG = 403 , SYSZ_INS_LAAL = 404 , SYSZ_INS_LAALG = 405 , SYSZ_INS_LAN = 406 , SYSZ_INS_LANG = 407 , SYSZ_INS_LAO = 408 , SYSZ_INS_LAOG = 409 , SYSZ_INS_LARL = 410 , SYSZ_INS_LAX = 411 , SYSZ_INS_LAXG = 412 , SYSZ_INS_LAY = 413 , SYSZ_INS_LB = 414 , SYSZ_INS_LBH = 415 , SYSZ_INS_LBR = 416 , SYSZ_INS_LCDBR = 417 , SYSZ_INS_LCEBR = 418 , SYSZ_INS_LCGFR = 419 , SYSZ_INS_LCGR = 420 , SYSZ_INS_LCR = 421 , SYSZ_INS_LCXBR = 422 , SYSZ_INS_LD = 423 , SYSZ_INS_LDEB = 424 , SYSZ_INS_LDEBR = 425 , SYSZ_INS_LDGR = 426 , SYSZ_INS_LDR = 427 , SYSZ_INS_LDXBR = 428 , SYSZ_INS_LDXBRA = 429 , SYSZ_INS_LDY = 430 , SYSZ_INS_LE = 431 , SYSZ_INS_LEDBR = 432 , SYSZ_INS_LEDBRA = 433 , SYSZ_INS_LER = 434 , SYSZ_INS_LEXBR = 435 , SYSZ_INS_LEXBRA = 436 , SYSZ_INS_LEY = 437 , SYSZ_INS_LFH = 438 , SYSZ_INS_LG = 439 , SYSZ_INS_LGB = 440 , SYSZ_INS_LGBR = 441 , SYSZ_INS_LGDR = 442 , SYSZ_INS_LGF = 443 , SYSZ_INS_LGFI = 444 , SYSZ_INS_LGFR = 445 , SYSZ_INS_LGFRL = 446 , SYSZ_INS_LGH = 447 , SYSZ_INS_LGHI = 448 , SYSZ_INS_LGHR = 449 , SYSZ_INS_LGHRL = 450 , SYSZ_INS_LGR = 451 , SYSZ_INS_LGRL = 452 , SYSZ_INS_LH = 453 , SYSZ_INS_LHH = 454 , SYSZ_INS_LHI = 455 , SYSZ_INS_LHR = 456 , SYSZ_INS_LHRL = 457 , SYSZ_INS_LHY = 458 , SYSZ_INS_LLC = 459 , SYSZ_INS_LLCH = 460 , SYSZ_INS_LLCR = 461 , SYSZ_INS_LLGC = 462 , SYSZ_INS_LLGCR = 463 , SYSZ_INS_LLGF = 464 , SYSZ_INS_LLGFR = 465 , SYSZ_INS_LLGFRL = 466 , SYSZ_INS_LLGH = 467 , SYSZ_INS_LLGHR = 468 , SYSZ_INS_LLGHRL = 469 , SYSZ_INS_LLH = 470 , SYSZ_INS_LLHH = 471 , SYSZ_INS_LLHR = 472 , SYSZ_INS_LLHRL = 473 , SYSZ_INS_LLIHF = 474 , SYSZ_INS_LLIHH = 475 , SYSZ_INS_LLIHL = 476 , SYSZ_INS_LLILF = 477 , SYSZ_INS_LLILH = 478 , SYSZ_INS_LLILL = 479 , SYSZ_INS_LMG = 480 , SYSZ_INS_LNDBR = 481 , SYSZ_INS_LNEBR = 482 , SYSZ_INS_LNGFR = 483 , SYSZ_INS_LNGR = 484 , SYSZ_INS_LNR = 485 , SYSZ_INS_LNXBR = 486 , SYSZ_INS_LPDBR = 487 , SYSZ_INS_LPEBR = 488 , SYSZ_INS_LPGFR = 489 , SYSZ_INS_LPGR = 490 , SYSZ_INS_LPR = 491 , SYSZ_INS_LPXBR = 492 , SYSZ_INS_LR = 493 , SYSZ_INS_LRL = 494 , SYSZ_INS_LRV = 495 , SYSZ_INS_LRVG = 496 , SYSZ_INS_LRVGR = 497 , SYSZ_INS_LRVR = 498 , SYSZ_INS_LT = 499 , SYSZ_INS_LTDBR = 500 , SYSZ_INS_LTEBR = 501 , SYSZ_INS_LTG = 502 , SYSZ_INS_LTGF = 503 , SYSZ_INS_LTGFR = 504 , SYSZ_INS_LTGR = 505 , SYSZ_INS_LTR = 506 , SYSZ_INS_LTXBR = 507 , SYSZ_INS_LXDB = 508 , SYSZ_INS_LXDBR = 509 , SYSZ_INS_LXEB = 510 , SYSZ_INS_LXEBR = 511 , SYSZ_INS_LXR = 512 , SYSZ_INS_LY = 513 , SYSZ_INS_LZDR = 514 , SYSZ_INS_LZER = 515 , SYSZ_INS_LZXR = 516 , SYSZ_INS_MADB = 517 , SYSZ_INS_MADBR = 518 , SYSZ_INS_MAEB = 519 , SYSZ_INS_MAEBR = 520 , SYSZ_INS_MDB = 521 , SYSZ_INS_MDBR = 522 , SYSZ_INS_MDEB = 523 , SYSZ_INS_MDEBR = 524 , SYSZ_INS_MEEB = 525 , SYSZ_INS_MEEBR = 526 , SYSZ_INS_MGHI = 527 , SYSZ_INS_MH = 528 , SYSZ_INS_MHI = 529 , SYSZ_INS_MHY = 530 , SYSZ_INS_MLG = 531 , SYSZ_INS_MLGR = 532 , SYSZ_INS_MS = 533 , SYSZ_INS_MSDB = 534 , SYSZ_INS_MSDBR = 535 , SYSZ_INS_MSEB = 536 , SYSZ_INS_MSEBR = 537 , SYSZ_INS_MSFI = 538 , SYSZ_INS_MSG = 539 , SYSZ_INS_MSGF = 540 , SYSZ_INS_MSGFI = 541 , SYSZ_INS_MSGFR = 542 , SYSZ_INS_MSGR = 543 , SYSZ_INS_MSR = 544 , SYSZ_INS_MSY = 545 , SYSZ_INS_MVC = 546 , SYSZ_INS_MVGHI = 547 , SYSZ_INS_MVHHI = 548 , SYSZ_INS_MVHI = 549 , SYSZ_INS_MVI = 550 , SYSZ_INS_MVIY = 551 , SYSZ_INS_MVST = 552 , SYSZ_INS_MXBR = 553 , SYSZ_INS_MXDB = 554 , SYSZ_INS_MXDBR = 555 , SYSZ_INS_N = 556 , SYSZ_INS_NC = 557 , SYSZ_INS_NG = 558 , SYSZ_INS_NGR = 559 , SYSZ_INS_NGRK = 560 , SYSZ_INS_NI = 561 , SYSZ_INS_NIHF = 562 , SYSZ_INS_NIHH = 563 , SYSZ_INS_NIHL = 564 , SYSZ_INS_NILF = 565 , SYSZ_INS_NILH = 566 , SYSZ_INS_NILL = 567 , SYSZ_INS_NIY = 568 , SYSZ_INS_NR = 569 , SYSZ_INS_NRK = 570 , SYSZ_INS_NY = 571 , SYSZ_INS_O = 572 , SYSZ_INS_OC = 573 , SYSZ_INS_OG = 574 , SYSZ_INS_OGR = 575 , SYSZ_INS_OGRK = 576 , SYSZ_INS_OI = 577 , SYSZ_INS_OIHF = 578 , SYSZ_INS_OIHH = 579 , SYSZ_INS_OIHL = 580 , SYSZ_INS_OILF = 581 , SYSZ_INS_OILH = 582 , SYSZ_INS_OILL = 583 , SYSZ_INS_OIY = 584 , SYSZ_INS_OR = 585 , SYSZ_INS_ORK = 586 , SYSZ_INS_OY = 587 , SYSZ_INS_PFD = 588 , SYSZ_INS_PFDRL = 589 , SYSZ_INS_RISBG = 590 , SYSZ_INS_RISBHG = 591 , SYSZ_INS_RISBLG = 592 , SYSZ_INS_RLL = 593 , SYSZ_INS_RLLG = 594 , SYSZ_INS_RNSBG = 595 , SYSZ_INS_ROSBG = 596 , SYSZ_INS_RXSBG = 597 , SYSZ_INS_S = 598 , SYSZ_INS_SDB = 599 , SYSZ_INS_SDBR = 600 , SYSZ_INS_SEB = 601 , SYSZ_INS_SEBR = 602 , SYSZ_INS_SG = 603 , SYSZ_INS_SGF = 604 , SYSZ_INS_SGFR = 605 , SYSZ_INS_SGR = 606 , SYSZ_INS_SGRK = 607 , SYSZ_INS_SH = 608 , SYSZ_INS_SHY = 609 , SYSZ_INS_SL = 610 , SYSZ_INS_SLB = 611 , SYSZ_INS_SLBG = 612 , SYSZ_INS_SLBR = 613 , SYSZ_INS_SLFI = 614 , SYSZ_INS_SLG = 615 , SYSZ_INS_SLBGR = 616 , SYSZ_INS_SLGF = 617 , SYSZ_INS_SLGFI = 618 , SYSZ_INS_SLGFR = 619 , SYSZ_INS_SLGR = 620 , SYSZ_INS_SLGRK = 621 , SYSZ_INS_SLL = 622 , SYSZ_INS_SLLG = 623 , SYSZ_INS_SLLK = 624 , SYSZ_INS_SLR = 625 , SYSZ_INS_SLRK = 626 , SYSZ_INS_SLY = 627 , SYSZ_INS_SQDB = 628 , SYSZ_INS_SQDBR = 629 , SYSZ_INS_SQEB = 630 , SYSZ_INS_SQEBR = 631 , SYSZ_INS_SQXBR = 632 , SYSZ_INS_SR = 633 , SYSZ_INS_SRA = 634 , SYSZ_INS_SRAG = 635 , SYSZ_INS_SRAK = 636 , SYSZ_INS_SRK = 637 , SYSZ_INS_SRL = 638 , SYSZ_INS_SRLG = 639 , SYSZ_INS_SRLK = 640 , SYSZ_INS_SRST = 641 , SYSZ_INS_ST = 642 , SYSZ_INS_STC = 643 , SYSZ_INS_STCH = 644 , SYSZ_INS_STCY = 645 , SYSZ_INS_STD = 646 , SYSZ_INS_STDY = 647 , SYSZ_INS_STE = 648 , SYSZ_INS_STEY = 649 , SYSZ_INS_STFH = 650 , SYSZ_INS_STG = 651 , SYSZ_INS_STGRL = 652 , SYSZ_INS_STH = 653 , SYSZ_INS_STHH = 654 , SYSZ_INS_STHRL = 655 , SYSZ_INS_STHY = 656 , SYSZ_INS_STMG = 657 , SYSZ_INS_STRL = 658 , SYSZ_INS_STRV = 659 , SYSZ_INS_STRVG = 660 , SYSZ_INS_STY = 661 , SYSZ_INS_SXBR = 662 , SYSZ_INS_SY = 663 , SYSZ_INS_TM = 664 , SYSZ_INS_TMHH = 665 , SYSZ_INS_TMHL = 666 , SYSZ_INS_TMLH = 667 , SYSZ_INS_TMLL = 668 , SYSZ_INS_TMY = 669 , SYSZ_INS_X = 670 , SYSZ_INS_XC = 671 , SYSZ_INS_XG = 672 , SYSZ_INS_XGR = 673 , SYSZ_INS_XGRK = 674 , SYSZ_INS_XI = 675 , SYSZ_INS_XIHF = 676 , SYSZ_INS_XILF = 677 , SYSZ_INS_XIY = 678 , SYSZ_INS_XR = 679 , SYSZ_INS_XRK = 680 , SYSZ_INS_XY = 681 , SYSZ_INS_AD = 682 , SYSZ_INS_ADR = 683 , SYSZ_INS_ADTR = 684 , SYSZ_INS_ADTRA = 685 , SYSZ_INS_AE = 686 , SYSZ_INS_AER = 687 , SYSZ_INS_AGH = 688 , SYSZ_INS_AHHHR = 689 , SYSZ_INS_AHHLR = 690 , SYSZ_INS_ALGSI = 691 , SYSZ_INS_ALHHHR = 692 , SYSZ_INS_ALHHLR = 693 , SYSZ_INS_ALSI = 694 , SYSZ_INS_ALSIH = 695 , SYSZ_INS_ALSIHN = 696 , SYSZ_INS_AP = 697 , SYSZ_INS_AU = 698 , SYSZ_INS_AUR = 699 , SYSZ_INS_AW = 700 , SYSZ_INS_AWR = 701 , SYSZ_INS_AXR = 702 , SYSZ_INS_AXTR = 703 , SYSZ_INS_AXTRA = 704 , SYSZ_INS_B = 705 , SYSZ_INS_BAKR = 706 , SYSZ_INS_BAL = 707 , SYSZ_INS_BALR = 708 , SYSZ_INS_BAS = 709 , SYSZ_INS_BASSM = 710 , SYSZ_INS_BC = 711 , SYSZ_INS_BCT = 712 , SYSZ_INS_BCTG = 713 , SYSZ_INS_BCTGR = 714 , SYSZ_INS_BCTR = 715 , SYSZ_INS_BE = 716 , SYSZ_INS_BH = 717 , SYSZ_INS_BHE = 718 , SYSZ_INS_BI = 719 , SYSZ_INS_BIC = 720 , SYSZ_INS_BIE = 721 , SYSZ_INS_BIH = 722 , SYSZ_INS_BIHE = 723 , SYSZ_INS_BIL = 724 , SYSZ_INS_BILE = 725 , SYSZ_INS_BILH = 726 , SYSZ_INS_BIM = 727 , SYSZ_INS_BINE = 728 , SYSZ_INS_BINH = 729 , SYSZ_INS_BINHE = 730 , SYSZ_INS_BINL = 731 , SYSZ_INS_BINLE = 732 , SYSZ_INS_BINLH = 733 , SYSZ_INS_BINM = 734 , SYSZ_INS_BINO = 735 , SYSZ_INS_BINP = 736 , SYSZ_INS_BINZ = 737 , SYSZ_INS_BIO = 738 , SYSZ_INS_BIP = 739 , SYSZ_INS_BIZ = 740 , SYSZ_INS_BL = 741 , SYSZ_INS_BLE = 742 , SYSZ_INS_BLH = 743 , SYSZ_INS_BM = 744 , SYSZ_INS_BMR = 745 , SYSZ_INS_BNE = 746 , SYSZ_INS_BNH = 747 , SYSZ_INS_BNHE = 748 , SYSZ_INS_BNL = 749 , SYSZ_INS_BNLE = 750 , SYSZ_INS_BNLH = 751 , SYSZ_INS_BNM = 752 , SYSZ_INS_BNMR = 753 , SYSZ_INS_BNO = 754 , SYSZ_INS_BNP = 755 , SYSZ_INS_BNPR = 756 , SYSZ_INS_BNZ = 757 , SYSZ_INS_BNZR = 758 , SYSZ_INS_BO = 759 , SYSZ_INS_BP = 760 , SYSZ_INS_BPP = 761 , SYSZ_INS_BPR = 762 , SYSZ_INS_BPRP = 763 , SYSZ_INS_BRCTH = 764 , SYSZ_INS_BRXH = 765 , SYSZ_INS_BRXHG = 766 , SYSZ_INS_BRXLE = 767 , SYSZ_INS_BRXLG = 768 , SYSZ_INS_BSA = 769 , SYSZ_INS_BSG = 770 , SYSZ_INS_BSM = 771 , SYSZ_INS_BXH = 772 , SYSZ_INS_BXHG = 773 , SYSZ_INS_BXLE = 774 , SYSZ_INS_BXLEG = 775 , SYSZ_INS_BZ = 776 , SYSZ_INS_BZR = 777 , SYSZ_INS_CD = 778 , SYSZ_INS_CDFBRA = 779 , SYSZ_INS_CDFR = 780 , SYSZ_INS_CDFTR = 781 , SYSZ_INS_CDGBRA = 782 , SYSZ_INS_CDGR = 783 , SYSZ_INS_CDGTR = 784 , SYSZ_INS_CDGTRA = 785 , SYSZ_INS_CDLFTR = 786 , SYSZ_INS_CDLGTR = 787 , SYSZ_INS_CDPT = 788 , SYSZ_INS_CDR = 789 , SYSZ_INS_CDS = 790 , SYSZ_INS_CDSG = 791 , SYSZ_INS_CDSTR = 792 , SYSZ_INS_CDSY = 793 , SYSZ_INS_CDTR = 794 , SYSZ_INS_CDUTR = 795 , SYSZ_INS_CDZT = 796 , SYSZ_INS_CE = 797 , SYSZ_INS_CEDTR = 798 , SYSZ_INS_CEFBRA = 799 , SYSZ_INS_CEFR = 800 , SYSZ_INS_CEGBRA = 801 , SYSZ_INS_CEGR = 802 , SYSZ_INS_CER = 803 , SYSZ_INS_CEXTR = 804 , SYSZ_INS_CFC = 805 , SYSZ_INS_CFDBRA = 806 , SYSZ_INS_CFDR = 807 , SYSZ_INS_CFDTR = 808 , SYSZ_INS_CFEBRA = 809 , SYSZ_INS_CFER = 810 , SYSZ_INS_CFXBRA = 811 , SYSZ_INS_CFXR = 812 , SYSZ_INS_CFXTR = 813 , SYSZ_INS_CGDBRA = 814 , SYSZ_INS_CGDR = 815 , SYSZ_INS_CGDTR = 816 , SYSZ_INS_CGDTRA = 817 , SYSZ_INS_CGEBRA = 818 , SYSZ_INS_CGER = 819 , SYSZ_INS_CGIB = 820 , SYSZ_INS_CGIBE = 821 , SYSZ_INS_CGIBH = 822 , SYSZ_INS_CGIBHE = 823 , SYSZ_INS_CGIBL = 824 , SYSZ_INS_CGIBLE = 825 , SYSZ_INS_CGIBLH = 826 , SYSZ_INS_CGIBNE = 827 , SYSZ_INS_CGIBNH = 828 , SYSZ_INS_CGIBNHE = 829 , SYSZ_INS_CGIBNL = 830 , SYSZ_INS_CGIBNLE = 831 , SYSZ_INS_CGIBNLH = 832 , SYSZ_INS_CGIT = 833 , SYSZ_INS_CGITE = 834 , SYSZ_INS_CGITH = 835 , SYSZ_INS_CGITHE = 836 , SYSZ_INS_CGITL = 837 , SYSZ_INS_CGITLE = 838 , SYSZ_INS_CGITLH = 839 , SYSZ_INS_CGITNE = 840 , SYSZ_INS_CGITNH = 841 , SYSZ_INS_CGITNHE = 842 , SYSZ_INS_CGITNL = 843 , SYSZ_INS_CGITNLE = 844 , SYSZ_INS_CGITNLH = 845 , SYSZ_INS_CGRB = 846 , SYSZ_INS_CGRBE = 847 , SYSZ_INS_CGRBH = 848 , SYSZ_INS_CGRBHE = 849 , SYSZ_INS_CGRBL = 850 , SYSZ_INS_CGRBLE = 851 , SYSZ_INS_CGRBLH = 852 , SYSZ_INS_CGRBNE = 853 , SYSZ_INS_CGRBNH = 854 , SYSZ_INS_CGRBNHE = 855 , SYSZ_INS_CGRBNL = 856 , SYSZ_INS_CGRBNLE = 857 , SYSZ_INS_CGRBNLH = 858 , SYSZ_INS_CGRT = 859 , SYSZ_INS_CGRTE = 860 , SYSZ_INS_CGRTH = 861 , SYSZ_INS_CGRTHE = 862 , SYSZ_INS_CGRTL = 863 , SYSZ_INS_CGRTLE = 864 , SYSZ_INS_CGRTLH = 865 , SYSZ_INS_CGRTNE = 866 , SYSZ_INS_CGRTNH = 867 , SYSZ_INS_CGRTNHE = 868 , SYSZ_INS_CGRTNL = 869 , SYSZ_INS_CGRTNLE = 870 , SYSZ_INS_CGRTNLH = 871 , SYSZ_INS_CGXBRA = 872 , SYSZ_INS_CGXR = 873 , SYSZ_INS_CGXTR = 874 , SYSZ_INS_CGXTRA = 875 , SYSZ_INS_CHHR = 876 , SYSZ_INS_CHLR = 877 , SYSZ_INS_CIB = 878 , SYSZ_INS_CIBE = 879 , SYSZ_INS_CIBH = 880 , SYSZ_INS_CIBHE = 881 , SYSZ_INS_CIBL = 882 , SYSZ_INS_CIBLE = 883 , SYSZ_INS_CIBLH = 884 , SYSZ_INS_CIBNE = 885 , SYSZ_INS_CIBNH = 886 , SYSZ_INS_CIBNHE = 887 , SYSZ_INS_CIBNL = 888 , SYSZ_INS_CIBNLE = 889 , SYSZ_INS_CIBNLH = 890 , SYSZ_INS_CIT = 891 , SYSZ_INS_CITE = 892 , SYSZ_INS_CITH = 893 , SYSZ_INS_CITHE = 894 , SYSZ_INS_CITL = 895 , SYSZ_INS_CITLE = 896 , SYSZ_INS_CITLH = 897 , SYSZ_INS_CITNE = 898 , SYSZ_INS_CITNH = 899 , SYSZ_INS_CITNHE = 900 , SYSZ_INS_CITNL = 901 , SYSZ_INS_CITNLE = 902 , SYSZ_INS_CITNLH = 903 , SYSZ_INS_CKSM = 904 , SYSZ_INS_CLCL = 905 , SYSZ_INS_CLCLE = 906 , SYSZ_INS_CLCLU = 907 , SYSZ_INS_CLFDTR = 908 , SYSZ_INS_CLFIT = 909 , SYSZ_INS_CLFITE = 910 , SYSZ_INS_CLFITH = 911 , SYSZ_INS_CLFITHE = 912 , SYSZ_INS_CLFITL = 913 , SYSZ_INS_CLFITLE = 914 , SYSZ_INS_CLFITLH = 915 , SYSZ_INS_CLFITNE = 916 , SYSZ_INS_CLFITNH = 917 , SYSZ_INS_CLFITNHE = 918 , SYSZ_INS_CLFITNL = 919 , SYSZ_INS_CLFITNLE = 920 , SYSZ_INS_CLFITNLH = 921 , SYSZ_INS_CLFXTR = 922 , SYSZ_INS_CLGDTR = 923 , SYSZ_INS_CLGIB = 924 , SYSZ_INS_CLGIBE = 925 , SYSZ_INS_CLGIBH = 926 , SYSZ_INS_CLGIBHE = 927 , SYSZ_INS_CLGIBL = 928 , SYSZ_INS_CLGIBLE = 929 , SYSZ_INS_CLGIBLH = 930 , SYSZ_INS_CLGIBNE = 931 , SYSZ_INS_CLGIBNH = 932 , SYSZ_INS_CLGIBNHE = 933 , SYSZ_INS_CLGIBNL = 934 , SYSZ_INS_CLGIBNLE = 935 , SYSZ_INS_CLGIBNLH = 936 , SYSZ_INS_CLGIT = 937 , SYSZ_INS_CLGITE = 938 , SYSZ_INS_CLGITH = 939 , SYSZ_INS_CLGITHE = 940 , SYSZ_INS_CLGITL = 941 , SYSZ_INS_CLGITLE = 942 , SYSZ_INS_CLGITLH = 943 , SYSZ_INS_CLGITNE = 944 , SYSZ_INS_CLGITNH = 945 , SYSZ_INS_CLGITNHE = 946 , SYSZ_INS_CLGITNL = 947 , SYSZ_INS_CLGITNLE = 948 , SYSZ_INS_CLGITNLH = 949 , SYSZ_INS_CLGRB = 950 , SYSZ_INS_CLGRBE = 951 , SYSZ_INS_CLGRBH = 952 , SYSZ_INS_CLGRBHE = 953 , SYSZ_INS_CLGRBL = 954 , SYSZ_INS_CLGRBLE = 955 , SYSZ_INS_CLGRBLH = 956 , SYSZ_INS_CLGRBNE = 957 , SYSZ_INS_CLGRBNH = 958 , SYSZ_INS_CLGRBNHE = 959 , SYSZ_INS_CLGRBNL = 960 , SYSZ_INS_CLGRBNLE = 961 , SYSZ_INS_CLGRBNLH = 962 , SYSZ_INS_CLGRT = 963 , SYSZ_INS_CLGRTE = 964 , SYSZ_INS_CLGRTH = 965 , SYSZ_INS_CLGRTHE = 966 , SYSZ_INS_CLGRTL = 967 , SYSZ_INS_CLGRTLE = 968 , SYSZ_INS_CLGRTLH = 969 , SYSZ_INS_CLGRTNE = 970 , SYSZ_INS_CLGRTNH = 971 , SYSZ_INS_CLGRTNHE = 972 , SYSZ_INS_CLGRTNL = 973 , SYSZ_INS_CLGRTNLE = 974 , SYSZ_INS_CLGRTNLH = 975 , SYSZ_INS_CLGT = 976 , SYSZ_INS_CLGTE = 977 , SYSZ_INS_CLGTH = 978 , SYSZ_INS_CLGTHE = 979 , SYSZ_INS_CLGTL = 980 , SYSZ_INS_CLGTLE = 981 , SYSZ_INS_CLGTLH = 982 , SYSZ_INS_CLGTNE = 983 , SYSZ_INS_CLGTNH = 984 , SYSZ_INS_CLGTNHE = 985 , SYSZ_INS_CLGTNL = 986 , SYSZ_INS_CLGTNLE = 987 , SYSZ_INS_CLGTNLH = 988 , SYSZ_INS_CLGXTR = 989 , SYSZ_INS_CLHHR = 990 , SYSZ_INS_CLHLR = 991 , SYSZ_INS_CLIB = 992 , SYSZ_INS_CLIBE = 993 , SYSZ_INS_CLIBH = 994 , SYSZ_INS_CLIBHE = 995 , SYSZ_INS_CLIBL = 996 , SYSZ_INS_CLIBLE = 997 , SYSZ_INS_CLIBLH = 998 , SYSZ_INS_CLIBNE = 999 , SYSZ_INS_CLIBNH = 1000 , SYSZ_INS_CLIBNHE = 1001 , SYSZ_INS_CLIBNL = 1002 , SYSZ_INS_CLIBNLE = 1003 , SYSZ_INS_CLIBNLH = 1004 , SYSZ_INS_CLM = 1005 , SYSZ_INS_CLMH = 1006 , SYSZ_INS_CLMY = 1007 , SYSZ_INS_CLRB = 1008 , SYSZ_INS_CLRBE = 1009 , SYSZ_INS_CLRBH = 1010 , SYSZ_INS_CLRBHE = 1011 , SYSZ_INS_CLRBL = 1012 , SYSZ_INS_CLRBLE = 1013 , SYSZ_INS_CLRBLH = 1014 , SYSZ_INS_CLRBNE = 1015 , SYSZ_INS_CLRBNH = 1016 , SYSZ_INS_CLRBNHE = 1017 , SYSZ_INS_CLRBNL = 1018 , SYSZ_INS_CLRBNLE = 1019 , SYSZ_INS_CLRBNLH = 1020 , SYSZ_INS_CLRT = 1021 , SYSZ_INS_CLRTE = 1022 , SYSZ_INS_CLRTH = 1023 , SYSZ_INS_CLRTHE = 1024 , SYSZ_INS_CLRTL = 1025 , SYSZ_INS_CLRTLE = 1026 , SYSZ_INS_CLRTLH = 1027 , SYSZ_INS_CLRTNE = 1028 , SYSZ_INS_CLRTNH = 1029 , SYSZ_INS_CLRTNHE = 1030 , SYSZ_INS_CLRTNL = 1031 , SYSZ_INS_CLRTNLE = 1032 , SYSZ_INS_CLRTNLH = 1033 , SYSZ_INS_CLT = 1034 , SYSZ_INS_CLTE = 1035 , SYSZ_INS_CLTH = 1036 , SYSZ_INS_CLTHE = 1037 , SYSZ_INS_CLTL = 1038 , SYSZ_INS_CLTLE = 1039 , SYSZ_INS_CLTLH = 1040 , SYSZ_INS_CLTNE = 1041 , SYSZ_INS_CLTNH = 1042 , SYSZ_INS_CLTNHE = 1043 , SYSZ_INS_CLTNL = 1044 , SYSZ_INS_CLTNLE = 1045 , SYSZ_INS_CLTNLH = 1046 , SYSZ_INS_CMPSC = 1047 , SYSZ_INS_CP = 1048 , SYSZ_INS_CPDT = 1049 , SYSZ_INS_CPXT = 1050 , SYSZ_INS_CPYA = 1051 , SYSZ_INS_CRB = 1052 , SYSZ_INS_CRBE = 1053 , SYSZ_INS_CRBH = 1054 , SYSZ_INS_CRBHE = 1055 , SYSZ_INS_CRBL = 1056 , SYSZ_INS_CRBLE = 1057 , SYSZ_INS_CRBLH = 1058 , SYSZ_INS_CRBNE = 1059 , SYSZ_INS_CRBNH = 1060 , SYSZ_INS_CRBNHE = 1061 , SYSZ_INS_CRBNL = 1062 , SYSZ_INS_CRBNLE = 1063 , SYSZ_INS_CRBNLH = 1064 , SYSZ_INS_CRDTE = 1065 , SYSZ_INS_CRT = 1066 , SYSZ_INS_CRTE = 1067 , SYSZ_INS_CRTH = 1068 , SYSZ_INS_CRTHE = 1069 , SYSZ_INS_CRTL = 1070 , SYSZ_INS_CRTLE = 1071 , SYSZ_INS_CRTLH = 1072 , SYSZ_INS_CRTNE = 1073 , SYSZ_INS_CRTNH = 1074 , SYSZ_INS_CRTNHE = 1075 , SYSZ_INS_CRTNL = 1076 , SYSZ_INS_CRTNLE = 1077 , SYSZ_INS_CRTNLH = 1078 , SYSZ_INS_CSCH = 1079 , SYSZ_INS_CSDTR = 1080 , SYSZ_INS_CSP = 1081 , SYSZ_INS_CSPG = 1082 , SYSZ_INS_CSST = 1083 , SYSZ_INS_CSXTR = 1084 , SYSZ_INS_CU12 = 1085 , SYSZ_INS_CU14 = 1086 , SYSZ_INS_CU21 = 1087 , SYSZ_INS_CU24 = 1088 , SYSZ_INS_CU41 = 1089 , SYSZ_INS_CU42 = 1090 , SYSZ_INS_CUDTR = 1091 , SYSZ_INS_CUSE = 1092 , SYSZ_INS_CUTFU = 1093 , SYSZ_INS_CUUTF = 1094 , SYSZ_INS_CUXTR = 1095 , SYSZ_INS_CVB = 1096 , SYSZ_INS_CVBG = 1097 , SYSZ_INS_CVBY = 1098 , SYSZ_INS_CVD = 1099 , SYSZ_INS_CVDG = 1100 , SYSZ_INS_CVDY = 1101 , SYSZ_INS_CXFBRA = 1102 , SYSZ_INS_CXFR = 1103 , SYSZ_INS_CXFTR = 1104 , SYSZ_INS_CXGBRA = 1105 , SYSZ_INS_CXGR = 1106 , SYSZ_INS_CXGTR = 1107 , SYSZ_INS_CXGTRA = 1108 , SYSZ_INS_CXLFTR = 1109 , SYSZ_INS_CXLGTR = 1110 , SYSZ_INS_CXPT = 1111 , SYSZ_INS_CXR = 1112 , SYSZ_INS_CXSTR = 1113 , SYSZ_INS_CXTR = 1114 , SYSZ_INS_CXUTR = 1115 , SYSZ_INS_CXZT = 1116 , SYSZ_INS_CZDT = 1117 , SYSZ_INS_CZXT = 1118 , SYSZ_INS_D = 1119 , SYSZ_INS_DD = 1120 , SYSZ_INS_DDR = 1121 , SYSZ_INS_DDTR = 1122 , SYSZ_INS_DDTRA = 1123 , SYSZ_INS_DE = 1124 , SYSZ_INS_DER = 1125 , SYSZ_INS_DIAG = 1126 , SYSZ_INS_DIDBR = 1127 , SYSZ_INS_DIEBR = 1128 , SYSZ_INS_DP = 1129 , SYSZ_INS_DR = 1130 , SYSZ_INS_DXR = 1131 , SYSZ_INS_DXTR = 1132 , SYSZ_INS_DXTRA = 1133 , SYSZ_INS_ECAG = 1134 , SYSZ_INS_ECCTR = 1135 , SYSZ_INS_ECPGA = 1136 , SYSZ_INS_ECTG = 1137 , SYSZ_INS_ED = 1138 , SYSZ_INS_EDMK = 1139 , SYSZ_INS_EEDTR = 1140 , SYSZ_INS_EEXTR = 1141 , SYSZ_INS_EFPC = 1142 , SYSZ_INS_EPAIR = 1143 , SYSZ_INS_EPAR = 1144 , SYSZ_INS_EPCTR = 1145 , SYSZ_INS_EPSW = 1146 , SYSZ_INS_EREG = 1147 , SYSZ_INS_EREGG = 1148 , SYSZ_INS_ESAIR = 1149 , SYSZ_INS_ESAR = 1150 , SYSZ_INS_ESDTR = 1151 , SYSZ_INS_ESEA = 1152 , SYSZ_INS_ESTA = 1153 , SYSZ_INS_ESXTR = 1154 , SYSZ_INS_ETND = 1155 , SYSZ_INS_EX = 1156 , SYSZ_INS_EXRL = 1157 , SYSZ_INS_FIDR = 1158 , SYSZ_INS_FIDTR = 1159 , SYSZ_INS_FIER = 1160 , SYSZ_INS_FIXR = 1161 , SYSZ_INS_FIXTR = 1162 , SYSZ_INS_HDR = 1163 , SYSZ_INS_HER = 1164 , SYSZ_INS_HSCH = 1165 , SYSZ_INS_IAC = 1166 , SYSZ_INS_ICM = 1167 , SYSZ_INS_ICMH = 1168 , SYSZ_INS_ICMY = 1169 , SYSZ_INS_IDTE = 1170 , SYSZ_INS_IEDTR = 1171 , SYSZ_INS_IEXTR = 1172 , SYSZ_INS_IPK = 1173 , SYSZ_INS_IPTE = 1174 , SYSZ_INS_IRBM = 1175 , SYSZ_INS_ISKE = 1176 , SYSZ_INS_IVSK = 1177 , SYSZ_INS_JGM = 1178 , SYSZ_INS_JGNM = 1179 , SYSZ_INS_JGNP = 1180 , SYSZ_INS_JGNZ = 1181 , SYSZ_INS_JGP = 1182 , SYSZ_INS_JGZ = 1183 , SYSZ_INS_JM = 1184 , SYSZ_INS_JNM = 1185 , SYSZ_INS_JNP = 1186 , SYSZ_INS_JNZ = 1187 , SYSZ_INS_JP = 1188 , SYSZ_INS_JZ = 1189 , SYSZ_INS_KDB = 1190 , SYSZ_INS_KDBR = 1191 , SYSZ_INS_KDTR = 1192 , SYSZ_INS_KEB = 1193 , SYSZ_INS_KEBR = 1194 , SYSZ_INS_KIMD = 1195 , SYSZ_INS_KLMD = 1196 , SYSZ_INS_KM = 1197 , SYSZ_INS_KMA = 1198 , SYSZ_INS_KMAC = 1199 , SYSZ_INS_KMC = 1200 , SYSZ_INS_KMCTR = 1201 , SYSZ_INS_KMF = 1202 , SYSZ_INS_KMO = 1203 , SYSZ_INS_KXBR = 1204 , SYSZ_INS_KXTR = 1205 , SYSZ_INS_LAE = 1206 , SYSZ_INS_LAEY = 1207 , SYSZ_INS_LAM = 1208 , SYSZ_INS_LAMY = 1209 , SYSZ_INS_LASP = 1210 , SYSZ_INS_LAT = 1211 , SYSZ_INS_LCBB = 1212 , SYSZ_INS_LCCTL = 1213 , SYSZ_INS_LCDFR = 1214 , SYSZ_INS_LCDR = 1215 , SYSZ_INS_LCER = 1216 , SYSZ_INS_LCTL = 1217 , SYSZ_INS_LCTLG = 1218 , SYSZ_INS_LCXR = 1219 , SYSZ_INS_LDE = 1220 , SYSZ_INS_LDER = 1221 , SYSZ_INS_LDETR = 1222 , SYSZ_INS_LDXR = 1223 , SYSZ_INS_LDXTR = 1224 , SYSZ_INS_LEDR = 1225 , SYSZ_INS_LEDTR = 1226 , SYSZ_INS_LEXR = 1227 , SYSZ_INS_LFAS = 1228 , SYSZ_INS_LFHAT = 1229 , SYSZ_INS_LFPC = 1230 , SYSZ_INS_LGAT = 1231 , SYSZ_INS_LGG = 1232 , SYSZ_INS_LGSC = 1233 , SYSZ_INS_LLGFAT = 1234 , SYSZ_INS_LLGFSG = 1235 , SYSZ_INS_LLGT = 1236 , SYSZ_INS_LLGTAT = 1237 , SYSZ_INS_LLGTR = 1238 , SYSZ_INS_LLZRGF = 1239 , SYSZ_INS_LM = 1240 , SYSZ_INS_LMD = 1241 , SYSZ_INS_LMH = 1242 , SYSZ_INS_LMY = 1243 , SYSZ_INS_LNDFR = 1244 , SYSZ_INS_LNDR = 1245 , SYSZ_INS_LNER = 1246 , SYSZ_INS_LNXR = 1247 , SYSZ_INS_LOCFH = 1248 , SYSZ_INS_LOCFHE = 1249 , SYSZ_INS_LOCFHH = 1250 , SYSZ_INS_LOCFHHE = 1251 , SYSZ_INS_LOCFHL = 1252 , SYSZ_INS_LOCFHLE = 1253 , SYSZ_INS_LOCFHLH = 1254 , SYSZ_INS_LOCFHM = 1255 , SYSZ_INS_LOCFHNE = 1256 , SYSZ_INS_LOCFHNH = 1257 , SYSZ_INS_LOCFHNHE = 1258 , SYSZ_INS_LOCFHNL = 1259 , SYSZ_INS_LOCFHNLE = 1260 , SYSZ_INS_LOCFHNLH = 1261 , SYSZ_INS_LOCFHNM = 1262 , SYSZ_INS_LOCFHNO = 1263 , SYSZ_INS_LOCFHNP = 1264 , SYSZ_INS_LOCFHNZ = 1265 , SYSZ_INS_LOCFHO = 1266 , SYSZ_INS_LOCFHP = 1267 , SYSZ_INS_LOCFHR = 1268 , SYSZ_INS_LOCFHRE = 1269 , SYSZ_INS_LOCFHRH = 1270 , SYSZ_INS_LOCFHRHE = 1271 , SYSZ_INS_LOCFHRL = 1272 , SYSZ_INS_LOCFHRLE = 1273 , SYSZ_INS_LOCFHRLH = 1274 , SYSZ_INS_LOCFHRM = 1275 , SYSZ_INS_LOCFHRNE = 1276 , SYSZ_INS_LOCFHRNH = 1277 , SYSZ_INS_LOCFHRNHE = 1278 , SYSZ_INS_LOCFHRNL = 1279 , SYSZ_INS_LOCFHRNLE = 1280 , SYSZ_INS_LOCFHRNLH = 1281 , SYSZ_INS_LOCFHRNM = 1282 , SYSZ_INS_LOCFHRNO = 1283 , SYSZ_INS_LOCFHRNP = 1284 , SYSZ_INS_LOCFHRNZ = 1285 , SYSZ_INS_LOCFHRO = 1286 , SYSZ_INS_LOCFHRP = 1287 , SYSZ_INS_LOCFHRZ = 1288 , SYSZ_INS_LOCFHZ = 1289 , SYSZ_INS_LOCGHI = 1290 , SYSZ_INS_LOCGHIE = 1291 , SYSZ_INS_LOCGHIH = 1292 , SYSZ_INS_LOCGHIHE = 1293 , SYSZ_INS_LOCGHIL = 1294 , SYSZ_INS_LOCGHILE = 1295 , SYSZ_INS_LOCGHILH = 1296 , SYSZ_INS_LOCGHIM = 1297 , SYSZ_INS_LOCGHINE = 1298 , SYSZ_INS_LOCGHINH = 1299 , SYSZ_INS_LOCGHINHE = 1300 , SYSZ_INS_LOCGHINL = 1301 , SYSZ_INS_LOCGHINLE = 1302 , SYSZ_INS_LOCGHINLH = 1303 , SYSZ_INS_LOCGHINM = 1304 , SYSZ_INS_LOCGHINO = 1305 , SYSZ_INS_LOCGHINP = 1306 , SYSZ_INS_LOCGHINZ = 1307 , SYSZ_INS_LOCGHIO = 1308 , SYSZ_INS_LOCGHIP = 1309 , SYSZ_INS_LOCGHIZ = 1310 , SYSZ_INS_LOCGM = 1311 , SYSZ_INS_LOCGNM = 1312 , SYSZ_INS_LOCGNP = 1313 , SYSZ_INS_LOCGNZ = 1314 , SYSZ_INS_LOCGP = 1315 , SYSZ_INS_LOCGRM = 1316 , SYSZ_INS_LOCGRNM = 1317 , SYSZ_INS_LOCGRNP = 1318 , SYSZ_INS_LOCGRNZ = 1319 , SYSZ_INS_LOCGRP = 1320 , SYSZ_INS_LOCGRZ = 1321 , SYSZ_INS_LOCGZ = 1322 , SYSZ_INS_LOCHHI = 1323 , SYSZ_INS_LOCHHIE = 1324 , SYSZ_INS_LOCHHIH = 1325 , SYSZ_INS_LOCHHIHE = 1326 , SYSZ_INS_LOCHHIL = 1327 , SYSZ_INS_LOCHHILE = 1328 , SYSZ_INS_LOCHHILH = 1329 , SYSZ_INS_LOCHHIM = 1330 , SYSZ_INS_LOCHHINE = 1331 , SYSZ_INS_LOCHHINH = 1332 , SYSZ_INS_LOCHHINHE = 1333 , SYSZ_INS_LOCHHINL = 1334 , SYSZ_INS_LOCHHINLE = 1335 , SYSZ_INS_LOCHHINLH = 1336 , SYSZ_INS_LOCHHINM = 1337 , SYSZ_INS_LOCHHINO = 1338 , SYSZ_INS_LOCHHINP = 1339 , SYSZ_INS_LOCHHINZ = 1340 , SYSZ_INS_LOCHHIO = 1341 , SYSZ_INS_LOCHHIP = 1342 , SYSZ_INS_LOCHHIZ = 1343 , SYSZ_INS_LOCHI = 1344 , SYSZ_INS_LOCHIE = 1345 , SYSZ_INS_LOCHIH = 1346 , SYSZ_INS_LOCHIHE = 1347 , SYSZ_INS_LOCHIL = 1348 , SYSZ_INS_LOCHILE = 1349 , SYSZ_INS_LOCHILH = 1350 , SYSZ_INS_LOCHIM = 1351 , SYSZ_INS_LOCHINE = 1352 , SYSZ_INS_LOCHINH = 1353 , SYSZ_INS_LOCHINHE = 1354 , SYSZ_INS_LOCHINL = 1355 , SYSZ_INS_LOCHINLE = 1356 , SYSZ_INS_LOCHINLH = 1357 , SYSZ_INS_LOCHINM = 1358 , SYSZ_INS_LOCHINO = 1359 , SYSZ_INS_LOCHINP = 1360 , SYSZ_INS_LOCHINZ = 1361 , SYSZ_INS_LOCHIO = 1362 , SYSZ_INS_LOCHIP = 1363 , SYSZ_INS_LOCHIZ = 1364 , SYSZ_INS_LOCM = 1365 , SYSZ_INS_LOCNM = 1366 , SYSZ_INS_LOCNP = 1367 , SYSZ_INS_LOCNZ = 1368 , SYSZ_INS_LOCP = 1369 , SYSZ_INS_LOCRM = 1370 , SYSZ_INS_LOCRNM = 1371 , SYSZ_INS_LOCRNP = 1372 , SYSZ_INS_LOCRNZ = 1373 , SYSZ_INS_LOCRP = 1374 , SYSZ_INS_LOCRZ = 1375 , SYSZ_INS_LOCZ = 1376 , SYSZ_INS_LPCTL = 1377 , SYSZ_INS_LPD = 1378 , SYSZ_INS_LPDFR = 1379 , SYSZ_INS_LPDG = 1380 , SYSZ_INS_LPDR = 1381 , SYSZ_INS_LPER = 1382 , SYSZ_INS_LPP = 1383 , SYSZ_INS_LPQ = 1384 , SYSZ_INS_LPSW = 1385 , SYSZ_INS_LPSWE = 1386 , SYSZ_INS_LPTEA = 1387 , SYSZ_INS_LPXR = 1388 , SYSZ_INS_LRA = 1389 , SYSZ_INS_LRAG = 1390 , SYSZ_INS_LRAY = 1391 , SYSZ_INS_LRDR = 1392 , SYSZ_INS_LRER = 1393 , SYSZ_INS_LRVH = 1394 , SYSZ_INS_LSCTL = 1395 , SYSZ_INS_LTDR = 1396 , SYSZ_INS_LTDTR = 1397 , SYSZ_INS_LTER = 1398 , SYSZ_INS_LTXR = 1399 , SYSZ_INS_LTXTR = 1400 , SYSZ_INS_LURA = 1401 , SYSZ_INS_LURAG = 1402 , SYSZ_INS_LXD = 1403 , SYSZ_INS_LXDR = 1404 , SYSZ_INS_LXDTR = 1405 , SYSZ_INS_LXE = 1406 , SYSZ_INS_LXER = 1407 , SYSZ_INS_LZRF = 1408 , SYSZ_INS_LZRG = 1409 , SYSZ_INS_M = 1410 , SYSZ_INS_MAD = 1411 , SYSZ_INS_MADR = 1412 , SYSZ_INS_MAE = 1413 , SYSZ_INS_MAER = 1414 , SYSZ_INS_MAY = 1415 , SYSZ_INS_MAYH = 1416 , SYSZ_INS_MAYHR = 1417 , SYSZ_INS_MAYL = 1418 , SYSZ_INS_MAYLR = 1419 , SYSZ_INS_MAYR = 1420 , SYSZ_INS_MC = 1421 , SYSZ_INS_MD = 1422 , SYSZ_INS_MDE = 1423 , SYSZ_INS_MDER = 1424 , SYSZ_INS_MDR = 1425 , SYSZ_INS_MDTR = 1426 , SYSZ_INS_MDTRA = 1427 , SYSZ_INS_ME = 1428 , SYSZ_INS_MEE = 1429 , SYSZ_INS_MEER = 1430 , SYSZ_INS_MER = 1431 , SYSZ_INS_MFY = 1432 , SYSZ_INS_MG = 1433 , SYSZ_INS_MGH = 1434 , SYSZ_INS_MGRK = 1435 , SYSZ_INS_ML = 1436 , SYSZ_INS_MLR = 1437 , SYSZ_INS_MP = 1438 , SYSZ_INS_MR = 1439 , SYSZ_INS_MSC = 1440 , SYSZ_INS_MSCH = 1441 , SYSZ_INS_MSD = 1442 , SYSZ_INS_MSDR = 1443 , SYSZ_INS_MSE = 1444 , SYSZ_INS_MSER = 1445 , SYSZ_INS_MSGC = 1446 , SYSZ_INS_MSGRKC = 1447 , SYSZ_INS_MSRKC = 1448 , SYSZ_INS_MSTA = 1449 , SYSZ_INS_MVCDK = 1450 , SYSZ_INS_MVCIN = 1451 , SYSZ_INS_MVCK = 1452 , SYSZ_INS_MVCL = 1453 , SYSZ_INS_MVCLE = 1454 , SYSZ_INS_MVCLU = 1455 , SYSZ_INS_MVCOS = 1456 , SYSZ_INS_MVCP = 1457 , SYSZ_INS_MVCS = 1458 , SYSZ_INS_MVCSK = 1459 , SYSZ_INS_MVN = 1460 , SYSZ_INS_MVO = 1461 , SYSZ_INS_MVPG = 1462 , SYSZ_INS_MVZ = 1463 , SYSZ_INS_MXD = 1464 , SYSZ_INS_MXDR = 1465 , SYSZ_INS_MXR = 1466 , SYSZ_INS_MXTR = 1467 , SYSZ_INS_MXTRA = 1468 , SYSZ_INS_MY = 1469 , SYSZ_INS_MYH = 1470 , SYSZ_INS_MYHR = 1471 , SYSZ_INS_MYL = 1472 , SYSZ_INS_MYLR = 1473 , SYSZ_INS_MYR = 1474 , SYSZ_INS_NIAI = 1475 , SYSZ_INS_NTSTG = 1476 , SYSZ_INS_PACK = 1477 , SYSZ_INS_PALB = 1478 , SYSZ_INS_PC = 1479 , SYSZ_INS_PCC = 1480 , SYSZ_INS_PCKMO = 1481 , SYSZ_INS_PFMF = 1482 , SYSZ_INS_PFPO = 1483 , SYSZ_INS_PGIN = 1484 , SYSZ_INS_PGOUT = 1485 , SYSZ_INS_PKA = 1486 , SYSZ_INS_PKU = 1487 , SYSZ_INS_PLO = 1488 , SYSZ_INS_POPCNT = 1489 , SYSZ_INS_PPA = 1490 , SYSZ_INS_PPNO = 1491 , SYSZ_INS_PR = 1492 , SYSZ_INS_PRNO = 1493 , SYSZ_INS_PT = 1494 , SYSZ_INS_PTF = 1495 , SYSZ_INS_PTFF = 1496 , SYSZ_INS_PTI = 1497 , SYSZ_INS_PTLB = 1498 , SYSZ_INS_QADTR = 1499 , SYSZ_INS_QAXTR = 1500 , SYSZ_INS_QCTRI = 1501 , SYSZ_INS_QSI = 1502 , SYSZ_INS_RCHP = 1503 , SYSZ_INS_RISBGN = 1504 , SYSZ_INS_RP = 1505 , SYSZ_INS_RRBE = 1506 , SYSZ_INS_RRBM = 1507 , SYSZ_INS_RRDTR = 1508 , SYSZ_INS_RRXTR = 1509 , SYSZ_INS_RSCH = 1510 , SYSZ_INS_SAC = 1511 , SYSZ_INS_SACF = 1512 , SYSZ_INS_SAL = 1513 , SYSZ_INS_SAM24 = 1514 , SYSZ_INS_SAM31 = 1515 , SYSZ_INS_SAM64 = 1516 , SYSZ_INS_SAR = 1517 , SYSZ_INS_SCCTR = 1518 , SYSZ_INS_SCHM = 1519 , SYSZ_INS_SCK = 1520 , SYSZ_INS_SCKC = 1521 , SYSZ_INS_SCKPF = 1522 , SYSZ_INS_SD = 1523 , SYSZ_INS_SDR = 1524 , SYSZ_INS_SDTR = 1525 , SYSZ_INS_SDTRA = 1526 , SYSZ_INS_SE = 1527 , SYSZ_INS_SER = 1528 , SYSZ_INS_SFASR = 1529 , SYSZ_INS_SFPC = 1530 , SYSZ_INS_SGH = 1531 , SYSZ_INS_SHHHR = 1532 , SYSZ_INS_SHHLR = 1533 , SYSZ_INS_SIE = 1534 , SYSZ_INS_SIGA = 1535 , SYSZ_INS_SIGP = 1536 , SYSZ_INS_SLA = 1537 , SYSZ_INS_SLAG = 1538 , SYSZ_INS_SLAK = 1539 , SYSZ_INS_SLDA = 1540 , SYSZ_INS_SLDL = 1541 , SYSZ_INS_SLDT = 1542 , SYSZ_INS_SLHHHR = 1543 , SYSZ_INS_SLHHLR = 1544 , SYSZ_INS_SLXT = 1545 , SYSZ_INS_SP = 1546 , SYSZ_INS_SPCTR = 1547 , SYSZ_INS_SPKA = 1548 , SYSZ_INS_SPM = 1549 , SYSZ_INS_SPT = 1550 , SYSZ_INS_SPX = 1551 , SYSZ_INS_SQD = 1552 , SYSZ_INS_SQDR = 1553 , SYSZ_INS_SQE = 1554 , SYSZ_INS_SQER = 1555 , SYSZ_INS_SQXR = 1556 , SYSZ_INS_SRDA = 1557 , SYSZ_INS_SRDL = 1558 , SYSZ_INS_SRDT = 1559 , SYSZ_INS_SRNM = 1560 , SYSZ_INS_SRNMB = 1561 , SYSZ_INS_SRNMT = 1562 , SYSZ_INS_SRP = 1563 , SYSZ_INS_SRSTU = 1564 , SYSZ_INS_SRXT = 1565 , SYSZ_INS_SSAIR = 1566 , SYSZ_INS_SSAR = 1567 , SYSZ_INS_SSCH = 1568 , SYSZ_INS_SSKE = 1569 , SYSZ_INS_SSM = 1570 , SYSZ_INS_STAM = 1571 , SYSZ_INS_STAMY = 1572 , SYSZ_INS_STAP = 1573 , SYSZ_INS_STCK = 1574 , SYSZ_INS_STCKC = 1575 , SYSZ_INS_STCKE = 1576 , SYSZ_INS_STCKF = 1577 , SYSZ_INS_STCM = 1578 , SYSZ_INS_STCMH = 1579 , SYSZ_INS_STCMY = 1580 , SYSZ_INS_STCPS = 1581 , SYSZ_INS_STCRW = 1582 , SYSZ_INS_STCTG = 1583 , SYSZ_INS_STCTL = 1584 , SYSZ_INS_STFL = 1585 , SYSZ_INS_STFLE = 1586 , SYSZ_INS_STFPC = 1587 , SYSZ_INS_STGSC = 1588 , SYSZ_INS_STIDP = 1589 , SYSZ_INS_STM = 1590 , SYSZ_INS_STMH = 1591 , SYSZ_INS_STMY = 1592 , SYSZ_INS_STNSM = 1593 , SYSZ_INS_STOCFH = 1594 , SYSZ_INS_STOCFHE = 1595 , SYSZ_INS_STOCFHH = 1596 , SYSZ_INS_STOCFHHE = 1597 , SYSZ_INS_STOCFHL = 1598 , SYSZ_INS_STOCFHLE = 1599 , SYSZ_INS_STOCFHLH = 1600 , SYSZ_INS_STOCFHM = 1601 , SYSZ_INS_STOCFHNE = 1602 , SYSZ_INS_STOCFHNH = 1603 , SYSZ_INS_STOCFHNHE = 1604 , SYSZ_INS_STOCFHNL = 1605 , SYSZ_INS_STOCFHNLE = 1606 , SYSZ_INS_STOCFHNLH = 1607 , SYSZ_INS_STOCFHNM = 1608 , SYSZ_INS_STOCFHNO = 1609 , SYSZ_INS_STOCFHNP = 1610 , SYSZ_INS_STOCFHNZ = 1611 , SYSZ_INS_STOCFHO = 1612 , SYSZ_INS_STOCFHP = 1613 , SYSZ_INS_STOCFHZ = 1614 , SYSZ_INS_STOCGM = 1615 , SYSZ_INS_STOCGNM = 1616 , SYSZ_INS_STOCGNP = 1617 , SYSZ_INS_STOCGNZ = 1618 , SYSZ_INS_STOCGP = 1619 , SYSZ_INS_STOCGZ = 1620 , SYSZ_INS_STOCM = 1621 , SYSZ_INS_STOCNM = 1622 , SYSZ_INS_STOCNP = 1623 , SYSZ_INS_STOCNZ = 1624 , SYSZ_INS_STOCP = 1625 , SYSZ_INS_STOCZ = 1626 , SYSZ_INS_STOSM = 1627 , SYSZ_INS_STPQ = 1628 , SYSZ_INS_STPT = 1629 , SYSZ_INS_STPX = 1630 , SYSZ_INS_STRAG = 1631 , SYSZ_INS_STRVH = 1632 , SYSZ_INS_STSCH = 1633 , SYSZ_INS_STSI = 1634 , SYSZ_INS_STURA = 1635 , SYSZ_INS_STURG = 1636 , SYSZ_INS_SU = 1637 , SYSZ_INS_SUR = 1638 , SYSZ_INS_SVC = 1639 , SYSZ_INS_SW = 1640 , SYSZ_INS_SWR = 1641 , SYSZ_INS_SXR = 1642 , SYSZ_INS_SXTR = 1643 , SYSZ_INS_SXTRA = 1644 , SYSZ_INS_TABORT = 1645 , SYSZ_INS_TAM = 1646 , SYSZ_INS_TAR = 1647 , SYSZ_INS_TB = 1648 , SYSZ_INS_TBDR = 1649 , SYSZ_INS_TBEDR = 1650 , SYSZ_INS_TBEGIN = 1651 , SYSZ_INS_TBEGINC = 1652 , SYSZ_INS_TCDB = 1653 , SYSZ_INS_TCEB = 1654 , SYSZ_INS_TCXB = 1655 , SYSZ_INS_TDCDT = 1656 , SYSZ_INS_TDCET = 1657 , SYSZ_INS_TDCXT = 1658 , SYSZ_INS_TDGDT = 1659 , SYSZ_INS_TDGET = 1660 , SYSZ_INS_TDGXT = 1661 , SYSZ_INS_TEND = 1662 , SYSZ_INS_THDER = 1663 , SYSZ_INS_THDR = 1664 , SYSZ_INS_TP = 1665 , SYSZ_INS_TPI = 1666 , SYSZ_INS_TPROT = 1667 , SYSZ_INS_TR = 1668 , SYSZ_INS_TRACE = 1669 , SYSZ_INS_TRACG = 1670 , SYSZ_INS_TRAP2 = 1671 , SYSZ_INS_TRAP4 = 1672 , SYSZ_INS_TRE = 1673 , SYSZ_INS_TROO = 1674 , SYSZ_INS_TROT = 1675 , SYSZ_INS_TRT = 1676 , SYSZ_INS_TRTE = 1677 , SYSZ_INS_TRTO = 1678 , SYSZ_INS_TRTR = 1679 , SYSZ_INS_TRTRE = 1680 , SYSZ_INS_TRTT = 1681 , SYSZ_INS_TS = 1682 , SYSZ_INS_TSCH = 1683 , SYSZ_INS_UNPK = 1684 , SYSZ_INS_UNPKA = 1685 , SYSZ_INS_UNPKU = 1686 , SYSZ_INS_UPT = 1687 , SYSZ_INS_VA = 1688 , SYSZ_INS_VAB = 1689 , SYSZ_INS_VAC = 1690 , SYSZ_INS_VACC = 1691 , SYSZ_INS_VACCB = 1692 , SYSZ_INS_VACCC = 1693 , SYSZ_INS_VACCCQ = 1694 , SYSZ_INS_VACCF = 1695 , SYSZ_INS_VACCG = 1696 , SYSZ_INS_VACCH = 1697 , SYSZ_INS_VACCQ = 1698 , SYSZ_INS_VACQ = 1699 , SYSZ_INS_VAF = 1700 , SYSZ_INS_VAG = 1701 , SYSZ_INS_VAH = 1702 , SYSZ_INS_VAP = 1703 , SYSZ_INS_VAQ = 1704 , SYSZ_INS_VAVG = 1705 , SYSZ_INS_VAVGB = 1706 , SYSZ_INS_VAVGF = 1707 , SYSZ_INS_VAVGG = 1708 , SYSZ_INS_VAVGH = 1709 , SYSZ_INS_VAVGL = 1710 , SYSZ_INS_VAVGLB = 1711 , SYSZ_INS_VAVGLF = 1712 , SYSZ_INS_VAVGLG = 1713 , SYSZ_INS_VAVGLH = 1714 , SYSZ_INS_VBPERM = 1715 , SYSZ_INS_VCDG = 1716 , SYSZ_INS_VCDGB = 1717 , SYSZ_INS_VCDLG = 1718 , SYSZ_INS_VCDLGB = 1719 , SYSZ_INS_VCEQ = 1720 , SYSZ_INS_VCEQB = 1721 , SYSZ_INS_VCEQBS = 1722 , SYSZ_INS_VCEQF = 1723 , SYSZ_INS_VCEQFS = 1724 , SYSZ_INS_VCEQG = 1725 , SYSZ_INS_VCEQGS = 1726 , SYSZ_INS_VCEQH = 1727 , SYSZ_INS_VCEQHS = 1728 , SYSZ_INS_VCGD = 1729 , SYSZ_INS_VCGDB = 1730 , SYSZ_INS_VCH = 1731 , SYSZ_INS_VCHB = 1732 , SYSZ_INS_VCHBS = 1733 , SYSZ_INS_VCHF = 1734 , SYSZ_INS_VCHFS = 1735 , SYSZ_INS_VCHG = 1736 , SYSZ_INS_VCHGS = 1737 , SYSZ_INS_VCHH = 1738 , SYSZ_INS_VCHHS = 1739 , SYSZ_INS_VCHL = 1740 , SYSZ_INS_VCHLB = 1741 , SYSZ_INS_VCHLBS = 1742 , SYSZ_INS_VCHLF = 1743 , SYSZ_INS_VCHLFS = 1744 , SYSZ_INS_VCHLG = 1745 , SYSZ_INS_VCHLGS = 1746 , SYSZ_INS_VCHLH = 1747 , SYSZ_INS_VCHLHS = 1748 , SYSZ_INS_VCKSM = 1749 , SYSZ_INS_VCLGD = 1750 , SYSZ_INS_VCLGDB = 1751 , SYSZ_INS_VCLZ = 1752 , SYSZ_INS_VCLZB = 1753 , SYSZ_INS_VCLZF = 1754 , SYSZ_INS_VCLZG = 1755 , SYSZ_INS_VCLZH = 1756 , SYSZ_INS_VCP = 1757 , SYSZ_INS_VCTZ = 1758 , SYSZ_INS_VCTZB = 1759 , SYSZ_INS_VCTZF = 1760 , SYSZ_INS_VCTZG = 1761 , SYSZ_INS_VCTZH = 1762 , SYSZ_INS_VCVB = 1763 , SYSZ_INS_VCVBG = 1764 , SYSZ_INS_VCVD = 1765 , SYSZ_INS_VCVDG = 1766 , SYSZ_INS_VDP = 1767 , SYSZ_INS_VEC = 1768 , SYSZ_INS_VECB = 1769 , SYSZ_INS_VECF = 1770 , SYSZ_INS_VECG = 1771 , SYSZ_INS_VECH = 1772 , SYSZ_INS_VECL = 1773 , SYSZ_INS_VECLB = 1774 , SYSZ_INS_VECLF = 1775 , SYSZ_INS_VECLG = 1776 , SYSZ_INS_VECLH = 1777 , SYSZ_INS_VERIM = 1778 , SYSZ_INS_VERIMB = 1779 , SYSZ_INS_VERIMF = 1780 , SYSZ_INS_VERIMG = 1781 , SYSZ_INS_VERIMH = 1782 , SYSZ_INS_VERLL = 1783 , SYSZ_INS_VERLLB = 1784 , SYSZ_INS_VERLLF = 1785 , SYSZ_INS_VERLLG = 1786 , SYSZ_INS_VERLLH = 1787 , SYSZ_INS_VERLLV = 1788 , SYSZ_INS_VERLLVB = 1789 , SYSZ_INS_VERLLVF = 1790 , SYSZ_INS_VERLLVG = 1791 , SYSZ_INS_VERLLVH = 1792 , SYSZ_INS_VESL = 1793 , SYSZ_INS_VESLB = 1794 , SYSZ_INS_VESLF = 1795 , SYSZ_INS_VESLG = 1796 , SYSZ_INS_VESLH = 1797 , SYSZ_INS_VESLV = 1798 , SYSZ_INS_VESLVB = 1799 , SYSZ_INS_VESLVF = 1800 , SYSZ_INS_VESLVG = 1801 , SYSZ_INS_VESLVH = 1802 , SYSZ_INS_VESRA = 1803 , SYSZ_INS_VESRAB = 1804 , SYSZ_INS_VESRAF = 1805 , SYSZ_INS_VESRAG = 1806 , SYSZ_INS_VESRAH = 1807 , SYSZ_INS_VESRAV = 1808 , SYSZ_INS_VESRAVB = 1809 , SYSZ_INS_VESRAVF = 1810 , SYSZ_INS_VESRAVG = 1811 , SYSZ_INS_VESRAVH = 1812 , SYSZ_INS_VESRL = 1813 , SYSZ_INS_VESRLB = 1814 , SYSZ_INS_VESRLF = 1815 , SYSZ_INS_VESRLG = 1816 , SYSZ_INS_VESRLH = 1817 , SYSZ_INS_VESRLV = 1818 , SYSZ_INS_VESRLVB = 1819 , SYSZ_INS_VESRLVF = 1820 , SYSZ_INS_VESRLVG = 1821 , SYSZ_INS_VESRLVH = 1822 , SYSZ_INS_VFA = 1823 , SYSZ_INS_VFADB = 1824 , SYSZ_INS_VFAE = 1825 , SYSZ_INS_VFAEB = 1826 , SYSZ_INS_VFAEBS = 1827 , SYSZ_INS_VFAEF = 1828 , SYSZ_INS_VFAEFS = 1829 , SYSZ_INS_VFAEH = 1830 , SYSZ_INS_VFAEHS = 1831 , SYSZ_INS_VFAEZB = 1832 , SYSZ_INS_VFAEZBS = 1833 , SYSZ_INS_VFAEZF = 1834 , SYSZ_INS_VFAEZFS = 1835 , SYSZ_INS_VFAEZH = 1836 , SYSZ_INS_VFAEZHS = 1837 , SYSZ_INS_VFASB = 1838 , SYSZ_INS_VFCE = 1839 , SYSZ_INS_VFCEDB = 1840 , SYSZ_INS_VFCEDBS = 1841 , SYSZ_INS_VFCESB = 1842 , SYSZ_INS_VFCESBS = 1843 , SYSZ_INS_VFCH = 1844 , SYSZ_INS_VFCHDB = 1845 , SYSZ_INS_VFCHDBS = 1846 , SYSZ_INS_VFCHE = 1847 , SYSZ_INS_VFCHEDB = 1848 , SYSZ_INS_VFCHEDBS = 1849 , SYSZ_INS_VFCHESB = 1850 , SYSZ_INS_VFCHESBS = 1851 , SYSZ_INS_VFCHSB = 1852 , SYSZ_INS_VFCHSBS = 1853 , SYSZ_INS_VFD = 1854 , SYSZ_INS_VFDDB = 1855 , SYSZ_INS_VFDSB = 1856 , SYSZ_INS_VFEE = 1857 , SYSZ_INS_VFEEB = 1858 , SYSZ_INS_VFEEBS = 1859 , SYSZ_INS_VFEEF = 1860 , SYSZ_INS_VFEEFS = 1861 , SYSZ_INS_VFEEH = 1862 , SYSZ_INS_VFEEHS = 1863 , SYSZ_INS_VFEEZB = 1864 , SYSZ_INS_VFEEZBS = 1865 , SYSZ_INS_VFEEZF = 1866 , SYSZ_INS_VFEEZFS = 1867 , SYSZ_INS_VFEEZH = 1868 , SYSZ_INS_VFEEZHS = 1869 , SYSZ_INS_VFENE = 1870 , SYSZ_INS_VFENEB = 1871 , SYSZ_INS_VFENEBS = 1872 , SYSZ_INS_VFENEF = 1873 , SYSZ_INS_VFENEFS = 1874 , SYSZ_INS_VFENEH = 1875 , SYSZ_INS_VFENEHS = 1876 , SYSZ_INS_VFENEZB = 1877 , SYSZ_INS_VFENEZBS = 1878 , SYSZ_INS_VFENEZF = 1879 , SYSZ_INS_VFENEZFS = 1880 , SYSZ_INS_VFENEZH = 1881 , SYSZ_INS_VFENEZHS = 1882 , SYSZ_INS_VFI = 1883 , SYSZ_INS_VFIDB = 1884 , SYSZ_INS_VFISB = 1885 , SYSZ_INS_VFKEDB = 1886 , SYSZ_INS_VFKEDBS = 1887 , SYSZ_INS_VFKESB = 1888 , SYSZ_INS_VFKESBS = 1889 , SYSZ_INS_VFKHDB = 1890 , SYSZ_INS_VFKHDBS = 1891 , SYSZ_INS_VFKHEDB = 1892 , SYSZ_INS_VFKHEDBS = 1893 , SYSZ_INS_VFKHESB = 1894 , SYSZ_INS_VFKHESBS = 1895 , SYSZ_INS_VFKHSB = 1896 , SYSZ_INS_VFKHSBS = 1897 , SYSZ_INS_VFLCDB = 1898 , SYSZ_INS_VFLCSB = 1899 , SYSZ_INS_VFLL = 1900 , SYSZ_INS_VFLLS = 1901 , SYSZ_INS_VFLNDB = 1902 , SYSZ_INS_VFLNSB = 1903 , SYSZ_INS_VFLPDB = 1904 , SYSZ_INS_VFLPSB = 1905 , SYSZ_INS_VFLR = 1906 , SYSZ_INS_VFLRD = 1907 , SYSZ_INS_VFM = 1908 , SYSZ_INS_VFMA = 1909 , SYSZ_INS_VFMADB = 1910 , SYSZ_INS_VFMASB = 1911 , SYSZ_INS_VFMAX = 1912 , SYSZ_INS_VFMAXDB = 1913 , SYSZ_INS_VFMAXSB = 1914 , SYSZ_INS_VFMDB = 1915 , SYSZ_INS_VFMIN = 1916 , SYSZ_INS_VFMINDB = 1917 , SYSZ_INS_VFMINSB = 1918 , SYSZ_INS_VFMS = 1919 , SYSZ_INS_VFMSB = 1920 , SYSZ_INS_VFMSDB = 1921 , SYSZ_INS_VFMSSB = 1922 , SYSZ_INS_VFNMA = 1923 , SYSZ_INS_VFNMADB = 1924 , SYSZ_INS_VFNMASB = 1925 , SYSZ_INS_VFNMS = 1926 , SYSZ_INS_VFNMSDB = 1927 , SYSZ_INS_VFNMSSB = 1928 , SYSZ_INS_VFPSO = 1929 , SYSZ_INS_VFPSODB = 1930 , SYSZ_INS_VFPSOSB = 1931 , SYSZ_INS_VFS = 1932 , SYSZ_INS_VFSDB = 1933 , SYSZ_INS_VFSQ = 1934 , SYSZ_INS_VFSQDB = 1935 , SYSZ_INS_VFSQSB = 1936 , SYSZ_INS_VFSSB = 1937 , SYSZ_INS_VFTCI = 1938 , SYSZ_INS_VFTCIDB = 1939 , SYSZ_INS_VFTCISB = 1940 , SYSZ_INS_VGBM = 1941 , SYSZ_INS_VGEF = 1942 , SYSZ_INS_VGEG = 1943 , SYSZ_INS_VGFM = 1944 , SYSZ_INS_VGFMA = 1945 , SYSZ_INS_VGFMAB = 1946 , SYSZ_INS_VGFMAF = 1947 , SYSZ_INS_VGFMAG = 1948 , SYSZ_INS_VGFMAH = 1949 , SYSZ_INS_VGFMB = 1950 , SYSZ_INS_VGFMF = 1951 , SYSZ_INS_VGFMG = 1952 , SYSZ_INS_VGFMH = 1953 , SYSZ_INS_VGM = 1954 , SYSZ_INS_VGMB = 1955 , SYSZ_INS_VGMF = 1956 , SYSZ_INS_VGMG = 1957 , SYSZ_INS_VGMH = 1958 , SYSZ_INS_VISTR = 1959 , SYSZ_INS_VISTRB = 1960 , SYSZ_INS_VISTRBS = 1961 , SYSZ_INS_VISTRF = 1962 , SYSZ_INS_VISTRFS = 1963 , SYSZ_INS_VISTRH = 1964 , SYSZ_INS_VISTRHS = 1965 , SYSZ_INS_VL = 1966 , SYSZ_INS_VLBB = 1967 , SYSZ_INS_VLC = 1968 , SYSZ_INS_VLCB = 1969 , SYSZ_INS_VLCF = 1970 , SYSZ_INS_VLCG = 1971 , SYSZ_INS_VLCH = 1972 , SYSZ_INS_VLDE = 1973 , SYSZ_INS_VLDEB = 1974 , SYSZ_INS_VLEB = 1975 , SYSZ_INS_VLED = 1976 , SYSZ_INS_VLEDB = 1977 , SYSZ_INS_VLEF = 1978 , SYSZ_INS_VLEG = 1979 , SYSZ_INS_VLEH = 1980 , SYSZ_INS_VLEIB = 1981 , SYSZ_INS_VLEIF = 1982 , SYSZ_INS_VLEIG = 1983 , SYSZ_INS_VLEIH = 1984 , SYSZ_INS_VLGV = 1985 , SYSZ_INS_VLGVB = 1986 , SYSZ_INS_VLGVF = 1987 , SYSZ_INS_VLGVG = 1988 , SYSZ_INS_VLGVH = 1989 , SYSZ_INS_VLIP = 1990 , SYSZ_INS_VLL = 1991 , SYSZ_INS_VLLEZ = 1992 , SYSZ_INS_VLLEZB = 1993 , SYSZ_INS_VLLEZF = 1994 , SYSZ_INS_VLLEZG = 1995 , SYSZ_INS_VLLEZH = 1996 , SYSZ_INS_VLLEZLF = 1997 , SYSZ_INS_VLM = 1998 , SYSZ_INS_VLP = 1999 , SYSZ_INS_VLPB = 2000 , SYSZ_INS_VLPF = 2001 , SYSZ_INS_VLPG = 2002 , SYSZ_INS_VLPH = 2003 , SYSZ_INS_VLR = 2004 , SYSZ_INS_VLREP = 2005 , SYSZ_INS_VLREPB = 2006 , SYSZ_INS_VLREPF = 2007 , SYSZ_INS_VLREPG = 2008 , SYSZ_INS_VLREPH = 2009 , SYSZ_INS_VLRL = 2010 , SYSZ_INS_VLRLR = 2011 , SYSZ_INS_VLVG = 2012 , SYSZ_INS_VLVGB = 2013 , SYSZ_INS_VLVGF = 2014 , SYSZ_INS_VLVGG = 2015 , SYSZ_INS_VLVGH = 2016 , SYSZ_INS_VLVGP = 2017 , SYSZ_INS_VMAE = 2018 , SYSZ_INS_VMAEB = 2019 , SYSZ_INS_VMAEF = 2020 , SYSZ_INS_VMAEH = 2021 , SYSZ_INS_VMAH = 2022 , SYSZ_INS_VMAHB = 2023 , SYSZ_INS_VMAHF = 2024 , SYSZ_INS_VMAHH = 2025 , SYSZ_INS_VMAL = 2026 , SYSZ_INS_VMALB = 2027 , SYSZ_INS_VMALE = 2028 , SYSZ_INS_VMALEB = 2029 , SYSZ_INS_VMALEF = 2030 , SYSZ_INS_VMALEH = 2031 , SYSZ_INS_VMALF = 2032 , SYSZ_INS_VMALH = 2033 , SYSZ_INS_VMALHB = 2034 , SYSZ_INS_VMALHF = 2035 , SYSZ_INS_VMALHH = 2036 , SYSZ_INS_VMALHW = 2037 , SYSZ_INS_VMALO = 2038 , SYSZ_INS_VMALOB = 2039 , SYSZ_INS_VMALOF = 2040 , SYSZ_INS_VMALOH = 2041 , SYSZ_INS_VMAO = 2042 , SYSZ_INS_VMAOB = 2043 , SYSZ_INS_VMAOF = 2044 , SYSZ_INS_VMAOH = 2045 , SYSZ_INS_VME = 2046 , SYSZ_INS_VMEB = 2047 , SYSZ_INS_VMEF = 2048 , SYSZ_INS_VMEH = 2049 , SYSZ_INS_VMH = 2050 , SYSZ_INS_VMHB = 2051 , SYSZ_INS_VMHF = 2052 , SYSZ_INS_VMHH = 2053 , SYSZ_INS_VML = 2054 , SYSZ_INS_VMLB = 2055 , SYSZ_INS_VMLE = 2056 , SYSZ_INS_VMLEB = 2057 , SYSZ_INS_VMLEF = 2058 , SYSZ_INS_VMLEH = 2059 , SYSZ_INS_VMLF = 2060 , SYSZ_INS_VMLH = 2061 , SYSZ_INS_VMLHB = 2062 , SYSZ_INS_VMLHF = 2063 , SYSZ_INS_VMLHH = 2064 , SYSZ_INS_VMLHW = 2065 , SYSZ_INS_VMLO = 2066 , SYSZ_INS_VMLOB = 2067 , SYSZ_INS_VMLOF = 2068 , SYSZ_INS_VMLOH = 2069 , SYSZ_INS_VMN = 2070 , SYSZ_INS_VMNB = 2071 , SYSZ_INS_VMNF = 2072 , SYSZ_INS_VMNG = 2073 , SYSZ_INS_VMNH = 2074 , SYSZ_INS_VMNL = 2075 , SYSZ_INS_VMNLB = 2076 , SYSZ_INS_VMNLF = 2077 , SYSZ_INS_VMNLG = 2078 , SYSZ_INS_VMNLH = 2079 , SYSZ_INS_VMO = 2080 , SYSZ_INS_VMOB = 2081 , SYSZ_INS_VMOF = 2082 , SYSZ_INS_VMOH = 2083 , SYSZ_INS_VMP = 2084 , SYSZ_INS_VMRH = 2085 , SYSZ_INS_VMRHB = 2086 , SYSZ_INS_VMRHF = 2087 , SYSZ_INS_VMRHG = 2088 , SYSZ_INS_VMRHH = 2089 , SYSZ_INS_VMRL = 2090 , SYSZ_INS_VMRLB = 2091 , SYSZ_INS_VMRLF = 2092 , SYSZ_INS_VMRLG = 2093 , SYSZ_INS_VMRLH = 2094 , SYSZ_INS_VMSL = 2095 , SYSZ_INS_VMSLG = 2096 , SYSZ_INS_VMSP = 2097 , SYSZ_INS_VMX = 2098 , SYSZ_INS_VMXB = 2099 , SYSZ_INS_VMXF = 2100 , SYSZ_INS_VMXG = 2101 , SYSZ_INS_VMXH = 2102 , SYSZ_INS_VMXL = 2103 , SYSZ_INS_VMXLB = 2104 , SYSZ_INS_VMXLF = 2105 , SYSZ_INS_VMXLG = 2106 , SYSZ_INS_VMXLH = 2107 , SYSZ_INS_VN = 2108 , SYSZ_INS_VNC = 2109 , SYSZ_INS_VNN = 2110 , SYSZ_INS_VNO = 2111 , SYSZ_INS_VNX = 2112 , SYSZ_INS_VO = 2113 , SYSZ_INS_VOC = 2114 , SYSZ_INS_VONE = 2115 , SYSZ_INS_VPDI = 2116 , SYSZ_INS_VPERM = 2117 , SYSZ_INS_VPK = 2118 , SYSZ_INS_VPKF = 2119 , SYSZ_INS_VPKG = 2120 , SYSZ_INS_VPKH = 2121 , SYSZ_INS_VPKLS = 2122 , SYSZ_INS_VPKLSF = 2123 , SYSZ_INS_VPKLSFS = 2124 , SYSZ_INS_VPKLSG = 2125 , SYSZ_INS_VPKLSGS = 2126 , SYSZ_INS_VPKLSH = 2127 , SYSZ_INS_VPKLSHS = 2128 , SYSZ_INS_VPKS = 2129 , SYSZ_INS_VPKSF = 2130 , SYSZ_INS_VPKSFS = 2131 , SYSZ_INS_VPKSG = 2132 , SYSZ_INS_VPKSGS = 2133 , SYSZ_INS_VPKSH = 2134 , SYSZ_INS_VPKSHS = 2135 , SYSZ_INS_VPKZ = 2136 , SYSZ_INS_VPOPCT = 2137 , SYSZ_INS_VPOPCTB = 2138 , SYSZ_INS_VPOPCTF = 2139 , SYSZ_INS_VPOPCTG = 2140 , SYSZ_INS_VPOPCTH = 2141 , SYSZ_INS_VPSOP = 2142 , SYSZ_INS_VREP = 2143 , SYSZ_INS_VREPB = 2144 , SYSZ_INS_VREPF = 2145 , SYSZ_INS_VREPG = 2146 , SYSZ_INS_VREPH = 2147 , SYSZ_INS_VREPI = 2148 , SYSZ_INS_VREPIB = 2149 , SYSZ_INS_VREPIF = 2150 , SYSZ_INS_VREPIG = 2151 , SYSZ_INS_VREPIH = 2152 , SYSZ_INS_VRP = 2153 , SYSZ_INS_VS = 2154 , SYSZ_INS_VSB = 2155 , SYSZ_INS_VSBCBI = 2156 , SYSZ_INS_VSBCBIQ = 2157 , SYSZ_INS_VSBI = 2158 , SYSZ_INS_VSBIQ = 2159 , SYSZ_INS_VSCBI = 2160 , SYSZ_INS_VSCBIB = 2161 , SYSZ_INS_VSCBIF = 2162 , SYSZ_INS_VSCBIG = 2163 , SYSZ_INS_VSCBIH = 2164 , SYSZ_INS_VSCBIQ = 2165 , SYSZ_INS_VSCEF = 2166 , SYSZ_INS_VSCEG = 2167 , SYSZ_INS_VSDP = 2168 , SYSZ_INS_VSEG = 2169 , SYSZ_INS_VSEGB = 2170 , SYSZ_INS_VSEGF = 2171 , SYSZ_INS_VSEGH = 2172 , SYSZ_INS_VSEL = 2173 , SYSZ_INS_VSF = 2174 , SYSZ_INS_VSG = 2175 , SYSZ_INS_VSH = 2176 , SYSZ_INS_VSL = 2177 , SYSZ_INS_VSLB = 2178 , SYSZ_INS_VSLDB = 2179 , SYSZ_INS_VSP = 2180 , SYSZ_INS_VSQ = 2181 , SYSZ_INS_VSRA = 2182 , SYSZ_INS_VSRAB = 2183 , SYSZ_INS_VSRL = 2184 , SYSZ_INS_VSRLB = 2185 , SYSZ_INS_VSRP = 2186 , SYSZ_INS_VST = 2187 , SYSZ_INS_VSTEB = 2188 , SYSZ_INS_VSTEF = 2189 , SYSZ_INS_VSTEG = 2190 , SYSZ_INS_VSTEH = 2191 , SYSZ_INS_VSTL = 2192 , SYSZ_INS_VSTM = 2193 , SYSZ_INS_VSTRC = 2194 , SYSZ_INS_VSTRCB = 2195 , SYSZ_INS_VSTRCBS = 2196 , SYSZ_INS_VSTRCF = 2197 , SYSZ_INS_VSTRCFS = 2198 , SYSZ_INS_VSTRCH = 2199 , SYSZ_INS_VSTRCHS = 2200 , SYSZ_INS_VSTRCZB = 2201 , SYSZ_INS_VSTRCZBS = 2202 , SYSZ_INS_VSTRCZF = 2203 , SYSZ_INS_VSTRCZFS = 2204 , SYSZ_INS_VSTRCZH = 2205 , SYSZ_INS_VSTRCZHS = 2206 , SYSZ_INS_VSTRL = 2207 , SYSZ_INS_VSTRLR = 2208 , SYSZ_INS_VSUM = 2209 , SYSZ_INS_VSUMB = 2210 , SYSZ_INS_VSUMG = 2211 , SYSZ_INS_VSUMGF = 2212 , SYSZ_INS_VSUMGH = 2213 , SYSZ_INS_VSUMH = 2214 , SYSZ_INS_VSUMQ = 2215 , SYSZ_INS_VSUMQF = 2216 , SYSZ_INS_VSUMQG = 2217 , SYSZ_INS_VTM = 2218 , SYSZ_INS_VTP = 2219 , SYSZ_INS_VUPH = 2220 , SYSZ_INS_VUPHB = 2221 , SYSZ_INS_VUPHF = 2222 , SYSZ_INS_VUPHH = 2223 , SYSZ_INS_VUPKZ = 2224 , SYSZ_INS_VUPL = 2225 , SYSZ_INS_VUPLB = 2226 , SYSZ_INS_VUPLF = 2227 , SYSZ_INS_VUPLH = 2228 , SYSZ_INS_VUPLHB = 2229 , SYSZ_INS_VUPLHF = 2230 , SYSZ_INS_VUPLHH = 2231 , SYSZ_INS_VUPLHW = 2232 , SYSZ_INS_VUPLL = 2233 , SYSZ_INS_VUPLLB = 2234 , SYSZ_INS_VUPLLF = 2235 , SYSZ_INS_VUPLLH = 2236 , SYSZ_INS_VX = 2237 , SYSZ_INS_VZERO = 2238 , SYSZ_INS_WCDGB = 2239 , SYSZ_INS_WCDLGB = 2240 , SYSZ_INS_WCGDB = 2241 , SYSZ_INS_WCLGDB = 2242 , SYSZ_INS_WFADB = 2243 , SYSZ_INS_WFASB = 2244 , SYSZ_INS_WFAXB = 2245 , SYSZ_INS_WFC = 2246 , SYSZ_INS_WFCDB = 2247 , SYSZ_INS_WFCEDB = 2248 , SYSZ_INS_WFCEDBS = 2249 , SYSZ_INS_WFCESB = 2250 , SYSZ_INS_WFCESBS = 2251 , SYSZ_INS_WFCEXB = 2252 , SYSZ_INS_WFCEXBS = 2253 , SYSZ_INS_WFCHDB = 2254 , SYSZ_INS_WFCHDBS = 2255 , SYSZ_INS_WFCHEDB = 2256 , SYSZ_INS_WFCHEDBS = 2257 , SYSZ_INS_WFCHESB = 2258 , SYSZ_INS_WFCHESBS = 2259 , SYSZ_INS_WFCHEXB = 2260 , SYSZ_INS_WFCHEXBS = 2261 , SYSZ_INS_WFCHSB = 2262 , SYSZ_INS_WFCHSBS = 2263 , SYSZ_INS_WFCHXB = 2264 , SYSZ_INS_WFCHXBS = 2265 , SYSZ_INS_WFCSB = 2266 , SYSZ_INS_WFCXB = 2267 , SYSZ_INS_WFDDB = 2268 , SYSZ_INS_WFDSB = 2269 , SYSZ_INS_WFDXB = 2270 , SYSZ_INS_WFIDB = 2271 , SYSZ_INS_WFISB = 2272 , SYSZ_INS_WFIXB = 2273 , SYSZ_INS_WFK = 2274 , SYSZ_INS_WFKDB = 2275 , SYSZ_INS_WFKEDB = 2276 , SYSZ_INS_WFKEDBS = 2277 , SYSZ_INS_WFKESB = 2278 , SYSZ_INS_WFKESBS = 2279 , SYSZ_INS_WFKEXB = 2280 , SYSZ_INS_WFKEXBS = 2281 , SYSZ_INS_WFKHDB = 2282 , SYSZ_INS_WFKHDBS = 2283 , SYSZ_INS_WFKHEDB = 2284 , SYSZ_INS_WFKHEDBS = 2285 , SYSZ_INS_WFKHESB = 2286 , SYSZ_INS_WFKHESBS = 2287 , SYSZ_INS_WFKHEXB = 2288 , SYSZ_INS_WFKHEXBS = 2289 , SYSZ_INS_WFKHSB = 2290 , SYSZ_INS_WFKHSBS = 2291 , SYSZ_INS_WFKHXB = 2292 , SYSZ_INS_WFKHXBS = 2293 , SYSZ_INS_WFKSB = 2294 , SYSZ_INS_WFKXB = 2295 , SYSZ_INS_WFLCDB = 2296 , SYSZ_INS_WFLCSB = 2297 , SYSZ_INS_WFLCXB = 2298 , SYSZ_INS_WFLLD = 2299 , SYSZ_INS_WFLLS = 2300 , SYSZ_INS_WFLNDB = 2301 , SYSZ_INS_WFLNSB = 2302 , SYSZ_INS_WFLNXB = 2303 , SYSZ_INS_WFLPDB = 2304 , SYSZ_INS_WFLPSB = 2305 , SYSZ_INS_WFLPXB = 2306 , SYSZ_INS_WFLRD = 2307 , SYSZ_INS_WFLRX = 2308 , SYSZ_INS_WFMADB = 2309 , SYSZ_INS_WFMASB = 2310 , SYSZ_INS_WFMAXB = 2311 , SYSZ_INS_WFMAXDB = 2312 , SYSZ_INS_WFMAXSB = 2313 , SYSZ_INS_WFMAXXB = 2314 , SYSZ_INS_WFMDB = 2315 , SYSZ_INS_WFMINDB = 2316 , SYSZ_INS_WFMINSB = 2317 , SYSZ_INS_WFMINXB = 2318 , SYSZ_INS_WFMSB = 2319 , SYSZ_INS_WFMSDB = 2320 , SYSZ_INS_WFMSSB = 2321 , SYSZ_INS_WFMSXB = 2322 , SYSZ_INS_WFMXB = 2323 , SYSZ_INS_WFNMADB = 2324 , SYSZ_INS_WFNMASB = 2325 , SYSZ_INS_WFNMAXB = 2326 , SYSZ_INS_WFNMSDB = 2327 , SYSZ_INS_WFNMSSB = 2328 , SYSZ_INS_WFNMSXB = 2329 , SYSZ_INS_WFPSODB = 2330 , SYSZ_INS_WFPSOSB = 2331 , SYSZ_INS_WFPSOXB = 2332 , SYSZ_INS_WFSDB = 2333 , SYSZ_INS_WFSQDB = 2334 , SYSZ_INS_WFSQSB = 2335 , SYSZ_INS_WFSQXB = 2336 , SYSZ_INS_WFSSB = 2337 , SYSZ_INS_WFSXB = 2338 , SYSZ_INS_WFTCIDB = 2339 , SYSZ_INS_WFTCISB = 2340 , SYSZ_INS_WFTCIXB = 2341 , SYSZ_INS_WLDEB = 2342 , SYSZ_INS_WLEDB = 2343 , SYSZ_INS_XSCH = 2344 , SYSZ_INS_ZAP = 2345 , SYSZ_INS_ENDING = 2346 , } # [repr (u32)] # [doc = " Group of SystemZ instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn_group { # [doc = "< = CS_GRP_INVALID"] SYSZ_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SYSZ_GRP_JUMP = 1 , SYSZ_GRP_DISTINCTOPS = 128 , SYSZ_GRP_FPEXTENSION = 129 , SYSZ_GRP_HIGHWORD = 130 , SYSZ_GRP_INTERLOCKEDACCESS1 = 131 , SYSZ_GRP_LOADSTOREONCOND = 132 , SYSZ_GRP_DFPPACKEDCONVERSION = 133 , SYSZ_GRP_DFPZONEDCONVERSION = 134 , SYSZ_GRP_ENHANCEDDAT2 = 135 , SYSZ_GRP_EXECUTIONHINT = 136 , SYSZ_GRP_GUARDEDSTORAGE = 137 , SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 , SYSZ_GRP_LOADANDTRAP = 139 , SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 , SYSZ_GRP_LOADSTOREONCOND2 = 141 , SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 , SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 , SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 , SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 , SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 , SYSZ_GRP_NOVECTOR = 149 , SYSZ_GRP_POPULATIONCOUNT = 150 , SYSZ_GRP_PROCESSORASSIST = 151 , SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 , SYSZ_GRP_TRANSACTIONALEXECUTION = 153 , SYSZ_GRP_VECTOR = 154 , SYSZ_GRP_VECTORENHANCEMENTS1 = 155 , SYSZ_GRP_VECTORPACKEDDECIMAL = 156 , SYSZ_GRP_ENDING = 157 , } # [repr (u32)] # [doc = " X86 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_reg { X86_REG_INVALID = 0 , X86_REG_AH = 1 , X86_REG_AL = 2 , X86_REG_AX = 3 , X86_REG_BH = 4 , X86_REG_BL = 5 , X86_REG_BP = 6 , X86_REG_BPL = 7 , X86_REG_BX = 8 , X86_REG_CH = 9 , X86_REG_CL = 10 , X86_REG_CS = 11 , X86_REG_CX = 12 , X86_REG_DH = 13 , X86_REG_DI = 14 , X86_REG_DIL = 15 , X86_REG_DL = 16 , X86_REG_DS = 17 , X86_REG_DX = 18 , X86_REG_EAX = 19 , X86_REG_EBP = 20 , X86_REG_EBX = 21 , X86_REG_ECX = 22 , X86_REG_EDI = 23 , X86_REG_EDX = 24 , X86_REG_EFLAGS = 25 , X86_REG_EIP = 26 , X86_REG_EIZ = 27 , X86_REG_ES = 28 , X86_REG_ESI = 29 , X86_REG_ESP = 30 , X86_REG_FPSW = 31 , X86_REG_FS = 32 , X86_REG_GS = 33 , X86_REG_IP = 34 , X86_REG_RAX = 35 , X86_REG_RBP = 36 , X86_REG_RBX = 37 , X86_REG_RCX = 38 , X86_REG_RDI = 39 , X86_REG_RDX = 40 , X86_REG_RIP = 41 , X86_REG_RIZ = 42 , X86_REG_RSI = 43 , X86_REG_RSP = 44 , X86_REG_SI = 45 , X86_REG_SIL = 46 , X86_REG_SP = 47 , X86_REG_SPL = 48 , X86_REG_SS = 49 , X86_REG_CR0 = 50 , X86_REG_CR1 = 51 , X86_REG_CR2 = 52 , X86_REG_CR3 = 53 , X86_REG_CR4 = 54 , X86_REG_CR5 = 55 , X86_REG_CR6 = 56 , X86_REG_CR7 = 57 , X86_REG_CR8 = 58 , X86_REG_CR9 = 59 , X86_REG_CR10 = 60 , X86_REG_CR11 = 61 , X86_REG_CR12 = 62 , X86_REG_CR13 = 63 , X86_REG_CR14 = 64 , X86_REG_CR15 = 65 , X86_REG_DR0 = 66 , X86_REG_DR1 = 67 , X86_REG_DR2 = 68 , X86_REG_DR3 = 69 , X86_REG_DR4 = 70 , X86_REG_DR5 = 71 , X86_REG_DR6 = 72 , X86_REG_DR7 = 73 , X86_REG_DR8 = 74 , X86_REG_DR9 = 75 , X86_REG_DR10 = 76 , X86_REG_DR11 = 77 , X86_REG_DR12 = 78 , X86_REG_DR13 = 79 , X86_REG_DR14 = 80 , X86_REG_DR15 = 81 , X86_REG_FP0 = 82 , X86_REG_FP1 = 83 , X86_REG_FP2 = 84 , X86_REG_FP3 = 85 , X86_REG_FP4 = 86 , X86_REG_FP5 = 87 , X86_REG_FP6 = 88 , X86_REG_FP7 = 89 , X86_REG_K0 = 90 , X86_REG_K1 = 91 , X86_REG_K2 = 92 , X86_REG_K3 = 93 , X86_REG_K4 = 94 , X86_REG_K5 = 95 , X86_REG_K6 = 96 , X86_REG_K7 = 97 , X86_REG_MM0 = 98 , X86_REG_MM1 = 99 , X86_REG_MM2 = 100 , X86_REG_MM3 = 101 , X86_REG_MM4 = 102 , X86_REG_MM5 = 103 , X86_REG_MM6 = 104 , X86_REG_MM7 = 105 , X86_REG_R8 = 106 , X86_REG_R9 = 107 , X86_REG_R10 = 108 , X86_REG_R11 = 109 , X86_REG_R12 = 110 , X86_REG_R13 = 111 , X86_REG_R14 = 112 , X86_REG_R15 = 113 , X86_REG_ST0 = 114 , X86_REG_ST1 = 115 , X86_REG_ST2 = 116 , X86_REG_ST3 = 117 , X86_REG_ST4 = 118 , X86_REG_ST5 = 119 , X86_REG_ST6 = 120 , X86_REG_ST7 = 121 , X86_REG_XMM0 = 122 , X86_REG_XMM1 = 123 , X86_REG_XMM2 = 124 , X86_REG_XMM3 = 125 , X86_REG_XMM4 = 126 , X86_REG_XMM5 = 127 , X86_REG_XMM6 = 128 , X86_REG_XMM7 = 129 , X86_REG_XMM8 = 130 , X86_REG_XMM9 = 131 , X86_REG_XMM10 = 132 , X86_REG_XMM11 = 133 , X86_REG_XMM12 = 134 , X86_REG_XMM13 = 135 , X86_REG_XMM14 = 136 , X86_REG_XMM15 = 137 , X86_REG_XMM16 = 138 , X86_REG_XMM17 = 139 , X86_REG_XMM18 = 140 , X86_REG_XMM19 = 141 , X86_REG_XMM20 = 142 , X86_REG_XMM21 = 143 , X86_REG_XMM22 = 144 , X86_REG_XMM23 = 145 , X86_REG_XMM24 = 146 , X86_REG_XMM25 = 147 , X86_REG_XMM26 = 148 , X86_REG_XMM27 = 149 , X86_REG_XMM28 = 150 , X86_REG_XMM29 = 151 , X86_REG_XMM30 = 152 , X86_REG_XMM31 = 153 , X86_REG_YMM0 = 154 , X86_REG_YMM1 = 155 , X86_REG_YMM2 = 156 , X86_REG_YMM3 = 157 , X86_REG_YMM4 = 158 , X86_REG_YMM5 = 159 , X86_REG_YMM6 = 160 , X86_REG_YMM7 = 161 , X86_REG_YMM8 = 162 , X86_REG_YMM9 = 163 , X86_REG_YMM10 = 164 , X86_REG_YMM11 = 165 , X86_REG_YMM12 = 166 , X86_REG_YMM13 = 167 , X86_REG_YMM14 = 168 , X86_REG_YMM15 = 169 , X86_REG_YMM16 = 170 , X86_REG_YMM17 = 171 , X86_REG_YMM18 = 172 , X86_REG_YMM19 = 173 , X86_REG_YMM20 = 174 , X86_REG_YMM21 = 175 , X86_REG_YMM22 = 176 , X86_REG_YMM23 = 177 , X86_REG_YMM24 = 178 , X86_REG_YMM25 = 179 , X86_REG_YMM26 = 180 , X86_REG_YMM27 = 181 , X86_REG_YMM28 = 182 , X86_REG_YMM29 = 183 , X86_REG_YMM30 = 184 , X86_REG_YMM31 = 185 , X86_REG_ZMM0 = 186 , X86_REG_ZMM1 = 187 , X86_REG_ZMM2 = 188 , X86_REG_ZMM3 = 189 , X86_REG_ZMM4 = 190 , X86_REG_ZMM5 = 191 , X86_REG_ZMM6 = 192 , X86_REG_ZMM7 = 193 , X86_REG_ZMM8 = 194 , X86_REG_ZMM9 = 195 , X86_REG_ZMM10 = 196 , X86_REG_ZMM11 = 197 , X86_REG_ZMM12 = 198 , X86_REG_ZMM13 = 199 , X86_REG_ZMM14 = 200 , X86_REG_ZMM15 = 201 , X86_REG_ZMM16 = 202 , X86_REG_ZMM17 = 203 , X86_REG_ZMM18 = 204 , X86_REG_ZMM19 = 205 , X86_REG_ZMM20 = 206 , X86_REG_ZMM21 = 207 , X86_REG_ZMM22 = 208 , X86_REG_ZMM23 = 209 , X86_REG_ZMM24 = 210 , X86_REG_ZMM25 = 211 , X86_REG_ZMM26 = 212 , X86_REG_ZMM27 = 213 , X86_REG_ZMM28 = 214 , X86_REG_ZMM29 = 215 , X86_REG_ZMM30 = 216 , X86_REG_ZMM31 = 217 , X86_REG_R8B = 218 , X86_REG_R9B = 219 , X86_REG_R10B = 220 , X86_REG_R11B = 221 , X86_REG_R12B = 222 , X86_REG_R13B = 223 , X86_REG_R14B = 224 , X86_REG_R15B = 225 , X86_REG_R8D = 226 , X86_REG_R9D = 227 , X86_REG_R10D = 228 , X86_REG_R11D = 229 , X86_REG_R12D = 230 , X86_REG_R13D = 231 , X86_REG_R14D = 232 , X86_REG_R15D = 233 , X86_REG_R8W = 234 , X86_REG_R9W = 235 , X86_REG_R10W = 236 , X86_REG_R11W = 237 , X86_REG_R12W = 238 , X86_REG_R13W = 239 , X86_REG_R14W = 240 , X86_REG_R15W = 241 , X86_REG_BND0 = 242 , X86_REG_BND1 = 243 , X86_REG_BND2 = 244 , X86_REG_BND3 = 245 , X86_REG_ENDING = 246 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] X86_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] X86_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] X86_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] X86_OP_MEM = 3 , } # [repr (u32)] # [doc = " XOP Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_xop_cc { # [doc = "< Uninitialized."] X86_XOP_CC_INVALID = 0 , X86_XOP_CC_LT = 1 , X86_XOP_CC_LE = 2 , X86_XOP_CC_GT = 3 , X86_XOP_CC_GE = 4 , X86_XOP_CC_EQ = 5 , X86_XOP_CC_NEQ = 6 , X86_XOP_CC_FALSE = 7 , X86_XOP_CC_TRUE = 8 , } # [repr (u32)] # [doc = " AVX broadcast type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_bcast { # [doc = "< Uninitialized."] X86_AVX_BCAST_INVALID = 0 , # [doc = "< AVX512 broadcast type {1to2}"] X86_AVX_BCAST_2 = 1 , # [doc = "< AVX512 broadcast type {1to4}"] X86_AVX_BCAST_4 = 2 , # [doc = "< AVX512 broadcast type {1to8}"] X86_AVX_BCAST_8 = 3 , # [doc = "< AVX512 broadcast type {1to16}"] X86_AVX_BCAST_16 = 4 , } # [repr (u32)] # [doc = " SSE Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_sse_cc { # [doc = "< Uninitialized."] X86_SSE_CC_INVALID = 0 , X86_SSE_CC_EQ = 1 , X86_SSE_CC_LT = 2 , X86_SSE_CC_LE = 3 , X86_SSE_CC_UNORD = 4 , X86_SSE_CC_NEQ = 5 , X86_SSE_CC_NLT = 6 , X86_SSE_CC_NLE = 7 , X86_SSE_CC_ORD = 8 , } # [repr (u32)] # [doc = " AVX Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_cc { # [doc = "< Uninitialized."] X86_AVX_CC_INVALID = 0 , X86_AVX_CC_EQ = 1 , X86_AVX_CC_LT = 2 , X86_AVX_CC_LE = 3 , X86_AVX_CC_UNORD = 4 , X86_AVX_CC_NEQ = 5 , X86_AVX_CC_NLT = 6 , X86_AVX_CC_NLE = 7 , X86_AVX_CC_ORD = 8 , X86_AVX_CC_EQ_UQ = 9 , X86_AVX_CC_NGE = 10 , X86_AVX_CC_NGT = 11 , X86_AVX_CC_FALSE = 12 , X86_AVX_CC_NEQ_OQ = 13 , X86_AVX_CC_GE = 14 , X86_AVX_CC_GT = 15 , X86_AVX_CC_TRUE = 16 , X86_AVX_CC_EQ_OS = 17 , X86_AVX_CC_LT_OQ = 18 , X86_AVX_CC_LE_OQ = 19 , X86_AVX_CC_UNORD_S = 20 , X86_AVX_CC_NEQ_US = 21 , X86_AVX_CC_NLT_UQ = 22 , X86_AVX_CC_NLE_UQ = 23 , X86_AVX_CC_ORD_S = 24 , X86_AVX_CC_EQ_US = 25 , X86_AVX_CC_NGE_UQ = 26 , X86_AVX_CC_NGT_UQ = 27 , X86_AVX_CC_FALSE_OS = 28 , X86_AVX_CC_NEQ_OS = 29 , X86_AVX_CC_GE_OQ = 30 , X86_AVX_CC_GT_OQ = 31 , X86_AVX_CC_TRUE_US = 32 , } # [repr (u32)] # [doc = " AVX static rounding mode type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_rm { # [doc = "< Uninitialized."] X86_AVX_RM_INVALID = 0 , # [doc = "< Round to nearest"] X86_AVX_RM_RN = 1 , # [doc = "< Round down"] X86_AVX_RM_RD = 2 , # [doc = "< Round up"] X86_AVX_RM_RU = 3 , # [doc = "< Round toward zero"] X86_AVX_RM_RZ = 4 , } impl x86_prefix { pub const X86_PREFIX_REPE : x86_prefix = x86_prefix :: X86_PREFIX_REP ; } # [repr (u32)] # [doc = " Instruction prefixes - to be used in cs_x86.prefix[]"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_prefix { # [doc = "< lock (cs_x86.prefix[0]"] X86_PREFIX_LOCK = 240 , # [doc = "< rep (cs_x86.prefix[0]"] X86_PREFIX_REP = 243 , # [doc = "< repne/repnz (cs_x86.prefix[0]"] X86_PREFIX_REPNE = 242 , # [doc = "< segment override CS (cs_x86.prefix[1]"] X86_PREFIX_CS = 46 , # [doc = "< segment override SS (cs_x86.prefix[1]"] X86_PREFIX_SS = 54 , # [doc = "< segment override DS (cs_x86.prefix[1]"] X86_PREFIX_DS = 62 , # [doc = "< segment override ES (cs_x86.prefix[1]"] X86_PREFIX_ES = 38 , # [doc = "< segment override FS (cs_x86.prefix[1]"] X86_PREFIX_FS = 100 , # [doc = "< segment override GS (cs_x86.prefix[1]"] X86_PREFIX_GS = 101 , # [doc = "< operand-size override (cs_x86.prefix[2]"] X86_PREFIX_OPSIZE = 102 , # [doc = "< address-size override (cs_x86.prefix[3]"] X86_PREFIX_ADDRSIZE = 103 , } # [doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct x86_op_mem { # [doc = "< segment register (or X86_REG_INVALID if irrelevant)"] pub segment : x86_reg , # [doc = "< base register (or X86_REG_INVALID if irrelevant)"] pub base : x86_reg , # [doc = "< index register (or X86_REG_INVALID if irrelevant)"] pub index : x86_reg , # [doc = "< scale for index register"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of x86_op_mem"] [:: std :: mem :: size_of :: < x86_op_mem > () - 24usize] ; ["Alignment of x86_op_mem"] [:: std :: mem :: align_of :: < x86_op_mem > () - 8usize] ; ["Offset of field: x86_op_mem::segment"] [:: std :: mem :: offset_of ! (x86_op_mem , segment) - 0usize] ; ["Offset of field: x86_op_mem::base"] [:: std :: mem :: offset_of ! (x86_op_mem , base) - 4usize] ; ["Offset of field: x86_op_mem::index"] [:: std :: mem :: offset_of ! (x86_op_mem , index) - 8usize] ; ["Offset of field: x86_op_mem::scale"] [:: std :: mem :: offset_of ! (x86_op_mem , scale) - 12usize] ; ["Offset of field: x86_op_mem::disp"] [:: std :: mem :: offset_of ! (x86_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86_op { # [doc = "< operand type"] pub type_ : x86_op_type , pub __bindgen_anon_1 : cs_x86_op__bindgen_ty_1 , # [doc = " size of this operand (in bytes)."] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " AVX broadcast type, or 0 if irrelevant"] pub avx_bcast : x86_avx_bcast , # [doc = " AVX zero opmask {z}"] pub avx_zero_opmask : bool , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : x86_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : x86_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op"] [:: std :: mem :: size_of :: < cs_x86_op > () - 48usize] ; ["Alignment of cs_x86_op"] [:: std :: mem :: align_of :: < cs_x86_op > () - 8usize] ; ["Offset of field: cs_x86_op::type_"] [:: std :: mem :: offset_of ! (cs_x86_op , type_) - 0usize] ; ["Offset of field: cs_x86_op::size"] [:: std :: mem :: offset_of ! (cs_x86_op , size) - 32usize] ; ["Offset of field: cs_x86_op::access"] [:: std :: mem :: offset_of ! (cs_x86_op , access) - 33usize] ; ["Offset of field: cs_x86_op::avx_bcast"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_bcast) - 36usize] ; ["Offset of field: cs_x86_op::avx_zero_opmask"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_zero_opmask) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask) } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_x86_encoding { # [doc = " ModR/M offset, or 0 when irrelevant"] pub modrm_offset : u8 , # [doc = " Displacement offset, or 0 when irrelevant."] pub disp_offset : u8 , pub disp_size : u8 , # [doc = " Immediate offset, or 0 when irrelevant."] pub imm_offset : u8 , pub imm_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_encoding"] [:: std :: mem :: size_of :: < cs_x86_encoding > () - 5usize] ; ["Alignment of cs_x86_encoding"] [:: std :: mem :: align_of :: < cs_x86_encoding > () - 1usize] ; ["Offset of field: cs_x86_encoding::modrm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , modrm_offset) - 0usize] ; ["Offset of field: cs_x86_encoding::disp_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_offset) - 1usize] ; ["Offset of field: cs_x86_encoding::disp_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_size) - 2usize] ; ["Offset of field: cs_x86_encoding::imm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_offset) - 3usize] ; ["Offset of field: cs_x86_encoding::imm_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_size) - 4usize] ; } ; # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86 { # [doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"] pub prefix : [u8 ; 4usize] , # [doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."] pub opcode : [u8 ; 4usize] , # [doc = " REX prefix: only a non-zero value is relevant for x86_64"] pub rex : u8 , # [doc = " Address size, which can be overridden with above prefix[5]."] pub addr_size : u8 , # [doc = " ModR/M byte"] pub modrm : u8 , # [doc = " SIB value, or 0 when irrelevant."] pub sib : u8 , # [doc = " Displacement value, valid if encoding.disp_offset != 0"] pub disp : i64 , # [doc = " SIB index register, or X86_REG_INVALID when irrelevant."] pub sib_index : x86_reg , # [doc = " SIB scale, only applicable if sib_index is valid."] pub sib_scale : i8 , # [doc = " SIB base register, or X86_REG_INVALID when irrelevant."] pub sib_base : x86_reg , # [doc = " XOP Code Condition"] pub xop_cc : x86_xop_cc , # [doc = " SSE Code Condition"] pub sse_cc : x86_sse_cc , # [doc = " AVX Code Condition"] pub avx_cc : x86_avx_cc , # [doc = " AVX Suppress all Exception"] pub avx_sae : bool , # [doc = " AVX static rounding mode"] pub avx_rm : x86_avx_rm , pub __bindgen_anon_1 : cs_x86__bindgen_ty_1 , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_x86_op ; 8usize] , # [doc = "< encoding information"] pub encoding : cs_x86_encoding , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86__bindgen_ty_1 { # [doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"] pub eflags : u64 , # [doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"] pub fpu_flags : u64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_x86__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86__bindgen_ty_1::eflags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , eflags) - 0usize] ; ["Offset of field: cs_x86__bindgen_ty_1::fpu_flags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , fpu_flags) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86"] [:: std :: mem :: size_of :: < cs_x86 > () - 464usize] ; ["Alignment of cs_x86"] [:: std :: mem :: align_of :: < cs_x86 > () - 8usize] ; ["Offset of field: cs_x86::prefix"] [:: std :: mem :: offset_of ! (cs_x86 , prefix) - 0usize] ; ["Offset of field: cs_x86::opcode"] [:: std :: mem :: offset_of ! (cs_x86 , opcode) - 4usize] ; ["Offset of field: cs_x86::rex"] [:: std :: mem :: offset_of ! (cs_x86 , rex) - 8usize] ; ["Offset of field: cs_x86::addr_size"] [:: std :: mem :: offset_of ! (cs_x86 , addr_size) - 9usize] ; ["Offset of field: cs_x86::modrm"] [:: std :: mem :: offset_of ! (cs_x86 , modrm) - 10usize] ; ["Offset of field: cs_x86::sib"] [:: std :: mem :: offset_of ! (cs_x86 , sib) - 11usize] ; ["Offset of field: cs_x86::disp"] [:: std :: mem :: offset_of ! (cs_x86 , disp) - 16usize] ; ["Offset of field: cs_x86::sib_index"] [:: std :: mem :: offset_of ! (cs_x86 , sib_index) - 24usize] ; ["Offset of field: cs_x86::sib_scale"] [:: std :: mem :: offset_of ! (cs_x86 , sib_scale) - 28usize] ; ["Offset of field: cs_x86::sib_base"] [:: std :: mem :: offset_of ! (cs_x86 , sib_base) - 32usize] ; ["Offset of field: cs_x86::xop_cc"] [:: std :: mem :: offset_of ! (cs_x86 , xop_cc) - 36usize] ; ["Offset of field: cs_x86::sse_cc"] [:: std :: mem :: offset_of ! (cs_x86 , sse_cc) - 40usize] ; ["Offset of field: cs_x86::avx_cc"] [:: std :: mem :: offset_of ! (cs_x86 , avx_cc) - 44usize] ; ["Offset of field: cs_x86::avx_sae"] [:: std :: mem :: offset_of ! (cs_x86 , avx_sae) - 48usize] ; ["Offset of field: cs_x86::avx_rm"] [:: std :: mem :: offset_of ! (cs_x86 , avx_rm) - 52usize] ; ["Offset of field: cs_x86::op_count"] [:: std :: mem :: offset_of ! (cs_x86 , op_count) - 64usize] ; ["Offset of field: cs_x86::operands"] [:: std :: mem :: offset_of ! (cs_x86 , operands) - 72usize] ; ["Offset of field: cs_x86::encoding"] [:: std :: mem :: offset_of ! (cs_x86 , encoding) - 456usize] ; } ; impl :: std :: fmt :: Debug for cs_x86 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding) } } # [repr (u32)] # [doc = " X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn { X86_INS_INVALID = 0 , X86_INS_AAA = 1 , X86_INS_AAD = 2 , X86_INS_AAM = 3 , X86_INS_AAS = 4 , X86_INS_FABS = 5 , X86_INS_ADC = 6 , X86_INS_ADCX = 7 , X86_INS_ADD = 8 , X86_INS_ADDPD = 9 , X86_INS_ADDPS = 10 , X86_INS_ADDSD = 11 , X86_INS_ADDSS = 12 , X86_INS_ADDSUBPD = 13 , X86_INS_ADDSUBPS = 14 , X86_INS_FADD = 15 , X86_INS_FIADD = 16 , X86_INS_ADOX = 17 , X86_INS_AESDECLAST = 18 , X86_INS_AESDEC = 19 , X86_INS_AESENCLAST = 20 , X86_INS_AESENC = 21 , X86_INS_AESIMC = 22 , X86_INS_AESKEYGENASSIST = 23 , X86_INS_AND = 24 , X86_INS_ANDN = 25 , X86_INS_ANDNPD = 26 , X86_INS_ANDNPS = 27 , X86_INS_ANDPD = 28 , X86_INS_ANDPS = 29 , X86_INS_ARPL = 30 , X86_INS_BEXTR = 31 , X86_INS_BLCFILL = 32 , X86_INS_BLCI = 33 , X86_INS_BLCIC = 34 , X86_INS_BLCMSK = 35 , X86_INS_BLCS = 36 , X86_INS_BLENDPD = 37 , X86_INS_BLENDPS = 38 , X86_INS_BLENDVPD = 39 , X86_INS_BLENDVPS = 40 , X86_INS_BLSFILL = 41 , X86_INS_BLSI = 42 , X86_INS_BLSIC = 43 , X86_INS_BLSMSK = 44 , X86_INS_BLSR = 45 , X86_INS_BNDCL = 46 , X86_INS_BNDCN = 47 , X86_INS_BNDCU = 48 , X86_INS_BNDLDX = 49 , X86_INS_BNDMK = 50 , X86_INS_BNDMOV = 51 , X86_INS_BNDSTX = 52 , X86_INS_BOUND = 53 , X86_INS_BSF = 54 , X86_INS_BSR = 55 , X86_INS_BSWAP = 56 , X86_INS_BT = 57 , X86_INS_BTC = 58 , X86_INS_BTR = 59 , X86_INS_BTS = 60 , X86_INS_BZHI = 61 , X86_INS_CALL = 62 , X86_INS_CBW = 63 , X86_INS_CDQ = 64 , X86_INS_CDQE = 65 , X86_INS_FCHS = 66 , X86_INS_CLAC = 67 , X86_INS_CLC = 68 , X86_INS_CLD = 69 , X86_INS_CLDEMOTE = 70 , X86_INS_CLFLUSH = 71 , X86_INS_CLFLUSHOPT = 72 , X86_INS_CLGI = 73 , X86_INS_CLI = 74 , X86_INS_CLRSSBSY = 75 , X86_INS_CLTS = 76 , X86_INS_CLWB = 77 , X86_INS_CLZERO = 78 , X86_INS_CMC = 79 , X86_INS_CMOVA = 80 , X86_INS_CMOVAE = 81 , X86_INS_CMOVB = 82 , X86_INS_CMOVBE = 83 , X86_INS_FCMOVBE = 84 , X86_INS_FCMOVB = 85 , X86_INS_CMOVE = 86 , X86_INS_FCMOVE = 87 , X86_INS_CMOVG = 88 , X86_INS_CMOVGE = 89 , X86_INS_CMOVL = 90 , X86_INS_CMOVLE = 91 , X86_INS_FCMOVNBE = 92 , X86_INS_FCMOVNB = 93 , X86_INS_CMOVNE = 94 , X86_INS_FCMOVNE = 95 , X86_INS_CMOVNO = 96 , X86_INS_CMOVNP = 97 , X86_INS_FCMOVNU = 98 , X86_INS_FCMOVNP = 99 , X86_INS_CMOVNS = 100 , X86_INS_CMOVO = 101 , X86_INS_CMOVP = 102 , X86_INS_FCMOVU = 103 , X86_INS_CMOVS = 104 , X86_INS_CMP = 105 , X86_INS_CMPPD = 106 , X86_INS_CMPPS = 107 , X86_INS_CMPSB = 108 , X86_INS_CMPSD = 109 , X86_INS_CMPSQ = 110 , X86_INS_CMPSS = 111 , X86_INS_CMPSW = 112 , X86_INS_CMPXCHG16B = 113 , X86_INS_CMPXCHG = 114 , X86_INS_CMPXCHG8B = 115 , X86_INS_COMISD = 116 , X86_INS_COMISS = 117 , X86_INS_FCOMP = 118 , X86_INS_FCOMPI = 119 , X86_INS_FCOMI = 120 , X86_INS_FCOM = 121 , X86_INS_FCOS = 122 , X86_INS_CPUID = 123 , X86_INS_CQO = 124 , X86_INS_CRC32 = 125 , X86_INS_CVTDQ2PD = 126 , X86_INS_CVTDQ2PS = 127 , X86_INS_CVTPD2DQ = 128 , X86_INS_CVTPD2PS = 129 , X86_INS_CVTPS2DQ = 130 , X86_INS_CVTPS2PD = 131 , X86_INS_CVTSD2SI = 132 , X86_INS_CVTSD2SS = 133 , X86_INS_CVTSI2SD = 134 , X86_INS_CVTSI2SS = 135 , X86_INS_CVTSS2SD = 136 , X86_INS_CVTSS2SI = 137 , X86_INS_CVTTPD2DQ = 138 , X86_INS_CVTTPS2DQ = 139 , X86_INS_CVTTSD2SI = 140 , X86_INS_CVTTSS2SI = 141 , X86_INS_CWD = 142 , X86_INS_CWDE = 143 , X86_INS_DAA = 144 , X86_INS_DAS = 145 , X86_INS_DATA16 = 146 , X86_INS_DEC = 147 , X86_INS_DIV = 148 , X86_INS_DIVPD = 149 , X86_INS_DIVPS = 150 , X86_INS_FDIVR = 151 , X86_INS_FIDIVR = 152 , X86_INS_FDIVRP = 153 , X86_INS_DIVSD = 154 , X86_INS_DIVSS = 155 , X86_INS_FDIV = 156 , X86_INS_FIDIV = 157 , X86_INS_FDIVP = 158 , X86_INS_DPPD = 159 , X86_INS_DPPS = 160 , X86_INS_ENCLS = 161 , X86_INS_ENCLU = 162 , X86_INS_ENCLV = 163 , X86_INS_ENDBR32 = 164 , X86_INS_ENDBR64 = 165 , X86_INS_ENTER = 166 , X86_INS_EXTRACTPS = 167 , X86_INS_EXTRQ = 168 , X86_INS_F2XM1 = 169 , X86_INS_LCALL = 170 , X86_INS_LJMP = 171 , X86_INS_JMP = 172 , X86_INS_FBLD = 173 , X86_INS_FBSTP = 174 , X86_INS_FCOMPP = 175 , X86_INS_FDECSTP = 176 , X86_INS_FDISI8087_NOP = 177 , X86_INS_FEMMS = 178 , X86_INS_FENI8087_NOP = 179 , X86_INS_FFREE = 180 , X86_INS_FFREEP = 181 , X86_INS_FICOM = 182 , X86_INS_FICOMP = 183 , X86_INS_FINCSTP = 184 , X86_INS_FLDCW = 185 , X86_INS_FLDENV = 186 , X86_INS_FLDL2E = 187 , X86_INS_FLDL2T = 188 , X86_INS_FLDLG2 = 189 , X86_INS_FLDLN2 = 190 , X86_INS_FLDPI = 191 , X86_INS_FNCLEX = 192 , X86_INS_FNINIT = 193 , X86_INS_FNOP = 194 , X86_INS_FNSTCW = 195 , X86_INS_FNSTSW = 196 , X86_INS_FPATAN = 197 , X86_INS_FSTPNCE = 198 , X86_INS_FPREM = 199 , X86_INS_FPREM1 = 200 , X86_INS_FPTAN = 201 , X86_INS_FRNDINT = 202 , X86_INS_FRSTOR = 203 , X86_INS_FNSAVE = 204 , X86_INS_FSCALE = 205 , X86_INS_FSETPM = 206 , X86_INS_FSINCOS = 207 , X86_INS_FNSTENV = 208 , X86_INS_FXAM = 209 , X86_INS_FXRSTOR = 210 , X86_INS_FXRSTOR64 = 211 , X86_INS_FXSAVE = 212 , X86_INS_FXSAVE64 = 213 , X86_INS_FXTRACT = 214 , X86_INS_FYL2X = 215 , X86_INS_FYL2XP1 = 216 , X86_INS_GETSEC = 217 , X86_INS_GF2P8AFFINEINVQB = 218 , X86_INS_GF2P8AFFINEQB = 219 , X86_INS_GF2P8MULB = 220 , X86_INS_HADDPD = 221 , X86_INS_HADDPS = 222 , X86_INS_HLT = 223 , X86_INS_HSUBPD = 224 , X86_INS_HSUBPS = 225 , X86_INS_IDIV = 226 , X86_INS_FILD = 227 , X86_INS_IMUL = 228 , X86_INS_IN = 229 , X86_INS_INC = 230 , X86_INS_INCSSPD = 231 , X86_INS_INCSSPQ = 232 , X86_INS_INSB = 233 , X86_INS_INSERTPS = 234 , X86_INS_INSERTQ = 235 , X86_INS_INSD = 236 , X86_INS_INSW = 237 , X86_INS_INT = 238 , X86_INS_INT1 = 239 , X86_INS_INT3 = 240 , X86_INS_INTO = 241 , X86_INS_INVD = 242 , X86_INS_INVEPT = 243 , X86_INS_INVLPG = 244 , X86_INS_INVLPGA = 245 , X86_INS_INVPCID = 246 , X86_INS_INVVPID = 247 , X86_INS_IRET = 248 , X86_INS_IRETD = 249 , X86_INS_IRETQ = 250 , X86_INS_FISTTP = 251 , X86_INS_FIST = 252 , X86_INS_FISTP = 253 , X86_INS_JAE = 254 , X86_INS_JA = 255 , X86_INS_JBE = 256 , X86_INS_JB = 257 , X86_INS_JCXZ = 258 , X86_INS_JECXZ = 259 , X86_INS_JE = 260 , X86_INS_JGE = 261 , X86_INS_JG = 262 , X86_INS_JLE = 263 , X86_INS_JL = 264 , X86_INS_JNE = 265 , X86_INS_JNO = 266 , X86_INS_JNP = 267 , X86_INS_JNS = 268 , X86_INS_JO = 269 , X86_INS_JP = 270 , X86_INS_JRCXZ = 271 , X86_INS_JS = 272 , X86_INS_KADDB = 273 , X86_INS_KADDD = 274 , X86_INS_KADDQ = 275 , X86_INS_KADDW = 276 , X86_INS_KANDB = 277 , X86_INS_KANDD = 278 , X86_INS_KANDNB = 279 , X86_INS_KANDND = 280 , X86_INS_KANDNQ = 281 , X86_INS_KANDNW = 282 , X86_INS_KANDQ = 283 , X86_INS_KANDW = 284 , X86_INS_KMOVB = 285 , X86_INS_KMOVD = 286 , X86_INS_KMOVQ = 287 , X86_INS_KMOVW = 288 , X86_INS_KNOTB = 289 , X86_INS_KNOTD = 290 , X86_INS_KNOTQ = 291 , X86_INS_KNOTW = 292 , X86_INS_KORB = 293 , X86_INS_KORD = 294 , X86_INS_KORQ = 295 , X86_INS_KORTESTB = 296 , X86_INS_KORTESTD = 297 , X86_INS_KORTESTQ = 298 , X86_INS_KORTESTW = 299 , X86_INS_KORW = 300 , X86_INS_KSHIFTLB = 301 , X86_INS_KSHIFTLD = 302 , X86_INS_KSHIFTLQ = 303 , X86_INS_KSHIFTLW = 304 , X86_INS_KSHIFTRB = 305 , X86_INS_KSHIFTRD = 306 , X86_INS_KSHIFTRQ = 307 , X86_INS_KSHIFTRW = 308 , X86_INS_KTESTB = 309 , X86_INS_KTESTD = 310 , X86_INS_KTESTQ = 311 , X86_INS_KTESTW = 312 , X86_INS_KUNPCKBW = 313 , X86_INS_KUNPCKDQ = 314 , X86_INS_KUNPCKWD = 315 , X86_INS_KXNORB = 316 , X86_INS_KXNORD = 317 , X86_INS_KXNORQ = 318 , X86_INS_KXNORW = 319 , X86_INS_KXORB = 320 , X86_INS_KXORD = 321 , X86_INS_KXORQ = 322 , X86_INS_KXORW = 323 , X86_INS_LAHF = 324 , X86_INS_LAR = 325 , X86_INS_LDDQU = 326 , X86_INS_LDMXCSR = 327 , X86_INS_LDS = 328 , X86_INS_FLDZ = 329 , X86_INS_FLD1 = 330 , X86_INS_FLD = 331 , X86_INS_LEA = 332 , X86_INS_LEAVE = 333 , X86_INS_LES = 334 , X86_INS_LFENCE = 335 , X86_INS_LFS = 336 , X86_INS_LGDT = 337 , X86_INS_LGS = 338 , X86_INS_LIDT = 339 , X86_INS_LLDT = 340 , X86_INS_LLWPCB = 341 , X86_INS_LMSW = 342 , X86_INS_LOCK = 343 , X86_INS_LODSB = 344 , X86_INS_LODSD = 345 , X86_INS_LODSQ = 346 , X86_INS_LODSW = 347 , X86_INS_LOOP = 348 , X86_INS_LOOPE = 349 , X86_INS_LOOPNE = 350 , X86_INS_RETF = 351 , X86_INS_RETFQ = 352 , X86_INS_LSL = 353 , X86_INS_LSS = 354 , X86_INS_LTR = 355 , X86_INS_LWPINS = 356 , X86_INS_LWPVAL = 357 , X86_INS_LZCNT = 358 , X86_INS_MASKMOVDQU = 359 , X86_INS_MAXPD = 360 , X86_INS_MAXPS = 361 , X86_INS_MAXSD = 362 , X86_INS_MAXSS = 363 , X86_INS_MFENCE = 364 , X86_INS_MINPD = 365 , X86_INS_MINPS = 366 , X86_INS_MINSD = 367 , X86_INS_MINSS = 368 , X86_INS_CVTPD2PI = 369 , X86_INS_CVTPI2PD = 370 , X86_INS_CVTPI2PS = 371 , X86_INS_CVTPS2PI = 372 , X86_INS_CVTTPD2PI = 373 , X86_INS_CVTTPS2PI = 374 , X86_INS_EMMS = 375 , X86_INS_MASKMOVQ = 376 , X86_INS_MOVD = 377 , X86_INS_MOVQ = 378 , X86_INS_MOVDQ2Q = 379 , X86_INS_MOVNTQ = 380 , X86_INS_MOVQ2DQ = 381 , X86_INS_PABSB = 382 , X86_INS_PABSD = 383 , X86_INS_PABSW = 384 , X86_INS_PACKSSDW = 385 , X86_INS_PACKSSWB = 386 , X86_INS_PACKUSWB = 387 , X86_INS_PADDB = 388 , X86_INS_PADDD = 389 , X86_INS_PADDQ = 390 , X86_INS_PADDSB = 391 , X86_INS_PADDSW = 392 , X86_INS_PADDUSB = 393 , X86_INS_PADDUSW = 394 , X86_INS_PADDW = 395 , X86_INS_PALIGNR = 396 , X86_INS_PANDN = 397 , X86_INS_PAND = 398 , X86_INS_PAVGB = 399 , X86_INS_PAVGW = 400 , X86_INS_PCMPEQB = 401 , X86_INS_PCMPEQD = 402 , X86_INS_PCMPEQW = 403 , X86_INS_PCMPGTB = 404 , X86_INS_PCMPGTD = 405 , X86_INS_PCMPGTW = 406 , X86_INS_PEXTRW = 407 , X86_INS_PHADDD = 408 , X86_INS_PHADDSW = 409 , X86_INS_PHADDW = 410 , X86_INS_PHSUBD = 411 , X86_INS_PHSUBSW = 412 , X86_INS_PHSUBW = 413 , X86_INS_PINSRW = 414 , X86_INS_PMADDUBSW = 415 , X86_INS_PMADDWD = 416 , X86_INS_PMAXSW = 417 , X86_INS_PMAXUB = 418 , X86_INS_PMINSW = 419 , X86_INS_PMINUB = 420 , X86_INS_PMOVMSKB = 421 , X86_INS_PMULHRSW = 422 , X86_INS_PMULHUW = 423 , X86_INS_PMULHW = 424 , X86_INS_PMULLW = 425 , X86_INS_PMULUDQ = 426 , X86_INS_POR = 427 , X86_INS_PSADBW = 428 , X86_INS_PSHUFB = 429 , X86_INS_PSHUFW = 430 , X86_INS_PSIGNB = 431 , X86_INS_PSIGND = 432 , X86_INS_PSIGNW = 433 , X86_INS_PSLLD = 434 , X86_INS_PSLLQ = 435 , X86_INS_PSLLW = 436 , X86_INS_PSRAD = 437 , X86_INS_PSRAW = 438 , X86_INS_PSRLD = 439 , X86_INS_PSRLQ = 440 , X86_INS_PSRLW = 441 , X86_INS_PSUBB = 442 , X86_INS_PSUBD = 443 , X86_INS_PSUBQ = 444 , X86_INS_PSUBSB = 445 , X86_INS_PSUBSW = 446 , X86_INS_PSUBUSB = 447 , X86_INS_PSUBUSW = 448 , X86_INS_PSUBW = 449 , X86_INS_PUNPCKHBW = 450 , X86_INS_PUNPCKHDQ = 451 , X86_INS_PUNPCKHWD = 452 , X86_INS_PUNPCKLBW = 453 , X86_INS_PUNPCKLDQ = 454 , X86_INS_PUNPCKLWD = 455 , X86_INS_PXOR = 456 , X86_INS_MONITORX = 457 , X86_INS_MONITOR = 458 , X86_INS_MONTMUL = 459 , X86_INS_MOV = 460 , X86_INS_MOVABS = 461 , X86_INS_MOVAPD = 462 , X86_INS_MOVAPS = 463 , X86_INS_MOVBE = 464 , X86_INS_MOVDDUP = 465 , X86_INS_MOVDIR64B = 466 , X86_INS_MOVDIRI = 467 , X86_INS_MOVDQA = 468 , X86_INS_MOVDQU = 469 , X86_INS_MOVHLPS = 470 , X86_INS_MOVHPD = 471 , X86_INS_MOVHPS = 472 , X86_INS_MOVLHPS = 473 , X86_INS_MOVLPD = 474 , X86_INS_MOVLPS = 475 , X86_INS_MOVMSKPD = 476 , X86_INS_MOVMSKPS = 477 , X86_INS_MOVNTDQA = 478 , X86_INS_MOVNTDQ = 479 , X86_INS_MOVNTI = 480 , X86_INS_MOVNTPD = 481 , X86_INS_MOVNTPS = 482 , X86_INS_MOVNTSD = 483 , X86_INS_MOVNTSS = 484 , X86_INS_MOVSB = 485 , X86_INS_MOVSD = 486 , X86_INS_MOVSHDUP = 487 , X86_INS_MOVSLDUP = 488 , X86_INS_MOVSQ = 489 , X86_INS_MOVSS = 490 , X86_INS_MOVSW = 491 , X86_INS_MOVSX = 492 , X86_INS_MOVSXD = 493 , X86_INS_MOVUPD = 494 , X86_INS_MOVUPS = 495 , X86_INS_MOVZX = 496 , X86_INS_MPSADBW = 497 , X86_INS_MUL = 498 , X86_INS_MULPD = 499 , X86_INS_MULPS = 500 , X86_INS_MULSD = 501 , X86_INS_MULSS = 502 , X86_INS_MULX = 503 , X86_INS_FMUL = 504 , X86_INS_FIMUL = 505 , X86_INS_FMULP = 506 , X86_INS_MWAITX = 507 , X86_INS_MWAIT = 508 , X86_INS_NEG = 509 , X86_INS_NOP = 510 , X86_INS_NOT = 511 , X86_INS_OR = 512 , X86_INS_ORPD = 513 , X86_INS_ORPS = 514 , X86_INS_OUT = 515 , X86_INS_OUTSB = 516 , X86_INS_OUTSD = 517 , X86_INS_OUTSW = 518 , X86_INS_PACKUSDW = 519 , X86_INS_PAUSE = 520 , X86_INS_PAVGUSB = 521 , X86_INS_PBLENDVB = 522 , X86_INS_PBLENDW = 523 , X86_INS_PCLMULQDQ = 524 , X86_INS_PCMPEQQ = 525 , X86_INS_PCMPESTRI = 526 , X86_INS_PCMPESTRM = 527 , X86_INS_PCMPGTQ = 528 , X86_INS_PCMPISTRI = 529 , X86_INS_PCMPISTRM = 530 , X86_INS_PCONFIG = 531 , X86_INS_PDEP = 532 , X86_INS_PEXT = 533 , X86_INS_PEXTRB = 534 , X86_INS_PEXTRD = 535 , X86_INS_PEXTRQ = 536 , X86_INS_PF2ID = 537 , X86_INS_PF2IW = 538 , X86_INS_PFACC = 539 , X86_INS_PFADD = 540 , X86_INS_PFCMPEQ = 541 , X86_INS_PFCMPGE = 542 , X86_INS_PFCMPGT = 543 , X86_INS_PFMAX = 544 , X86_INS_PFMIN = 545 , X86_INS_PFMUL = 546 , X86_INS_PFNACC = 547 , X86_INS_PFPNACC = 548 , X86_INS_PFRCPIT1 = 549 , X86_INS_PFRCPIT2 = 550 , X86_INS_PFRCP = 551 , X86_INS_PFRSQIT1 = 552 , X86_INS_PFRSQRT = 553 , X86_INS_PFSUBR = 554 , X86_INS_PFSUB = 555 , X86_INS_PHMINPOSUW = 556 , X86_INS_PI2FD = 557 , X86_INS_PI2FW = 558 , X86_INS_PINSRB = 559 , X86_INS_PINSRD = 560 , X86_INS_PINSRQ = 561 , X86_INS_PMAXSB = 562 , X86_INS_PMAXSD = 563 , X86_INS_PMAXUD = 564 , X86_INS_PMAXUW = 565 , X86_INS_PMINSB = 566 , X86_INS_PMINSD = 567 , X86_INS_PMINUD = 568 , X86_INS_PMINUW = 569 , X86_INS_PMOVSXBD = 570 , X86_INS_PMOVSXBQ = 571 , X86_INS_PMOVSXBW = 572 , X86_INS_PMOVSXDQ = 573 , X86_INS_PMOVSXWD = 574 , X86_INS_PMOVSXWQ = 575 , X86_INS_PMOVZXBD = 576 , X86_INS_PMOVZXBQ = 577 , X86_INS_PMOVZXBW = 578 , X86_INS_PMOVZXDQ = 579 , X86_INS_PMOVZXWD = 580 , X86_INS_PMOVZXWQ = 581 , X86_INS_PMULDQ = 582 , X86_INS_PMULHRW = 583 , X86_INS_PMULLD = 584 , X86_INS_POP = 585 , X86_INS_POPAW = 586 , X86_INS_POPAL = 587 , X86_INS_POPCNT = 588 , X86_INS_POPF = 589 , X86_INS_POPFD = 590 , X86_INS_POPFQ = 591 , X86_INS_PREFETCH = 592 , X86_INS_PREFETCHNTA = 593 , X86_INS_PREFETCHT0 = 594 , X86_INS_PREFETCHT1 = 595 , X86_INS_PREFETCHT2 = 596 , X86_INS_PREFETCHW = 597 , X86_INS_PREFETCHWT1 = 598 , X86_INS_PSHUFD = 599 , X86_INS_PSHUFHW = 600 , X86_INS_PSHUFLW = 601 , X86_INS_PSLLDQ = 602 , X86_INS_PSRLDQ = 603 , X86_INS_PSWAPD = 604 , X86_INS_PTEST = 605 , X86_INS_PTWRITE = 606 , X86_INS_PUNPCKHQDQ = 607 , X86_INS_PUNPCKLQDQ = 608 , X86_INS_PUSH = 609 , X86_INS_PUSHAW = 610 , X86_INS_PUSHAL = 611 , X86_INS_PUSHF = 612 , X86_INS_PUSHFD = 613 , X86_INS_PUSHFQ = 614 , X86_INS_RCL = 615 , X86_INS_RCPPS = 616 , X86_INS_RCPSS = 617 , X86_INS_RCR = 618 , X86_INS_RDFSBASE = 619 , X86_INS_RDGSBASE = 620 , X86_INS_RDMSR = 621 , X86_INS_RDPID = 622 , X86_INS_RDPKRU = 623 , X86_INS_RDPMC = 624 , X86_INS_RDRAND = 625 , X86_INS_RDSEED = 626 , X86_INS_RDSSPD = 627 , X86_INS_RDSSPQ = 628 , X86_INS_RDTSC = 629 , X86_INS_RDTSCP = 630 , X86_INS_REPNE = 631 , X86_INS_REP = 632 , X86_INS_RET = 633 , X86_INS_REX64 = 634 , X86_INS_ROL = 635 , X86_INS_ROR = 636 , X86_INS_RORX = 637 , X86_INS_ROUNDPD = 638 , X86_INS_ROUNDPS = 639 , X86_INS_ROUNDSD = 640 , X86_INS_ROUNDSS = 641 , X86_INS_RSM = 642 , X86_INS_RSQRTPS = 643 , X86_INS_RSQRTSS = 644 , X86_INS_RSTORSSP = 645 , X86_INS_SAHF = 646 , X86_INS_SAL = 647 , X86_INS_SALC = 648 , X86_INS_SAR = 649 , X86_INS_SARX = 650 , X86_INS_SAVEPREVSSP = 651 , X86_INS_SBB = 652 , X86_INS_SCASB = 653 , X86_INS_SCASD = 654 , X86_INS_SCASQ = 655 , X86_INS_SCASW = 656 , X86_INS_SETAE = 657 , X86_INS_SETA = 658 , X86_INS_SETBE = 659 , X86_INS_SETB = 660 , X86_INS_SETE = 661 , X86_INS_SETGE = 662 , X86_INS_SETG = 663 , X86_INS_SETLE = 664 , X86_INS_SETL = 665 , X86_INS_SETNE = 666 , X86_INS_SETNO = 667 , X86_INS_SETNP = 668 , X86_INS_SETNS = 669 , X86_INS_SETO = 670 , X86_INS_SETP = 671 , X86_INS_SETSSBSY = 672 , X86_INS_SETS = 673 , X86_INS_SFENCE = 674 , X86_INS_SGDT = 675 , X86_INS_SHA1MSG1 = 676 , X86_INS_SHA1MSG2 = 677 , X86_INS_SHA1NEXTE = 678 , X86_INS_SHA1RNDS4 = 679 , X86_INS_SHA256MSG1 = 680 , X86_INS_SHA256MSG2 = 681 , X86_INS_SHA256RNDS2 = 682 , X86_INS_SHL = 683 , X86_INS_SHLD = 684 , X86_INS_SHLX = 685 , X86_INS_SHR = 686 , X86_INS_SHRD = 687 , X86_INS_SHRX = 688 , X86_INS_SHUFPD = 689 , X86_INS_SHUFPS = 690 , X86_INS_SIDT = 691 , X86_INS_FSIN = 692 , X86_INS_SKINIT = 693 , X86_INS_SLDT = 694 , X86_INS_SLWPCB = 695 , X86_INS_SMSW = 696 , X86_INS_SQRTPD = 697 , X86_INS_SQRTPS = 698 , X86_INS_SQRTSD = 699 , X86_INS_SQRTSS = 700 , X86_INS_FSQRT = 701 , X86_INS_STAC = 702 , X86_INS_STC = 703 , X86_INS_STD = 704 , X86_INS_STGI = 705 , X86_INS_STI = 706 , X86_INS_STMXCSR = 707 , X86_INS_STOSB = 708 , X86_INS_STOSD = 709 , X86_INS_STOSQ = 710 , X86_INS_STOSW = 711 , X86_INS_STR = 712 , X86_INS_FST = 713 , X86_INS_FSTP = 714 , X86_INS_SUB = 715 , X86_INS_SUBPD = 716 , X86_INS_SUBPS = 717 , X86_INS_FSUBR = 718 , X86_INS_FISUBR = 719 , X86_INS_FSUBRP = 720 , X86_INS_SUBSD = 721 , X86_INS_SUBSS = 722 , X86_INS_FSUB = 723 , X86_INS_FISUB = 724 , X86_INS_FSUBP = 725 , X86_INS_SWAPGS = 726 , X86_INS_SYSCALL = 727 , X86_INS_SYSENTER = 728 , X86_INS_SYSEXIT = 729 , X86_INS_SYSEXITQ = 730 , X86_INS_SYSRET = 731 , X86_INS_SYSRETQ = 732 , X86_INS_T1MSKC = 733 , X86_INS_TEST = 734 , X86_INS_TPAUSE = 735 , X86_INS_FTST = 736 , X86_INS_TZCNT = 737 , X86_INS_TZMSK = 738 , X86_INS_UCOMISD = 739 , X86_INS_UCOMISS = 740 , X86_INS_FUCOMPI = 741 , X86_INS_FUCOMI = 742 , X86_INS_FUCOMPP = 743 , X86_INS_FUCOMP = 744 , X86_INS_FUCOM = 745 , X86_INS_UD0 = 746 , X86_INS_UD1 = 747 , X86_INS_UD2 = 748 , X86_INS_UMONITOR = 749 , X86_INS_UMWAIT = 750 , X86_INS_UNPCKHPD = 751 , X86_INS_UNPCKHPS = 752 , X86_INS_UNPCKLPD = 753 , X86_INS_UNPCKLPS = 754 , X86_INS_V4FMADDPS = 755 , X86_INS_V4FMADDSS = 756 , X86_INS_V4FNMADDPS = 757 , X86_INS_V4FNMADDSS = 758 , X86_INS_VADDPD = 759 , X86_INS_VADDPS = 760 , X86_INS_VADDSD = 761 , X86_INS_VADDSS = 762 , X86_INS_VADDSUBPD = 763 , X86_INS_VADDSUBPS = 764 , X86_INS_VAESDECLAST = 765 , X86_INS_VAESDEC = 766 , X86_INS_VAESENCLAST = 767 , X86_INS_VAESENC = 768 , X86_INS_VAESIMC = 769 , X86_INS_VAESKEYGENASSIST = 770 , X86_INS_VALIGND = 771 , X86_INS_VALIGNQ = 772 , X86_INS_VANDNPD = 773 , X86_INS_VANDNPS = 774 , X86_INS_VANDPD = 775 , X86_INS_VANDPS = 776 , X86_INS_VBLENDMPD = 777 , X86_INS_VBLENDMPS = 778 , X86_INS_VBLENDPD = 779 , X86_INS_VBLENDPS = 780 , X86_INS_VBLENDVPD = 781 , X86_INS_VBLENDVPS = 782 , X86_INS_VBROADCASTF128 = 783 , X86_INS_VBROADCASTF32X2 = 784 , X86_INS_VBROADCASTF32X4 = 785 , X86_INS_VBROADCASTF32X8 = 786 , X86_INS_VBROADCASTF64X2 = 787 , X86_INS_VBROADCASTF64X4 = 788 , X86_INS_VBROADCASTI128 = 789 , X86_INS_VBROADCASTI32X2 = 790 , X86_INS_VBROADCASTI32X4 = 791 , X86_INS_VBROADCASTI32X8 = 792 , X86_INS_VBROADCASTI64X2 = 793 , X86_INS_VBROADCASTI64X4 = 794 , X86_INS_VBROADCASTSD = 795 , X86_INS_VBROADCASTSS = 796 , X86_INS_VCMP = 797 , X86_INS_VCMPPD = 798 , X86_INS_VCMPPS = 799 , X86_INS_VCMPSD = 800 , X86_INS_VCMPSS = 801 , X86_INS_VCOMISD = 802 , X86_INS_VCOMISS = 803 , X86_INS_VCOMPRESSPD = 804 , X86_INS_VCOMPRESSPS = 805 , X86_INS_VCVTDQ2PD = 806 , X86_INS_VCVTDQ2PS = 807 , X86_INS_VCVTPD2DQ = 808 , X86_INS_VCVTPD2PS = 809 , X86_INS_VCVTPD2QQ = 810 , X86_INS_VCVTPD2UDQ = 811 , X86_INS_VCVTPD2UQQ = 812 , X86_INS_VCVTPH2PS = 813 , X86_INS_VCVTPS2DQ = 814 , X86_INS_VCVTPS2PD = 815 , X86_INS_VCVTPS2PH = 816 , X86_INS_VCVTPS2QQ = 817 , X86_INS_VCVTPS2UDQ = 818 , X86_INS_VCVTPS2UQQ = 819 , X86_INS_VCVTQQ2PD = 820 , X86_INS_VCVTQQ2PS = 821 , X86_INS_VCVTSD2SI = 822 , X86_INS_VCVTSD2SS = 823 , X86_INS_VCVTSD2USI = 824 , X86_INS_VCVTSI2SD = 825 , X86_INS_VCVTSI2SS = 826 , X86_INS_VCVTSS2SD = 827 , X86_INS_VCVTSS2SI = 828 , X86_INS_VCVTSS2USI = 829 , X86_INS_VCVTTPD2DQ = 830 , X86_INS_VCVTTPD2QQ = 831 , X86_INS_VCVTTPD2UDQ = 832 , X86_INS_VCVTTPD2UQQ = 833 , X86_INS_VCVTTPS2DQ = 834 , X86_INS_VCVTTPS2QQ = 835 , X86_INS_VCVTTPS2UDQ = 836 , X86_INS_VCVTTPS2UQQ = 837 , X86_INS_VCVTTSD2SI = 838 , X86_INS_VCVTTSD2USI = 839 , X86_INS_VCVTTSS2SI = 840 , X86_INS_VCVTTSS2USI = 841 , X86_INS_VCVTUDQ2PD = 842 , X86_INS_VCVTUDQ2PS = 843 , X86_INS_VCVTUQQ2PD = 844 , X86_INS_VCVTUQQ2PS = 845 , X86_INS_VCVTUSI2SD = 846 , X86_INS_VCVTUSI2SS = 847 , X86_INS_VDBPSADBW = 848 , X86_INS_VDIVPD = 849 , X86_INS_VDIVPS = 850 , X86_INS_VDIVSD = 851 , X86_INS_VDIVSS = 852 , X86_INS_VDPPD = 853 , X86_INS_VDPPS = 854 , X86_INS_VERR = 855 , X86_INS_VERW = 856 , X86_INS_VEXP2PD = 857 , X86_INS_VEXP2PS = 858 , X86_INS_VEXPANDPD = 859 , X86_INS_VEXPANDPS = 860 , X86_INS_VEXTRACTF128 = 861 , X86_INS_VEXTRACTF32X4 = 862 , X86_INS_VEXTRACTF32X8 = 863 , X86_INS_VEXTRACTF64X2 = 864 , X86_INS_VEXTRACTF64X4 = 865 , X86_INS_VEXTRACTI128 = 866 , X86_INS_VEXTRACTI32X4 = 867 , X86_INS_VEXTRACTI32X8 = 868 , X86_INS_VEXTRACTI64X2 = 869 , X86_INS_VEXTRACTI64X4 = 870 , X86_INS_VEXTRACTPS = 871 , X86_INS_VFIXUPIMMPD = 872 , X86_INS_VFIXUPIMMPS = 873 , X86_INS_VFIXUPIMMSD = 874 , X86_INS_VFIXUPIMMSS = 875 , X86_INS_VFMADD132PD = 876 , X86_INS_VFMADD132PS = 877 , X86_INS_VFMADD132SD = 878 , X86_INS_VFMADD132SS = 879 , X86_INS_VFMADD213PD = 880 , X86_INS_VFMADD213PS = 881 , X86_INS_VFMADD213SD = 882 , X86_INS_VFMADD213SS = 883 , X86_INS_VFMADD231PD = 884 , X86_INS_VFMADD231PS = 885 , X86_INS_VFMADD231SD = 886 , X86_INS_VFMADD231SS = 887 , X86_INS_VFMADDPD = 888 , X86_INS_VFMADDPS = 889 , X86_INS_VFMADDSD = 890 , X86_INS_VFMADDSS = 891 , X86_INS_VFMADDSUB132PD = 892 , X86_INS_VFMADDSUB132PS = 893 , X86_INS_VFMADDSUB213PD = 894 , X86_INS_VFMADDSUB213PS = 895 , X86_INS_VFMADDSUB231PD = 896 , X86_INS_VFMADDSUB231PS = 897 , X86_INS_VFMADDSUBPD = 898 , X86_INS_VFMADDSUBPS = 899 , X86_INS_VFMSUB132PD = 900 , X86_INS_VFMSUB132PS = 901 , X86_INS_VFMSUB132SD = 902 , X86_INS_VFMSUB132SS = 903 , X86_INS_VFMSUB213PD = 904 , X86_INS_VFMSUB213PS = 905 , X86_INS_VFMSUB213SD = 906 , X86_INS_VFMSUB213SS = 907 , X86_INS_VFMSUB231PD = 908 , X86_INS_VFMSUB231PS = 909 , X86_INS_VFMSUB231SD = 910 , X86_INS_VFMSUB231SS = 911 , X86_INS_VFMSUBADD132PD = 912 , X86_INS_VFMSUBADD132PS = 913 , X86_INS_VFMSUBADD213PD = 914 , X86_INS_VFMSUBADD213PS = 915 , X86_INS_VFMSUBADD231PD = 916 , X86_INS_VFMSUBADD231PS = 917 , X86_INS_VFMSUBADDPD = 918 , X86_INS_VFMSUBADDPS = 919 , X86_INS_VFMSUBPD = 920 , X86_INS_VFMSUBPS = 921 , X86_INS_VFMSUBSD = 922 , X86_INS_VFMSUBSS = 923 , X86_INS_VFNMADD132PD = 924 , X86_INS_VFNMADD132PS = 925 , X86_INS_VFNMADD132SD = 926 , X86_INS_VFNMADD132SS = 927 , X86_INS_VFNMADD213PD = 928 , X86_INS_VFNMADD213PS = 929 , X86_INS_VFNMADD213SD = 930 , X86_INS_VFNMADD213SS = 931 , X86_INS_VFNMADD231PD = 932 , X86_INS_VFNMADD231PS = 933 , X86_INS_VFNMADD231SD = 934 , X86_INS_VFNMADD231SS = 935 , X86_INS_VFNMADDPD = 936 , X86_INS_VFNMADDPS = 937 , X86_INS_VFNMADDSD = 938 , X86_INS_VFNMADDSS = 939 , X86_INS_VFNMSUB132PD = 940 , X86_INS_VFNMSUB132PS = 941 , X86_INS_VFNMSUB132SD = 942 , X86_INS_VFNMSUB132SS = 943 , X86_INS_VFNMSUB213PD = 944 , X86_INS_VFNMSUB213PS = 945 , X86_INS_VFNMSUB213SD = 946 , X86_INS_VFNMSUB213SS = 947 , X86_INS_VFNMSUB231PD = 948 , X86_INS_VFNMSUB231PS = 949 , X86_INS_VFNMSUB231SD = 950 , X86_INS_VFNMSUB231SS = 951 , X86_INS_VFNMSUBPD = 952 , X86_INS_VFNMSUBPS = 953 , X86_INS_VFNMSUBSD = 954 , X86_INS_VFNMSUBSS = 955 , X86_INS_VFPCLASSPD = 956 , X86_INS_VFPCLASSPS = 957 , X86_INS_VFPCLASSSD = 958 , X86_INS_VFPCLASSSS = 959 , X86_INS_VFRCZPD = 960 , X86_INS_VFRCZPS = 961 , X86_INS_VFRCZSD = 962 , X86_INS_VFRCZSS = 963 , X86_INS_VGATHERDPD = 964 , X86_INS_VGATHERDPS = 965 , X86_INS_VGATHERPF0DPD = 966 , X86_INS_VGATHERPF0DPS = 967 , X86_INS_VGATHERPF0QPD = 968 , X86_INS_VGATHERPF0QPS = 969 , X86_INS_VGATHERPF1DPD = 970 , X86_INS_VGATHERPF1DPS = 971 , X86_INS_VGATHERPF1QPD = 972 , X86_INS_VGATHERPF1QPS = 973 , X86_INS_VGATHERQPD = 974 , X86_INS_VGATHERQPS = 975 , X86_INS_VGETEXPPD = 976 , X86_INS_VGETEXPPS = 977 , X86_INS_VGETEXPSD = 978 , X86_INS_VGETEXPSS = 979 , X86_INS_VGETMANTPD = 980 , X86_INS_VGETMANTPS = 981 , X86_INS_VGETMANTSD = 982 , X86_INS_VGETMANTSS = 983 , X86_INS_VGF2P8AFFINEINVQB = 984 , X86_INS_VGF2P8AFFINEQB = 985 , X86_INS_VGF2P8MULB = 986 , X86_INS_VHADDPD = 987 , X86_INS_VHADDPS = 988 , X86_INS_VHSUBPD = 989 , X86_INS_VHSUBPS = 990 , X86_INS_VINSERTF128 = 991 , X86_INS_VINSERTF32X4 = 992 , X86_INS_VINSERTF32X8 = 993 , X86_INS_VINSERTF64X2 = 994 , X86_INS_VINSERTF64X4 = 995 , X86_INS_VINSERTI128 = 996 , X86_INS_VINSERTI32X4 = 997 , X86_INS_VINSERTI32X8 = 998 , X86_INS_VINSERTI64X2 = 999 , X86_INS_VINSERTI64X4 = 1000 , X86_INS_VINSERTPS = 1001 , X86_INS_VLDDQU = 1002 , X86_INS_VLDMXCSR = 1003 , X86_INS_VMASKMOVDQU = 1004 , X86_INS_VMASKMOVPD = 1005 , X86_INS_VMASKMOVPS = 1006 , X86_INS_VMAXPD = 1007 , X86_INS_VMAXPS = 1008 , X86_INS_VMAXSD = 1009 , X86_INS_VMAXSS = 1010 , X86_INS_VMCALL = 1011 , X86_INS_VMCLEAR = 1012 , X86_INS_VMFUNC = 1013 , X86_INS_VMINPD = 1014 , X86_INS_VMINPS = 1015 , X86_INS_VMINSD = 1016 , X86_INS_VMINSS = 1017 , X86_INS_VMLAUNCH = 1018 , X86_INS_VMLOAD = 1019 , X86_INS_VMMCALL = 1020 , X86_INS_VMOVQ = 1021 , X86_INS_VMOVAPD = 1022 , X86_INS_VMOVAPS = 1023 , X86_INS_VMOVDDUP = 1024 , X86_INS_VMOVD = 1025 , X86_INS_VMOVDQA32 = 1026 , X86_INS_VMOVDQA64 = 1027 , X86_INS_VMOVDQA = 1028 , X86_INS_VMOVDQU16 = 1029 , X86_INS_VMOVDQU32 = 1030 , X86_INS_VMOVDQU64 = 1031 , X86_INS_VMOVDQU8 = 1032 , X86_INS_VMOVDQU = 1033 , X86_INS_VMOVHLPS = 1034 , X86_INS_VMOVHPD = 1035 , X86_INS_VMOVHPS = 1036 , X86_INS_VMOVLHPS = 1037 , X86_INS_VMOVLPD = 1038 , X86_INS_VMOVLPS = 1039 , X86_INS_VMOVMSKPD = 1040 , X86_INS_VMOVMSKPS = 1041 , X86_INS_VMOVNTDQA = 1042 , X86_INS_VMOVNTDQ = 1043 , X86_INS_VMOVNTPD = 1044 , X86_INS_VMOVNTPS = 1045 , X86_INS_VMOVSD = 1046 , X86_INS_VMOVSHDUP = 1047 , X86_INS_VMOVSLDUP = 1048 , X86_INS_VMOVSS = 1049 , X86_INS_VMOVUPD = 1050 , X86_INS_VMOVUPS = 1051 , X86_INS_VMPSADBW = 1052 , X86_INS_VMPTRLD = 1053 , X86_INS_VMPTRST = 1054 , X86_INS_VMREAD = 1055 , X86_INS_VMRESUME = 1056 , X86_INS_VMRUN = 1057 , X86_INS_VMSAVE = 1058 , X86_INS_VMULPD = 1059 , X86_INS_VMULPS = 1060 , X86_INS_VMULSD = 1061 , X86_INS_VMULSS = 1062 , X86_INS_VMWRITE = 1063 , X86_INS_VMXOFF = 1064 , X86_INS_VMXON = 1065 , X86_INS_VORPD = 1066 , X86_INS_VORPS = 1067 , X86_INS_VP4DPWSSDS = 1068 , X86_INS_VP4DPWSSD = 1069 , X86_INS_VPABSB = 1070 , X86_INS_VPABSD = 1071 , X86_INS_VPABSQ = 1072 , X86_INS_VPABSW = 1073 , X86_INS_VPACKSSDW = 1074 , X86_INS_VPACKSSWB = 1075 , X86_INS_VPACKUSDW = 1076 , X86_INS_VPACKUSWB = 1077 , X86_INS_VPADDB = 1078 , X86_INS_VPADDD = 1079 , X86_INS_VPADDQ = 1080 , X86_INS_VPADDSB = 1081 , X86_INS_VPADDSW = 1082 , X86_INS_VPADDUSB = 1083 , X86_INS_VPADDUSW = 1084 , X86_INS_VPADDW = 1085 , X86_INS_VPALIGNR = 1086 , X86_INS_VPANDD = 1087 , X86_INS_VPANDND = 1088 , X86_INS_VPANDNQ = 1089 , X86_INS_VPANDN = 1090 , X86_INS_VPANDQ = 1091 , X86_INS_VPAND = 1092 , X86_INS_VPAVGB = 1093 , X86_INS_VPAVGW = 1094 , X86_INS_VPBLENDD = 1095 , X86_INS_VPBLENDMB = 1096 , X86_INS_VPBLENDMD = 1097 , X86_INS_VPBLENDMQ = 1098 , X86_INS_VPBLENDMW = 1099 , X86_INS_VPBLENDVB = 1100 , X86_INS_VPBLENDW = 1101 , X86_INS_VPBROADCASTB = 1102 , X86_INS_VPBROADCASTD = 1103 , X86_INS_VPBROADCASTMB2Q = 1104 , X86_INS_VPBROADCASTMW2D = 1105 , X86_INS_VPBROADCASTQ = 1106 , X86_INS_VPBROADCASTW = 1107 , X86_INS_VPCLMULQDQ = 1108 , X86_INS_VPCMOV = 1109 , X86_INS_VPCMP = 1110 , X86_INS_VPCMPB = 1111 , X86_INS_VPCMPD = 1112 , X86_INS_VPCMPEQB = 1113 , X86_INS_VPCMPEQD = 1114 , X86_INS_VPCMPEQQ = 1115 , X86_INS_VPCMPEQW = 1116 , X86_INS_VPCMPESTRI = 1117 , X86_INS_VPCMPESTRM = 1118 , X86_INS_VPCMPGTB = 1119 , X86_INS_VPCMPGTD = 1120 , X86_INS_VPCMPGTQ = 1121 , X86_INS_VPCMPGTW = 1122 , X86_INS_VPCMPISTRI = 1123 , X86_INS_VPCMPISTRM = 1124 , X86_INS_VPCMPQ = 1125 , X86_INS_VPCMPUB = 1126 , X86_INS_VPCMPUD = 1127 , X86_INS_VPCMPUQ = 1128 , X86_INS_VPCMPUW = 1129 , X86_INS_VPCMPW = 1130 , X86_INS_VPCOM = 1131 , X86_INS_VPCOMB = 1132 , X86_INS_VPCOMD = 1133 , X86_INS_VPCOMPRESSB = 1134 , X86_INS_VPCOMPRESSD = 1135 , X86_INS_VPCOMPRESSQ = 1136 , X86_INS_VPCOMPRESSW = 1137 , X86_INS_VPCOMQ = 1138 , X86_INS_VPCOMUB = 1139 , X86_INS_VPCOMUD = 1140 , X86_INS_VPCOMUQ = 1141 , X86_INS_VPCOMUW = 1142 , X86_INS_VPCOMW = 1143 , X86_INS_VPCONFLICTD = 1144 , X86_INS_VPCONFLICTQ = 1145 , X86_INS_VPDPBUSDS = 1146 , X86_INS_VPDPBUSD = 1147 , X86_INS_VPDPWSSDS = 1148 , X86_INS_VPDPWSSD = 1149 , X86_INS_VPERM2F128 = 1150 , X86_INS_VPERM2I128 = 1151 , X86_INS_VPERMB = 1152 , X86_INS_VPERMD = 1153 , X86_INS_VPERMI2B = 1154 , X86_INS_VPERMI2D = 1155 , X86_INS_VPERMI2PD = 1156 , X86_INS_VPERMI2PS = 1157 , X86_INS_VPERMI2Q = 1158 , X86_INS_VPERMI2W = 1159 , X86_INS_VPERMIL2PD = 1160 , X86_INS_VPERMILPD = 1161 , X86_INS_VPERMIL2PS = 1162 , X86_INS_VPERMILPS = 1163 , X86_INS_VPERMPD = 1164 , X86_INS_VPERMPS = 1165 , X86_INS_VPERMQ = 1166 , X86_INS_VPERMT2B = 1167 , X86_INS_VPERMT2D = 1168 , X86_INS_VPERMT2PD = 1169 , X86_INS_VPERMT2PS = 1170 , X86_INS_VPERMT2Q = 1171 , X86_INS_VPERMT2W = 1172 , X86_INS_VPERMW = 1173 , X86_INS_VPEXPANDB = 1174 , X86_INS_VPEXPANDD = 1175 , X86_INS_VPEXPANDQ = 1176 , X86_INS_VPEXPANDW = 1177 , X86_INS_VPEXTRB = 1178 , X86_INS_VPEXTRD = 1179 , X86_INS_VPEXTRQ = 1180 , X86_INS_VPEXTRW = 1181 , X86_INS_VPGATHERDD = 1182 , X86_INS_VPGATHERDQ = 1183 , X86_INS_VPGATHERQD = 1184 , X86_INS_VPGATHERQQ = 1185 , X86_INS_VPHADDBD = 1186 , X86_INS_VPHADDBQ = 1187 , X86_INS_VPHADDBW = 1188 , X86_INS_VPHADDDQ = 1189 , X86_INS_VPHADDD = 1190 , X86_INS_VPHADDSW = 1191 , X86_INS_VPHADDUBD = 1192 , X86_INS_VPHADDUBQ = 1193 , X86_INS_VPHADDUBW = 1194 , X86_INS_VPHADDUDQ = 1195 , X86_INS_VPHADDUWD = 1196 , X86_INS_VPHADDUWQ = 1197 , X86_INS_VPHADDWD = 1198 , X86_INS_VPHADDWQ = 1199 , X86_INS_VPHADDW = 1200 , X86_INS_VPHMINPOSUW = 1201 , X86_INS_VPHSUBBW = 1202 , X86_INS_VPHSUBDQ = 1203 , X86_INS_VPHSUBD = 1204 , X86_INS_VPHSUBSW = 1205 , X86_INS_VPHSUBWD = 1206 , X86_INS_VPHSUBW = 1207 , X86_INS_VPINSRB = 1208 , X86_INS_VPINSRD = 1209 , X86_INS_VPINSRQ = 1210 , X86_INS_VPINSRW = 1211 , X86_INS_VPLZCNTD = 1212 , X86_INS_VPLZCNTQ = 1213 , X86_INS_VPMACSDD = 1214 , X86_INS_VPMACSDQH = 1215 , X86_INS_VPMACSDQL = 1216 , X86_INS_VPMACSSDD = 1217 , X86_INS_VPMACSSDQH = 1218 , X86_INS_VPMACSSDQL = 1219 , X86_INS_VPMACSSWD = 1220 , X86_INS_VPMACSSWW = 1221 , X86_INS_VPMACSWD = 1222 , X86_INS_VPMACSWW = 1223 , X86_INS_VPMADCSSWD = 1224 , X86_INS_VPMADCSWD = 1225 , X86_INS_VPMADD52HUQ = 1226 , X86_INS_VPMADD52LUQ = 1227 , X86_INS_VPMADDUBSW = 1228 , X86_INS_VPMADDWD = 1229 , X86_INS_VPMASKMOVD = 1230 , X86_INS_VPMASKMOVQ = 1231 , X86_INS_VPMAXSB = 1232 , X86_INS_VPMAXSD = 1233 , X86_INS_VPMAXSQ = 1234 , X86_INS_VPMAXSW = 1235 , X86_INS_VPMAXUB = 1236 , X86_INS_VPMAXUD = 1237 , X86_INS_VPMAXUQ = 1238 , X86_INS_VPMAXUW = 1239 , X86_INS_VPMINSB = 1240 , X86_INS_VPMINSD = 1241 , X86_INS_VPMINSQ = 1242 , X86_INS_VPMINSW = 1243 , X86_INS_VPMINUB = 1244 , X86_INS_VPMINUD = 1245 , X86_INS_VPMINUQ = 1246 , X86_INS_VPMINUW = 1247 , X86_INS_VPMOVB2M = 1248 , X86_INS_VPMOVD2M = 1249 , X86_INS_VPMOVDB = 1250 , X86_INS_VPMOVDW = 1251 , X86_INS_VPMOVM2B = 1252 , X86_INS_VPMOVM2D = 1253 , X86_INS_VPMOVM2Q = 1254 , X86_INS_VPMOVM2W = 1255 , X86_INS_VPMOVMSKB = 1256 , X86_INS_VPMOVQ2M = 1257 , X86_INS_VPMOVQB = 1258 , X86_INS_VPMOVQD = 1259 , X86_INS_VPMOVQW = 1260 , X86_INS_VPMOVSDB = 1261 , X86_INS_VPMOVSDW = 1262 , X86_INS_VPMOVSQB = 1263 , X86_INS_VPMOVSQD = 1264 , X86_INS_VPMOVSQW = 1265 , X86_INS_VPMOVSWB = 1266 , X86_INS_VPMOVSXBD = 1267 , X86_INS_VPMOVSXBQ = 1268 , X86_INS_VPMOVSXBW = 1269 , X86_INS_VPMOVSXDQ = 1270 , X86_INS_VPMOVSXWD = 1271 , X86_INS_VPMOVSXWQ = 1272 , X86_INS_VPMOVUSDB = 1273 , X86_INS_VPMOVUSDW = 1274 , X86_INS_VPMOVUSQB = 1275 , X86_INS_VPMOVUSQD = 1276 , X86_INS_VPMOVUSQW = 1277 , X86_INS_VPMOVUSWB = 1278 , X86_INS_VPMOVW2M = 1279 , X86_INS_VPMOVWB = 1280 , X86_INS_VPMOVZXBD = 1281 , X86_INS_VPMOVZXBQ = 1282 , X86_INS_VPMOVZXBW = 1283 , X86_INS_VPMOVZXDQ = 1284 , X86_INS_VPMOVZXWD = 1285 , X86_INS_VPMOVZXWQ = 1286 , X86_INS_VPMULDQ = 1287 , X86_INS_VPMULHRSW = 1288 , X86_INS_VPMULHUW = 1289 , X86_INS_VPMULHW = 1290 , X86_INS_VPMULLD = 1291 , X86_INS_VPMULLQ = 1292 , X86_INS_VPMULLW = 1293 , X86_INS_VPMULTISHIFTQB = 1294 , X86_INS_VPMULUDQ = 1295 , X86_INS_VPOPCNTB = 1296 , X86_INS_VPOPCNTD = 1297 , X86_INS_VPOPCNTQ = 1298 , X86_INS_VPOPCNTW = 1299 , X86_INS_VPORD = 1300 , X86_INS_VPORQ = 1301 , X86_INS_VPOR = 1302 , X86_INS_VPPERM = 1303 , X86_INS_VPROLD = 1304 , X86_INS_VPROLQ = 1305 , X86_INS_VPROLVD = 1306 , X86_INS_VPROLVQ = 1307 , X86_INS_VPRORD = 1308 , X86_INS_VPRORQ = 1309 , X86_INS_VPRORVD = 1310 , X86_INS_VPRORVQ = 1311 , X86_INS_VPROTB = 1312 , X86_INS_VPROTD = 1313 , X86_INS_VPROTQ = 1314 , X86_INS_VPROTW = 1315 , X86_INS_VPSADBW = 1316 , X86_INS_VPSCATTERDD = 1317 , X86_INS_VPSCATTERDQ = 1318 , X86_INS_VPSCATTERQD = 1319 , X86_INS_VPSCATTERQQ = 1320 , X86_INS_VPSHAB = 1321 , X86_INS_VPSHAD = 1322 , X86_INS_VPSHAQ = 1323 , X86_INS_VPSHAW = 1324 , X86_INS_VPSHLB = 1325 , X86_INS_VPSHLDD = 1326 , X86_INS_VPSHLDQ = 1327 , X86_INS_VPSHLDVD = 1328 , X86_INS_VPSHLDVQ = 1329 , X86_INS_VPSHLDVW = 1330 , X86_INS_VPSHLDW = 1331 , X86_INS_VPSHLD = 1332 , X86_INS_VPSHLQ = 1333 , X86_INS_VPSHLW = 1334 , X86_INS_VPSHRDD = 1335 , X86_INS_VPSHRDQ = 1336 , X86_INS_VPSHRDVD = 1337 , X86_INS_VPSHRDVQ = 1338 , X86_INS_VPSHRDVW = 1339 , X86_INS_VPSHRDW = 1340 , X86_INS_VPSHUFBITQMB = 1341 , X86_INS_VPSHUFB = 1342 , X86_INS_VPSHUFD = 1343 , X86_INS_VPSHUFHW = 1344 , X86_INS_VPSHUFLW = 1345 , X86_INS_VPSIGNB = 1346 , X86_INS_VPSIGND = 1347 , X86_INS_VPSIGNW = 1348 , X86_INS_VPSLLDQ = 1349 , X86_INS_VPSLLD = 1350 , X86_INS_VPSLLQ = 1351 , X86_INS_VPSLLVD = 1352 , X86_INS_VPSLLVQ = 1353 , X86_INS_VPSLLVW = 1354 , X86_INS_VPSLLW = 1355 , X86_INS_VPSRAD = 1356 , X86_INS_VPSRAQ = 1357 , X86_INS_VPSRAVD = 1358 , X86_INS_VPSRAVQ = 1359 , X86_INS_VPSRAVW = 1360 , X86_INS_VPSRAW = 1361 , X86_INS_VPSRLDQ = 1362 , X86_INS_VPSRLD = 1363 , X86_INS_VPSRLQ = 1364 , X86_INS_VPSRLVD = 1365 , X86_INS_VPSRLVQ = 1366 , X86_INS_VPSRLVW = 1367 , X86_INS_VPSRLW = 1368 , X86_INS_VPSUBB = 1369 , X86_INS_VPSUBD = 1370 , X86_INS_VPSUBQ = 1371 , X86_INS_VPSUBSB = 1372 , X86_INS_VPSUBSW = 1373 , X86_INS_VPSUBUSB = 1374 , X86_INS_VPSUBUSW = 1375 , X86_INS_VPSUBW = 1376 , X86_INS_VPTERNLOGD = 1377 , X86_INS_VPTERNLOGQ = 1378 , X86_INS_VPTESTMB = 1379 , X86_INS_VPTESTMD = 1380 , X86_INS_VPTESTMQ = 1381 , X86_INS_VPTESTMW = 1382 , X86_INS_VPTESTNMB = 1383 , X86_INS_VPTESTNMD = 1384 , X86_INS_VPTESTNMQ = 1385 , X86_INS_VPTESTNMW = 1386 , X86_INS_VPTEST = 1387 , X86_INS_VPUNPCKHBW = 1388 , X86_INS_VPUNPCKHDQ = 1389 , X86_INS_VPUNPCKHQDQ = 1390 , X86_INS_VPUNPCKHWD = 1391 , X86_INS_VPUNPCKLBW = 1392 , X86_INS_VPUNPCKLDQ = 1393 , X86_INS_VPUNPCKLQDQ = 1394 , X86_INS_VPUNPCKLWD = 1395 , X86_INS_VPXORD = 1396 , X86_INS_VPXORQ = 1397 , X86_INS_VPXOR = 1398 , X86_INS_VRANGEPD = 1399 , X86_INS_VRANGEPS = 1400 , X86_INS_VRANGESD = 1401 , X86_INS_VRANGESS = 1402 , X86_INS_VRCP14PD = 1403 , X86_INS_VRCP14PS = 1404 , X86_INS_VRCP14SD = 1405 , X86_INS_VRCP14SS = 1406 , X86_INS_VRCP28PD = 1407 , X86_INS_VRCP28PS = 1408 , X86_INS_VRCP28SD = 1409 , X86_INS_VRCP28SS = 1410 , X86_INS_VRCPPS = 1411 , X86_INS_VRCPSS = 1412 , X86_INS_VREDUCEPD = 1413 , X86_INS_VREDUCEPS = 1414 , X86_INS_VREDUCESD = 1415 , X86_INS_VREDUCESS = 1416 , X86_INS_VRNDSCALEPD = 1417 , X86_INS_VRNDSCALEPS = 1418 , X86_INS_VRNDSCALESD = 1419 , X86_INS_VRNDSCALESS = 1420 , X86_INS_VROUNDPD = 1421 , X86_INS_VROUNDPS = 1422 , X86_INS_VROUNDSD = 1423 , X86_INS_VROUNDSS = 1424 , X86_INS_VRSQRT14PD = 1425 , X86_INS_VRSQRT14PS = 1426 , X86_INS_VRSQRT14SD = 1427 , X86_INS_VRSQRT14SS = 1428 , X86_INS_VRSQRT28PD = 1429 , X86_INS_VRSQRT28PS = 1430 , X86_INS_VRSQRT28SD = 1431 , X86_INS_VRSQRT28SS = 1432 , X86_INS_VRSQRTPS = 1433 , X86_INS_VRSQRTSS = 1434 , X86_INS_VSCALEFPD = 1435 , X86_INS_VSCALEFPS = 1436 , X86_INS_VSCALEFSD = 1437 , X86_INS_VSCALEFSS = 1438 , X86_INS_VSCATTERDPD = 1439 , X86_INS_VSCATTERDPS = 1440 , X86_INS_VSCATTERPF0DPD = 1441 , X86_INS_VSCATTERPF0DPS = 1442 , X86_INS_VSCATTERPF0QPD = 1443 , X86_INS_VSCATTERPF0QPS = 1444 , X86_INS_VSCATTERPF1DPD = 1445 , X86_INS_VSCATTERPF1DPS = 1446 , X86_INS_VSCATTERPF1QPD = 1447 , X86_INS_VSCATTERPF1QPS = 1448 , X86_INS_VSCATTERQPD = 1449 , X86_INS_VSCATTERQPS = 1450 , X86_INS_VSHUFF32X4 = 1451 , X86_INS_VSHUFF64X2 = 1452 , X86_INS_VSHUFI32X4 = 1453 , X86_INS_VSHUFI64X2 = 1454 , X86_INS_VSHUFPD = 1455 , X86_INS_VSHUFPS = 1456 , X86_INS_VSQRTPD = 1457 , X86_INS_VSQRTPS = 1458 , X86_INS_VSQRTSD = 1459 , X86_INS_VSQRTSS = 1460 , X86_INS_VSTMXCSR = 1461 , X86_INS_VSUBPD = 1462 , X86_INS_VSUBPS = 1463 , X86_INS_VSUBSD = 1464 , X86_INS_VSUBSS = 1465 , X86_INS_VTESTPD = 1466 , X86_INS_VTESTPS = 1467 , X86_INS_VUCOMISD = 1468 , X86_INS_VUCOMISS = 1469 , X86_INS_VUNPCKHPD = 1470 , X86_INS_VUNPCKHPS = 1471 , X86_INS_VUNPCKLPD = 1472 , X86_INS_VUNPCKLPS = 1473 , X86_INS_VXORPD = 1474 , X86_INS_VXORPS = 1475 , X86_INS_VZEROALL = 1476 , X86_INS_VZEROUPPER = 1477 , X86_INS_WAIT = 1478 , X86_INS_WBINVD = 1479 , X86_INS_WBNOINVD = 1480 , X86_INS_WRFSBASE = 1481 , X86_INS_WRGSBASE = 1482 , X86_INS_WRMSR = 1483 , X86_INS_WRPKRU = 1484 , X86_INS_WRSSD = 1485 , X86_INS_WRSSQ = 1486 , X86_INS_WRUSSD = 1487 , X86_INS_WRUSSQ = 1488 , X86_INS_XABORT = 1489 , X86_INS_XACQUIRE = 1490 , X86_INS_XADD = 1491 , X86_INS_XBEGIN = 1492 , X86_INS_XCHG = 1493 , X86_INS_FXCH = 1494 , X86_INS_XCRYPTCBC = 1495 , X86_INS_XCRYPTCFB = 1496 , X86_INS_XCRYPTCTR = 1497 , X86_INS_XCRYPTECB = 1498 , X86_INS_XCRYPTOFB = 1499 , X86_INS_XEND = 1500 , X86_INS_XGETBV = 1501 , X86_INS_XLATB = 1502 , X86_INS_XOR = 1503 , X86_INS_XORPD = 1504 , X86_INS_XORPS = 1505 , X86_INS_XRELEASE = 1506 , X86_INS_XRSTOR = 1507 , X86_INS_XRSTOR64 = 1508 , X86_INS_XRSTORS = 1509 , X86_INS_XRSTORS64 = 1510 , X86_INS_XSAVE = 1511 , X86_INS_XSAVE64 = 1512 , X86_INS_XSAVEC = 1513 , X86_INS_XSAVEC64 = 1514 , X86_INS_XSAVEOPT = 1515 , X86_INS_XSAVEOPT64 = 1516 , X86_INS_XSAVES = 1517 , X86_INS_XSAVES64 = 1518 , X86_INS_XSETBV = 1519 , X86_INS_XSHA1 = 1520 , X86_INS_XSHA256 = 1521 , X86_INS_XSTORE = 1522 , X86_INS_XTEST = 1523 , X86_INS_ENDING = 1524 , } # [repr (u32)] # [doc = " Group of X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn_group { # [doc = "< = CS_GRP_INVALID"] X86_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] X86_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] X86_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] X86_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] X86_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] X86_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] X86_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] X86_GRP_BRANCH_RELATIVE = 7 , # [doc = "< all virtualization instructions (VT-x + AMD-V)"] X86_GRP_VM = 128 , X86_GRP_3DNOW = 129 , X86_GRP_AES = 130 , X86_GRP_ADX = 131 , X86_GRP_AVX = 132 , X86_GRP_AVX2 = 133 , X86_GRP_AVX512 = 134 , X86_GRP_BMI = 135 , X86_GRP_BMI2 = 136 , X86_GRP_CMOV = 137 , X86_GRP_F16C = 138 , X86_GRP_FMA = 139 , X86_GRP_FMA4 = 140 , X86_GRP_FSGSBASE = 141 , X86_GRP_HLE = 142 , X86_GRP_MMX = 143 , X86_GRP_MODE32 = 144 , X86_GRP_MODE64 = 145 , X86_GRP_RTM = 146 , X86_GRP_SHA = 147 , X86_GRP_SSE1 = 148 , X86_GRP_SSE2 = 149 , X86_GRP_SSE3 = 150 , X86_GRP_SSE41 = 151 , X86_GRP_SSE42 = 152 , X86_GRP_SSE4A = 153 , X86_GRP_SSSE3 = 154 , X86_GRP_PCLMUL = 155 , X86_GRP_XOP = 156 , X86_GRP_CDI = 157 , X86_GRP_ERI = 158 , X86_GRP_TBM = 159 , X86_GRP_16BITMODE = 160 , X86_GRP_NOT64BITMODE = 161 , X86_GRP_SGX = 162 , X86_GRP_DQI = 163 , X86_GRP_BWI = 164 , X86_GRP_PFI = 165 , X86_GRP_VLX = 166 , X86_GRP_SMAP = 167 , X86_GRP_NOVLX = 168 , X86_GRP_FPU = 169 , X86_GRP_ENDING = 170 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] XCORE_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] XCORE_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] XCORE_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] XCORE_OP_MEM = 3 , } # [repr (u32)] # [doc = " XCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_reg { XCORE_REG_INVALID = 0 , XCORE_REG_CP = 1 , XCORE_REG_DP = 2 , XCORE_REG_LR = 3 , XCORE_REG_SP = 4 , XCORE_REG_R0 = 5 , XCORE_REG_R1 = 6 , XCORE_REG_R2 = 7 , XCORE_REG_R3 = 8 , XCORE_REG_R4 = 9 , XCORE_REG_R5 = 10 , XCORE_REG_R6 = 11 , XCORE_REG_R7 = 12 , XCORE_REG_R8 = 13 , XCORE_REG_R9 = 14 , XCORE_REG_R10 = 15 , XCORE_REG_R11 = 16 , # [doc = "< pc"] XCORE_REG_PC = 17 , # [doc = "< save pc"] XCORE_REG_SCP = 18 , XCORE_REG_SSR = 19 , XCORE_REG_ET = 20 , XCORE_REG_ED = 21 , XCORE_REG_SED = 22 , XCORE_REG_KEP = 23 , XCORE_REG_KSP = 24 , XCORE_REG_ID = 25 , XCORE_REG_ENDING = 26 , } # [doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct xcore_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , # [doc = "< +1: forward, -1: backward"] pub direct : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of xcore_op_mem"] [:: std :: mem :: size_of :: < xcore_op_mem > () - 12usize] ; ["Alignment of xcore_op_mem"] [:: std :: mem :: align_of :: < xcore_op_mem > () - 4usize] ; ["Offset of field: xcore_op_mem::base"] [:: std :: mem :: offset_of ! (xcore_op_mem , base) - 0usize] ; ["Offset of field: xcore_op_mem::index"] [:: std :: mem :: offset_of ! (xcore_op_mem , index) - 1usize] ; ["Offset of field: xcore_op_mem::disp"] [:: std :: mem :: offset_of ! (xcore_op_mem , disp) - 4usize] ; ["Offset of field: xcore_op_mem::direct"] [:: std :: mem :: offset_of ! (xcore_op_mem , direct) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore_op { # [doc = "< operand type"] pub type_ : xcore_op_type , pub __bindgen_anon_1 : cs_xcore_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_xcore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : xcore_reg , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : xcore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_xcore_op__bindgen_ty_1 > () - 12usize] ; ["Alignment of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_xcore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op"] [:: std :: mem :: size_of :: < cs_xcore_op > () - 16usize] ; ["Alignment of cs_xcore_op"] [:: std :: mem :: align_of :: < cs_xcore_op > () - 4usize] ; ["Offset of field: cs_xcore_op::type_"] [:: std :: mem :: offset_of ! (cs_xcore_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_xcore_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore"] [:: std :: mem :: size_of :: < cs_xcore > () - 132usize] ; ["Alignment of cs_xcore"] [:: std :: mem :: align_of :: < cs_xcore > () - 4usize] ; ["Offset of field: cs_xcore::op_count"] [:: std :: mem :: offset_of ! (cs_xcore , op_count) - 0usize] ; ["Offset of field: cs_xcore::operands"] [:: std :: mem :: offset_of ! (cs_xcore , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " XCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn { XCORE_INS_INVALID = 0 , XCORE_INS_ADD = 1 , XCORE_INS_ANDNOT = 2 , XCORE_INS_AND = 3 , XCORE_INS_ASHR = 4 , XCORE_INS_BAU = 5 , XCORE_INS_BITREV = 6 , XCORE_INS_BLA = 7 , XCORE_INS_BLAT = 8 , XCORE_INS_BL = 9 , XCORE_INS_BF = 10 , XCORE_INS_BT = 11 , XCORE_INS_BU = 12 , XCORE_INS_BRU = 13 , XCORE_INS_BYTEREV = 14 , XCORE_INS_CHKCT = 15 , XCORE_INS_CLRE = 16 , XCORE_INS_CLRPT = 17 , XCORE_INS_CLRSR = 18 , XCORE_INS_CLZ = 19 , XCORE_INS_CRC8 = 20 , XCORE_INS_CRC32 = 21 , XCORE_INS_DCALL = 22 , XCORE_INS_DENTSP = 23 , XCORE_INS_DGETREG = 24 , XCORE_INS_DIVS = 25 , XCORE_INS_DIVU = 26 , XCORE_INS_DRESTSP = 27 , XCORE_INS_DRET = 28 , XCORE_INS_ECALLF = 29 , XCORE_INS_ECALLT = 30 , XCORE_INS_EDU = 31 , XCORE_INS_EEF = 32 , XCORE_INS_EET = 33 , XCORE_INS_EEU = 34 , XCORE_INS_ENDIN = 35 , XCORE_INS_ENTSP = 36 , XCORE_INS_EQ = 37 , XCORE_INS_EXTDP = 38 , XCORE_INS_EXTSP = 39 , XCORE_INS_FREER = 40 , XCORE_INS_FREET = 41 , XCORE_INS_GETD = 42 , XCORE_INS_GET = 43 , XCORE_INS_GETN = 44 , XCORE_INS_GETR = 45 , XCORE_INS_GETSR = 46 , XCORE_INS_GETST = 47 , XCORE_INS_GETTS = 48 , XCORE_INS_INCT = 49 , XCORE_INS_INIT = 50 , XCORE_INS_INPW = 51 , XCORE_INS_INSHR = 52 , XCORE_INS_INT = 53 , XCORE_INS_IN = 54 , XCORE_INS_KCALL = 55 , XCORE_INS_KENTSP = 56 , XCORE_INS_KRESTSP = 57 , XCORE_INS_KRET = 58 , XCORE_INS_LADD = 59 , XCORE_INS_LD16S = 60 , XCORE_INS_LD8U = 61 , XCORE_INS_LDA16 = 62 , XCORE_INS_LDAP = 63 , XCORE_INS_LDAW = 64 , XCORE_INS_LDC = 65 , XCORE_INS_LDW = 66 , XCORE_INS_LDIVU = 67 , XCORE_INS_LMUL = 68 , XCORE_INS_LSS = 69 , XCORE_INS_LSUB = 70 , XCORE_INS_LSU = 71 , XCORE_INS_MACCS = 72 , XCORE_INS_MACCU = 73 , XCORE_INS_MJOIN = 74 , XCORE_INS_MKMSK = 75 , XCORE_INS_MSYNC = 76 , XCORE_INS_MUL = 77 , XCORE_INS_NEG = 78 , XCORE_INS_NOT = 79 , XCORE_INS_OR = 80 , XCORE_INS_OUTCT = 81 , XCORE_INS_OUTPW = 82 , XCORE_INS_OUTSHR = 83 , XCORE_INS_OUTT = 84 , XCORE_INS_OUT = 85 , XCORE_INS_PEEK = 86 , XCORE_INS_REMS = 87 , XCORE_INS_REMU = 88 , XCORE_INS_RETSP = 89 , XCORE_INS_SETCLK = 90 , XCORE_INS_SET = 91 , XCORE_INS_SETC = 92 , XCORE_INS_SETD = 93 , XCORE_INS_SETEV = 94 , XCORE_INS_SETN = 95 , XCORE_INS_SETPSC = 96 , XCORE_INS_SETPT = 97 , XCORE_INS_SETRDY = 98 , XCORE_INS_SETSR = 99 , XCORE_INS_SETTW = 100 , XCORE_INS_SETV = 101 , XCORE_INS_SEXT = 102 , XCORE_INS_SHL = 103 , XCORE_INS_SHR = 104 , XCORE_INS_SSYNC = 105 , XCORE_INS_ST16 = 106 , XCORE_INS_ST8 = 107 , XCORE_INS_STW = 108 , XCORE_INS_SUB = 109 , XCORE_INS_SYNCR = 110 , XCORE_INS_TESTCT = 111 , XCORE_INS_TESTLCL = 112 , XCORE_INS_TESTWCT = 113 , XCORE_INS_TSETMR = 114 , XCORE_INS_START = 115 , XCORE_INS_WAITEF = 116 , XCORE_INS_WAITET = 117 , XCORE_INS_WAITEU = 118 , XCORE_INS_XOR = 119 , XCORE_INS_ZEXT = 120 , XCORE_INS_ENDING = 121 , } # [repr (u32)] # [doc = " Group of XCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn_group { # [doc = "< = CS_GRP_INVALID"] XCORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] XCORE_GRP_JUMP = 1 , XCORE_GRP_ENDING = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] TMS320C64X_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] TMS320C64X_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] TMS320C64X_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] TMS320C64X_OP_MEM = 3 , # [doc = "< Register pair for double word ops"] TMS320C64X_OP_REGPAIR = 64 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0 , TMS320C64X_MEM_DISP_CONSTANT = 1 , TMS320C64X_MEM_DISP_REGISTER = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0 , TMS320C64X_MEM_DIR_FW = 1 , TMS320C64X_MEM_DIR_BW = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0 , TMS320C64X_MEM_MOD_NO = 1 , TMS320C64X_MEM_MOD_PRE = 2 , TMS320C64X_MEM_MOD_POST = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tms320c64x_op_mem { # [doc = "< base register"] pub base : :: std :: os :: raw :: c_uint , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_uint , # [doc = "< unit of base and offset register"] pub unit : :: std :: os :: raw :: c_uint , # [doc = "< offset scaled"] pub scaled : :: std :: os :: raw :: c_uint , # [doc = "< displacement type"] pub disptype : :: std :: os :: raw :: c_uint , # [doc = "< direction"] pub direction : :: std :: os :: raw :: c_uint , # [doc = "< modification"] pub modify : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tms320c64x_op_mem"] [:: std :: mem :: size_of :: < tms320c64x_op_mem > () - 28usize] ; ["Alignment of tms320c64x_op_mem"] [:: std :: mem :: align_of :: < tms320c64x_op_mem > () - 4usize] ; ["Offset of field: tms320c64x_op_mem::base"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , base) - 0usize] ; ["Offset of field: tms320c64x_op_mem::disp"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disp) - 4usize] ; ["Offset of field: tms320c64x_op_mem::unit"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , unit) - 8usize] ; ["Offset of field: tms320c64x_op_mem::scaled"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , scaled) - 12usize] ; ["Offset of field: tms320c64x_op_mem::disptype"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disptype) - 16usize] ; ["Offset of field: tms320c64x_op_mem::direction"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , direction) - 20usize] ; ["Offset of field: tms320c64x_op_mem::modify"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , modify) - 24usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x_op { # [doc = "< operand type"] pub type_ : tms320c64x_op_type , pub __bindgen_anon_1 : cs_tms320c64x_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tms320c64x_op__bindgen_ty_1 { # [doc = "< register value for REG operand or first register for REGPAIR operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tms320c64x_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 28usize] ; ["Alignment of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op"] [:: std :: mem :: size_of :: < cs_tms320c64x_op > () - 32usize] ; ["Alignment of cs_tms320c64x_op"] [:: std :: mem :: align_of :: < cs_tms320c64x_op > () - 4usize] ; ["Offset of field: cs_tms320c64x_op::type_"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x { pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tms320c64x_op ; 8usize] , pub condition : cs_tms320c64x__bindgen_ty_1 , pub funit : cs_tms320c64x__bindgen_ty_2 , pub parallel : :: std :: os :: raw :: c_uint , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub zero : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::zero"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , zero) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_2 { pub unit : :: std :: os :: raw :: c_uint , pub side : :: std :: os :: raw :: c_uint , pub crosspath : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_2 > () - 12usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_2 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::unit"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , unit) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::side"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , side) - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::crosspath"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , crosspath) - 8usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x"] [:: std :: mem :: size_of :: < cs_tms320c64x > () - 284usize] ; ["Alignment of cs_tms320c64x"] [:: std :: mem :: align_of :: < cs_tms320c64x > () - 4usize] ; ["Offset of field: cs_tms320c64x::op_count"] [:: std :: mem :: offset_of ! (cs_tms320c64x , op_count) - 0usize] ; ["Offset of field: cs_tms320c64x::operands"] [:: std :: mem :: offset_of ! (cs_tms320c64x , operands) - 4usize] ; ["Offset of field: cs_tms320c64x::condition"] [:: std :: mem :: offset_of ! (cs_tms320c64x , condition) - 260usize] ; ["Offset of field: cs_tms320c64x::funit"] [:: std :: mem :: offset_of ! (cs_tms320c64x , funit) - 268usize] ; ["Offset of field: cs_tms320c64x::parallel"] [:: std :: mem :: offset_of ! (cs_tms320c64x , parallel) - 280usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel) } } impl tms320c64x_reg { pub const TMS320C64X_REG_EFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ECR ; } impl tms320c64x_reg { pub const TMS320C64X_REG_IFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ISR ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0 , TMS320C64X_REG_AMR = 1 , TMS320C64X_REG_CSR = 2 , TMS320C64X_REG_DIER = 3 , TMS320C64X_REG_DNUM = 4 , TMS320C64X_REG_ECR = 5 , TMS320C64X_REG_GFPGFR = 6 , TMS320C64X_REG_GPLYA = 7 , TMS320C64X_REG_GPLYB = 8 , TMS320C64X_REG_ICR = 9 , TMS320C64X_REG_IER = 10 , TMS320C64X_REG_IERR = 11 , TMS320C64X_REG_ILC = 12 , TMS320C64X_REG_IRP = 13 , TMS320C64X_REG_ISR = 14 , TMS320C64X_REG_ISTP = 15 , TMS320C64X_REG_ITSR = 16 , TMS320C64X_REG_NRP = 17 , TMS320C64X_REG_NTSR = 18 , TMS320C64X_REG_REP = 19 , TMS320C64X_REG_RILC = 20 , TMS320C64X_REG_SSR = 21 , TMS320C64X_REG_TSCH = 22 , TMS320C64X_REG_TSCL = 23 , TMS320C64X_REG_TSR = 24 , TMS320C64X_REG_A0 = 25 , TMS320C64X_REG_A1 = 26 , TMS320C64X_REG_A2 = 27 , TMS320C64X_REG_A3 = 28 , TMS320C64X_REG_A4 = 29 , TMS320C64X_REG_A5 = 30 , TMS320C64X_REG_A6 = 31 , TMS320C64X_REG_A7 = 32 , TMS320C64X_REG_A8 = 33 , TMS320C64X_REG_A9 = 34 , TMS320C64X_REG_A10 = 35 , TMS320C64X_REG_A11 = 36 , TMS320C64X_REG_A12 = 37 , TMS320C64X_REG_A13 = 38 , TMS320C64X_REG_A14 = 39 , TMS320C64X_REG_A15 = 40 , TMS320C64X_REG_A16 = 41 , TMS320C64X_REG_A17 = 42 , TMS320C64X_REG_A18 = 43 , TMS320C64X_REG_A19 = 44 , TMS320C64X_REG_A20 = 45 , TMS320C64X_REG_A21 = 46 , TMS320C64X_REG_A22 = 47 , TMS320C64X_REG_A23 = 48 , TMS320C64X_REG_A24 = 49 , TMS320C64X_REG_A25 = 50 , TMS320C64X_REG_A26 = 51 , TMS320C64X_REG_A27 = 52 , TMS320C64X_REG_A28 = 53 , TMS320C64X_REG_A29 = 54 , TMS320C64X_REG_A30 = 55 , TMS320C64X_REG_A31 = 56 , TMS320C64X_REG_B0 = 57 , TMS320C64X_REG_B1 = 58 , TMS320C64X_REG_B2 = 59 , TMS320C64X_REG_B3 = 60 , TMS320C64X_REG_B4 = 61 , TMS320C64X_REG_B5 = 62 , TMS320C64X_REG_B6 = 63 , TMS320C64X_REG_B7 = 64 , TMS320C64X_REG_B8 = 65 , TMS320C64X_REG_B9 = 66 , TMS320C64X_REG_B10 = 67 , TMS320C64X_REG_B11 = 68 , TMS320C64X_REG_B12 = 69 , TMS320C64X_REG_B13 = 70 , TMS320C64X_REG_B14 = 71 , TMS320C64X_REG_B15 = 72 , TMS320C64X_REG_B16 = 73 , TMS320C64X_REG_B17 = 74 , TMS320C64X_REG_B18 = 75 , TMS320C64X_REG_B19 = 76 , TMS320C64X_REG_B20 = 77 , TMS320C64X_REG_B21 = 78 , TMS320C64X_REG_B22 = 79 , TMS320C64X_REG_B23 = 80 , TMS320C64X_REG_B24 = 81 , TMS320C64X_REG_B25 = 82 , TMS320C64X_REG_B26 = 83 , TMS320C64X_REG_B27 = 84 , TMS320C64X_REG_B28 = 85 , TMS320C64X_REG_B29 = 86 , TMS320C64X_REG_B30 = 87 , TMS320C64X_REG_B31 = 88 , TMS320C64X_REG_PCE1 = 89 , TMS320C64X_REG_ENDING = 90 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0 , TMS320C64X_INS_ABS = 1 , TMS320C64X_INS_ABS2 = 2 , TMS320C64X_INS_ADD = 3 , TMS320C64X_INS_ADD2 = 4 , TMS320C64X_INS_ADD4 = 5 , TMS320C64X_INS_ADDAB = 6 , TMS320C64X_INS_ADDAD = 7 , TMS320C64X_INS_ADDAH = 8 , TMS320C64X_INS_ADDAW = 9 , TMS320C64X_INS_ADDK = 10 , TMS320C64X_INS_ADDKPC = 11 , TMS320C64X_INS_ADDU = 12 , TMS320C64X_INS_AND = 13 , TMS320C64X_INS_ANDN = 14 , TMS320C64X_INS_AVG2 = 15 , TMS320C64X_INS_AVGU4 = 16 , TMS320C64X_INS_B = 17 , TMS320C64X_INS_BDEC = 18 , TMS320C64X_INS_BITC4 = 19 , TMS320C64X_INS_BNOP = 20 , TMS320C64X_INS_BPOS = 21 , TMS320C64X_INS_CLR = 22 , TMS320C64X_INS_CMPEQ = 23 , TMS320C64X_INS_CMPEQ2 = 24 , TMS320C64X_INS_CMPEQ4 = 25 , TMS320C64X_INS_CMPGT = 26 , TMS320C64X_INS_CMPGT2 = 27 , TMS320C64X_INS_CMPGTU4 = 28 , TMS320C64X_INS_CMPLT = 29 , TMS320C64X_INS_CMPLTU = 30 , TMS320C64X_INS_DEAL = 31 , TMS320C64X_INS_DOTP2 = 32 , TMS320C64X_INS_DOTPN2 = 33 , TMS320C64X_INS_DOTPNRSU2 = 34 , TMS320C64X_INS_DOTPRSU2 = 35 , TMS320C64X_INS_DOTPSU4 = 36 , TMS320C64X_INS_DOTPU4 = 37 , TMS320C64X_INS_EXT = 38 , TMS320C64X_INS_EXTU = 39 , TMS320C64X_INS_GMPGTU = 40 , TMS320C64X_INS_GMPY4 = 41 , TMS320C64X_INS_LDB = 42 , TMS320C64X_INS_LDBU = 43 , TMS320C64X_INS_LDDW = 44 , TMS320C64X_INS_LDH = 45 , TMS320C64X_INS_LDHU = 46 , TMS320C64X_INS_LDNDW = 47 , TMS320C64X_INS_LDNW = 48 , TMS320C64X_INS_LDW = 49 , TMS320C64X_INS_LMBD = 50 , TMS320C64X_INS_MAX2 = 51 , TMS320C64X_INS_MAXU4 = 52 , TMS320C64X_INS_MIN2 = 53 , TMS320C64X_INS_MINU4 = 54 , TMS320C64X_INS_MPY = 55 , TMS320C64X_INS_MPY2 = 56 , TMS320C64X_INS_MPYH = 57 , TMS320C64X_INS_MPYHI = 58 , TMS320C64X_INS_MPYHIR = 59 , TMS320C64X_INS_MPYHL = 60 , TMS320C64X_INS_MPYHLU = 61 , TMS320C64X_INS_MPYHSLU = 62 , TMS320C64X_INS_MPYHSU = 63 , TMS320C64X_INS_MPYHU = 64 , TMS320C64X_INS_MPYHULS = 65 , TMS320C64X_INS_MPYHUS = 66 , TMS320C64X_INS_MPYLH = 67 , TMS320C64X_INS_MPYLHU = 68 , TMS320C64X_INS_MPYLI = 69 , TMS320C64X_INS_MPYLIR = 70 , TMS320C64X_INS_MPYLSHU = 71 , TMS320C64X_INS_MPYLUHS = 72 , TMS320C64X_INS_MPYSU = 73 , TMS320C64X_INS_MPYSU4 = 74 , TMS320C64X_INS_MPYU = 75 , TMS320C64X_INS_MPYU4 = 76 , TMS320C64X_INS_MPYUS = 77 , TMS320C64X_INS_MVC = 78 , TMS320C64X_INS_MVD = 79 , TMS320C64X_INS_MVK = 80 , TMS320C64X_INS_MVKL = 81 , TMS320C64X_INS_MVKLH = 82 , TMS320C64X_INS_NOP = 83 , TMS320C64X_INS_NORM = 84 , TMS320C64X_INS_OR = 85 , TMS320C64X_INS_PACK2 = 86 , TMS320C64X_INS_PACKH2 = 87 , TMS320C64X_INS_PACKH4 = 88 , TMS320C64X_INS_PACKHL2 = 89 , TMS320C64X_INS_PACKL4 = 90 , TMS320C64X_INS_PACKLH2 = 91 , TMS320C64X_INS_ROTL = 92 , TMS320C64X_INS_SADD = 93 , TMS320C64X_INS_SADD2 = 94 , TMS320C64X_INS_SADDU4 = 95 , TMS320C64X_INS_SADDUS2 = 96 , TMS320C64X_INS_SAT = 97 , TMS320C64X_INS_SET = 98 , TMS320C64X_INS_SHFL = 99 , TMS320C64X_INS_SHL = 100 , TMS320C64X_INS_SHLMB = 101 , TMS320C64X_INS_SHR = 102 , TMS320C64X_INS_SHR2 = 103 , TMS320C64X_INS_SHRMB = 104 , TMS320C64X_INS_SHRU = 105 , TMS320C64X_INS_SHRU2 = 106 , TMS320C64X_INS_SMPY = 107 , TMS320C64X_INS_SMPY2 = 108 , TMS320C64X_INS_SMPYH = 109 , TMS320C64X_INS_SMPYHL = 110 , TMS320C64X_INS_SMPYLH = 111 , TMS320C64X_INS_SPACK2 = 112 , TMS320C64X_INS_SPACKU4 = 113 , TMS320C64X_INS_SSHL = 114 , TMS320C64X_INS_SSHVL = 115 , TMS320C64X_INS_SSHVR = 116 , TMS320C64X_INS_SSUB = 117 , TMS320C64X_INS_STB = 118 , TMS320C64X_INS_STDW = 119 , TMS320C64X_INS_STH = 120 , TMS320C64X_INS_STNDW = 121 , TMS320C64X_INS_STNW = 122 , TMS320C64X_INS_STW = 123 , TMS320C64X_INS_SUB = 124 , TMS320C64X_INS_SUB2 = 125 , TMS320C64X_INS_SUB4 = 126 , TMS320C64X_INS_SUBAB = 127 , TMS320C64X_INS_SUBABS4 = 128 , TMS320C64X_INS_SUBAH = 129 , TMS320C64X_INS_SUBAW = 130 , TMS320C64X_INS_SUBC = 131 , TMS320C64X_INS_SUBU = 132 , TMS320C64X_INS_SWAP4 = 133 , TMS320C64X_INS_UNPKHU4 = 134 , TMS320C64X_INS_UNPKLU4 = 135 , TMS320C64X_INS_XOR = 136 , TMS320C64X_INS_XPND2 = 137 , TMS320C64X_INS_XPND4 = 138 , TMS320C64X_INS_IDLE = 139 , TMS320C64X_INS_MV = 140 , TMS320C64X_INS_NEG = 141 , TMS320C64X_INS_NOT = 142 , TMS320C64X_INS_SWAP2 = 143 , TMS320C64X_INS_ZERO = 144 , TMS320C64X_INS_ENDING = 145 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn_group { # [doc = "< = CS_GRP_INVALID"] TMS320C64X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] TMS320C64X_GRP_JUMP = 1 , TMS320C64X_GRP_FUNIT_D = 128 , TMS320C64X_GRP_FUNIT_L = 129 , TMS320C64X_GRP_FUNIT_M = 130 , TMS320C64X_GRP_FUNIT_S = 131 , TMS320C64X_GRP_FUNIT_NO = 132 , TMS320C64X_GRP_ENDING = 133 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0 , TMS320C64X_FUNIT_D = 1 , TMS320C64X_FUNIT_L = 2 , TMS320C64X_FUNIT_M = 3 , TMS320C64X_FUNIT_S = 4 , TMS320C64X_FUNIT_NO = 5 , } # [repr (u32)] # [doc = " M680X registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_reg { M680X_REG_INVALID = 0 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_A = 1 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_B = 2 , # [doc = "< HD6309"] M680X_REG_E = 3 , # [doc = "< HD6309"] M680X_REG_F = 4 , # [doc = "< HD6309"] M680X_REG_0 = 5 , # [doc = "< M6801/3/9, HD6301/9"] M680X_REG_D = 6 , # [doc = "< HD6309"] M680X_REG_W = 7 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_CC = 8 , # [doc = "< M6809/M6309"] M680X_REG_DP = 9 , # [doc = "< M6309"] M680X_REG_MD = 10 , # [doc = "< M6808"] M680X_REG_HX = 11 , # [doc = "< M6808"] M680X_REG_H = 12 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_X = 13 , # [doc = "< M6809/M6309"] M680X_REG_Y = 14 , # [doc = "< M6809/M6309"] M680X_REG_S = 15 , # [doc = "< M6809/M6309"] M680X_REG_U = 16 , # [doc = "< M6309"] M680X_REG_V = 17 , # [doc = "< M6309"] M680X_REG_Q = 18 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_PC = 19 , # [doc = "< CPU12"] M680X_REG_TMP2 = 20 , # [doc = "< CPU12"] M680X_REG_TMP3 = 21 , # [doc = "< <-- mark the end of the list of registers"] M680X_REG_ENDING = 22 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M680X_OP_INVALID = 0 , # [doc = "< = Register operand."] M680X_OP_REGISTER = 1 , # [doc = "< = Immediate operand."] M680X_OP_IMMEDIATE = 2 , # [doc = "< = Indexed addressing operand."] M680X_OP_INDEXED = 3 , # [doc = "< = Extended addressing operand."] M680X_OP_EXTENDED = 4 , # [doc = "< = Direct addressing operand."] M680X_OP_DIRECT = 5 , # [doc = "< = Relative addressing operand."] M680X_OP_RELATIVE = 6 , # [doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."] M680X_OP_CONSTANT = 7 , } # [doc = " Instruction's operand referring to indexed addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_idx { # [doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"] pub base_reg : m680x_reg , # [doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"] pub offset_reg : m680x_reg , # [doc = "< 5-,8- or 16-bit offset. See also offset_bits."] pub offset : i16 , # [doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"] pub offset_addr : u16 , # [doc = "< offset width in bits for indexed addressing"] pub offset_bits : u8 , # [doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"] pub inc_dec : i8 , # [doc = "< 8-bit flags (see above)"] pub flags : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_idx"] [:: std :: mem :: size_of :: < m680x_op_idx > () - 16usize] ; ["Alignment of m680x_op_idx"] [:: std :: mem :: align_of :: < m680x_op_idx > () - 4usize] ; ["Offset of field: m680x_op_idx::base_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , base_reg) - 0usize] ; ["Offset of field: m680x_op_idx::offset_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_reg) - 4usize] ; ["Offset of field: m680x_op_idx::offset"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset) - 8usize] ; ["Offset of field: m680x_op_idx::offset_addr"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_addr) - 10usize] ; ["Offset of field: m680x_op_idx::offset_bits"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_bits) - 12usize] ; ["Offset of field: m680x_op_idx::inc_dec"] [:: std :: mem :: offset_of ! (m680x_op_idx , inc_dec) - 13usize] ; ["Offset of field: m680x_op_idx::flags"] [:: std :: mem :: offset_of ! (m680x_op_idx , flags) - 14usize] ; } ; # [doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_rel { # [doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."] pub address : u16 , # [doc = "< the offset/displacement value"] pub offset : i16 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_rel"] [:: std :: mem :: size_of :: < m680x_op_rel > () - 4usize] ; ["Alignment of m680x_op_rel"] [:: std :: mem :: align_of :: < m680x_op_rel > () - 2usize] ; ["Offset of field: m680x_op_rel::address"] [:: std :: mem :: offset_of ! (m680x_op_rel , address) - 0usize] ; ["Offset of field: m680x_op_rel::offset"] [:: std :: mem :: offset_of ! (m680x_op_rel , offset) - 2usize] ; } ; # [doc = " Instruction's operand referring to extended addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_ext { # [doc = "< The absolute address"] pub address : u16 , # [doc = "< true if extended indirect addressing"] pub indirect : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_ext"] [:: std :: mem :: size_of :: < m680x_op_ext > () - 4usize] ; ["Alignment of m680x_op_ext"] [:: std :: mem :: align_of :: < m680x_op_ext > () - 2usize] ; ["Offset of field: m680x_op_ext::address"] [:: std :: mem :: offset_of ! (m680x_op_ext , address) - 0usize] ; ["Offset of field: m680x_op_ext::indirect"] [:: std :: mem :: offset_of ! (m680x_op_ext , indirect) - 2usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x_op { pub type_ : m680x_op_type , pub __bindgen_anon_1 : cs_m680x_op__bindgen_ty_1 , # [doc = "< size of this operand (in bytes)"] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m680x_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< register value for REG operand"] pub reg : m680x_reg , # [doc = "< Indexed addressing operand"] pub idx : m680x_op_idx , # [doc = "< Relative address. operand (Bcc/LBcc)"] pub rel : m680x_op_rel , # [doc = "< Extended address"] pub ext : m680x_op_ext , # [doc = "<</ Direct address (lower 8-bit)"] pub direct_addr : u8 , # [doc = "< constant value (bit index, page nr.)"] pub const_val : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m680x_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m680x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::idx"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , idx) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::rel"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , rel) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , ext) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::direct_addr"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , direct_addr) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::const_val"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , const_val) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op"] [:: std :: mem :: size_of :: < cs_m680x_op > () - 24usize] ; ["Alignment of cs_m680x_op"] [:: std :: mem :: align_of :: < cs_m680x_op > () - 4usize] ; ["Offset of field: cs_m680x_op::type_"] [:: std :: mem :: offset_of ! (cs_m680x_op , type_) - 0usize] ; ["Offset of field: cs_m680x_op::size"] [:: std :: mem :: offset_of ! (cs_m680x_op , size) - 20usize] ; ["Offset of field: cs_m680x_op::access"] [:: std :: mem :: offset_of ! (cs_m680x_op , access) - 21usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access) } } # [repr (u32)] # [doc = " Group of M680X instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_group_type { M680X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M680X_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] M680X_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] M680X_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] M680X_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] M680X_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEDGE; not used"] M680X_GRP_PRIV = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M680X_GRP_BRAREL = 7 , M680X_GRP_ENDING = 8 , } # [doc = " The M680X instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x { # [doc = "< See: M680X instruction flags"] pub flags : u8 , # [doc = "< number of operands for the instruction or 0"] pub op_count : u8 , # [doc = "< operands for this insn."] pub operands : [cs_m680x_op ; 9usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x"] [:: std :: mem :: size_of :: < cs_m680x > () - 220usize] ; ["Alignment of cs_m680x"] [:: std :: mem :: align_of :: < cs_m680x > () - 4usize] ; ["Offset of field: cs_m680x::flags"] [:: std :: mem :: offset_of ! (cs_m680x , flags) - 0usize] ; ["Offset of field: cs_m680x::op_count"] [:: std :: mem :: offset_of ! (cs_m680x , op_count) - 1usize] ; ["Offset of field: cs_m680x::operands"] [:: std :: mem :: offset_of ! (cs_m680x , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " M680X instruction IDs"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_insn { M680X_INS_INVLD = 0 , # [doc = "< M6800/1/2/3"] M680X_INS_ABA = 1 , M680X_INS_ABX = 2 , M680X_INS_ABY = 3 , M680X_INS_ADC = 4 , M680X_INS_ADCA = 5 , M680X_INS_ADCB = 6 , M680X_INS_ADCD = 7 , M680X_INS_ADCR = 8 , M680X_INS_ADD = 9 , M680X_INS_ADDA = 10 , M680X_INS_ADDB = 11 , M680X_INS_ADDD = 12 , M680X_INS_ADDE = 13 , M680X_INS_ADDF = 14 , M680X_INS_ADDR = 15 , M680X_INS_ADDW = 16 , M680X_INS_AIM = 17 , M680X_INS_AIS = 18 , M680X_INS_AIX = 19 , M680X_INS_AND = 20 , M680X_INS_ANDA = 21 , M680X_INS_ANDB = 22 , M680X_INS_ANDCC = 23 , M680X_INS_ANDD = 24 , M680X_INS_ANDR = 25 , M680X_INS_ASL = 26 , M680X_INS_ASLA = 27 , M680X_INS_ASLB = 28 , # [doc = "< or LSLD"] M680X_INS_ASLD = 29 , M680X_INS_ASR = 30 , M680X_INS_ASRA = 31 , M680X_INS_ASRB = 32 , M680X_INS_ASRD = 33 , M680X_INS_ASRX = 34 , M680X_INS_BAND = 35 , # [doc = "< or BHS"] M680X_INS_BCC = 36 , M680X_INS_BCLR = 37 , # [doc = "< or BLO"] M680X_INS_BCS = 38 , M680X_INS_BEOR = 39 , M680X_INS_BEQ = 40 , M680X_INS_BGE = 41 , M680X_INS_BGND = 42 , M680X_INS_BGT = 43 , M680X_INS_BHCC = 44 , M680X_INS_BHCS = 45 , M680X_INS_BHI = 46 , M680X_INS_BIAND = 47 , M680X_INS_BIEOR = 48 , M680X_INS_BIH = 49 , M680X_INS_BIL = 50 , M680X_INS_BIOR = 51 , M680X_INS_BIT = 52 , M680X_INS_BITA = 53 , M680X_INS_BITB = 54 , M680X_INS_BITD = 55 , M680X_INS_BITMD = 56 , M680X_INS_BLE = 57 , M680X_INS_BLS = 58 , M680X_INS_BLT = 59 , M680X_INS_BMC = 60 , M680X_INS_BMI = 61 , M680X_INS_BMS = 62 , M680X_INS_BNE = 63 , M680X_INS_BOR = 64 , M680X_INS_BPL = 65 , M680X_INS_BRCLR = 66 , M680X_INS_BRSET = 67 , M680X_INS_BRA = 68 , M680X_INS_BRN = 69 , M680X_INS_BSET = 70 , M680X_INS_BSR = 71 , M680X_INS_BVC = 72 , M680X_INS_BVS = 73 , M680X_INS_CALL = 74 , # [doc = "< M6800/1/2/3"] M680X_INS_CBA = 75 , M680X_INS_CBEQ = 76 , M680X_INS_CBEQA = 77 , M680X_INS_CBEQX = 78 , # [doc = "< M6800/1/2/3"] M680X_INS_CLC = 79 , # [doc = "< M6800/1/2/3"] M680X_INS_CLI = 80 , M680X_INS_CLR = 81 , M680X_INS_CLRA = 82 , M680X_INS_CLRB = 83 , M680X_INS_CLRD = 84 , M680X_INS_CLRE = 85 , M680X_INS_CLRF = 86 , M680X_INS_CLRH = 87 , M680X_INS_CLRW = 88 , M680X_INS_CLRX = 89 , # [doc = "< M6800/1/2/3"] M680X_INS_CLV = 90 , M680X_INS_CMP = 91 , M680X_INS_CMPA = 92 , M680X_INS_CMPB = 93 , M680X_INS_CMPD = 94 , M680X_INS_CMPE = 95 , M680X_INS_CMPF = 96 , M680X_INS_CMPR = 97 , M680X_INS_CMPS = 98 , M680X_INS_CMPU = 99 , M680X_INS_CMPW = 100 , M680X_INS_CMPX = 101 , M680X_INS_CMPY = 102 , M680X_INS_COM = 103 , M680X_INS_COMA = 104 , M680X_INS_COMB = 105 , M680X_INS_COMD = 106 , M680X_INS_COME = 107 , M680X_INS_COMF = 108 , M680X_INS_COMW = 109 , M680X_INS_COMX = 110 , M680X_INS_CPD = 111 , M680X_INS_CPHX = 112 , M680X_INS_CPS = 113 , # [doc = "< M6800/1/2/3"] M680X_INS_CPX = 114 , M680X_INS_CPY = 115 , M680X_INS_CWAI = 116 , M680X_INS_DAA = 117 , M680X_INS_DBEQ = 118 , M680X_INS_DBNE = 119 , M680X_INS_DBNZ = 120 , M680X_INS_DBNZA = 121 , M680X_INS_DBNZX = 122 , M680X_INS_DEC = 123 , M680X_INS_DECA = 124 , M680X_INS_DECB = 125 , M680X_INS_DECD = 126 , M680X_INS_DECE = 127 , M680X_INS_DECF = 128 , M680X_INS_DECW = 129 , M680X_INS_DECX = 130 , # [doc = "< M6800/1/2/3"] M680X_INS_DES = 131 , # [doc = "< M6800/1/2/3"] M680X_INS_DEX = 132 , M680X_INS_DEY = 133 , M680X_INS_DIV = 134 , M680X_INS_DIVD = 135 , M680X_INS_DIVQ = 136 , M680X_INS_EDIV = 137 , M680X_INS_EDIVS = 138 , M680X_INS_EIM = 139 , M680X_INS_EMACS = 140 , M680X_INS_EMAXD = 141 , M680X_INS_EMAXM = 142 , M680X_INS_EMIND = 143 , M680X_INS_EMINM = 144 , M680X_INS_EMUL = 145 , M680X_INS_EMULS = 146 , M680X_INS_EOR = 147 , M680X_INS_EORA = 148 , M680X_INS_EORB = 149 , M680X_INS_EORD = 150 , M680X_INS_EORR = 151 , M680X_INS_ETBL = 152 , M680X_INS_EXG = 153 , M680X_INS_FDIV = 154 , M680X_INS_IBEQ = 155 , M680X_INS_IBNE = 156 , M680X_INS_IDIV = 157 , M680X_INS_IDIVS = 158 , M680X_INS_ILLGL = 159 , M680X_INS_INC = 160 , M680X_INS_INCA = 161 , M680X_INS_INCB = 162 , M680X_INS_INCD = 163 , M680X_INS_INCE = 164 , M680X_INS_INCF = 165 , M680X_INS_INCW = 166 , M680X_INS_INCX = 167 , # [doc = "< M6800/1/2/3"] M680X_INS_INS = 168 , # [doc = "< M6800/1/2/3"] M680X_INS_INX = 169 , M680X_INS_INY = 170 , M680X_INS_JMP = 171 , M680X_INS_JSR = 172 , # [doc = "< or LBHS"] M680X_INS_LBCC = 173 , # [doc = "< or LBLO"] M680X_INS_LBCS = 174 , M680X_INS_LBEQ = 175 , M680X_INS_LBGE = 176 , M680X_INS_LBGT = 177 , M680X_INS_LBHI = 178 , M680X_INS_LBLE = 179 , M680X_INS_LBLS = 180 , M680X_INS_LBLT = 181 , M680X_INS_LBMI = 182 , M680X_INS_LBNE = 183 , M680X_INS_LBPL = 184 , M680X_INS_LBRA = 185 , M680X_INS_LBRN = 186 , M680X_INS_LBSR = 187 , M680X_INS_LBVC = 188 , M680X_INS_LBVS = 189 , M680X_INS_LDA = 190 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAA = 191 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAB = 192 , M680X_INS_LDB = 193 , M680X_INS_LDBT = 194 , M680X_INS_LDD = 195 , M680X_INS_LDE = 196 , M680X_INS_LDF = 197 , M680X_INS_LDHX = 198 , M680X_INS_LDMD = 199 , M680X_INS_LDQ = 200 , M680X_INS_LDS = 201 , M680X_INS_LDU = 202 , M680X_INS_LDW = 203 , M680X_INS_LDX = 204 , M680X_INS_LDY = 205 , M680X_INS_LEAS = 206 , M680X_INS_LEAU = 207 , M680X_INS_LEAX = 208 , M680X_INS_LEAY = 209 , M680X_INS_LSL = 210 , M680X_INS_LSLA = 211 , M680X_INS_LSLB = 212 , M680X_INS_LSLD = 213 , M680X_INS_LSLX = 214 , M680X_INS_LSR = 215 , M680X_INS_LSRA = 216 , M680X_INS_LSRB = 217 , # [doc = "< or ASRD"] M680X_INS_LSRD = 218 , M680X_INS_LSRW = 219 , M680X_INS_LSRX = 220 , M680X_INS_MAXA = 221 , M680X_INS_MAXM = 222 , M680X_INS_MEM = 223 , M680X_INS_MINA = 224 , M680X_INS_MINM = 225 , M680X_INS_MOV = 226 , M680X_INS_MOVB = 227 , M680X_INS_MOVW = 228 , M680X_INS_MUL = 229 , M680X_INS_MULD = 230 , M680X_INS_NEG = 231 , M680X_INS_NEGA = 232 , M680X_INS_NEGB = 233 , M680X_INS_NEGD = 234 , M680X_INS_NEGX = 235 , M680X_INS_NOP = 236 , M680X_INS_NSA = 237 , M680X_INS_OIM = 238 , M680X_INS_ORA = 239 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAA = 240 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAB = 241 , M680X_INS_ORB = 242 , M680X_INS_ORCC = 243 , M680X_INS_ORD = 244 , M680X_INS_ORR = 245 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHA = 246 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHB = 247 , M680X_INS_PSHC = 248 , M680X_INS_PSHD = 249 , M680X_INS_PSHH = 250 , M680X_INS_PSHS = 251 , M680X_INS_PSHSW = 252 , M680X_INS_PSHU = 253 , M680X_INS_PSHUW = 254 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHX = 255 , M680X_INS_PSHY = 256 , # [doc = "< M6800/1/2/3"] M680X_INS_PULA = 257 , # [doc = "< M6800/1/2/3"] M680X_INS_PULB = 258 , M680X_INS_PULC = 259 , M680X_INS_PULD = 260 , M680X_INS_PULH = 261 , M680X_INS_PULS = 262 , M680X_INS_PULSW = 263 , M680X_INS_PULU = 264 , M680X_INS_PULUW = 265 , # [doc = "< M6800/1/2/3"] M680X_INS_PULX = 266 , M680X_INS_PULY = 267 , M680X_INS_REV = 268 , M680X_INS_REVW = 269 , M680X_INS_ROL = 270 , M680X_INS_ROLA = 271 , M680X_INS_ROLB = 272 , M680X_INS_ROLD = 273 , M680X_INS_ROLW = 274 , M680X_INS_ROLX = 275 , M680X_INS_ROR = 276 , M680X_INS_RORA = 277 , M680X_INS_RORB = 278 , M680X_INS_RORD = 279 , M680X_INS_RORW = 280 , M680X_INS_RORX = 281 , M680X_INS_RSP = 282 , M680X_INS_RTC = 283 , M680X_INS_RTI = 284 , M680X_INS_RTS = 285 , # [doc = "< M6800/1/2/3"] M680X_INS_SBA = 286 , M680X_INS_SBC = 287 , M680X_INS_SBCA = 288 , M680X_INS_SBCB = 289 , M680X_INS_SBCD = 290 , M680X_INS_SBCR = 291 , M680X_INS_SEC = 292 , M680X_INS_SEI = 293 , M680X_INS_SEV = 294 , M680X_INS_SEX = 295 , M680X_INS_SEXW = 296 , M680X_INS_SLP = 297 , M680X_INS_STA = 298 , # [doc = "< M6800/1/2/3"] M680X_INS_STAA = 299 , # [doc = "< M6800/1/2/3"] M680X_INS_STAB = 300 , M680X_INS_STB = 301 , M680X_INS_STBT = 302 , M680X_INS_STD = 303 , M680X_INS_STE = 304 , M680X_INS_STF = 305 , M680X_INS_STOP = 306 , M680X_INS_STHX = 307 , M680X_INS_STQ = 308 , M680X_INS_STS = 309 , M680X_INS_STU = 310 , M680X_INS_STW = 311 , M680X_INS_STX = 312 , M680X_INS_STY = 313 , M680X_INS_SUB = 314 , M680X_INS_SUBA = 315 , M680X_INS_SUBB = 316 , M680X_INS_SUBD = 317 , M680X_INS_SUBE = 318 , M680X_INS_SUBF = 319 , M680X_INS_SUBR = 320 , M680X_INS_SUBW = 321 , M680X_INS_SWI = 322 , M680X_INS_SWI2 = 323 , M680X_INS_SWI3 = 324 , M680X_INS_SYNC = 325 , # [doc = "< M6800/1/2/3"] M680X_INS_TAB = 326 , # [doc = "< M6800/1/2/3"] M680X_INS_TAP = 327 , M680X_INS_TAX = 328 , # [doc = "< M6800/1/2/3"] M680X_INS_TBA = 329 , M680X_INS_TBEQ = 330 , M680X_INS_TBL = 331 , M680X_INS_TBNE = 332 , M680X_INS_TEST = 333 , M680X_INS_TFM = 334 , M680X_INS_TFR = 335 , M680X_INS_TIM = 336 , # [doc = "< M6800/1/2/3"] M680X_INS_TPA = 337 , M680X_INS_TST = 338 , M680X_INS_TSTA = 339 , M680X_INS_TSTB = 340 , M680X_INS_TSTD = 341 , M680X_INS_TSTE = 342 , M680X_INS_TSTF = 343 , M680X_INS_TSTW = 344 , M680X_INS_TSTX = 345 , # [doc = "< M6800/1/2/3"] M680X_INS_TSX = 346 , M680X_INS_TSY = 347 , M680X_INS_TXA = 348 , # [doc = "< M6800/1/2/3"] M680X_INS_TXS = 349 , M680X_INS_TYS = 350 , # [doc = "< M6800/1/2/3"] M680X_INS_WAI = 351 , M680X_INS_WAIT = 352 , M680X_INS_WAV = 353 , M680X_INS_WAVR = 354 , # [doc = "< HD6301"] M680X_INS_XGDX = 355 , M680X_INS_XGDY = 356 , M680X_INS_ENDING = 357 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_evm { # [doc = "< number of items popped from the stack"] pub pop : :: std :: os :: raw :: c_uchar , # [doc = "< number of items pushed into the stack"] pub push : :: std :: os :: raw :: c_uchar , # [doc = "< gas fee for the instruction"] pub fee : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_evm"] [:: std :: mem :: size_of :: < cs_evm > () - 8usize] ; ["Alignment of cs_evm"] [:: std :: mem :: align_of :: < cs_evm > () - 4usize] ; ["Offset of field: cs_evm::pop"] [:: std :: mem :: offset_of ! (cs_evm , pop) - 0usize] ; ["Offset of field: cs_evm::push"] [:: std :: mem :: offset_of ! (cs_evm , push) - 1usize] ; ["Offset of field: cs_evm::fee"] [:: std :: mem :: offset_of ! (cs_evm , fee) - 4usize] ; } ; # [repr (u32)] # [doc = " EVM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn { EVM_INS_STOP = 0 , EVM_INS_ADD = 1 , EVM_INS_MUL = 2 , EVM_INS_SUB = 3 , EVM_INS_DIV = 4 , EVM_INS_SDIV = 5 , EVM_INS_MOD = 6 , EVM_INS_SMOD = 7 , EVM_INS_ADDMOD = 8 , EVM_INS_MULMOD = 9 , EVM_INS_EXP = 10 , EVM_INS_SIGNEXTEND = 11 , EVM_INS_LT = 16 , EVM_INS_GT = 17 , EVM_INS_SLT = 18 , EVM_INS_SGT = 19 , EVM_INS_EQ = 20 , EVM_INS_ISZERO = 21 , EVM_INS_AND = 22 , EVM_INS_OR = 23 , EVM_INS_XOR = 24 , EVM_INS_NOT = 25 , EVM_INS_BYTE = 26 , EVM_INS_SHA3 = 32 , EVM_INS_ADDRESS = 48 , EVM_INS_BALANCE = 49 , EVM_INS_ORIGIN = 50 , EVM_INS_CALLER = 51 , EVM_INS_CALLVALUE = 52 , EVM_INS_CALLDATALOAD = 53 , EVM_INS_CALLDATASIZE = 54 , EVM_INS_CALLDATACOPY = 55 , EVM_INS_CODESIZE = 56 , EVM_INS_CODECOPY = 57 , EVM_INS_GASPRICE = 58 , EVM_INS_EXTCODESIZE = 59 , EVM_INS_EXTCODECOPY = 60 , EVM_INS_RETURNDATASIZE = 61 , EVM_INS_RETURNDATACOPY = 62 , EVM_INS_BLOCKHASH = 64 , EVM_INS_COINBASE = 65 , EVM_INS_TIMESTAMP = 66 , EVM_INS_NUMBER = 67 , EVM_INS_DIFFICULTY = 68 , EVM_INS_GASLIMIT = 69 , EVM_INS_POP = 80 , EVM_INS_MLOAD = 81 , EVM_INS_MSTORE = 82 , EVM_INS_MSTORE8 = 83 , EVM_INS_SLOAD = 84 , EVM_INS_SSTORE = 85 , EVM_INS_JUMP = 86 , EVM_INS_JUMPI = 87 , EVM_INS_PC = 88 , EVM_INS_MSIZE = 89 , EVM_INS_GAS = 90 , EVM_INS_JUMPDEST = 91 , EVM_INS_PUSH1 = 96 , EVM_INS_PUSH2 = 97 , EVM_INS_PUSH3 = 98 , EVM_INS_PUSH4 = 99 , EVM_INS_PUSH5 = 100 , EVM_INS_PUSH6 = 101 , EVM_INS_PUSH7 = 102 , EVM_INS_PUSH8 = 103 , EVM_INS_PUSH9 = 104 , EVM_INS_PUSH10 = 105 , EVM_INS_PUSH11 = 106 , EVM_INS_PUSH12 = 107 , EVM_INS_PUSH13 = 108 , EVM_INS_PUSH14 = 109 , EVM_INS_PUSH15 = 110 , EVM_INS_PUSH16 = 111 , EVM_INS_PUSH17 = 112 , EVM_INS_PUSH18 = 113 , EVM_INS_PUSH19 = 114 , EVM_INS_PUSH20 = 115 , EVM_INS_PUSH21 = 116 , EVM_INS_PUSH22 = 117 , EVM_INS_PUSH23 = 118 , EVM_INS_PUSH24 = 119 , EVM_INS_PUSH25 = 120 , EVM_INS_PUSH26 = 121 , EVM_INS_PUSH27 = 122 , EVM_INS_PUSH28 = 123 , EVM_INS_PUSH29 = 124 , EVM_INS_PUSH30 = 125 , EVM_INS_PUSH31 = 126 , EVM_INS_PUSH32 = 127 , EVM_INS_DUP1 = 128 , EVM_INS_DUP2 = 129 , EVM_INS_DUP3 = 130 , EVM_INS_DUP4 = 131 , EVM_INS_DUP5 = 132 , EVM_INS_DUP6 = 133 , EVM_INS_DUP7 = 134 , EVM_INS_DUP8 = 135 , EVM_INS_DUP9 = 136 , EVM_INS_DUP10 = 137 , EVM_INS_DUP11 = 138 , EVM_INS_DUP12 = 139 , EVM_INS_DUP13 = 140 , EVM_INS_DUP14 = 141 , EVM_INS_DUP15 = 142 , EVM_INS_DUP16 = 143 , EVM_INS_SWAP1 = 144 , EVM_INS_SWAP2 = 145 , EVM_INS_SWAP3 = 146 , EVM_INS_SWAP4 = 147 , EVM_INS_SWAP5 = 148 , EVM_INS_SWAP6 = 149 , EVM_INS_SWAP7 = 150 , EVM_INS_SWAP8 = 151 , EVM_INS_SWAP9 = 152 , EVM_INS_SWAP10 = 153 , EVM_INS_SWAP11 = 154 , EVM_INS_SWAP12 = 155 , EVM_INS_SWAP13 = 156 , EVM_INS_SWAP14 = 157 , EVM_INS_SWAP15 = 158 , EVM_INS_SWAP16 = 159 , EVM_INS_LOG0 = 160 , EVM_INS_LOG1 = 161 , EVM_INS_LOG2 = 162 , EVM_INS_LOG3 = 163 , EVM_INS_LOG4 = 164 , EVM_INS_CREATE = 240 , EVM_INS_CALL = 241 , EVM_INS_CALLCODE = 242 , EVM_INS_RETURN = 243 , EVM_INS_DELEGATECALL = 244 , EVM_INS_CALLBLACKBOX = 245 , EVM_INS_STATICCALL = 250 , EVM_INS_REVERT = 253 , EVM_INS_SUICIDE = 255 , EVM_INS_INVALID = 512 , EVM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of EVM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn_group { # [doc = "< = CS_GRP_INVALID"] EVM_GRP_INVALID = 0 , # [doc = "< all jump instructions"] EVM_GRP_JUMP = 1 , # [doc = "< math instructions"] EVM_GRP_MATH = 8 , # [doc = "< instructions write to stack"] EVM_GRP_STACK_WRITE = 9 , # [doc = "< instructions read from stack"] EVM_GRP_STACK_READ = 10 , # [doc = "< instructions write to memory"] EVM_GRP_MEM_WRITE = 11 , # [doc = "< instructions read from memory"] EVM_GRP_MEM_READ = 12 , # [doc = "< instructions write to storage"] EVM_GRP_STORE_WRITE = 13 , # [doc = "< instructions read from storage"] EVM_GRP_STORE_READ = 14 , # [doc = "< instructions halt execution"] EVM_GRP_HALT = 15 , # [doc = "< <-- mark the end of the list of groups"] EVM_GRP_ENDING = 16 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_op_type { RISCV_OP_INVALID = 0 , RISCV_OP_REG = 1 , RISCV_OP_IMM = 2 , RISCV_OP_MEM = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct riscv_op_mem { pub base : :: std :: os :: raw :: c_uint , pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of riscv_op_mem"] [:: std :: mem :: size_of :: < riscv_op_mem > () - 16usize] ; ["Alignment of riscv_op_mem"] [:: std :: mem :: align_of :: < riscv_op_mem > () - 8usize] ; ["Offset of field: riscv_op_mem::base"] [:: std :: mem :: offset_of ! (riscv_op_mem , base) - 0usize] ; ["Offset of field: riscv_op_mem::disp"] [:: std :: mem :: offset_of ! (riscv_op_mem , disp) - 8usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv_op { pub type_ : riscv_op_type , pub __bindgen_anon_1 : cs_riscv_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_riscv_op__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub imm : i64 , pub mem : riscv_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_riscv_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_riscv_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op"] [:: std :: mem :: size_of :: < cs_riscv_op > () - 24usize] ; ["Alignment of cs_riscv_op"] [:: std :: mem :: align_of :: < cs_riscv_op > () - 8usize] ; ["Offset of field: cs_riscv_op::type_"] [:: std :: mem :: offset_of ! (cs_riscv_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv { pub need_effective_addr : bool , pub op_count : u8 , pub operands : [cs_riscv_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv"] [:: std :: mem :: size_of :: < cs_riscv > () - 200usize] ; ["Alignment of cs_riscv"] [:: std :: mem :: align_of :: < cs_riscv > () - 8usize] ; ["Offset of field: cs_riscv::need_effective_addr"] [:: std :: mem :: offset_of ! (cs_riscv , need_effective_addr) - 0usize] ; ["Offset of field: cs_riscv::op_count"] [:: std :: mem :: offset_of ! (cs_riscv , op_count) - 1usize] ; ["Offset of field: cs_riscv::operands"] [:: std :: mem :: offset_of ! (cs_riscv , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}" , self . need_effective_addr , self . op_count , self . operands) } } impl riscv_reg { pub const RISCV_REG_ZERO : riscv_reg = riscv_reg :: RISCV_REG_X0 ; } impl riscv_reg { pub const RISCV_REG_RA : riscv_reg = riscv_reg :: RISCV_REG_X1 ; } impl riscv_reg { pub const RISCV_REG_SP : riscv_reg = riscv_reg :: RISCV_REG_X2 ; } impl riscv_reg { pub const RISCV_REG_GP : riscv_reg = riscv_reg :: RISCV_REG_X3 ; } impl riscv_reg { pub const RISCV_REG_TP : riscv_reg = riscv_reg :: RISCV_REG_X4 ; } impl riscv_reg { pub const RISCV_REG_T0 : riscv_reg = riscv_reg :: RISCV_REG_X5 ; } impl riscv_reg { pub const RISCV_REG_T1 : riscv_reg = riscv_reg :: RISCV_REG_X6 ; } impl riscv_reg { pub const RISCV_REG_T2 : riscv_reg = riscv_reg :: RISCV_REG_X7 ; } impl riscv_reg { pub const RISCV_REG_S0 : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_FP : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_S1 : riscv_reg = riscv_reg :: RISCV_REG_X9 ; } impl riscv_reg { pub const RISCV_REG_A0 : riscv_reg = riscv_reg :: RISCV_REG_X10 ; } impl riscv_reg { pub const RISCV_REG_A1 : riscv_reg = riscv_reg :: RISCV_REG_X11 ; } impl riscv_reg { pub const RISCV_REG_A2 : riscv_reg = riscv_reg :: RISCV_REG_X12 ; } impl riscv_reg { pub const RISCV_REG_A3 : riscv_reg = riscv_reg :: RISCV_REG_X13 ; } impl riscv_reg { pub const RISCV_REG_A4 : riscv_reg = riscv_reg :: RISCV_REG_X14 ; } impl riscv_reg { pub const RISCV_REG_A5 : riscv_reg = riscv_reg :: RISCV_REG_X15 ; } impl riscv_reg { pub const RISCV_REG_A6 : riscv_reg = riscv_reg :: RISCV_REG_X16 ; } impl riscv_reg { pub const RISCV_REG_A7 : riscv_reg = riscv_reg :: RISCV_REG_X17 ; } impl riscv_reg { pub const RISCV_REG_S2 : riscv_reg = riscv_reg :: RISCV_REG_X18 ; } impl riscv_reg { pub const RISCV_REG_S3 : riscv_reg = riscv_reg :: RISCV_REG_X19 ; } impl riscv_reg { pub const RISCV_REG_S4 : riscv_reg = riscv_reg :: RISCV_REG_X20 ; } impl riscv_reg { pub const RISCV_REG_S5 : riscv_reg = riscv_reg :: RISCV_REG_X21 ; } impl riscv_reg { pub const RISCV_REG_S6 : riscv_reg = riscv_reg :: RISCV_REG_X22 ; } impl riscv_reg { pub const RISCV_REG_S7 : riscv_reg = riscv_reg :: RISCV_REG_X23 ; } impl riscv_reg { pub const RISCV_REG_S8 : riscv_reg = riscv_reg :: RISCV_REG_X24 ; } impl riscv_reg { pub const RISCV_REG_S9 : riscv_reg = riscv_reg :: RISCV_REG_X25 ; } impl riscv_reg { pub const RISCV_REG_S10 : riscv_reg = riscv_reg :: RISCV_REG_X26 ; } impl riscv_reg { pub const RISCV_REG_S11 : riscv_reg = riscv_reg :: RISCV_REG_X27 ; } impl riscv_reg { pub const RISCV_REG_T3 : riscv_reg = riscv_reg :: RISCV_REG_X28 ; } impl riscv_reg { pub const RISCV_REG_T4 : riscv_reg = riscv_reg :: RISCV_REG_X29 ; } impl riscv_reg { pub const RISCV_REG_T5 : riscv_reg = riscv_reg :: RISCV_REG_X30 ; } impl riscv_reg { pub const RISCV_REG_T6 : riscv_reg = riscv_reg :: RISCV_REG_X31 ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_reg { RISCV_REG_INVALID = 0 , RISCV_REG_X0 = 1 , RISCV_REG_X1 = 2 , RISCV_REG_X2 = 3 , RISCV_REG_X3 = 4 , RISCV_REG_X4 = 5 , RISCV_REG_X5 = 6 , RISCV_REG_X6 = 7 , RISCV_REG_X7 = 8 , RISCV_REG_X8 = 9 , RISCV_REG_X9 = 10 , RISCV_REG_X10 = 11 , RISCV_REG_X11 = 12 , RISCV_REG_X12 = 13 , RISCV_REG_X13 = 14 , RISCV_REG_X14 = 15 , RISCV_REG_X15 = 16 , RISCV_REG_X16 = 17 , RISCV_REG_X17 = 18 , RISCV_REG_X18 = 19 , RISCV_REG_X19 = 20 , RISCV_REG_X20 = 21 , RISCV_REG_X21 = 22 , RISCV_REG_X22 = 23 , RISCV_REG_X23 = 24 , RISCV_REG_X24 = 25 , RISCV_REG_X25 = 26 , RISCV_REG_X26 = 27 , RISCV_REG_X27 = 28 , RISCV_REG_X28 = 29 , RISCV_REG_X29 = 30 , RISCV_REG_X30 = 31 , RISCV_REG_X31 = 32 , RISCV_REG_F0_32 = 33 , RISCV_REG_F0_64 = 34 , RISCV_REG_F1_32 = 35 , RISCV_REG_F1_64 = 36 , RISCV_REG_F2_32 = 37 , RISCV_REG_F2_64 = 38 , RISCV_REG_F3_32 = 39 , RISCV_REG_F3_64 = 40 , RISCV_REG_F4_32 = 41 , RISCV_REG_F4_64 = 42 , RISCV_REG_F5_32 = 43 , RISCV_REG_F5_64 = 44 , RISCV_REG_F6_32 = 45 , RISCV_REG_F6_64 = 46 , RISCV_REG_F7_32 = 47 , RISCV_REG_F7_64 = 48 , RISCV_REG_F8_32 = 49 , RISCV_REG_F8_64 = 50 , RISCV_REG_F9_32 = 51 , RISCV_REG_F9_64 = 52 , RISCV_REG_F10_32 = 53 , RISCV_REG_F10_64 = 54 , RISCV_REG_F11_32 = 55 , RISCV_REG_F11_64 = 56 , RISCV_REG_F12_32 = 57 , RISCV_REG_F12_64 = 58 , RISCV_REG_F13_32 = 59 , RISCV_REG_F13_64 = 60 , RISCV_REG_F14_32 = 61 , RISCV_REG_F14_64 = 62 , RISCV_REG_F15_32 = 63 , RISCV_REG_F15_64 = 64 , RISCV_REG_F16_32 = 65 , RISCV_REG_F16_64 = 66 , RISCV_REG_F17_32 = 67 , RISCV_REG_F17_64 = 68 , RISCV_REG_F18_32 = 69 , RISCV_REG_F18_64 = 70 , RISCV_REG_F19_32 = 71 , RISCV_REG_F19_64 = 72 , RISCV_REG_F20_32 = 73 , RISCV_REG_F20_64 = 74 , RISCV_REG_F21_32 = 75 , RISCV_REG_F21_64 = 76 , RISCV_REG_F22_32 = 77 , RISCV_REG_F22_64 = 78 , RISCV_REG_F23_32 = 79 , RISCV_REG_F23_64 = 80 , RISCV_REG_F24_32 = 81 , RISCV_REG_F24_64 = 82 , RISCV_REG_F25_32 = 83 , RISCV_REG_F25_64 = 84 , RISCV_REG_F26_32 = 85 , RISCV_REG_F26_64 = 86 , RISCV_REG_F27_32 = 87 , RISCV_REG_F27_64 = 88 , RISCV_REG_F28_32 = 89 , RISCV_REG_F28_64 = 90 , RISCV_REG_F29_32 = 91 , RISCV_REG_F29_64 = 92 , RISCV_REG_F30_32 = 93 , RISCV_REG_F30_64 = 94 , RISCV_REG_F31_32 = 95 , RISCV_REG_F31_64 = 96 , RISCV_REG_ENDING = 97 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn { RISCV_INS_INVALID = 0 , RISCV_INS_ADD = 1 , RISCV_INS_ADDI = 2 , RISCV_INS_ADDIW = 3 , RISCV_INS_ADDW = 4 , RISCV_INS_AMOADD_D = 5 , RISCV_INS_AMOADD_D_AQ = 6 , RISCV_INS_AMOADD_D_AQ_RL = 7 , RISCV_INS_AMOADD_D_RL = 8 , RISCV_INS_AMOADD_W = 9 , RISCV_INS_AMOADD_W_AQ = 10 , RISCV_INS_AMOADD_W_AQ_RL = 11 , RISCV_INS_AMOADD_W_RL = 12 , RISCV_INS_AMOAND_D = 13 , RISCV_INS_AMOAND_D_AQ = 14 , RISCV_INS_AMOAND_D_AQ_RL = 15 , RISCV_INS_AMOAND_D_RL = 16 , RISCV_INS_AMOAND_W = 17 , RISCV_INS_AMOAND_W_AQ = 18 , RISCV_INS_AMOAND_W_AQ_RL = 19 , RISCV_INS_AMOAND_W_RL = 20 , RISCV_INS_AMOMAXU_D = 21 , RISCV_INS_AMOMAXU_D_AQ = 22 , RISCV_INS_AMOMAXU_D_AQ_RL = 23 , RISCV_INS_AMOMAXU_D_RL = 24 , RISCV_INS_AMOMAXU_W = 25 , RISCV_INS_AMOMAXU_W_AQ = 26 , RISCV_INS_AMOMAXU_W_AQ_RL = 27 , RISCV_INS_AMOMAXU_W_RL = 28 , RISCV_INS_AMOMAX_D = 29 , RISCV_INS_AMOMAX_D_AQ = 30 , RISCV_INS_AMOMAX_D_AQ_RL = 31 , RISCV_INS_AMOMAX_D_RL = 32 , RISCV_INS_AMOMAX_W = 33 , RISCV_INS_AMOMAX_W_AQ = 34 , RISCV_INS_AMOMAX_W_AQ_RL = 35 , RISCV_INS_AMOMAX_W_RL = 36 , RISCV_INS_AMOMINU_D = 37 , RISCV_INS_AMOMINU_D_AQ = 38 , RISCV_INS_AMOMINU_D_AQ_RL = 39 , RISCV_INS_AMOMINU_D_RL = 40 , RISCV_INS_AMOMINU_W = 41 , RISCV_INS_AMOMINU_W_AQ = 42 , RISCV_INS_AMOMINU_W_AQ_RL = 43 , RISCV_INS_AMOMINU_W_RL = 44 , RISCV_INS_AMOMIN_D = 45 , RISCV_INS_AMOMIN_D_AQ = 46 , RISCV_INS_AMOMIN_D_AQ_RL = 47 , RISCV_INS_AMOMIN_D_RL = 48 , RISCV_INS_AMOMIN_W = 49 , RISCV_INS_AMOMIN_W_AQ = 50 , RISCV_INS_AMOMIN_W_AQ_RL = 51 , RISCV_INS_AMOMIN_W_RL = 52 , RISCV_INS_AMOOR_D = 53 , RISCV_INS_AMOOR_D_AQ = 54 , RISCV_INS_AMOOR_D_AQ_RL = 55 , RISCV_INS_AMOOR_D_RL = 56 , RISCV_INS_AMOOR_W = 57 , RISCV_INS_AMOOR_W_AQ = 58 , RISCV_INS_AMOOR_W_AQ_RL = 59 , RISCV_INS_AMOOR_W_RL = 60 , RISCV_INS_AMOSWAP_D = 61 , RISCV_INS_AMOSWAP_D_AQ = 62 , RISCV_INS_AMOSWAP_D_AQ_RL = 63 , RISCV_INS_AMOSWAP_D_RL = 64 , RISCV_INS_AMOSWAP_W = 65 , RISCV_INS_AMOSWAP_W_AQ = 66 , RISCV_INS_AMOSWAP_W_AQ_RL = 67 , RISCV_INS_AMOSWAP_W_RL = 68 , RISCV_INS_AMOXOR_D = 69 , RISCV_INS_AMOXOR_D_AQ = 70 , RISCV_INS_AMOXOR_D_AQ_RL = 71 , RISCV_INS_AMOXOR_D_RL = 72 , RISCV_INS_AMOXOR_W = 73 , RISCV_INS_AMOXOR_W_AQ = 74 , RISCV_INS_AMOXOR_W_AQ_RL = 75 , RISCV_INS_AMOXOR_W_RL = 76 , RISCV_INS_AND = 77 , RISCV_INS_ANDI = 78 , RISCV_INS_AUIPC = 79 , RISCV_INS_BEQ = 80 , RISCV_INS_BGE = 81 , RISCV_INS_BGEU = 82 , RISCV_INS_BLT = 83 , RISCV_INS_BLTU = 84 , RISCV_INS_BNE = 85 , RISCV_INS_CSRRC = 86 , RISCV_INS_CSRRCI = 87 , RISCV_INS_CSRRS = 88 , RISCV_INS_CSRRSI = 89 , RISCV_INS_CSRRW = 90 , RISCV_INS_CSRRWI = 91 , RISCV_INS_C_ADD = 92 , RISCV_INS_C_ADDI = 93 , RISCV_INS_C_ADDI16SP = 94 , RISCV_INS_C_ADDI4SPN = 95 , RISCV_INS_C_ADDIW = 96 , RISCV_INS_C_ADDW = 97 , RISCV_INS_C_AND = 98 , RISCV_INS_C_ANDI = 99 , RISCV_INS_C_BEQZ = 100 , RISCV_INS_C_BNEZ = 101 , RISCV_INS_C_EBREAK = 102 , RISCV_INS_C_FLD = 103 , RISCV_INS_C_FLDSP = 104 , RISCV_INS_C_FLW = 105 , RISCV_INS_C_FLWSP = 106 , RISCV_INS_C_FSD = 107 , RISCV_INS_C_FSDSP = 108 , RISCV_INS_C_FSW = 109 , RISCV_INS_C_FSWSP = 110 , RISCV_INS_C_J = 111 , RISCV_INS_C_JAL = 112 , RISCV_INS_C_JALR = 113 , RISCV_INS_C_JR = 114 , RISCV_INS_C_LD = 115 , RISCV_INS_C_LDSP = 116 , RISCV_INS_C_LI = 117 , RISCV_INS_C_LUI = 118 , RISCV_INS_C_LW = 119 , RISCV_INS_C_LWSP = 120 , RISCV_INS_C_MV = 121 , RISCV_INS_C_NOP = 122 , RISCV_INS_C_OR = 123 , RISCV_INS_C_SD = 124 , RISCV_INS_C_SDSP = 125 , RISCV_INS_C_SLLI = 126 , RISCV_INS_C_SRAI = 127 , RISCV_INS_C_SRLI = 128 , RISCV_INS_C_SUB = 129 , RISCV_INS_C_SUBW = 130 , RISCV_INS_C_SW = 131 , RISCV_INS_C_SWSP = 132 , RISCV_INS_C_UNIMP = 133 , RISCV_INS_C_XOR = 134 , RISCV_INS_DIV = 135 , RISCV_INS_DIVU = 136 , RISCV_INS_DIVUW = 137 , RISCV_INS_DIVW = 138 , RISCV_INS_EBREAK = 139 , RISCV_INS_ECALL = 140 , RISCV_INS_FADD_D = 141 , RISCV_INS_FADD_S = 142 , RISCV_INS_FCLASS_D = 143 , RISCV_INS_FCLASS_S = 144 , RISCV_INS_FCVT_D_L = 145 , RISCV_INS_FCVT_D_LU = 146 , RISCV_INS_FCVT_D_S = 147 , RISCV_INS_FCVT_D_W = 148 , RISCV_INS_FCVT_D_WU = 149 , RISCV_INS_FCVT_LU_D = 150 , RISCV_INS_FCVT_LU_S = 151 , RISCV_INS_FCVT_L_D = 152 , RISCV_INS_FCVT_L_S = 153 , RISCV_INS_FCVT_S_D = 154 , RISCV_INS_FCVT_S_L = 155 , RISCV_INS_FCVT_S_LU = 156 , RISCV_INS_FCVT_S_W = 157 , RISCV_INS_FCVT_S_WU = 158 , RISCV_INS_FCVT_WU_D = 159 , RISCV_INS_FCVT_WU_S = 160 , RISCV_INS_FCVT_W_D = 161 , RISCV_INS_FCVT_W_S = 162 , RISCV_INS_FDIV_D = 163 , RISCV_INS_FDIV_S = 164 , RISCV_INS_FENCE = 165 , RISCV_INS_FENCE_I = 166 , RISCV_INS_FENCE_TSO = 167 , RISCV_INS_FEQ_D = 168 , RISCV_INS_FEQ_S = 169 , RISCV_INS_FLD = 170 , RISCV_INS_FLE_D = 171 , RISCV_INS_FLE_S = 172 , RISCV_INS_FLT_D = 173 , RISCV_INS_FLT_S = 174 , RISCV_INS_FLW = 175 , RISCV_INS_FMADD_D = 176 , RISCV_INS_FMADD_S = 177 , RISCV_INS_FMAX_D = 178 , RISCV_INS_FMAX_S = 179 , RISCV_INS_FMIN_D = 180 , RISCV_INS_FMIN_S = 181 , RISCV_INS_FMSUB_D = 182 , RISCV_INS_FMSUB_S = 183 , RISCV_INS_FMUL_D = 184 , RISCV_INS_FMUL_S = 185 , RISCV_INS_FMV_D_X = 186 , RISCV_INS_FMV_W_X = 187 , RISCV_INS_FMV_X_D = 188 , RISCV_INS_FMV_X_W = 189 , RISCV_INS_FNMADD_D = 190 , RISCV_INS_FNMADD_S = 191 , RISCV_INS_FNMSUB_D = 192 , RISCV_INS_FNMSUB_S = 193 , RISCV_INS_FSD = 194 , RISCV_INS_FSGNJN_D = 195 , RISCV_INS_FSGNJN_S = 196 , RISCV_INS_FSGNJX_D = 197 , RISCV_INS_FSGNJX_S = 198 , RISCV_INS_FSGNJ_D = 199 , RISCV_INS_FSGNJ_S = 200 , RISCV_INS_FSQRT_D = 201 , RISCV_INS_FSQRT_S = 202 , RISCV_INS_FSUB_D = 203 , RISCV_INS_FSUB_S = 204 , RISCV_INS_FSW = 205 , RISCV_INS_JAL = 206 , RISCV_INS_JALR = 207 , RISCV_INS_LB = 208 , RISCV_INS_LBU = 209 , RISCV_INS_LD = 210 , RISCV_INS_LH = 211 , RISCV_INS_LHU = 212 , RISCV_INS_LR_D = 213 , RISCV_INS_LR_D_AQ = 214 , RISCV_INS_LR_D_AQ_RL = 215 , RISCV_INS_LR_D_RL = 216 , RISCV_INS_LR_W = 217 , RISCV_INS_LR_W_AQ = 218 , RISCV_INS_LR_W_AQ_RL = 219 , RISCV_INS_LR_W_RL = 220 , RISCV_INS_LUI = 221 , RISCV_INS_LW = 222 , RISCV_INS_LWU = 223 , RISCV_INS_MRET = 224 , RISCV_INS_MUL = 225 , RISCV_INS_MULH = 226 , RISCV_INS_MULHSU = 227 , RISCV_INS_MULHU = 228 , RISCV_INS_MULW = 229 , RISCV_INS_OR = 230 , RISCV_INS_ORI = 231 , RISCV_INS_REM = 232 , RISCV_INS_REMU = 233 , RISCV_INS_REMUW = 234 , RISCV_INS_REMW = 235 , RISCV_INS_SB = 236 , RISCV_INS_SC_D = 237 , RISCV_INS_SC_D_AQ = 238 , RISCV_INS_SC_D_AQ_RL = 239 , RISCV_INS_SC_D_RL = 240 , RISCV_INS_SC_W = 241 , RISCV_INS_SC_W_AQ = 242 , RISCV_INS_SC_W_AQ_RL = 243 , RISCV_INS_SC_W_RL = 244 , RISCV_INS_SD = 245 , RISCV_INS_SFENCE_VMA = 246 , RISCV_INS_SH = 247 , RISCV_INS_SLL = 248 , RISCV_INS_SLLI = 249 , RISCV_INS_SLLIW = 250 , RISCV_INS_SLLW = 251 , RISCV_INS_SLT = 252 , RISCV_INS_SLTI = 253 , RISCV_INS_SLTIU = 254 , RISCV_INS_SLTU = 255 , RISCV_INS_SRA = 256 , RISCV_INS_SRAI = 257 , RISCV_INS_SRAIW = 258 , RISCV_INS_SRAW = 259 , RISCV_INS_SRET = 260 , RISCV_INS_SRL = 261 , RISCV_INS_SRLI = 262 , RISCV_INS_SRLIW = 263 , RISCV_INS_SRLW = 264 , RISCV_INS_SUB = 265 , RISCV_INS_SUBW = 266 , RISCV_INS_SW = 267 , RISCV_INS_UNIMP = 268 , RISCV_INS_URET = 269 , RISCV_INS_WFI = 270 , RISCV_INS_XOR = 271 , RISCV_INS_XORI = 272 , RISCV_INS_ENDING = 273 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn_group { # [doc = "< = CS_GRP_INVALID"] RISCV_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] RISCV_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] RISCV_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] RISCV_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] RISCV_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] RISCV_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] RISCV_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] RISCV_GRP_BRANCH_RELATIVE = 7 , RISCV_GRP_ISRV32 = 128 , RISCV_GRP_ISRV64 = 129 , RISCV_GRP_HASSTDEXTA = 130 , RISCV_GRP_HASSTDEXTC = 131 , RISCV_GRP_HASSTDEXTD = 132 , RISCV_GRP_HASSTDEXTF = 133 , RISCV_GRP_HASSTDEXTM = 134 , RISCV_GRP_ENDING = 135 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_op_type { WASM_OP_INVALID = 0 , WASM_OP_NONE = 1 , WASM_OP_INT7 = 2 , WASM_OP_VARUINT32 = 3 , WASM_OP_VARUINT64 = 4 , WASM_OP_UINT32 = 5 , WASM_OP_UINT64 = 6 , WASM_OP_IMM = 7 , WASM_OP_BRTABLE = 8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_wasm_brtable { pub length : u32 , pub address : u64 , pub default_target : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_brtable"] [:: std :: mem :: size_of :: < cs_wasm_brtable > () - 24usize] ; ["Alignment of cs_wasm_brtable"] [:: std :: mem :: align_of :: < cs_wasm_brtable > () - 8usize] ; ["Offset of field: cs_wasm_brtable::length"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , length) - 0usize] ; ["Offset of field: cs_wasm_brtable::address"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , address) - 8usize] ; ["Offset of field: cs_wasm_brtable::default_target"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , default_target) - 16usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm_op { pub type_ : wasm_op_type , pub size : u32 , pub __bindgen_anon_1 : cs_wasm_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_wasm_op__bindgen_ty_1 { pub int7 : i8 , pub varuint32 : u32 , pub varuint64 : u64 , pub uint32 : u32 , pub uint64 : u64 , pub immediate : [u32 ; 2usize] , pub brtable : cs_wasm_brtable , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_wasm_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_wasm_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::int7"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , int7) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::immediate"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , immediate) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::brtable"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , brtable) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op"] [:: std :: mem :: size_of :: < cs_wasm_op > () - 32usize] ; ["Alignment of cs_wasm_op"] [:: std :: mem :: align_of :: < cs_wasm_op > () - 8usize] ; ["Offset of field: cs_wasm_op::type_"] [:: std :: mem :: offset_of ! (cs_wasm_op , type_) - 0usize] ; ["Offset of field: cs_wasm_op::size"] [:: std :: mem :: offset_of ! (cs_wasm_op , size) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . size , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm { pub op_count : u8 , pub operands : [cs_wasm_op ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm"] [:: std :: mem :: size_of :: < cs_wasm > () - 72usize] ; ["Alignment of cs_wasm"] [:: std :: mem :: align_of :: < cs_wasm > () - 8usize] ; ["Offset of field: cs_wasm::op_count"] [:: std :: mem :: offset_of ! (cs_wasm , op_count) - 0usize] ; ["Offset of field: cs_wasm::operands"] [:: std :: mem :: offset_of ! (cs_wasm , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " WASM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn { WASM_INS_UNREACHABLE = 0 , WASM_INS_NOP = 1 , WASM_INS_BLOCK = 2 , WASM_INS_LOOP = 3 , WASM_INS_IF = 4 , WASM_INS_ELSE = 5 , WASM_INS_END = 11 , WASM_INS_BR = 12 , WASM_INS_BR_IF = 13 , WASM_INS_BR_TABLE = 14 , WASM_INS_RETURN = 15 , WASM_INS_CALL = 16 , WASM_INS_CALL_INDIRECT = 17 , WASM_INS_DROP = 26 , WASM_INS_SELECT = 27 , WASM_INS_GET_LOCAL = 32 , WASM_INS_SET_LOCAL = 33 , WASM_INS_TEE_LOCAL = 34 , WASM_INS_GET_GLOBAL = 35 , WASM_INS_SET_GLOBAL = 36 , WASM_INS_I32_LOAD = 40 , WASM_INS_I64_LOAD = 41 , WASM_INS_F32_LOAD = 42 , WASM_INS_F64_LOAD = 43 , WASM_INS_I32_LOAD8_S = 44 , WASM_INS_I32_LOAD8_U = 45 , WASM_INS_I32_LOAD16_S = 46 , WASM_INS_I32_LOAD16_U = 47 , WASM_INS_I64_LOAD8_S = 48 , WASM_INS_I64_LOAD8_U = 49 , WASM_INS_I64_LOAD16_S = 50 , WASM_INS_I64_LOAD16_U = 51 , WASM_INS_I64_LOAD32_S = 52 , WASM_INS_I64_LOAD32_U = 53 , WASM_INS_I32_STORE = 54 , WASM_INS_I64_STORE = 55 , WASM_INS_F32_STORE = 56 , WASM_INS_F64_STORE = 57 , WASM_INS_I32_STORE8 = 58 , WASM_INS_I32_STORE16 = 59 , WASM_INS_I64_STORE8 = 60 , WASM_INS_I64_STORE16 = 61 , WASM_INS_I64_STORE32 = 62 , WASM_INS_CURRENT_MEMORY = 63 , WASM_INS_GROW_MEMORY = 64 , WASM_INS_I32_CONST = 65 , WASM_INS_I64_CONST = 66 , WASM_INS_F32_CONST = 67 , WASM_INS_F64_CONST = 68 , WASM_INS_I32_EQZ = 69 , WASM_INS_I32_EQ = 70 , WASM_INS_I32_NE = 71 , WASM_INS_I32_LT_S = 72 , WASM_INS_I32_LT_U = 73 , WASM_INS_I32_GT_S = 74 , WASM_INS_I32_GT_U = 75 , WASM_INS_I32_LE_S = 76 , WASM_INS_I32_LE_U = 77 , WASM_INS_I32_GE_S = 78 , WASM_INS_I32_GE_U = 79 , WASM_INS_I64_EQZ = 80 , WASM_INS_I64_EQ = 81 , WASM_INS_I64_NE = 82 , WASM_INS_I64_LT_S = 83 , WASM_INS_I64_LT_U = 84 , WASN_INS_I64_GT_S = 85 , WASM_INS_I64_GT_U = 86 , WASM_INS_I64_LE_S = 87 , WASM_INS_I64_LE_U = 88 , WASM_INS_I64_GE_S = 89 , WASM_INS_I64_GE_U = 90 , WASM_INS_F32_EQ = 91 , WASM_INS_F32_NE = 92 , WASM_INS_F32_LT = 93 , WASM_INS_F32_GT = 94 , WASM_INS_F32_LE = 95 , WASM_INS_F32_GE = 96 , WASM_INS_F64_EQ = 97 , WASM_INS_F64_NE = 98 , WASM_INS_F64_LT = 99 , WASM_INS_F64_GT = 100 , WASM_INS_F64_LE = 101 , WASM_INS_F64_GE = 102 , WASM_INS_I32_CLZ = 103 , WASM_INS_I32_CTZ = 104 , WASM_INS_I32_POPCNT = 105 , WASM_INS_I32_ADD = 106 , WASM_INS_I32_SUB = 107 , WASM_INS_I32_MUL = 108 , WASM_INS_I32_DIV_S = 109 , WASM_INS_I32_DIV_U = 110 , WASM_INS_I32_REM_S = 111 , WASM_INS_I32_REM_U = 112 , WASM_INS_I32_AND = 113 , WASM_INS_I32_OR = 114 , WASM_INS_I32_XOR = 115 , WASM_INS_I32_SHL = 116 , WASM_INS_I32_SHR_S = 117 , WASM_INS_I32_SHR_U = 118 , WASM_INS_I32_ROTL = 119 , WASM_INS_I32_ROTR = 120 , WASM_INS_I64_CLZ = 121 , WASM_INS_I64_CTZ = 122 , WASM_INS_I64_POPCNT = 123 , WASM_INS_I64_ADD = 124 , WASM_INS_I64_SUB = 125 , WASM_INS_I64_MUL = 126 , WASM_INS_I64_DIV_S = 127 , WASM_INS_I64_DIV_U = 128 , WASM_INS_I64_REM_S = 129 , WASM_INS_I64_REM_U = 130 , WASM_INS_I64_AND = 131 , WASM_INS_I64_OR = 132 , WASM_INS_I64_XOR = 133 , WASM_INS_I64_SHL = 134 , WASM_INS_I64_SHR_S = 135 , WASM_INS_I64_SHR_U = 136 , WASM_INS_I64_ROTL = 137 , WASM_INS_I64_ROTR = 138 , WASM_INS_F32_ABS = 139 , WASM_INS_F32_NEG = 140 , WASM_INS_F32_CEIL = 141 , WASM_INS_F32_FLOOR = 142 , WASM_INS_F32_TRUNC = 143 , WASM_INS_F32_NEAREST = 144 , WASM_INS_F32_SQRT = 145 , WASM_INS_F32_ADD = 146 , WASM_INS_F32_SUB = 147 , WASM_INS_F32_MUL = 148 , WASM_INS_F32_DIV = 149 , WASM_INS_F32_MIN = 150 , WASM_INS_F32_MAX = 151 , WASM_INS_F32_COPYSIGN = 152 , WASM_INS_F64_ABS = 153 , WASM_INS_F64_NEG = 154 , WASM_INS_F64_CEIL = 155 , WASM_INS_F64_FLOOR = 156 , WASM_INS_F64_TRUNC = 157 , WASM_INS_F64_NEAREST = 158 , WASM_INS_F64_SQRT = 159 , WASM_INS_F64_ADD = 160 , WASM_INS_F64_SUB = 161 , WASM_INS_F64_MUL = 162 , WASM_INS_F64_DIV = 163 , WASM_INS_F64_MIN = 164 , WASM_INS_F64_MAX = 165 , WASM_INS_F64_COPYSIGN = 166 , WASM_INS_I32_WARP_I64 = 167 , WASP_INS_I32_TRUNC_S_F32 = 168 , WASM_INS_I32_TRUNC_U_F32 = 169 , WASM_INS_I32_TRUNC_S_F64 = 170 , WASM_INS_I32_TRUNC_U_F64 = 171 , WASM_INS_I64_EXTEND_S_I32 = 172 , WASM_INS_I64_EXTEND_U_I32 = 173 , WASM_INS_I64_TRUNC_S_F32 = 174 , WASM_INS_I64_TRUNC_U_F32 = 175 , WASM_INS_I64_TRUNC_S_F64 = 176 , WASM_INS_I64_TRUNC_U_F64 = 177 , WASM_INS_F32_CONVERT_S_I32 = 178 , WASM_INS_F32_CONVERT_U_I32 = 179 , WASM_INS_F32_CONVERT_S_I64 = 180 , WASM_INS_F32_CONVERT_U_I64 = 181 , WASM_INS_F32_DEMOTE_F64 = 182 , WASM_INS_F64_CONVERT_S_I32 = 183 , WASM_INS_F64_CONVERT_U_I32 = 184 , WASM_INS_F64_CONVERT_S_I64 = 185 , WASM_INS_F64_CONVERT_U_I64 = 186 , WASM_INS_F64_PROMOTE_F32 = 187 , WASM_INS_I32_REINTERPRET_F32 = 188 , WASM_INS_I64_REINTERPRET_F64 = 189 , WASM_INS_F32_REINTERPRET_I32 = 190 , WASM_INS_F64_REINTERPRET_I64 = 191 , WASM_INS_INVALID = 512 , WASM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of WASM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn_group { # [doc = "< = CS_GRP_INVALID"] WASM_GRP_INVALID = 0 , WASM_GRP_NUMBERIC = 8 , WASM_GRP_PARAMETRIC = 9 , WASM_GRP_VARIABLE = 10 , WASM_GRP_MEMORY = 11 , WASM_GRP_CONTROL = 12 , # [doc = "< <-- mark the end of the list of groups"] WASM_GRP_ENDING = 13 , } # [repr (u32)] # [doc = " MOS65XX registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_reg { MOS65XX_REG_INVALID = 0 , # [doc = "< accumulator"] MOS65XX_REG_ACC = 1 , # [doc = "< X index register"] MOS65XX_REG_X = 2 , # [doc = "< Y index register"] MOS65XX_REG_Y = 3 , # [doc = "< status register"] MOS65XX_REG_P = 4 , # [doc = "< stack pointer register"] MOS65XX_REG_SP = 5 , # [doc = "< direct page register"] MOS65XX_REG_DP = 6 , # [doc = "< data bank register"] MOS65XX_REG_B = 7 , # [doc = "< program bank register"] MOS65XX_REG_K = 8 , MOS65XX_REG_ENDING = 9 , } # [repr (u32)] # [doc = " MOS65XX Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_address_mode { # [doc = "< No address mode."] MOS65XX_AM_NONE = 0 , # [doc = "< implied addressing (no addressing mode)"] MOS65XX_AM_IMP = 1 , # [doc = "< accumulator addressing"] MOS65XX_AM_ACC = 2 , # [doc = "< 8/16 Bit immediate value"] MOS65XX_AM_IMM = 3 , # [doc = "< relative addressing used by branches"] MOS65XX_AM_REL = 4 , # [doc = "< interrupt addressing"] MOS65XX_AM_INT = 5 , # [doc = "< memory block addressing"] MOS65XX_AM_BLOCK = 6 , # [doc = "< zeropage addressing"] MOS65XX_AM_ZP = 7 , # [doc = "< indexed zeropage addressing by the X index register"] MOS65XX_AM_ZP_X = 8 , # [doc = "< indexed zeropage addressing by the Y index register"] MOS65XX_AM_ZP_Y = 9 , # [doc = "< zero page address, branch relative address"] MOS65XX_AM_ZP_REL = 10 , # [doc = "< indirect zeropage addressing"] MOS65XX_AM_ZP_IND = 11 , # [doc = "< indexed zeropage indirect addressing by the X index register"] MOS65XX_AM_ZP_X_IND = 12 , # [doc = "< indirect zeropage indexed addressing by the Y index register"] MOS65XX_AM_ZP_IND_Y = 13 , # [doc = "< zeropage indirect long addressing"] MOS65XX_AM_ZP_IND_LONG = 14 , # [doc = "< zeropage indirect long addressing indexed by Y register"] MOS65XX_AM_ZP_IND_LONG_Y = 15 , # [doc = "< absolute addressing"] MOS65XX_AM_ABS = 16 , # [doc = "< indexed absolute addressing by the X index register"] MOS65XX_AM_ABS_X = 17 , # [doc = "< indexed absolute addressing by the Y index register"] MOS65XX_AM_ABS_Y = 18 , # [doc = "< absolute indirect addressing"] MOS65XX_AM_ABS_IND = 19 , # [doc = "< indexed absolute indirect addressing by the X index register"] MOS65XX_AM_ABS_X_IND = 20 , # [doc = "< absolute indirect long addressing"] MOS65XX_AM_ABS_IND_LONG = 21 , # [doc = "< absolute long address mode"] MOS65XX_AM_ABS_LONG = 22 , # [doc = "< absolute long address mode, indexed by X register"] MOS65XX_AM_ABS_LONG_X = 23 , # [doc = "< stack relative addressing"] MOS65XX_AM_SR = 24 , # [doc = "< indirect stack relative addressing indexed by the Y index register"] MOS65XX_AM_SR_IND_Y = 25 , } # [repr (u32)] # [doc = " MOS65XX instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_insn { MOS65XX_INS_INVALID = 0 , MOS65XX_INS_ADC = 1 , MOS65XX_INS_AND = 2 , MOS65XX_INS_ASL = 3 , MOS65XX_INS_BBR = 4 , MOS65XX_INS_BBS = 5 , MOS65XX_INS_BCC = 6 , MOS65XX_INS_BCS = 7 , MOS65XX_INS_BEQ = 8 , MOS65XX_INS_BIT = 9 , MOS65XX_INS_BMI = 10 , MOS65XX_INS_BNE = 11 , MOS65XX_INS_BPL = 12 , MOS65XX_INS_BRA = 13 , MOS65XX_INS_BRK = 14 , MOS65XX_INS_BRL = 15 , MOS65XX_INS_BVC = 16 , MOS65XX_INS_BVS = 17 , MOS65XX_INS_CLC = 18 , MOS65XX_INS_CLD = 19 , MOS65XX_INS_CLI = 20 , MOS65XX_INS_CLV = 21 , MOS65XX_INS_CMP = 22 , MOS65XX_INS_COP = 23 , MOS65XX_INS_CPX = 24 , MOS65XX_INS_CPY = 25 , MOS65XX_INS_DEC = 26 , MOS65XX_INS_DEX = 27 , MOS65XX_INS_DEY = 28 , MOS65XX_INS_EOR = 29 , MOS65XX_INS_INC = 30 , MOS65XX_INS_INX = 31 , MOS65XX_INS_INY = 32 , MOS65XX_INS_JML = 33 , MOS65XX_INS_JMP = 34 , MOS65XX_INS_JSL = 35 , MOS65XX_INS_JSR = 36 , MOS65XX_INS_LDA = 37 , MOS65XX_INS_LDX = 38 , MOS65XX_INS_LDY = 39 , MOS65XX_INS_LSR = 40 , MOS65XX_INS_MVN = 41 , MOS65XX_INS_MVP = 42 , MOS65XX_INS_NOP = 43 , MOS65XX_INS_ORA = 44 , MOS65XX_INS_PEA = 45 , MOS65XX_INS_PEI = 46 , MOS65XX_INS_PER = 47 , MOS65XX_INS_PHA = 48 , MOS65XX_INS_PHB = 49 , MOS65XX_INS_PHD = 50 , MOS65XX_INS_PHK = 51 , MOS65XX_INS_PHP = 52 , MOS65XX_INS_PHX = 53 , MOS65XX_INS_PHY = 54 , MOS65XX_INS_PLA = 55 , MOS65XX_INS_PLB = 56 , MOS65XX_INS_PLD = 57 , MOS65XX_INS_PLP = 58 , MOS65XX_INS_PLX = 59 , MOS65XX_INS_PLY = 60 , MOS65XX_INS_REP = 61 , MOS65XX_INS_RMB = 62 , MOS65XX_INS_ROL = 63 , MOS65XX_INS_ROR = 64 , MOS65XX_INS_RTI = 65 , MOS65XX_INS_RTL = 66 , MOS65XX_INS_RTS = 67 , MOS65XX_INS_SBC = 68 , MOS65XX_INS_SEC = 69 , MOS65XX_INS_SED = 70 , MOS65XX_INS_SEI = 71 , MOS65XX_INS_SEP = 72 , MOS65XX_INS_SMB = 73 , MOS65XX_INS_STA = 74 , MOS65XX_INS_STP = 75 , MOS65XX_INS_STX = 76 , MOS65XX_INS_STY = 77 , MOS65XX_INS_STZ = 78 , MOS65XX_INS_TAX = 79 , MOS65XX_INS_TAY = 80 , MOS65XX_INS_TCD = 81 , MOS65XX_INS_TCS = 82 , MOS65XX_INS_TDC = 83 , MOS65XX_INS_TRB = 84 , MOS65XX_INS_TSB = 85 , MOS65XX_INS_TSC = 86 , MOS65XX_INS_TSX = 87 , MOS65XX_INS_TXA = 88 , MOS65XX_INS_TXS = 89 , MOS65XX_INS_TXY = 90 , MOS65XX_INS_TYA = 91 , MOS65XX_INS_TYX = 92 , MOS65XX_INS_WAI = 93 , MOS65XX_INS_WDM = 94 , MOS65XX_INS_XBA = 95 , MOS65XX_INS_XCE = 96 , MOS65XX_INS_ENDING = 97 , } # [repr (u32)] # [doc = " Group of MOS65XX instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_group_type { # [doc = "< CS_GRP_INVALID"] MOS65XX_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MOS65XX_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MOS65XX_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MOS65XX_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MOS65XX_GRP_BRANCH_RELATIVE = 6 , MOS65XX_GRP_ENDING = 7 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MOS65XX_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MOS65XX_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MOS65XX_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MOS65XX_OP_MEM = 3 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx_op { # [doc = "< operand type"] pub type_ : mos65xx_op_type , pub __bindgen_anon_1 : cs_mos65xx_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mos65xx_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : mos65xx_reg , # [doc = "< immediate value for IMM operand"] pub imm : u16 , # [doc = "< address for MEM operand"] pub mem : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Alignment of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op"] [:: std :: mem :: size_of :: < cs_mos65xx_op > () - 8usize] ; ["Alignment of cs_mos65xx_op"] [:: std :: mem :: align_of :: < cs_mos65xx_op > () - 4usize] ; ["Offset of field: cs_mos65xx_op::type_"] [:: std :: mem :: offset_of ! (cs_mos65xx_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The MOS65XX address mode and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx { pub am : mos65xx_address_mode , pub modifies_flags : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mos65xx_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx"] [:: std :: mem :: size_of :: < cs_mos65xx > () - 32usize] ; ["Alignment of cs_mos65xx"] [:: std :: mem :: align_of :: < cs_mos65xx > () - 4usize] ; ["Offset of field: cs_mos65xx::am"] [:: std :: mem :: offset_of ! (cs_mos65xx , am) - 0usize] ; ["Offset of field: cs_mos65xx::modifies_flags"] [:: std :: mem :: offset_of ! (cs_mos65xx , modifies_flags) - 4usize] ; ["Offset of field: cs_mos65xx::op_count"] [:: std :: mem :: offset_of ! (cs_mos65xx , op_count) - 5usize] ; ["Offset of field: cs_mos65xx::operands"] [:: std :: mem :: offset_of ! (cs_mos65xx , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . am , self . modifies_flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_op_type { BPF_OP_INVALID = 0 , BPF_OP_REG = 1 , BPF_OP_IMM = 2 , BPF_OP_OFF = 3 , BPF_OP_MEM = 4 , # [doc = "< M[k] in cBPF"] BPF_OP_MMEM = 5 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] BPF_OP_MSH = 6 , # [doc = "< cBPF's extension (not eBPF)"] BPF_OP_EXT = 7 , } # [repr (u32)] # [doc = " BPF registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_reg { BPF_REG_INVALID = 0 , BPF_REG_A = 1 , BPF_REG_X = 2 , BPF_REG_R0 = 3 , BPF_REG_R1 = 4 , BPF_REG_R2 = 5 , BPF_REG_R3 = 6 , BPF_REG_R4 = 7 , BPF_REG_R5 = 8 , BPF_REG_R6 = 9 , BPF_REG_R7 = 10 , BPF_REG_R8 = 11 , BPF_REG_R9 = 12 , BPF_REG_R10 = 13 , BPF_REG_ENDING = 14 , } # [doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct bpf_op_mem { # [doc = "< base register"] pub base : bpf_reg , # [doc = "< offset value"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of bpf_op_mem"] [:: std :: mem :: size_of :: < bpf_op_mem > () - 8usize] ; ["Alignment of bpf_op_mem"] [:: std :: mem :: align_of :: < bpf_op_mem > () - 4usize] ; ["Offset of field: bpf_op_mem::base"] [:: std :: mem :: offset_of ! (bpf_op_mem , base) - 0usize] ; ["Offset of field: bpf_op_mem::disp"] [:: std :: mem :: offset_of ! (bpf_op_mem , disp) - 4usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_ext_type { BPF_EXT_INVALID = 0 , BPF_EXT_LEN = 1 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf_op { pub type_ : bpf_op_type , pub __bindgen_anon_1 : cs_bpf_op__bindgen_ty_1 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_bpf_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : u8 , # [doc = "< immediate value IMM operand"] pub imm : u64 , # [doc = "< offset value, used in jump & call"] pub off : u32 , # [doc = "< base/disp value for MEM operand"] pub mem : bpf_op_mem , # [doc = "< M[k] in cBPF"] pub mmem : u32 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] pub msh : u32 , # [doc = "< cBPF's extension (not eBPF)"] pub ext : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::off"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , off) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mmem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mmem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::msh"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , msh) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , ext) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op"] [:: std :: mem :: size_of :: < cs_bpf_op > () - 24usize] ; ["Alignment of cs_bpf_op"] [:: std :: mem :: align_of :: < cs_bpf_op > () - 8usize] ; ["Offset of field: cs_bpf_op::type_"] [:: std :: mem :: offset_of ! (cs_bpf_op , type_) - 0usize] ; ["Offset of field: cs_bpf_op::access"] [:: std :: mem :: offset_of ! (cs_bpf_op , access) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf { pub op_count : u8 , pub operands : [cs_bpf_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf"] [:: std :: mem :: size_of :: < cs_bpf > () - 104usize] ; ["Alignment of cs_bpf"] [:: std :: mem :: align_of :: < cs_bpf > () - 8usize] ; ["Offset of field: cs_bpf::op_count"] [:: std :: mem :: offset_of ! (cs_bpf , op_count) - 0usize] ; ["Offset of field: cs_bpf::operands"] [:: std :: mem :: offset_of ! (cs_bpf , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } impl bpf_insn { pub const BPF_INS_LD : bpf_insn = bpf_insn :: BPF_INS_LDW ; } impl bpf_insn { pub const BPF_INS_LDX : bpf_insn = bpf_insn :: BPF_INS_LDXW ; } impl bpf_insn { pub const BPF_INS_ST : bpf_insn = bpf_insn :: BPF_INS_STW ; } impl bpf_insn { pub const BPF_INS_STX : bpf_insn = bpf_insn :: BPF_INS_STXW ; } # [repr (u32)] # [doc = " BPF instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn { BPF_INS_INVALID = 0 , BPF_INS_ADD = 1 , BPF_INS_SUB = 2 , BPF_INS_MUL = 3 , BPF_INS_DIV = 4 , BPF_INS_OR = 5 , BPF_INS_AND = 6 , BPF_INS_LSH = 7 , BPF_INS_RSH = 8 , BPF_INS_NEG = 9 , BPF_INS_MOD = 10 , BPF_INS_XOR = 11 , # [doc = "< eBPF only"] BPF_INS_MOV = 12 , # [doc = "< eBPF only"] BPF_INS_ARSH = 13 , BPF_INS_ADD64 = 14 , BPF_INS_SUB64 = 15 , BPF_INS_MUL64 = 16 , BPF_INS_DIV64 = 17 , BPF_INS_OR64 = 18 , BPF_INS_AND64 = 19 , BPF_INS_LSH64 = 20 , BPF_INS_RSH64 = 21 , BPF_INS_NEG64 = 22 , BPF_INS_MOD64 = 23 , BPF_INS_XOR64 = 24 , BPF_INS_MOV64 = 25 , BPF_INS_ARSH64 = 26 , BPF_INS_LE16 = 27 , BPF_INS_LE32 = 28 , BPF_INS_LE64 = 29 , BPF_INS_BE16 = 30 , BPF_INS_BE32 = 31 , BPF_INS_BE64 = 32 , # [doc = "< eBPF only"] BPF_INS_LDW = 33 , BPF_INS_LDH = 34 , BPF_INS_LDB = 35 , # [doc = "< eBPF only: load 64-bit imm"] BPF_INS_LDDW = 36 , # [doc = "< eBPF only"] BPF_INS_LDXW = 37 , # [doc = "< eBPF only"] BPF_INS_LDXH = 38 , # [doc = "< eBPF only"] BPF_INS_LDXB = 39 , # [doc = "< eBPF only"] BPF_INS_LDXDW = 40 , # [doc = "< eBPF only"] BPF_INS_STW = 41 , # [doc = "< eBPF only"] BPF_INS_STH = 42 , # [doc = "< eBPF only"] BPF_INS_STB = 43 , # [doc = "< eBPF only"] BPF_INS_STDW = 44 , # [doc = "< eBPF only"] BPF_INS_STXW = 45 , # [doc = "< eBPF only"] BPF_INS_STXH = 46 , # [doc = "< eBPF only"] BPF_INS_STXB = 47 , # [doc = "< eBPF only"] BPF_INS_STXDW = 48 , # [doc = "< eBPF only"] BPF_INS_XADDW = 49 , # [doc = "< eBPF only"] BPF_INS_XADDDW = 50 , BPF_INS_JMP = 51 , BPF_INS_JEQ = 52 , BPF_INS_JGT = 53 , BPF_INS_JGE = 54 , BPF_INS_JSET = 55 , # [doc = "< eBPF only"] BPF_INS_JNE = 56 , # [doc = "< eBPF only"] BPF_INS_JSGT = 57 , # [doc = "< eBPF only"] BPF_INS_JSGE = 58 , # [doc = "< eBPF only"] BPF_INS_CALL = 59 , # [doc = "< eBPF only"] BPF_INS_CALLX = 60 , # [doc = "< eBPF only"] BPF_INS_EXIT = 61 , # [doc = "< eBPF only"] BPF_INS_JLT = 62 , # [doc = "< eBPF only"] BPF_INS_JLE = 63 , # [doc = "< eBPF only"] BPF_INS_JSLT = 64 , # [doc = "< eBPF only"] BPF_INS_JSLE = 65 , BPF_INS_RET = 66 , BPF_INS_TAX = 67 , BPF_INS_TXA = 68 , BPF_INS_ENDING = 69 , } # [repr (u32)] # [doc = " Group of BPF instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn_group { # [doc = "< = CS_GRP_INVALID"] BPF_GRP_INVALID = 0 , BPF_GRP_LOAD = 1 , BPF_GRP_STORE = 2 , BPF_GRP_ALU = 3 , BPF_GRP_JUMP = 4 , # [doc = "< eBPF only"] BPF_GRP_CALL = 5 , BPF_GRP_RETURN = 6 , # [doc = "< cBPF only"] BPF_GRP_MISC = 7 , BPF_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " SH registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_reg { SH_REG_INVALID = 0 , SH_REG_R0 = 1 , SH_REG_R1 = 2 , SH_REG_R2 = 3 , SH_REG_R3 = 4 , SH_REG_R4 = 5 , SH_REG_R5 = 6 , SH_REG_R6 = 7 , SH_REG_R7 = 8 , SH_REG_R8 = 9 , SH_REG_R9 = 10 , SH_REG_R10 = 11 , SH_REG_R11 = 12 , SH_REG_R12 = 13 , SH_REG_R13 = 14 , SH_REG_R14 = 15 , SH_REG_R15 = 16 , SH_REG_R0_BANK = 17 , SH_REG_R1_BANK = 18 , SH_REG_R2_BANK = 19 , SH_REG_R3_BANK = 20 , SH_REG_R4_BANK = 21 , SH_REG_R5_BANK = 22 , SH_REG_R6_BANK = 23 , SH_REG_R7_BANK = 24 , SH_REG_FR0 = 25 , SH_REG_FR1 = 26 , SH_REG_FR2 = 27 , SH_REG_FR3 = 28 , SH_REG_FR4 = 29 , SH_REG_FR5 = 30 , SH_REG_FR6 = 31 , SH_REG_FR7 = 32 , SH_REG_FR8 = 33 , SH_REG_FR9 = 34 , SH_REG_FR10 = 35 , SH_REG_FR11 = 36 , SH_REG_FR12 = 37 , SH_REG_FR13 = 38 , SH_REG_FR14 = 39 , SH_REG_FR15 = 40 , SH_REG_DR0 = 41 , SH_REG_DR2 = 42 , SH_REG_DR4 = 43 , SH_REG_DR6 = 44 , SH_REG_DR8 = 45 , SH_REG_DR10 = 46 , SH_REG_DR12 = 47 , SH_REG_DR14 = 48 , SH_REG_XD0 = 49 , SH_REG_XD2 = 50 , SH_REG_XD4 = 51 , SH_REG_XD6 = 52 , SH_REG_XD8 = 53 , SH_REG_XD10 = 54 , SH_REG_XD12 = 55 , SH_REG_XD14 = 56 , SH_REG_XF0 = 57 , SH_REG_XF1 = 58 , SH_REG_XF2 = 59 , SH_REG_XF3 = 60 , SH_REG_XF4 = 61 , SH_REG_XF5 = 62 , SH_REG_XF6 = 63 , SH_REG_XF7 = 64 , SH_REG_XF8 = 65 , SH_REG_XF9 = 66 , SH_REG_XF10 = 67 , SH_REG_XF11 = 68 , SH_REG_XF12 = 69 , SH_REG_XF13 = 70 , SH_REG_XF14 = 71 , SH_REG_XF15 = 72 , SH_REG_FV0 = 73 , SH_REG_FV4 = 74 , SH_REG_FV8 = 75 , SH_REG_FV12 = 76 , SH_REG_XMATRX = 77 , SH_REG_PC = 78 , SH_REG_PR = 79 , SH_REG_MACH = 80 , SH_REG_MACL = 81 , SH_REG_SR = 82 , SH_REG_GBR = 83 , SH_REG_SSR = 84 , SH_REG_SPC = 85 , SH_REG_SGR = 86 , SH_REG_DBR = 87 , SH_REG_VBR = 88 , SH_REG_TBR = 89 , SH_REG_RS = 90 , SH_REG_RE = 91 , SH_REG_MOD = 92 , SH_REG_FPUL = 93 , SH_REG_FPSCR = 94 , SH_REG_DSP_X0 = 95 , SH_REG_DSP_X1 = 96 , SH_REG_DSP_Y0 = 97 , SH_REG_DSP_Y1 = 98 , SH_REG_DSP_A0 = 99 , SH_REG_DSP_A1 = 100 , SH_REG_DSP_A0G = 101 , SH_REG_DSP_A1G = 102 , SH_REG_DSP_M0 = 103 , SH_REG_DSP_M1 = 104 , SH_REG_DSP_DSR = 105 , SH_REG_DSP_RSV0 = 106 , SH_REG_DSP_RSV1 = 107 , SH_REG_DSP_RSV2 = 108 , SH_REG_DSP_RSV3 = 109 , SH_REG_DSP_RSV4 = 110 , SH_REG_DSP_RSV5 = 111 , SH_REG_DSP_RSV6 = 112 , SH_REG_DSP_RSV7 = 113 , SH_REG_DSP_RSV8 = 114 , SH_REG_DSP_RSV9 = 115 , SH_REG_DSP_RSVA = 116 , SH_REG_DSP_RSVB = 117 , SH_REG_DSP_RSVC = 118 , SH_REG_DSP_RSVD = 119 , SH_REG_DSP_RSVE = 120 , SH_REG_DSP_RSVF = 121 , SH_REG_ENDING = 122 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SH_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SH_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SH_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SH_OP_MEM = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_mem_type { SH_OP_MEM_INVALID = 0 , # [doc = " <= Invalid"] SH_OP_MEM_REG_IND = 1 , # [doc = " <= Register indirect"] SH_OP_MEM_REG_POST = 2 , # [doc = " <= Register post increment"] SH_OP_MEM_REG_PRE = 3 , # [doc = " <= Register pre decrement"] SH_OP_MEM_REG_DISP = 4 , # [doc = " <= displacement"] SH_OP_MEM_REG_R0 = 5 , # [doc = " <= R0 indexed"] SH_OP_MEM_GBR_DISP = 6 , # [doc = " <= GBR based displacement"] SH_OP_MEM_GBR_R0 = 7 , # [doc = " <= GBR based R0 indexed"] SH_OP_MEM_PCR = 8 , # [doc = " <= PC relative"] SH_OP_MEM_TBR_DISP = 9 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_mem { pub address : sh_op_mem_type , # [doc = " <= memory address"] pub reg : sh_reg , # [doc = " <= base register"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_mem"] [:: std :: mem :: size_of :: < sh_op_mem > () - 12usize] ; ["Alignment of sh_op_mem"] [:: std :: mem :: align_of :: < sh_op_mem > () - 4usize] ; ["Offset of field: sh_op_mem::address"] [:: std :: mem :: offset_of ! (sh_op_mem , address) - 0usize] ; ["Offset of field: sh_op_mem::reg"] [:: std :: mem :: offset_of ! (sh_op_mem , reg) - 4usize] ; ["Offset of field: sh_op_mem::disp"] [:: std :: mem :: offset_of ! (sh_op_mem , disp) - 8usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn_type { SH_INS_DSP_INVALID = 0 , SH_INS_DSP_DOUBLE = 1 , SH_INS_DSP_SINGLE = 2 , SH_INS_DSP_PARALLEL = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn { SH_INS_DSP_NOP = 1 , SH_INS_DSP_MOV = 2 , SH_INS_DSP_PSHL = 3 , SH_INS_DSP_PSHA = 4 , SH_INS_DSP_PMULS = 5 , SH_INS_DSP_PCLR_PMULS = 6 , SH_INS_DSP_PSUB_PMULS = 7 , SH_INS_DSP_PADD_PMULS = 8 , SH_INS_DSP_PSUBC = 9 , SH_INS_DSP_PADDC = 10 , SH_INS_DSP_PCMP = 11 , SH_INS_DSP_PABS = 12 , SH_INS_DSP_PRND = 13 , SH_INS_DSP_PSUB = 14 , SH_INS_DSP_PSUBr = 15 , SH_INS_DSP_PADD = 16 , SH_INS_DSP_PAND = 17 , SH_INS_DSP_PXOR = 18 , SH_INS_DSP_POR = 19 , SH_INS_DSP_PDEC = 20 , SH_INS_DSP_PINC = 21 , SH_INS_DSP_PCLR = 22 , SH_INS_DSP_PDMSB = 23 , SH_INS_DSP_PNEG = 24 , SH_INS_DSP_PCOPY = 25 , SH_INS_DSP_PSTS = 26 , SH_INS_DSP_PLDS = 27 , SH_INS_DSP_PSWAP = 28 , SH_INS_DSP_PWAD = 29 , SH_INS_DSP_PWSB = 30 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_operand { SH_OP_DSP_INVALID = 0 , SH_OP_DSP_REG_PRE = 1 , SH_OP_DSP_REG_IND = 2 , SH_OP_DSP_REG_POST = 3 , SH_OP_DSP_REG_INDEX = 4 , SH_OP_DSP_REG = 5 , SH_OP_DSP_IMM = 6 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_cc { SH_DSP_CC_INVALID = 0 , SH_DSP_CC_NONE = 1 , SH_DSP_CC_DCT = 2 , SH_DSP_CC_DCF = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_dsp { pub insn : sh_dsp_insn , pub operand : [sh_dsp_operand ; 2usize] , pub r : [sh_reg ; 6usize] , pub cc : sh_dsp_cc , pub imm : u8 , pub size : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_dsp"] [:: std :: mem :: size_of :: < sh_op_dsp > () - 48usize] ; ["Alignment of sh_op_dsp"] [:: std :: mem :: align_of :: < sh_op_dsp > () - 4usize] ; ["Offset of field: sh_op_dsp::insn"] [:: std :: mem :: offset_of ! (sh_op_dsp , insn) - 0usize] ; ["Offset of field: sh_op_dsp::operand"] [:: std :: mem :: offset_of ! (sh_op_dsp , operand) - 4usize] ; ["Offset of field: sh_op_dsp::r"] [:: std :: mem :: offset_of ! (sh_op_dsp , r) - 12usize] ; ["Offset of field: sh_op_dsp::cc"] [:: std :: mem :: offset_of ! (sh_op_dsp , cc) - 36usize] ; ["Offset of field: sh_op_dsp::imm"] [:: std :: mem :: offset_of ! (sh_op_dsp , imm) - 40usize] ; ["Offset of field: sh_op_dsp::size"] [:: std :: mem :: offset_of ! (sh_op_dsp , size) - 44usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh_op { pub type_ : sh_op_type , pub __bindgen_anon_1 : cs_sh_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sh_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< register value for REG operand"] pub reg : sh_reg , # [doc = "< data when operand is targeting memory"] pub mem : sh_op_mem , # [doc = "< dsp instruction"] pub dsp : sh_op_dsp , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sh_op__bindgen_ty_1 > () - 48usize] ; ["Alignment of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sh_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::dsp"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , dsp) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op"] [:: std :: mem :: size_of :: < cs_sh_op > () - 56usize] ; ["Alignment of cs_sh_op"] [:: std :: mem :: align_of :: < cs_sh_op > () - 8usize] ; ["Offset of field: cs_sh_op::type_"] [:: std :: mem :: offset_of ! (cs_sh_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (u32)] # [doc = " SH instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn { SH_INS_INVALID = 0 , SH_INS_ADD_r = 1 , SH_INS_ADD = 2 , SH_INS_ADDC = 3 , SH_INS_ADDV = 4 , SH_INS_AND = 5 , SH_INS_BAND = 6 , SH_INS_BANDNOT = 7 , SH_INS_BCLR = 8 , SH_INS_BF = 9 , SH_INS_BF_S = 10 , SH_INS_BLD = 11 , SH_INS_BLDNOT = 12 , SH_INS_BOR = 13 , SH_INS_BORNOT = 14 , SH_INS_BRA = 15 , SH_INS_BRAF = 16 , SH_INS_BSET = 17 , SH_INS_BSR = 18 , SH_INS_BSRF = 19 , SH_INS_BST = 20 , SH_INS_BT = 21 , SH_INS_BT_S = 22 , SH_INS_BXOR = 23 , SH_INS_CLIPS = 24 , SH_INS_CLIPU = 25 , SH_INS_CLRDMXY = 26 , SH_INS_CLRMAC = 27 , SH_INS_CLRS = 28 , SH_INS_CLRT = 29 , SH_INS_CMP_EQ = 30 , SH_INS_CMP_GE = 31 , SH_INS_CMP_GT = 32 , SH_INS_CMP_HI = 33 , SH_INS_CMP_HS = 34 , SH_INS_CMP_PL = 35 , SH_INS_CMP_PZ = 36 , SH_INS_CMP_STR = 37 , SH_INS_DIV0S = 38 , SH_INS_DIV0U = 39 , SH_INS_DIV1 = 40 , SH_INS_DIVS = 41 , SH_INS_DIVU = 42 , SH_INS_DMULS_L = 43 , SH_INS_DMULU_L = 44 , SH_INS_DT = 45 , SH_INS_EXTS_B = 46 , SH_INS_EXTS_W = 47 , SH_INS_EXTU_B = 48 , SH_INS_EXTU_W = 49 , SH_INS_FABS = 50 , SH_INS_FADD = 51 , SH_INS_FCMP_EQ = 52 , SH_INS_FCMP_GT = 53 , SH_INS_FCNVDS = 54 , SH_INS_FCNVSD = 55 , SH_INS_FDIV = 56 , SH_INS_FIPR = 57 , SH_INS_FLDI0 = 58 , SH_INS_FLDI1 = 59 , SH_INS_FLDS = 60 , SH_INS_FLOAT = 61 , SH_INS_FMAC = 62 , SH_INS_FMOV = 63 , SH_INS_FMUL = 64 , SH_INS_FNEG = 65 , SH_INS_FPCHG = 66 , SH_INS_FRCHG = 67 , SH_INS_FSCA = 68 , SH_INS_FSCHG = 69 , SH_INS_FSQRT = 70 , SH_INS_FSRRA = 71 , SH_INS_FSTS = 72 , SH_INS_FSUB = 73 , SH_INS_FTRC = 74 , SH_INS_FTRV = 75 , SH_INS_ICBI = 76 , SH_INS_JMP = 77 , SH_INS_JSR = 78 , SH_INS_JSR_N = 79 , SH_INS_LDBANK = 80 , SH_INS_LDC = 81 , SH_INS_LDRC = 82 , SH_INS_LDRE = 83 , SH_INS_LDRS = 84 , SH_INS_LDS = 85 , SH_INS_LDTLB = 86 , SH_INS_MAC_L = 87 , SH_INS_MAC_W = 88 , SH_INS_MOV = 89 , SH_INS_MOVA = 90 , SH_INS_MOVCA = 91 , SH_INS_MOVCO = 92 , SH_INS_MOVI20 = 93 , SH_INS_MOVI20S = 94 , SH_INS_MOVLI = 95 , SH_INS_MOVML = 96 , SH_INS_MOVMU = 97 , SH_INS_MOVRT = 98 , SH_INS_MOVT = 99 , SH_INS_MOVU = 100 , SH_INS_MOVUA = 101 , SH_INS_MUL_L = 102 , SH_INS_MULR = 103 , SH_INS_MULS_W = 104 , SH_INS_MULU_W = 105 , SH_INS_NEG = 106 , SH_INS_NEGC = 107 , SH_INS_NOP = 108 , SH_INS_NOT = 109 , SH_INS_NOTT = 110 , SH_INS_OCBI = 111 , SH_INS_OCBP = 112 , SH_INS_OCBWB = 113 , SH_INS_OR = 114 , SH_INS_PREF = 115 , SH_INS_PREFI = 116 , SH_INS_RESBANK = 117 , SH_INS_ROTCL = 118 , SH_INS_ROTCR = 119 , SH_INS_ROTL = 120 , SH_INS_ROTR = 121 , SH_INS_RTE = 122 , SH_INS_RTS = 123 , SH_INS_RTS_N = 124 , SH_INS_RTV_N = 125 , SH_INS_SETDMX = 126 , SH_INS_SETDMY = 127 , SH_INS_SETRC = 128 , SH_INS_SETS = 129 , SH_INS_SETT = 130 , SH_INS_SHAD = 131 , SH_INS_SHAL = 132 , SH_INS_SHAR = 133 , SH_INS_SHLD = 134 , SH_INS_SHLL = 135 , SH_INS_SHLL16 = 136 , SH_INS_SHLL2 = 137 , SH_INS_SHLL8 = 138 , SH_INS_SHLR = 139 , SH_INS_SHLR16 = 140 , SH_INS_SHLR2 = 141 , SH_INS_SHLR8 = 142 , SH_INS_SLEEP = 143 , SH_INS_STBANK = 144 , SH_INS_STC = 145 , SH_INS_STS = 146 , SH_INS_SUB = 147 , SH_INS_SUBC = 148 , SH_INS_SUBV = 149 , SH_INS_SWAP_B = 150 , SH_INS_SWAP_W = 151 , SH_INS_SYNCO = 152 , SH_INS_TAS = 153 , SH_INS_TRAPA = 154 , SH_INS_TST = 155 , SH_INS_XOR = 156 , SH_INS_XTRCT = 157 , SH_INS_DSP = 158 , SH_INS_ENDING = 159 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh { pub insn : sh_insn , pub size : u8 , pub op_count : u8 , pub operands : [cs_sh_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh"] [:: std :: mem :: size_of :: < cs_sh > () - 176usize] ; ["Alignment of cs_sh"] [:: std :: mem :: align_of :: < cs_sh > () - 8usize] ; ["Offset of field: cs_sh::insn"] [:: std :: mem :: offset_of ! (cs_sh , insn) - 0usize] ; ["Offset of field: cs_sh::size"] [:: std :: mem :: offset_of ! (cs_sh , size) - 4usize] ; ["Offset of field: cs_sh::op_count"] [:: std :: mem :: offset_of ! (cs_sh , op_count) - 5usize] ; ["Offset of field: cs_sh::operands"] [:: std :: mem :: offset_of ! (cs_sh , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sh { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh {{ insn: {:?}, size: {:?}, op_count: {:?}, operands: {:?} }}" , self . insn , self . size , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Group of SH instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn_group { # [doc = "< CS_GRUP_INVALID"] SH_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SH_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] SH_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] SH_GRP_INT = 3 , # [doc = "< = CS_GRP_RET"] SH_GRP_RET = 4 , # [doc = "< = CS_GRP_IRET"] SH_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] SH_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] SH_GRP_BRANCH_RELATIVE = 7 , SH_GRP_SH1 = 8 , SH_GRP_SH2 = 9 , SH_GRP_SH2E = 10 , SH_GRP_SH2DSP = 11 , SH_GRP_SH2A = 12 , SH_GRP_SH2AFPU = 13 , SH_GRP_SH3 = 14 , SH_GRP_SH3DSP = 15 , SH_GRP_SH4 = 16 , SH_GRP_SH4A = 17 , SH_GRP_ENDING = 18 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_op_type { # [doc = "< CS_OP_INVALID (Uninitialized)."] TRICORE_OP_INVALID = 0 , # [doc = "< CS_OP_REG (Register operand)."] TRICORE_OP_REG = 1 , # [doc = "< CS_OP_IMM (Immediate operand)."] TRICORE_OP_IMM = 2 , # [doc = "< CS_OP_MEM (Memory operand)."] TRICORE_OP_MEM = 3 , } # [doc = " Instruction's operand referring to memory\n This is associated with TRICORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tricore_op_mem { # [doc = "< base register"] pub base : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tricore_op_mem"] [:: std :: mem :: size_of :: < tricore_op_mem > () - 8usize] ; ["Alignment of tricore_op_mem"] [:: std :: mem :: align_of :: < tricore_op_mem > () - 4usize] ; ["Offset of field: tricore_op_mem::base"] [:: std :: mem :: offset_of ! (tricore_op_mem , base) - 0usize] ; ["Offset of field: tricore_op_mem::disp"] [:: std :: mem :: offset_of ! (tricore_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore_op { # [doc = "< operand type"] pub type_ : tricore_op_type , pub __bindgen_anon_1 : cs_tricore_op__bindgen_ty_1 , # [doc = "< How is this operand accessed? (READ, WRITE or READ|WRITE)"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tricore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tricore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tricore_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tricore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op"] [:: std :: mem :: size_of :: < cs_tricore_op > () - 16usize] ; ["Alignment of cs_tricore_op"] [:: std :: mem :: align_of :: < cs_tricore_op > () - 4usize] ; ["Offset of field: cs_tricore_op::type_"] [:: std :: mem :: offset_of ! (cs_tricore_op , type_) - 0usize] ; ["Offset of field: cs_tricore_op::access"] [:: std :: mem :: offset_of ! (cs_tricore_op , access) - 12usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore { # [doc = "< number of operands of this instruction."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tricore_op ; 8usize] , # [doc = "< whether the flags register is updated."] pub update_flags : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore"] [:: std :: mem :: size_of :: < cs_tricore > () - 136usize] ; ["Alignment of cs_tricore"] [:: std :: mem :: align_of :: < cs_tricore > () - 4usize] ; ["Offset of field: cs_tricore::op_count"] [:: std :: mem :: offset_of ! (cs_tricore , op_count) - 0usize] ; ["Offset of field: cs_tricore::operands"] [:: std :: mem :: offset_of ! (cs_tricore , operands) - 4usize] ; ["Offset of field: cs_tricore::update_flags"] [:: std :: mem :: offset_of ! (cs_tricore , update_flags) - 132usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore {{ op_count: {:?}, operands: {:?}, update_flags: {:?} }}" , self . op_count , self . operands , self . update_flags) } } # [repr (u32)] # [doc = " TriCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_reg { TRICORE_REG_INVALID = 0 , TRICORE_REG_FCX = 1 , TRICORE_REG_PC = 2 , TRICORE_REG_PCXI = 3 , TRICORE_REG_PSW = 4 , TRICORE_REG_A0 = 5 , TRICORE_REG_A1 = 6 , TRICORE_REG_A2 = 7 , TRICORE_REG_A3 = 8 , TRICORE_REG_A4 = 9 , TRICORE_REG_A5 = 10 , TRICORE_REG_A6 = 11 , TRICORE_REG_A7 = 12 , TRICORE_REG_A8 = 13 , TRICORE_REG_A9 = 14 , TRICORE_REG_A10 = 15 , TRICORE_REG_A11 = 16 , TRICORE_REG_A12 = 17 , TRICORE_REG_A13 = 18 , TRICORE_REG_A14 = 19 , TRICORE_REG_A15 = 20 , TRICORE_REG_D0 = 21 , TRICORE_REG_D1 = 22 , TRICORE_REG_D2 = 23 , TRICORE_REG_D3 = 24 , TRICORE_REG_D4 = 25 , TRICORE_REG_D5 = 26 , TRICORE_REG_D6 = 27 , TRICORE_REG_D7 = 28 , TRICORE_REG_D8 = 29 , TRICORE_REG_D9 = 30 , TRICORE_REG_D10 = 31 , TRICORE_REG_D11 = 32 , TRICORE_REG_D12 = 33 , TRICORE_REG_D13 = 34 , TRICORE_REG_D14 = 35 , TRICORE_REG_D15 = 36 , TRICORE_REG_E0 = 37 , TRICORE_REG_E2 = 38 , TRICORE_REG_E4 = 39 , TRICORE_REG_E6 = 40 , TRICORE_REG_E8 = 41 , TRICORE_REG_E10 = 42 , TRICORE_REG_E12 = 43 , TRICORE_REG_E14 = 44 , TRICORE_REG_P0 = 45 , TRICORE_REG_P2 = 46 , TRICORE_REG_P4 = 47 , TRICORE_REG_P6 = 48 , TRICORE_REG_P8 = 49 , TRICORE_REG_P10 = 50 , TRICORE_REG_P12 = 51 , TRICORE_REG_P14 = 52 , TRICORE_REG_A0_A1 = 53 , TRICORE_REG_A2_A3 = 54 , TRICORE_REG_A4_A5 = 55 , TRICORE_REG_A6_A7 = 56 , TRICORE_REG_A8_A9 = 57 , TRICORE_REG_A10_A11 = 58 , TRICORE_REG_A12_A13 = 59 , TRICORE_REG_A14_A15 = 60 , TRICORE_REG_ENDING = 61 , } # [repr (u32)] # [doc = " TriCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn { TRICORE_INS_INVALID = 0 , TRICORE_INS_XOR_T = 1 , TRICORE_INS_ABSDIFS_B = 2 , TRICORE_INS_ABSDIFS_H = 3 , TRICORE_INS_ABSDIFS = 4 , TRICORE_INS_ABSDIF_B = 5 , TRICORE_INS_ABSDIF_H = 6 , TRICORE_INS_ABSDIF = 7 , TRICORE_INS_ABSS_B = 8 , TRICORE_INS_ABSS_H = 9 , TRICORE_INS_ABSS = 10 , TRICORE_INS_ABS_B = 11 , TRICORE_INS_ABS_H = 12 , TRICORE_INS_ABS = 13 , TRICORE_INS_ADDC = 14 , TRICORE_INS_ADDIH_A = 15 , TRICORE_INS_ADDIH = 16 , TRICORE_INS_ADDI = 17 , TRICORE_INS_ADDSC_AT = 18 , TRICORE_INS_ADDSC_A = 19 , TRICORE_INS_ADDS_BU = 20 , TRICORE_INS_ADDS_B = 21 , TRICORE_INS_ADDS_H = 22 , TRICORE_INS_ADDS_HU = 23 , TRICORE_INS_ADDS_U = 24 , TRICORE_INS_ADDS = 25 , TRICORE_INS_ADDX = 26 , TRICORE_INS_ADD_A = 27 , TRICORE_INS_ADD_B = 28 , TRICORE_INS_ADD_F = 29 , TRICORE_INS_ADD_H = 30 , TRICORE_INS_ADD = 31 , TRICORE_INS_ANDN_T = 32 , TRICORE_INS_ANDN = 33 , TRICORE_INS_AND_ANDN_T = 34 , TRICORE_INS_AND_AND_T = 35 , TRICORE_INS_AND_EQ = 36 , TRICORE_INS_AND_GE_U = 37 , TRICORE_INS_AND_GE = 38 , TRICORE_INS_AND_LT_U = 39 , TRICORE_INS_AND_LT = 40 , TRICORE_INS_AND_NE = 41 , TRICORE_INS_AND_NOR_T = 42 , TRICORE_INS_AND_OR_T = 43 , TRICORE_INS_AND_T = 44 , TRICORE_INS_AND = 45 , TRICORE_INS_BISR = 46 , TRICORE_INS_BMERGE = 47 , TRICORE_INS_BSPLIT = 48 , TRICORE_INS_CACHEA_I = 49 , TRICORE_INS_CACHEA_WI = 50 , TRICORE_INS_CACHEA_W = 51 , TRICORE_INS_CACHEI_I = 52 , TRICORE_INS_CACHEI_WI = 53 , TRICORE_INS_CACHEI_W = 54 , TRICORE_INS_CADDN_A = 55 , TRICORE_INS_CADDN = 56 , TRICORE_INS_CADD_A = 57 , TRICORE_INS_CADD = 58 , TRICORE_INS_CALLA = 59 , TRICORE_INS_CALLI = 60 , TRICORE_INS_CALL = 61 , TRICORE_INS_CLO_B = 62 , TRICORE_INS_CLO_H = 63 , TRICORE_INS_CLO = 64 , TRICORE_INS_CLS_B = 65 , TRICORE_INS_CLS_H = 66 , TRICORE_INS_CLS = 67 , TRICORE_INS_CLZ_B = 68 , TRICORE_INS_CLZ_H = 69 , TRICORE_INS_CLZ = 70 , TRICORE_INS_CMOVN = 71 , TRICORE_INS_CMOV = 72 , TRICORE_INS_CMPSWAP_W = 73 , TRICORE_INS_CMP_F = 74 , TRICORE_INS_CRC32B_W = 75 , TRICORE_INS_CRC32L_W = 76 , TRICORE_INS_CRC32_B = 77 , TRICORE_INS_CRCN = 78 , TRICORE_INS_CSUBN_A = 79 , TRICORE_INS_CSUBN = 80 , TRICORE_INS_CSUB_A = 81 , TRICORE_INS_CSUB = 82 , TRICORE_INS_DEBUG = 83 , TRICORE_INS_DEXTR = 84 , TRICORE_INS_DIFSC_A = 85 , TRICORE_INS_DISABLE = 86 , TRICORE_INS_DIV_F = 87 , TRICORE_INS_DIV_U = 88 , TRICORE_INS_DIV = 89 , TRICORE_INS_DSYNC = 90 , TRICORE_INS_DVADJ = 91 , TRICORE_INS_DVINIT_BU = 92 , TRICORE_INS_DVINIT_B = 93 , TRICORE_INS_DVINIT_HU = 94 , TRICORE_INS_DVINIT_H = 95 , TRICORE_INS_DVINIT_U = 96 , TRICORE_INS_DVINIT = 97 , TRICORE_INS_DVSTEP_U = 98 , TRICORE_INS_DVSTEP = 99 , TRICORE_INS_ENABLE = 100 , TRICORE_INS_EQANY_B = 101 , TRICORE_INS_EQANY_H = 102 , TRICORE_INS_EQZ_A = 103 , TRICORE_INS_EQ_A = 104 , TRICORE_INS_EQ_B = 105 , TRICORE_INS_EQ_H = 106 , TRICORE_INS_EQ_W = 107 , TRICORE_INS_EQ = 108 , TRICORE_INS_EXTR_U = 109 , TRICORE_INS_EXTR = 110 , TRICORE_INS_FCALLA = 111 , TRICORE_INS_FCALLI = 112 , TRICORE_INS_FCALL = 113 , TRICORE_INS_FRET = 114 , TRICORE_INS_FTOHP = 115 , TRICORE_INS_FTOIZ = 116 , TRICORE_INS_FTOI = 117 , TRICORE_INS_FTOQ31Z = 118 , TRICORE_INS_FTOQ31 = 119 , TRICORE_INS_FTOUZ = 120 , TRICORE_INS_FTOU = 121 , TRICORE_INS_GE_A = 122 , TRICORE_INS_GE_U = 123 , TRICORE_INS_GE = 124 , TRICORE_INS_HPTOF = 125 , TRICORE_INS_IMASK = 126 , TRICORE_INS_INSERT = 127 , TRICORE_INS_INSN_T = 128 , TRICORE_INS_INS_T = 129 , TRICORE_INS_ISYNC = 130 , TRICORE_INS_ITOF = 131 , TRICORE_INS_IXMAX_U = 132 , TRICORE_INS_IXMAX = 133 , TRICORE_INS_IXMIN_U = 134 , TRICORE_INS_IXMIN = 135 , TRICORE_INS_JA = 136 , TRICORE_INS_JEQ_A = 137 , TRICORE_INS_JEQ = 138 , TRICORE_INS_JGEZ = 139 , TRICORE_INS_JGE_U = 140 , TRICORE_INS_JGE = 141 , TRICORE_INS_JGTZ = 142 , TRICORE_INS_JI = 143 , TRICORE_INS_JLA = 144 , TRICORE_INS_JLEZ = 145 , TRICORE_INS_JLI = 146 , TRICORE_INS_JLTZ = 147 , TRICORE_INS_JLT_U = 148 , TRICORE_INS_JLT = 149 , TRICORE_INS_JL = 150 , TRICORE_INS_JNED = 151 , TRICORE_INS_JNEI = 152 , TRICORE_INS_JNE_A = 153 , TRICORE_INS_JNE = 154 , TRICORE_INS_JNZ_A = 155 , TRICORE_INS_JNZ_T = 156 , TRICORE_INS_JNZ = 157 , TRICORE_INS_JZ_A = 158 , TRICORE_INS_JZ_T = 159 , TRICORE_INS_JZ = 160 , TRICORE_INS_J = 161 , TRICORE_INS_LDLCX = 162 , TRICORE_INS_LDMST = 163 , TRICORE_INS_LDUCX = 164 , TRICORE_INS_LD_A = 165 , TRICORE_INS_LD_BU = 166 , TRICORE_INS_LD_B = 167 , TRICORE_INS_LD_DA = 168 , TRICORE_INS_LD_D = 169 , TRICORE_INS_LD_HU = 170 , TRICORE_INS_LD_H = 171 , TRICORE_INS_LD_Q = 172 , TRICORE_INS_LD_W = 173 , TRICORE_INS_LEA = 174 , TRICORE_INS_LHA = 175 , TRICORE_INS_LOOPU = 176 , TRICORE_INS_LOOP = 177 , TRICORE_INS_LT_A = 178 , TRICORE_INS_LT_B = 179 , TRICORE_INS_LT_BU = 180 , TRICORE_INS_LT_H = 181 , TRICORE_INS_LT_HU = 182 , TRICORE_INS_LT_U = 183 , TRICORE_INS_LT_W = 184 , TRICORE_INS_LT_WU = 185 , TRICORE_INS_LT = 186 , TRICORE_INS_MADDMS_H = 187 , TRICORE_INS_MADDMS_U = 188 , TRICORE_INS_MADDMS = 189 , TRICORE_INS_MADDM_H = 190 , TRICORE_INS_MADDM_Q = 191 , TRICORE_INS_MADDM_U = 192 , TRICORE_INS_MADDM = 193 , TRICORE_INS_MADDRS_H = 194 , TRICORE_INS_MADDRS_Q = 195 , TRICORE_INS_MADDR_H = 196 , TRICORE_INS_MADDR_Q = 197 , TRICORE_INS_MADDSUMS_H = 198 , TRICORE_INS_MADDSUM_H = 199 , TRICORE_INS_MADDSURS_H = 200 , TRICORE_INS_MADDSUR_H = 201 , TRICORE_INS_MADDSUS_H = 202 , TRICORE_INS_MADDSU_H = 203 , TRICORE_INS_MADDS_H = 204 , TRICORE_INS_MADDS_Q = 205 , TRICORE_INS_MADDS_U = 206 , TRICORE_INS_MADDS = 207 , TRICORE_INS_MADD_F = 208 , TRICORE_INS_MADD_H = 209 , TRICORE_INS_MADD_Q = 210 , TRICORE_INS_MADD_U = 211 , TRICORE_INS_MADD = 212 , TRICORE_INS_MAX_B = 213 , TRICORE_INS_MAX_BU = 214 , TRICORE_INS_MAX_H = 215 , TRICORE_INS_MAX_HU = 216 , TRICORE_INS_MAX_U = 217 , TRICORE_INS_MAX = 218 , TRICORE_INS_MFCR = 219 , TRICORE_INS_MIN_B = 220 , TRICORE_INS_MIN_BU = 221 , TRICORE_INS_MIN_H = 222 , TRICORE_INS_MIN_HU = 223 , TRICORE_INS_MIN_U = 224 , TRICORE_INS_MIN = 225 , TRICORE_INS_MOVH_A = 226 , TRICORE_INS_MOVH = 227 , TRICORE_INS_MOVZ_A = 228 , TRICORE_INS_MOV_AA = 229 , TRICORE_INS_MOV_A = 230 , TRICORE_INS_MOV_D = 231 , TRICORE_INS_MOV_U = 232 , TRICORE_INS_MOV = 233 , TRICORE_INS_MSUBADMS_H = 234 , TRICORE_INS_MSUBADM_H = 235 , TRICORE_INS_MSUBADRS_H = 236 , TRICORE_INS_MSUBADR_H = 237 , TRICORE_INS_MSUBADS_H = 238 , TRICORE_INS_MSUBAD_H = 239 , TRICORE_INS_MSUBMS_H = 240 , TRICORE_INS_MSUBMS_U = 241 , TRICORE_INS_MSUBMS = 242 , TRICORE_INS_MSUBM_H = 243 , TRICORE_INS_MSUBM_Q = 244 , TRICORE_INS_MSUBM_U = 245 , TRICORE_INS_MSUBM = 246 , TRICORE_INS_MSUBRS_H = 247 , TRICORE_INS_MSUBRS_Q = 248 , TRICORE_INS_MSUBR_H = 249 , TRICORE_INS_MSUBR_Q = 250 , TRICORE_INS_MSUBS_H = 251 , TRICORE_INS_MSUBS_Q = 252 , TRICORE_INS_MSUBS_U = 253 , TRICORE_INS_MSUBS = 254 , TRICORE_INS_MSUB_F = 255 , TRICORE_INS_MSUB_H = 256 , TRICORE_INS_MSUB_Q = 257 , TRICORE_INS_MSUB_U = 258 , TRICORE_INS_MSUB = 259 , TRICORE_INS_MTCR = 260 , TRICORE_INS_MULMS_H = 261 , TRICORE_INS_MULM_H = 262 , TRICORE_INS_MULM_U = 263 , TRICORE_INS_MULM = 264 , TRICORE_INS_MULR_H = 265 , TRICORE_INS_MULR_Q = 266 , TRICORE_INS_MULS_U = 267 , TRICORE_INS_MULS = 268 , TRICORE_INS_MUL_F = 269 , TRICORE_INS_MUL_H = 270 , TRICORE_INS_MUL_Q = 271 , TRICORE_INS_MUL_U = 272 , TRICORE_INS_MUL = 273 , TRICORE_INS_NAND_T = 274 , TRICORE_INS_NAND = 275 , TRICORE_INS_NEZ_A = 276 , TRICORE_INS_NE_A = 277 , TRICORE_INS_NE = 278 , TRICORE_INS_NOP = 279 , TRICORE_INS_NOR_T = 280 , TRICORE_INS_NOR = 281 , TRICORE_INS_NOT = 282 , TRICORE_INS_ORN_T = 283 , TRICORE_INS_ORN = 284 , TRICORE_INS_OR_ANDN_T = 285 , TRICORE_INS_OR_AND_T = 286 , TRICORE_INS_OR_EQ = 287 , TRICORE_INS_OR_GE_U = 288 , TRICORE_INS_OR_GE = 289 , TRICORE_INS_OR_LT_U = 290 , TRICORE_INS_OR_LT = 291 , TRICORE_INS_OR_NE = 292 , TRICORE_INS_OR_NOR_T = 293 , TRICORE_INS_OR_OR_T = 294 , TRICORE_INS_OR_T = 295 , TRICORE_INS_OR = 296 , TRICORE_INS_PACK = 297 , TRICORE_INS_PARITY = 298 , TRICORE_INS_POPCNT_W = 299 , TRICORE_INS_Q31TOF = 300 , TRICORE_INS_QSEED_F = 301 , TRICORE_INS_RESTORE = 302 , TRICORE_INS_RET = 303 , TRICORE_INS_RFE = 304 , TRICORE_INS_RFM = 305 , TRICORE_INS_RSLCX = 306 , TRICORE_INS_RSTV = 307 , TRICORE_INS_RSUBS_U = 308 , TRICORE_INS_RSUBS = 309 , TRICORE_INS_RSUB = 310 , TRICORE_INS_SAT_BU = 311 , TRICORE_INS_SAT_B = 312 , TRICORE_INS_SAT_HU = 313 , TRICORE_INS_SAT_H = 314 , TRICORE_INS_SELN_A = 315 , TRICORE_INS_SELN = 316 , TRICORE_INS_SEL_A = 317 , TRICORE_INS_SEL = 318 , TRICORE_INS_SHAS = 319 , TRICORE_INS_SHA_B = 320 , TRICORE_INS_SHA_H = 321 , TRICORE_INS_SHA = 322 , TRICORE_INS_SHUFFLE = 323 , TRICORE_INS_SH_ANDN_T = 324 , TRICORE_INS_SH_AND_T = 325 , TRICORE_INS_SH_B = 326 , TRICORE_INS_SH_EQ = 327 , TRICORE_INS_SH_GE_U = 328 , TRICORE_INS_SH_GE = 329 , TRICORE_INS_SH_H = 330 , TRICORE_INS_SH_LT_U = 331 , TRICORE_INS_SH_LT = 332 , TRICORE_INS_SH_NAND_T = 333 , TRICORE_INS_SH_NE = 334 , TRICORE_INS_SH_NOR_T = 335 , TRICORE_INS_SH_ORN_T = 336 , TRICORE_INS_SH_OR_T = 337 , TRICORE_INS_SH_XNOR_T = 338 , TRICORE_INS_SH_XOR_T = 339 , TRICORE_INS_SH = 340 , TRICORE_INS_STLCX = 341 , TRICORE_INS_STUCX = 342 , TRICORE_INS_ST_A = 343 , TRICORE_INS_ST_B = 344 , TRICORE_INS_ST_DA = 345 , TRICORE_INS_ST_D = 346 , TRICORE_INS_ST_H = 347 , TRICORE_INS_ST_Q = 348 , TRICORE_INS_ST_T = 349 , TRICORE_INS_ST_W = 350 , TRICORE_INS_SUBC = 351 , TRICORE_INS_SUBSC_A = 352 , TRICORE_INS_SUBS_BU = 353 , TRICORE_INS_SUBS_B = 354 , TRICORE_INS_SUBS_HU = 355 , TRICORE_INS_SUBS_H = 356 , TRICORE_INS_SUBS_U = 357 , TRICORE_INS_SUBS = 358 , TRICORE_INS_SUBX = 359 , TRICORE_INS_SUB_A = 360 , TRICORE_INS_SUB_B = 361 , TRICORE_INS_SUB_F = 362 , TRICORE_INS_SUB_H = 363 , TRICORE_INS_SUB = 364 , TRICORE_INS_SVLCX = 365 , TRICORE_INS_SWAPMSK_W = 366 , TRICORE_INS_SWAP_A = 367 , TRICORE_INS_SWAP_W = 368 , TRICORE_INS_SYSCALL = 369 , TRICORE_INS_TLBDEMAP = 370 , TRICORE_INS_TLBFLUSH_A = 371 , TRICORE_INS_TLBFLUSH_B = 372 , TRICORE_INS_TLBMAP = 373 , TRICORE_INS_TLBPROBE_A = 374 , TRICORE_INS_TLBPROBE_I = 375 , TRICORE_INS_TRAPSV = 376 , TRICORE_INS_TRAPV = 377 , TRICORE_INS_UNPACK = 378 , TRICORE_INS_UPDFL = 379 , TRICORE_INS_UTOF = 380 , TRICORE_INS_WAIT = 381 , TRICORE_INS_XNOR_T = 382 , TRICORE_INS_XNOR = 383 , TRICORE_INS_XOR_EQ = 384 , TRICORE_INS_XOR_GE_U = 385 , TRICORE_INS_XOR_GE = 386 , TRICORE_INS_XOR_LT_U = 387 , TRICORE_INS_XOR_LT = 388 , TRICORE_INS_XOR_NE = 389 , TRICORE_INS_XOR = 390 , TRICORE_INS_ENDING = 391 , } # [repr (u32)] # [doc = " Group of TriCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn_group { # [doc = "< = CS_GRP_INVALID"] TRICORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_CALL"] TRICORE_GRP_CALL = 1 , # [doc = "< = CS_GRP_JUMP"] TRICORE_GRP_JUMP = 2 , # [doc = "< mark the end of the list of groups"] TRICORE_GRP_ENDING = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_feature_t { TRICORE_FEATURE_INVALID = 0 , TRICORE_FEATURE_HasV110 = 128 , TRICORE_FEATURE_HasV120_UP = 129 , TRICORE_FEATURE_HasV130_UP = 130 , TRICORE_FEATURE_HasV161 = 131 , TRICORE_FEATURE_HasV160_UP = 132 , TRICORE_FEATURE_HasV131_UP = 133 , TRICORE_FEATURE_HasV161_UP = 134 , TRICORE_FEATURE_HasV162 = 135 , TRICORE_FEATURE_HasV162_UP = 136 , # [doc = "< mark the end of the list of features"] TRICORE_FEATURE_ENDING = 137 , } pub use self :: tricore_feature_t as tricore_feature ; # [doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_detail { pub regs_read : [u16 ; 20usize] , # [doc = "< number of implicit registers read by this insn"] pub regs_read_count : u8 , pub regs_write : [u16 ; 20usize] , # [doc = "< number of implicit registers modified by this insn"] pub regs_write_count : u8 , # [doc = "< list of group this instruction belong to"] pub groups : [u8 ; 8usize] , # [doc = "< number of groups this insn belongs to"] pub groups_count : u8 , # [doc = "< Instruction has writeback operands."] pub writeback : bool , pub __bindgen_anon_1 : cs_detail__bindgen_ty_1 , } # [doc = " Architecture-specific instruction info"] # [repr (C)] # [derive (Copy , Clone)] pub union cs_detail__bindgen_ty_1 { # [doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"] pub x86 : cs_x86 , # [doc = "< ARM64 architecture (aka AArch64)"] pub arm64 : cs_arm64 , # [doc = "< ARM architecture (including Thumb/Thumb2)"] pub arm : cs_arm , # [doc = "< M68K architecture"] pub m68k : cs_m68k , # [doc = "< MIPS architecture"] pub mips : cs_mips , # [doc = "< PowerPC architecture"] pub ppc : cs_ppc , # [doc = "< Sparc architecture"] pub sparc : cs_sparc , # [doc = "< SystemZ architecture"] pub sysz : cs_sysz , # [doc = "< XCore architecture"] pub xcore : cs_xcore , # [doc = "< TMS320C64x architecture"] pub tms320c64x : cs_tms320c64x , # [doc = "< M680X architecture"] pub m680x : cs_m680x , # [doc = "< Ethereum architecture"] pub evm : cs_evm , # [doc = "< MOS65XX architecture (including MOS6502)"] pub mos65xx : cs_mos65xx , # [doc = "< Web Assembly architecture"] pub wasm : cs_wasm , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] pub bpf : cs_bpf , # [doc = "< RISCV architecture"] pub riscv : cs_riscv , # [doc = "< SH architecture"] pub sh : cs_sh , # [doc = "< TriCore architecture"] pub tricore : cs_tricore , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_detail__bindgen_ty_1 > () - 1768usize] ; ["Alignment of cs_detail__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_detail__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_detail__bindgen_ty_1::x86"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , x86) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm64"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm64) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m68k"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m68k) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mips"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mips) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::ppc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , ppc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sparc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sparc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sysz"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sysz) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::xcore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , xcore) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tms320c64x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tms320c64x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m680x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m680x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::evm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , evm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mos65xx"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mos65xx) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::wasm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , wasm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::bpf"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , bpf) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::riscv"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , riscv) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sh"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sh) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tricore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tricore) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_detail__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail"] [:: std :: mem :: size_of :: < cs_detail > () - 1864usize] ; ["Alignment of cs_detail"] [:: std :: mem :: align_of :: < cs_detail > () - 8usize] ; ["Offset of field: cs_detail::regs_read"] [:: std :: mem :: offset_of ! (cs_detail , regs_read) - 0usize] ; ["Offset of field: cs_detail::regs_read_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_read_count) - 40usize] ; ["Offset of field: cs_detail::regs_write"] [:: std :: mem :: offset_of ! (cs_detail , regs_write) - 42usize] ; ["Offset of field: cs_detail::regs_write_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_write_count) - 82usize] ; ["Offset of field: cs_detail::groups"] [:: std :: mem :: offset_of ! (cs_detail , groups) - 83usize] ; ["Offset of field: cs_detail::groups_count"] [:: std :: mem :: offset_of ! (cs_detail , groups_count) - 91usize] ; ["Offset of field: cs_detail::writeback"] [:: std :: mem :: offset_of ! (cs_detail , writeback) - 92usize] ; } ; impl :: std :: fmt :: Debug for cs_detail { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, writeback: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . writeback , self . __bindgen_anon_1) } } # [doc = " Detail information of disassembled instruction"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_insn { # [doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub address : u64 , # [doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub size : u16 , # [doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub bytes : [u8 ; 24usize] , # [doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub mnemonic : [:: std :: os :: raw :: c_char ; 32usize] , # [doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub op_str : [:: std :: os :: raw :: c_char ; 160usize] , # [doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."] pub detail : * mut cs_detail , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_insn"] [:: std :: mem :: size_of :: < cs_insn > () - 248usize] ; ["Alignment of cs_insn"] [:: std :: mem :: align_of :: < cs_insn > () - 8usize] ; ["Offset of field: cs_insn::id"] [:: std :: mem :: offset_of ! (cs_insn , id) - 0usize] ; ["Offset of field: cs_insn::address"] [:: std :: mem :: offset_of ! (cs_insn , address) - 8usize] ; ["Offset of field: cs_insn::size"] [:: std :: mem :: offset_of ! (cs_insn , size) - 16usize] ; ["Offset of field: cs_insn::bytes"] [:: std :: mem :: offset_of ! (cs_insn , bytes) - 18usize] ; ["Offset of field: cs_insn::mnemonic"] [:: std :: mem :: offset_of ! (cs_insn , mnemonic) - 42usize] ; ["Offset of field: cs_insn::op_str"] [:: std :: mem :: offset_of ! (cs_insn , op_str) - 74usize] ; ["Offset of field: cs_insn::detail"] [:: std :: mem :: offset_of ! (cs_insn , detail) - 240usize] ; } ; # [repr (u32)] # [doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_err { # [doc = "< No error: everything was fine"] CS_ERR_OK = 0 , # [doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"] CS_ERR_MEM = 1 , # [doc = "< Unsupported architecture: cs_open()"] CS_ERR_ARCH = 2 , # [doc = "< Invalid handle: cs_op_count(), cs_op_index()"] CS_ERR_HANDLE = 3 , # [doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"] CS_ERR_CSH = 4 , # [doc = "< Invalid/unsupported mode: cs_open()"] CS_ERR_MODE = 5 , # [doc = "< Invalid/unsupported option: cs_option()"] CS_ERR_OPTION = 6 , # [doc = "< Information is unavailable because detail option is OFF"] CS_ERR_DETAIL = 7 , # [doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"] CS_ERR_MEMSETUP = 8 , # [doc = "< Unsupported version (bindings)"] CS_ERR_VERSION = 9 , # [doc = "< Access irrelevant data in \"diet\" engine"] CS_ERR_DIET = 10 , # [doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"] CS_ERR_SKIPDATA = 11 , # [doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_ATT = 12 , # [doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_INTEL = 13 , # [doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_MASM = 14 , } unsafe extern "C" { # [doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."] pub fn cs_version (major : * mut :: std :: os :: raw :: c_int , minor : * mut :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_uint ; } unsafe extern "C" { # [doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."] pub fn cs_support (query : :: std :: os :: raw :: c_int) -> bool ; } unsafe extern "C" { # [doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_open (arch : cs_arch , mode : cs_mode , handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_close (handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"] pub fn cs_option (handle : csh , type_ : cs_opt_type , value : usize) -> cs_err ; } unsafe extern "C" { # [doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"] pub fn cs_errno (handle : csh) -> cs_err ; } unsafe extern "C" { # [doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"] pub fn cs_strerror (code : cs_err) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm (handle : csh , code : * const u8 , code_size : usize , address : u64 , count : usize , insn : * mut * mut cs_insn) -> usize ; } unsafe extern "C" { # [doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."] pub fn cs_free (insn : * mut cs_insn , count : usize) ; } unsafe extern "C" { # [doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"] pub fn cs_malloc (handle : csh) -> * mut cs_insn ; } unsafe extern "C" { # [doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm_iter (handle : csh , code : * mut * const u8 , size : * mut usize , address : * mut u64 , insn : * mut cs_insn) -> bool ; } unsafe extern "C" { # [doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."] pub fn cs_reg_name (handle : csh , reg_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."] pub fn cs_insn_name (handle : csh , insn_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."] pub fn cs_group_name (handle : csh , group_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."] pub fn cs_insn_group (handle : csh , insn : * const cs_insn , group_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."] pub fn cs_reg_read (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."] pub fn cs_reg_write (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."] pub fn cs_op_count (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."] pub fn cs_op_index (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint , position : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } # [doc = " Type of array to keep the list of registers"] pub type cs_regs = [u16 ; 64usize] ; unsafe extern "C" { # [doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_regs_access (handle : csh , insn : * const cs_insn , regs_read : * mut u16 , regs_read_count : * mut u8 , regs_write : * mut u16 , regs_write_count : * mut u8) -> cs_err ; } pub type __builtin_va_list = [__va_list_tag ; 1usize] ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __va_list_tag { pub gp_offset : :: std :: os :: raw :: c_uint , pub fp_offset : :: std :: os :: raw :: c_uint , pub overflow_arg_area : * mut :: std :: os :: raw :: c_void , pub reg_save_area : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __va_list_tag"] [:: std :: mem :: size_of :: < __va_list_tag > () - 24usize] ; ["Alignment of __va_list_tag"] [:: std :: mem :: align_of :: < __va_list_tag > () - 8usize] ; ["Offset of field: __va_list_tag::gp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , gp_offset) - 0usize] ; ["Offset of field: __va_list_tag::fp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , fp_offset) - 4usize] ; ["Offset of field: __va_list_tag::overflow_arg_area"] [:: std :: mem :: offset_of ! (__va_list_tag , overflow_arg_area) - 8usize] ; ["Offset of field: __va_list_tag::reg_save_area"] [:: std :: mem :: offset_of ! (__va_list_tag , reg_save_area) - 16usize] ; } ;
[INFO] [stdout]   |
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: unnecessary transmute
[INFO] [stdout]  --> /opt/rustwide/target/debug/build/falcon_capstone/f982cdb455ed4cf6/out/bindings.rs:3:80524
[INFO] [stdout]   |
[INFO] [stdout] 3 | ... { :: std :: mem :: transmute (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } ...
[INFO] [stdout]   |       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout] help: replace this with
[INFO] [stdout]   |
[INFO] [stdout] 3 - # [repr (C)] # [derive (Copy , Clone , Debug , Default , Eq , Hash , Ord , PartialEq , PartialOrd)] pub struct __BindgenBitfieldUnit < Storage > { storage : Storage , } impl < Storage > __BindgenBitfieldUnit < Storage > { # [inline] pub const fn new (storage : Storage) -> Self { Self { storage } } } impl < Storage > __BindgenBitfieldUnit < Storage > where Storage : AsRef < [u8] > + AsMut < [u8] >, { # [inline] fn extract_bit (byte : u8 , index : usize) -> bool { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; byte & mask == mask } # [inline] pub fn get_bit (& self , index : usize) -> bool { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = self . storage . as_ref () [byte_index] ; Self :: extract_bit (byte , index) } # [inline] pub unsafe fn raw_get_bit (this : * const Self , index : usize) -> bool { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { * (core :: ptr :: addr_of ! ((* this) . storage) as * const u8) . offset (byte_index as isize) } ; Self :: extract_bit (byte , index) } # [inline] fn change_bit (byte : u8 , index : usize , val : bool) -> u8 { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; if val { byte | mask } else { byte & ! mask } } # [inline] pub fn set_bit (& mut self , index : usize , val : bool) { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = & mut self . storage . as_mut () [byte_index] ; * byte = Self :: change_bit (* byte , index , val) ; } # [inline] pub unsafe fn raw_set_bit (this : * mut Self , index : usize , val : bool) { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { (core :: ptr :: addr_of_mut ! ((* this) . storage) as * mut u8) . offset (byte_index as isize) } ; unsafe { * byte = Self :: change_bit (* byte , index , val) } ; } # [inline] pub fn get (& self , bit_offset : usize , bit_width : u8) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if self . get_bit (i + bit_offset) { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub unsafe fn raw_get (this : * const Self , bit_offset : usize , bit_width : u8 ,) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if unsafe { Self :: raw_get_bit (this , i + bit_offset) } { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub fn set (& mut self , bit_offset : usize , bit_width : u8 , val : u64) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; self . set_bit (index + bit_offset , val_bit_is_set) ; } } # [inline] pub unsafe fn raw_set (this : * mut Self , bit_offset : usize , bit_width : u8 , val : u64 ,) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; unsafe { Self :: raw_set_bit (this , index + bit_offset , val_bit_is_set) } ; } } } # [derive (PartialEq , Copy , Clone , Hash , Debug , Default)] # [repr (C)] pub struct __BindgenComplex < T > { pub re : T , pub im : T } pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __GLIBC_USE_ISOC2Y : u32 = 0 ; pub const __GLIBC_USE_ISOC23 : u32 = 0 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 202405 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_XOPEN2K24 : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const __TIMESIZE : u32 = 64 ; pub const __USE_TIME_BITS64 : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_GETS : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_SCANF : u32 = 0 ; pub const __GLIBC_USE_C23_STRTOL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_60559_BFP__ : u32 = 201404 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_IEC_60559_COMPLEX__ : u32 = 201404 ; pub const __STDC_ISO_10646__ : u32 = 201706 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 43 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __glibc_c99_flexarr_available : u32 = 1 ; pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI : u32 = 0 ; pub const __HAVE_GENERIC_SELECTION : u32 = 1 ; pub const __GLIBC_USE_LIB_EXT2 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_TYPES_EXT : u32 = 0 ; pub const _STDLIB_H : u32 = 1 ; pub const WNOHANG : u32 = 1 ; pub const WUNTRACED : u32 = 2 ; pub const WSTOPPED : u32 = 2 ; pub const WEXITED : u32 = 4 ; pub const WCONTINUED : u32 = 8 ; pub const WNOWAIT : u32 = 16777216 ; pub const __WNOTHREAD : u32 = 536870912 ; pub const __WALL : u32 = 1073741824 ; pub const __WCLONE : u32 = 2147483648 ; pub const __W_CONTINUED : u32 = 65535 ; pub const __WCOREFLAG : u32 = 128 ; pub const __HAVE_FLOAT128 : u32 = 1 ; pub const __HAVE_DISTINCT_FLOAT128 : u32 = 1 ; pub const __HAVE_FLOAT64X : u32 = 1 ; pub const __HAVE_FLOAT64X_LONG_DOUBLE : u32 = 1 ; pub const __HAVE_FLOAT16 : u32 = 0 ; pub const __HAVE_FLOAT32 : u32 = 1 ; pub const __HAVE_FLOAT64 : u32 = 1 ; pub const __HAVE_FLOAT32X : u32 = 1 ; pub const __HAVE_FLOAT128X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT16 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT128X : u32 = 0 ; pub const __HAVE_FLOATN_NOT_TYPEDEF : u32 = 0 ; pub const __ldiv_t_defined : u32 = 1 ; pub const __lldiv_t_defined : u32 = 1 ; pub const RAND_MAX : u32 = 2147483647 ; pub const EXIT_FAILURE : u32 = 1 ; pub const EXIT_SUCCESS : u32 = 0 ; pub const _SYS_TYPES_H : u32 = 1 ; pub const _BITS_TYPES_H : u32 = 1 ; pub const _BITS_TYPESIZES_H : u32 = 1 ; pub const __OFF_T_MATCHES_OFF64_T : u32 = 1 ; pub const __INO_T_MATCHES_INO64_T : u32 = 1 ; pub const __RLIM_T_MATCHES_RLIM64_T : u32 = 1 ; pub const __STATFS_MATCHES_STATFS64 : u32 = 1 ; pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 : u32 = 1 ; pub const __FD_SETSIZE : u32 = 1024 ; pub const _BITS_TIME64_H : u32 = 1 ; pub const __clock_t_defined : u32 = 1 ; pub const __clockid_t_defined : u32 = 1 ; pub const __time_t_defined : u32 = 1 ; pub const __timer_t_defined : u32 = 1 ; pub const _BITS_STDINT_INTN_H : u32 = 1 ; pub const __BIT_TYPES_DEFINED__ : u32 = 1 ; pub const _ENDIAN_H : u32 = 1 ; pub const _BITS_ENDIAN_H : u32 = 1 ; pub const __LITTLE_ENDIAN : u32 = 1234 ; pub const __BIG_ENDIAN : u32 = 4321 ; pub const __PDP_ENDIAN : u32 = 3412 ; pub const _BITS_ENDIANNESS_H : u32 = 1 ; pub const __BYTE_ORDER : u32 = 1234 ; pub const __FLOAT_WORD_ORDER : u32 = 1234 ; pub const LITTLE_ENDIAN : u32 = 1234 ; pub const BIG_ENDIAN : u32 = 4321 ; pub const PDP_ENDIAN : u32 = 3412 ; pub const BYTE_ORDER : u32 = 1234 ; pub const _BITS_BYTESWAP_H : u32 = 1 ; pub const _BITS_UINTN_IDENTITY_H : u32 = 1 ; pub const _SYS_SELECT_H : u32 = 1 ; pub const __sigset_t_defined : u32 = 1 ; pub const __timeval_defined : u32 = 1 ; pub const _STRUCT_TIMESPEC : u32 = 1 ; pub const FD_SETSIZE : u32 = 1024 ; pub const _BITS_PTHREADTYPES_COMMON_H : u32 = 1 ; pub const _THREAD_SHARED_TYPES_H : u32 = 1 ; pub const _BITS_PTHREADTYPES_ARCH_H : u32 = 1 ; pub const __SIZEOF_PTHREAD_MUTEX_T : u32 = 40 ; pub const __SIZEOF_PTHREAD_ATTR_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_RWLOCK_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_BARRIER_T : u32 = 32 ; pub const __SIZEOF_PTHREAD_MUTEXATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_COND_T : u32 = 48 ; pub const __SIZEOF_PTHREAD_CONDATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_RWLOCKATTR_T : u32 = 8 ; pub const __SIZEOF_PTHREAD_BARRIERATTR_T : u32 = 4 ; pub const _THREAD_MUTEX_INTERNAL_H : u32 = 1 ; pub const __PTHREAD_MUTEX_HAVE_PREV : u32 = 1 ; pub const __have_pthread_attr_t : u32 = 1 ; pub const _ALLOCA_H : u32 = 1 ; pub const _STDIO_H : u32 = 1 ; pub const _____fpos_t_defined : u32 = 1 ; pub const ____mbstate_t_defined : u32 = 1 ; pub const _____fpos64_t_defined : u32 = 1 ; pub const ____FILE_defined : u32 = 1 ; pub const __FILE_defined : u32 = 1 ; pub const __struct_FILE_defined : u32 = 1 ; pub const _IO_EOF_SEEN : u32 = 16 ; pub const _IO_ERR_SEEN : u32 = 32 ; pub const _IO_USER_LOCK : u32 = 32768 ; pub const __cookie_io_functions_t_defined : u32 = 1 ; pub const _IOFBF : u32 = 0 ; pub const _IOLBF : u32 = 1 ; pub const _IONBF : u32 = 2 ; pub const BUFSIZ : u32 = 8192 ; pub const EOF : i32 = - 1 ; pub const SEEK_SET : u32 = 0 ; pub const SEEK_CUR : u32 = 1 ; pub const SEEK_END : u32 = 2 ; pub const P_tmpdir : & [u8 ; 5] = b"/tmp\0" ; pub const L_tmpnam : u32 = 20 ; pub const TMP_MAX : u32 = 238328 ; pub const _BITS_STDIO_LIM_H : u32 = 1 ; pub const FILENAME_MAX : u32 = 4096 ; pub const L_ctermid : u32 = 9 ; pub const FOPEN_MAX : u32 = 16 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const _INTTYPES_H : u32 = 1 ; pub const _STDINT_H : u32 = 1 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const _BITS_STDINT_UINTN_H : u32 = 1 ; pub const _BITS_STDINT_LEAST_H : u32 = 1 ; pub const INT8_MIN : i32 = - 128 ; pub const INT16_MIN : i32 = - 32768 ; pub const INT32_MIN : i32 = - 2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = - 128 ; pub const INT_LEAST16_MIN : i32 = - 32768 ; pub const INT_LEAST32_MIN : i32 = - 2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = - 128 ; pub const INT_FAST16_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST32_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = - 1 ; pub const UINT_FAST32_MAX : i32 = - 1 ; pub const INTPTR_MIN : i64 = - 9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = - 1 ; pub const PTRDIFF_MIN : i64 = - 9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = - 2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = - 1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const ____gwchar_t_defined : u32 = 1 ; pub const __PRI64_PREFIX : & [u8 ; 2] = b"l\0" ; pub const __PRIPTR_PREFIX : & [u8 ; 2] = b"l\0" ; pub const PRId8 : & [u8 ; 4] = b"hhd\0" ; pub const PRId16 : & [u8 ; 3] = b"hd\0" ; pub const PRId32 : & [u8 ; 2] = b"d\0" ; pub const PRId64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const PRIdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const PRIdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIi8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIi16 : & [u8 ; 3] = b"hi\0" ; pub const PRIi32 : & [u8 ; 2] = b"i\0" ; pub const PRIi64 : & [u8 ; 3] = b"li\0" ; pub const PRIiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const PRIiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const PRIiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiFAST16 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST32 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIo8 : & [u8 ; 4] = b"hho\0" ; pub const PRIo16 : & [u8 ; 3] = b"ho\0" ; pub const PRIo32 : & [u8 ; 2] = b"o\0" ; pub const PRIo64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const PRIoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const PRIoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIu8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIu16 : & [u8 ; 3] = b"hu\0" ; pub const PRIu32 : & [u8 ; 2] = b"u\0" ; pub const PRIu64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const PRIuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const PRIuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIx8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIx16 : & [u8 ; 3] = b"hx\0" ; pub const PRIx32 : & [u8 ; 2] = b"x\0" ; pub const PRIx64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const PRIxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const PRIxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIX8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIX16 : & [u8 ; 3] = b"hX\0" ; pub const PRIX32 : & [u8 ; 2] = b"X\0" ; pub const PRIX64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXLEAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXLEAST16 : & [u8 ; 3] = b"hX\0" ; pub const PRIXLEAST32 : & [u8 ; 2] = b"X\0" ; pub const PRIXLEAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXFAST16 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST32 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIdMAX : & [u8 ; 3] = b"ld\0" ; pub const PRIiMAX : & [u8 ; 3] = b"li\0" ; pub const PRIoMAX : & [u8 ; 3] = b"lo\0" ; pub const PRIuMAX : & [u8 ; 3] = b"lu\0" ; pub const PRIxMAX : & [u8 ; 3] = b"lx\0" ; pub const PRIXMAX : & [u8 ; 3] = b"lX\0" ; pub const PRIdPTR : & [u8 ; 3] = b"ld\0" ; pub const PRIiPTR : & [u8 ; 3] = b"li\0" ; pub const PRIoPTR : & [u8 ; 3] = b"lo\0" ; pub const PRIuPTR : & [u8 ; 3] = b"lu\0" ; pub const PRIxPTR : & [u8 ; 3] = b"lx\0" ; pub const PRIXPTR : & [u8 ; 3] = b"lX\0" ; pub const SCNd8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNd16 : & [u8 ; 3] = b"hd\0" ; pub const SCNd32 : & [u8 ; 2] = b"d\0" ; pub const SCNd64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const SCNdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const SCNdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNi8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNi16 : & [u8 ; 3] = b"hi\0" ; pub const SCNi32 : & [u8 ; 2] = b"i\0" ; pub const SCNi64 : & [u8 ; 3] = b"li\0" ; pub const SCNiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const SCNiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const SCNiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiFAST16 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST32 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNu8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNu16 : & [u8 ; 3] = b"hu\0" ; pub const SCNu32 : & [u8 ; 2] = b"u\0" ; pub const SCNu64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const SCNuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const SCNuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNo8 : & [u8 ; 4] = b"hho\0" ; pub const SCNo16 : & [u8 ; 3] = b"ho\0" ; pub const SCNo32 : & [u8 ; 2] = b"o\0" ; pub const SCNo64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const SCNoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const SCNoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNx8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNx16 : & [u8 ; 3] = b"hx\0" ; pub const SCNx32 : & [u8 ; 2] = b"x\0" ; pub const SCNx64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const SCNxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const SCNxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNdMAX : & [u8 ; 3] = b"ld\0" ; pub const SCNiMAX : & [u8 ; 3] = b"li\0" ; pub const SCNoMAX : & [u8 ; 3] = b"lo\0" ; pub const SCNuMAX : & [u8 ; 3] = b"lu\0" ; pub const SCNxMAX : & [u8 ; 3] = b"lx\0" ; pub const SCNdPTR : & [u8 ; 3] = b"ld\0" ; pub const SCNiPTR : & [u8 ; 3] = b"li\0" ; pub const SCNoPTR : & [u8 ; 3] = b"lo\0" ; pub const SCNuPTR : & [u8 ; 3] = b"lu\0" ; pub const SCNxPTR : & [u8 ; 3] = b"lx\0" ; pub const CS_API_MAJOR : u32 = 5 ; pub const CS_API_MINOR : u32 = 0 ; pub const CS_NEXT_VERSION : u32 = 5 ; pub const CS_VERSION_MAJOR : u32 = 5 ; pub const CS_VERSION_MINOR : u32 = 0 ; pub const CS_VERSION_EXTRA : u32 = 7 ; pub const CS_MNEMONIC_SIZE : u32 = 32 ; pub const M68K_OPERAND_COUNT : u32 = 4 ; pub const X86_EFLAGS_MODIFY_AF : u32 = 1 ; pub const X86_EFLAGS_MODIFY_CF : u32 = 2 ; pub const X86_EFLAGS_MODIFY_SF : u32 = 4 ; pub const X86_EFLAGS_MODIFY_ZF : u32 = 8 ; pub const X86_EFLAGS_MODIFY_PF : u32 = 16 ; pub const X86_EFLAGS_MODIFY_OF : u32 = 32 ; pub const X86_EFLAGS_MODIFY_TF : u32 = 64 ; pub const X86_EFLAGS_MODIFY_IF : u32 = 128 ; pub const X86_EFLAGS_MODIFY_DF : u32 = 256 ; pub const X86_EFLAGS_MODIFY_NT : u32 = 512 ; pub const X86_EFLAGS_MODIFY_RF : u32 = 1024 ; pub const X86_EFLAGS_PRIOR_OF : u32 = 2048 ; pub const X86_EFLAGS_PRIOR_SF : u32 = 4096 ; pub const X86_EFLAGS_PRIOR_ZF : u32 = 8192 ; pub const X86_EFLAGS_PRIOR_AF : u32 = 16384 ; pub const X86_EFLAGS_PRIOR_PF : u32 = 32768 ; pub const X86_EFLAGS_PRIOR_CF : u32 = 65536 ; pub const X86_EFLAGS_PRIOR_TF : u32 = 131072 ; pub const X86_EFLAGS_PRIOR_IF : u32 = 262144 ; pub const X86_EFLAGS_PRIOR_DF : u32 = 524288 ; pub const X86_EFLAGS_PRIOR_NT : u32 = 1048576 ; pub const X86_EFLAGS_RESET_OF : u32 = 2097152 ; pub const X86_EFLAGS_RESET_CF : u32 = 4194304 ; pub const X86_EFLAGS_RESET_DF : u32 = 8388608 ; pub const X86_EFLAGS_RESET_IF : u32 = 16777216 ; pub const X86_EFLAGS_RESET_SF : u32 = 33554432 ; pub const X86_EFLAGS_RESET_AF : u32 = 67108864 ; pub const X86_EFLAGS_RESET_TF : u32 = 134217728 ; pub const X86_EFLAGS_RESET_NT : u32 = 268435456 ; pub const X86_EFLAGS_RESET_PF : u32 = 536870912 ; pub const X86_EFLAGS_SET_CF : u32 = 1073741824 ; pub const X86_EFLAGS_SET_DF : u32 = 2147483648 ; pub const X86_EFLAGS_SET_IF : u64 = 4294967296 ; pub const X86_EFLAGS_TEST_OF : u64 = 8589934592 ; pub const X86_EFLAGS_TEST_SF : u64 = 17179869184 ; pub const X86_EFLAGS_TEST_ZF : u64 = 34359738368 ; pub const X86_EFLAGS_TEST_PF : u64 = 68719476736 ; pub const X86_EFLAGS_TEST_CF : u64 = 137438953472 ; pub const X86_EFLAGS_TEST_NT : u64 = 274877906944 ; pub const X86_EFLAGS_TEST_DF : u64 = 549755813888 ; pub const X86_EFLAGS_UNDEFINED_OF : u64 = 1099511627776 ; pub const X86_EFLAGS_UNDEFINED_SF : u64 = 2199023255552 ; pub const X86_EFLAGS_UNDEFINED_ZF : u64 = 4398046511104 ; pub const X86_EFLAGS_UNDEFINED_PF : u64 = 8796093022208 ; pub const X86_EFLAGS_UNDEFINED_AF : u64 = 17592186044416 ; pub const X86_EFLAGS_UNDEFINED_CF : u64 = 35184372088832 ; pub const X86_EFLAGS_RESET_RF : u64 = 70368744177664 ; pub const X86_EFLAGS_TEST_RF : u64 = 140737488355328 ; pub const X86_EFLAGS_TEST_IF : u64 = 281474976710656 ; pub const X86_EFLAGS_TEST_TF : u64 = 562949953421312 ; pub const X86_EFLAGS_TEST_AF : u64 = 1125899906842624 ; pub const X86_EFLAGS_RESET_ZF : u64 = 2251799813685248 ; pub const X86_EFLAGS_SET_OF : u64 = 4503599627370496 ; pub const X86_EFLAGS_SET_SF : u64 = 9007199254740992 ; pub const X86_EFLAGS_SET_ZF : u64 = 18014398509481984 ; pub const X86_EFLAGS_SET_AF : u64 = 36028797018963968 ; pub const X86_EFLAGS_SET_PF : u64 = 72057594037927936 ; pub const X86_EFLAGS_RESET_0F : u64 = 144115188075855872 ; pub const X86_EFLAGS_RESET_AC : u64 = 288230376151711744 ; pub const X86_FPU_FLAGS_MODIFY_C0 : u32 = 1 ; pub const X86_FPU_FLAGS_MODIFY_C1 : u32 = 2 ; pub const X86_FPU_FLAGS_MODIFY_C2 : u32 = 4 ; pub const X86_FPU_FLAGS_MODIFY_C3 : u32 = 8 ; pub const X86_FPU_FLAGS_RESET_C0 : u32 = 16 ; pub const X86_FPU_FLAGS_RESET_C1 : u32 = 32 ; pub const X86_FPU_FLAGS_RESET_C2 : u32 = 64 ; pub const X86_FPU_FLAGS_RESET_C3 : u32 = 128 ; pub const X86_FPU_FLAGS_SET_C0 : u32 = 256 ; pub const X86_FPU_FLAGS_SET_C1 : u32 = 512 ; pub const X86_FPU_FLAGS_SET_C2 : u32 = 1024 ; pub const X86_FPU_FLAGS_SET_C3 : u32 = 2048 ; pub const X86_FPU_FLAGS_UNDEFINED_C0 : u32 = 4096 ; pub const X86_FPU_FLAGS_UNDEFINED_C1 : u32 = 8192 ; pub const X86_FPU_FLAGS_UNDEFINED_C2 : u32 = 16384 ; pub const X86_FPU_FLAGS_UNDEFINED_C3 : u32 = 32768 ; pub const X86_FPU_FLAGS_TEST_C0 : u32 = 65536 ; pub const X86_FPU_FLAGS_TEST_C1 : u32 = 131072 ; pub const X86_FPU_FLAGS_TEST_C2 : u32 = 262144 ; pub const X86_FPU_FLAGS_TEST_C3 : u32 = 524288 ; pub const M680X_OPERAND_COUNT : u32 = 9 ; pub const M680X_OFFSET_NONE : u32 = 0 ; pub const M680X_OFFSET_BITS_5 : u32 = 5 ; pub const M680X_OFFSET_BITS_8 : u32 = 8 ; pub const M680X_OFFSET_BITS_9 : u32 = 9 ; pub const M680X_OFFSET_BITS_16 : u32 = 16 ; pub const M680X_IDX_INDIRECT : u32 = 1 ; pub const M680X_IDX_NO_COMMA : u32 = 2 ; pub const M680X_IDX_POST_INC_DEC : u32 = 4 ; pub const M680X_FIRST_OP_IN_MNEM : u32 = 1 ; pub const M680X_SECOND_OP_IN_MNEM : u32 = 2 ; pub const TRICORE_OP_COUNT : u32 = 8 ; pub const MAX_IMPL_W_REGS : u32 = 20 ; pub const MAX_IMPL_R_REGS : u32 = 20 ; pub const MAX_NUM_GROUPS : u32 = 8 ; pub type __gnuc_va_list = __builtin_va_list ; pub type va_list = __builtin_va_list ; pub type wchar_t = :: std :: os :: raw :: c_int ; pub type __cfloat128 = __BindgenComplex < u128 > ; pub type _Float128 = u128 ; pub type _Float32 = f32 ; pub type _Float64 = f64 ; pub type _Float32x = f64 ; pub type _Float64x = u128 ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct div_t { pub quot : :: std :: os :: raw :: c_int , pub rem : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of div_t"] [:: std :: mem :: size_of :: < div_t > () - 8usize] ; ["Alignment of div_t"] [:: std :: mem :: align_of :: < div_t > () - 4usize] ; ["Offset of field: div_t::quot"] [:: std :: mem :: offset_of ! (div_t , quot) - 0usize] ; ["Offset of field: div_t::rem"] [:: std :: mem :: offset_of ! (div_t , rem) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ldiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ldiv_t"] [:: std :: mem :: size_of :: < ldiv_t > () - 16usize] ; ["Alignment of ldiv_t"] [:: std :: mem :: align_of :: < ldiv_t > () - 8usize] ; ["Offset of field: ldiv_t::quot"] [:: std :: mem :: offset_of ! (ldiv_t , quot) - 0usize] ; ["Offset of field: ldiv_t::rem"] [:: std :: mem :: offset_of ! (ldiv_t , rem) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct lldiv_t { pub quot : :: std :: os :: raw :: c_longlong , pub rem : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of lldiv_t"] [:: std :: mem :: size_of :: < lldiv_t > () - 16usize] ; ["Alignment of lldiv_t"] [:: std :: mem :: align_of :: < lldiv_t > () - 8usize] ; ["Offset of field: lldiv_t::quot"] [:: std :: mem :: offset_of ! (lldiv_t , quot) - 0usize] ; ["Offset of field: lldiv_t::rem"] [:: std :: mem :: offset_of ! (lldiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn __ctype_get_mb_cur_max () -> usize ; } unsafe extern "C" { pub fn atof (__nptr : * const :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn atoi (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn atol (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn atoll (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtod (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn strtof (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f32 ; } unsafe extern "C" { pub fn strtold (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> u128 ; } unsafe extern "C" { pub fn strtol (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn strtoul (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn strtoq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtouq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn strtoll (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtoull (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn l64a (__n : :: std :: os :: raw :: c_long) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn a64l (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } pub type __u_char = :: std :: os :: raw :: c_uchar ; pub type __u_short = :: std :: os :: raw :: c_ushort ; pub type __u_int = :: std :: os :: raw :: c_uint ; pub type __u_long = :: std :: os :: raw :: c_ulong ; pub type __int8_t = :: std :: os :: raw :: c_schar ; pub type __uint8_t = :: std :: os :: raw :: c_uchar ; pub type __int16_t = :: std :: os :: raw :: c_short ; pub type __uint16_t = :: std :: os :: raw :: c_ushort ; pub type __int32_t = :: std :: os :: raw :: c_int ; pub type __uint32_t = :: std :: os :: raw :: c_uint ; pub type __int64_t = :: std :: os :: raw :: c_long ; pub type __uint64_t = :: std :: os :: raw :: c_ulong ; pub type __int_least8_t = __int8_t ; pub type __uint_least8_t = __uint8_t ; pub type __int_least16_t = __int16_t ; pub type __uint_least16_t = __uint16_t ; pub type __int_least32_t = __int32_t ; pub type __uint_least32_t = __uint32_t ; pub type __int_least64_t = __int64_t ; pub type __uint_least64_t = __uint64_t ; pub type __quad_t = :: std :: os :: raw :: c_long ; pub type __u_quad_t = :: std :: os :: raw :: c_ulong ; pub type __intmax_t = :: std :: os :: raw :: c_long ; pub type __uintmax_t = :: std :: os :: raw :: c_ulong ; pub type __dev_t = :: std :: os :: raw :: c_ulong ; pub type __uid_t = :: std :: os :: raw :: c_uint ; pub type __gid_t = :: std :: os :: raw :: c_uint ; pub type __ino_t = :: std :: os :: raw :: c_ulong ; pub type __ino64_t = :: std :: os :: raw :: c_ulong ; pub type __mode_t = :: std :: os :: raw :: c_uint ; pub type __nlink_t = :: std :: os :: raw :: c_ulong ; pub type __off_t = :: std :: os :: raw :: c_long ; pub type __off64_t = :: std :: os :: raw :: c_long ; pub type __pid_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __fsid_t { pub __val : [:: std :: os :: raw :: c_int ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __fsid_t"] [:: std :: mem :: size_of :: < __fsid_t > () - 8usize] ; ["Alignment of __fsid_t"] [:: std :: mem :: align_of :: < __fsid_t > () - 4usize] ; ["Offset of field: __fsid_t::__val"] [:: std :: mem :: offset_of ! (__fsid_t , __val) - 0usize] ; } ; pub type __clock_t = :: std :: os :: raw :: c_long ; pub type __rlim_t = :: std :: os :: raw :: c_ulong ; pub type __rlim64_t = :: std :: os :: raw :: c_ulong ; pub type __id_t = :: std :: os :: raw :: c_uint ; pub type __time_t = :: std :: os :: raw :: c_long ; pub type __useconds_t = :: std :: os :: raw :: c_uint ; pub type __suseconds_t = :: std :: os :: raw :: c_long ; pub type __suseconds64_t = :: std :: os :: raw :: c_long ; pub type __daddr_t = :: std :: os :: raw :: c_int ; pub type __key_t = :: std :: os :: raw :: c_int ; pub type __clockid_t = :: std :: os :: raw :: c_int ; pub type __timer_t = * mut :: std :: os :: raw :: c_void ; pub type __blksize_t = :: std :: os :: raw :: c_long ; pub type __blkcnt_t = :: std :: os :: raw :: c_long ; pub type __blkcnt64_t = :: std :: os :: raw :: c_long ; pub type __fsblkcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsblkcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsword_t = :: std :: os :: raw :: c_long ; pub type __ssize_t = :: std :: os :: raw :: c_long ; pub type __syscall_slong_t = :: std :: os :: raw :: c_long ; pub type __syscall_ulong_t = :: std :: os :: raw :: c_ulong ; pub type __loff_t = __off64_t ; pub type __caddr_t = * mut :: std :: os :: raw :: c_char ; pub type __intptr_t = :: std :: os :: raw :: c_long ; pub type __socklen_t = :: std :: os :: raw :: c_uint ; pub type __sig_atomic_t = :: std :: os :: raw :: c_int ; pub type u_char = __u_char ; pub type u_short = __u_short ; pub type u_int = __u_int ; pub type u_long = __u_long ; pub type quad_t = __quad_t ; pub type u_quad_t = __u_quad_t ; pub type fsid_t = __fsid_t ; pub type loff_t = __loff_t ; pub type ino_t = __ino_t ; pub type dev_t = __dev_t ; pub type gid_t = __gid_t ; pub type mode_t = __mode_t ; pub type nlink_t = __nlink_t ; pub type uid_t = __uid_t ; pub type off_t = __off_t ; pub type pid_t = __pid_t ; pub type id_t = __id_t ; pub type daddr_t = __daddr_t ; pub type caddr_t = __caddr_t ; pub type key_t = __key_t ; pub type clock_t = __clock_t ; pub type clockid_t = __clockid_t ; pub type time_t = __time_t ; pub type timer_t = __timer_t ; pub type ulong = :: std :: os :: raw :: c_ulong ; pub type ushort = :: std :: os :: raw :: c_ushort ; pub type uint = :: std :: os :: raw :: c_uint ; pub type u_int8_t = __uint8_t ; pub type u_int16_t = __uint16_t ; pub type u_int32_t = __uint32_t ; pub type u_int64_t = __uint64_t ; pub type register_t = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __sigset_t { pub __val : [:: std :: os :: raw :: c_ulong ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __sigset_t"] [:: std :: mem :: size_of :: < __sigset_t > () - 128usize] ; ["Alignment of __sigset_t"] [:: std :: mem :: align_of :: < __sigset_t > () - 8usize] ; ["Offset of field: __sigset_t::__val"] [:: std :: mem :: offset_of ! (__sigset_t , __val) - 0usize] ; } ; pub type sigset_t = __sigset_t ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timeval { pub tv_sec : __time_t , pub tv_usec : __suseconds_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timeval"] [:: std :: mem :: size_of :: < timeval > () - 16usize] ; ["Alignment of timeval"] [:: std :: mem :: align_of :: < timeval > () - 8usize] ; ["Offset of field: timeval::tv_sec"] [:: std :: mem :: offset_of ! (timeval , tv_sec) - 0usize] ; ["Offset of field: timeval::tv_usec"] [:: std :: mem :: offset_of ! (timeval , tv_usec) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timespec { pub tv_sec : __time_t , pub tv_nsec : __syscall_slong_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timespec"] [:: std :: mem :: size_of :: < timespec > () - 16usize] ; ["Alignment of timespec"] [:: std :: mem :: align_of :: < timespec > () - 8usize] ; ["Offset of field: timespec::tv_sec"] [:: std :: mem :: offset_of ! (timespec , tv_sec) - 0usize] ; ["Offset of field: timespec::tv_nsec"] [:: std :: mem :: offset_of ! (timespec , tv_nsec) - 8usize] ; } ; pub type suseconds_t = __suseconds_t ; pub type __fd_mask = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct fd_set { pub __fds_bits : [__fd_mask ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of fd_set"] [:: std :: mem :: size_of :: < fd_set > () - 128usize] ; ["Alignment of fd_set"] [:: std :: mem :: align_of :: < fd_set > () - 8usize] ; ["Offset of field: fd_set::__fds_bits"] [:: std :: mem :: offset_of ! (fd_set , __fds_bits) - 0usize] ; } ; pub type fd_mask = __fd_mask ; unsafe extern "C" { pub fn select (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * mut timeval) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pselect (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * const timespec , __sigmask : * const __sigset_t) -> :: std :: os :: raw :: c_int ; } pub type blksize_t = __blksize_t ; pub type blkcnt_t = __blkcnt_t ; pub type fsblkcnt_t = __fsblkcnt_t ; pub type fsfilcnt_t = __fsfilcnt_t ; # [repr (C)] # [derive (Copy , Clone)] pub union __atomic_wide_counter { pub __value64 : :: std :: os :: raw :: c_ulonglong , pub __value32 : __atomic_wide_counter__bindgen_ty_1 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __atomic_wide_counter__bindgen_ty_1 { pub __low : :: std :: os :: raw :: c_uint , pub __high : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: size_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 8usize] ; ["Alignment of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: align_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__low"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __low) - 0usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__high"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __high) - 4usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter"] [:: std :: mem :: size_of :: < __atomic_wide_counter > () - 8usize] ; ["Alignment of __atomic_wide_counter"] [:: std :: mem :: align_of :: < __atomic_wide_counter > () - 8usize] ; ["Offset of field: __atomic_wide_counter::__value64"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value64) - 0usize] ; ["Offset of field: __atomic_wide_counter::__value32"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value32) - 0usize] ; } ; impl :: std :: fmt :: Debug for __atomic_wide_counter { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__atomic_wide_counter {{ union }}") } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_list { pub __prev : * mut __pthread_internal_list , pub __next : * mut __pthread_internal_list , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_list"] [:: std :: mem :: size_of :: < __pthread_internal_list > () - 16usize] ; ["Alignment of __pthread_internal_list"] [:: std :: mem :: align_of :: < __pthread_internal_list > () - 8usize] ; ["Offset of field: __pthread_internal_list::__prev"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __prev) - 0usize] ; ["Offset of field: __pthread_internal_list::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __next) - 8usize] ; } ; pub type __pthread_list_t = __pthread_internal_list ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_slist { pub __next : * mut __pthread_internal_slist , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_slist"] [:: std :: mem :: size_of :: < __pthread_internal_slist > () - 8usize] ; ["Alignment of __pthread_internal_slist"] [:: std :: mem :: align_of :: < __pthread_internal_slist > () - 8usize] ; ["Offset of field: __pthread_internal_slist::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_slist , __next) - 0usize] ; } ; pub type __pthread_slist_t = __pthread_internal_slist ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_mutex_s { pub __lock : :: std :: os :: raw :: c_int , pub __count : :: std :: os :: raw :: c_uint , pub __owner : :: std :: os :: raw :: c_int , pub __nusers : :: std :: os :: raw :: c_uint , pub __kind : :: std :: os :: raw :: c_int , pub __spins : :: std :: os :: raw :: c_short , pub __unused : :: std :: os :: raw :: c_short , pub __list : __pthread_list_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_mutex_s"] [:: std :: mem :: size_of :: < __pthread_mutex_s > () - 40usize] ; ["Alignment of __pthread_mutex_s"] [:: std :: mem :: align_of :: < __pthread_mutex_s > () - 8usize] ; ["Offset of field: __pthread_mutex_s::__lock"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __lock) - 0usize] ; ["Offset of field: __pthread_mutex_s::__count"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __count) - 4usize] ; ["Offset of field: __pthread_mutex_s::__owner"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __owner) - 8usize] ; ["Offset of field: __pthread_mutex_s::__nusers"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __nusers) - 12usize] ; ["Offset of field: __pthread_mutex_s::__kind"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __kind) - 16usize] ; ["Offset of field: __pthread_mutex_s::__spins"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __spins) - 20usize] ; ["Offset of field: __pthread_mutex_s::__unused"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __unused) - 22usize] ; ["Offset of field: __pthread_mutex_s::__list"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __list) - 24usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_rwlock_arch_t { pub __readers : :: std :: os :: raw :: c_uint , pub __writers : :: std :: os :: raw :: c_uint , pub __wrphase_futex : :: std :: os :: raw :: c_uint , pub __writers_futex : :: std :: os :: raw :: c_uint , pub __pad3 : :: std :: os :: raw :: c_uint , pub __pad4 : :: std :: os :: raw :: c_uint , pub __cur_writer : :: std :: os :: raw :: c_int , pub __shared : :: std :: os :: raw :: c_int , pub __pad1 : :: std :: os :: raw :: c_ulong , pub __pad2 : :: std :: os :: raw :: c_ulong , pub __flags : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_rwlock_arch_t"] [:: std :: mem :: size_of :: < __pthread_rwlock_arch_t > () - 56usize] ; ["Alignment of __pthread_rwlock_arch_t"] [:: std :: mem :: align_of :: < __pthread_rwlock_arch_t > () - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__readers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __readers) - 0usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers) - 4usize] ; ["Offset of field: __pthread_rwlock_arch_t::__wrphase_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __wrphase_futex) - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers_futex) - 12usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad3"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad3) - 16usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad4"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad4) - 20usize] ; ["Offset of field: __pthread_rwlock_arch_t::__cur_writer"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __cur_writer) - 24usize] ; ["Offset of field: __pthread_rwlock_arch_t::__shared"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __shared) - 28usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad1"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad1) - 32usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad2"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad2) - 40usize] ; ["Offset of field: __pthread_rwlock_arch_t::__flags"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __flags) - 48usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct __pthread_cond_s { pub __wseq : __atomic_wide_counter , pub __g1_start : __atomic_wide_counter , pub __g_size : [:: std :: os :: raw :: c_uint ; 2usize] , pub __g1_orig_size : :: std :: os :: raw :: c_uint , pub __wrefs : :: std :: os :: raw :: c_uint , pub __g_signals : [:: std :: os :: raw :: c_uint ; 2usize] , pub __unused_initialized_1 : :: std :: os :: raw :: c_uint , pub __unused_initialized_2 : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_cond_s"] [:: std :: mem :: size_of :: < __pthread_cond_s > () - 48usize] ; ["Alignment of __pthread_cond_s"] [:: std :: mem :: align_of :: < __pthread_cond_s > () - 8usize] ; ["Offset of field: __pthread_cond_s::__wseq"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wseq) - 0usize] ; ["Offset of field: __pthread_cond_s::__g1_start"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_start) - 8usize] ; ["Offset of field: __pthread_cond_s::__g_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_size) - 16usize] ; ["Offset of field: __pthread_cond_s::__g1_orig_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_orig_size) - 24usize] ; ["Offset of field: __pthread_cond_s::__wrefs"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wrefs) - 28usize] ; ["Offset of field: __pthread_cond_s::__g_signals"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_signals) - 32usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_1"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_1) - 40usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_2"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_2) - 44usize] ; } ; impl :: std :: fmt :: Debug for __pthread_cond_s { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__pthread_cond_s {{ __wseq: {:?}, __g1_start: {:?}, __g_size: {:?}, __g1_orig_size: {:?}, __wrefs: {:?}, __g_signals: {:?}, __unused_initialized_1: {:?}, __unused_initialized_2: {:?} }}" , self . __wseq , self . __g1_start , self . __g_size , self . __g1_orig_size , self . __wrefs , self . __g_signals , self . __unused_initialized_1 , self . __unused_initialized_2) } } pub type __tss_t = :: std :: os :: raw :: c_uint ; pub type __thrd_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __once_flag { pub __data : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __once_flag"] [:: std :: mem :: size_of :: < __once_flag > () - 4usize] ; ["Alignment of __once_flag"] [:: std :: mem :: align_of :: < __once_flag > () - 4usize] ; ["Offset of field: __once_flag::__data"] [:: std :: mem :: offset_of ! (__once_flag , __data) - 0usize] ; } ; pub type pthread_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutexattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutexattr_t"] [:: std :: mem :: size_of :: < pthread_mutexattr_t > () - 4usize] ; ["Alignment of pthread_mutexattr_t"] [:: std :: mem :: align_of :: < pthread_mutexattr_t > () - 4usize] ; ["Offset of field: pthread_mutexattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __size) - 0usize] ; ["Offset of field: pthread_mutexattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutexattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutexattr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_condattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_condattr_t"] [:: std :: mem :: size_of :: < pthread_condattr_t > () - 4usize] ; ["Alignment of pthread_condattr_t"] [:: std :: mem :: align_of :: < pthread_condattr_t > () - 4usize] ; ["Offset of field: pthread_condattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __size) - 0usize] ; ["Offset of field: pthread_condattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_condattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_condattr_t {{ union }}") } } pub type pthread_key_t = :: std :: os :: raw :: c_uint ; pub type pthread_once_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_attr_t { pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_attr_t"] [:: std :: mem :: size_of :: < pthread_attr_t > () - 56usize] ; ["Alignment of pthread_attr_t"] [:: std :: mem :: align_of :: < pthread_attr_t > () - 8usize] ; ["Offset of field: pthread_attr_t::__size"] [:: std :: mem :: offset_of ! (pthread_attr_t , __size) - 0usize] ; ["Offset of field: pthread_attr_t::__align"] [:: std :: mem :: offset_of ! (pthread_attr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_attr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_attr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutex_t { pub __data : __pthread_mutex_s , pub __size : [:: std :: os :: raw :: c_char ; 40usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutex_t"] [:: std :: mem :: size_of :: < pthread_mutex_t > () - 40usize] ; ["Alignment of pthread_mutex_t"] [:: std :: mem :: align_of :: < pthread_mutex_t > () - 8usize] ; ["Offset of field: pthread_mutex_t::__data"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __data) - 0usize] ; ["Offset of field: pthread_mutex_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __size) - 0usize] ; ["Offset of field: pthread_mutex_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutex_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutex_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_cond_t { pub __data : __pthread_cond_s , pub __size : [:: std :: os :: raw :: c_char ; 48usize] , pub __align : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_cond_t"] [:: std :: mem :: size_of :: < pthread_cond_t > () - 48usize] ; ["Alignment of pthread_cond_t"] [:: std :: mem :: align_of :: < pthread_cond_t > () - 8usize] ; ["Offset of field: pthread_cond_t::__data"] [:: std :: mem :: offset_of ! (pthread_cond_t , __data) - 0usize] ; ["Offset of field: pthread_cond_t::__size"] [:: std :: mem :: offset_of ! (pthread_cond_t , __size) - 0usize] ; ["Offset of field: pthread_cond_t::__align"] [:: std :: mem :: offset_of ! (pthread_cond_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_cond_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_cond_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlock_t { pub __data : __pthread_rwlock_arch_t , pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlock_t"] [:: std :: mem :: size_of :: < pthread_rwlock_t > () - 56usize] ; ["Alignment of pthread_rwlock_t"] [:: std :: mem :: align_of :: < pthread_rwlock_t > () - 8usize] ; ["Offset of field: pthread_rwlock_t::__data"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __data) - 0usize] ; ["Offset of field: pthread_rwlock_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __size) - 0usize] ; ["Offset of field: pthread_rwlock_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlock_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlock_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlockattr_t { pub __size : [:: std :: os :: raw :: c_char ; 8usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlockattr_t"] [:: std :: mem :: size_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Alignment of pthread_rwlockattr_t"] [:: std :: mem :: align_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Offset of field: pthread_rwlockattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __size) - 0usize] ; ["Offset of field: pthread_rwlockattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlockattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlockattr_t {{ union }}") } } pub type pthread_spinlock_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrier_t { pub __size : [:: std :: os :: raw :: c_char ; 32usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrier_t"] [:: std :: mem :: size_of :: < pthread_barrier_t > () - 32usize] ; ["Alignment of pthread_barrier_t"] [:: std :: mem :: align_of :: < pthread_barrier_t > () - 8usize] ; ["Offset of field: pthread_barrier_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __size) - 0usize] ; ["Offset of field: pthread_barrier_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrier_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrier_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrierattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrierattr_t"] [:: std :: mem :: size_of :: < pthread_barrierattr_t > () - 4usize] ; ["Alignment of pthread_barrierattr_t"] [:: std :: mem :: align_of :: < pthread_barrierattr_t > () - 4usize] ; ["Offset of field: pthread_barrierattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __size) - 0usize] ; ["Offset of field: pthread_barrierattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrierattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrierattr_t {{ union }}") } } unsafe extern "C" { pub fn random () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srandom (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn initstate (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn setstate (__statebuf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct random_data { pub fptr : * mut i32 , pub rptr : * mut i32 , pub state : * mut i32 , pub rand_type : :: std :: os :: raw :: c_int , pub rand_deg : :: std :: os :: raw :: c_int , pub rand_sep : :: std :: os :: raw :: c_int , pub end_ptr : * mut i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of random_data"] [:: std :: mem :: size_of :: < random_data > () - 48usize] ; ["Alignment of random_data"] [:: std :: mem :: align_of :: < random_data > () - 8usize] ; ["Offset of field: random_data::fptr"] [:: std :: mem :: offset_of ! (random_data , fptr) - 0usize] ; ["Offset of field: random_data::rptr"] [:: std :: mem :: offset_of ! (random_data , rptr) - 8usize] ; ["Offset of field: random_data::state"] [:: std :: mem :: offset_of ! (random_data , state) - 16usize] ; ["Offset of field: random_data::rand_type"] [:: std :: mem :: offset_of ! (random_data , rand_type) - 24usize] ; ["Offset of field: random_data::rand_deg"] [:: std :: mem :: offset_of ! (random_data , rand_deg) - 28usize] ; ["Offset of field: random_data::rand_sep"] [:: std :: mem :: offset_of ! (random_data , rand_sep) - 32usize] ; ["Offset of field: random_data::end_ptr"] [:: std :: mem :: offset_of ! (random_data , end_ptr) - 40usize] ; } ; unsafe extern "C" { pub fn random_r (__buf : * mut random_data , __result : * mut i32) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srandom_r (__seed : :: std :: os :: raw :: c_uint , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn initstate_r (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setstate_r (__statebuf : * mut :: std :: os :: raw :: c_char , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rand () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn rand_r (__seed : * mut :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn drand48 () -> f64 ; } unsafe extern "C" { pub fn erand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> f64 ; } unsafe extern "C" { pub fn lrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn nrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn mrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn jrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srand48 (__seedval : :: std :: os :: raw :: c_long) ; } unsafe extern "C" { pub fn seed48 (__seed16v : * mut :: std :: os :: raw :: c_ushort) -> * mut :: std :: os :: raw :: c_ushort ; } unsafe extern "C" { pub fn lcong48 (__param : * mut :: std :: os :: raw :: c_ushort) ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct drand48_data { pub __x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __old_x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __c : :: std :: os :: raw :: c_ushort , pub __init : :: std :: os :: raw :: c_ushort , pub __a : :: std :: os :: raw :: c_ulonglong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of drand48_data"] [:: std :: mem :: size_of :: < drand48_data > () - 24usize] ; ["Alignment of drand48_data"] [:: std :: mem :: align_of :: < drand48_data > () - 8usize] ; ["Offset of field: drand48_data::__x"] [:: std :: mem :: offset_of ! (drand48_data , __x) - 0usize] ; ["Offset of field: drand48_data::__old_x"] [:: std :: mem :: offset_of ! (drand48_data , __old_x) - 6usize] ; ["Offset of field: drand48_data::__c"] [:: std :: mem :: offset_of ! (drand48_data , __c) - 12usize] ; ["Offset of field: drand48_data::__init"] [:: std :: mem :: offset_of ! (drand48_data , __init) - 14usize] ; ["Offset of field: drand48_data::__a"] [:: std :: mem :: offset_of ! (drand48_data , __a) - 16usize] ; } ; unsafe extern "C" { pub fn drand48_r (__buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn erand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn nrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn jrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand48_r (__seedval : :: std :: os :: raw :: c_long , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn seed48_r (__seed16v : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lcong48_r (__param : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn arc4random () -> __uint32_t ; } unsafe extern "C" { pub fn arc4random_buf (__buf : * mut :: std :: os :: raw :: c_void , __size : usize) ; } unsafe extern "C" { pub fn arc4random_uniform (__upper_bound : __uint32_t) -> __uint32_t ; } unsafe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn calloc (__nmemb : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn free (__ptr : * mut :: std :: os :: raw :: c_void) ; } unsafe extern "C" { pub fn reallocarray (__ptr : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn alloca (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn valloc (__size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn posix_memalign (__memptr : * mut * mut :: std :: os :: raw :: c_void , __alignment : usize , __size : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn aligned_alloc (__alignment : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn abort () -> ! ; } unsafe extern "C" { pub fn atexit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn at_quick_exit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn on_exit (__func : :: std :: option :: Option < unsafe extern "C" fn (__status : :: std :: os :: raw :: c_int , __arg : * mut :: std :: os :: raw :: c_void) > , __arg : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn quick_exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn _Exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn getenv (__name : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn putenv (__string : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setenv (__name : * const :: std :: os :: raw :: c_char , __value : * const :: std :: os :: raw :: c_char , __replace : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn unsetenv (__name : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearenv () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mktemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn mkstemp (__template : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkstemps (__template : * mut :: std :: os :: raw :: c_char , __suffixlen : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkdtemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn system (__command : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn realpath (__name : * const :: std :: os :: raw :: c_char , __resolved : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } pub type __compar_fn_t = :: std :: option :: Option < unsafe extern "C" fn (arg1 : * const :: std :: os :: raw :: c_void , arg2 : * const :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; unsafe extern "C" { pub fn bsearch (__key : * const :: std :: os :: raw :: c_void , __base : * const :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn qsort (__base : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) ; } unsafe extern "C" { pub fn abs (__x : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn labs (__x : :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn llabs (__x : :: std :: os :: raw :: c_longlong) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn div (__numer : :: std :: os :: raw :: c_int , __denom : :: std :: os :: raw :: c_int) -> div_t ; } unsafe extern "C" { pub fn ldiv (__numer : :: std :: os :: raw :: c_long , __denom : :: std :: os :: raw :: c_long) -> ldiv_t ; } unsafe extern "C" { pub fn lldiv (__numer : :: std :: os :: raw :: c_longlong , __denom : :: std :: os :: raw :: c_longlong) -> lldiv_t ; } unsafe extern "C" { pub fn ecvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn gcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qecvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qfcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qgcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn ecvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fcvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qecvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qfcvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mblen (__s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbtowc (__pwc : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn wctomb (__s : * mut :: std :: os :: raw :: c_char , __wchar : wchar_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbstowcs (__pwcs : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> usize ; } unsafe extern "C" { pub fn wcstombs (__s : * mut :: std :: os :: raw :: c_char , __pwcs : * const wchar_t , __n : usize) -> usize ; } unsafe extern "C" { pub fn rpmatch (__response : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getsubopt (__optionp : * mut * mut :: std :: os :: raw :: c_char , __tokens : * const * mut :: std :: os :: raw :: c_char , __valuep : * mut * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getloadavg (__loadavg : * mut f64 , __nelem : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } # [repr (C)] # [derive (Copy , Clone)] pub struct __mbstate_t { pub __count : :: std :: os :: raw :: c_int , pub __value : __mbstate_t__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union __mbstate_t__bindgen_ty_1 { pub __wch : :: std :: os :: raw :: c_uint , pub __wchb : [:: std :: os :: raw :: c_char ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: size_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Alignment of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: align_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wch"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wch) - 0usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wchb"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wchb) - 0usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t"] [:: std :: mem :: size_of :: < __mbstate_t > () - 8usize] ; ["Alignment of __mbstate_t"] [:: std :: mem :: align_of :: < __mbstate_t > () - 4usize] ; ["Offset of field: __mbstate_t::__count"] [:: std :: mem :: offset_of ! (__mbstate_t , __count) - 0usize] ; ["Offset of field: __mbstate_t::__value"] [:: std :: mem :: offset_of ! (__mbstate_t , __value) - 4usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t {{ __count: {:?}, __value: {:?} }}" , self . __count , self . __value) } } # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos_t { pub __pos : __off_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos_t"] [:: std :: mem :: size_of :: < _G_fpos_t > () - 16usize] ; ["Alignment of _G_fpos_t"] [:: std :: mem :: align_of :: < _G_fpos_t > () - 8usize] ; ["Offset of field: _G_fpos_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos_t , __pos) - 0usize] ; ["Offset of field: _G_fpos_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos_t = _G_fpos_t ; # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos64_t { pub __pos : __off64_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos64_t"] [:: std :: mem :: size_of :: < _G_fpos64_t > () - 16usize] ; ["Alignment of _G_fpos64_t"] [:: std :: mem :: align_of :: < _G_fpos64_t > () - 8usize] ; ["Offset of field: _G_fpos64_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __pos) - 0usize] ; ["Offset of field: _G_fpos64_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos64_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos64_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos64_t = _G_fpos64_t ; pub type __FILE = _IO_FILE ; pub type FILE = _IO_FILE ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_marker { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_codecvt { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_wide_data { _unused : [u8 ; 0] , } pub type _IO_lock_t = :: std :: os :: raw :: c_void ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_FILE { pub _flags : :: std :: os :: raw :: c_int , pub _IO_read_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_read_end : * mut :: std :: os :: raw :: c_char , pub _IO_read_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_write_end : * mut :: std :: os :: raw :: c_char , pub _IO_buf_base : * mut :: std :: os :: raw :: c_char , pub _IO_buf_end : * mut :: std :: os :: raw :: c_char , pub _IO_save_base : * mut :: std :: os :: raw :: c_char , pub _IO_backup_base : * mut :: std :: os :: raw :: c_char , pub _IO_save_end : * mut :: std :: os :: raw :: c_char , pub _markers : * mut _IO_marker , pub _chain : * mut _IO_FILE , pub _fileno : :: std :: os :: raw :: c_int , pub _bitfield_align_1 : [u32 ; 0] , pub _bitfield_1 : __BindgenBitfieldUnit < [u8 ; 3usize] > , pub _short_backupbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _old_offset : __off_t , pub _cur_column : :: std :: os :: raw :: c_ushort , pub _vtable_offset : :: std :: os :: raw :: c_schar , pub _shortbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _lock : * mut _IO_lock_t , pub _offset : __off64_t , pub _codecvt : * mut _IO_codecvt , pub _wide_data : * mut _IO_wide_data , pub _freeres_list : * mut _IO_FILE , pub _freeres_buf : * mut :: std :: os :: raw :: c_void , pub _prevchain : * mut * mut _IO_FILE , pub _mode : :: std :: os :: raw :: c_int , pub _unused3 : :: std :: os :: raw :: c_int , pub _total_written : __uint64_t , pub _unused2 : [:: std :: os :: raw :: c_char ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_FILE"] [:: std :: mem :: size_of :: < _IO_FILE > () - 216usize] ; ["Alignment of _IO_FILE"] [:: std :: mem :: align_of :: < _IO_FILE > () - 8usize] ; ["Offset of field: _IO_FILE::_flags"] [:: std :: mem :: offset_of ! (_IO_FILE , _flags) - 0usize] ; ["Offset of field: _IO_FILE::_IO_read_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_ptr) - 8usize] ; ["Offset of field: _IO_FILE::_IO_read_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_end) - 16usize] ; ["Offset of field: _IO_FILE::_IO_read_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_base) - 24usize] ; ["Offset of field: _IO_FILE::_IO_write_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_base) - 32usize] ; ["Offset of field: _IO_FILE::_IO_write_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_ptr) - 40usize] ; ["Offset of field: _IO_FILE::_IO_write_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_end) - 48usize] ; ["Offset of field: _IO_FILE::_IO_buf_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_base) - 56usize] ; ["Offset of field: _IO_FILE::_IO_buf_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_end) - 64usize] ; ["Offset of field: _IO_FILE::_IO_save_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_base) - 72usize] ; ["Offset of field: _IO_FILE::_IO_backup_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_backup_base) - 80usize] ; ["Offset of field: _IO_FILE::_IO_save_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_end) - 88usize] ; ["Offset of field: _IO_FILE::_markers"] [:: std :: mem :: offset_of ! (_IO_FILE , _markers) - 96usize] ; ["Offset of field: _IO_FILE::_chain"] [:: std :: mem :: offset_of ! (_IO_FILE , _chain) - 104usize] ; ["Offset of field: _IO_FILE::_fileno"] [:: std :: mem :: offset_of ! (_IO_FILE , _fileno) - 112usize] ; ["Offset of field: _IO_FILE::_short_backupbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _short_backupbuf) - 119usize] ; ["Offset of field: _IO_FILE::_old_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _old_offset) - 120usize] ; ["Offset of field: _IO_FILE::_cur_column"] [:: std :: mem :: offset_of ! (_IO_FILE , _cur_column) - 128usize] ; ["Offset of field: _IO_FILE::_vtable_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _vtable_offset) - 130usize] ; ["Offset of field: _IO_FILE::_shortbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _shortbuf) - 131usize] ; ["Offset of field: _IO_FILE::_lock"] [:: std :: mem :: offset_of ! (_IO_FILE , _lock) - 136usize] ; ["Offset of field: _IO_FILE::_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _offset) - 144usize] ; ["Offset of field: _IO_FILE::_codecvt"] [:: std :: mem :: offset_of ! (_IO_FILE , _codecvt) - 152usize] ; ["Offset of field: _IO_FILE::_wide_data"] [:: std :: mem :: offset_of ! (_IO_FILE , _wide_data) - 160usize] ; ["Offset of field: _IO_FILE::_freeres_list"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_list) - 168usize] ; ["Offset of field: _IO_FILE::_freeres_buf"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_buf) - 176usize] ; ["Offset of field: _IO_FILE::_prevchain"] [:: std :: mem :: offset_of ! (_IO_FILE , _prevchain) - 184usize] ; ["Offset of field: _IO_FILE::_mode"] [:: std :: mem :: offset_of ! (_IO_FILE , _mode) - 192usize] ; ["Offset of field: _IO_FILE::_unused3"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused3) - 196usize] ; ["Offset of field: _IO_FILE::_total_written"] [:: std :: mem :: offset_of ! (_IO_FILE , _total_written) - 200usize] ; ["Offset of field: _IO_FILE::_unused2"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused2) - 208usize] ; } ; impl _IO_FILE { # [inline] pub fn _flags2 (& self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set__flags2 (& mut self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; self . _bitfield_1 . set (0usize , 24u8 , val as u64) } } # [inline] pub unsafe fn _flags2_raw (this : * const Self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } } # [inline] pub unsafe fn set__flags2_raw (this : * mut Self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_set (:: std :: ptr :: addr_of_mut ! ((* this) . _bitfield_1) , 0usize , 24u8 , val as u64 ,) } } # [inline] pub fn new_bitfield_1 (_flags2 : :: std :: os :: raw :: c_int) -> __BindgenBitfieldUnit < [u8 ; 3usize] > { let mut __bindgen_bitfield_unit : __BindgenBitfieldUnit < [u8 ; 3usize] > = Default :: default () ; __bindgen_bitfield_unit . set (0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_unit } } pub type cookie_read_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * mut :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_write_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * const :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_seek_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __pos : * mut __off64_t , __w : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int > ; pub type cookie_close_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_cookie_io_functions_t { pub read : cookie_read_function_t , pub write : cookie_write_function_t , pub seek : cookie_seek_function_t , pub close : cookie_close_function_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_cookie_io_functions_t"] [:: std :: mem :: size_of :: < _IO_cookie_io_functions_t > () - 32usize] ; ["Alignment of _IO_cookie_io_functions_t"] [:: std :: mem :: align_of :: < _IO_cookie_io_functions_t > () - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::read"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , read) - 0usize] ; ["Offset of field: _IO_cookie_io_functions_t::write"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , write) - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::seek"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , seek) - 16usize] ; ["Offset of field: _IO_cookie_io_functions_t::close"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , close) - 24usize] ; } ; pub type cookie_io_functions_t = _IO_cookie_io_functions_t ; pub type fpos_t = __fpos_t ; unsafe extern "C" { pub static mut stdin : * mut FILE ; } unsafe extern "C" { pub static mut stdout : * mut FILE ; } unsafe extern "C" { pub static mut stderr : * mut FILE ; } unsafe extern "C" { pub fn remove (__filename : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rename (__old : * const :: std :: os :: raw :: c_char , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn renameat (__oldfd : :: std :: os :: raw :: c_int , __old : * const :: std :: os :: raw :: c_char , __newfd : :: std :: os :: raw :: c_int , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn tmpfile () -> * mut FILE ; } unsafe extern "C" { pub fn tmpnam (arg1 : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tmpnam_r (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tempnam (__dir : * const :: std :: os :: raw :: c_char , __pfx : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fflush (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fflush_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn freopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> * mut FILE ; } unsafe extern "C" { pub fn fdopen (__fd : :: std :: os :: raw :: c_int , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn fopencookie (__magic_cookie : * mut :: std :: os :: raw :: c_void , __modes : * const :: std :: os :: raw :: c_char , __io_funcs : cookie_io_functions_t) -> * mut FILE ; } unsafe extern "C" { pub fn fmemopen (__s : * mut :: std :: os :: raw :: c_void , __len : usize , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn open_memstream (__bufloc : * mut * mut :: std :: os :: raw :: c_char , __sizeloc : * mut usize) -> * mut FILE ; } unsafe extern "C" { pub fn setbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn setvbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __modes : :: std :: os :: raw :: c_int , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setbuffer (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __size : usize) ; } unsafe extern "C" { pub fn setlinebuf (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fprintf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn printf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfprintf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vprintf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn snprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsnprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vasprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __f : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vdprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn dprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fscanf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn scanf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_fscanf"] pub fn fscanf1 (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_scanf"] pub fn scanf1 (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_sscanf"] pub fn sscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfscanf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vscanf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vfscanf"] pub fn vfscanf1 (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vscanf"] pub fn vscanf1 (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vsscanf"] pub fn vsscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar_unlocked () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar_unlocked (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getw (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putw (__w : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgets (__s : * mut :: std :: os :: raw :: c_char , __n : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn __getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getline (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn fputs (__s : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn puts (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ungetc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fread (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __stream : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fwrite (__ptr : * const :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __s : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fread_unlocked (__ptr : * mut :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fwrite_unlocked (__ptr : * const :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fseek (__stream : * mut FILE , __off : :: std :: os :: raw :: c_long , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftell (__stream : * mut FILE) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn rewind (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fseeko (__stream : * mut FILE , __off : __off_t , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftello (__stream : * mut FILE) -> __off_t ; } unsafe extern "C" { pub fn fgetpos (__stream : * mut FILE , __pos : * mut fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fsetpos (__stream : * mut FILE , __pos : * const fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr_unlocked (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn perror (__s : * const :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn fileno (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fileno_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn popen (__command : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn ctermid (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn flockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn ftrylockfile (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn funlockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn __uflow (arg1 : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __overflow (arg1 : * mut FILE , arg2 : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } pub type int_least8_t = __int_least8_t ; pub type int_least16_t = __int_least16_t ; pub type int_least32_t = __int_least32_t ; pub type int_least64_t = __int_least64_t ; pub type uint_least8_t = __uint_least8_t ; pub type uint_least16_t = __uint_least16_t ; pub type uint_least32_t = __uint_least32_t ; pub type uint_least64_t = __uint_least64_t ; pub type int_fast8_t = :: std :: os :: raw :: c_schar ; pub type int_fast16_t = :: std :: os :: raw :: c_long ; pub type int_fast32_t = :: std :: os :: raw :: c_long ; pub type int_fast64_t = :: std :: os :: raw :: c_long ; pub type uint_fast8_t = :: std :: os :: raw :: c_uchar ; pub type uint_fast16_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast32_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast64_t = :: std :: os :: raw :: c_ulong ; pub type intmax_t = __intmax_t ; pub type uintmax_t = __uintmax_t ; pub type __gwchar_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct imaxdiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of imaxdiv_t"] [:: std :: mem :: size_of :: < imaxdiv_t > () - 16usize] ; ["Alignment of imaxdiv_t"] [:: std :: mem :: align_of :: < imaxdiv_t > () - 8usize] ; ["Offset of field: imaxdiv_t::quot"] [:: std :: mem :: offset_of ! (imaxdiv_t , quot) - 0usize] ; ["Offset of field: imaxdiv_t::rem"] [:: std :: mem :: offset_of ! (imaxdiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn imaxabs (__n : intmax_t) -> intmax_t ; } unsafe extern "C" { pub fn imaxdiv (__numer : intmax_t , __denom : intmax_t) -> imaxdiv_t ; } unsafe extern "C" { pub fn strtoimax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn strtoumax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } unsafe extern "C" { pub fn wcstoimax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn wcstoumax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } pub type csh = usize ; # [repr (u32)] # [doc = " Architecture type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_arch { # [doc = "< ARM architecture (including Thumb, Thumb-2)"] CS_ARCH_ARM = 0 , # [doc = "< ARM-64, also called AArch64"] CS_ARCH_ARM64 = 1 , # [doc = "< Mips architecture"] CS_ARCH_MIPS = 2 , # [doc = "< X86 architecture (including x86 & x86-64)"] CS_ARCH_X86 = 3 , # [doc = "< PowerPC architecture"] CS_ARCH_PPC = 4 , # [doc = "< Sparc architecture"] CS_ARCH_SPARC = 5 , # [doc = "< SystemZ architecture"] CS_ARCH_SYSZ = 6 , # [doc = "< XCore architecture"] CS_ARCH_XCORE = 7 , # [doc = "< 68K architecture"] CS_ARCH_M68K = 8 , # [doc = "< TMS320C64x architecture"] CS_ARCH_TMS320C64X = 9 , # [doc = "< 680X architecture"] CS_ARCH_M680X = 10 , # [doc = "< Ethereum architecture"] CS_ARCH_EVM = 11 , # [doc = "< MOS65XX architecture (including MOS6502)"] CS_ARCH_MOS65XX = 12 , # [doc = "< WebAssembly architecture"] CS_ARCH_WASM = 13 , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] CS_ARCH_BPF = 14 , # [doc = "< RISCV architecture"] CS_ARCH_RISCV = 15 , # [doc = "< SH architecture"] CS_ARCH_SH = 16 , # [doc = "< TriCore architecture"] CS_ARCH_TRICORE = 17 , CS_ARCH_MAX = 18 , CS_ARCH_ALL = 65535 , } # [doc = "< little-endian mode (default mode)"] pub const cs_mode_CS_MODE_LITTLE_ENDIAN : cs_mode = 0 ; # [doc = "< 32-bit ARM"] pub const cs_mode_CS_MODE_ARM : cs_mode = 0 ; # [doc = "< 16-bit mode (X86)"] pub const cs_mode_CS_MODE_16 : cs_mode = 2 ; # [doc = "< 32-bit mode (X86)"] pub const cs_mode_CS_MODE_32 : cs_mode = 4 ; # [doc = "< 64-bit mode (X86, PPC)"] pub const cs_mode_CS_MODE_64 : cs_mode = 8 ; # [doc = "< ARM's Thumb mode, including Thumb-2"] pub const cs_mode_CS_MODE_THUMB : cs_mode = 16 ; # [doc = "< ARM's Cortex-M series"] pub const cs_mode_CS_MODE_MCLASS : cs_mode = 32 ; # [doc = "< ARMv8 A32 encodings for ARM"] pub const cs_mode_CS_MODE_V8 : cs_mode = 64 ; # [doc = "< MicroMips mode (MIPS)"] pub const cs_mode_CS_MODE_MICRO : cs_mode = 16 ; # [doc = "< Mips III ISA"] pub const cs_mode_CS_MODE_MIPS3 : cs_mode = 32 ; # [doc = "< Mips32r6 ISA"] pub const cs_mode_CS_MODE_MIPS32R6 : cs_mode = 64 ; # [doc = "< Mips II ISA"] pub const cs_mode_CS_MODE_MIPS2 : cs_mode = 128 ; # [doc = "< SparcV9 mode (Sparc)"] pub const cs_mode_CS_MODE_V9 : cs_mode = 16 ; # [doc = "< Quad Processing eXtensions mode (PPC)"] pub const cs_mode_CS_MODE_QPX : cs_mode = 16 ; # [doc = "< Signal Processing Engine mode (PPC)"] pub const cs_mode_CS_MODE_SPE : cs_mode = 32 ; # [doc = "< Book-E mode (PPC)"] pub const cs_mode_CS_MODE_BOOKE : cs_mode = 64 ; # [doc = "< Paired-singles mode (PPC)"] pub const cs_mode_CS_MODE_PS : cs_mode = 128 ; # [doc = "< M68K 68000 mode"] pub const cs_mode_CS_MODE_M68K_000 : cs_mode = 2 ; # [doc = "< M68K 68010 mode"] pub const cs_mode_CS_MODE_M68K_010 : cs_mode = 4 ; # [doc = "< M68K 68020 mode"] pub const cs_mode_CS_MODE_M68K_020 : cs_mode = 8 ; # [doc = "< M68K 68030 mode"] pub const cs_mode_CS_MODE_M68K_030 : cs_mode = 16 ; # [doc = "< M68K 68040 mode"] pub const cs_mode_CS_MODE_M68K_040 : cs_mode = 32 ; # [doc = "< M68K 68060 mode"] pub const cs_mode_CS_MODE_M68K_060 : cs_mode = 64 ; # [doc = "< big-endian mode"] pub const cs_mode_CS_MODE_BIG_ENDIAN : cs_mode = 2147483648 ; # [doc = "< Mips32 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS32 : cs_mode = 4 ; # [doc = "< Mips64 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS64 : cs_mode = 8 ; # [doc = "< M680X Hitachi 6301,6303 mode"] pub const cs_mode_CS_MODE_M680X_6301 : cs_mode = 2 ; # [doc = "< M680X Hitachi 6309 mode"] pub const cs_mode_CS_MODE_M680X_6309 : cs_mode = 4 ; # [doc = "< M680X Motorola 6800,6802 mode"] pub const cs_mode_CS_MODE_M680X_6800 : cs_mode = 8 ; # [doc = "< M680X Motorola 6801,6803 mode"] pub const cs_mode_CS_MODE_M680X_6801 : cs_mode = 16 ; # [doc = "< M680X Motorola/Freescale 6805 mode"] pub const cs_mode_CS_MODE_M680X_6805 : cs_mode = 32 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"] pub const cs_mode_CS_MODE_M680X_6808 : cs_mode = 64 ; # [doc = "< M680X Motorola 6809 mode"] pub const cs_mode_CS_MODE_M680X_6809 : cs_mode = 128 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"] pub const cs_mode_CS_MODE_M680X_6811 : cs_mode = 256 ; # [doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"] pub const cs_mode_CS_MODE_M680X_CPU12 : cs_mode = 512 ; # [doc = "< M680X Freescale/NXP HCS08 mode"] pub const cs_mode_CS_MODE_M680X_HCS08 : cs_mode = 1024 ; # [doc = "< Classic BPF mode (default)"] pub const cs_mode_CS_MODE_BPF_CLASSIC : cs_mode = 0 ; # [doc = "< Extended BPF mode"] pub const cs_mode_CS_MODE_BPF_EXTENDED : cs_mode = 1 ; # [doc = "< RISCV RV32G"] pub const cs_mode_CS_MODE_RISCV32 : cs_mode = 1 ; # [doc = "< RISCV RV64G"] pub const cs_mode_CS_MODE_RISCV64 : cs_mode = 2 ; # [doc = "< RISCV compressed instructure mode"] pub const cs_mode_CS_MODE_RISCVC : cs_mode = 4 ; # [doc = "< MOS65XXX MOS 6502"] pub const cs_mode_CS_MODE_MOS65XX_6502 : cs_mode = 2 ; # [doc = "< MOS65XXX WDC 65c02"] pub const cs_mode_CS_MODE_MOS65XX_65C02 : cs_mode = 4 ; # [doc = "< MOS65XXX WDC W65c02"] pub const cs_mode_CS_MODE_MOS65XX_W65C02 : cs_mode = 8 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m/x"] pub const cs_mode_CS_MODE_MOS65XX_65816 : cs_mode = 16 ; # [doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_M : cs_mode = 32 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_X : cs_mode = 64 ; pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_MX : cs_mode = 96 ; # [doc = "< SH2"] pub const cs_mode_CS_MODE_SH2 : cs_mode = 2 ; # [doc = "< SH2A"] pub const cs_mode_CS_MODE_SH2A : cs_mode = 4 ; # [doc = "< SH3"] pub const cs_mode_CS_MODE_SH3 : cs_mode = 8 ; # [doc = "< SH4"] pub const cs_mode_CS_MODE_SH4 : cs_mode = 16 ; # [doc = "< SH4A"] pub const cs_mode_CS_MODE_SH4A : cs_mode = 32 ; # [doc = "< w/ FPU"] pub const cs_mode_CS_MODE_SHFPU : cs_mode = 64 ; # [doc = "< w/ DSP"] pub const cs_mode_CS_MODE_SHDSP : cs_mode = 128 ; # [doc = "< Tricore 1.1"] pub const cs_mode_CS_MODE_TRICORE_110 : cs_mode = 2 ; # [doc = "< Tricore 1.2"] pub const cs_mode_CS_MODE_TRICORE_120 : cs_mode = 4 ; # [doc = "< Tricore 1.3"] pub const cs_mode_CS_MODE_TRICORE_130 : cs_mode = 8 ; # [doc = "< Tricore 1.3.1"] pub const cs_mode_CS_MODE_TRICORE_131 : cs_mode = 16 ; # [doc = "< Tricore 1.6"] pub const cs_mode_CS_MODE_TRICORE_160 : cs_mode = 32 ; # [doc = "< Tricore 1.6.1"] pub const cs_mode_CS_MODE_TRICORE_161 : cs_mode = 64 ; # [doc = "< Tricore 1.6.2"] pub const cs_mode_CS_MODE_TRICORE_162 : cs_mode = 128 ; # [doc = " Mode type"] pub type cs_mode = :: std :: os :: raw :: c_uint ; pub type cs_malloc_t = :: std :: option :: Option < unsafe extern "C" fn (size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_calloc_t = :: std :: option :: Option < unsafe extern "C" fn (nmemb : usize , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_realloc_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_free_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void) > ; pub type cs_vsnprintf_t = :: std :: option :: Option < unsafe extern "C" fn (str_ : * mut :: std :: os :: raw :: c_char , size : usize , format : * const :: std :: os :: raw :: c_char , ap : * mut __va_list_tag) -> :: std :: os :: raw :: c_int > ; # [doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mem { pub malloc : cs_malloc_t , pub calloc : cs_calloc_t , pub realloc : cs_realloc_t , pub free : cs_free_t , pub vsnprintf : cs_vsnprintf_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mem"] [:: std :: mem :: size_of :: < cs_opt_mem > () - 40usize] ; ["Alignment of cs_opt_mem"] [:: std :: mem :: align_of :: < cs_opt_mem > () - 8usize] ; ["Offset of field: cs_opt_mem::malloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , malloc) - 0usize] ; ["Offset of field: cs_opt_mem::calloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , calloc) - 8usize] ; ["Offset of field: cs_opt_mem::realloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , realloc) - 16usize] ; ["Offset of field: cs_opt_mem::free"] [:: std :: mem :: offset_of ! (cs_opt_mem , free) - 24usize] ; ["Offset of field: cs_opt_mem::vsnprintf"] [:: std :: mem :: offset_of ! (cs_opt_mem , vsnprintf) - 32usize] ; } ; # [doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mnem { # [doc = " ID of instruction to be customized."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Customized instruction mnemonic."] pub mnemonic : * const :: std :: os :: raw :: c_char , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mnem"] [:: std :: mem :: size_of :: < cs_opt_mnem > () - 16usize] ; ["Alignment of cs_opt_mnem"] [:: std :: mem :: align_of :: < cs_opt_mnem > () - 8usize] ; ["Offset of field: cs_opt_mnem::id"] [:: std :: mem :: offset_of ! (cs_opt_mnem , id) - 0usize] ; ["Offset of field: cs_opt_mnem::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_mnem , mnemonic) - 8usize] ; } ; # [repr (u32)] # [doc = " Runtime option for the disassembled engine"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_type { # [doc = "< No option specified"] CS_OPT_INVALID = 0 , # [doc = "< Assembly output syntax"] CS_OPT_SYNTAX = 1 , # [doc = "< Break down instruction structure into details"] CS_OPT_DETAIL = 2 , # [doc = "< Change engine's mode at run-time"] CS_OPT_MODE = 3 , # [doc = "< User-defined dynamic memory related functions"] CS_OPT_MEM = 4 , # [doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."] CS_OPT_SKIPDATA = 5 , # [doc = "< Setup user-defined function for SKIPDATA option"] CS_OPT_SKIPDATA_SETUP = 6 , # [doc = "< Customize instruction mnemonic"] CS_OPT_MNEMONIC = 7 , # [doc = "< print immediate operands in unsigned form"] CS_OPT_UNSIGNED = 8 , # [doc = "< ARM, prints branch immediates without offset."] CS_OPT_NO_BRANCH_OFFSET = 9 , } impl cs_opt_value { pub const CS_OPT_SYNTAX_DEFAULT : cs_opt_value = cs_opt_value :: CS_OPT_OFF ; } impl cs_opt_value { pub const CS_OPT_SYNTAX_NOREGNAME : cs_opt_value = cs_opt_value :: CS_OPT_ON ; } # [repr (u32)] # [doc = " Runtime option value (associated with option type above)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_value { # [doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."] CS_OPT_OFF = 0 , # [doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."] CS_OPT_ON = 3 , # [doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_INTEL = 1 , # [doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_ATT = 2 , # [doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_MASM = 4 , # [doc = "< MOS65XX use $ as hex prefix"] CS_OPT_SYNTAX_MOTOROLA = 5 , } # [repr (u32)] # [doc = " Common instruction operand types - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_op_type { # [doc = "< uninitialized/invalid operand."] CS_OP_INVALID = 0 , # [doc = "< Register operand."] CS_OP_REG = 1 , # [doc = "< Immediate operand."] CS_OP_IMM = 2 , # [doc = "< Memory operand. Can be ORed with another operand type."] CS_OP_MEM = 3 , # [doc = "< Floating-Point operand."] CS_OP_FP = 4 , } # [repr (u32)] # [doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_ac_type { # [doc = "< Uninitialized/invalid access type."] CS_AC_INVALID = 0 , # [doc = "< Operand read from memory or register."] CS_AC_READ = 1 , # [doc = "< Operand write to memory or register."] CS_AC_WRITE = 2 , } # [repr (u32)] # [doc = " Common instruction groups - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_group_type { # [doc = "< uninitialized/invalid group."] CS_GRP_INVALID = 0 , # [doc = "< all jump instructions (conditional+direct+indirect jumps)"] CS_GRP_JUMP = 1 , # [doc = "< all call instructions"] CS_GRP_CALL = 2 , # [doc = "< all return instructions"] CS_GRP_RET = 3 , # [doc = "< all interrupt instructions (int+syscall)"] CS_GRP_INT = 4 , # [doc = "< all interrupt return instructions"] CS_GRP_IRET = 5 , # [doc = "< all privileged instructions"] CS_GRP_PRIVILEGE = 6 , # [doc = "< all relative branching instructions"] CS_GRP_BRANCH_RELATIVE = 7 , } # [doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."] pub type cs_skipdata_cb_t = :: std :: option :: Option < unsafe extern "C" fn (code : * const u8 , code_size : usize , offset : usize , user_data : * mut :: std :: os :: raw :: c_void) -> usize > ; # [doc = " User-customized setup for SKIPDATA option"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_skipdata { # [doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."] pub mnemonic : * const :: std :: os :: raw :: c_char , # [doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes.\n TriCore: 2 bytes."] pub callback : cs_skipdata_cb_t , # [doc = " User-defined data to be passed to @callback function pointer."] pub user_data : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_skipdata"] [:: std :: mem :: size_of :: < cs_opt_skipdata > () - 24usize] ; ["Alignment of cs_opt_skipdata"] [:: std :: mem :: align_of :: < cs_opt_skipdata > () - 8usize] ; ["Offset of field: cs_opt_skipdata::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , mnemonic) - 0usize] ; ["Offset of field: cs_opt_skipdata::callback"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , callback) - 8usize] ; ["Offset of field: cs_opt_skipdata::user_data"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , user_data) - 16usize] ; } ; # [repr (u32)] # [doc = " ARM shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_shifter { ARM_SFT_INVALID = 0 , # [doc = "< shift with immediate const"] ARM_SFT_ASR = 1 , # [doc = "< shift with immediate const"] ARM_SFT_LSL = 2 , # [doc = "< shift with immediate const"] ARM_SFT_LSR = 3 , # [doc = "< shift with immediate const"] ARM_SFT_ROR = 4 , # [doc = "< shift with immediate const"] ARM_SFT_RRX = 5 , # [doc = "< shift with register"] ARM_SFT_ASR_REG = 6 , # [doc = "< shift with register"] ARM_SFT_LSL_REG = 7 , # [doc = "< shift with register"] ARM_SFT_LSR_REG = 8 , # [doc = "< shift with register"] ARM_SFT_ROR_REG = 9 , # [doc = "< shift with register"] ARM_SFT_RRX_REG = 10 , } # [repr (u32)] # [doc = " ARM condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cc { ARM_CC_INVALID = 0 , # [doc = "< Equal                      Equal"] ARM_CC_EQ = 1 , # [doc = "< Not equal                  Not equal, or unordered"] ARM_CC_NE = 2 , # [doc = "< Carry set                  >, ==, or unordered"] ARM_CC_HS = 3 , # [doc = "< Carry clear                Less than"] ARM_CC_LO = 4 , # [doc = "< Minus, negative            Less than"] ARM_CC_MI = 5 , # [doc = "< Plus, positive or zero     >, ==, or unordered"] ARM_CC_PL = 6 , # [doc = "< Overflow                   Unordered"] ARM_CC_VS = 7 , # [doc = "< No overflow                Not unordered"] ARM_CC_VC = 8 , # [doc = "< Unsigned higher            Greater than, or unordered"] ARM_CC_HI = 9 , # [doc = "< Unsigned lower or same     Less than or equal"] ARM_CC_LS = 10 , # [doc = "< Greater than or equal      Greater than or equal"] ARM_CC_GE = 11 , # [doc = "< Less than                  Less than, or unordered"] ARM_CC_LT = 12 , # [doc = "< Greater than               Greater than"] ARM_CC_GT = 13 , # [doc = "< Less than or equal         <, ==, or unordered"] ARM_CC_LE = 14 , # [doc = "< Always (unconditional)     Always (unconditional)"] ARM_CC_AL = 15 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_sysreg { # [doc = " Special registers for MSR"] ARM_SYSREG_INVALID = 0 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_C = 1 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_X = 2 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_S = 4 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_F = 8 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_C = 16 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_X = 32 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_S = 64 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_F = 128 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR = 256 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_G = 257 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQ = 258 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQG = 259 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR = 260 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_G = 261 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQG = 262 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQ = 263 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR = 264 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_G = 265 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQG = 266 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQ = 267 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR = 268 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_G = 269 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQG = 270 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQ = 271 , # [doc = " Special registers for MSR"] ARM_SYSREG_IPSR = 272 , # [doc = " Special registers for MSR"] ARM_SYSREG_EPSR = 273 , # [doc = " Special registers for MSR"] ARM_SYSREG_IEPSR = 274 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP = 275 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP = 276 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK = 277 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI = 278 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_MAX = 279 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK = 280 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL = 281 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM = 282 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM = 283 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP_NS = 284 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP_NS = 285 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM_NS = 286 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM_NS = 287 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK_NS = 288 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_NS = 289 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK_NS = 290 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL_NS = 291 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_NS = 292 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_USR = 293 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_USR = 294 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_USR = 295 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_USR = 296 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_USR = 297 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_USR = 298 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_USR = 299 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_FIQ = 300 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_FIQ = 301 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_FIQ = 302 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_FIQ = 303 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_FIQ = 304 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_FIQ = 305 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_FIQ = 306 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_IRQ = 307 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_IRQ = 308 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_SVC = 309 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_SVC = 310 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_ABT = 311 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_ABT = 312 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_UND = 313 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_UND = 314 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_MON = 315 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_MON = 316 , # [doc = " Special registers for MSR"] ARM_SYSREG_ELR_HYP = 317 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_HYP = 318 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_FIQ = 319 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_IRQ = 320 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_SVC = 321 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_ABT = 322 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_UND = 323 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_MON = 324 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_HYP = 325 , } # [repr (u32)] # [doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_mem_barrier { ARM_MB_INVALID = 0 , ARM_MB_RESERVED_0 = 1 , ARM_MB_OSHLD = 2 , ARM_MB_OSHST = 3 , ARM_MB_OSH = 4 , ARM_MB_RESERVED_4 = 5 , ARM_MB_NSHLD = 6 , ARM_MB_NSHST = 7 , ARM_MB_NSH = 8 , ARM_MB_RESERVED_8 = 9 , ARM_MB_ISHLD = 10 , ARM_MB_ISHST = 11 , ARM_MB_ISH = 12 , ARM_MB_RESERVED_12 = 13 , ARM_MB_LD = 14 , ARM_MB_ST = 15 , ARM_MB_SY = 16 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM_OP_FP = 4 , # [doc = "< C-Immediate (coprocessor registers)"] ARM_OP_CIMM = 64 , # [doc = "< P-Immediate (coprocessor registers)"] ARM_OP_PIMM = 65 , # [doc = "< operand for SETEND instruction"] ARM_OP_SETEND = 66 , # [doc = "< MSR/MRS special register operand"] ARM_OP_SYSREG = 67 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_setend_type { # [doc = "< Uninitialized."] ARM_SETEND_INVALID = 0 , # [doc = "< BE operand."] ARM_SETEND_BE = 1 , # [doc = "< LE operand"] ARM_SETEND_LE = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0 , ARM_CPSMODE_IE = 2 , ARM_CPSMODE_ID = 3 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0 , ARM_CPSFLAG_F = 1 , ARM_CPSFLAG_I = 2 , ARM_CPSFLAG_A = 4 , # [doc = "< no flag"] ARM_CPSFLAG_NONE = 16 , } # [repr (u32)] # [doc = " Data type for elements of vector instructions."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0 , ARM_VECTORDATA_I8 = 1 , ARM_VECTORDATA_I16 = 2 , ARM_VECTORDATA_I32 = 3 , ARM_VECTORDATA_I64 = 4 , ARM_VECTORDATA_S8 = 5 , ARM_VECTORDATA_S16 = 6 , ARM_VECTORDATA_S32 = 7 , ARM_VECTORDATA_S64 = 8 , ARM_VECTORDATA_U8 = 9 , ARM_VECTORDATA_U16 = 10 , ARM_VECTORDATA_U32 = 11 , ARM_VECTORDATA_U64 = 12 , ARM_VECTORDATA_P8 = 13 , ARM_VECTORDATA_F16 = 14 , ARM_VECTORDATA_F32 = 15 , ARM_VECTORDATA_F64 = 16 , ARM_VECTORDATA_F16F64 = 17 , ARM_VECTORDATA_F64F16 = 18 , ARM_VECTORDATA_F32F16 = 19 , ARM_VECTORDATA_F16F32 = 20 , ARM_VECTORDATA_F64F32 = 21 , ARM_VECTORDATA_F32F64 = 22 , ARM_VECTORDATA_S32F32 = 23 , ARM_VECTORDATA_U32F32 = 24 , ARM_VECTORDATA_F32S32 = 25 , ARM_VECTORDATA_F32U32 = 26 , ARM_VECTORDATA_F64S16 = 27 , ARM_VECTORDATA_F32S16 = 28 , ARM_VECTORDATA_F64S32 = 29 , ARM_VECTORDATA_S16F64 = 30 , ARM_VECTORDATA_S16F32 = 31 , ARM_VECTORDATA_S32F64 = 32 , ARM_VECTORDATA_U16F64 = 33 , ARM_VECTORDATA_U16F32 = 34 , ARM_VECTORDATA_U32F64 = 35 , ARM_VECTORDATA_F64U16 = 36 , ARM_VECTORDATA_F32U16 = 37 , ARM_VECTORDATA_F64U32 = 38 , ARM_VECTORDATA_F16U16 = 39 , ARM_VECTORDATA_U16F16 = 40 , ARM_VECTORDATA_F16U32 = 41 , ARM_VECTORDATA_U32F16 = 42 , } impl arm_reg { pub const ARM_REG_R13 : arm_reg = arm_reg :: ARM_REG_SP ; } impl arm_reg { pub const ARM_REG_R14 : arm_reg = arm_reg :: ARM_REG_LR ; } impl arm_reg { pub const ARM_REG_R15 : arm_reg = arm_reg :: ARM_REG_PC ; } impl arm_reg { pub const ARM_REG_SB : arm_reg = arm_reg :: ARM_REG_R9 ; } impl arm_reg { pub const ARM_REG_SL : arm_reg = arm_reg :: ARM_REG_R10 ; } impl arm_reg { pub const ARM_REG_FP : arm_reg = arm_reg :: ARM_REG_R11 ; } impl arm_reg { pub const ARM_REG_IP : arm_reg = arm_reg :: ARM_REG_R12 ; } # [repr (u32)] # [doc = " ARM registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_reg { ARM_REG_INVALID = 0 , ARM_REG_APSR = 1 , ARM_REG_APSR_NZCV = 2 , ARM_REG_CPSR = 3 , ARM_REG_FPEXC = 4 , ARM_REG_FPINST = 5 , ARM_REG_FPSCR = 6 , ARM_REG_FPSCR_NZCV = 7 , ARM_REG_FPSID = 8 , ARM_REG_ITSTATE = 9 , ARM_REG_LR = 10 , ARM_REG_PC = 11 , ARM_REG_SP = 12 , ARM_REG_SPSR = 13 , ARM_REG_D0 = 14 , ARM_REG_D1 = 15 , ARM_REG_D2 = 16 , ARM_REG_D3 = 17 , ARM_REG_D4 = 18 , ARM_REG_D5 = 19 , ARM_REG_D6 = 20 , ARM_REG_D7 = 21 , ARM_REG_D8 = 22 , ARM_REG_D9 = 23 , ARM_REG_D10 = 24 , ARM_REG_D11 = 25 , ARM_REG_D12 = 26 , ARM_REG_D13 = 27 , ARM_REG_D14 = 28 , ARM_REG_D15 = 29 , ARM_REG_D16 = 30 , ARM_REG_D17 = 31 , ARM_REG_D18 = 32 , ARM_REG_D19 = 33 , ARM_REG_D20 = 34 , ARM_REG_D21 = 35 , ARM_REG_D22 = 36 , ARM_REG_D23 = 37 , ARM_REG_D24 = 38 , ARM_REG_D25 = 39 , ARM_REG_D26 = 40 , ARM_REG_D27 = 41 , ARM_REG_D28 = 42 , ARM_REG_D29 = 43 , ARM_REG_D30 = 44 , ARM_REG_D31 = 45 , ARM_REG_FPINST2 = 46 , ARM_REG_MVFR0 = 47 , ARM_REG_MVFR1 = 48 , ARM_REG_MVFR2 = 49 , ARM_REG_Q0 = 50 , ARM_REG_Q1 = 51 , ARM_REG_Q2 = 52 , ARM_REG_Q3 = 53 , ARM_REG_Q4 = 54 , ARM_REG_Q5 = 55 , ARM_REG_Q6 = 56 , ARM_REG_Q7 = 57 , ARM_REG_Q8 = 58 , ARM_REG_Q9 = 59 , ARM_REG_Q10 = 60 , ARM_REG_Q11 = 61 , ARM_REG_Q12 = 62 , ARM_REG_Q13 = 63 , ARM_REG_Q14 = 64 , ARM_REG_Q15 = 65 , ARM_REG_R0 = 66 , ARM_REG_R1 = 67 , ARM_REG_R2 = 68 , ARM_REG_R3 = 69 , ARM_REG_R4 = 70 , ARM_REG_R5 = 71 , ARM_REG_R6 = 72 , ARM_REG_R7 = 73 , ARM_REG_R8 = 74 , ARM_REG_R9 = 75 , ARM_REG_R10 = 76 , ARM_REG_R11 = 77 , ARM_REG_R12 = 78 , ARM_REG_S0 = 79 , ARM_REG_S1 = 80 , ARM_REG_S2 = 81 , ARM_REG_S3 = 82 , ARM_REG_S4 = 83 , ARM_REG_S5 = 84 , ARM_REG_S6 = 85 , ARM_REG_S7 = 86 , ARM_REG_S8 = 87 , ARM_REG_S9 = 88 , ARM_REG_S10 = 89 , ARM_REG_S11 = 90 , ARM_REG_S12 = 91 , ARM_REG_S13 = 92 , ARM_REG_S14 = 93 , ARM_REG_S15 = 94 , ARM_REG_S16 = 95 , ARM_REG_S17 = 96 , ARM_REG_S18 = 97 , ARM_REG_S19 = 98 , ARM_REG_S20 = 99 , ARM_REG_S21 = 100 , ARM_REG_S22 = 101 , ARM_REG_S23 = 102 , ARM_REG_S24 = 103 , ARM_REG_S25 = 104 , ARM_REG_S26 = 105 , ARM_REG_S27 = 106 , ARM_REG_S28 = 107 , ARM_REG_S29 = 108 , ARM_REG_S30 = 109 , ARM_REG_S31 = 110 , ARM_REG_ENDING = 111 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm_op_mem { # [doc = "< base register"] pub base : arm_reg , # [doc = "< index register"] pub index : arm_reg , # [doc = "< scale for index register (can be 1, or -1)"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_int , # [doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"] pub lshift : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm_op_mem"] [:: std :: mem :: size_of :: < arm_op_mem > () - 20usize] ; ["Alignment of arm_op_mem"] [:: std :: mem :: align_of :: < arm_op_mem > () - 4usize] ; ["Offset of field: arm_op_mem::base"] [:: std :: mem :: offset_of ! (arm_op_mem , base) - 0usize] ; ["Offset of field: arm_op_mem::index"] [:: std :: mem :: offset_of ! (arm_op_mem , index) - 4usize] ; ["Offset of field: arm_op_mem::scale"] [:: std :: mem :: offset_of ! (arm_op_mem , scale) - 8usize] ; ["Offset of field: arm_op_mem::disp"] [:: std :: mem :: offset_of ! (arm_op_mem , disp) - 12usize] ; ["Offset of field: arm_op_mem::lshift"] [:: std :: mem :: offset_of ! (arm_op_mem , lshift) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm_op { # [doc = "< Vector Index for some vector operands (or -1 if irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , pub shift : cs_arm_op__bindgen_ty_1 , # [doc = "< operand type"] pub type_ : arm_op_type , pub __bindgen_anon_1 : cs_arm_op__bindgen_ty_2 , # [doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."] pub subtracted : bool , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"] pub neon_lane : i8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm_op__bindgen_ty_1 { pub type_ : arm_shifter , pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm_op__bindgen_ty_2 { # [doc = "< register value for REG/SYSREG operand"] pub reg : :: std :: os :: raw :: c_int , # [doc = "< immediate value for C-IMM, P-IMM or IMM operand"] pub imm : i32 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm_op_mem , # [doc = "< SETEND instruction's operand type"] pub setend : arm_setend_type , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_2 > () - 24usize] ; ["Alignment of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::setend"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , setend) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op"] [:: std :: mem :: size_of :: < cs_arm_op > () - 48usize] ; ["Alignment of cs_arm_op"] [:: std :: mem :: align_of :: < cs_arm_op > () - 8usize] ; ["Offset of field: cs_arm_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm_op , vector_index) - 0usize] ; ["Offset of field: cs_arm_op::shift"] [:: std :: mem :: offset_of ! (cs_arm_op , shift) - 4usize] ; ["Offset of field: cs_arm_op::type_"] [:: std :: mem :: offset_of ! (cs_arm_op , type_) - 12usize] ; ["Offset of field: cs_arm_op::subtracted"] [:: std :: mem :: offset_of ! (cs_arm_op , subtracted) - 40usize] ; ["Offset of field: cs_arm_op::access"] [:: std :: mem :: offset_of ! (cs_arm_op , access) - 41usize] ; ["Offset of field: cs_arm_op::neon_lane"] [:: std :: mem :: offset_of ! (cs_arm_op , neon_lane) - 42usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm { # [doc = "< User-mode registers to be loaded (for LDM/STM instructions)"] pub usermode : bool , # [doc = "< Scalar size for vector instructions"] pub vector_size : :: std :: os :: raw :: c_int , # [doc = "< Data type for elements of vector instructions"] pub vector_data : arm_vectordata_type , # [doc = "< CPS mode for CPS instruction"] pub cps_mode : arm_cpsmode_type , # [doc = "< CPS mode for CPS instruction"] pub cps_flag : arm_cpsflag_type , # [doc = "< conditional code for this insn"] pub cc : arm_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn write-back?"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = "< Option for some memory barrier instructions"] pub mem_barrier : arm_mem_barrier , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm_op ; 36usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm"] [:: std :: mem :: size_of :: < cs_arm > () - 1768usize] ; ["Alignment of cs_arm"] [:: std :: mem :: align_of :: < cs_arm > () - 8usize] ; ["Offset of field: cs_arm::usermode"] [:: std :: mem :: offset_of ! (cs_arm , usermode) - 0usize] ; ["Offset of field: cs_arm::vector_size"] [:: std :: mem :: offset_of ! (cs_arm , vector_size) - 4usize] ; ["Offset of field: cs_arm::vector_data"] [:: std :: mem :: offset_of ! (cs_arm , vector_data) - 8usize] ; ["Offset of field: cs_arm::cps_mode"] [:: std :: mem :: offset_of ! (cs_arm , cps_mode) - 12usize] ; ["Offset of field: cs_arm::cps_flag"] [:: std :: mem :: offset_of ! (cs_arm , cps_flag) - 16usize] ; ["Offset of field: cs_arm::cc"] [:: std :: mem :: offset_of ! (cs_arm , cc) - 20usize] ; ["Offset of field: cs_arm::update_flags"] [:: std :: mem :: offset_of ! (cs_arm , update_flags) - 24usize] ; ["Offset of field: cs_arm::writeback"] [:: std :: mem :: offset_of ! (cs_arm , writeback) - 25usize] ; ["Offset of field: cs_arm::post_index"] [:: std :: mem :: offset_of ! (cs_arm , post_index) - 26usize] ; ["Offset of field: cs_arm::mem_barrier"] [:: std :: mem :: offset_of ! (cs_arm , mem_barrier) - 28usize] ; ["Offset of field: cs_arm::op_count"] [:: std :: mem :: offset_of ! (cs_arm , op_count) - 32usize] ; ["Offset of field: cs_arm::operands"] [:: std :: mem :: offset_of ! (cs_arm , operands) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_arm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . post_index , self . mem_barrier , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn { ARM_INS_INVALID = 0 , ARM_INS_ADC = 1 , ARM_INS_ADD = 2 , ARM_INS_ADDW = 3 , ARM_INS_ADR = 4 , ARM_INS_AESD = 5 , ARM_INS_AESE = 6 , ARM_INS_AESIMC = 7 , ARM_INS_AESMC = 8 , ARM_INS_AND = 9 , ARM_INS_ASR = 10 , ARM_INS_B = 11 , ARM_INS_BFC = 12 , ARM_INS_BFI = 13 , ARM_INS_BIC = 14 , ARM_INS_BKPT = 15 , ARM_INS_BL = 16 , ARM_INS_BLX = 17 , ARM_INS_BLXNS = 18 , ARM_INS_BX = 19 , ARM_INS_BXJ = 20 , ARM_INS_BXNS = 21 , ARM_INS_CBNZ = 22 , ARM_INS_CBZ = 23 , ARM_INS_CDP = 24 , ARM_INS_CDP2 = 25 , ARM_INS_CLREX = 26 , ARM_INS_CLZ = 27 , ARM_INS_CMN = 28 , ARM_INS_CMP = 29 , ARM_INS_CPS = 30 , ARM_INS_CRC32B = 31 , ARM_INS_CRC32CB = 32 , ARM_INS_CRC32CH = 33 , ARM_INS_CRC32CW = 34 , ARM_INS_CRC32H = 35 , ARM_INS_CRC32W = 36 , ARM_INS_CSDB = 37 , ARM_INS_DBG = 38 , ARM_INS_DCPS1 = 39 , ARM_INS_DCPS2 = 40 , ARM_INS_DCPS3 = 41 , ARM_INS_DFB = 42 , ARM_INS_DMB = 43 , ARM_INS_DSB = 44 , ARM_INS_EOR = 45 , ARM_INS_ERET = 46 , ARM_INS_ESB = 47 , ARM_INS_FADDD = 48 , ARM_INS_FADDS = 49 , ARM_INS_FCMPZD = 50 , ARM_INS_FCMPZS = 51 , ARM_INS_FCONSTD = 52 , ARM_INS_FCONSTS = 53 , ARM_INS_FLDMDBX = 54 , ARM_INS_FLDMIAX = 55 , ARM_INS_FMDHR = 56 , ARM_INS_FMDLR = 57 , ARM_INS_FMSTAT = 58 , ARM_INS_FSTMDBX = 59 , ARM_INS_FSTMIAX = 60 , ARM_INS_FSUBD = 61 , ARM_INS_FSUBS = 62 , ARM_INS_HINT = 63 , ARM_INS_HLT = 64 , ARM_INS_HVC = 65 , ARM_INS_ISB = 66 , ARM_INS_IT = 67 , ARM_INS_LDA = 68 , ARM_INS_LDAB = 69 , ARM_INS_LDAEX = 70 , ARM_INS_LDAEXB = 71 , ARM_INS_LDAEXD = 72 , ARM_INS_LDAEXH = 73 , ARM_INS_LDAH = 74 , ARM_INS_LDC = 75 , ARM_INS_LDC2 = 76 , ARM_INS_LDC2L = 77 , ARM_INS_LDCL = 78 , ARM_INS_LDM = 79 , ARM_INS_LDMDA = 80 , ARM_INS_LDMDB = 81 , ARM_INS_LDMIB = 82 , ARM_INS_LDR = 83 , ARM_INS_LDRB = 84 , ARM_INS_LDRBT = 85 , ARM_INS_LDRD = 86 , ARM_INS_LDREX = 87 , ARM_INS_LDREXB = 88 , ARM_INS_LDREXD = 89 , ARM_INS_LDREXH = 90 , ARM_INS_LDRH = 91 , ARM_INS_LDRHT = 92 , ARM_INS_LDRSB = 93 , ARM_INS_LDRSBT = 94 , ARM_INS_LDRSH = 95 , ARM_INS_LDRSHT = 96 , ARM_INS_LDRT = 97 , ARM_INS_LSL = 98 , ARM_INS_LSR = 99 , ARM_INS_MCR = 100 , ARM_INS_MCR2 = 101 , ARM_INS_MCRR = 102 , ARM_INS_MCRR2 = 103 , ARM_INS_MLA = 104 , ARM_INS_MLS = 105 , ARM_INS_MOV = 106 , ARM_INS_MOVS = 107 , ARM_INS_MOVT = 108 , ARM_INS_MOVW = 109 , ARM_INS_MRC = 110 , ARM_INS_MRC2 = 111 , ARM_INS_MRRC = 112 , ARM_INS_MRRC2 = 113 , ARM_INS_MRS = 114 , ARM_INS_MSR = 115 , ARM_INS_MUL = 116 , ARM_INS_MVN = 117 , ARM_INS_NEG = 118 , ARM_INS_NOP = 119 , ARM_INS_ORN = 120 , ARM_INS_ORR = 121 , ARM_INS_PKHBT = 122 , ARM_INS_PKHTB = 123 , ARM_INS_PLD = 124 , ARM_INS_PLDW = 125 , ARM_INS_PLI = 126 , ARM_INS_POP = 127 , ARM_INS_PUSH = 128 , ARM_INS_QADD = 129 , ARM_INS_QADD16 = 130 , ARM_INS_QADD8 = 131 , ARM_INS_QASX = 132 , ARM_INS_QDADD = 133 , ARM_INS_QDSUB = 134 , ARM_INS_QSAX = 135 , ARM_INS_QSUB = 136 , ARM_INS_QSUB16 = 137 , ARM_INS_QSUB8 = 138 , ARM_INS_RBIT = 139 , ARM_INS_REV = 140 , ARM_INS_REV16 = 141 , ARM_INS_REVSH = 142 , ARM_INS_RFEDA = 143 , ARM_INS_RFEDB = 144 , ARM_INS_RFEIA = 145 , ARM_INS_RFEIB = 146 , ARM_INS_ROR = 147 , ARM_INS_RRX = 148 , ARM_INS_RSB = 149 , ARM_INS_RSC = 150 , ARM_INS_SADD16 = 151 , ARM_INS_SADD8 = 152 , ARM_INS_SASX = 153 , ARM_INS_SBC = 154 , ARM_INS_SBFX = 155 , ARM_INS_SDIV = 156 , ARM_INS_SEL = 157 , ARM_INS_SETEND = 158 , ARM_INS_SETPAN = 159 , ARM_INS_SEV = 160 , ARM_INS_SEVL = 161 , ARM_INS_SG = 162 , ARM_INS_SHA1C = 163 , ARM_INS_SHA1H = 164 , ARM_INS_SHA1M = 165 , ARM_INS_SHA1P = 166 , ARM_INS_SHA1SU0 = 167 , ARM_INS_SHA1SU1 = 168 , ARM_INS_SHA256H = 169 , ARM_INS_SHA256H2 = 170 , ARM_INS_SHA256SU0 = 171 , ARM_INS_SHA256SU1 = 172 , ARM_INS_SHADD16 = 173 , ARM_INS_SHADD8 = 174 , ARM_INS_SHASX = 175 , ARM_INS_SHSAX = 176 , ARM_INS_SHSUB16 = 177 , ARM_INS_SHSUB8 = 178 , ARM_INS_SMC = 179 , ARM_INS_SMLABB = 180 , ARM_INS_SMLABT = 181 , ARM_INS_SMLAD = 182 , ARM_INS_SMLADX = 183 , ARM_INS_SMLAL = 184 , ARM_INS_SMLALBB = 185 , ARM_INS_SMLALBT = 186 , ARM_INS_SMLALD = 187 , ARM_INS_SMLALDX = 188 , ARM_INS_SMLALTB = 189 , ARM_INS_SMLALTT = 190 , ARM_INS_SMLATB = 191 , ARM_INS_SMLATT = 192 , ARM_INS_SMLAWB = 193 , ARM_INS_SMLAWT = 194 , ARM_INS_SMLSD = 195 , ARM_INS_SMLSDX = 196 , ARM_INS_SMLSLD = 197 , ARM_INS_SMLSLDX = 198 , ARM_INS_SMMLA = 199 , ARM_INS_SMMLAR = 200 , ARM_INS_SMMLS = 201 , ARM_INS_SMMLSR = 202 , ARM_INS_SMMUL = 203 , ARM_INS_SMMULR = 204 , ARM_INS_SMUAD = 205 , ARM_INS_SMUADX = 206 , ARM_INS_SMULBB = 207 , ARM_INS_SMULBT = 208 , ARM_INS_SMULL = 209 , ARM_INS_SMULTB = 210 , ARM_INS_SMULTT = 211 , ARM_INS_SMULWB = 212 , ARM_INS_SMULWT = 213 , ARM_INS_SMUSD = 214 , ARM_INS_SMUSDX = 215 , ARM_INS_SRSDA = 216 , ARM_INS_SRSDB = 217 , ARM_INS_SRSIA = 218 , ARM_INS_SRSIB = 219 , ARM_INS_SSAT = 220 , ARM_INS_SSAT16 = 221 , ARM_INS_SSAX = 222 , ARM_INS_SSUB16 = 223 , ARM_INS_SSUB8 = 224 , ARM_INS_STC = 225 , ARM_INS_STC2 = 226 , ARM_INS_STC2L = 227 , ARM_INS_STCL = 228 , ARM_INS_STL = 229 , ARM_INS_STLB = 230 , ARM_INS_STLEX = 231 , ARM_INS_STLEXB = 232 , ARM_INS_STLEXD = 233 , ARM_INS_STLEXH = 234 , ARM_INS_STLH = 235 , ARM_INS_STM = 236 , ARM_INS_STMDA = 237 , ARM_INS_STMDB = 238 , ARM_INS_STMIB = 239 , ARM_INS_STR = 240 , ARM_INS_STRB = 241 , ARM_INS_STRBT = 242 , ARM_INS_STRD = 243 , ARM_INS_STREX = 244 , ARM_INS_STREXB = 245 , ARM_INS_STREXD = 246 , ARM_INS_STREXH = 247 , ARM_INS_STRH = 248 , ARM_INS_STRHT = 249 , ARM_INS_STRT = 250 , ARM_INS_SUB = 251 , ARM_INS_SUBS = 252 , ARM_INS_SUBW = 253 , ARM_INS_SVC = 254 , ARM_INS_SWP = 255 , ARM_INS_SWPB = 256 , ARM_INS_SXTAB = 257 , ARM_INS_SXTAB16 = 258 , ARM_INS_SXTAH = 259 , ARM_INS_SXTB = 260 , ARM_INS_SXTB16 = 261 , ARM_INS_SXTH = 262 , ARM_INS_TBB = 263 , ARM_INS_TBH = 264 , ARM_INS_TEQ = 265 , ARM_INS_TRAP = 266 , ARM_INS_TSB = 267 , ARM_INS_TST = 268 , ARM_INS_TT = 269 , ARM_INS_TTA = 270 , ARM_INS_TTAT = 271 , ARM_INS_TTT = 272 , ARM_INS_UADD16 = 273 , ARM_INS_UADD8 = 274 , ARM_INS_UASX = 275 , ARM_INS_UBFX = 276 , ARM_INS_UDF = 277 , ARM_INS_UDIV = 278 , ARM_INS_UHADD16 = 279 , ARM_INS_UHADD8 = 280 , ARM_INS_UHASX = 281 , ARM_INS_UHSAX = 282 , ARM_INS_UHSUB16 = 283 , ARM_INS_UHSUB8 = 284 , ARM_INS_UMAAL = 285 , ARM_INS_UMLAL = 286 , ARM_INS_UMULL = 287 , ARM_INS_UQADD16 = 288 , ARM_INS_UQADD8 = 289 , ARM_INS_UQASX = 290 , ARM_INS_UQSAX = 291 , ARM_INS_UQSUB16 = 292 , ARM_INS_UQSUB8 = 293 , ARM_INS_USAD8 = 294 , ARM_INS_USADA8 = 295 , ARM_INS_USAT = 296 , ARM_INS_USAT16 = 297 , ARM_INS_USAX = 298 , ARM_INS_USUB16 = 299 , ARM_INS_USUB8 = 300 , ARM_INS_UXTAB = 301 , ARM_INS_UXTAB16 = 302 , ARM_INS_UXTAH = 303 , ARM_INS_UXTB = 304 , ARM_INS_UXTB16 = 305 , ARM_INS_UXTH = 306 , ARM_INS_VABA = 307 , ARM_INS_VABAL = 308 , ARM_INS_VABD = 309 , ARM_INS_VABDL = 310 , ARM_INS_VABS = 311 , ARM_INS_VACGE = 312 , ARM_INS_VACGT = 313 , ARM_INS_VACLE = 314 , ARM_INS_VACLT = 315 , ARM_INS_VADD = 316 , ARM_INS_VADDHN = 317 , ARM_INS_VADDL = 318 , ARM_INS_VADDW = 319 , ARM_INS_VAND = 320 , ARM_INS_VBIC = 321 , ARM_INS_VBIF = 322 , ARM_INS_VBIT = 323 , ARM_INS_VBSL = 324 , ARM_INS_VCADD = 325 , ARM_INS_VCEQ = 326 , ARM_INS_VCGE = 327 , ARM_INS_VCGT = 328 , ARM_INS_VCLE = 329 , ARM_INS_VCLS = 330 , ARM_INS_VCLT = 331 , ARM_INS_VCLZ = 332 , ARM_INS_VCMLA = 333 , ARM_INS_VCMP = 334 , ARM_INS_VCMPE = 335 , ARM_INS_VCNT = 336 , ARM_INS_VCVT = 337 , ARM_INS_VCVTA = 338 , ARM_INS_VCVTB = 339 , ARM_INS_VCVTM = 340 , ARM_INS_VCVTN = 341 , ARM_INS_VCVTP = 342 , ARM_INS_VCVTR = 343 , ARM_INS_VCVTT = 344 , ARM_INS_VDIV = 345 , ARM_INS_VDUP = 346 , ARM_INS_VEOR = 347 , ARM_INS_VEXT = 348 , ARM_INS_VFMA = 349 , ARM_INS_VFMS = 350 , ARM_INS_VFNMA = 351 , ARM_INS_VFNMS = 352 , ARM_INS_VHADD = 353 , ARM_INS_VHSUB = 354 , ARM_INS_VINS = 355 , ARM_INS_VJCVT = 356 , ARM_INS_VLD1 = 357 , ARM_INS_VLD2 = 358 , ARM_INS_VLD3 = 359 , ARM_INS_VLD4 = 360 , ARM_INS_VLDMDB = 361 , ARM_INS_VLDMIA = 362 , ARM_INS_VLDR = 363 , ARM_INS_VLLDM = 364 , ARM_INS_VLSTM = 365 , ARM_INS_VMAX = 366 , ARM_INS_VMAXNM = 367 , ARM_INS_VMIN = 368 , ARM_INS_VMINNM = 369 , ARM_INS_VMLA = 370 , ARM_INS_VMLAL = 371 , ARM_INS_VMLS = 372 , ARM_INS_VMLSL = 373 , ARM_INS_VMOV = 374 , ARM_INS_VMOVL = 375 , ARM_INS_VMOVN = 376 , ARM_INS_VMOVX = 377 , ARM_INS_VMRS = 378 , ARM_INS_VMSR = 379 , ARM_INS_VMUL = 380 , ARM_INS_VMULL = 381 , ARM_INS_VMVN = 382 , ARM_INS_VNEG = 383 , ARM_INS_VNMLA = 384 , ARM_INS_VNMLS = 385 , ARM_INS_VNMUL = 386 , ARM_INS_VORN = 387 , ARM_INS_VORR = 388 , ARM_INS_VPADAL = 389 , ARM_INS_VPADD = 390 , ARM_INS_VPADDL = 391 , ARM_INS_VPMAX = 392 , ARM_INS_VPMIN = 393 , ARM_INS_VPOP = 394 , ARM_INS_VPUSH = 395 , ARM_INS_VQABS = 396 , ARM_INS_VQADD = 397 , ARM_INS_VQDMLAL = 398 , ARM_INS_VQDMLSL = 399 , ARM_INS_VQDMULH = 400 , ARM_INS_VQDMULL = 401 , ARM_INS_VQMOVN = 402 , ARM_INS_VQMOVUN = 403 , ARM_INS_VQNEG = 404 , ARM_INS_VQRDMLAH = 405 , ARM_INS_VQRDMLSH = 406 , ARM_INS_VQRDMULH = 407 , ARM_INS_VQRSHL = 408 , ARM_INS_VQRSHRN = 409 , ARM_INS_VQRSHRUN = 410 , ARM_INS_VQSHL = 411 , ARM_INS_VQSHLU = 412 , ARM_INS_VQSHRN = 413 , ARM_INS_VQSHRUN = 414 , ARM_INS_VQSUB = 415 , ARM_INS_VRADDHN = 416 , ARM_INS_VRECPE = 417 , ARM_INS_VRECPS = 418 , ARM_INS_VREV16 = 419 , ARM_INS_VREV32 = 420 , ARM_INS_VREV64 = 421 , ARM_INS_VRHADD = 422 , ARM_INS_VRINTA = 423 , ARM_INS_VRINTM = 424 , ARM_INS_VRINTN = 425 , ARM_INS_VRINTP = 426 , ARM_INS_VRINTR = 427 , ARM_INS_VRINTX = 428 , ARM_INS_VRINTZ = 429 , ARM_INS_VRSHL = 430 , ARM_INS_VRSHR = 431 , ARM_INS_VRSHRN = 432 , ARM_INS_VRSQRTE = 433 , ARM_INS_VRSQRTS = 434 , ARM_INS_VRSRA = 435 , ARM_INS_VRSUBHN = 436 , ARM_INS_VSDOT = 437 , ARM_INS_VSELEQ = 438 , ARM_INS_VSELGE = 439 , ARM_INS_VSELGT = 440 , ARM_INS_VSELVS = 441 , ARM_INS_VSHL = 442 , ARM_INS_VSHLL = 443 , ARM_INS_VSHR = 444 , ARM_INS_VSHRN = 445 , ARM_INS_VSLI = 446 , ARM_INS_VSQRT = 447 , ARM_INS_VSRA = 448 , ARM_INS_VSRI = 449 , ARM_INS_VST1 = 450 , ARM_INS_VST2 = 451 , ARM_INS_VST3 = 452 , ARM_INS_VST4 = 453 , ARM_INS_VSTMDB = 454 , ARM_INS_VSTMIA = 455 , ARM_INS_VSTR = 456 , ARM_INS_VSUB = 457 , ARM_INS_VSUBHN = 458 , ARM_INS_VSUBL = 459 , ARM_INS_VSUBW = 460 , ARM_INS_VSWP = 461 , ARM_INS_VTBL = 462 , ARM_INS_VTBX = 463 , ARM_INS_VTRN = 464 , ARM_INS_VTST = 465 , ARM_INS_VUDOT = 466 , ARM_INS_VUZP = 467 , ARM_INS_VZIP = 468 , ARM_INS_WFE = 469 , ARM_INS_WFI = 470 , ARM_INS_YIELD = 471 , ARM_INS_ENDING = 472 , } # [repr (u32)] # [doc = " Group of ARM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] ARM_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] ARM_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM_GRP_BRANCH_RELATIVE = 7 , ARM_GRP_CRYPTO = 128 , ARM_GRP_DATABARRIER = 129 , ARM_GRP_DIVIDE = 130 , ARM_GRP_FPARMV8 = 131 , ARM_GRP_MULTPRO = 132 , ARM_GRP_NEON = 133 , ARM_GRP_T2EXTRACTPACK = 134 , ARM_GRP_THUMB2DSP = 135 , ARM_GRP_TRUSTZONE = 136 , ARM_GRP_V4T = 137 , ARM_GRP_V5T = 138 , ARM_GRP_V5TE = 139 , ARM_GRP_V6 = 140 , ARM_GRP_V6T2 = 141 , ARM_GRP_V7 = 142 , ARM_GRP_V8 = 143 , ARM_GRP_VFP2 = 144 , ARM_GRP_VFP3 = 145 , ARM_GRP_VFP4 = 146 , ARM_GRP_ARM = 147 , ARM_GRP_MCLASS = 148 , ARM_GRP_NOTMCLASS = 149 , ARM_GRP_THUMB = 150 , ARM_GRP_THUMB1ONLY = 151 , ARM_GRP_THUMB2 = 152 , ARM_GRP_PREV8 = 153 , ARM_GRP_FPVMLX = 154 , ARM_GRP_MULOPS = 155 , ARM_GRP_CRC = 156 , ARM_GRP_DPVFP = 157 , ARM_GRP_V6M = 158 , ARM_GRP_VIRTUALIZATION = 159 , ARM_GRP_ENDING = 160 , } # [repr (u32)] # [doc = " ARM64 shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_shifter { ARM64_SFT_INVALID = 0 , ARM64_SFT_LSL = 1 , ARM64_SFT_MSL = 2 , ARM64_SFT_LSR = 3 , ARM64_SFT_ASR = 4 , ARM64_SFT_ROR = 5 , } # [repr (u32)] # [doc = " ARM64 extender type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_extender { ARM64_EXT_INVALID = 0 , ARM64_EXT_UXTB = 1 , ARM64_EXT_UXTH = 2 , ARM64_EXT_UXTW = 3 , ARM64_EXT_UXTX = 4 , ARM64_EXT_SXTB = 5 , ARM64_EXT_SXTH = 6 , ARM64_EXT_SXTW = 7 , ARM64_EXT_SXTX = 8 , } # [repr (u32)] # [doc = " ARM64 condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_cc { ARM64_CC_INVALID = 0 , # [doc = "< Equal"] ARM64_CC_EQ = 1 , # [doc = "< Not equal:                 Not equal, or unordered"] ARM64_CC_NE = 2 , # [doc = "< Unsigned higher or same:   >, ==, or unordered"] ARM64_CC_HS = 3 , # [doc = "< Unsigned lower or same:    Less than"] ARM64_CC_LO = 4 , # [doc = "< Minus, negative:           Less than"] ARM64_CC_MI = 5 , # [doc = "< Plus, positive or zero:    >, ==, or unordered"] ARM64_CC_PL = 6 , # [doc = "< Overflow:                  Unordered"] ARM64_CC_VS = 7 , # [doc = "< No overflow:               Ordered"] ARM64_CC_VC = 8 , # [doc = "< Unsigned higher:           Greater than, or unordered"] ARM64_CC_HI = 9 , # [doc = "< Unsigned lower or same:    Less than or equal"] ARM64_CC_LS = 10 , # [doc = "< Greater than or equal:     Greater than or equal"] ARM64_CC_GE = 11 , # [doc = "< Less than:                 Less than, or unordered"] ARM64_CC_LT = 12 , # [doc = "< Signed greater than:       Greater than"] ARM64_CC_GT = 13 , # [doc = "< Signed less than or equal: <, ==, or unordered"] ARM64_CC_LE = 14 , # [doc = "< Always (unconditional):    Always (unconditional)"] ARM64_CC_AL = 15 , # [doc = "< Always (unconditional):   Always (unconditional)"] ARM64_CC_NV = 16 , } impl arm64_sysreg { pub const ARM64_SYSREG_DBGDTRTX_EL0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_DBGDTRRX_EL0 ; } impl arm64_sysreg { pub const ARM64_SYSREG_TRCEXTINSELR0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TRCEXTINSELR ; } impl arm64_sysreg { pub const ARM64_SYSREG_VSCTLR_EL2 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TTBR0_EL2 ; } # [repr (u32)] # [doc = " System registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sysreg { ARM64_SYSREG_INVALID = 0 , ARM64_SYSREG_ACCDATA_EL1 = 50821 , ARM64_SYSREG_ACTLR_EL1 = 49281 , ARM64_SYSREG_ACTLR_EL2 = 57473 , ARM64_SYSREG_ACTLR_EL3 = 61569 , ARM64_SYSREG_AFSR0_EL1 = 49800 , ARM64_SYSREG_AFSR0_EL12 = 60040 , ARM64_SYSREG_AFSR0_EL2 = 57992 , ARM64_SYSREG_AFSR0_EL3 = 62088 , ARM64_SYSREG_AFSR1_EL1 = 49801 , ARM64_SYSREG_AFSR1_EL12 = 60041 , ARM64_SYSREG_AFSR1_EL2 = 57993 , ARM64_SYSREG_AFSR1_EL3 = 62089 , ARM64_SYSREG_AIDR_EL1 = 51207 , ARM64_SYSREG_AMAIR_EL1 = 50456 , ARM64_SYSREG_AMAIR_EL12 = 60696 , ARM64_SYSREG_AMAIR_EL2 = 58648 , ARM64_SYSREG_AMAIR_EL3 = 62744 , ARM64_SYSREG_AMCFGR_EL0 = 56977 , ARM64_SYSREG_AMCGCR_EL0 = 56978 , ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980 , ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984 , ARM64_SYSREG_AMCNTENSET0_EL0 = 56981 , ARM64_SYSREG_AMCNTENSET1_EL0 = 56985 , ARM64_SYSREG_AMCR_EL0 = 56976 , ARM64_SYSREG_AMEVCNTR00_EL0 = 56992 , ARM64_SYSREG_AMEVCNTR01_EL0 = 56993 , ARM64_SYSREG_AMEVCNTR02_EL0 = 56994 , ARM64_SYSREG_AMEVCNTR03_EL0 = 56995 , ARM64_SYSREG_AMEVCNTR10_EL0 = 57056 , ARM64_SYSREG_AMEVCNTR110_EL0 = 57066 , ARM64_SYSREG_AMEVCNTR111_EL0 = 57067 , ARM64_SYSREG_AMEVCNTR112_EL0 = 57068 , ARM64_SYSREG_AMEVCNTR113_EL0 = 57069 , ARM64_SYSREG_AMEVCNTR114_EL0 = 57070 , ARM64_SYSREG_AMEVCNTR115_EL0 = 57071 , ARM64_SYSREG_AMEVCNTR11_EL0 = 57057 , ARM64_SYSREG_AMEVCNTR12_EL0 = 57058 , ARM64_SYSREG_AMEVCNTR13_EL0 = 57059 , ARM64_SYSREG_AMEVCNTR14_EL0 = 57060 , ARM64_SYSREG_AMEVCNTR15_EL0 = 57061 , ARM64_SYSREG_AMEVCNTR16_EL0 = 57062 , ARM64_SYSREG_AMEVCNTR17_EL0 = 57063 , ARM64_SYSREG_AMEVCNTR18_EL0 = 57064 , ARM64_SYSREG_AMEVCNTR19_EL0 = 57065 , ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 59072 , ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 59082 , ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 59083 , ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 59084 , ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 59085 , ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 59086 , ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 59087 , ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 59073 , ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 59074 , ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 59075 , ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 59076 , ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 59077 , ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 59078 , ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 59079 , ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 59080 , ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 59081 , ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 59088 , ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 59098 , ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 59099 , ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 59100 , ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 59101 , ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 59102 , ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 59103 , ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 59089 , ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 59090 , ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 59091 , ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 59092 , ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 59093 , ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 59094 , ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 59095 , ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 59096 , ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 59097 , ARM64_SYSREG_AMEVTYPER00_EL0 = 57008 , ARM64_SYSREG_AMEVTYPER01_EL0 = 57009 , ARM64_SYSREG_AMEVTYPER02_EL0 = 57010 , ARM64_SYSREG_AMEVTYPER03_EL0 = 57011 , ARM64_SYSREG_AMEVTYPER10_EL0 = 57072 , ARM64_SYSREG_AMEVTYPER110_EL0 = 57082 , ARM64_SYSREG_AMEVTYPER111_EL0 = 57083 , ARM64_SYSREG_AMEVTYPER112_EL0 = 57084 , ARM64_SYSREG_AMEVTYPER113_EL0 = 57085 , ARM64_SYSREG_AMEVTYPER114_EL0 = 57086 , ARM64_SYSREG_AMEVTYPER115_EL0 = 57087 , ARM64_SYSREG_AMEVTYPER11_EL0 = 57073 , ARM64_SYSREG_AMEVTYPER12_EL0 = 57074 , ARM64_SYSREG_AMEVTYPER13_EL0 = 57075 , ARM64_SYSREG_AMEVTYPER14_EL0 = 57076 , ARM64_SYSREG_AMEVTYPER15_EL0 = 57077 , ARM64_SYSREG_AMEVTYPER16_EL0 = 57078 , ARM64_SYSREG_AMEVTYPER17_EL0 = 57079 , ARM64_SYSREG_AMEVTYPER18_EL0 = 57080 , ARM64_SYSREG_AMEVTYPER19_EL0 = 57081 , ARM64_SYSREG_AMUSERENR_EL0 = 56979 , ARM64_SYSREG_APDAKEYHI_EL1 = 49425 , ARM64_SYSREG_APDAKEYLO_EL1 = 49424 , ARM64_SYSREG_APDBKEYHI_EL1 = 49427 , ARM64_SYSREG_APDBKEYLO_EL1 = 49426 , ARM64_SYSREG_APGAKEYHI_EL1 = 49433 , ARM64_SYSREG_APGAKEYLO_EL1 = 49432 , ARM64_SYSREG_APIAKEYHI_EL1 = 49417 , ARM64_SYSREG_APIAKEYLO_EL1 = 49416 , ARM64_SYSREG_APIBKEYHI_EL1 = 49419 , ARM64_SYSREG_APIBKEYLO_EL1 = 49418 , ARM64_SYSREG_BRBCR_EL1 = 35968 , ARM64_SYSREG_BRBCR_EL12 = 44160 , ARM64_SYSREG_BRBCR_EL2 = 42112 , ARM64_SYSREG_BRBFCR_EL1 = 35969 , ARM64_SYSREG_BRBIDR0_EL1 = 35984 , ARM64_SYSREG_BRBINF0_EL1 = 35840 , ARM64_SYSREG_BRBINF10_EL1 = 35920 , ARM64_SYSREG_BRBINF11_EL1 = 35928 , ARM64_SYSREG_BRBINF12_EL1 = 35936 , ARM64_SYSREG_BRBINF13_EL1 = 35944 , ARM64_SYSREG_BRBINF14_EL1 = 35952 , ARM64_SYSREG_BRBINF15_EL1 = 35960 , ARM64_SYSREG_BRBINF16_EL1 = 35844 , ARM64_SYSREG_BRBINF17_EL1 = 35852 , ARM64_SYSREG_BRBINF18_EL1 = 35860 , ARM64_SYSREG_BRBINF19_EL1 = 35868 , ARM64_SYSREG_BRBINF1_EL1 = 35848 , ARM64_SYSREG_BRBINF20_EL1 = 35876 , ARM64_SYSREG_BRBINF21_EL1 = 35884 , ARM64_SYSREG_BRBINF22_EL1 = 35892 , ARM64_SYSREG_BRBINF23_EL1 = 35900 , ARM64_SYSREG_BRBINF24_EL1 = 35908 , ARM64_SYSREG_BRBINF25_EL1 = 35916 , ARM64_SYSREG_BRBINF26_EL1 = 35924 , ARM64_SYSREG_BRBINF27_EL1 = 35932 , ARM64_SYSREG_BRBINF28_EL1 = 35940 , ARM64_SYSREG_BRBINF29_EL1 = 35948 , ARM64_SYSREG_BRBINF2_EL1 = 35856 , ARM64_SYSREG_BRBINF30_EL1 = 35956 , ARM64_SYSREG_BRBINF31_EL1 = 35964 , ARM64_SYSREG_BRBINF3_EL1 = 35864 , ARM64_SYSREG_BRBINF4_EL1 = 35872 , ARM64_SYSREG_BRBINF5_EL1 = 35880 , ARM64_SYSREG_BRBINF6_EL1 = 35888 , ARM64_SYSREG_BRBINF7_EL1 = 35896 , ARM64_SYSREG_BRBINF8_EL1 = 35904 , ARM64_SYSREG_BRBINF9_EL1 = 35912 , ARM64_SYSREG_BRBINFINJ_EL1 = 35976 , ARM64_SYSREG_BRBSRC0_EL1 = 35841 , ARM64_SYSREG_BRBSRC10_EL1 = 35921 , ARM64_SYSREG_BRBSRC11_EL1 = 35929 , ARM64_SYSREG_BRBSRC12_EL1 = 35937 , ARM64_SYSREG_BRBSRC13_EL1 = 35945 , ARM64_SYSREG_BRBSRC14_EL1 = 35953 , ARM64_SYSREG_BRBSRC15_EL1 = 35961 , ARM64_SYSREG_BRBSRC16_EL1 = 35845 , ARM64_SYSREG_BRBSRC17_EL1 = 35853 , ARM64_SYSREG_BRBSRC18_EL1 = 35861 , ARM64_SYSREG_BRBSRC19_EL1 = 35869 , ARM64_SYSREG_BRBSRC1_EL1 = 35849 , ARM64_SYSREG_BRBSRC20_EL1 = 35877 , ARM64_SYSREG_BRBSRC21_EL1 = 35885 , ARM64_SYSREG_BRBSRC22_EL1 = 35893 , ARM64_SYSREG_BRBSRC23_EL1 = 35901 , ARM64_SYSREG_BRBSRC24_EL1 = 35909 , ARM64_SYSREG_BRBSRC25_EL1 = 35917 , ARM64_SYSREG_BRBSRC26_EL1 = 35925 , ARM64_SYSREG_BRBSRC27_EL1 = 35933 , ARM64_SYSREG_BRBSRC28_EL1 = 35941 , ARM64_SYSREG_BRBSRC29_EL1 = 35949 , ARM64_SYSREG_BRBSRC2_EL1 = 35857 , ARM64_SYSREG_BRBSRC30_EL1 = 35957 , ARM64_SYSREG_BRBSRC31_EL1 = 35965 , ARM64_SYSREG_BRBSRC3_EL1 = 35865 , ARM64_SYSREG_BRBSRC4_EL1 = 35873 , ARM64_SYSREG_BRBSRC5_EL1 = 35881 , ARM64_SYSREG_BRBSRC6_EL1 = 35889 , ARM64_SYSREG_BRBSRC7_EL1 = 35897 , ARM64_SYSREG_BRBSRC8_EL1 = 35905 , ARM64_SYSREG_BRBSRC9_EL1 = 35913 , ARM64_SYSREG_BRBSRCINJ_EL1 = 35977 , ARM64_SYSREG_BRBTGT0_EL1 = 35842 , ARM64_SYSREG_BRBTGT10_EL1 = 35922 , ARM64_SYSREG_BRBTGT11_EL1 = 35930 , ARM64_SYSREG_BRBTGT12_EL1 = 35938 , ARM64_SYSREG_BRBTGT13_EL1 = 35946 , ARM64_SYSREG_BRBTGT14_EL1 = 35954 , ARM64_SYSREG_BRBTGT15_EL1 = 35962 , ARM64_SYSREG_BRBTGT16_EL1 = 35846 , ARM64_SYSREG_BRBTGT17_EL1 = 35854 , ARM64_SYSREG_BRBTGT18_EL1 = 35862 , ARM64_SYSREG_BRBTGT19_EL1 = 35870 , ARM64_SYSREG_BRBTGT1_EL1 = 35850 , ARM64_SYSREG_BRBTGT20_EL1 = 35878 , ARM64_SYSREG_BRBTGT21_EL1 = 35886 , ARM64_SYSREG_BRBTGT22_EL1 = 35894 , ARM64_SYSREG_BRBTGT23_EL1 = 35902 , ARM64_SYSREG_BRBTGT24_EL1 = 35910 , ARM64_SYSREG_BRBTGT25_EL1 = 35918 , ARM64_SYSREG_BRBTGT26_EL1 = 35926 , ARM64_SYSREG_BRBTGT27_EL1 = 35934 , ARM64_SYSREG_BRBTGT28_EL1 = 35942 , ARM64_SYSREG_BRBTGT29_EL1 = 35950 , ARM64_SYSREG_BRBTGT2_EL1 = 35858 , ARM64_SYSREG_BRBTGT30_EL1 = 35958 , ARM64_SYSREG_BRBTGT31_EL1 = 35966 , ARM64_SYSREG_BRBTGT3_EL1 = 35866 , ARM64_SYSREG_BRBTGT4_EL1 = 35874 , ARM64_SYSREG_BRBTGT5_EL1 = 35882 , ARM64_SYSREG_BRBTGT6_EL1 = 35890 , ARM64_SYSREG_BRBTGT7_EL1 = 35898 , ARM64_SYSREG_BRBTGT8_EL1 = 35906 , ARM64_SYSREG_BRBTGT9_EL1 = 35914 , ARM64_SYSREG_BRBTGTINJ_EL1 = 35978 , ARM64_SYSREG_BRBTS_EL1 = 35970 , ARM64_SYSREG_CCSIDR2_EL1 = 51202 , ARM64_SYSREG_CCSIDR_EL1 = 51200 , ARM64_SYSREG_CLIDR_EL1 = 51201 , ARM64_SYSREG_CNTFRQ_EL0 = 57088 , ARM64_SYSREG_CNTHCTL_EL2 = 59144 , ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177 , ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178 , ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176 , ARM64_SYSREG_CNTHP_CTL_EL2 = 59153 , ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154 , ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152 , ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169 , ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170 , ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168 , ARM64_SYSREG_CNTHV_CTL_EL2 = 59161 , ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162 , ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160 , ARM64_SYSREG_CNTISCALE_EL2 = 59141 , ARM64_SYSREG_CNTKCTL_EL1 = 50952 , ARM64_SYSREG_CNTKCTL_EL12 = 61192 , ARM64_SYSREG_CNTPCTSS_EL0 = 57093 , ARM64_SYSREG_CNTPCT_EL0 = 57089 , ARM64_SYSREG_CNTPOFF_EL2 = 59142 , ARM64_SYSREG_CNTPS_CTL_EL1 = 65297 , ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298 , ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296 , ARM64_SYSREG_CNTP_CTL_EL0 = 57105 , ARM64_SYSREG_CNTP_CTL_EL02 = 61201 , ARM64_SYSREG_CNTP_CVAL_EL0 = 57106 , ARM64_SYSREG_CNTP_CVAL_EL02 = 61202 , ARM64_SYSREG_CNTP_TVAL_EL0 = 57104 , ARM64_SYSREG_CNTP_TVAL_EL02 = 61200 , ARM64_SYSREG_CNTSCALE_EL2 = 59140 , ARM64_SYSREG_CNTVCTSS_EL0 = 57094 , ARM64_SYSREG_CNTVCT_EL0 = 57090 , ARM64_SYSREG_CNTVFRQ_EL2 = 59143 , ARM64_SYSREG_CNTVOFF_EL2 = 59139 , ARM64_SYSREG_CNTV_CTL_EL0 = 57113 , ARM64_SYSREG_CNTV_CTL_EL02 = 61209 , ARM64_SYSREG_CNTV_CVAL_EL0 = 57114 , ARM64_SYSREG_CNTV_CVAL_EL02 = 61210 , ARM64_SYSREG_CNTV_TVAL_EL0 = 57112 , ARM64_SYSREG_CNTV_TVAL_EL02 = 61208 , ARM64_SYSREG_CONTEXTIDR_EL1 = 50817 , ARM64_SYSREG_CONTEXTIDR_EL12 = 61057 , ARM64_SYSREG_CONTEXTIDR_EL2 = 59009 , ARM64_SYSREG_CPACR_EL1 = 49282 , ARM64_SYSREG_CPACR_EL12 = 59522 , ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424 , ARM64_SYSREG_CPTR_EL2 = 57482 , ARM64_SYSREG_CPTR_EL3 = 61578 , ARM64_SYSREG_CSSELR_EL1 = 53248 , ARM64_SYSREG_CTR_EL0 = 55297 , ARM64_SYSREG_CURRENTEL = 49682 , ARM64_SYSREG_DACR32_EL2 = 57728 , ARM64_SYSREG_DAIF = 55825 , ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782 , ARM64_SYSREG_DBGBCR0_EL1 = 32773 , ARM64_SYSREG_DBGBCR10_EL1 = 32853 , ARM64_SYSREG_DBGBCR11_EL1 = 32861 , ARM64_SYSREG_DBGBCR12_EL1 = 32869 , ARM64_SYSREG_DBGBCR13_EL1 = 32877 , ARM64_SYSREG_DBGBCR14_EL1 = 32885 , ARM64_SYSREG_DBGBCR15_EL1 = 32893 , ARM64_SYSREG_DBGBCR1_EL1 = 32781 , ARM64_SYSREG_DBGBCR2_EL1 = 32789 , ARM64_SYSREG_DBGBCR3_EL1 = 32797 , ARM64_SYSREG_DBGBCR4_EL1 = 32805 , ARM64_SYSREG_DBGBCR5_EL1 = 32813 , ARM64_SYSREG_DBGBCR6_EL1 = 32821 , ARM64_SYSREG_DBGBCR7_EL1 = 32829 , ARM64_SYSREG_DBGBCR8_EL1 = 32837 , ARM64_SYSREG_DBGBCR9_EL1 = 32845 , ARM64_SYSREG_DBGBVR0_EL1 = 32772 , ARM64_SYSREG_DBGBVR10_EL1 = 32852 , ARM64_SYSREG_DBGBVR11_EL1 = 32860 , ARM64_SYSREG_DBGBVR12_EL1 = 32868 , ARM64_SYSREG_DBGBVR13_EL1 = 32876 , ARM64_SYSREG_DBGBVR14_EL1 = 32884 , ARM64_SYSREG_DBGBVR15_EL1 = 32892 , ARM64_SYSREG_DBGBVR1_EL1 = 32780 , ARM64_SYSREG_DBGBVR2_EL1 = 32788 , ARM64_SYSREG_DBGBVR3_EL1 = 32796 , ARM64_SYSREG_DBGBVR4_EL1 = 32804 , ARM64_SYSREG_DBGBVR5_EL1 = 32812 , ARM64_SYSREG_DBGBVR6_EL1 = 32820 , ARM64_SYSREG_DBGBVR7_EL1 = 32828 , ARM64_SYSREG_DBGBVR8_EL1 = 32836 , ARM64_SYSREG_DBGBVR9_EL1 = 32844 , ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742 , ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734 , ARM64_SYSREG_DBGDTRRX_EL0 = 38952 , ARM64_SYSREG_DBGDTR_EL0 = 38944 , ARM64_SYSREG_DBGPRCR_EL1 = 32932 , ARM64_SYSREG_DBGVCR32_EL2 = 41016 , ARM64_SYSREG_DBGWCR0_EL1 = 32775 , ARM64_SYSREG_DBGWCR10_EL1 = 32855 , ARM64_SYSREG_DBGWCR11_EL1 = 32863 , ARM64_SYSREG_DBGWCR12_EL1 = 32871 , ARM64_SYSREG_DBGWCR13_EL1 = 32879 , ARM64_SYSREG_DBGWCR14_EL1 = 32887 , ARM64_SYSREG_DBGWCR15_EL1 = 32895 , ARM64_SYSREG_DBGWCR1_EL1 = 32783 , ARM64_SYSREG_DBGWCR2_EL1 = 32791 , ARM64_SYSREG_DBGWCR3_EL1 = 32799 , ARM64_SYSREG_DBGWCR4_EL1 = 32807 , ARM64_SYSREG_DBGWCR5_EL1 = 32815 , ARM64_SYSREG_DBGWCR6_EL1 = 32823 , ARM64_SYSREG_DBGWCR7_EL1 = 32831 , ARM64_SYSREG_DBGWCR8_EL1 = 32839 , ARM64_SYSREG_DBGWCR9_EL1 = 32847 , ARM64_SYSREG_DBGWVR0_EL1 = 32774 , ARM64_SYSREG_DBGWVR10_EL1 = 32854 , ARM64_SYSREG_DBGWVR11_EL1 = 32862 , ARM64_SYSREG_DBGWVR12_EL1 = 32870 , ARM64_SYSREG_DBGWVR13_EL1 = 32878 , ARM64_SYSREG_DBGWVR14_EL1 = 32886 , ARM64_SYSREG_DBGWVR15_EL1 = 32894 , ARM64_SYSREG_DBGWVR1_EL1 = 32782 , ARM64_SYSREG_DBGWVR2_EL1 = 32790 , ARM64_SYSREG_DBGWVR3_EL1 = 32798 , ARM64_SYSREG_DBGWVR4_EL1 = 32806 , ARM64_SYSREG_DBGWVR5_EL1 = 32814 , ARM64_SYSREG_DBGWVR6_EL1 = 32822 , ARM64_SYSREG_DBGWVR7_EL1 = 32830 , ARM64_SYSREG_DBGWVR8_EL1 = 32838 , ARM64_SYSREG_DBGWVR9_EL1 = 32846 , ARM64_SYSREG_DCZID_EL0 = 55303 , ARM64_SYSREG_DISR_EL1 = 50697 , ARM64_SYSREG_DIT = 55829 , ARM64_SYSREG_DLR_EL0 = 55849 , ARM64_SYSREG_DSPSR_EL0 = 55848 , ARM64_SYSREG_ELR_EL1 = 49665 , ARM64_SYSREG_ELR_EL12 = 59905 , ARM64_SYSREG_ELR_EL2 = 57857 , ARM64_SYSREG_ELR_EL3 = 61953 , ARM64_SYSREG_ERRIDR_EL1 = 49816 , ARM64_SYSREG_ERRSELR_EL1 = 49817 , ARM64_SYSREG_ERXADDR_EL1 = 49827 , ARM64_SYSREG_ERXCTLR_EL1 = 49825 , ARM64_SYSREG_ERXFR_EL1 = 49824 , ARM64_SYSREG_ERXMISC0_EL1 = 49832 , ARM64_SYSREG_ERXMISC1_EL1 = 49833 , ARM64_SYSREG_ERXMISC2_EL1 = 49834 , ARM64_SYSREG_ERXMISC3_EL1 = 49835 , ARM64_SYSREG_ERXPFGCDN_EL1 = 49830 , ARM64_SYSREG_ERXPFGCTL_EL1 = 49829 , ARM64_SYSREG_ERXPFGF_EL1 = 49828 , ARM64_SYSREG_ERXSTATUS_EL1 = 49826 , ARM64_SYSREG_ESR_EL1 = 49808 , ARM64_SYSREG_ESR_EL12 = 60048 , ARM64_SYSREG_ESR_EL2 = 58000 , ARM64_SYSREG_ESR_EL3 = 62096 , ARM64_SYSREG_FAR_EL1 = 49920 , ARM64_SYSREG_FAR_EL12 = 60160 , ARM64_SYSREG_FAR_EL2 = 58112 , ARM64_SYSREG_FAR_EL3 = 62208 , ARM64_SYSREG_FPCR = 55840 , ARM64_SYSREG_FPEXC32_EL2 = 58008 , ARM64_SYSREG_FPSR = 55841 , ARM64_SYSREG_GCR_EL1 = 49286 , ARM64_SYSREG_GMID_EL1 = 51204 , ARM64_SYSREG_GPCCR_EL3 = 61710 , ARM64_SYSREG_GPTBR_EL3 = 61708 , ARM64_SYSREG_HACR_EL2 = 57487 , ARM64_SYSREG_HCRX_EL2 = 57490 , ARM64_SYSREG_HCR_EL2 = 57480 , ARM64_SYSREG_HDFGRTR_EL2 = 57740 , ARM64_SYSREG_HDFGWTR_EL2 = 57741 , ARM64_SYSREG_HFGITR_EL2 = 57486 , ARM64_SYSREG_HFGRTR_EL2 = 57484 , ARM64_SYSREG_HFGWTR_EL2 = 57485 , ARM64_SYSREG_HPFAR_EL2 = 58116 , ARM64_SYSREG_HSTR_EL2 = 57483 , ARM64_SYSREG_ICC_AP0R0_EL1 = 50756 , ARM64_SYSREG_ICC_AP0R1_EL1 = 50757 , ARM64_SYSREG_ICC_AP0R2_EL1 = 50758 , ARM64_SYSREG_ICC_AP0R3_EL1 = 50759 , ARM64_SYSREG_ICC_AP1R0_EL1 = 50760 , ARM64_SYSREG_ICC_AP1R1_EL1 = 50761 , ARM64_SYSREG_ICC_AP1R2_EL1 = 50762 , ARM64_SYSREG_ICC_AP1R3_EL1 = 50763 , ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782 , ARM64_SYSREG_ICC_BPR0_EL1 = 50755 , ARM64_SYSREG_ICC_BPR1_EL1 = 50787 , ARM64_SYSREG_ICC_CTLR_EL1 = 50788 , ARM64_SYSREG_ICC_CTLR_EL3 = 63076 , ARM64_SYSREG_ICC_DIR_EL1 = 50777 , ARM64_SYSREG_ICC_EOIR0_EL1 = 50753 , ARM64_SYSREG_ICC_EOIR1_EL1 = 50785 , ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754 , ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786 , ARM64_SYSREG_ICC_IAR0_EL1 = 50752 , ARM64_SYSREG_ICC_IAR1_EL1 = 50784 , ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790 , ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791 , ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079 , ARM64_SYSREG_ICC_PMR_EL1 = 49712 , ARM64_SYSREG_ICC_RPR_EL1 = 50779 , ARM64_SYSREG_ICC_SGI0R_EL1 = 50783 , ARM64_SYSREG_ICC_SGI1R_EL1 = 50781 , ARM64_SYSREG_ICC_SRE_EL1 = 50789 , ARM64_SYSREG_ICC_SRE_EL2 = 58957 , ARM64_SYSREG_ICC_SRE_EL3 = 63077 , ARM64_SYSREG_ICH_AP0R0_EL2 = 58944 , ARM64_SYSREG_ICH_AP0R1_EL2 = 58945 , ARM64_SYSREG_ICH_AP0R2_EL2 = 58946 , ARM64_SYSREG_ICH_AP0R3_EL2 = 58947 , ARM64_SYSREG_ICH_AP1R0_EL2 = 58952 , ARM64_SYSREG_ICH_AP1R1_EL2 = 58953 , ARM64_SYSREG_ICH_AP1R2_EL2 = 58954 , ARM64_SYSREG_ICH_AP1R3_EL2 = 58955 , ARM64_SYSREG_ICH_EISR_EL2 = 58971 , ARM64_SYSREG_ICH_ELRSR_EL2 = 58973 , ARM64_SYSREG_ICH_HCR_EL2 = 58968 , ARM64_SYSREG_ICH_LR0_EL2 = 58976 , ARM64_SYSREG_ICH_LR10_EL2 = 58986 , ARM64_SYSREG_ICH_LR11_EL2 = 58987 , ARM64_SYSREG_ICH_LR12_EL2 = 58988 , ARM64_SYSREG_ICH_LR13_EL2 = 58989 , ARM64_SYSREG_ICH_LR14_EL2 = 58990 , ARM64_SYSREG_ICH_LR15_EL2 = 58991 , ARM64_SYSREG_ICH_LR1_EL2 = 58977 , ARM64_SYSREG_ICH_LR2_EL2 = 58978 , ARM64_SYSREG_ICH_LR3_EL2 = 58979 , ARM64_SYSREG_ICH_LR4_EL2 = 58980 , ARM64_SYSREG_ICH_LR5_EL2 = 58981 , ARM64_SYSREG_ICH_LR6_EL2 = 58982 , ARM64_SYSREG_ICH_LR7_EL2 = 58983 , ARM64_SYSREG_ICH_LR8_EL2 = 58984 , ARM64_SYSREG_ICH_LR9_EL2 = 58985 , ARM64_SYSREG_ICH_MISR_EL2 = 58970 , ARM64_SYSREG_ICH_VMCR_EL2 = 58975 , ARM64_SYSREG_ICH_VTR_EL2 = 58969 , ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196 , ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197 , ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192 , ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193 , ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200 , ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201 , ARM64_SYSREG_ID_AA64ISAR2_EL1 = 49202 , ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208 , ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209 , ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210 , ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184 , ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185 , ARM64_SYSREG_ID_AA64SMFR0_EL1 = 49189 , ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188 , ARM64_SYSREG_ID_AFR0_EL1 = 49163 , ARM64_SYSREG_ID_DFR0_EL1 = 49162 , ARM64_SYSREG_ID_ISAR0_EL1 = 49168 , ARM64_SYSREG_ID_ISAR1_EL1 = 49169 , ARM64_SYSREG_ID_ISAR2_EL1 = 49170 , ARM64_SYSREG_ID_ISAR3_EL1 = 49171 , ARM64_SYSREG_ID_ISAR4_EL1 = 49172 , ARM64_SYSREG_ID_ISAR5_EL1 = 49173 , ARM64_SYSREG_ID_ISAR6_EL1 = 49175 , ARM64_SYSREG_ID_MMFR0_EL1 = 49164 , ARM64_SYSREG_ID_MMFR1_EL1 = 49165 , ARM64_SYSREG_ID_MMFR2_EL1 = 49166 , ARM64_SYSREG_ID_MMFR3_EL1 = 49167 , ARM64_SYSREG_ID_MMFR4_EL1 = 49174 , ARM64_SYSREG_ID_MMFR5_EL1 = 49182 , ARM64_SYSREG_ID_PFR0_EL1 = 49160 , ARM64_SYSREG_ID_PFR1_EL1 = 49161 , ARM64_SYSREG_ID_PFR2_EL1 = 49180 , ARM64_SYSREG_IFSR32_EL2 = 57985 , ARM64_SYSREG_ISR_EL1 = 50696 , ARM64_SYSREG_LORC_EL1 = 50467 , ARM64_SYSREG_LOREA_EL1 = 50465 , ARM64_SYSREG_LORID_EL1 = 50471 , ARM64_SYSREG_LORN_EL1 = 50466 , ARM64_SYSREG_LORSA_EL1 = 50464 , ARM64_SYSREG_MAIR_EL1 = 50448 , ARM64_SYSREG_MAIR_EL12 = 60688 , ARM64_SYSREG_MAIR_EL2 = 58640 , ARM64_SYSREG_MAIR_EL3 = 62736 , ARM64_SYSREG_MDCCINT_EL1 = 32784 , ARM64_SYSREG_MDCCSR_EL0 = 38920 , ARM64_SYSREG_MDCR_EL2 = 57481 , ARM64_SYSREG_MDCR_EL3 = 61593 , ARM64_SYSREG_MDRAR_EL1 = 32896 , ARM64_SYSREG_MDSCR_EL1 = 32786 , ARM64_SYSREG_MFAR_EL3 = 62213 , ARM64_SYSREG_MIDR_EL1 = 49152 , ARM64_SYSREG_MPAM0_EL1 = 50473 , ARM64_SYSREG_MPAM1_EL1 = 50472 , ARM64_SYSREG_MPAM1_EL12 = 60712 , ARM64_SYSREG_MPAM2_EL2 = 58664 , ARM64_SYSREG_MPAM3_EL3 = 62760 , ARM64_SYSREG_MPAMHCR_EL2 = 58656 , ARM64_SYSREG_MPAMIDR_EL1 = 50468 , ARM64_SYSREG_MPAMSM_EL1 = 50475 , ARM64_SYSREG_MPAMVPM0_EL2 = 58672 , ARM64_SYSREG_MPAMVPM1_EL2 = 58673 , ARM64_SYSREG_MPAMVPM2_EL2 = 58674 , ARM64_SYSREG_MPAMVPM3_EL2 = 58675 , ARM64_SYSREG_MPAMVPM4_EL2 = 58676 , ARM64_SYSREG_MPAMVPM5_EL2 = 58677 , ARM64_SYSREG_MPAMVPM6_EL2 = 58678 , ARM64_SYSREG_MPAMVPM7_EL2 = 58679 , ARM64_SYSREG_MPAMVPMV_EL2 = 58657 , ARM64_SYSREG_MPIDR_EL1 = 49157 , ARM64_SYSREG_MPUIR_EL1 = 49156 , ARM64_SYSREG_MPUIR_EL2 = 57348 , ARM64_SYSREG_MVFR0_EL1 = 49176 , ARM64_SYSREG_MVFR1_EL1 = 49177 , ARM64_SYSREG_MVFR2_EL1 = 49178 , ARM64_SYSREG_NZCV = 55824 , ARM64_SYSREG_OSDLR_EL1 = 32924 , ARM64_SYSREG_OSDTRRX_EL1 = 32770 , ARM64_SYSREG_OSDTRTX_EL1 = 32794 , ARM64_SYSREG_OSECCR_EL1 = 32818 , ARM64_SYSREG_OSLAR_EL1 = 32900 , ARM64_SYSREG_OSLSR_EL1 = 32908 , ARM64_SYSREG_PAN = 49683 , ARM64_SYSREG_PAR_EL1 = 50080 , ARM64_SYSREG_PMBIDR_EL1 = 50391 , ARM64_SYSREG_PMBLIMITR_EL1 = 50384 , ARM64_SYSREG_PMBPTR_EL1 = 50385 , ARM64_SYSREG_PMBSR_EL1 = 50387 , ARM64_SYSREG_PMCCFILTR_EL0 = 57215 , ARM64_SYSREG_PMCCNTR_EL0 = 56552 , ARM64_SYSREG_PMCEID0_EL0 = 56550 , ARM64_SYSREG_PMCEID1_EL0 = 56551 , ARM64_SYSREG_PMCNTENCLR_EL0 = 56546 , ARM64_SYSREG_PMCNTENSET_EL0 = 56545 , ARM64_SYSREG_PMCR_EL0 = 56544 , ARM64_SYSREG_PMEVCNTR0_EL0 = 57152 , ARM64_SYSREG_PMEVCNTR10_EL0 = 57162 , ARM64_SYSREG_PMEVCNTR11_EL0 = 57163 , ARM64_SYSREG_PMEVCNTR12_EL0 = 57164 , ARM64_SYSREG_PMEVCNTR13_EL0 = 57165 , ARM64_SYSREG_PMEVCNTR14_EL0 = 57166 , ARM64_SYSREG_PMEVCNTR15_EL0 = 57167 , ARM64_SYSREG_PMEVCNTR16_EL0 = 57168 , ARM64_SYSREG_PMEVCNTR17_EL0 = 57169 , ARM64_SYSREG_PMEVCNTR18_EL0 = 57170 , ARM64_SYSREG_PMEVCNTR19_EL0 = 57171 , ARM64_SYSREG_PMEVCNTR1_EL0 = 57153 , ARM64_SYSREG_PMEVCNTR20_EL0 = 57172 , ARM64_SYSREG_PMEVCNTR21_EL0 = 57173 , ARM64_SYSREG_PMEVCNTR22_EL0 = 57174 , ARM64_SYSREG_PMEVCNTR23_EL0 = 57175 , ARM64_SYSREG_PMEVCNTR24_EL0 = 57176 , ARM64_SYSREG_PMEVCNTR25_EL0 = 57177 , ARM64_SYSREG_PMEVCNTR26_EL0 = 57178 , ARM64_SYSREG_PMEVCNTR27_EL0 = 57179 , ARM64_SYSREG_PMEVCNTR28_EL0 = 57180 , ARM64_SYSREG_PMEVCNTR29_EL0 = 57181 , ARM64_SYSREG_PMEVCNTR2_EL0 = 57154 , ARM64_SYSREG_PMEVCNTR30_EL0 = 57182 , ARM64_SYSREG_PMEVCNTR3_EL0 = 57155 , ARM64_SYSREG_PMEVCNTR4_EL0 = 57156 , ARM64_SYSREG_PMEVCNTR5_EL0 = 57157 , ARM64_SYSREG_PMEVCNTR6_EL0 = 57158 , ARM64_SYSREG_PMEVCNTR7_EL0 = 57159 , ARM64_SYSREG_PMEVCNTR8_EL0 = 57160 , ARM64_SYSREG_PMEVCNTR9_EL0 = 57161 , ARM64_SYSREG_PMEVTYPER0_EL0 = 57184 , ARM64_SYSREG_PMEVTYPER10_EL0 = 57194 , ARM64_SYSREG_PMEVTYPER11_EL0 = 57195 , ARM64_SYSREG_PMEVTYPER12_EL0 = 57196 , ARM64_SYSREG_PMEVTYPER13_EL0 = 57197 , ARM64_SYSREG_PMEVTYPER14_EL0 = 57198 , ARM64_SYSREG_PMEVTYPER15_EL0 = 57199 , ARM64_SYSREG_PMEVTYPER16_EL0 = 57200 , ARM64_SYSREG_PMEVTYPER17_EL0 = 57201 , ARM64_SYSREG_PMEVTYPER18_EL0 = 57202 , ARM64_SYSREG_PMEVTYPER19_EL0 = 57203 , ARM64_SYSREG_PMEVTYPER1_EL0 = 57185 , ARM64_SYSREG_PMEVTYPER20_EL0 = 57204 , ARM64_SYSREG_PMEVTYPER21_EL0 = 57205 , ARM64_SYSREG_PMEVTYPER22_EL0 = 57206 , ARM64_SYSREG_PMEVTYPER23_EL0 = 57207 , ARM64_SYSREG_PMEVTYPER24_EL0 = 57208 , ARM64_SYSREG_PMEVTYPER25_EL0 = 57209 , ARM64_SYSREG_PMEVTYPER26_EL0 = 57210 , ARM64_SYSREG_PMEVTYPER27_EL0 = 57211 , ARM64_SYSREG_PMEVTYPER28_EL0 = 57212 , ARM64_SYSREG_PMEVTYPER29_EL0 = 57213 , ARM64_SYSREG_PMEVTYPER2_EL0 = 57186 , ARM64_SYSREG_PMEVTYPER30_EL0 = 57214 , ARM64_SYSREG_PMEVTYPER3_EL0 = 57187 , ARM64_SYSREG_PMEVTYPER4_EL0 = 57188 , ARM64_SYSREG_PMEVTYPER5_EL0 = 57189 , ARM64_SYSREG_PMEVTYPER6_EL0 = 57190 , ARM64_SYSREG_PMEVTYPER7_EL0 = 57191 , ARM64_SYSREG_PMEVTYPER8_EL0 = 57192 , ARM64_SYSREG_PMEVTYPER9_EL0 = 57193 , ARM64_SYSREG_PMINTENCLR_EL1 = 50418 , ARM64_SYSREG_PMINTENSET_EL1 = 50417 , ARM64_SYSREG_PMMIR_EL1 = 50422 , ARM64_SYSREG_PMOVSCLR_EL0 = 56547 , ARM64_SYSREG_PMOVSSET_EL0 = 56563 , ARM64_SYSREG_PMSCR_EL1 = 50376 , ARM64_SYSREG_PMSCR_EL12 = 60616 , ARM64_SYSREG_PMSCR_EL2 = 58568 , ARM64_SYSREG_PMSELR_EL0 = 56549 , ARM64_SYSREG_PMSEVFR_EL1 = 50381 , ARM64_SYSREG_PMSFCR_EL1 = 50380 , ARM64_SYSREG_PMSICR_EL1 = 50378 , ARM64_SYSREG_PMSIDR_EL1 = 50383 , ARM64_SYSREG_PMSIRR_EL1 = 50379 , ARM64_SYSREG_PMSLATFR_EL1 = 50382 , ARM64_SYSREG_PMSNEVFR_EL1 = 50377 , ARM64_SYSREG_PMSWINC_EL0 = 56548 , ARM64_SYSREG_PMUSERENR_EL0 = 56560 , ARM64_SYSREG_PMXEVCNTR_EL0 = 56554 , ARM64_SYSREG_PMXEVTYPER_EL0 = 56553 , ARM64_SYSREG_PRBAR10_EL1 = 50024 , ARM64_SYSREG_PRBAR10_EL2 = 58216 , ARM64_SYSREG_PRBAR11_EL1 = 50028 , ARM64_SYSREG_PRBAR11_EL2 = 58220 , ARM64_SYSREG_PRBAR12_EL1 = 50032 , ARM64_SYSREG_PRBAR12_EL2 = 58224 , ARM64_SYSREG_PRBAR13_EL1 = 50036 , ARM64_SYSREG_PRBAR13_EL2 = 58228 , ARM64_SYSREG_PRBAR14_EL1 = 50040 , ARM64_SYSREG_PRBAR14_EL2 = 58232 , ARM64_SYSREG_PRBAR15_EL1 = 50044 , ARM64_SYSREG_PRBAR15_EL2 = 58236 , ARM64_SYSREG_PRBAR1_EL1 = 49988 , ARM64_SYSREG_PRBAR1_EL2 = 58180 , ARM64_SYSREG_PRBAR2_EL1 = 49992 , ARM64_SYSREG_PRBAR2_EL2 = 58184 , ARM64_SYSREG_PRBAR3_EL1 = 49996 , ARM64_SYSREG_PRBAR3_EL2 = 58188 , ARM64_SYSREG_PRBAR4_EL1 = 50000 , ARM64_SYSREG_PRBAR4_EL2 = 58192 , ARM64_SYSREG_PRBAR5_EL1 = 50004 , ARM64_SYSREG_PRBAR5_EL2 = 58196 , ARM64_SYSREG_PRBAR6_EL1 = 50008 , ARM64_SYSREG_PRBAR6_EL2 = 58200 , ARM64_SYSREG_PRBAR7_EL1 = 50012 , ARM64_SYSREG_PRBAR7_EL2 = 58204 , ARM64_SYSREG_PRBAR8_EL1 = 50016 , ARM64_SYSREG_PRBAR8_EL2 = 58208 , ARM64_SYSREG_PRBAR9_EL1 = 50020 , ARM64_SYSREG_PRBAR9_EL2 = 58212 , ARM64_SYSREG_PRBAR_EL1 = 49984 , ARM64_SYSREG_PRBAR_EL2 = 58176 , ARM64_SYSREG_PRENR_EL1 = 49929 , ARM64_SYSREG_PRENR_EL2 = 58121 , ARM64_SYSREG_PRLAR10_EL1 = 50025 , ARM64_SYSREG_PRLAR10_EL2 = 58217 , ARM64_SYSREG_PRLAR11_EL1 = 50029 , ARM64_SYSREG_PRLAR11_EL2 = 58221 , ARM64_SYSREG_PRLAR12_EL1 = 50033 , ARM64_SYSREG_PRLAR12_EL2 = 58225 , ARM64_SYSREG_PRLAR13_EL1 = 50037 , ARM64_SYSREG_PRLAR13_EL2 = 58229 , ARM64_SYSREG_PRLAR14_EL1 = 50041 , ARM64_SYSREG_PRLAR14_EL2 = 58233 , ARM64_SYSREG_PRLAR15_EL1 = 50045 , ARM64_SYSREG_PRLAR15_EL2 = 58237 , ARM64_SYSREG_PRLAR1_EL1 = 49989 , ARM64_SYSREG_PRLAR1_EL2 = 58181 , ARM64_SYSREG_PRLAR2_EL1 = 49993 , ARM64_SYSREG_PRLAR2_EL2 = 58185 , ARM64_SYSREG_PRLAR3_EL1 = 49997 , ARM64_SYSREG_PRLAR3_EL2 = 58189 , ARM64_SYSREG_PRLAR4_EL1 = 50001 , ARM64_SYSREG_PRLAR4_EL2 = 58193 , ARM64_SYSREG_PRLAR5_EL1 = 50005 , ARM64_SYSREG_PRLAR5_EL2 = 58197 , ARM64_SYSREG_PRLAR6_EL1 = 50009 , ARM64_SYSREG_PRLAR6_EL2 = 58201 , ARM64_SYSREG_PRLAR7_EL1 = 50013 , ARM64_SYSREG_PRLAR7_EL2 = 58205 , ARM64_SYSREG_PRLAR8_EL1 = 50017 , ARM64_SYSREG_PRLAR8_EL2 = 58209 , ARM64_SYSREG_PRLAR9_EL1 = 50021 , ARM64_SYSREG_PRLAR9_EL2 = 58213 , ARM64_SYSREG_PRLAR_EL1 = 49985 , ARM64_SYSREG_PRLAR_EL2 = 58177 , ARM64_SYSREG_PRSELR_EL1 = 49937 , ARM64_SYSREG_PRSELR_EL2 = 58129 , ARM64_SYSREG_REVIDR_EL1 = 49158 , ARM64_SYSREG_RGSR_EL1 = 49285 , ARM64_SYSREG_RMR_EL1 = 50690 , ARM64_SYSREG_RMR_EL2 = 58882 , ARM64_SYSREG_RMR_EL3 = 62978 , ARM64_SYSREG_RNDR = 55584 , ARM64_SYSREG_RNDRRS = 55585 , ARM64_SYSREG_RVBAR_EL1 = 50689 , ARM64_SYSREG_RVBAR_EL2 = 58881 , ARM64_SYSREG_RVBAR_EL3 = 62977 , ARM64_SYSREG_SCR_EL3 = 61576 , ARM64_SYSREG_SCTLR_EL1 = 49280 , ARM64_SYSREG_SCTLR_EL12 = 59520 , ARM64_SYSREG_SCTLR_EL2 = 57472 , ARM64_SYSREG_SCTLR_EL3 = 61568 , ARM64_SYSREG_SCXTNUM_EL0 = 56967 , ARM64_SYSREG_SCXTNUM_EL1 = 50823 , ARM64_SYSREG_SCXTNUM_EL12 = 61063 , ARM64_SYSREG_SCXTNUM_EL2 = 59015 , ARM64_SYSREG_SCXTNUM_EL3 = 63111 , ARM64_SYSREG_SDER32_EL2 = 57497 , ARM64_SYSREG_SDER32_EL3 = 61577 , ARM64_SYSREG_SMCR_EL1 = 49302 , ARM64_SYSREG_SMCR_EL12 = 59542 , ARM64_SYSREG_SMCR_EL2 = 57494 , ARM64_SYSREG_SMCR_EL3 = 61590 , ARM64_SYSREG_SMIDR_EL1 = 51206 , ARM64_SYSREG_SMPRIMAP_EL2 = 57493 , ARM64_SYSREG_SMPRI_EL1 = 49300 , ARM64_SYSREG_SPSEL = 49680 , ARM64_SYSREG_SPSR_ABT = 57881 , ARM64_SYSREG_SPSR_EL1 = 49664 , ARM64_SYSREG_SPSR_EL12 = 59904 , ARM64_SYSREG_SPSR_EL2 = 57856 , ARM64_SYSREG_SPSR_EL3 = 61952 , ARM64_SYSREG_SPSR_FIQ = 57883 , ARM64_SYSREG_SPSR_IRQ = 57880 , ARM64_SYSREG_SPSR_UND = 57882 , ARM64_SYSREG_SP_EL0 = 49672 , ARM64_SYSREG_SP_EL1 = 57864 , ARM64_SYSREG_SP_EL2 = 61960 , ARM64_SYSREG_SSBS = 55830 , ARM64_SYSREG_SVCR = 55826 , ARM64_SYSREG_TCO = 55831 , ARM64_SYSREG_TCR_EL1 = 49410 , ARM64_SYSREG_TCR_EL12 = 59650 , ARM64_SYSREG_TCR_EL2 = 57602 , ARM64_SYSREG_TCR_EL3 = 61698 , ARM64_SYSREG_TEECR32_EL1 = 36864 , ARM64_SYSREG_TEEHBR32_EL1 = 36992 , ARM64_SYSREG_TFSRE0_EL1 = 49841 , ARM64_SYSREG_TFSR_EL1 = 49840 , ARM64_SYSREG_TFSR_EL12 = 60080 , ARM64_SYSREG_TFSR_EL2 = 58032 , ARM64_SYSREG_TFSR_EL3 = 62128 , ARM64_SYSREG_TPIDR2_EL0 = 56965 , ARM64_SYSREG_TPIDRRO_EL0 = 56963 , ARM64_SYSREG_TPIDR_EL0 = 56962 , ARM64_SYSREG_TPIDR_EL1 = 50820 , ARM64_SYSREG_TPIDR_EL2 = 59010 , ARM64_SYSREG_TPIDR_EL3 = 63106 , ARM64_SYSREG_TRBBASER_EL1 = 50394 , ARM64_SYSREG_TRBIDR_EL1 = 50399 , ARM64_SYSREG_TRBLIMITR_EL1 = 50392 , ARM64_SYSREG_TRBMAR_EL1 = 50396 , ARM64_SYSREG_TRBPTR_EL1 = 50393 , ARM64_SYSREG_TRBSR_EL1 = 50395 , ARM64_SYSREG_TRBTRG_EL1 = 50398 , ARM64_SYSREG_TRCACATR0 = 35074 , ARM64_SYSREG_TRCACATR1 = 35090 , ARM64_SYSREG_TRCACATR10 = 35107 , ARM64_SYSREG_TRCACATR11 = 35123 , ARM64_SYSREG_TRCACATR12 = 35139 , ARM64_SYSREG_TRCACATR13 = 35155 , ARM64_SYSREG_TRCACATR14 = 35171 , ARM64_SYSREG_TRCACATR15 = 35187 , ARM64_SYSREG_TRCACATR2 = 35106 , ARM64_SYSREG_TRCACATR3 = 35122 , ARM64_SYSREG_TRCACATR4 = 35138 , ARM64_SYSREG_TRCACATR5 = 35154 , ARM64_SYSREG_TRCACATR6 = 35170 , ARM64_SYSREG_TRCACATR7 = 35186 , ARM64_SYSREG_TRCACATR8 = 35075 , ARM64_SYSREG_TRCACATR9 = 35091 , ARM64_SYSREG_TRCACVR0 = 35072 , ARM64_SYSREG_TRCACVR1 = 35088 , ARM64_SYSREG_TRCACVR10 = 35105 , ARM64_SYSREG_TRCACVR11 = 35121 , ARM64_SYSREG_TRCACVR12 = 35137 , ARM64_SYSREG_TRCACVR13 = 35153 , ARM64_SYSREG_TRCACVR14 = 35169 , ARM64_SYSREG_TRCACVR15 = 35185 , ARM64_SYSREG_TRCACVR2 = 35104 , ARM64_SYSREG_TRCACVR3 = 35120 , ARM64_SYSREG_TRCACVR4 = 35136 , ARM64_SYSREG_TRCACVR5 = 35152 , ARM64_SYSREG_TRCACVR6 = 35168 , ARM64_SYSREG_TRCACVR7 = 35184 , ARM64_SYSREG_TRCACVR8 = 35073 , ARM64_SYSREG_TRCACVR9 = 35089 , ARM64_SYSREG_TRCAUTHSTATUS = 35830 , ARM64_SYSREG_TRCAUXCTLR = 34864 , ARM64_SYSREG_TRCBBCTLR = 34936 , ARM64_SYSREG_TRCCCCTLR = 34928 , ARM64_SYSREG_TRCCIDCCTLR0 = 35202 , ARM64_SYSREG_TRCCIDCCTLR1 = 35210 , ARM64_SYSREG_TRCCIDCVR0 = 35200 , ARM64_SYSREG_TRCCIDCVR1 = 35216 , ARM64_SYSREG_TRCCIDCVR2 = 35232 , ARM64_SYSREG_TRCCIDCVR3 = 35248 , ARM64_SYSREG_TRCCIDCVR4 = 35264 , ARM64_SYSREG_TRCCIDCVR5 = 35280 , ARM64_SYSREG_TRCCIDCVR6 = 35296 , ARM64_SYSREG_TRCCIDCVR7 = 35312 , ARM64_SYSREG_TRCCIDR0 = 35815 , ARM64_SYSREG_TRCCIDR1 = 35823 , ARM64_SYSREG_TRCCIDR2 = 35831 , ARM64_SYSREG_TRCCIDR3 = 35839 , ARM64_SYSREG_TRCCLAIMCLR = 35790 , ARM64_SYSREG_TRCCLAIMSET = 35782 , ARM64_SYSREG_TRCCNTCTLR0 = 34853 , ARM64_SYSREG_TRCCNTCTLR1 = 34861 , ARM64_SYSREG_TRCCNTCTLR2 = 34869 , ARM64_SYSREG_TRCCNTCTLR3 = 34877 , ARM64_SYSREG_TRCCNTRLDVR0 = 34821 , ARM64_SYSREG_TRCCNTRLDVR1 = 34829 , ARM64_SYSREG_TRCCNTRLDVR2 = 34837 , ARM64_SYSREG_TRCCNTRLDVR3 = 34845 , ARM64_SYSREG_TRCCNTVR0 = 34885 , ARM64_SYSREG_TRCCNTVR1 = 34893 , ARM64_SYSREG_TRCCNTVR2 = 34901 , ARM64_SYSREG_TRCCNTVR3 = 34909 , ARM64_SYSREG_TRCCONFIGR = 34848 , ARM64_SYSREG_TRCDEVAFF0 = 35798 , ARM64_SYSREG_TRCDEVAFF1 = 35806 , ARM64_SYSREG_TRCDEVARCH = 35838 , ARM64_SYSREG_TRCDEVID = 35735 , ARM64_SYSREG_TRCDEVTYPE = 35743 , ARM64_SYSREG_TRCDVCMR0 = 35078 , ARM64_SYSREG_TRCDVCMR1 = 35110 , ARM64_SYSREG_TRCDVCMR2 = 35142 , ARM64_SYSREG_TRCDVCMR3 = 35174 , ARM64_SYSREG_TRCDVCMR4 = 35079 , ARM64_SYSREG_TRCDVCMR5 = 35111 , ARM64_SYSREG_TRCDVCMR6 = 35143 , ARM64_SYSREG_TRCDVCMR7 = 35175 , ARM64_SYSREG_TRCDVCVR0 = 35076 , ARM64_SYSREG_TRCDVCVR1 = 35108 , ARM64_SYSREG_TRCDVCVR2 = 35140 , ARM64_SYSREG_TRCDVCVR3 = 35172 , ARM64_SYSREG_TRCDVCVR4 = 35077 , ARM64_SYSREG_TRCDVCVR5 = 35109 , ARM64_SYSREG_TRCDVCVR6 = 35141 , ARM64_SYSREG_TRCDVCVR7 = 35173 , ARM64_SYSREG_TRCEVENTCTL0R = 34880 , ARM64_SYSREG_TRCEVENTCTL1R = 34888 , ARM64_SYSREG_TRCEXTINSELR = 34884 , ARM64_SYSREG_TRCEXTINSELR1 = 34892 , ARM64_SYSREG_TRCEXTINSELR2 = 34900 , ARM64_SYSREG_TRCEXTINSELR3 = 34908 , ARM64_SYSREG_TRCIDR0 = 34887 , ARM64_SYSREG_TRCIDR1 = 34895 , ARM64_SYSREG_TRCIDR10 = 34838 , ARM64_SYSREG_TRCIDR11 = 34846 , ARM64_SYSREG_TRCIDR12 = 34854 , ARM64_SYSREG_TRCIDR13 = 34862 , ARM64_SYSREG_TRCIDR2 = 34903 , ARM64_SYSREG_TRCIDR3 = 34911 , ARM64_SYSREG_TRCIDR4 = 34919 , ARM64_SYSREG_TRCIDR5 = 34927 , ARM64_SYSREG_TRCIDR6 = 34935 , ARM64_SYSREG_TRCIDR7 = 34943 , ARM64_SYSREG_TRCIDR8 = 34822 , ARM64_SYSREG_TRCIDR9 = 34830 , ARM64_SYSREG_TRCIMSPEC0 = 34823 , ARM64_SYSREG_TRCIMSPEC1 = 34831 , ARM64_SYSREG_TRCIMSPEC2 = 34839 , ARM64_SYSREG_TRCIMSPEC3 = 34847 , ARM64_SYSREG_TRCIMSPEC4 = 34855 , ARM64_SYSREG_TRCIMSPEC5 = 34863 , ARM64_SYSREG_TRCIMSPEC6 = 34871 , ARM64_SYSREG_TRCIMSPEC7 = 34879 , ARM64_SYSREG_TRCITCTRL = 35716 , ARM64_SYSREG_TRCLAR = 35814 , ARM64_SYSREG_TRCLSR = 35822 , ARM64_SYSREG_TRCOSLAR = 34948 , ARM64_SYSREG_TRCOSLSR = 34956 , ARM64_SYSREG_TRCPDCR = 34980 , ARM64_SYSREG_TRCPDSR = 34988 , ARM64_SYSREG_TRCPIDR0 = 35783 , ARM64_SYSREG_TRCPIDR1 = 35791 , ARM64_SYSREG_TRCPIDR2 = 35799 , ARM64_SYSREG_TRCPIDR3 = 35807 , ARM64_SYSREG_TRCPIDR4 = 35751 , ARM64_SYSREG_TRCPIDR5 = 35759 , ARM64_SYSREG_TRCPIDR6 = 35767 , ARM64_SYSREG_TRCPIDR7 = 35775 , ARM64_SYSREG_TRCPRGCTLR = 34824 , ARM64_SYSREG_TRCPROCSELR = 34832 , ARM64_SYSREG_TRCQCTLR = 34825 , ARM64_SYSREG_TRCRSCTLR10 = 35024 , ARM64_SYSREG_TRCRSCTLR11 = 35032 , ARM64_SYSREG_TRCRSCTLR12 = 35040 , ARM64_SYSREG_TRCRSCTLR13 = 35048 , ARM64_SYSREG_TRCRSCTLR14 = 35056 , ARM64_SYSREG_TRCRSCTLR15 = 35064 , ARM64_SYSREG_TRCRSCTLR16 = 34945 , ARM64_SYSREG_TRCRSCTLR17 = 34953 , ARM64_SYSREG_TRCRSCTLR18 = 34961 , ARM64_SYSREG_TRCRSCTLR19 = 34969 , ARM64_SYSREG_TRCRSCTLR2 = 34960 , ARM64_SYSREG_TRCRSCTLR20 = 34977 , ARM64_SYSREG_TRCRSCTLR21 = 34985 , ARM64_SYSREG_TRCRSCTLR22 = 34993 , ARM64_SYSREG_TRCRSCTLR23 = 35001 , ARM64_SYSREG_TRCRSCTLR24 = 35009 , ARM64_SYSREG_TRCRSCTLR25 = 35017 , ARM64_SYSREG_TRCRSCTLR26 = 35025 , ARM64_SYSREG_TRCRSCTLR27 = 35033 , ARM64_SYSREG_TRCRSCTLR28 = 35041 , ARM64_SYSREG_TRCRSCTLR29 = 35049 , ARM64_SYSREG_TRCRSCTLR3 = 34968 , ARM64_SYSREG_TRCRSCTLR30 = 35057 , ARM64_SYSREG_TRCRSCTLR31 = 35065 , ARM64_SYSREG_TRCRSCTLR4 = 34976 , ARM64_SYSREG_TRCRSCTLR5 = 34984 , ARM64_SYSREG_TRCRSCTLR6 = 34992 , ARM64_SYSREG_TRCRSCTLR7 = 35000 , ARM64_SYSREG_TRCRSCTLR8 = 35008 , ARM64_SYSREG_TRCRSCTLR9 = 35016 , ARM64_SYSREG_TRCRSR = 34896 , ARM64_SYSREG_TRCSEQEVR0 = 34820 , ARM64_SYSREG_TRCSEQEVR1 = 34828 , ARM64_SYSREG_TRCSEQEVR2 = 34836 , ARM64_SYSREG_TRCSEQRSTEVR = 34868 , ARM64_SYSREG_TRCSEQSTR = 34876 , ARM64_SYSREG_TRCSSCCR0 = 34946 , ARM64_SYSREG_TRCSSCCR1 = 34954 , ARM64_SYSREG_TRCSSCCR2 = 34962 , ARM64_SYSREG_TRCSSCCR3 = 34970 , ARM64_SYSREG_TRCSSCCR4 = 34978 , ARM64_SYSREG_TRCSSCCR5 = 34986 , ARM64_SYSREG_TRCSSCCR6 = 34994 , ARM64_SYSREG_TRCSSCCR7 = 35002 , ARM64_SYSREG_TRCSSCSR0 = 35010 , ARM64_SYSREG_TRCSSCSR1 = 35018 , ARM64_SYSREG_TRCSSCSR2 = 35026 , ARM64_SYSREG_TRCSSCSR3 = 35034 , ARM64_SYSREG_TRCSSCSR4 = 35042 , ARM64_SYSREG_TRCSSCSR5 = 35050 , ARM64_SYSREG_TRCSSCSR6 = 35058 , ARM64_SYSREG_TRCSSCSR7 = 35066 , ARM64_SYSREG_TRCSSPCICR0 = 34947 , ARM64_SYSREG_TRCSSPCICR1 = 34955 , ARM64_SYSREG_TRCSSPCICR2 = 34963 , ARM64_SYSREG_TRCSSPCICR3 = 34971 , ARM64_SYSREG_TRCSSPCICR4 = 34979 , ARM64_SYSREG_TRCSSPCICR5 = 34987 , ARM64_SYSREG_TRCSSPCICR6 = 34995 , ARM64_SYSREG_TRCSSPCICR7 = 35003 , ARM64_SYSREG_TRCSTALLCTLR = 34904 , ARM64_SYSREG_TRCSTATR = 34840 , ARM64_SYSREG_TRCSYNCPR = 34920 , ARM64_SYSREG_TRCTRACEIDR = 34817 , ARM64_SYSREG_TRCTSCTLR = 34912 , ARM64_SYSREG_TRCVDARCCTLR = 34898 , ARM64_SYSREG_TRCVDCTLR = 34882 , ARM64_SYSREG_TRCVDSACCTLR = 34890 , ARM64_SYSREG_TRCVICTLR = 34818 , ARM64_SYSREG_TRCVIIECTLR = 34826 , ARM64_SYSREG_TRCVIPCSSCTLR = 34842 , ARM64_SYSREG_TRCVISSCTLR = 34834 , ARM64_SYSREG_TRCVMIDCCTLR0 = 35218 , ARM64_SYSREG_TRCVMIDCCTLR1 = 35226 , ARM64_SYSREG_TRCVMIDCVR0 = 35201 , ARM64_SYSREG_TRCVMIDCVR1 = 35217 , ARM64_SYSREG_TRCVMIDCVR2 = 35233 , ARM64_SYSREG_TRCVMIDCVR3 = 35249 , ARM64_SYSREG_TRCVMIDCVR4 = 35265 , ARM64_SYSREG_TRCVMIDCVR5 = 35281 , ARM64_SYSREG_TRCVMIDCVR6 = 35297 , ARM64_SYSREG_TRCVMIDCVR7 = 35313 , ARM64_SYSREG_TRFCR_EL1 = 49297 , ARM64_SYSREG_TRFCR_EL12 = 59537 , ARM64_SYSREG_TRFCR_EL2 = 57489 , ARM64_SYSREG_TTBR0_EL1 = 49408 , ARM64_SYSREG_TTBR0_EL12 = 59648 , ARM64_SYSREG_TTBR0_EL2 = 57600 , ARM64_SYSREG_TTBR0_EL3 = 61696 , ARM64_SYSREG_TTBR1_EL1 = 49409 , ARM64_SYSREG_TTBR1_EL12 = 59649 , ARM64_SYSREG_TTBR1_EL2 = 57601 , ARM64_SYSREG_UAO = 49684 , ARM64_SYSREG_VBAR_EL1 = 50688 , ARM64_SYSREG_VBAR_EL12 = 60928 , ARM64_SYSREG_VBAR_EL2 = 58880 , ARM64_SYSREG_VBAR_EL3 = 62976 , ARM64_SYSREG_VDISR_EL2 = 58889 , ARM64_SYSREG_VMPIDR_EL2 = 57349 , ARM64_SYSREG_VNCR_EL2 = 57616 , ARM64_SYSREG_VPIDR_EL2 = 57344 , ARM64_SYSREG_VSESR_EL2 = 58003 , ARM64_SYSREG_VSTCR_EL2 = 57650 , ARM64_SYSREG_VSTTBR_EL2 = 57648 , ARM64_SYSREG_VTCR_EL2 = 57610 , ARM64_SYSREG_VTTBR_EL2 = 57608 , ARM64_SYSREG_ZCR_EL1 = 49296 , ARM64_SYSREG_ZCR_EL12 = 59536 , ARM64_SYSREG_ZCR_EL2 = 57488 , ARM64_SYSREG_ZCR_EL3 = 61584 , } # [repr (u32)] # [doc = " System PState Field (MSR instruction)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_pstate { ARM64_PSTATE_INVALID = 0 , ARM64_PSTATE_SPSEL = 5 , ARM64_PSTATE_DAIFSET = 30 , ARM64_PSTATE_DAIFCLR = 31 , ARM64_PSTATE_PAN = 4 , ARM64_PSTATE_UAO = 3 , ARM64_PSTATE_DIT = 26 , } # [repr (u32)] # [doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_vas { ARM64_VAS_INVALID = 0 , ARM64_VAS_16B = 1 , ARM64_VAS_8B = 2 , ARM64_VAS_4B = 3 , ARM64_VAS_1B = 4 , ARM64_VAS_8H = 5 , ARM64_VAS_4H = 6 , ARM64_VAS_2H = 7 , ARM64_VAS_1H = 8 , ARM64_VAS_4S = 9 , ARM64_VAS_2S = 10 , ARM64_VAS_1S = 11 , ARM64_VAS_2D = 12 , ARM64_VAS_1D = 13 , ARM64_VAS_1Q = 14 , } # [repr (u32)] # [doc = " Memory barrier operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0 , ARM64_BARRIER_OSHLD = 1 , ARM64_BARRIER_OSHST = 2 , ARM64_BARRIER_OSH = 3 , ARM64_BARRIER_NSHLD = 5 , ARM64_BARRIER_NSHST = 6 , ARM64_BARRIER_NSH = 7 , ARM64_BARRIER_ISHLD = 9 , ARM64_BARRIER_ISHST = 10 , ARM64_BARRIER_ISH = 11 , ARM64_BARRIER_LD = 13 , ARM64_BARRIER_ST = 14 , ARM64_BARRIER_SY = 15 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM64_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM64_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM64_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM64_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM64_OP_FP = 4 , # [doc = "< C-Immediate"] ARM64_OP_CIMM = 64 , # [doc = "< MRS register operand."] ARM64_OP_REG_MRS = 65 , # [doc = "< MSR register operand."] ARM64_OP_REG_MSR = 66 , # [doc = "< PState operand."] ARM64_OP_PSTATE = 67 , # [doc = "< SYS operand for IC/DC/AT/TLBI instructions."] ARM64_OP_SYS = 68 , # [doc = "< SVCR operand for MSR SVCR instructions."] ARM64_OP_SVCR = 69 , # [doc = "< Prefetch operand (PRFM)."] ARM64_OP_PREFETCH = 70 , # [doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."] ARM64_OP_BARRIER = 71 , # [doc = "< SME instruction operand with with index."] ARM64_OP_SME_INDEX = 72 , } # [repr (u32)] # [doc = " SYS operands (IC/DC/AC/TLBI)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sys_op { ARM64_SYS_INVALID = 0 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1 = 1 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1IS = 2 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1ISNXS = 3 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1NXS = 4 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OS = 5 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OSNXS = 6 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2 = 7 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2IS = 8 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2ISNXS = 9 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2NXS = 10 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OS = 11 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OSNXS = 12 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3 = 13 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3IS = 14 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3ISNXS = 15 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3NXS = 16 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OS = 17 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OSNXS = 18 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1 = 19 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1IS = 20 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1ISNXS = 21 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1NXS = 22 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OS = 23 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OSNXS = 24 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1 = 25 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1IS = 26 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1ISNXS = 27 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1NXS = 28 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OS = 29 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OSNXS = 30 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1 = 31 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1IS = 32 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1ISNXS = 33 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1NXS = 34 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OS = 35 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OSNXS = 36 , # [doc = " TLBI operations"] ARM64_TLBI_PAALL = 37 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLNXS = 38 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOS = 39 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOSNXS = 40 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1 = 41 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1IS = 42 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1ISNXS = 43 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1NXS = 44 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OS = 45 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OSNXS = 46 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1 = 47 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1IS = 48 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1ISNXS = 49 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1NXS = 50 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OS = 51 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OSNXS = 52 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOS = 53 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOSNXS = 54 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOS = 55 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOSNXS = 56 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1 = 57 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1IS = 58 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1ISNXS = 59 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1NXS = 60 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OS = 61 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OSNXS = 62 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1 = 63 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1IS = 64 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1ISNXS = 65 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1NXS = 66 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OS = 67 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OSNXS = 68 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1 = 69 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1IS = 70 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1ISNXS = 71 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1NXS = 72 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OS = 73 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OSNXS = 74 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2 = 75 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2IS = 76 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2ISNXS = 77 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2NXS = 78 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OS = 79 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OSNXS = 80 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3 = 81 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3IS = 82 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3ISNXS = 83 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3NXS = 84 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OS = 85 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OSNXS = 86 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1 = 87 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1IS = 88 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1ISNXS = 89 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1NXS = 90 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OS = 91 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OSNXS = 92 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2 = 93 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2IS = 94 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2ISNXS = 95 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2NXS = 96 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OS = 97 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OSNXS = 98 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3 = 99 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3IS = 100 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3ISNXS = 101 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3NXS = 102 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OS = 103 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OSNXS = 104 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1 = 105 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1IS = 106 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1ISNXS = 107 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1NXS = 108 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OS = 109 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OSNXS = 110 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1 = 111 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1IS = 112 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1ISNXS = 113 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1NXS = 114 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OS = 115 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OSNXS = 116 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1 = 117 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1IS = 118 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1ISNXS = 119 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1NXS = 120 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OS = 121 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OSNXS = 122 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2 = 123 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2IS = 124 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2ISNXS = 125 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2NXS = 126 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OS = 127 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OSNXS = 128 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3 = 129 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3IS = 130 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3ISNXS = 131 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3NXS = 132 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OS = 133 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OSNXS = 134 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1 = 135 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1IS = 136 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1ISNXS = 137 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1NXS = 138 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OS = 139 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OSNXS = 140 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2 = 141 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2IS = 142 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2ISNXS = 143 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2NXS = 144 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OS = 145 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OSNXS = 146 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3 = 147 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3IS = 148 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3ISNXS = 149 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3NXS = 150 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OS = 151 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OSNXS = 152 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1 = 153 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1IS = 154 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1ISNXS = 155 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1NXS = 156 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OS = 157 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OSNXS = 158 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1 = 159 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1IS = 160 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1ISNXS = 161 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1NXS = 162 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OS = 163 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OSNXS = 164 , # [doc = " AT operations"] ARM64_AT_S1E1R = 165 , # [doc = " AT operations"] ARM64_AT_S1E2R = 166 , # [doc = " AT operations"] ARM64_AT_S1E3R = 167 , # [doc = " AT operations"] ARM64_AT_S1E1W = 168 , # [doc = " AT operations"] ARM64_AT_S1E2W = 169 , # [doc = " AT operations"] ARM64_AT_S1E3W = 170 , # [doc = " AT operations"] ARM64_AT_S1E0R = 171 , # [doc = " AT operations"] ARM64_AT_S1E0W = 172 , # [doc = " AT operations"] ARM64_AT_S12E1R = 173 , # [doc = " AT operations"] ARM64_AT_S12E1W = 174 , # [doc = " AT operations"] ARM64_AT_S12E0R = 175 , # [doc = " AT operations"] ARM64_AT_S12E0W = 176 , # [doc = " AT operations"] ARM64_AT_S1E1RP = 177 , # [doc = " AT operations"] ARM64_AT_S1E1WP = 178 , # [doc = " DC operations"] ARM64_DC_CGDSW = 179 , # [doc = " DC operations"] ARM64_DC_CGDVAC = 180 , # [doc = " DC operations"] ARM64_DC_CGDVADP = 181 , # [doc = " DC operations"] ARM64_DC_CGDVAP = 182 , # [doc = " DC operations"] ARM64_DC_CGSW = 183 , # [doc = " DC operations"] ARM64_DC_CGVAC = 184 , # [doc = " DC operations"] ARM64_DC_CGVADP = 185 , # [doc = " DC operations"] ARM64_DC_CGVAP = 186 , # [doc = " DC operations"] ARM64_DC_CIGDSW = 187 , # [doc = " DC operations"] ARM64_DC_CIGDVAC = 188 , # [doc = " DC operations"] ARM64_DC_CIGSW = 189 , # [doc = " DC operations"] ARM64_DC_CIGVAC = 190 , # [doc = " DC operations"] ARM64_DC_CISW = 191 , # [doc = " DC operations"] ARM64_DC_CIVAC = 192 , # [doc = " DC operations"] ARM64_DC_CSW = 193 , # [doc = " DC operations"] ARM64_DC_CVAC = 194 , # [doc = " DC operations"] ARM64_DC_CVADP = 195 , # [doc = " DC operations"] ARM64_DC_CVAP = 196 , # [doc = " DC operations"] ARM64_DC_CVAU = 197 , # [doc = " DC operations"] ARM64_DC_GVA = 198 , # [doc = " DC operations"] ARM64_DC_GZVA = 199 , # [doc = " DC operations"] ARM64_DC_IGDSW = 200 , # [doc = " DC operations"] ARM64_DC_IGDVAC = 201 , # [doc = " DC operations"] ARM64_DC_IGSW = 202 , # [doc = " DC operations"] ARM64_DC_IGVAC = 203 , # [doc = " DC operations"] ARM64_DC_ISW = 204 , # [doc = " DC operations"] ARM64_DC_IVAC = 205 , # [doc = " DC operations"] ARM64_DC_ZVA = 206 , # [doc = " IC operations"] ARM64_IC_IALLUIS = 207 , # [doc = " IC operations"] ARM64_IC_IALLU = 208 , # [doc = " IC operations"] ARM64_IC_IVAU = 209 , } # [repr (u32)] # [doc = " SVCR operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_svcr_op { ARM64_SVCR_INVALID = 0 , ARM64_SVCR_SVCRSM = 1 , ARM64_SVCR_SVCRSMZA = 3 , ARM64_SVCR_SVCRZA = 2 , } # [repr (u32)] # [doc = " Prefetch operations (PRFM)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0 , ARM64_PRFM_PLDL1KEEP = 1 , ARM64_PRFM_PLDL1STRM = 2 , ARM64_PRFM_PLDL2KEEP = 3 , ARM64_PRFM_PLDL2STRM = 4 , ARM64_PRFM_PLDL3KEEP = 5 , ARM64_PRFM_PLDL3STRM = 6 , ARM64_PRFM_PLIL1KEEP = 9 , ARM64_PRFM_PLIL1STRM = 10 , ARM64_PRFM_PLIL2KEEP = 11 , ARM64_PRFM_PLIL2STRM = 12 , ARM64_PRFM_PLIL3KEEP = 13 , ARM64_PRFM_PLIL3STRM = 14 , ARM64_PRFM_PSTL1KEEP = 17 , ARM64_PRFM_PSTL1STRM = 18 , ARM64_PRFM_PSTL2KEEP = 19 , ARM64_PRFM_PSTL2STRM = 20 , ARM64_PRFM_PSTL3KEEP = 21 , ARM64_PRFM_PSTL3STRM = 22 , } impl arm64_reg { pub const ARM64_REG_IP0 : arm64_reg = arm64_reg :: ARM64_REG_X16 ; } impl arm64_reg { pub const ARM64_REG_IP1 : arm64_reg = arm64_reg :: ARM64_REG_X17 ; } impl arm64_reg { pub const ARM64_REG_X29 : arm64_reg = arm64_reg :: ARM64_REG_FP ; } impl arm64_reg { pub const ARM64_REG_X30 : arm64_reg = arm64_reg :: ARM64_REG_LR ; } # [repr (u32)] # [doc = " ARM64 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_reg { ARM64_REG_INVALID = 0 , ARM64_REG_FFR = 1 , ARM64_REG_FP = 2 , ARM64_REG_LR = 3 , ARM64_REG_NZCV = 4 , ARM64_REG_SP = 5 , ARM64_REG_VG = 6 , ARM64_REG_WSP = 7 , ARM64_REG_WZR = 8 , ARM64_REG_XZR = 9 , ARM64_REG_ZA = 10 , ARM64_REG_B0 = 11 , ARM64_REG_B1 = 12 , ARM64_REG_B2 = 13 , ARM64_REG_B3 = 14 , ARM64_REG_B4 = 15 , ARM64_REG_B5 = 16 , ARM64_REG_B6 = 17 , ARM64_REG_B7 = 18 , ARM64_REG_B8 = 19 , ARM64_REG_B9 = 20 , ARM64_REG_B10 = 21 , ARM64_REG_B11 = 22 , ARM64_REG_B12 = 23 , ARM64_REG_B13 = 24 , ARM64_REG_B14 = 25 , ARM64_REG_B15 = 26 , ARM64_REG_B16 = 27 , ARM64_REG_B17 = 28 , ARM64_REG_B18 = 29 , ARM64_REG_B19 = 30 , ARM64_REG_B20 = 31 , ARM64_REG_B21 = 32 , ARM64_REG_B22 = 33 , ARM64_REG_B23 = 34 , ARM64_REG_B24 = 35 , ARM64_REG_B25 = 36 , ARM64_REG_B26 = 37 , ARM64_REG_B27 = 38 , ARM64_REG_B28 = 39 , ARM64_REG_B29 = 40 , ARM64_REG_B30 = 41 , ARM64_REG_B31 = 42 , ARM64_REG_D0 = 43 , ARM64_REG_D1 = 44 , ARM64_REG_D2 = 45 , ARM64_REG_D3 = 46 , ARM64_REG_D4 = 47 , ARM64_REG_D5 = 48 , ARM64_REG_D6 = 49 , ARM64_REG_D7 = 50 , ARM64_REG_D8 = 51 , ARM64_REG_D9 = 52 , ARM64_REG_D10 = 53 , ARM64_REG_D11 = 54 , ARM64_REG_D12 = 55 , ARM64_REG_D13 = 56 , ARM64_REG_D14 = 57 , ARM64_REG_D15 = 58 , ARM64_REG_D16 = 59 , ARM64_REG_D17 = 60 , ARM64_REG_D18 = 61 , ARM64_REG_D19 = 62 , ARM64_REG_D20 = 63 , ARM64_REG_D21 = 64 , ARM64_REG_D22 = 65 , ARM64_REG_D23 = 66 , ARM64_REG_D24 = 67 , ARM64_REG_D25 = 68 , ARM64_REG_D26 = 69 , ARM64_REG_D27 = 70 , ARM64_REG_D28 = 71 , ARM64_REG_D29 = 72 , ARM64_REG_D30 = 73 , ARM64_REG_D31 = 74 , ARM64_REG_H0 = 75 , ARM64_REG_H1 = 76 , ARM64_REG_H2 = 77 , ARM64_REG_H3 = 78 , ARM64_REG_H4 = 79 , ARM64_REG_H5 = 80 , ARM64_REG_H6 = 81 , ARM64_REG_H7 = 82 , ARM64_REG_H8 = 83 , ARM64_REG_H9 = 84 , ARM64_REG_H10 = 85 , ARM64_REG_H11 = 86 , ARM64_REG_H12 = 87 , ARM64_REG_H13 = 88 , ARM64_REG_H14 = 89 , ARM64_REG_H15 = 90 , ARM64_REG_H16 = 91 , ARM64_REG_H17 = 92 , ARM64_REG_H18 = 93 , ARM64_REG_H19 = 94 , ARM64_REG_H20 = 95 , ARM64_REG_H21 = 96 , ARM64_REG_H22 = 97 , ARM64_REG_H23 = 98 , ARM64_REG_H24 = 99 , ARM64_REG_H25 = 100 , ARM64_REG_H26 = 101 , ARM64_REG_H27 = 102 , ARM64_REG_H28 = 103 , ARM64_REG_H29 = 104 , ARM64_REG_H30 = 105 , ARM64_REG_H31 = 106 , ARM64_REG_P0 = 107 , ARM64_REG_P1 = 108 , ARM64_REG_P2 = 109 , ARM64_REG_P3 = 110 , ARM64_REG_P4 = 111 , ARM64_REG_P5 = 112 , ARM64_REG_P6 = 113 , ARM64_REG_P7 = 114 , ARM64_REG_P8 = 115 , ARM64_REG_P9 = 116 , ARM64_REG_P10 = 117 , ARM64_REG_P11 = 118 , ARM64_REG_P12 = 119 , ARM64_REG_P13 = 120 , ARM64_REG_P14 = 121 , ARM64_REG_P15 = 122 , ARM64_REG_Q0 = 123 , ARM64_REG_Q1 = 124 , ARM64_REG_Q2 = 125 , ARM64_REG_Q3 = 126 , ARM64_REG_Q4 = 127 , ARM64_REG_Q5 = 128 , ARM64_REG_Q6 = 129 , ARM64_REG_Q7 = 130 , ARM64_REG_Q8 = 131 , ARM64_REG_Q9 = 132 , ARM64_REG_Q10 = 133 , ARM64_REG_Q11 = 134 , ARM64_REG_Q12 = 135 , ARM64_REG_Q13 = 136 , ARM64_REG_Q14 = 137 , ARM64_REG_Q15 = 138 , ARM64_REG_Q16 = 139 , ARM64_REG_Q17 = 140 , ARM64_REG_Q18 = 141 , ARM64_REG_Q19 = 142 , ARM64_REG_Q20 = 143 , ARM64_REG_Q21 = 144 , ARM64_REG_Q22 = 145 , ARM64_REG_Q23 = 146 , ARM64_REG_Q24 = 147 , ARM64_REG_Q25 = 148 , ARM64_REG_Q26 = 149 , ARM64_REG_Q27 = 150 , ARM64_REG_Q28 = 151 , ARM64_REG_Q29 = 152 , ARM64_REG_Q30 = 153 , ARM64_REG_Q31 = 154 , ARM64_REG_S0 = 155 , ARM64_REG_S1 = 156 , ARM64_REG_S2 = 157 , ARM64_REG_S3 = 158 , ARM64_REG_S4 = 159 , ARM64_REG_S5 = 160 , ARM64_REG_S6 = 161 , ARM64_REG_S7 = 162 , ARM64_REG_S8 = 163 , ARM64_REG_S9 = 164 , ARM64_REG_S10 = 165 , ARM64_REG_S11 = 166 , ARM64_REG_S12 = 167 , ARM64_REG_S13 = 168 , ARM64_REG_S14 = 169 , ARM64_REG_S15 = 170 , ARM64_REG_S16 = 171 , ARM64_REG_S17 = 172 , ARM64_REG_S18 = 173 , ARM64_REG_S19 = 174 , ARM64_REG_S20 = 175 , ARM64_REG_S21 = 176 , ARM64_REG_S22 = 177 , ARM64_REG_S23 = 178 , ARM64_REG_S24 = 179 , ARM64_REG_S25 = 180 , ARM64_REG_S26 = 181 , ARM64_REG_S27 = 182 , ARM64_REG_S28 = 183 , ARM64_REG_S29 = 184 , ARM64_REG_S30 = 185 , ARM64_REG_S31 = 186 , ARM64_REG_W0 = 187 , ARM64_REG_W1 = 188 , ARM64_REG_W2 = 189 , ARM64_REG_W3 = 190 , ARM64_REG_W4 = 191 , ARM64_REG_W5 = 192 , ARM64_REG_W6 = 193 , ARM64_REG_W7 = 194 , ARM64_REG_W8 = 195 , ARM64_REG_W9 = 196 , ARM64_REG_W10 = 197 , ARM64_REG_W11 = 198 , ARM64_REG_W12 = 199 , ARM64_REG_W13 = 200 , ARM64_REG_W14 = 201 , ARM64_REG_W15 = 202 , ARM64_REG_W16 = 203 , ARM64_REG_W17 = 204 , ARM64_REG_W18 = 205 , ARM64_REG_W19 = 206 , ARM64_REG_W20 = 207 , ARM64_REG_W21 = 208 , ARM64_REG_W22 = 209 , ARM64_REG_W23 = 210 , ARM64_REG_W24 = 211 , ARM64_REG_W25 = 212 , ARM64_REG_W26 = 213 , ARM64_REG_W27 = 214 , ARM64_REG_W28 = 215 , ARM64_REG_W29 = 216 , ARM64_REG_W30 = 217 , ARM64_REG_X0 = 218 , ARM64_REG_X1 = 219 , ARM64_REG_X2 = 220 , ARM64_REG_X3 = 221 , ARM64_REG_X4 = 222 , ARM64_REG_X5 = 223 , ARM64_REG_X6 = 224 , ARM64_REG_X7 = 225 , ARM64_REG_X8 = 226 , ARM64_REG_X9 = 227 , ARM64_REG_X10 = 228 , ARM64_REG_X11 = 229 , ARM64_REG_X12 = 230 , ARM64_REG_X13 = 231 , ARM64_REG_X14 = 232 , ARM64_REG_X15 = 233 , ARM64_REG_X16 = 234 , ARM64_REG_X17 = 235 , ARM64_REG_X18 = 236 , ARM64_REG_X19 = 237 , ARM64_REG_X20 = 238 , ARM64_REG_X21 = 239 , ARM64_REG_X22 = 240 , ARM64_REG_X23 = 241 , ARM64_REG_X24 = 242 , ARM64_REG_X25 = 243 , ARM64_REG_X26 = 244 , ARM64_REG_X27 = 245 , ARM64_REG_X28 = 246 , ARM64_REG_Z0 = 247 , ARM64_REG_Z1 = 248 , ARM64_REG_Z2 = 249 , ARM64_REG_Z3 = 250 , ARM64_REG_Z4 = 251 , ARM64_REG_Z5 = 252 , ARM64_REG_Z6 = 253 , ARM64_REG_Z7 = 254 , ARM64_REG_Z8 = 255 , ARM64_REG_Z9 = 256 , ARM64_REG_Z10 = 257 , ARM64_REG_Z11 = 258 , ARM64_REG_Z12 = 259 , ARM64_REG_Z13 = 260 , ARM64_REG_Z14 = 261 , ARM64_REG_Z15 = 262 , ARM64_REG_Z16 = 263 , ARM64_REG_Z17 = 264 , ARM64_REG_Z18 = 265 , ARM64_REG_Z19 = 266 , ARM64_REG_Z20 = 267 , ARM64_REG_Z21 = 268 , ARM64_REG_Z22 = 269 , ARM64_REG_Z23 = 270 , ARM64_REG_Z24 = 271 , ARM64_REG_Z25 = 272 , ARM64_REG_Z26 = 273 , ARM64_REG_Z27 = 274 , ARM64_REG_Z28 = 275 , ARM64_REG_Z29 = 276 , ARM64_REG_Z30 = 277 , ARM64_REG_Z31 = 278 , ARM64_REG_ZAB0 = 279 , ARM64_REG_ZAD0 = 280 , ARM64_REG_ZAD1 = 281 , ARM64_REG_ZAD2 = 282 , ARM64_REG_ZAD3 = 283 , ARM64_REG_ZAD4 = 284 , ARM64_REG_ZAD5 = 285 , ARM64_REG_ZAD6 = 286 , ARM64_REG_ZAD7 = 287 , ARM64_REG_ZAH0 = 288 , ARM64_REG_ZAH1 = 289 , ARM64_REG_ZAQ0 = 290 , ARM64_REG_ZAQ1 = 291 , ARM64_REG_ZAQ2 = 292 , ARM64_REG_ZAQ3 = 293 , ARM64_REG_ZAQ4 = 294 , ARM64_REG_ZAQ5 = 295 , ARM64_REG_ZAQ6 = 296 , ARM64_REG_ZAQ7 = 297 , ARM64_REG_ZAQ8 = 298 , ARM64_REG_ZAQ9 = 299 , ARM64_REG_ZAQ10 = 300 , ARM64_REG_ZAQ11 = 301 , ARM64_REG_ZAQ12 = 302 , ARM64_REG_ZAQ13 = 303 , ARM64_REG_ZAQ14 = 304 , ARM64_REG_ZAQ15 = 305 , ARM64_REG_ZAS0 = 306 , ARM64_REG_ZAS1 = 307 , ARM64_REG_ZAS2 = 308 , ARM64_REG_ZAS3 = 309 , ARM64_REG_V0 = 310 , ARM64_REG_V1 = 311 , ARM64_REG_V2 = 312 , ARM64_REG_V3 = 313 , ARM64_REG_V4 = 314 , ARM64_REG_V5 = 315 , ARM64_REG_V6 = 316 , ARM64_REG_V7 = 317 , ARM64_REG_V8 = 318 , ARM64_REG_V9 = 319 , ARM64_REG_V10 = 320 , ARM64_REG_V11 = 321 , ARM64_REG_V12 = 322 , ARM64_REG_V13 = 323 , ARM64_REG_V14 = 324 , ARM64_REG_V15 = 325 , ARM64_REG_V16 = 326 , ARM64_REG_V17 = 327 , ARM64_REG_V18 = 328 , ARM64_REG_V19 = 329 , ARM64_REG_V20 = 330 , ARM64_REG_V21 = 331 , ARM64_REG_V22 = 332 , ARM64_REG_V23 = 333 , ARM64_REG_V24 = 334 , ARM64_REG_V25 = 335 , ARM64_REG_V26 = 336 , ARM64_REG_V27 = 337 , ARM64_REG_V28 = 338 , ARM64_REG_V29 = 339 , ARM64_REG_V30 = 340 , ARM64_REG_V31 = 341 , ARM64_REG_ENDING = 342 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_mem { # [doc = "< base register"] pub base : arm64_reg , # [doc = "< index register"] pub index : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_mem"] [:: std :: mem :: size_of :: < arm64_op_mem > () - 12usize] ; ["Alignment of arm64_op_mem"] [:: std :: mem :: align_of :: < arm64_op_mem > () - 4usize] ; ["Offset of field: arm64_op_mem::base"] [:: std :: mem :: offset_of ! (arm64_op_mem , base) - 0usize] ; ["Offset of field: arm64_op_mem::index"] [:: std :: mem :: offset_of ! (arm64_op_mem , index) - 4usize] ; ["Offset of field: arm64_op_mem::disp"] [:: std :: mem :: offset_of ! (arm64_op_mem , disp) - 8usize] ; } ; # [doc = " SME Instruction's operand has index\n This is associated with ARM64_OP_SME_INDEX operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_sme_index { # [doc = "< register being indexed"] pub reg : arm64_reg , # [doc = "< base register"] pub base : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_sme_index"] [:: std :: mem :: size_of :: < arm64_op_sme_index > () - 12usize] ; ["Alignment of arm64_op_sme_index"] [:: std :: mem :: align_of :: < arm64_op_sme_index > () - 4usize] ; ["Offset of field: arm64_op_sme_index::reg"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , reg) - 0usize] ; ["Offset of field: arm64_op_sme_index::base"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , base) - 4usize] ; ["Offset of field: arm64_op_sme_index::disp"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64_op { # [doc = "< Vector Index for some vector operands (or -1 if\n< irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , # [doc = "< Vector Arrangement Specifier"] pub vas : arm64_vas , pub shift : cs_arm64_op__bindgen_ty_1 , # [doc = "< extender type of this operand"] pub ext : arm64_extender , # [doc = "< operand type"] pub type_ : arm64_op_type , # [doc = "< MSR/MRS SVCR instruction variant."] pub svcr : arm64_svcr_op , pub __bindgen_anon_1 : cs_arm64_op__bindgen_ty_2 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm64_op__bindgen_ty_1 { # [doc = "< shifter type of this operand"] pub type_ : arm64_shifter , # [doc = "< shifter value of this operand"] pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm64_op__bindgen_ty_2 { # [doc = "< register value for REG operand"] pub reg : arm64_reg , # [doc = "< immediate value, or index for C-IMM or IMM operand"] pub imm : i64 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm64_op_mem , # [doc = "< PState field of MSR instruction."] pub pstate : arm64_pstate , # [doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op,\n< arm64_dc_op, arm64_at_op, arm64_tlbi_op)"] pub sys : arm64_sys_op , # [doc = "< PRFM operation."] pub prefetch : arm64_prefetch_op , # [doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."] pub barrier : arm64_barrier_op , # [doc = "< base/disp value for matrix tile slice\n< instructions."] pub sme_index : arm64_op_sme_index , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_2 > () - 16usize] ; ["Alignment of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::pstate"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , pstate) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sys"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sys) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::prefetch"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , prefetch) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::barrier"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , barrier) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sme_index"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sme_index) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op"] [:: std :: mem :: size_of :: < cs_arm64_op > () - 56usize] ; ["Alignment of cs_arm64_op"] [:: std :: mem :: align_of :: < cs_arm64_op > () - 8usize] ; ["Offset of field: cs_arm64_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm64_op , vector_index) - 0usize] ; ["Offset of field: cs_arm64_op::vas"] [:: std :: mem :: offset_of ! (cs_arm64_op , vas) - 4usize] ; ["Offset of field: cs_arm64_op::shift"] [:: std :: mem :: offset_of ! (cs_arm64_op , shift) - 8usize] ; ["Offset of field: cs_arm64_op::ext"] [:: std :: mem :: offset_of ! (cs_arm64_op , ext) - 16usize] ; ["Offset of field: cs_arm64_op::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op , type_) - 20usize] ; ["Offset of field: cs_arm64_op::svcr"] [:: std :: mem :: offset_of ! (cs_arm64_op , svcr) - 24usize] ; ["Offset of field: cs_arm64_op::access"] [:: std :: mem :: offset_of ! (cs_arm64_op , access) - 48usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, svcr: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . svcr , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64 { # [doc = "< conditional code for this insn"] pub cc : arm64_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn request writeback? 'True' means 'yes'"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm64_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64"] [:: std :: mem :: size_of :: < cs_arm64 > () - 456usize] ; ["Alignment of cs_arm64"] [:: std :: mem :: align_of :: < cs_arm64 > () - 8usize] ; ["Offset of field: cs_arm64::cc"] [:: std :: mem :: offset_of ! (cs_arm64 , cc) - 0usize] ; ["Offset of field: cs_arm64::update_flags"] [:: std :: mem :: offset_of ! (cs_arm64 , update_flags) - 4usize] ; ["Offset of field: cs_arm64::writeback"] [:: std :: mem :: offset_of ! (cs_arm64 , writeback) - 5usize] ; ["Offset of field: cs_arm64::post_index"] [:: std :: mem :: offset_of ! (cs_arm64 , post_index) - 6usize] ; ["Offset of field: cs_arm64::op_count"] [:: std :: mem :: offset_of ! (cs_arm64 , op_count) - 7usize] ; ["Offset of field: cs_arm64::operands"] [:: std :: mem :: offset_of ! (cs_arm64 , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . post_index , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM64 instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn { ARM64_INS_INVALID = 0 , ARM64_INS_ABS = 1 , ARM64_INS_ADC = 2 , ARM64_INS_ADCLB = 3 , ARM64_INS_ADCLT = 4 , ARM64_INS_ADCS = 5 , ARM64_INS_ADD = 6 , ARM64_INS_ADDG = 7 , ARM64_INS_ADDHA = 8 , ARM64_INS_ADDHN = 9 , ARM64_INS_ADDHN2 = 10 , ARM64_INS_ADDHNB = 11 , ARM64_INS_ADDHNT = 12 , ARM64_INS_ADDP = 13 , ARM64_INS_ADDPL = 14 , ARM64_INS_ADDS = 15 , ARM64_INS_ADDV = 16 , ARM64_INS_ADDVA = 17 , ARM64_INS_ADDVL = 18 , ARM64_INS_ADR = 19 , ARM64_INS_ADRP = 20 , ARM64_INS_AESD = 21 , ARM64_INS_AESE = 22 , ARM64_INS_AESIMC = 23 , ARM64_INS_AESMC = 24 , ARM64_INS_AND = 25 , ARM64_INS_ANDS = 26 , ARM64_INS_ANDV = 27 , ARM64_INS_ASR = 28 , ARM64_INS_ASRD = 29 , ARM64_INS_ASRR = 30 , ARM64_INS_ASRV = 31 , ARM64_INS_AUTDA = 32 , ARM64_INS_AUTDB = 33 , ARM64_INS_AUTDZA = 34 , ARM64_INS_AUTDZB = 35 , ARM64_INS_AUTIA = 36 , ARM64_INS_AUTIA1716 = 37 , ARM64_INS_AUTIASP = 38 , ARM64_INS_AUTIAZ = 39 , ARM64_INS_AUTIB = 40 , ARM64_INS_AUTIB1716 = 41 , ARM64_INS_AUTIBSP = 42 , ARM64_INS_AUTIBZ = 43 , ARM64_INS_AUTIZA = 44 , ARM64_INS_AUTIZB = 45 , ARM64_INS_AXFLAG = 46 , ARM64_INS_B = 47 , ARM64_INS_BC = 48 , ARM64_INS_BCAX = 49 , ARM64_INS_BDEP = 50 , ARM64_INS_BEXT = 51 , ARM64_INS_BFCVT = 52 , ARM64_INS_BFCVTN = 53 , ARM64_INS_BFCVTN2 = 54 , ARM64_INS_BFCVTNT = 55 , ARM64_INS_BFDOT = 56 , ARM64_INS_BFM = 57 , ARM64_INS_BFMLALB = 58 , ARM64_INS_BFMLALT = 59 , ARM64_INS_BFMMLA = 60 , ARM64_INS_BFMOPA = 61 , ARM64_INS_BFMOPS = 62 , ARM64_INS_BGRP = 63 , ARM64_INS_BIC = 64 , ARM64_INS_BICS = 65 , ARM64_INS_BIF = 66 , ARM64_INS_BIT = 67 , ARM64_INS_BL = 68 , ARM64_INS_BLR = 69 , ARM64_INS_BLRAA = 70 , ARM64_INS_BLRAAZ = 71 , ARM64_INS_BLRAB = 72 , ARM64_INS_BLRABZ = 73 , ARM64_INS_BR = 74 , ARM64_INS_BRAA = 75 , ARM64_INS_BRAAZ = 76 , ARM64_INS_BRAB = 77 , ARM64_INS_BRABZ = 78 , ARM64_INS_BRB = 79 , ARM64_INS_BRK = 80 , ARM64_INS_BRKA = 81 , ARM64_INS_BRKAS = 82 , ARM64_INS_BRKB = 83 , ARM64_INS_BRKBS = 84 , ARM64_INS_BRKN = 85 , ARM64_INS_BRKNS = 86 , ARM64_INS_BRKPA = 87 , ARM64_INS_BRKPAS = 88 , ARM64_INS_BRKPB = 89 , ARM64_INS_BRKPBS = 90 , ARM64_INS_BSL = 91 , ARM64_INS_BSL1N = 92 , ARM64_INS_BSL2N = 93 , ARM64_INS_BTI = 94 , ARM64_INS_CADD = 95 , ARM64_INS_CAS = 96 , ARM64_INS_CASA = 97 , ARM64_INS_CASAB = 98 , ARM64_INS_CASAH = 99 , ARM64_INS_CASAL = 100 , ARM64_INS_CASALB = 101 , ARM64_INS_CASALH = 102 , ARM64_INS_CASB = 103 , ARM64_INS_CASH = 104 , ARM64_INS_CASL = 105 , ARM64_INS_CASLB = 106 , ARM64_INS_CASLH = 107 , ARM64_INS_CASP = 108 , ARM64_INS_CASPA = 109 , ARM64_INS_CASPAL = 110 , ARM64_INS_CASPL = 111 , ARM64_INS_CBNZ = 112 , ARM64_INS_CBZ = 113 , ARM64_INS_CCMN = 114 , ARM64_INS_CCMP = 115 , ARM64_INS_CDOT = 116 , ARM64_INS_CFINV = 117 , ARM64_INS_CINC = 118 , ARM64_INS_CINV = 119 , ARM64_INS_CLASTA = 120 , ARM64_INS_CLASTB = 121 , ARM64_INS_CLREX = 122 , ARM64_INS_CLS = 123 , ARM64_INS_CLZ = 124 , ARM64_INS_CMEQ = 125 , ARM64_INS_CMGE = 126 , ARM64_INS_CMGT = 127 , ARM64_INS_CMHI = 128 , ARM64_INS_CMHS = 129 , ARM64_INS_CMLA = 130 , ARM64_INS_CMLE = 131 , ARM64_INS_CMLO = 132 , ARM64_INS_CMLS = 133 , ARM64_INS_CMLT = 134 , ARM64_INS_CMN = 135 , ARM64_INS_CMP = 136 , ARM64_INS_CMPEQ = 137 , ARM64_INS_CMPGE = 138 , ARM64_INS_CMPGT = 139 , ARM64_INS_CMPHI = 140 , ARM64_INS_CMPHS = 141 , ARM64_INS_CMPLE = 142 , ARM64_INS_CMPLO = 143 , ARM64_INS_CMPLS = 144 , ARM64_INS_CMPLT = 145 , ARM64_INS_CMPNE = 146 , ARM64_INS_CMPP = 147 , ARM64_INS_CMTST = 148 , ARM64_INS_CNEG = 149 , ARM64_INS_CNOT = 150 , ARM64_INS_CNT = 151 , ARM64_INS_CNTB = 152 , ARM64_INS_CNTD = 153 , ARM64_INS_CNTH = 154 , ARM64_INS_CNTP = 155 , ARM64_INS_CNTW = 156 , ARM64_INS_COMPACT = 157 , ARM64_INS_CPY = 158 , ARM64_INS_CPYE = 159 , ARM64_INS_CPYEN = 160 , ARM64_INS_CPYERN = 161 , ARM64_INS_CPYERT = 162 , ARM64_INS_CPYERTN = 163 , ARM64_INS_CPYERTRN = 164 , ARM64_INS_CPYERTWN = 165 , ARM64_INS_CPYET = 166 , ARM64_INS_CPYETN = 167 , ARM64_INS_CPYETRN = 168 , ARM64_INS_CPYETWN = 169 , ARM64_INS_CPYEWN = 170 , ARM64_INS_CPYEWT = 171 , ARM64_INS_CPYEWTN = 172 , ARM64_INS_CPYEWTRN = 173 , ARM64_INS_CPYEWTWN = 174 , ARM64_INS_CPYFE = 175 , ARM64_INS_CPYFEN = 176 , ARM64_INS_CPYFERN = 177 , ARM64_INS_CPYFERT = 178 , ARM64_INS_CPYFERTN = 179 , ARM64_INS_CPYFERTRN = 180 , ARM64_INS_CPYFERTWN = 181 , ARM64_INS_CPYFET = 182 , ARM64_INS_CPYFETN = 183 , ARM64_INS_CPYFETRN = 184 , ARM64_INS_CPYFETWN = 185 , ARM64_INS_CPYFEWN = 186 , ARM64_INS_CPYFEWT = 187 , ARM64_INS_CPYFEWTN = 188 , ARM64_INS_CPYFEWTRN = 189 , ARM64_INS_CPYFEWTWN = 190 , ARM64_INS_CPYFM = 191 , ARM64_INS_CPYFMN = 192 , ARM64_INS_CPYFMRN = 193 , ARM64_INS_CPYFMRT = 194 , ARM64_INS_CPYFMRTN = 195 , ARM64_INS_CPYFMRTRN = 196 , ARM64_INS_CPYFMRTWN = 197 , ARM64_INS_CPYFMT = 198 , ARM64_INS_CPYFMTN = 199 , ARM64_INS_CPYFMTRN = 200 , ARM64_INS_CPYFMTWN = 201 , ARM64_INS_CPYFMWN = 202 , ARM64_INS_CPYFMWT = 203 , ARM64_INS_CPYFMWTN = 204 , ARM64_INS_CPYFMWTRN = 205 , ARM64_INS_CPYFMWTWN = 206 , ARM64_INS_CPYFP = 207 , ARM64_INS_CPYFPN = 208 , ARM64_INS_CPYFPRN = 209 , ARM64_INS_CPYFPRT = 210 , ARM64_INS_CPYFPRTN = 211 , ARM64_INS_CPYFPRTRN = 212 , ARM64_INS_CPYFPRTWN = 213 , ARM64_INS_CPYFPT = 214 , ARM64_INS_CPYFPTN = 215 , ARM64_INS_CPYFPTRN = 216 , ARM64_INS_CPYFPTWN = 217 , ARM64_INS_CPYFPWN = 218 , ARM64_INS_CPYFPWT = 219 , ARM64_INS_CPYFPWTN = 220 , ARM64_INS_CPYFPWTRN = 221 , ARM64_INS_CPYFPWTWN = 222 , ARM64_INS_CPYM = 223 , ARM64_INS_CPYMN = 224 , ARM64_INS_CPYMRN = 225 , ARM64_INS_CPYMRT = 226 , ARM64_INS_CPYMRTN = 227 , ARM64_INS_CPYMRTRN = 228 , ARM64_INS_CPYMRTWN = 229 , ARM64_INS_CPYMT = 230 , ARM64_INS_CPYMTN = 231 , ARM64_INS_CPYMTRN = 232 , ARM64_INS_CPYMTWN = 233 , ARM64_INS_CPYMWN = 234 , ARM64_INS_CPYMWT = 235 , ARM64_INS_CPYMWTN = 236 , ARM64_INS_CPYMWTRN = 237 , ARM64_INS_CPYMWTWN = 238 , ARM64_INS_CPYP = 239 , ARM64_INS_CPYPN = 240 , ARM64_INS_CPYPRN = 241 , ARM64_INS_CPYPRT = 242 , ARM64_INS_CPYPRTN = 243 , ARM64_INS_CPYPRTRN = 244 , ARM64_INS_CPYPRTWN = 245 , ARM64_INS_CPYPT = 246 , ARM64_INS_CPYPTN = 247 , ARM64_INS_CPYPTRN = 248 , ARM64_INS_CPYPTWN = 249 , ARM64_INS_CPYPWN = 250 , ARM64_INS_CPYPWT = 251 , ARM64_INS_CPYPWTN = 252 , ARM64_INS_CPYPWTRN = 253 , ARM64_INS_CPYPWTWN = 254 , ARM64_INS_CRC32B = 255 , ARM64_INS_CRC32CB = 256 , ARM64_INS_CRC32CH = 257 , ARM64_INS_CRC32CW = 258 , ARM64_INS_CRC32CX = 259 , ARM64_INS_CRC32H = 260 , ARM64_INS_CRC32W = 261 , ARM64_INS_CRC32X = 262 , ARM64_INS_CSDB = 263 , ARM64_INS_CSEL = 264 , ARM64_INS_CSET = 265 , ARM64_INS_CSETM = 266 , ARM64_INS_CSINC = 267 , ARM64_INS_CSINV = 268 , ARM64_INS_CSNEG = 269 , ARM64_INS_CTERMEQ = 270 , ARM64_INS_CTERMNE = 271 , ARM64_INS_DCPS1 = 272 , ARM64_INS_DCPS2 = 273 , ARM64_INS_DCPS3 = 274 , ARM64_INS_DECB = 275 , ARM64_INS_DECD = 276 , ARM64_INS_DECH = 277 , ARM64_INS_DECP = 278 , ARM64_INS_DECW = 279 , ARM64_INS_DFB = 280 , ARM64_INS_DGH = 281 , ARM64_INS_DMB = 282 , ARM64_INS_DRPS = 283 , ARM64_INS_DSB = 284 , ARM64_INS_DUP = 285 , ARM64_INS_DUPM = 286 , ARM64_INS_EON = 287 , ARM64_INS_EOR = 288 , ARM64_INS_EOR3 = 289 , ARM64_INS_EORBT = 290 , ARM64_INS_EORS = 291 , ARM64_INS_EORTB = 292 , ARM64_INS_EORV = 293 , ARM64_INS_ERET = 294 , ARM64_INS_ERETAA = 295 , ARM64_INS_ERETAB = 296 , ARM64_INS_ESB = 297 , ARM64_INS_EXT = 298 , ARM64_INS_EXTR = 299 , ARM64_INS_FABD = 300 , ARM64_INS_FABS = 301 , ARM64_INS_FACGE = 302 , ARM64_INS_FACGT = 303 , ARM64_INS_FACLE = 304 , ARM64_INS_FACLT = 305 , ARM64_INS_FADD = 306 , ARM64_INS_FADDA = 307 , ARM64_INS_FADDP = 308 , ARM64_INS_FADDV = 309 , ARM64_INS_FCADD = 310 , ARM64_INS_FCCMP = 311 , ARM64_INS_FCCMPE = 312 , ARM64_INS_FCMEQ = 313 , ARM64_INS_FCMGE = 314 , ARM64_INS_FCMGT = 315 , ARM64_INS_FCMLA = 316 , ARM64_INS_FCMLE = 317 , ARM64_INS_FCMLT = 318 , ARM64_INS_FCMNE = 319 , ARM64_INS_FCMP = 320 , ARM64_INS_FCMPE = 321 , ARM64_INS_FCMUO = 322 , ARM64_INS_FCPY = 323 , ARM64_INS_FCSEL = 324 , ARM64_INS_FCVT = 325 , ARM64_INS_FCVTAS = 326 , ARM64_INS_FCVTAU = 327 , ARM64_INS_FCVTL = 328 , ARM64_INS_FCVTL2 = 329 , ARM64_INS_FCVTLT = 330 , ARM64_INS_FCVTMS = 331 , ARM64_INS_FCVTMU = 332 , ARM64_INS_FCVTN = 333 , ARM64_INS_FCVTN2 = 334 , ARM64_INS_FCVTNS = 335 , ARM64_INS_FCVTNT = 336 , ARM64_INS_FCVTNU = 337 , ARM64_INS_FCVTPS = 338 , ARM64_INS_FCVTPU = 339 , ARM64_INS_FCVTX = 340 , ARM64_INS_FCVTXN = 341 , ARM64_INS_FCVTXN2 = 342 , ARM64_INS_FCVTXNT = 343 , ARM64_INS_FCVTZS = 344 , ARM64_INS_FCVTZU = 345 , ARM64_INS_FDIV = 346 , ARM64_INS_FDIVR = 347 , ARM64_INS_FDUP = 348 , ARM64_INS_FEXPA = 349 , ARM64_INS_FJCVTZS = 350 , ARM64_INS_FLOGB = 351 , ARM64_INS_FMAD = 352 , ARM64_INS_FMADD = 353 , ARM64_INS_FMAX = 354 , ARM64_INS_FMAXNM = 355 , ARM64_INS_FMAXNMP = 356 , ARM64_INS_FMAXNMV = 357 , ARM64_INS_FMAXP = 358 , ARM64_INS_FMAXV = 359 , ARM64_INS_FMIN = 360 , ARM64_INS_FMINNM = 361 , ARM64_INS_FMINNMP = 362 , ARM64_INS_FMINNMV = 363 , ARM64_INS_FMINP = 364 , ARM64_INS_FMINV = 365 , ARM64_INS_FMLA = 366 , ARM64_INS_FMLAL = 367 , ARM64_INS_FMLAL2 = 368 , ARM64_INS_FMLALB = 369 , ARM64_INS_FMLALT = 370 , ARM64_INS_FMLS = 371 , ARM64_INS_FMLSL = 372 , ARM64_INS_FMLSL2 = 373 , ARM64_INS_FMLSLB = 374 , ARM64_INS_FMLSLT = 375 , ARM64_INS_FMMLA = 376 , ARM64_INS_FMOPA = 377 , ARM64_INS_FMOPS = 378 , ARM64_INS_FMOV = 379 , ARM64_INS_FMSB = 380 , ARM64_INS_FMSUB = 381 , ARM64_INS_FMUL = 382 , ARM64_INS_FMULX = 383 , ARM64_INS_FNEG = 384 , ARM64_INS_FNMAD = 385 , ARM64_INS_FNMADD = 386 , ARM64_INS_FNMLA = 387 , ARM64_INS_FNMLS = 388 , ARM64_INS_FNMSB = 389 , ARM64_INS_FNMSUB = 390 , ARM64_INS_FNMUL = 391 , ARM64_INS_FRECPE = 392 , ARM64_INS_FRECPS = 393 , ARM64_INS_FRECPX = 394 , ARM64_INS_FRINT32X = 395 , ARM64_INS_FRINT32Z = 396 , ARM64_INS_FRINT64X = 397 , ARM64_INS_FRINT64Z = 398 , ARM64_INS_FRINTA = 399 , ARM64_INS_FRINTI = 400 , ARM64_INS_FRINTM = 401 , ARM64_INS_FRINTN = 402 , ARM64_INS_FRINTP = 403 , ARM64_INS_FRINTX = 404 , ARM64_INS_FRINTZ = 405 , ARM64_INS_FRSQRTE = 406 , ARM64_INS_FRSQRTS = 407 , ARM64_INS_FSCALE = 408 , ARM64_INS_FSQRT = 409 , ARM64_INS_FSUB = 410 , ARM64_INS_FSUBR = 411 , ARM64_INS_FTMAD = 412 , ARM64_INS_FTSMUL = 413 , ARM64_INS_FTSSEL = 414 , ARM64_INS_GMI = 415 , ARM64_INS_HINT = 416 , ARM64_INS_HISTCNT = 417 , ARM64_INS_HISTSEG = 418 , ARM64_INS_HLT = 419 , ARM64_INS_HVC = 420 , ARM64_INS_INCB = 421 , ARM64_INS_INCD = 422 , ARM64_INS_INCH = 423 , ARM64_INS_INCP = 424 , ARM64_INS_INCW = 425 , ARM64_INS_INDEX = 426 , ARM64_INS_INS = 427 , ARM64_INS_INSR = 428 , ARM64_INS_IRG = 429 , ARM64_INS_ISB = 430 , ARM64_INS_LASTA = 431 , ARM64_INS_LASTB = 432 , ARM64_INS_LD1 = 433 , ARM64_INS_LD1B = 434 , ARM64_INS_LD1D = 435 , ARM64_INS_LD1H = 436 , ARM64_INS_LD1Q = 437 , ARM64_INS_LD1R = 438 , ARM64_INS_LD1RB = 439 , ARM64_INS_LD1RD = 440 , ARM64_INS_LD1RH = 441 , ARM64_INS_LD1ROB = 442 , ARM64_INS_LD1ROD = 443 , ARM64_INS_LD1ROH = 444 , ARM64_INS_LD1ROW = 445 , ARM64_INS_LD1RQB = 446 , ARM64_INS_LD1RQD = 447 , ARM64_INS_LD1RQH = 448 , ARM64_INS_LD1RQW = 449 , ARM64_INS_LD1RSB = 450 , ARM64_INS_LD1RSH = 451 , ARM64_INS_LD1RSW = 452 , ARM64_INS_LD1RW = 453 , ARM64_INS_LD1SB = 454 , ARM64_INS_LD1SH = 455 , ARM64_INS_LD1SW = 456 , ARM64_INS_LD1W = 457 , ARM64_INS_LD2 = 458 , ARM64_INS_LD2B = 459 , ARM64_INS_LD2D = 460 , ARM64_INS_LD2H = 461 , ARM64_INS_LD2R = 462 , ARM64_INS_LD2W = 463 , ARM64_INS_LD3 = 464 , ARM64_INS_LD3B = 465 , ARM64_INS_LD3D = 466 , ARM64_INS_LD3H = 467 , ARM64_INS_LD3R = 468 , ARM64_INS_LD3W = 469 , ARM64_INS_LD4 = 470 , ARM64_INS_LD4B = 471 , ARM64_INS_LD4D = 472 , ARM64_INS_LD4H = 473 , ARM64_INS_LD4R = 474 , ARM64_INS_LD4W = 475 , ARM64_INS_LD64B = 476 , ARM64_INS_LDADD = 477 , ARM64_INS_LDADDA = 478 , ARM64_INS_LDADDAB = 479 , ARM64_INS_LDADDAH = 480 , ARM64_INS_LDADDAL = 481 , ARM64_INS_LDADDALB = 482 , ARM64_INS_LDADDALH = 483 , ARM64_INS_LDADDB = 484 , ARM64_INS_LDADDH = 485 , ARM64_INS_LDADDL = 486 , ARM64_INS_LDADDLB = 487 , ARM64_INS_LDADDLH = 488 , ARM64_INS_LDAPR = 489 , ARM64_INS_LDAPRB = 490 , ARM64_INS_LDAPRH = 491 , ARM64_INS_LDAPUR = 492 , ARM64_INS_LDAPURB = 493 , ARM64_INS_LDAPURH = 494 , ARM64_INS_LDAPURSB = 495 , ARM64_INS_LDAPURSH = 496 , ARM64_INS_LDAPURSW = 497 , ARM64_INS_LDAR = 498 , ARM64_INS_LDARB = 499 , ARM64_INS_LDARH = 500 , ARM64_INS_LDAXP = 501 , ARM64_INS_LDAXR = 502 , ARM64_INS_LDAXRB = 503 , ARM64_INS_LDAXRH = 504 , ARM64_INS_LDCLR = 505 , ARM64_INS_LDCLRA = 506 , ARM64_INS_LDCLRAB = 507 , ARM64_INS_LDCLRAH = 508 , ARM64_INS_LDCLRAL = 509 , ARM64_INS_LDCLRALB = 510 , ARM64_INS_LDCLRALH = 511 , ARM64_INS_LDCLRB = 512 , ARM64_INS_LDCLRH = 513 , ARM64_INS_LDCLRL = 514 , ARM64_INS_LDCLRLB = 515 , ARM64_INS_LDCLRLH = 516 , ARM64_INS_LDEOR = 517 , ARM64_INS_LDEORA = 518 , ARM64_INS_LDEORAB = 519 , ARM64_INS_LDEORAH = 520 , ARM64_INS_LDEORAL = 521 , ARM64_INS_LDEORALB = 522 , ARM64_INS_LDEORALH = 523 , ARM64_INS_LDEORB = 524 , ARM64_INS_LDEORH = 525 , ARM64_INS_LDEORL = 526 , ARM64_INS_LDEORLB = 527 , ARM64_INS_LDEORLH = 528 , ARM64_INS_LDFF1B = 529 , ARM64_INS_LDFF1D = 530 , ARM64_INS_LDFF1H = 531 , ARM64_INS_LDFF1SB = 532 , ARM64_INS_LDFF1SH = 533 , ARM64_INS_LDFF1SW = 534 , ARM64_INS_LDFF1W = 535 , ARM64_INS_LDG = 536 , ARM64_INS_LDGM = 537 , ARM64_INS_LDLAR = 538 , ARM64_INS_LDLARB = 539 , ARM64_INS_LDLARH = 540 , ARM64_INS_LDNF1B = 541 , ARM64_INS_LDNF1D = 542 , ARM64_INS_LDNF1H = 543 , ARM64_INS_LDNF1SB = 544 , ARM64_INS_LDNF1SH = 545 , ARM64_INS_LDNF1SW = 546 , ARM64_INS_LDNF1W = 547 , ARM64_INS_LDNP = 548 , ARM64_INS_LDNT1B = 549 , ARM64_INS_LDNT1D = 550 , ARM64_INS_LDNT1H = 551 , ARM64_INS_LDNT1SB = 552 , ARM64_INS_LDNT1SH = 553 , ARM64_INS_LDNT1SW = 554 , ARM64_INS_LDNT1W = 555 , ARM64_INS_LDP = 556 , ARM64_INS_LDPSW = 557 , ARM64_INS_LDR = 558 , ARM64_INS_LDRAA = 559 , ARM64_INS_LDRAB = 560 , ARM64_INS_LDRB = 561 , ARM64_INS_LDRH = 562 , ARM64_INS_LDRSB = 563 , ARM64_INS_LDRSH = 564 , ARM64_INS_LDRSW = 565 , ARM64_INS_LDSET = 566 , ARM64_INS_LDSETA = 567 , ARM64_INS_LDSETAB = 568 , ARM64_INS_LDSETAH = 569 , ARM64_INS_LDSETAL = 570 , ARM64_INS_LDSETALB = 571 , ARM64_INS_LDSETALH = 572 , ARM64_INS_LDSETB = 573 , ARM64_INS_LDSETH = 574 , ARM64_INS_LDSETL = 575 , ARM64_INS_LDSETLB = 576 , ARM64_INS_LDSETLH = 577 , ARM64_INS_LDSMAX = 578 , ARM64_INS_LDSMAXA = 579 , ARM64_INS_LDSMAXAB = 580 , ARM64_INS_LDSMAXAH = 581 , ARM64_INS_LDSMAXAL = 582 , ARM64_INS_LDSMAXALB = 583 , ARM64_INS_LDSMAXALH = 584 , ARM64_INS_LDSMAXB = 585 , ARM64_INS_LDSMAXH = 586 , ARM64_INS_LDSMAXL = 587 , ARM64_INS_LDSMAXLB = 588 , ARM64_INS_LDSMAXLH = 589 , ARM64_INS_LDSMIN = 590 , ARM64_INS_LDSMINA = 591 , ARM64_INS_LDSMINAB = 592 , ARM64_INS_LDSMINAH = 593 , ARM64_INS_LDSMINAL = 594 , ARM64_INS_LDSMINALB = 595 , ARM64_INS_LDSMINALH = 596 , ARM64_INS_LDSMINB = 597 , ARM64_INS_LDSMINH = 598 , ARM64_INS_LDSMINL = 599 , ARM64_INS_LDSMINLB = 600 , ARM64_INS_LDSMINLH = 601 , ARM64_INS_LDTR = 602 , ARM64_INS_LDTRB = 603 , ARM64_INS_LDTRH = 604 , ARM64_INS_LDTRSB = 605 , ARM64_INS_LDTRSH = 606 , ARM64_INS_LDTRSW = 607 , ARM64_INS_LDUMAX = 608 , ARM64_INS_LDUMAXA = 609 , ARM64_INS_LDUMAXAB = 610 , ARM64_INS_LDUMAXAH = 611 , ARM64_INS_LDUMAXAL = 612 , ARM64_INS_LDUMAXALB = 613 , ARM64_INS_LDUMAXALH = 614 , ARM64_INS_LDUMAXB = 615 , ARM64_INS_LDUMAXH = 616 , ARM64_INS_LDUMAXL = 617 , ARM64_INS_LDUMAXLB = 618 , ARM64_INS_LDUMAXLH = 619 , ARM64_INS_LDUMIN = 620 , ARM64_INS_LDUMINA = 621 , ARM64_INS_LDUMINAB = 622 , ARM64_INS_LDUMINAH = 623 , ARM64_INS_LDUMINAL = 624 , ARM64_INS_LDUMINALB = 625 , ARM64_INS_LDUMINALH = 626 , ARM64_INS_LDUMINB = 627 , ARM64_INS_LDUMINH = 628 , ARM64_INS_LDUMINL = 629 , ARM64_INS_LDUMINLB = 630 , ARM64_INS_LDUMINLH = 631 , ARM64_INS_LDUR = 632 , ARM64_INS_LDURB = 633 , ARM64_INS_LDURH = 634 , ARM64_INS_LDURSB = 635 , ARM64_INS_LDURSH = 636 , ARM64_INS_LDURSW = 637 , ARM64_INS_LDXP = 638 , ARM64_INS_LDXR = 639 , ARM64_INS_LDXRB = 640 , ARM64_INS_LDXRH = 641 , ARM64_INS_LSL = 642 , ARM64_INS_LSLR = 643 , ARM64_INS_LSLV = 644 , ARM64_INS_LSR = 645 , ARM64_INS_LSRR = 646 , ARM64_INS_LSRV = 647 , ARM64_INS_MAD = 648 , ARM64_INS_MADD = 649 , ARM64_INS_MATCH = 650 , ARM64_INS_MLA = 651 , ARM64_INS_MLS = 652 , ARM64_INS_MNEG = 653 , ARM64_INS_MOV = 654 , ARM64_INS_MOVA = 655 , ARM64_INS_MOVI = 656 , ARM64_INS_MOVK = 657 , ARM64_INS_MOVN = 658 , ARM64_INS_MOVPRFX = 659 , ARM64_INS_MOVS = 660 , ARM64_INS_MOVZ = 661 , ARM64_INS_MRS = 662 , ARM64_INS_MSB = 663 , ARM64_INS_MSR = 664 , ARM64_INS_MSUB = 665 , ARM64_INS_MUL = 666 , ARM64_INS_MVN = 667 , ARM64_INS_MVNI = 668 , ARM64_INS_NAND = 669 , ARM64_INS_NANDS = 670 , ARM64_INS_NBSL = 671 , ARM64_INS_NEG = 672 , ARM64_INS_NEGS = 673 , ARM64_INS_NGC = 674 , ARM64_INS_NGCS = 675 , ARM64_INS_NMATCH = 676 , ARM64_INS_NOP = 677 , ARM64_INS_NOR = 678 , ARM64_INS_NORS = 679 , ARM64_INS_NOT = 680 , ARM64_INS_NOTS = 681 , ARM64_INS_ORN = 682 , ARM64_INS_ORNS = 683 , ARM64_INS_ORR = 684 , ARM64_INS_ORRS = 685 , ARM64_INS_ORV = 686 , ARM64_INS_PACDA = 687 , ARM64_INS_PACDB = 688 , ARM64_INS_PACDZA = 689 , ARM64_INS_PACDZB = 690 , ARM64_INS_PACGA = 691 , ARM64_INS_PACIA = 692 , ARM64_INS_PACIA1716 = 693 , ARM64_INS_PACIASP = 694 , ARM64_INS_PACIAZ = 695 , ARM64_INS_PACIB = 696 , ARM64_INS_PACIB1716 = 697 , ARM64_INS_PACIBSP = 698 , ARM64_INS_PACIBZ = 699 , ARM64_INS_PACIZA = 700 , ARM64_INS_PACIZB = 701 , ARM64_INS_PFALSE = 702 , ARM64_INS_PFIRST = 703 , ARM64_INS_PMUL = 704 , ARM64_INS_PMULL = 705 , ARM64_INS_PMULL2 = 706 , ARM64_INS_PMULLB = 707 , ARM64_INS_PMULLT = 708 , ARM64_INS_PNEXT = 709 , ARM64_INS_PRFB = 710 , ARM64_INS_PRFD = 711 , ARM64_INS_PRFH = 712 , ARM64_INS_PRFM = 713 , ARM64_INS_PRFUM = 714 , ARM64_INS_PRFW = 715 , ARM64_INS_PSB = 716 , ARM64_INS_PSEL = 717 , ARM64_INS_PSSBB = 718 , ARM64_INS_PTEST = 719 , ARM64_INS_PTRUE = 720 , ARM64_INS_PTRUES = 721 , ARM64_INS_PUNPKHI = 722 , ARM64_INS_PUNPKLO = 723 , ARM64_INS_RADDHN = 724 , ARM64_INS_RADDHN2 = 725 , ARM64_INS_RADDHNB = 726 , ARM64_INS_RADDHNT = 727 , ARM64_INS_RAX1 = 728 , ARM64_INS_RBIT = 729 , ARM64_INS_RDFFR = 730 , ARM64_INS_RDFFRS = 731 , ARM64_INS_RDVL = 732 , ARM64_INS_RET = 733 , ARM64_INS_RETAA = 734 , ARM64_INS_RETAB = 735 , ARM64_INS_REV = 736 , ARM64_INS_REV16 = 737 , ARM64_INS_REV32 = 738 , ARM64_INS_REV64 = 739 , ARM64_INS_REVB = 740 , ARM64_INS_REVD = 741 , ARM64_INS_REVH = 742 , ARM64_INS_REVW = 743 , ARM64_INS_RMIF = 744 , ARM64_INS_ROR = 745 , ARM64_INS_RORV = 746 , ARM64_INS_RSHRN = 747 , ARM64_INS_RSHRN2 = 748 , ARM64_INS_RSHRNB = 749 , ARM64_INS_RSHRNT = 750 , ARM64_INS_RSUBHN = 751 , ARM64_INS_RSUBHN2 = 752 , ARM64_INS_RSUBHNB = 753 , ARM64_INS_RSUBHNT = 754 , ARM64_INS_SABA = 755 , ARM64_INS_SABAL = 756 , ARM64_INS_SABAL2 = 757 , ARM64_INS_SABALB = 758 , ARM64_INS_SABALT = 759 , ARM64_INS_SABD = 760 , ARM64_INS_SABDL = 761 , ARM64_INS_SABDL2 = 762 , ARM64_INS_SABDLB = 763 , ARM64_INS_SABDLT = 764 , ARM64_INS_SADALP = 765 , ARM64_INS_SADDL = 766 , ARM64_INS_SADDL2 = 767 , ARM64_INS_SADDLB = 768 , ARM64_INS_SADDLBT = 769 , ARM64_INS_SADDLP = 770 , ARM64_INS_SADDLT = 771 , ARM64_INS_SADDLV = 772 , ARM64_INS_SADDV = 773 , ARM64_INS_SADDW = 774 , ARM64_INS_SADDW2 = 775 , ARM64_INS_SADDWB = 776 , ARM64_INS_SADDWT = 777 , ARM64_INS_SB = 778 , ARM64_INS_SBC = 779 , ARM64_INS_SBCLB = 780 , ARM64_INS_SBCLT = 781 , ARM64_INS_SBCS = 782 , ARM64_INS_SBFM = 783 , ARM64_INS_SCLAMP = 784 , ARM64_INS_SCVTF = 785 , ARM64_INS_SDIV = 786 , ARM64_INS_SDIVR = 787 , ARM64_INS_SDOT = 788 , ARM64_INS_SEL = 789 , ARM64_INS_SETE = 790 , ARM64_INS_SETEN = 791 , ARM64_INS_SETET = 792 , ARM64_INS_SETETN = 793 , ARM64_INS_SETF16 = 794 , ARM64_INS_SETF8 = 795 , ARM64_INS_SETFFR = 796 , ARM64_INS_SETGE = 797 , ARM64_INS_SETGEN = 798 , ARM64_INS_SETGET = 799 , ARM64_INS_SETGETN = 800 , ARM64_INS_SETGM = 801 , ARM64_INS_SETGMN = 802 , ARM64_INS_SETGMT = 803 , ARM64_INS_SETGMTN = 804 , ARM64_INS_SETGP = 805 , ARM64_INS_SETGPN = 806 , ARM64_INS_SETGPT = 807 , ARM64_INS_SETGPTN = 808 , ARM64_INS_SETM = 809 , ARM64_INS_SETMN = 810 , ARM64_INS_SETMT = 811 , ARM64_INS_SETMTN = 812 , ARM64_INS_SETP = 813 , ARM64_INS_SETPN = 814 , ARM64_INS_SETPT = 815 , ARM64_INS_SETPTN = 816 , ARM64_INS_SEV = 817 , ARM64_INS_SEVL = 818 , ARM64_INS_SHA1C = 819 , ARM64_INS_SHA1H = 820 , ARM64_INS_SHA1M = 821 , ARM64_INS_SHA1P = 822 , ARM64_INS_SHA1SU0 = 823 , ARM64_INS_SHA1SU1 = 824 , ARM64_INS_SHA256H = 825 , ARM64_INS_SHA256H2 = 826 , ARM64_INS_SHA256SU0 = 827 , ARM64_INS_SHA256SU1 = 828 , ARM64_INS_SHA512H = 829 , ARM64_INS_SHA512H2 = 830 , ARM64_INS_SHA512SU0 = 831 , ARM64_INS_SHA512SU1 = 832 , ARM64_INS_SHADD = 833 , ARM64_INS_SHL = 834 , ARM64_INS_SHLL = 835 , ARM64_INS_SHLL2 = 836 , ARM64_INS_SHRN = 837 , ARM64_INS_SHRN2 = 838 , ARM64_INS_SHRNB = 839 , ARM64_INS_SHRNT = 840 , ARM64_INS_SHSUB = 841 , ARM64_INS_SHSUBR = 842 , ARM64_INS_SLI = 843 , ARM64_INS_SM3PARTW1 = 844 , ARM64_INS_SM3PARTW2 = 845 , ARM64_INS_SM3SS1 = 846 , ARM64_INS_SM3TT1A = 847 , ARM64_INS_SM3TT1B = 848 , ARM64_INS_SM3TT2A = 849 , ARM64_INS_SM3TT2B = 850 , ARM64_INS_SM4E = 851 , ARM64_INS_SM4EKEY = 852 , ARM64_INS_SMADDL = 853 , ARM64_INS_SMAX = 854 , ARM64_INS_SMAXP = 855 , ARM64_INS_SMAXV = 856 , ARM64_INS_SMC = 857 , ARM64_INS_SMIN = 858 , ARM64_INS_SMINP = 859 , ARM64_INS_SMINV = 860 , ARM64_INS_SMLAL = 861 , ARM64_INS_SMLAL2 = 862 , ARM64_INS_SMLALB = 863 , ARM64_INS_SMLALT = 864 , ARM64_INS_SMLSL = 865 , ARM64_INS_SMLSL2 = 866 , ARM64_INS_SMLSLB = 867 , ARM64_INS_SMLSLT = 868 , ARM64_INS_SMMLA = 869 , ARM64_INS_SMNEGL = 870 , ARM64_INS_SMOPA = 871 , ARM64_INS_SMOPS = 872 , ARM64_INS_SMOV = 873 , ARM64_INS_SMSTART = 874 , ARM64_INS_SMSTOP = 875 , ARM64_INS_SMSUBL = 876 , ARM64_INS_SMULH = 877 , ARM64_INS_SMULL = 878 , ARM64_INS_SMULL2 = 879 , ARM64_INS_SMULLB = 880 , ARM64_INS_SMULLT = 881 , ARM64_INS_SPLICE = 882 , ARM64_INS_SQABS = 883 , ARM64_INS_SQADD = 884 , ARM64_INS_SQCADD = 885 , ARM64_INS_SQDECB = 886 , ARM64_INS_SQDECD = 887 , ARM64_INS_SQDECH = 888 , ARM64_INS_SQDECP = 889 , ARM64_INS_SQDECW = 890 , ARM64_INS_SQDMLAL = 891 , ARM64_INS_SQDMLAL2 = 892 , ARM64_INS_SQDMLALB = 893 , ARM64_INS_SQDMLALBT = 894 , ARM64_INS_SQDMLALT = 895 , ARM64_INS_SQDMLSL = 896 , ARM64_INS_SQDMLSL2 = 897 , ARM64_INS_SQDMLSLB = 898 , ARM64_INS_SQDMLSLBT = 899 , ARM64_INS_SQDMLSLT = 900 , ARM64_INS_SQDMULH = 901 , ARM64_INS_SQDMULL = 902 , ARM64_INS_SQDMULL2 = 903 , ARM64_INS_SQDMULLB = 904 , ARM64_INS_SQDMULLT = 905 , ARM64_INS_SQINCB = 906 , ARM64_INS_SQINCD = 907 , ARM64_INS_SQINCH = 908 , ARM64_INS_SQINCP = 909 , ARM64_INS_SQINCW = 910 , ARM64_INS_SQNEG = 911 , ARM64_INS_SQRDCMLAH = 912 , ARM64_INS_SQRDMLAH = 913 , ARM64_INS_SQRDMLSH = 914 , ARM64_INS_SQRDMULH = 915 , ARM64_INS_SQRSHL = 916 , ARM64_INS_SQRSHLR = 917 , ARM64_INS_SQRSHRN = 918 , ARM64_INS_SQRSHRN2 = 919 , ARM64_INS_SQRSHRNB = 920 , ARM64_INS_SQRSHRNT = 921 , ARM64_INS_SQRSHRUN = 922 , ARM64_INS_SQRSHRUN2 = 923 , ARM64_INS_SQRSHRUNB = 924 , ARM64_INS_SQRSHRUNT = 925 , ARM64_INS_SQSHL = 926 , ARM64_INS_SQSHLR = 927 , ARM64_INS_SQSHLU = 928 , ARM64_INS_SQSHRN = 929 , ARM64_INS_SQSHRN2 = 930 , ARM64_INS_SQSHRNB = 931 , ARM64_INS_SQSHRNT = 932 , ARM64_INS_SQSHRUN = 933 , ARM64_INS_SQSHRUN2 = 934 , ARM64_INS_SQSHRUNB = 935 , ARM64_INS_SQSHRUNT = 936 , ARM64_INS_SQSUB = 937 , ARM64_INS_SQSUBR = 938 , ARM64_INS_SQXTN = 939 , ARM64_INS_SQXTN2 = 940 , ARM64_INS_SQXTNB = 941 , ARM64_INS_SQXTNT = 942 , ARM64_INS_SQXTUN = 943 , ARM64_INS_SQXTUN2 = 944 , ARM64_INS_SQXTUNB = 945 , ARM64_INS_SQXTUNT = 946 , ARM64_INS_SRHADD = 947 , ARM64_INS_SRI = 948 , ARM64_INS_SRSHL = 949 , ARM64_INS_SRSHLR = 950 , ARM64_INS_SRSHR = 951 , ARM64_INS_SRSRA = 952 , ARM64_INS_SSBB = 953 , ARM64_INS_SSHL = 954 , ARM64_INS_SSHLL = 955 , ARM64_INS_SSHLL2 = 956 , ARM64_INS_SSHLLB = 957 , ARM64_INS_SSHLLT = 958 , ARM64_INS_SSHR = 959 , ARM64_INS_SSRA = 960 , ARM64_INS_SSUBL = 961 , ARM64_INS_SSUBL2 = 962 , ARM64_INS_SSUBLB = 963 , ARM64_INS_SSUBLBT = 964 , ARM64_INS_SSUBLT = 965 , ARM64_INS_SSUBLTB = 966 , ARM64_INS_SSUBW = 967 , ARM64_INS_SSUBW2 = 968 , ARM64_INS_SSUBWB = 969 , ARM64_INS_SSUBWT = 970 , ARM64_INS_ST1 = 971 , ARM64_INS_ST1B = 972 , ARM64_INS_ST1D = 973 , ARM64_INS_ST1H = 974 , ARM64_INS_ST1Q = 975 , ARM64_INS_ST1W = 976 , ARM64_INS_ST2 = 977 , ARM64_INS_ST2B = 978 , ARM64_INS_ST2D = 979 , ARM64_INS_ST2G = 980 , ARM64_INS_ST2H = 981 , ARM64_INS_ST2W = 982 , ARM64_INS_ST3 = 983 , ARM64_INS_ST3B = 984 , ARM64_INS_ST3D = 985 , ARM64_INS_ST3H = 986 , ARM64_INS_ST3W = 987 , ARM64_INS_ST4 = 988 , ARM64_INS_ST4B = 989 , ARM64_INS_ST4D = 990 , ARM64_INS_ST4H = 991 , ARM64_INS_ST4W = 992 , ARM64_INS_ST64B = 993 , ARM64_INS_ST64BV = 994 , ARM64_INS_ST64BV0 = 995 , ARM64_INS_STADD = 996 , ARM64_INS_STADDB = 997 , ARM64_INS_STADDH = 998 , ARM64_INS_STADDL = 999 , ARM64_INS_STADDLB = 1000 , ARM64_INS_STADDLH = 1001 , ARM64_INS_STCLR = 1002 , ARM64_INS_STCLRB = 1003 , ARM64_INS_STCLRH = 1004 , ARM64_INS_STCLRL = 1005 , ARM64_INS_STCLRLB = 1006 , ARM64_INS_STCLRLH = 1007 , ARM64_INS_STEOR = 1008 , ARM64_INS_STEORB = 1009 , ARM64_INS_STEORH = 1010 , ARM64_INS_STEORL = 1011 , ARM64_INS_STEORLB = 1012 , ARM64_INS_STEORLH = 1013 , ARM64_INS_STG = 1014 , ARM64_INS_STGM = 1015 , ARM64_INS_STGP = 1016 , ARM64_INS_STLLR = 1017 , ARM64_INS_STLLRB = 1018 , ARM64_INS_STLLRH = 1019 , ARM64_INS_STLR = 1020 , ARM64_INS_STLRB = 1021 , ARM64_INS_STLRH = 1022 , ARM64_INS_STLUR = 1023 , ARM64_INS_STLURB = 1024 , ARM64_INS_STLURH = 1025 , ARM64_INS_STLXP = 1026 , ARM64_INS_STLXR = 1027 , ARM64_INS_STLXRB = 1028 , ARM64_INS_STLXRH = 1029 , ARM64_INS_STNP = 1030 , ARM64_INS_STNT1B = 1031 , ARM64_INS_STNT1D = 1032 , ARM64_INS_STNT1H = 1033 , ARM64_INS_STNT1W = 1034 , ARM64_INS_STP = 1035 , ARM64_INS_STR = 1036 , ARM64_INS_STRB = 1037 , ARM64_INS_STRH = 1038 , ARM64_INS_STSET = 1039 , ARM64_INS_STSETB = 1040 , ARM64_INS_STSETH = 1041 , ARM64_INS_STSETL = 1042 , ARM64_INS_STSETLB = 1043 , ARM64_INS_STSETLH = 1044 , ARM64_INS_STSMAX = 1045 , ARM64_INS_STSMAXB = 1046 , ARM64_INS_STSMAXH = 1047 , ARM64_INS_STSMAXL = 1048 , ARM64_INS_STSMAXLB = 1049 , ARM64_INS_STSMAXLH = 1050 , ARM64_INS_STSMIN = 1051 , ARM64_INS_STSMINB = 1052 , ARM64_INS_STSMINH = 1053 , ARM64_INS_STSMINL = 1054 , ARM64_INS_STSMINLB = 1055 , ARM64_INS_STSMINLH = 1056 , ARM64_INS_STTR = 1057 , ARM64_INS_STTRB = 1058 , ARM64_INS_STTRH = 1059 , ARM64_INS_STUMAX = 1060 , ARM64_INS_STUMAXB = 1061 , ARM64_INS_STUMAXH = 1062 , ARM64_INS_STUMAXL = 1063 , ARM64_INS_STUMAXLB = 1064 , ARM64_INS_STUMAXLH = 1065 , ARM64_INS_STUMIN = 1066 , ARM64_INS_STUMINB = 1067 , ARM64_INS_STUMINH = 1068 , ARM64_INS_STUMINL = 1069 , ARM64_INS_STUMINLB = 1070 , ARM64_INS_STUMINLH = 1071 , ARM64_INS_STUR = 1072 , ARM64_INS_STURB = 1073 , ARM64_INS_STURH = 1074 , ARM64_INS_STXP = 1075 , ARM64_INS_STXR = 1076 , ARM64_INS_STXRB = 1077 , ARM64_INS_STXRH = 1078 , ARM64_INS_STZ2G = 1079 , ARM64_INS_STZG = 1080 , ARM64_INS_STZGM = 1081 , ARM64_INS_SUB = 1082 , ARM64_INS_SUBG = 1083 , ARM64_INS_SUBHN = 1084 , ARM64_INS_SUBHN2 = 1085 , ARM64_INS_SUBHNB = 1086 , ARM64_INS_SUBHNT = 1087 , ARM64_INS_SUBP = 1088 , ARM64_INS_SUBPS = 1089 , ARM64_INS_SUBR = 1090 , ARM64_INS_SUBS = 1091 , ARM64_INS_SUDOT = 1092 , ARM64_INS_SUMOPA = 1093 , ARM64_INS_SUMOPS = 1094 , ARM64_INS_SUNPKHI = 1095 , ARM64_INS_SUNPKLO = 1096 , ARM64_INS_SUQADD = 1097 , ARM64_INS_SVC = 1098 , ARM64_INS_SWP = 1099 , ARM64_INS_SWPA = 1100 , ARM64_INS_SWPAB = 1101 , ARM64_INS_SWPAH = 1102 , ARM64_INS_SWPAL = 1103 , ARM64_INS_SWPALB = 1104 , ARM64_INS_SWPALH = 1105 , ARM64_INS_SWPB = 1106 , ARM64_INS_SWPH = 1107 , ARM64_INS_SWPL = 1108 , ARM64_INS_SWPLB = 1109 , ARM64_INS_SWPLH = 1110 , ARM64_INS_SXTB = 1111 , ARM64_INS_SXTH = 1112 , ARM64_INS_SXTL = 1113 , ARM64_INS_SXTL2 = 1114 , ARM64_INS_SXTW = 1115 , ARM64_INS_SYS = 1116 , ARM64_INS_SYSL = 1117 , ARM64_INS_TBL = 1118 , ARM64_INS_TBNZ = 1119 , ARM64_INS_TBX = 1120 , ARM64_INS_TBZ = 1121 , ARM64_INS_TCANCEL = 1122 , ARM64_INS_TCOMMIT = 1123 , ARM64_INS_TRN1 = 1124 , ARM64_INS_TRN2 = 1125 , ARM64_INS_TSB = 1126 , ARM64_INS_TST = 1127 , ARM64_INS_TSTART = 1128 , ARM64_INS_TTEST = 1129 , ARM64_INS_UABA = 1130 , ARM64_INS_UABAL = 1131 , ARM64_INS_UABAL2 = 1132 , ARM64_INS_UABALB = 1133 , ARM64_INS_UABALT = 1134 , ARM64_INS_UABD = 1135 , ARM64_INS_UABDL = 1136 , ARM64_INS_UABDL2 = 1137 , ARM64_INS_UABDLB = 1138 , ARM64_INS_UABDLT = 1139 , ARM64_INS_UADALP = 1140 , ARM64_INS_UADDL = 1141 , ARM64_INS_UADDL2 = 1142 , ARM64_INS_UADDLB = 1143 , ARM64_INS_UADDLP = 1144 , ARM64_INS_UADDLT = 1145 , ARM64_INS_UADDLV = 1146 , ARM64_INS_UADDV = 1147 , ARM64_INS_UADDW = 1148 , ARM64_INS_UADDW2 = 1149 , ARM64_INS_UADDWB = 1150 , ARM64_INS_UADDWT = 1151 , ARM64_INS_UBFM = 1152 , ARM64_INS_UCLAMP = 1153 , ARM64_INS_UCVTF = 1154 , ARM64_INS_UDF = 1155 , ARM64_INS_UDIV = 1156 , ARM64_INS_UDIVR = 1157 , ARM64_INS_UDOT = 1158 , ARM64_INS_UHADD = 1159 , ARM64_INS_UHSUB = 1160 , ARM64_INS_UHSUBR = 1161 , ARM64_INS_UMADDL = 1162 , ARM64_INS_UMAX = 1163 , ARM64_INS_UMAXP = 1164 , ARM64_INS_UMAXV = 1165 , ARM64_INS_UMIN = 1166 , ARM64_INS_UMINP = 1167 , ARM64_INS_UMINV = 1168 , ARM64_INS_UMLAL = 1169 , ARM64_INS_UMLAL2 = 1170 , ARM64_INS_UMLALB = 1171 , ARM64_INS_UMLALT = 1172 , ARM64_INS_UMLSL = 1173 , ARM64_INS_UMLSL2 = 1174 , ARM64_INS_UMLSLB = 1175 , ARM64_INS_UMLSLT = 1176 , ARM64_INS_UMMLA = 1177 , ARM64_INS_UMNEGL = 1178 , ARM64_INS_UMOPA = 1179 , ARM64_INS_UMOPS = 1180 , ARM64_INS_UMOV = 1181 , ARM64_INS_UMSUBL = 1182 , ARM64_INS_UMULH = 1183 , ARM64_INS_UMULL = 1184 , ARM64_INS_UMULL2 = 1185 , ARM64_INS_UMULLB = 1186 , ARM64_INS_UMULLT = 1187 , ARM64_INS_UQADD = 1188 , ARM64_INS_UQDECB = 1189 , ARM64_INS_UQDECD = 1190 , ARM64_INS_UQDECH = 1191 , ARM64_INS_UQDECP = 1192 , ARM64_INS_UQDECW = 1193 , ARM64_INS_UQINCB = 1194 , ARM64_INS_UQINCD = 1195 , ARM64_INS_UQINCH = 1196 , ARM64_INS_UQINCP = 1197 , ARM64_INS_UQINCW = 1198 , ARM64_INS_UQRSHL = 1199 , ARM64_INS_UQRSHLR = 1200 , ARM64_INS_UQRSHRN = 1201 , ARM64_INS_UQRSHRN2 = 1202 , ARM64_INS_UQRSHRNB = 1203 , ARM64_INS_UQRSHRNT = 1204 , ARM64_INS_UQSHL = 1205 , ARM64_INS_UQSHLR = 1206 , ARM64_INS_UQSHRN = 1207 , ARM64_INS_UQSHRN2 = 1208 , ARM64_INS_UQSHRNB = 1209 , ARM64_INS_UQSHRNT = 1210 , ARM64_INS_UQSUB = 1211 , ARM64_INS_UQSUBR = 1212 , ARM64_INS_UQXTN = 1213 , ARM64_INS_UQXTN2 = 1214 , ARM64_INS_UQXTNB = 1215 , ARM64_INS_UQXTNT = 1216 , ARM64_INS_URECPE = 1217 , ARM64_INS_URHADD = 1218 , ARM64_INS_URSHL = 1219 , ARM64_INS_URSHLR = 1220 , ARM64_INS_URSHR = 1221 , ARM64_INS_URSQRTE = 1222 , ARM64_INS_URSRA = 1223 , ARM64_INS_USDOT = 1224 , ARM64_INS_USHL = 1225 , ARM64_INS_USHLL = 1226 , ARM64_INS_USHLL2 = 1227 , ARM64_INS_USHLLB = 1228 , ARM64_INS_USHLLT = 1229 , ARM64_INS_USHR = 1230 , ARM64_INS_USMMLA = 1231 , ARM64_INS_USMOPA = 1232 , ARM64_INS_USMOPS = 1233 , ARM64_INS_USQADD = 1234 , ARM64_INS_USRA = 1235 , ARM64_INS_USUBL = 1236 , ARM64_INS_USUBL2 = 1237 , ARM64_INS_USUBLB = 1238 , ARM64_INS_USUBLT = 1239 , ARM64_INS_USUBW = 1240 , ARM64_INS_USUBW2 = 1241 , ARM64_INS_USUBWB = 1242 , ARM64_INS_USUBWT = 1243 , ARM64_INS_UUNPKHI = 1244 , ARM64_INS_UUNPKLO = 1245 , ARM64_INS_UXTB = 1246 , ARM64_INS_UXTH = 1247 , ARM64_INS_UXTL = 1248 , ARM64_INS_UXTL2 = 1249 , ARM64_INS_UXTW = 1250 , ARM64_INS_UZP1 = 1251 , ARM64_INS_UZP2 = 1252 , ARM64_INS_WFE = 1253 , ARM64_INS_WFET = 1254 , ARM64_INS_WFI = 1255 , ARM64_INS_WFIT = 1256 , ARM64_INS_WHILEGE = 1257 , ARM64_INS_WHILEGT = 1258 , ARM64_INS_WHILEHI = 1259 , ARM64_INS_WHILEHS = 1260 , ARM64_INS_WHILELE = 1261 , ARM64_INS_WHILELO = 1262 , ARM64_INS_WHILELS = 1263 , ARM64_INS_WHILELT = 1264 , ARM64_INS_WHILERW = 1265 , ARM64_INS_WHILEWR = 1266 , ARM64_INS_WRFFR = 1267 , ARM64_INS_XAFLAG = 1268 , ARM64_INS_XAR = 1269 , ARM64_INS_XPACD = 1270 , ARM64_INS_XPACI = 1271 , ARM64_INS_XPACLRI = 1272 , ARM64_INS_XTN = 1273 , ARM64_INS_XTN2 = 1274 , ARM64_INS_YIELD = 1275 , ARM64_INS_ZERO = 1276 , ARM64_INS_ZIP1 = 1277 , ARM64_INS_ZIP2 = 1278 , ARM64_INS_SBFIZ = 1279 , ARM64_INS_UBFIZ = 1280 , ARM64_INS_SBFX = 1281 , ARM64_INS_UBFX = 1282 , ARM64_INS_BFI = 1283 , ARM64_INS_BFXIL = 1284 , ARM64_INS_IC = 1285 , ARM64_INS_DC = 1286 , ARM64_INS_AT = 1287 , ARM64_INS_TLBI = 1288 , ARM64_INS_ENDING = 1289 , } # [repr (u32)] # [doc = " Group of ARM64 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM64_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM64_GRP_JUMP = 1 , ARM64_GRP_CALL = 2 , ARM64_GRP_RET = 3 , ARM64_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM64_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM64_GRP_BRANCH_RELATIVE = 7 , ARM64_GRP_PAC = 8 , ARM64_GRP_CRYPTO = 128 , ARM64_GRP_FPARMV8 = 129 , ARM64_GRP_NEON = 130 , ARM64_GRP_CRC = 131 , ARM64_GRP_AES = 132 , ARM64_GRP_DOTPROD = 133 , ARM64_GRP_FULLFP16 = 134 , ARM64_GRP_LSE = 135 , ARM64_GRP_RCPC = 136 , ARM64_GRP_RDM = 137 , ARM64_GRP_SHA2 = 138 , ARM64_GRP_SHA3 = 139 , ARM64_GRP_SM4 = 140 , ARM64_GRP_SVE = 141 , ARM64_GRP_SVE2 = 142 , ARM64_GRP_SVE2AES = 143 , ARM64_GRP_SVE2BitPerm = 144 , ARM64_GRP_SVE2SHA3 = 145 , ARM64_GRP_SVE2SM4 = 146 , ARM64_GRP_SME = 147 , ARM64_GRP_SMEF64 = 148 , ARM64_GRP_SMEI64 = 149 , ARM64_GRP_MatMulFP32 = 150 , ARM64_GRP_MatMulFP64 = 151 , ARM64_GRP_MatMulInt8 = 152 , ARM64_GRP_V8_1A = 153 , ARM64_GRP_V8_3A = 154 , ARM64_GRP_V8_4A = 155 , ARM64_GRP_ENDING = 156 , } # [repr (u32)] # [doc = " M68K registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_reg { M68K_REG_INVALID = 0 , M68K_REG_D0 = 1 , M68K_REG_D1 = 2 , M68K_REG_D2 = 3 , M68K_REG_D3 = 4 , M68K_REG_D4 = 5 , M68K_REG_D5 = 6 , M68K_REG_D6 = 7 , M68K_REG_D7 = 8 , M68K_REG_A0 = 9 , M68K_REG_A1 = 10 , M68K_REG_A2 = 11 , M68K_REG_A3 = 12 , M68K_REG_A4 = 13 , M68K_REG_A5 = 14 , M68K_REG_A6 = 15 , M68K_REG_A7 = 16 , M68K_REG_FP0 = 17 , M68K_REG_FP1 = 18 , M68K_REG_FP2 = 19 , M68K_REG_FP3 = 20 , M68K_REG_FP4 = 21 , M68K_REG_FP5 = 22 , M68K_REG_FP6 = 23 , M68K_REG_FP7 = 24 , M68K_REG_PC = 25 , M68K_REG_SR = 26 , M68K_REG_CCR = 27 , M68K_REG_SFC = 28 , M68K_REG_DFC = 29 , M68K_REG_USP = 30 , M68K_REG_VBR = 31 , M68K_REG_CACR = 32 , M68K_REG_CAAR = 33 , M68K_REG_MSP = 34 , M68K_REG_ISP = 35 , M68K_REG_TC = 36 , M68K_REG_ITT0 = 37 , M68K_REG_ITT1 = 38 , M68K_REG_DTT0 = 39 , M68K_REG_DTT1 = 40 , M68K_REG_MMUSR = 41 , M68K_REG_URP = 42 , M68K_REG_SRP = 43 , M68K_REG_FPCR = 44 , M68K_REG_FPSR = 45 , M68K_REG_FPIAR = 46 , M68K_REG_ENDING = 47 , } # [repr (u32)] # [doc = " M68K Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_address_mode { # [doc = "< No address mode."] M68K_AM_NONE = 0 , # [doc = "< Register Direct - Data"] M68K_AM_REG_DIRECT_DATA = 1 , # [doc = "< Register Direct - Address"] M68K_AM_REG_DIRECT_ADDR = 2 , # [doc = "< Register Indirect - Address"] M68K_AM_REGI_ADDR = 3 , # [doc = "< Register Indirect - Address with Postincrement"] M68K_AM_REGI_ADDR_POST_INC = 4 , # [doc = "< Register Indirect - Address with Predecrement"] M68K_AM_REGI_ADDR_PRE_DEC = 5 , # [doc = "< Register Indirect - Address with Displacement"] M68K_AM_REGI_ADDR_DISP = 6 , # [doc = "< Address Register Indirect With Index- 8-bit displacement"] M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 , # [doc = "< Address Register Indirect With Index- Base displacement"] M68K_AM_AREGI_INDEX_BASE_DISP = 8 , # [doc = "< Memory indirect - Postindex"] M68K_AM_MEMI_POST_INDEX = 9 , # [doc = "< Memory indirect - Preindex"] M68K_AM_MEMI_PRE_INDEX = 10 , # [doc = "< Program Counter Indirect - with Displacement"] M68K_AM_PCI_DISP = 11 , # [doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"] M68K_AM_PCI_INDEX_8_BIT_DISP = 12 , # [doc = "< Program Counter Indirect with Index - with Base Displacement"] M68K_AM_PCI_INDEX_BASE_DISP = 13 , # [doc = "< Program Counter Memory Indirect - Postindexed"] M68K_AM_PC_MEMI_POST_INDEX = 14 , # [doc = "< Program Counter Memory Indirect - Preindexed"] M68K_AM_PC_MEMI_PRE_INDEX = 15 , # [doc = "< Absolute Data Addressing  - Short"] M68K_AM_ABSOLUTE_DATA_SHORT = 16 , # [doc = "< Absolute Data Addressing  - Long"] M68K_AM_ABSOLUTE_DATA_LONG = 17 , # [doc = "< Immediate value"] M68K_AM_IMMEDIATE = 18 , # [doc = "< Address as displacement from (PC+2) used by branches"] M68K_AM_BRANCH_DISPLACEMENT = 19 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] M68K_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] M68K_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] M68K_OP_MEM = 3 , # [doc = "< single precision Floating-Point operand"] M68K_OP_FP_SINGLE = 4 , # [doc = "< double precision Floating-Point operand"] M68K_OP_FP_DOUBLE = 5 , # [doc = "< Register bits move"] M68K_OP_REG_BITS = 6 , # [doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"] M68K_OP_REG_PAIR = 7 , # [doc = "< Branch displacement"] M68K_OP_BR_DISP = 8 , } # [doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_mem { # [doc = "< base register (or M68K_REG_INVALID if irrelevant)"] pub base_reg : m68k_reg , # [doc = "< index register (or M68K_REG_INVALID if irrelevant)"] pub index_reg : m68k_reg , # [doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"] pub in_base_reg : m68k_reg , # [doc = "< indirect displacement"] pub in_disp : u32 , # [doc = "< other displacement"] pub out_disp : u32 , # [doc = "< displacement value"] pub disp : i16 , # [doc = "< scale for index register"] pub scale : u8 , # [doc = "< set to true if the two values below should be used"] pub bitfield : u8 , # [doc = "< used for bf* instructions"] pub width : u8 , # [doc = "< used for bf* instructions"] pub offset : u8 , # [doc = "< 0 = w, 1 = l"] pub index_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_mem"] [:: std :: mem :: size_of :: < m68k_op_mem > () - 28usize] ; ["Alignment of m68k_op_mem"] [:: std :: mem :: align_of :: < m68k_op_mem > () - 4usize] ; ["Offset of field: m68k_op_mem::base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , base_reg) - 0usize] ; ["Offset of field: m68k_op_mem::index_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_reg) - 4usize] ; ["Offset of field: m68k_op_mem::in_base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_base_reg) - 8usize] ; ["Offset of field: m68k_op_mem::in_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_disp) - 12usize] ; ["Offset of field: m68k_op_mem::out_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , out_disp) - 16usize] ; ["Offset of field: m68k_op_mem::disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , disp) - 20usize] ; ["Offset of field: m68k_op_mem::scale"] [:: std :: mem :: offset_of ! (m68k_op_mem , scale) - 22usize] ; ["Offset of field: m68k_op_mem::bitfield"] [:: std :: mem :: offset_of ! (m68k_op_mem , bitfield) - 23usize] ; ["Offset of field: m68k_op_mem::width"] [:: std :: mem :: offset_of ! (m68k_op_mem , width) - 24usize] ; ["Offset of field: m68k_op_mem::offset"] [:: std :: mem :: offset_of ! (m68k_op_mem , offset) - 25usize] ; ["Offset of field: m68k_op_mem::index_size"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_size) - 26usize] ; } ; # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_br_disp_size { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_BR_DISP_SIZE_INVALID = 0 , # [doc = "< signed 8-bit displacement"] M68K_OP_BR_DISP_SIZE_BYTE = 1 , # [doc = "< signed 16-bit displacement"] M68K_OP_BR_DISP_SIZE_WORD = 2 , # [doc = "< signed 32-bit displacement"] M68K_OP_BR_DISP_SIZE_LONG = 4 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_br_disp { # [doc = "< displacement value"] pub disp : i32 , # [doc = "< Size from m68k_op_br_disp_size type above"] pub disp_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_br_disp"] [:: std :: mem :: size_of :: < m68k_op_br_disp > () - 8usize] ; ["Alignment of m68k_op_br_disp"] [:: std :: mem :: align_of :: < m68k_op_br_disp > () - 4usize] ; ["Offset of field: m68k_op_br_disp::disp"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp) - 0usize] ; ["Offset of field: m68k_op_br_disp::disp_size"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp_size) - 4usize] ; } ; # [doc = " Register pair in one operand."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_m68k_op_reg_pair { pub reg_0 : m68k_reg , pub reg_1 : m68k_reg , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op_reg_pair"] [:: std :: mem :: size_of :: < cs_m68k_op_reg_pair > () - 8usize] ; ["Alignment of cs_m68k_op_reg_pair"] [:: std :: mem :: align_of :: < cs_m68k_op_reg_pair > () - 4usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_0"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_0) - 0usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_1"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_1) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k_op { pub __bindgen_anon_1 : cs_m68k_op__bindgen_ty_1 , # [doc = "< data when operand is targeting memory"] pub mem : m68k_op_mem , # [doc = "< data when operand is a branch displacement"] pub br_disp : m68k_op_br_disp , # [doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"] pub register_bits : u32 , pub type_ : m68k_op_type , # [doc = "< M68K addressing mode for this op"] pub address_mode : m68k_address_mode , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m68k_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< double imm"] pub dimm : f64 , # [doc = "< float imm"] pub simm : f32 , # [doc = "< register value for REG operand"] pub reg : m68k_reg , # [doc = "< register pair in one operand"] pub reg_pair : cs_m68k_op_reg_pair , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::dimm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , dimm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::simm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , simm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg_pair"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg_pair) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op"] [:: std :: mem :: size_of :: < cs_m68k_op > () - 56usize] ; ["Alignment of cs_m68k_op"] [:: std :: mem :: align_of :: < cs_m68k_op > () - 8usize] ; ["Offset of field: cs_m68k_op::mem"] [:: std :: mem :: offset_of ! (cs_m68k_op , mem) - 8usize] ; ["Offset of field: cs_m68k_op::br_disp"] [:: std :: mem :: offset_of ! (cs_m68k_op , br_disp) - 36usize] ; ["Offset of field: cs_m68k_op::register_bits"] [:: std :: mem :: offset_of ! (cs_m68k_op , register_bits) - 44usize] ; ["Offset of field: cs_m68k_op::type_"] [:: std :: mem :: offset_of ! (cs_m68k_op , type_) - 48usize] ; ["Offset of field: cs_m68k_op::address_mode"] [:: std :: mem :: offset_of ! (cs_m68k_op , address_mode) - 52usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode) } } # [repr (u32)] # [doc = " Operation size of the CPU instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_cpu_size { # [doc = "< unsized or unspecified"] M68K_CPU_SIZE_NONE = 0 , # [doc = "< 1 byte in size"] M68K_CPU_SIZE_BYTE = 1 , # [doc = "< 2 bytes in size"] M68K_CPU_SIZE_WORD = 2 , # [doc = "< 4 bytes in size"] M68K_CPU_SIZE_LONG = 4 , } # [repr (u32)] # [doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_fpu_size { # [doc = "< unsized like fsave/frestore"] M68K_FPU_SIZE_NONE = 0 , # [doc = "< 4 byte in size (single float)"] M68K_FPU_SIZE_SINGLE = 4 , # [doc = "< 8 byte in size (double)"] M68K_FPU_SIZE_DOUBLE = 8 , # [doc = "< 12 byte in size (extended real format)"] M68K_FPU_SIZE_EXTENDED = 12 , } # [repr (u32)] # [doc = " Type of size that is being used for the current instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0 , M68K_SIZE_TYPE_CPU = 1 , M68K_SIZE_TYPE_FPU = 2 , } # [doc = " Operation size of the current instruction (NOT the actually size of instruction)"] # [repr (C)] # [derive (Copy , Clone)] pub struct m68k_op_size { pub type_ : m68k_size_type , pub __bindgen_anon_1 : m68k_op_size__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union m68k_op_size__bindgen_ty_1 { pub cpu_size : m68k_cpu_size , pub fpu_size : m68k_fpu_size , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: size_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Alignment of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: align_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::cpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , cpu_size) - 0usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::fpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , fpu_size) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size"] [:: std :: mem :: size_of :: < m68k_op_size > () - 8usize] ; ["Alignment of m68k_op_size"] [:: std :: mem :: align_of :: < m68k_op_size > () - 4usize] ; ["Offset of field: m68k_op_size::type_"] [:: std :: mem :: offset_of ! (m68k_op_size , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The M68K instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k { # [doc = "< operands for this instruction."] pub operands : [cs_m68k_op ; 4usize] , # [doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"] pub op_size : m68k_op_size , # [doc = "< number of operands for the instruction"] pub op_count : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k"] [:: std :: mem :: size_of :: < cs_m68k > () - 240usize] ; ["Alignment of cs_m68k"] [:: std :: mem :: align_of :: < cs_m68k > () - 8usize] ; ["Offset of field: cs_m68k::operands"] [:: std :: mem :: offset_of ! (cs_m68k , operands) - 0usize] ; ["Offset of field: cs_m68k::op_size"] [:: std :: mem :: offset_of ! (cs_m68k , op_size) - 224usize] ; ["Offset of field: cs_m68k::op_count"] [:: std :: mem :: offset_of ! (cs_m68k , op_count) - 232usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}" , self . operands , self . op_size , self . op_count) } } # [repr (u32)] # [doc = " M68K instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_insn { M68K_INS_INVALID = 0 , M68K_INS_ABCD = 1 , M68K_INS_ADD = 2 , M68K_INS_ADDA = 3 , M68K_INS_ADDI = 4 , M68K_INS_ADDQ = 5 , M68K_INS_ADDX = 6 , M68K_INS_AND = 7 , M68K_INS_ANDI = 8 , M68K_INS_ASL = 9 , M68K_INS_ASR = 10 , M68K_INS_BHS = 11 , M68K_INS_BLO = 12 , M68K_INS_BHI = 13 , M68K_INS_BLS = 14 , M68K_INS_BCC = 15 , M68K_INS_BCS = 16 , M68K_INS_BNE = 17 , M68K_INS_BEQ = 18 , M68K_INS_BVC = 19 , M68K_INS_BVS = 20 , M68K_INS_BPL = 21 , M68K_INS_BMI = 22 , M68K_INS_BGE = 23 , M68K_INS_BLT = 24 , M68K_INS_BGT = 25 , M68K_INS_BLE = 26 , M68K_INS_BRA = 27 , M68K_INS_BSR = 28 , M68K_INS_BCHG = 29 , M68K_INS_BCLR = 30 , M68K_INS_BSET = 31 , M68K_INS_BTST = 32 , M68K_INS_BFCHG = 33 , M68K_INS_BFCLR = 34 , M68K_INS_BFEXTS = 35 , M68K_INS_BFEXTU = 36 , M68K_INS_BFFFO = 37 , M68K_INS_BFINS = 38 , M68K_INS_BFSET = 39 , M68K_INS_BFTST = 40 , M68K_INS_BKPT = 41 , M68K_INS_CALLM = 42 , M68K_INS_CAS = 43 , M68K_INS_CAS2 = 44 , M68K_INS_CHK = 45 , M68K_INS_CHK2 = 46 , M68K_INS_CLR = 47 , M68K_INS_CMP = 48 , M68K_INS_CMPA = 49 , M68K_INS_CMPI = 50 , M68K_INS_CMPM = 51 , M68K_INS_CMP2 = 52 , M68K_INS_CINVL = 53 , M68K_INS_CINVP = 54 , M68K_INS_CINVA = 55 , M68K_INS_CPUSHL = 56 , M68K_INS_CPUSHP = 57 , M68K_INS_CPUSHA = 58 , M68K_INS_DBT = 59 , M68K_INS_DBF = 60 , M68K_INS_DBHI = 61 , M68K_INS_DBLS = 62 , M68K_INS_DBCC = 63 , M68K_INS_DBCS = 64 , M68K_INS_DBNE = 65 , M68K_INS_DBEQ = 66 , M68K_INS_DBVC = 67 , M68K_INS_DBVS = 68 , M68K_INS_DBPL = 69 , M68K_INS_DBMI = 70 , M68K_INS_DBGE = 71 , M68K_INS_DBLT = 72 , M68K_INS_DBGT = 73 , M68K_INS_DBLE = 74 , M68K_INS_DBRA = 75 , M68K_INS_DIVS = 76 , M68K_INS_DIVSL = 77 , M68K_INS_DIVU = 78 , M68K_INS_DIVUL = 79 , M68K_INS_EOR = 80 , M68K_INS_EORI = 81 , M68K_INS_EXG = 82 , M68K_INS_EXT = 83 , M68K_INS_EXTB = 84 , M68K_INS_FABS = 85 , M68K_INS_FSABS = 86 , M68K_INS_FDABS = 87 , M68K_INS_FACOS = 88 , M68K_INS_FADD = 89 , M68K_INS_FSADD = 90 , M68K_INS_FDADD = 91 , M68K_INS_FASIN = 92 , M68K_INS_FATAN = 93 , M68K_INS_FATANH = 94 , M68K_INS_FBF = 95 , M68K_INS_FBEQ = 96 , M68K_INS_FBOGT = 97 , M68K_INS_FBOGE = 98 , M68K_INS_FBOLT = 99 , M68K_INS_FBOLE = 100 , M68K_INS_FBOGL = 101 , M68K_INS_FBOR = 102 , M68K_INS_FBUN = 103 , M68K_INS_FBUEQ = 104 , M68K_INS_FBUGT = 105 , M68K_INS_FBUGE = 106 , M68K_INS_FBULT = 107 , M68K_INS_FBULE = 108 , M68K_INS_FBNE = 109 , M68K_INS_FBT = 110 , M68K_INS_FBSF = 111 , M68K_INS_FBSEQ = 112 , M68K_INS_FBGT = 113 , M68K_INS_FBGE = 114 , M68K_INS_FBLT = 115 , M68K_INS_FBLE = 116 , M68K_INS_FBGL = 117 , M68K_INS_FBGLE = 118 , M68K_INS_FBNGLE = 119 , M68K_INS_FBNGL = 120 , M68K_INS_FBNLE = 121 , M68K_INS_FBNLT = 122 , M68K_INS_FBNGE = 123 , M68K_INS_FBNGT = 124 , M68K_INS_FBSNE = 125 , M68K_INS_FBST = 126 , M68K_INS_FCMP = 127 , M68K_INS_FCOS = 128 , M68K_INS_FCOSH = 129 , M68K_INS_FDBF = 130 , M68K_INS_FDBEQ = 131 , M68K_INS_FDBOGT = 132 , M68K_INS_FDBOGE = 133 , M68K_INS_FDBOLT = 134 , M68K_INS_FDBOLE = 135 , M68K_INS_FDBOGL = 136 , M68K_INS_FDBOR = 137 , M68K_INS_FDBUN = 138 , M68K_INS_FDBUEQ = 139 , M68K_INS_FDBUGT = 140 , M68K_INS_FDBUGE = 141 , M68K_INS_FDBULT = 142 , M68K_INS_FDBULE = 143 , M68K_INS_FDBNE = 144 , M68K_INS_FDBT = 145 , M68K_INS_FDBSF = 146 , M68K_INS_FDBSEQ = 147 , M68K_INS_FDBGT = 148 , M68K_INS_FDBGE = 149 , M68K_INS_FDBLT = 150 , M68K_INS_FDBLE = 151 , M68K_INS_FDBGL = 152 , M68K_INS_FDBGLE = 153 , M68K_INS_FDBNGLE = 154 , M68K_INS_FDBNGL = 155 , M68K_INS_FDBNLE = 156 , M68K_INS_FDBNLT = 157 , M68K_INS_FDBNGE = 158 , M68K_INS_FDBNGT = 159 , M68K_INS_FDBSNE = 160 , M68K_INS_FDBST = 161 , M68K_INS_FDIV = 162 , M68K_INS_FSDIV = 163 , M68K_INS_FDDIV = 164 , M68K_INS_FETOX = 165 , M68K_INS_FETOXM1 = 166 , M68K_INS_FGETEXP = 167 , M68K_INS_FGETMAN = 168 , M68K_INS_FINT = 169 , M68K_INS_FINTRZ = 170 , M68K_INS_FLOG10 = 171 , M68K_INS_FLOG2 = 172 , M68K_INS_FLOGN = 173 , M68K_INS_FLOGNP1 = 174 , M68K_INS_FMOD = 175 , M68K_INS_FMOVE = 176 , M68K_INS_FSMOVE = 177 , M68K_INS_FDMOVE = 178 , M68K_INS_FMOVECR = 179 , M68K_INS_FMOVEM = 180 , M68K_INS_FMUL = 181 , M68K_INS_FSMUL = 182 , M68K_INS_FDMUL = 183 , M68K_INS_FNEG = 184 , M68K_INS_FSNEG = 185 , M68K_INS_FDNEG = 186 , M68K_INS_FNOP = 187 , M68K_INS_FREM = 188 , M68K_INS_FRESTORE = 189 , M68K_INS_FSAVE = 190 , M68K_INS_FSCALE = 191 , M68K_INS_FSGLDIV = 192 , M68K_INS_FSGLMUL = 193 , M68K_INS_FSIN = 194 , M68K_INS_FSINCOS = 195 , M68K_INS_FSINH = 196 , M68K_INS_FSQRT = 197 , M68K_INS_FSSQRT = 198 , M68K_INS_FDSQRT = 199 , M68K_INS_FSF = 200 , M68K_INS_FSBEQ = 201 , M68K_INS_FSOGT = 202 , M68K_INS_FSOGE = 203 , M68K_INS_FSOLT = 204 , M68K_INS_FSOLE = 205 , M68K_INS_FSOGL = 206 , M68K_INS_FSOR = 207 , M68K_INS_FSUN = 208 , M68K_INS_FSUEQ = 209 , M68K_INS_FSUGT = 210 , M68K_INS_FSUGE = 211 , M68K_INS_FSULT = 212 , M68K_INS_FSULE = 213 , M68K_INS_FSNE = 214 , M68K_INS_FST = 215 , M68K_INS_FSSF = 216 , M68K_INS_FSSEQ = 217 , M68K_INS_FSGT = 218 , M68K_INS_FSGE = 219 , M68K_INS_FSLT = 220 , M68K_INS_FSLE = 221 , M68K_INS_FSGL = 222 , M68K_INS_FSGLE = 223 , M68K_INS_FSNGLE = 224 , M68K_INS_FSNGL = 225 , M68K_INS_FSNLE = 226 , M68K_INS_FSNLT = 227 , M68K_INS_FSNGE = 228 , M68K_INS_FSNGT = 229 , M68K_INS_FSSNE = 230 , M68K_INS_FSST = 231 , M68K_INS_FSUB = 232 , M68K_INS_FSSUB = 233 , M68K_INS_FDSUB = 234 , M68K_INS_FTAN = 235 , M68K_INS_FTANH = 236 , M68K_INS_FTENTOX = 237 , M68K_INS_FTRAPF = 238 , M68K_INS_FTRAPEQ = 239 , M68K_INS_FTRAPOGT = 240 , M68K_INS_FTRAPOGE = 241 , M68K_INS_FTRAPOLT = 242 , M68K_INS_FTRAPOLE = 243 , M68K_INS_FTRAPOGL = 244 , M68K_INS_FTRAPOR = 245 , M68K_INS_FTRAPUN = 246 , M68K_INS_FTRAPUEQ = 247 , M68K_INS_FTRAPUGT = 248 , M68K_INS_FTRAPUGE = 249 , M68K_INS_FTRAPULT = 250 , M68K_INS_FTRAPULE = 251 , M68K_INS_FTRAPNE = 252 , M68K_INS_FTRAPT = 253 , M68K_INS_FTRAPSF = 254 , M68K_INS_FTRAPSEQ = 255 , M68K_INS_FTRAPGT = 256 , M68K_INS_FTRAPGE = 257 , M68K_INS_FTRAPLT = 258 , M68K_INS_FTRAPLE = 259 , M68K_INS_FTRAPGL = 260 , M68K_INS_FTRAPGLE = 261 , M68K_INS_FTRAPNGLE = 262 , M68K_INS_FTRAPNGL = 263 , M68K_INS_FTRAPNLE = 264 , M68K_INS_FTRAPNLT = 265 , M68K_INS_FTRAPNGE = 266 , M68K_INS_FTRAPNGT = 267 , M68K_INS_FTRAPSNE = 268 , M68K_INS_FTRAPST = 269 , M68K_INS_FTST = 270 , M68K_INS_FTWOTOX = 271 , M68K_INS_HALT = 272 , M68K_INS_ILLEGAL = 273 , M68K_INS_JMP = 274 , M68K_INS_JSR = 275 , M68K_INS_LEA = 276 , M68K_INS_LINK = 277 , M68K_INS_LPSTOP = 278 , M68K_INS_LSL = 279 , M68K_INS_LSR = 280 , M68K_INS_MOVE = 281 , M68K_INS_MOVEA = 282 , M68K_INS_MOVEC = 283 , M68K_INS_MOVEM = 284 , M68K_INS_MOVEP = 285 , M68K_INS_MOVEQ = 286 , M68K_INS_MOVES = 287 , M68K_INS_MOVE16 = 288 , M68K_INS_MULS = 289 , M68K_INS_MULU = 290 , M68K_INS_NBCD = 291 , M68K_INS_NEG = 292 , M68K_INS_NEGX = 293 , M68K_INS_NOP = 294 , M68K_INS_NOT = 295 , M68K_INS_OR = 296 , M68K_INS_ORI = 297 , M68K_INS_PACK = 298 , M68K_INS_PEA = 299 , M68K_INS_PFLUSH = 300 , M68K_INS_PFLUSHA = 301 , M68K_INS_PFLUSHAN = 302 , M68K_INS_PFLUSHN = 303 , M68K_INS_PLOADR = 304 , M68K_INS_PLOADW = 305 , M68K_INS_PLPAR = 306 , M68K_INS_PLPAW = 307 , M68K_INS_PMOVE = 308 , M68K_INS_PMOVEFD = 309 , M68K_INS_PTESTR = 310 , M68K_INS_PTESTW = 311 , M68K_INS_PULSE = 312 , M68K_INS_REMS = 313 , M68K_INS_REMU = 314 , M68K_INS_RESET = 315 , M68K_INS_ROL = 316 , M68K_INS_ROR = 317 , M68K_INS_ROXL = 318 , M68K_INS_ROXR = 319 , M68K_INS_RTD = 320 , M68K_INS_RTE = 321 , M68K_INS_RTM = 322 , M68K_INS_RTR = 323 , M68K_INS_RTS = 324 , M68K_INS_SBCD = 325 , M68K_INS_ST = 326 , M68K_INS_SF = 327 , M68K_INS_SHI = 328 , M68K_INS_SLS = 329 , M68K_INS_SCC = 330 , M68K_INS_SHS = 331 , M68K_INS_SCS = 332 , M68K_INS_SLO = 333 , M68K_INS_SNE = 334 , M68K_INS_SEQ = 335 , M68K_INS_SVC = 336 , M68K_INS_SVS = 337 , M68K_INS_SPL = 338 , M68K_INS_SMI = 339 , M68K_INS_SGE = 340 , M68K_INS_SLT = 341 , M68K_INS_SGT = 342 , M68K_INS_SLE = 343 , M68K_INS_STOP = 344 , M68K_INS_SUB = 345 , M68K_INS_SUBA = 346 , M68K_INS_SUBI = 347 , M68K_INS_SUBQ = 348 , M68K_INS_SUBX = 349 , M68K_INS_SWAP = 350 , M68K_INS_TAS = 351 , M68K_INS_TRAP = 352 , M68K_INS_TRAPV = 353 , M68K_INS_TRAPT = 354 , M68K_INS_TRAPF = 355 , M68K_INS_TRAPHI = 356 , M68K_INS_TRAPLS = 357 , M68K_INS_TRAPCC = 358 , M68K_INS_TRAPHS = 359 , M68K_INS_TRAPCS = 360 , M68K_INS_TRAPLO = 361 , M68K_INS_TRAPNE = 362 , M68K_INS_TRAPEQ = 363 , M68K_INS_TRAPVC = 364 , M68K_INS_TRAPVS = 365 , M68K_INS_TRAPPL = 366 , M68K_INS_TRAPMI = 367 , M68K_INS_TRAPGE = 368 , M68K_INS_TRAPLT = 369 , M68K_INS_TRAPGT = 370 , M68K_INS_TRAPLE = 371 , M68K_INS_TST = 372 , M68K_INS_UNLK = 373 , M68K_INS_UNPK = 374 , M68K_INS_ENDING = 375 , } # [repr (u32)] # [doc = " Group of M68K instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_group_type { # [doc = "< CS_GRUP_INVALID"] M68K_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M68K_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] M68K_GRP_RET = 3 , # [doc = "< = CS_GRP_IRET"] M68K_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M68K_GRP_BRANCH_RELATIVE = 7 , M68K_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MIPS_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MIPS_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MIPS_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MIPS_OP_MEM = 3 , } impl mips_reg { pub const MIPS_REG_ZERO : mips_reg = mips_reg :: MIPS_REG_0 ; } impl mips_reg { pub const MIPS_REG_AT : mips_reg = mips_reg :: MIPS_REG_1 ; } impl mips_reg { pub const MIPS_REG_V0 : mips_reg = mips_reg :: MIPS_REG_2 ; } impl mips_reg { pub const MIPS_REG_V1 : mips_reg = mips_reg :: MIPS_REG_3 ; } impl mips_reg { pub const MIPS_REG_A0 : mips_reg = mips_reg :: MIPS_REG_4 ; } impl mips_reg { pub const MIPS_REG_A1 : mips_reg = mips_reg :: MIPS_REG_5 ; } impl mips_reg { pub const MIPS_REG_A2 : mips_reg = mips_reg :: MIPS_REG_6 ; } impl mips_reg { pub const MIPS_REG_A3 : mips_reg = mips_reg :: MIPS_REG_7 ; } impl mips_reg { pub const MIPS_REG_T0 : mips_reg = mips_reg :: MIPS_REG_8 ; } impl mips_reg { pub const MIPS_REG_T1 : mips_reg = mips_reg :: MIPS_REG_9 ; } impl mips_reg { pub const MIPS_REG_T2 : mips_reg = mips_reg :: MIPS_REG_10 ; } impl mips_reg { pub const MIPS_REG_T3 : mips_reg = mips_reg :: MIPS_REG_11 ; } impl mips_reg { pub const MIPS_REG_T4 : mips_reg = mips_reg :: MIPS_REG_12 ; } impl mips_reg { pub const MIPS_REG_T5 : mips_reg = mips_reg :: MIPS_REG_13 ; } impl mips_reg { pub const MIPS_REG_T6 : mips_reg = mips_reg :: MIPS_REG_14 ; } impl mips_reg { pub const MIPS_REG_T7 : mips_reg = mips_reg :: MIPS_REG_15 ; } impl mips_reg { pub const MIPS_REG_S0 : mips_reg = mips_reg :: MIPS_REG_16 ; } impl mips_reg { pub const MIPS_REG_S1 : mips_reg = mips_reg :: MIPS_REG_17 ; } impl mips_reg { pub const MIPS_REG_S2 : mips_reg = mips_reg :: MIPS_REG_18 ; } impl mips_reg { pub const MIPS_REG_S3 : mips_reg = mips_reg :: MIPS_REG_19 ; } impl mips_reg { pub const MIPS_REG_S4 : mips_reg = mips_reg :: MIPS_REG_20 ; } impl mips_reg { pub const MIPS_REG_S5 : mips_reg = mips_reg :: MIPS_REG_21 ; } impl mips_reg { pub const MIPS_REG_S6 : mips_reg = mips_reg :: MIPS_REG_22 ; } impl mips_reg { pub const MIPS_REG_S7 : mips_reg = mips_reg :: MIPS_REG_23 ; } impl mips_reg { pub const MIPS_REG_T8 : mips_reg = mips_reg :: MIPS_REG_24 ; } impl mips_reg { pub const MIPS_REG_T9 : mips_reg = mips_reg :: MIPS_REG_25 ; } impl mips_reg { pub const MIPS_REG_K0 : mips_reg = mips_reg :: MIPS_REG_26 ; } impl mips_reg { pub const MIPS_REG_K1 : mips_reg = mips_reg :: MIPS_REG_27 ; } impl mips_reg { pub const MIPS_REG_GP : mips_reg = mips_reg :: MIPS_REG_28 ; } impl mips_reg { pub const MIPS_REG_SP : mips_reg = mips_reg :: MIPS_REG_29 ; } impl mips_reg { pub const MIPS_REG_FP : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_S8 : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_RA : mips_reg = mips_reg :: MIPS_REG_31 ; } impl mips_reg { pub const MIPS_REG_HI0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_HI1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_HI2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_HI3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } impl mips_reg { pub const MIPS_REG_LO0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_LO1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_LO2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_LO3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } # [repr (u32)] # [doc = " MIPS registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_reg { MIPS_REG_INVALID = 0 , MIPS_REG_PC = 1 , MIPS_REG_0 = 2 , MIPS_REG_1 = 3 , MIPS_REG_2 = 4 , MIPS_REG_3 = 5 , MIPS_REG_4 = 6 , MIPS_REG_5 = 7 , MIPS_REG_6 = 8 , MIPS_REG_7 = 9 , MIPS_REG_8 = 10 , MIPS_REG_9 = 11 , MIPS_REG_10 = 12 , MIPS_REG_11 = 13 , MIPS_REG_12 = 14 , MIPS_REG_13 = 15 , MIPS_REG_14 = 16 , MIPS_REG_15 = 17 , MIPS_REG_16 = 18 , MIPS_REG_17 = 19 , MIPS_REG_18 = 20 , MIPS_REG_19 = 21 , MIPS_REG_20 = 22 , MIPS_REG_21 = 23 , MIPS_REG_22 = 24 , MIPS_REG_23 = 25 , MIPS_REG_24 = 26 , MIPS_REG_25 = 27 , MIPS_REG_26 = 28 , MIPS_REG_27 = 29 , MIPS_REG_28 = 30 , MIPS_REG_29 = 31 , MIPS_REG_30 = 32 , MIPS_REG_31 = 33 , MIPS_REG_DSPCCOND = 34 , MIPS_REG_DSPCARRY = 35 , MIPS_REG_DSPEFI = 36 , MIPS_REG_DSPOUTFLAG = 37 , MIPS_REG_DSPOUTFLAG16_19 = 38 , MIPS_REG_DSPOUTFLAG20 = 39 , MIPS_REG_DSPOUTFLAG21 = 40 , MIPS_REG_DSPOUTFLAG22 = 41 , MIPS_REG_DSPOUTFLAG23 = 42 , MIPS_REG_DSPPOS = 43 , MIPS_REG_DSPSCOUNT = 44 , MIPS_REG_AC0 = 45 , MIPS_REG_AC1 = 46 , MIPS_REG_AC2 = 47 , MIPS_REG_AC3 = 48 , MIPS_REG_CC0 = 49 , MIPS_REG_CC1 = 50 , MIPS_REG_CC2 = 51 , MIPS_REG_CC3 = 52 , MIPS_REG_CC4 = 53 , MIPS_REG_CC5 = 54 , MIPS_REG_CC6 = 55 , MIPS_REG_CC7 = 56 , MIPS_REG_F0 = 57 , MIPS_REG_F1 = 58 , MIPS_REG_F2 = 59 , MIPS_REG_F3 = 60 , MIPS_REG_F4 = 61 , MIPS_REG_F5 = 62 , MIPS_REG_F6 = 63 , MIPS_REG_F7 = 64 , MIPS_REG_F8 = 65 , MIPS_REG_F9 = 66 , MIPS_REG_F10 = 67 , MIPS_REG_F11 = 68 , MIPS_REG_F12 = 69 , MIPS_REG_F13 = 70 , MIPS_REG_F14 = 71 , MIPS_REG_F15 = 72 , MIPS_REG_F16 = 73 , MIPS_REG_F17 = 74 , MIPS_REG_F18 = 75 , MIPS_REG_F19 = 76 , MIPS_REG_F20 = 77 , MIPS_REG_F21 = 78 , MIPS_REG_F22 = 79 , MIPS_REG_F23 = 80 , MIPS_REG_F24 = 81 , MIPS_REG_F25 = 82 , MIPS_REG_F26 = 83 , MIPS_REG_F27 = 84 , MIPS_REG_F28 = 85 , MIPS_REG_F29 = 86 , MIPS_REG_F30 = 87 , MIPS_REG_F31 = 88 , MIPS_REG_FCC0 = 89 , MIPS_REG_FCC1 = 90 , MIPS_REG_FCC2 = 91 , MIPS_REG_FCC3 = 92 , MIPS_REG_FCC4 = 93 , MIPS_REG_FCC5 = 94 , MIPS_REG_FCC6 = 95 , MIPS_REG_FCC7 = 96 , MIPS_REG_W0 = 97 , MIPS_REG_W1 = 98 , MIPS_REG_W2 = 99 , MIPS_REG_W3 = 100 , MIPS_REG_W4 = 101 , MIPS_REG_W5 = 102 , MIPS_REG_W6 = 103 , MIPS_REG_W7 = 104 , MIPS_REG_W8 = 105 , MIPS_REG_W9 = 106 , MIPS_REG_W10 = 107 , MIPS_REG_W11 = 108 , MIPS_REG_W12 = 109 , MIPS_REG_W13 = 110 , MIPS_REG_W14 = 111 , MIPS_REG_W15 = 112 , MIPS_REG_W16 = 113 , MIPS_REG_W17 = 114 , MIPS_REG_W18 = 115 , MIPS_REG_W19 = 116 , MIPS_REG_W20 = 117 , MIPS_REG_W21 = 118 , MIPS_REG_W22 = 119 , MIPS_REG_W23 = 120 , MIPS_REG_W24 = 121 , MIPS_REG_W25 = 122 , MIPS_REG_W26 = 123 , MIPS_REG_W27 = 124 , MIPS_REG_W28 = 125 , MIPS_REG_W29 = 126 , MIPS_REG_W30 = 127 , MIPS_REG_W31 = 128 , MIPS_REG_HI = 129 , MIPS_REG_LO = 130 , MIPS_REG_P0 = 131 , MIPS_REG_P1 = 132 , MIPS_REG_P2 = 133 , MIPS_REG_MPL0 = 134 , MIPS_REG_MPL1 = 135 , MIPS_REG_MPL2 = 136 , MIPS_REG_ENDING = 137 , } # [doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct mips_op_mem { # [doc = "< base register"] pub base : mips_reg , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of mips_op_mem"] [:: std :: mem :: size_of :: < mips_op_mem > () - 16usize] ; ["Alignment of mips_op_mem"] [:: std :: mem :: align_of :: < mips_op_mem > () - 8usize] ; ["Offset of field: mips_op_mem::base"] [:: std :: mem :: offset_of ! (mips_op_mem , base) - 0usize] ; ["Offset of field: mips_op_mem::disp"] [:: std :: mem :: offset_of ! (mips_op_mem , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips_op { # [doc = "< operand type"] pub type_ : mips_op_type , pub __bindgen_anon_1 : cs_mips_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mips_op__bindgen_ty_1 { # [doc = "< register id for REG operand"] pub reg : mips_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : mips_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mips_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mips_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op"] [:: std :: mem :: size_of :: < cs_mips_op > () - 24usize] ; ["Alignment of cs_mips_op"] [:: std :: mem :: align_of :: < cs_mips_op > () - 8usize] ; ["Offset of field: cs_mips_op::type_"] [:: std :: mem :: offset_of ! (cs_mips_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mips_op ; 10usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips"] [:: std :: mem :: size_of :: < cs_mips > () - 248usize] ; ["Alignment of cs_mips"] [:: std :: mem :: align_of :: < cs_mips > () - 8usize] ; ["Offset of field: cs_mips::op_count"] [:: std :: mem :: offset_of ! (cs_mips , op_count) - 0usize] ; ["Offset of field: cs_mips::operands"] [:: std :: mem :: offset_of ! (cs_mips , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mips { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " MIPS instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn { MIPS_INS_INVALID = 0 , MIPS_INS_ABSQ_S = 1 , MIPS_INS_ADD = 2 , MIPS_INS_ADDIUPC = 3 , MIPS_INS_ADDIUR1SP = 4 , MIPS_INS_ADDIUR2 = 5 , MIPS_INS_ADDIUS5 = 6 , MIPS_INS_ADDIUSP = 7 , MIPS_INS_ADDQH = 8 , MIPS_INS_ADDQH_R = 9 , MIPS_INS_ADDQ = 10 , MIPS_INS_ADDQ_S = 11 , MIPS_INS_ADDSC = 12 , MIPS_INS_ADDS_A = 13 , MIPS_INS_ADDS_S = 14 , MIPS_INS_ADDS_U = 15 , MIPS_INS_ADDU16 = 16 , MIPS_INS_ADDUH = 17 , MIPS_INS_ADDUH_R = 18 , MIPS_INS_ADDU = 19 , MIPS_INS_ADDU_S = 20 , MIPS_INS_ADDVI = 21 , MIPS_INS_ADDV = 22 , MIPS_INS_ADDWC = 23 , MIPS_INS_ADD_A = 24 , MIPS_INS_ADDI = 25 , MIPS_INS_ADDIU = 26 , MIPS_INS_ALIGN = 27 , MIPS_INS_ALUIPC = 28 , MIPS_INS_AND = 29 , MIPS_INS_AND16 = 30 , MIPS_INS_ANDI16 = 31 , MIPS_INS_ANDI = 32 , MIPS_INS_APPEND = 33 , MIPS_INS_ASUB_S = 34 , MIPS_INS_ASUB_U = 35 , MIPS_INS_AUI = 36 , MIPS_INS_AUIPC = 37 , MIPS_INS_AVER_S = 38 , MIPS_INS_AVER_U = 39 , MIPS_INS_AVE_S = 40 , MIPS_INS_AVE_U = 41 , MIPS_INS_B16 = 42 , MIPS_INS_BADDU = 43 , MIPS_INS_BAL = 44 , MIPS_INS_BALC = 45 , MIPS_INS_BALIGN = 46 , MIPS_INS_BBIT0 = 47 , MIPS_INS_BBIT032 = 48 , MIPS_INS_BBIT1 = 49 , MIPS_INS_BBIT132 = 50 , MIPS_INS_BC = 51 , MIPS_INS_BC0F = 52 , MIPS_INS_BC0FL = 53 , MIPS_INS_BC0T = 54 , MIPS_INS_BC0TL = 55 , MIPS_INS_BC1EQZ = 56 , MIPS_INS_BC1F = 57 , MIPS_INS_BC1FL = 58 , MIPS_INS_BC1NEZ = 59 , MIPS_INS_BC1T = 60 , MIPS_INS_BC1TL = 61 , MIPS_INS_BC2EQZ = 62 , MIPS_INS_BC2F = 63 , MIPS_INS_BC2FL = 64 , MIPS_INS_BC2NEZ = 65 , MIPS_INS_BC2T = 66 , MIPS_INS_BC2TL = 67 , MIPS_INS_BC3F = 68 , MIPS_INS_BC3FL = 69 , MIPS_INS_BC3T = 70 , MIPS_INS_BC3TL = 71 , MIPS_INS_BCLRI = 72 , MIPS_INS_BCLR = 73 , MIPS_INS_BEQ = 74 , MIPS_INS_BEQC = 75 , MIPS_INS_BEQL = 76 , MIPS_INS_BEQZ16 = 77 , MIPS_INS_BEQZALC = 78 , MIPS_INS_BEQZC = 79 , MIPS_INS_BGEC = 80 , MIPS_INS_BGEUC = 81 , MIPS_INS_BGEZ = 82 , MIPS_INS_BGEZAL = 83 , MIPS_INS_BGEZALC = 84 , MIPS_INS_BGEZALL = 85 , MIPS_INS_BGEZALS = 86 , MIPS_INS_BGEZC = 87 , MIPS_INS_BGEZL = 88 , MIPS_INS_BGTZ = 89 , MIPS_INS_BGTZALC = 90 , MIPS_INS_BGTZC = 91 , MIPS_INS_BGTZL = 92 , MIPS_INS_BINSLI = 93 , MIPS_INS_BINSL = 94 , MIPS_INS_BINSRI = 95 , MIPS_INS_BINSR = 96 , MIPS_INS_BITREV = 97 , MIPS_INS_BITSWAP = 98 , MIPS_INS_BLEZ = 99 , MIPS_INS_BLEZALC = 100 , MIPS_INS_BLEZC = 101 , MIPS_INS_BLEZL = 102 , MIPS_INS_BLTC = 103 , MIPS_INS_BLTUC = 104 , MIPS_INS_BLTZ = 105 , MIPS_INS_BLTZAL = 106 , MIPS_INS_BLTZALC = 107 , MIPS_INS_BLTZALL = 108 , MIPS_INS_BLTZALS = 109 , MIPS_INS_BLTZC = 110 , MIPS_INS_BLTZL = 111 , MIPS_INS_BMNZI = 112 , MIPS_INS_BMNZ = 113 , MIPS_INS_BMZI = 114 , MIPS_INS_BMZ = 115 , MIPS_INS_BNE = 116 , MIPS_INS_BNEC = 117 , MIPS_INS_BNEGI = 118 , MIPS_INS_BNEG = 119 , MIPS_INS_BNEL = 120 , MIPS_INS_BNEZ16 = 121 , MIPS_INS_BNEZALC = 122 , MIPS_INS_BNEZC = 123 , MIPS_INS_BNVC = 124 , MIPS_INS_BNZ = 125 , MIPS_INS_BOVC = 126 , MIPS_INS_BPOSGE32 = 127 , MIPS_INS_BREAK = 128 , MIPS_INS_BREAK16 = 129 , MIPS_INS_BSELI = 130 , MIPS_INS_BSEL = 131 , MIPS_INS_BSETI = 132 , MIPS_INS_BSET = 133 , MIPS_INS_BZ = 134 , MIPS_INS_BEQZ = 135 , MIPS_INS_B = 136 , MIPS_INS_BNEZ = 137 , MIPS_INS_BTEQZ = 138 , MIPS_INS_BTNEZ = 139 , MIPS_INS_CACHE = 140 , MIPS_INS_CEIL = 141 , MIPS_INS_CEQI = 142 , MIPS_INS_CEQ = 143 , MIPS_INS_CFC1 = 144 , MIPS_INS_CFCMSA = 145 , MIPS_INS_CINS = 146 , MIPS_INS_CINS32 = 147 , MIPS_INS_CLASS = 148 , MIPS_INS_CLEI_S = 149 , MIPS_INS_CLEI_U = 150 , MIPS_INS_CLE_S = 151 , MIPS_INS_CLE_U = 152 , MIPS_INS_CLO = 153 , MIPS_INS_CLTI_S = 154 , MIPS_INS_CLTI_U = 155 , MIPS_INS_CLT_S = 156 , MIPS_INS_CLT_U = 157 , MIPS_INS_CLZ = 158 , MIPS_INS_CMPGDU = 159 , MIPS_INS_CMPGU = 160 , MIPS_INS_CMPU = 161 , MIPS_INS_CMP = 162 , MIPS_INS_COPY_S = 163 , MIPS_INS_COPY_U = 164 , MIPS_INS_CTC1 = 165 , MIPS_INS_CTCMSA = 166 , MIPS_INS_CVT = 167 , MIPS_INS_C = 168 , MIPS_INS_CMPI = 169 , MIPS_INS_DADD = 170 , MIPS_INS_DADDI = 171 , MIPS_INS_DADDIU = 172 , MIPS_INS_DADDU = 173 , MIPS_INS_DAHI = 174 , MIPS_INS_DALIGN = 175 , MIPS_INS_DATI = 176 , MIPS_INS_DAUI = 177 , MIPS_INS_DBITSWAP = 178 , MIPS_INS_DCLO = 179 , MIPS_INS_DCLZ = 180 , MIPS_INS_DDIV = 181 , MIPS_INS_DDIVU = 182 , MIPS_INS_DERET = 183 , MIPS_INS_DEXT = 184 , MIPS_INS_DEXTM = 185 , MIPS_INS_DEXTU = 186 , MIPS_INS_DI = 187 , MIPS_INS_DINS = 188 , MIPS_INS_DINSM = 189 , MIPS_INS_DINSU = 190 , MIPS_INS_DIV = 191 , MIPS_INS_DIVU = 192 , MIPS_INS_DIV_S = 193 , MIPS_INS_DIV_U = 194 , MIPS_INS_DLSA = 195 , MIPS_INS_DMFC0 = 196 , MIPS_INS_DMFC1 = 197 , MIPS_INS_DMFC2 = 198 , MIPS_INS_DMOD = 199 , MIPS_INS_DMODU = 200 , MIPS_INS_DMTC0 = 201 , MIPS_INS_DMTC1 = 202 , MIPS_INS_DMTC2 = 203 , MIPS_INS_DMUH = 204 , MIPS_INS_DMUHU = 205 , MIPS_INS_DMUL = 206 , MIPS_INS_DMULT = 207 , MIPS_INS_DMULTU = 208 , MIPS_INS_DMULU = 209 , MIPS_INS_DOTP_S = 210 , MIPS_INS_DOTP_U = 211 , MIPS_INS_DPADD_S = 212 , MIPS_INS_DPADD_U = 213 , MIPS_INS_DPAQX_SA = 214 , MIPS_INS_DPAQX_S = 215 , MIPS_INS_DPAQ_SA = 216 , MIPS_INS_DPAQ_S = 217 , MIPS_INS_DPAU = 218 , MIPS_INS_DPAX = 219 , MIPS_INS_DPA = 220 , MIPS_INS_DPOP = 221 , MIPS_INS_DPSQX_SA = 222 , MIPS_INS_DPSQX_S = 223 , MIPS_INS_DPSQ_SA = 224 , MIPS_INS_DPSQ_S = 225 , MIPS_INS_DPSUB_S = 226 , MIPS_INS_DPSUB_U = 227 , MIPS_INS_DPSU = 228 , MIPS_INS_DPSX = 229 , MIPS_INS_DPS = 230 , MIPS_INS_DROTR = 231 , MIPS_INS_DROTR32 = 232 , MIPS_INS_DROTRV = 233 , MIPS_INS_DSBH = 234 , MIPS_INS_DSHD = 235 , MIPS_INS_DSLL = 236 , MIPS_INS_DSLL32 = 237 , MIPS_INS_DSLLV = 238 , MIPS_INS_DSRA = 239 , MIPS_INS_DSRA32 = 240 , MIPS_INS_DSRAV = 241 , MIPS_INS_DSRL = 242 , MIPS_INS_DSRL32 = 243 , MIPS_INS_DSRLV = 244 , MIPS_INS_DSUB = 245 , MIPS_INS_DSUBU = 246 , MIPS_INS_EHB = 247 , MIPS_INS_EI = 248 , MIPS_INS_ERET = 249 , MIPS_INS_EXT = 250 , MIPS_INS_EXTP = 251 , MIPS_INS_EXTPDP = 252 , MIPS_INS_EXTPDPV = 253 , MIPS_INS_EXTPV = 254 , MIPS_INS_EXTRV_RS = 255 , MIPS_INS_EXTRV_R = 256 , MIPS_INS_EXTRV_S = 257 , MIPS_INS_EXTRV = 258 , MIPS_INS_EXTR_RS = 259 , MIPS_INS_EXTR_R = 260 , MIPS_INS_EXTR_S = 261 , MIPS_INS_EXTR = 262 , MIPS_INS_EXTS = 263 , MIPS_INS_EXTS32 = 264 , MIPS_INS_ABS = 265 , MIPS_INS_FADD = 266 , MIPS_INS_FCAF = 267 , MIPS_INS_FCEQ = 268 , MIPS_INS_FCLASS = 269 , MIPS_INS_FCLE = 270 , MIPS_INS_FCLT = 271 , MIPS_INS_FCNE = 272 , MIPS_INS_FCOR = 273 , MIPS_INS_FCUEQ = 274 , MIPS_INS_FCULE = 275 , MIPS_INS_FCULT = 276 , MIPS_INS_FCUNE = 277 , MIPS_INS_FCUN = 278 , MIPS_INS_FDIV = 279 , MIPS_INS_FEXDO = 280 , MIPS_INS_FEXP2 = 281 , MIPS_INS_FEXUPL = 282 , MIPS_INS_FEXUPR = 283 , MIPS_INS_FFINT_S = 284 , MIPS_INS_FFINT_U = 285 , MIPS_INS_FFQL = 286 , MIPS_INS_FFQR = 287 , MIPS_INS_FILL = 288 , MIPS_INS_FLOG2 = 289 , MIPS_INS_FLOOR = 290 , MIPS_INS_FMADD = 291 , MIPS_INS_FMAX_A = 292 , MIPS_INS_FMAX = 293 , MIPS_INS_FMIN_A = 294 , MIPS_INS_FMIN = 295 , MIPS_INS_MOV = 296 , MIPS_INS_FMSUB = 297 , MIPS_INS_FMUL = 298 , MIPS_INS_MUL = 299 , MIPS_INS_NEG = 300 , MIPS_INS_FRCP = 301 , MIPS_INS_FRINT = 302 , MIPS_INS_FRSQRT = 303 , MIPS_INS_FSAF = 304 , MIPS_INS_FSEQ = 305 , MIPS_INS_FSLE = 306 , MIPS_INS_FSLT = 307 , MIPS_INS_FSNE = 308 , MIPS_INS_FSOR = 309 , MIPS_INS_FSQRT = 310 , MIPS_INS_SQRT = 311 , MIPS_INS_FSUB = 312 , MIPS_INS_SUB = 313 , MIPS_INS_FSUEQ = 314 , MIPS_INS_FSULE = 315 , MIPS_INS_FSULT = 316 , MIPS_INS_FSUNE = 317 , MIPS_INS_FSUN = 318 , MIPS_INS_FTINT_S = 319 , MIPS_INS_FTINT_U = 320 , MIPS_INS_FTQ = 321 , MIPS_INS_FTRUNC_S = 322 , MIPS_INS_FTRUNC_U = 323 , MIPS_INS_HADD_S = 324 , MIPS_INS_HADD_U = 325 , MIPS_INS_HSUB_S = 326 , MIPS_INS_HSUB_U = 327 , MIPS_INS_ILVEV = 328 , MIPS_INS_ILVL = 329 , MIPS_INS_ILVOD = 330 , MIPS_INS_ILVR = 331 , MIPS_INS_INS = 332 , MIPS_INS_INSERT = 333 , MIPS_INS_INSV = 334 , MIPS_INS_INSVE = 335 , MIPS_INS_J = 336 , MIPS_INS_JAL = 337 , MIPS_INS_JALR = 338 , MIPS_INS_JALRS16 = 339 , MIPS_INS_JALRS = 340 , MIPS_INS_JALS = 341 , MIPS_INS_JALX = 342 , MIPS_INS_JIALC = 343 , MIPS_INS_JIC = 344 , MIPS_INS_JR = 345 , MIPS_INS_JR16 = 346 , MIPS_INS_JRADDIUSP = 347 , MIPS_INS_JRC = 348 , MIPS_INS_JALRC = 349 , MIPS_INS_LB = 350 , MIPS_INS_LBU16 = 351 , MIPS_INS_LBUX = 352 , MIPS_INS_LBU = 353 , MIPS_INS_LD = 354 , MIPS_INS_LDC1 = 355 , MIPS_INS_LDC2 = 356 , MIPS_INS_LDC3 = 357 , MIPS_INS_LDI = 358 , MIPS_INS_LDL = 359 , MIPS_INS_LDPC = 360 , MIPS_INS_LDR = 361 , MIPS_INS_LDXC1 = 362 , MIPS_INS_LH = 363 , MIPS_INS_LHU16 = 364 , MIPS_INS_LHX = 365 , MIPS_INS_LHU = 366 , MIPS_INS_LI16 = 367 , MIPS_INS_LL = 368 , MIPS_INS_LLD = 369 , MIPS_INS_LSA = 370 , MIPS_INS_LUXC1 = 371 , MIPS_INS_LUI = 372 , MIPS_INS_LW = 373 , MIPS_INS_LW16 = 374 , MIPS_INS_LWC1 = 375 , MIPS_INS_LWC2 = 376 , MIPS_INS_LWC3 = 377 , MIPS_INS_LWL = 378 , MIPS_INS_LWM16 = 379 , MIPS_INS_LWM32 = 380 , MIPS_INS_LWPC = 381 , MIPS_INS_LWP = 382 , MIPS_INS_LWR = 383 , MIPS_INS_LWUPC = 384 , MIPS_INS_LWU = 385 , MIPS_INS_LWX = 386 , MIPS_INS_LWXC1 = 387 , MIPS_INS_LWXS = 388 , MIPS_INS_LI = 389 , MIPS_INS_MADD = 390 , MIPS_INS_MADDF = 391 , MIPS_INS_MADDR_Q = 392 , MIPS_INS_MADDU = 393 , MIPS_INS_MADDV = 394 , MIPS_INS_MADD_Q = 395 , MIPS_INS_MAQ_SA = 396 , MIPS_INS_MAQ_S = 397 , MIPS_INS_MAXA = 398 , MIPS_INS_MAXI_S = 399 , MIPS_INS_MAXI_U = 400 , MIPS_INS_MAX_A = 401 , MIPS_INS_MAX = 402 , MIPS_INS_MAX_S = 403 , MIPS_INS_MAX_U = 404 , MIPS_INS_MFC0 = 405 , MIPS_INS_MFC1 = 406 , MIPS_INS_MFC2 = 407 , MIPS_INS_MFHC1 = 408 , MIPS_INS_MFHI = 409 , MIPS_INS_MFLO = 410 , MIPS_INS_MINA = 411 , MIPS_INS_MINI_S = 412 , MIPS_INS_MINI_U = 413 , MIPS_INS_MIN_A = 414 , MIPS_INS_MIN = 415 , MIPS_INS_MIN_S = 416 , MIPS_INS_MIN_U = 417 , MIPS_INS_MOD = 418 , MIPS_INS_MODSUB = 419 , MIPS_INS_MODU = 420 , MIPS_INS_MOD_S = 421 , MIPS_INS_MOD_U = 422 , MIPS_INS_MOVE = 423 , MIPS_INS_MOVEP = 424 , MIPS_INS_MOVF = 425 , MIPS_INS_MOVN = 426 , MIPS_INS_MOVT = 427 , MIPS_INS_MOVZ = 428 , MIPS_INS_MSUB = 429 , MIPS_INS_MSUBF = 430 , MIPS_INS_MSUBR_Q = 431 , MIPS_INS_MSUBU = 432 , MIPS_INS_MSUBV = 433 , MIPS_INS_MSUB_Q = 434 , MIPS_INS_MTC0 = 435 , MIPS_INS_MTC1 = 436 , MIPS_INS_MTC2 = 437 , MIPS_INS_MTHC1 = 438 , MIPS_INS_MTHI = 439 , MIPS_INS_MTHLIP = 440 , MIPS_INS_MTLO = 441 , MIPS_INS_MTM0 = 442 , MIPS_INS_MTM1 = 443 , MIPS_INS_MTM2 = 444 , MIPS_INS_MTP0 = 445 , MIPS_INS_MTP1 = 446 , MIPS_INS_MTP2 = 447 , MIPS_INS_MUH = 448 , MIPS_INS_MUHU = 449 , MIPS_INS_MULEQ_S = 450 , MIPS_INS_MULEU_S = 451 , MIPS_INS_MULQ_RS = 452 , MIPS_INS_MULQ_S = 453 , MIPS_INS_MULR_Q = 454 , MIPS_INS_MULSAQ_S = 455 , MIPS_INS_MULSA = 456 , MIPS_INS_MULT = 457 , MIPS_INS_MULTU = 458 , MIPS_INS_MULU = 459 , MIPS_INS_MULV = 460 , MIPS_INS_MUL_Q = 461 , MIPS_INS_MUL_S = 462 , MIPS_INS_NLOC = 463 , MIPS_INS_NLZC = 464 , MIPS_INS_NMADD = 465 , MIPS_INS_NMSUB = 466 , MIPS_INS_NOR = 467 , MIPS_INS_NORI = 468 , MIPS_INS_NOT16 = 469 , MIPS_INS_NOT = 470 , MIPS_INS_OR = 471 , MIPS_INS_OR16 = 472 , MIPS_INS_ORI = 473 , MIPS_INS_PACKRL = 474 , MIPS_INS_PAUSE = 475 , MIPS_INS_PCKEV = 476 , MIPS_INS_PCKOD = 477 , MIPS_INS_PCNT = 478 , MIPS_INS_PICK = 479 , MIPS_INS_POP = 480 , MIPS_INS_PRECEQU = 481 , MIPS_INS_PRECEQ = 482 , MIPS_INS_PRECEU = 483 , MIPS_INS_PRECRQU_S = 484 , MIPS_INS_PRECRQ = 485 , MIPS_INS_PRECRQ_RS = 486 , MIPS_INS_PRECR = 487 , MIPS_INS_PRECR_SRA = 488 , MIPS_INS_PRECR_SRA_R = 489 , MIPS_INS_PREF = 490 , MIPS_INS_PREPEND = 491 , MIPS_INS_RADDU = 492 , MIPS_INS_RDDSP = 493 , MIPS_INS_RDHWR = 494 , MIPS_INS_REPLV = 495 , MIPS_INS_REPL = 496 , MIPS_INS_RINT = 497 , MIPS_INS_ROTR = 498 , MIPS_INS_ROTRV = 499 , MIPS_INS_ROUND = 500 , MIPS_INS_SAT_S = 501 , MIPS_INS_SAT_U = 502 , MIPS_INS_SB = 503 , MIPS_INS_SB16 = 504 , MIPS_INS_SC = 505 , MIPS_INS_SCD = 506 , MIPS_INS_SD = 507 , MIPS_INS_SDBBP = 508 , MIPS_INS_SDBBP16 = 509 , MIPS_INS_SDC1 = 510 , MIPS_INS_SDC2 = 511 , MIPS_INS_SDC3 = 512 , MIPS_INS_SDL = 513 , MIPS_INS_SDR = 514 , MIPS_INS_SDXC1 = 515 , MIPS_INS_SEB = 516 , MIPS_INS_SEH = 517 , MIPS_INS_SELEQZ = 518 , MIPS_INS_SELNEZ = 519 , MIPS_INS_SEL = 520 , MIPS_INS_SEQ = 521 , MIPS_INS_SEQI = 522 , MIPS_INS_SH = 523 , MIPS_INS_SH16 = 524 , MIPS_INS_SHF = 525 , MIPS_INS_SHILO = 526 , MIPS_INS_SHILOV = 527 , MIPS_INS_SHLLV = 528 , MIPS_INS_SHLLV_S = 529 , MIPS_INS_SHLL = 530 , MIPS_INS_SHLL_S = 531 , MIPS_INS_SHRAV = 532 , MIPS_INS_SHRAV_R = 533 , MIPS_INS_SHRA = 534 , MIPS_INS_SHRA_R = 535 , MIPS_INS_SHRLV = 536 , MIPS_INS_SHRL = 537 , MIPS_INS_SLDI = 538 , MIPS_INS_SLD = 539 , MIPS_INS_SLL = 540 , MIPS_INS_SLL16 = 541 , MIPS_INS_SLLI = 542 , MIPS_INS_SLLV = 543 , MIPS_INS_SLT = 544 , MIPS_INS_SLTI = 545 , MIPS_INS_SLTIU = 546 , MIPS_INS_SLTU = 547 , MIPS_INS_SNE = 548 , MIPS_INS_SNEI = 549 , MIPS_INS_SPLATI = 550 , MIPS_INS_SPLAT = 551 , MIPS_INS_SRA = 552 , MIPS_INS_SRAI = 553 , MIPS_INS_SRARI = 554 , MIPS_INS_SRAR = 555 , MIPS_INS_SRAV = 556 , MIPS_INS_SRL = 557 , MIPS_INS_SRL16 = 558 , MIPS_INS_SRLI = 559 , MIPS_INS_SRLRI = 560 , MIPS_INS_SRLR = 561 , MIPS_INS_SRLV = 562 , MIPS_INS_SSNOP = 563 , MIPS_INS_ST = 564 , MIPS_INS_SUBQH = 565 , MIPS_INS_SUBQH_R = 566 , MIPS_INS_SUBQ = 567 , MIPS_INS_SUBQ_S = 568 , MIPS_INS_SUBSUS_U = 569 , MIPS_INS_SUBSUU_S = 570 , MIPS_INS_SUBS_S = 571 , MIPS_INS_SUBS_U = 572 , MIPS_INS_SUBU16 = 573 , MIPS_INS_SUBUH = 574 , MIPS_INS_SUBUH_R = 575 , MIPS_INS_SUBU = 576 , MIPS_INS_SUBU_S = 577 , MIPS_INS_SUBVI = 578 , MIPS_INS_SUBV = 579 , MIPS_INS_SUXC1 = 580 , MIPS_INS_SW = 581 , MIPS_INS_SW16 = 582 , MIPS_INS_SWC1 = 583 , MIPS_INS_SWC2 = 584 , MIPS_INS_SWC3 = 585 , MIPS_INS_SWL = 586 , MIPS_INS_SWM16 = 587 , MIPS_INS_SWM32 = 588 , MIPS_INS_SWP = 589 , MIPS_INS_SWR = 590 , MIPS_INS_SWXC1 = 591 , MIPS_INS_SYNC = 592 , MIPS_INS_SYNCI = 593 , MIPS_INS_SYSCALL = 594 , MIPS_INS_TEQ = 595 , MIPS_INS_TEQI = 596 , MIPS_INS_TGE = 597 , MIPS_INS_TGEI = 598 , MIPS_INS_TGEIU = 599 , MIPS_INS_TGEU = 600 , MIPS_INS_TLBP = 601 , MIPS_INS_TLBR = 602 , MIPS_INS_TLBWI = 603 , MIPS_INS_TLBWR = 604 , MIPS_INS_TLT = 605 , MIPS_INS_TLTI = 606 , MIPS_INS_TLTIU = 607 , MIPS_INS_TLTU = 608 , MIPS_INS_TNE = 609 , MIPS_INS_TNEI = 610 , MIPS_INS_TRUNC = 611 , MIPS_INS_V3MULU = 612 , MIPS_INS_VMM0 = 613 , MIPS_INS_VMULU = 614 , MIPS_INS_VSHF = 615 , MIPS_INS_WAIT = 616 , MIPS_INS_WRDSP = 617 , MIPS_INS_WSBH = 618 , MIPS_INS_XOR = 619 , MIPS_INS_XOR16 = 620 , MIPS_INS_XORI = 621 , MIPS_INS_NOP = 622 , MIPS_INS_NEGU = 623 , MIPS_INS_JALR_HB = 624 , MIPS_INS_JR_HB = 625 , MIPS_INS_ENDING = 626 , } # [repr (u32)] # [doc = " Group of MIPS instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn_group { # [doc = "< = CS_GRP_INVALID"] MIPS_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MIPS_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] MIPS_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MIPS_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MIPS_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MIPS_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] MIPS_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MIPS_GRP_BRANCH_RELATIVE = 7 , MIPS_GRP_BITCOUNT = 128 , MIPS_GRP_DSP = 129 , MIPS_GRP_DSPR2 = 130 , MIPS_GRP_FPIDX = 131 , MIPS_GRP_MSA = 132 , MIPS_GRP_MIPS32R2 = 133 , MIPS_GRP_MIPS64 = 134 , MIPS_GRP_MIPS64R2 = 135 , MIPS_GRP_SEINREG = 136 , MIPS_GRP_STDENC = 137 , MIPS_GRP_SWAP = 138 , MIPS_GRP_MICROMIPS = 139 , MIPS_GRP_MIPS16MODE = 140 , MIPS_GRP_FP64BIT = 141 , MIPS_GRP_NONANSFPMATH = 142 , MIPS_GRP_NOTFP64BIT = 143 , MIPS_GRP_NOTINMICROMIPS = 144 , MIPS_GRP_NOTNACL = 145 , MIPS_GRP_NOTMIPS32R6 = 146 , MIPS_GRP_NOTMIPS64R6 = 147 , MIPS_GRP_CNMIPS = 148 , MIPS_GRP_MIPS32 = 149 , MIPS_GRP_MIPS32R6 = 150 , MIPS_GRP_MIPS64R6 = 151 , MIPS_GRP_MIPS2 = 152 , MIPS_GRP_MIPS3 = 153 , MIPS_GRP_MIPS3_32 = 154 , MIPS_GRP_MIPS3_32R2 = 155 , MIPS_GRP_MIPS4_32 = 156 , MIPS_GRP_MIPS4_32R2 = 157 , MIPS_GRP_MIPS5_32R2 = 158 , MIPS_GRP_GP32BIT = 159 , MIPS_GRP_GP64BIT = 160 , MIPS_GRP_ENDING = 161 , } # [repr (u32)] # [doc = " PPC branch codes for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bc { PPC_BC_INVALID = 0 , PPC_BC_LT = 12 , PPC_BC_LE = 36 , PPC_BC_EQ = 76 , PPC_BC_GE = 4 , PPC_BC_GT = 44 , PPC_BC_NE = 68 , PPC_BC_UN = 108 , PPC_BC_NU = 100 , # [doc = "< summary overflow"] PPC_BC_SO = 140 , # [doc = "< not summary overflow"] PPC_BC_NS = 132 , } # [repr (u32)] # [doc = " PPC branch hint for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bh { # [doc = "< no hint"] PPC_BH_INVALID = 0 , # [doc = "< PLUS hint"] PPC_BH_PLUS = 1 , # [doc = "< MINUS hint"] PPC_BH_MINUS = 2 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] PPC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] PPC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] PPC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] PPC_OP_MEM = 3 , # [doc = "< Condition Register field"] PPC_OP_CRX = 64 , } # [repr (u32)] # [doc = " PPC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_reg { PPC_REG_INVALID = 0 , PPC_REG_CARRY = 2 , PPC_REG_CTR = 3 , PPC_REG_LR = 5 , PPC_REG_RM = 6 , PPC_REG_VRSAVE = 8 , PPC_REG_XER = 9 , PPC_REG_ZERO = 10 , PPC_REG_CR0 = 12 , PPC_REG_CR1 = 13 , PPC_REG_CR2 = 14 , PPC_REG_CR3 = 15 , PPC_REG_CR4 = 16 , PPC_REG_CR5 = 17 , PPC_REG_CR6 = 18 , PPC_REG_CR7 = 19 , PPC_REG_CTR8 = 20 , PPC_REG_F0 = 21 , PPC_REG_F1 = 22 , PPC_REG_F2 = 23 , PPC_REG_F3 = 24 , PPC_REG_F4 = 25 , PPC_REG_F5 = 26 , PPC_REG_F6 = 27 , PPC_REG_F7 = 28 , PPC_REG_F8 = 29 , PPC_REG_F9 = 30 , PPC_REG_F10 = 31 , PPC_REG_F11 = 32 , PPC_REG_F12 = 33 , PPC_REG_F13 = 34 , PPC_REG_F14 = 35 , PPC_REG_F15 = 36 , PPC_REG_F16 = 37 , PPC_REG_F17 = 38 , PPC_REG_F18 = 39 , PPC_REG_F19 = 40 , PPC_REG_F20 = 41 , PPC_REG_F21 = 42 , PPC_REG_F22 = 43 , PPC_REG_F23 = 44 , PPC_REG_F24 = 45 , PPC_REG_F25 = 46 , PPC_REG_F26 = 47 , PPC_REG_F27 = 48 , PPC_REG_F28 = 49 , PPC_REG_F29 = 50 , PPC_REG_F30 = 51 , PPC_REG_F31 = 52 , PPC_REG_LR8 = 54 , PPC_REG_Q0 = 55 , PPC_REG_Q1 = 56 , PPC_REG_Q2 = 57 , PPC_REG_Q3 = 58 , PPC_REG_Q4 = 59 , PPC_REG_Q5 = 60 , PPC_REG_Q6 = 61 , PPC_REG_Q7 = 62 , PPC_REG_Q8 = 63 , PPC_REG_Q9 = 64 , PPC_REG_Q10 = 65 , PPC_REG_Q11 = 66 , PPC_REG_Q12 = 67 , PPC_REG_Q13 = 68 , PPC_REG_Q14 = 69 , PPC_REG_Q15 = 70 , PPC_REG_Q16 = 71 , PPC_REG_Q17 = 72 , PPC_REG_Q18 = 73 , PPC_REG_Q19 = 74 , PPC_REG_Q20 = 75 , PPC_REG_Q21 = 76 , PPC_REG_Q22 = 77 , PPC_REG_Q23 = 78 , PPC_REG_Q24 = 79 , PPC_REG_Q25 = 80 , PPC_REG_Q26 = 81 , PPC_REG_Q27 = 82 , PPC_REG_Q28 = 83 , PPC_REG_Q29 = 84 , PPC_REG_Q30 = 85 , PPC_REG_Q31 = 86 , PPC_REG_R0 = 87 , PPC_REG_R1 = 88 , PPC_REG_R2 = 89 , PPC_REG_R3 = 90 , PPC_REG_R4 = 91 , PPC_REG_R5 = 92 , PPC_REG_R6 = 93 , PPC_REG_R7 = 94 , PPC_REG_R8 = 95 , PPC_REG_R9 = 96 , PPC_REG_R10 = 97 , PPC_REG_R11 = 98 , PPC_REG_R12 = 99 , PPC_REG_R13 = 100 , PPC_REG_R14 = 101 , PPC_REG_R15 = 102 , PPC_REG_R16 = 103 , PPC_REG_R17 = 104 , PPC_REG_R18 = 105 , PPC_REG_R19 = 106 , PPC_REG_R20 = 107 , PPC_REG_R21 = 108 , PPC_REG_R22 = 109 , PPC_REG_R23 = 110 , PPC_REG_R24 = 111 , PPC_REG_R25 = 112 , PPC_REG_R26 = 113 , PPC_REG_R27 = 114 , PPC_REG_R28 = 115 , PPC_REG_R29 = 116 , PPC_REG_R30 = 117 , PPC_REG_R31 = 118 , PPC_REG_V0 = 151 , PPC_REG_V1 = 152 , PPC_REG_V2 = 153 , PPC_REG_V3 = 154 , PPC_REG_V4 = 155 , PPC_REG_V5 = 156 , PPC_REG_V6 = 157 , PPC_REG_V7 = 158 , PPC_REG_V8 = 159 , PPC_REG_V9 = 160 , PPC_REG_V10 = 161 , PPC_REG_V11 = 162 , PPC_REG_V12 = 163 , PPC_REG_V13 = 164 , PPC_REG_V14 = 165 , PPC_REG_V15 = 166 , PPC_REG_V16 = 167 , PPC_REG_V17 = 168 , PPC_REG_V18 = 169 , PPC_REG_V19 = 170 , PPC_REG_V20 = 171 , PPC_REG_V21 = 172 , PPC_REG_V22 = 173 , PPC_REG_V23 = 174 , PPC_REG_V24 = 175 , PPC_REG_V25 = 176 , PPC_REG_V26 = 177 , PPC_REG_V27 = 178 , PPC_REG_V28 = 179 , PPC_REG_V29 = 180 , PPC_REG_V30 = 181 , PPC_REG_V31 = 182 , PPC_REG_VS0 = 215 , PPC_REG_VS1 = 216 , PPC_REG_VS2 = 217 , PPC_REG_VS3 = 218 , PPC_REG_VS4 = 219 , PPC_REG_VS5 = 220 , PPC_REG_VS6 = 221 , PPC_REG_VS7 = 222 , PPC_REG_VS8 = 223 , PPC_REG_VS9 = 224 , PPC_REG_VS10 = 225 , PPC_REG_VS11 = 226 , PPC_REG_VS12 = 227 , PPC_REG_VS13 = 228 , PPC_REG_VS14 = 229 , PPC_REG_VS15 = 230 , PPC_REG_VS16 = 231 , PPC_REG_VS17 = 232 , PPC_REG_VS18 = 233 , PPC_REG_VS19 = 234 , PPC_REG_VS20 = 235 , PPC_REG_VS21 = 236 , PPC_REG_VS22 = 237 , PPC_REG_VS23 = 238 , PPC_REG_VS24 = 239 , PPC_REG_VS25 = 240 , PPC_REG_VS26 = 241 , PPC_REG_VS27 = 242 , PPC_REG_VS28 = 243 , PPC_REG_VS29 = 244 , PPC_REG_VS30 = 245 , PPC_REG_VS31 = 246 , PPC_REG_VS32 = 247 , PPC_REG_VS33 = 248 , PPC_REG_VS34 = 249 , PPC_REG_VS35 = 250 , PPC_REG_VS36 = 251 , PPC_REG_VS37 = 252 , PPC_REG_VS38 = 253 , PPC_REG_VS39 = 254 , PPC_REG_VS40 = 255 , PPC_REG_VS41 = 256 , PPC_REG_VS42 = 257 , PPC_REG_VS43 = 258 , PPC_REG_VS44 = 259 , PPC_REG_VS45 = 260 , PPC_REG_VS46 = 261 , PPC_REG_VS47 = 262 , PPC_REG_VS48 = 263 , PPC_REG_VS49 = 264 , PPC_REG_VS50 = 265 , PPC_REG_VS51 = 266 , PPC_REG_VS52 = 267 , PPC_REG_VS53 = 268 , PPC_REG_VS54 = 269 , PPC_REG_VS55 = 270 , PPC_REG_VS56 = 271 , PPC_REG_VS57 = 272 , PPC_REG_VS58 = 273 , PPC_REG_VS59 = 274 , PPC_REG_VS60 = 275 , PPC_REG_VS61 = 276 , PPC_REG_VS62 = 277 , PPC_REG_VS63 = 278 , PPC_REG_CR0EQ = 312 , PPC_REG_CR1EQ = 313 , PPC_REG_CR2EQ = 314 , PPC_REG_CR3EQ = 315 , PPC_REG_CR4EQ = 316 , PPC_REG_CR5EQ = 317 , PPC_REG_CR6EQ = 318 , PPC_REG_CR7EQ = 319 , PPC_REG_CR0GT = 320 , PPC_REG_CR1GT = 321 , PPC_REG_CR2GT = 322 , PPC_REG_CR3GT = 323 , PPC_REG_CR4GT = 324 , PPC_REG_CR5GT = 325 , PPC_REG_CR6GT = 326 , PPC_REG_CR7GT = 327 , PPC_REG_CR0LT = 328 , PPC_REG_CR1LT = 329 , PPC_REG_CR2LT = 330 , PPC_REG_CR3LT = 331 , PPC_REG_CR4LT = 332 , PPC_REG_CR5LT = 333 , PPC_REG_CR6LT = 334 , PPC_REG_CR7LT = 335 , PPC_REG_CR0UN = 336 , PPC_REG_CR1UN = 337 , PPC_REG_CR2UN = 338 , PPC_REG_CR3UN = 339 , PPC_REG_CR4UN = 340 , PPC_REG_CR5UN = 341 , PPC_REG_CR6UN = 342 , PPC_REG_CR7UN = 343 , PPC_REG_ENDING = 344 , } # [doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_mem { # [doc = "< base register"] pub base : ppc_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_mem"] [:: std :: mem :: size_of :: < ppc_op_mem > () - 8usize] ; ["Alignment of ppc_op_mem"] [:: std :: mem :: align_of :: < ppc_op_mem > () - 4usize] ; ["Offset of field: ppc_op_mem::base"] [:: std :: mem :: offset_of ! (ppc_op_mem , base) - 0usize] ; ["Offset of field: ppc_op_mem::disp"] [:: std :: mem :: offset_of ! (ppc_op_mem , disp) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_crx { pub scale : :: std :: os :: raw :: c_uint , pub reg : ppc_reg , pub cond : ppc_bc , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_crx"] [:: std :: mem :: size_of :: < ppc_op_crx > () - 12usize] ; ["Alignment of ppc_op_crx"] [:: std :: mem :: align_of :: < ppc_op_crx > () - 4usize] ; ["Offset of field: ppc_op_crx::scale"] [:: std :: mem :: offset_of ! (ppc_op_crx , scale) - 0usize] ; ["Offset of field: ppc_op_crx::reg"] [:: std :: mem :: offset_of ! (ppc_op_crx , reg) - 4usize] ; ["Offset of field: ppc_op_crx::cond"] [:: std :: mem :: offset_of ! (ppc_op_crx , cond) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc_op { # [doc = "< operand type"] pub type_ : ppc_op_type , pub __bindgen_anon_1 : cs_ppc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_ppc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : ppc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : ppc_op_mem , # [doc = "< operand with condition register"] pub crx : ppc_op_crx , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_ppc_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_ppc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::crx"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , crx) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op"] [:: std :: mem :: size_of :: < cs_ppc_op > () - 24usize] ; ["Alignment of cs_ppc_op"] [:: std :: mem :: align_of :: < cs_ppc_op > () - 8usize] ; ["Offset of field: cs_ppc_op::type_"] [:: std :: mem :: offset_of ! (cs_ppc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc { # [doc = " branch code for branch instructions"] pub bc : ppc_bc , # [doc = " branch hint for branch instructions"] pub bh : ppc_bh , # [doc = " if update_cr0 = True, then this 'dot' insn updates CR0"] pub update_cr0 : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_ppc_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc"] [:: std :: mem :: size_of :: < cs_ppc > () - 208usize] ; ["Alignment of cs_ppc"] [:: std :: mem :: align_of :: < cs_ppc > () - 8usize] ; ["Offset of field: cs_ppc::bc"] [:: std :: mem :: offset_of ! (cs_ppc , bc) - 0usize] ; ["Offset of field: cs_ppc::bh"] [:: std :: mem :: offset_of ! (cs_ppc , bh) - 4usize] ; ["Offset of field: cs_ppc::update_cr0"] [:: std :: mem :: offset_of ! (cs_ppc , update_cr0) - 8usize] ; ["Offset of field: cs_ppc::op_count"] [:: std :: mem :: offset_of ! (cs_ppc , op_count) - 9usize] ; ["Offset of field: cs_ppc::operands"] [:: std :: mem :: offset_of ! (cs_ppc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}" , self . bc , self . bh , self . update_cr0 , self . op_count , self . operands) } } # [repr (u32)] # [doc = " PPC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn { PPC_INS_INVALID = 0 , PPC_INS_ADD = 1 , PPC_INS_ADDC = 2 , PPC_INS_ADDE = 3 , PPC_INS_ADDI = 4 , PPC_INS_ADDIC = 5 , PPC_INS_ADDIS = 6 , PPC_INS_ADDME = 7 , PPC_INS_ADDPCIS = 8 , PPC_INS_ADDZE = 9 , PPC_INS_AND = 10 , PPC_INS_ANDC = 11 , PPC_INS_ANDI = 12 , PPC_INS_ANDIS = 13 , PPC_INS_ATTN = 14 , PPC_INS_B = 15 , PPC_INS_BA = 16 , PPC_INS_BC = 17 , PPC_INS_BCA = 18 , PPC_INS_BCCTR = 19 , PPC_INS_BCCTRL = 20 , PPC_INS_BCDCFN = 21 , PPC_INS_BCDCFSQ = 22 , PPC_INS_BCDCFZ = 23 , PPC_INS_BCDCPSGN = 24 , PPC_INS_BCDCTN = 25 , PPC_INS_BCDCTSQ = 26 , PPC_INS_BCDCTZ = 27 , PPC_INS_BCDS = 28 , PPC_INS_BCDSETSGN = 29 , PPC_INS_BCDSR = 30 , PPC_INS_BCDTRUNC = 31 , PPC_INS_BCDUS = 32 , PPC_INS_BCDUTRUNC = 33 , PPC_INS_BCL = 34 , PPC_INS_BCLA = 35 , PPC_INS_BCLR = 36 , PPC_INS_BCLRL = 37 , PPC_INS_BCTR = 38 , PPC_INS_BCTRL = 39 , PPC_INS_BDNZ = 40 , PPC_INS_BDNZA = 41 , PPC_INS_BDNZF = 42 , PPC_INS_BDNZFA = 43 , PPC_INS_BDNZFL = 44 , PPC_INS_BDNZFLA = 45 , PPC_INS_BDNZFLR = 46 , PPC_INS_BDNZFLRL = 47 , PPC_INS_BDNZL = 48 , PPC_INS_BDNZLA = 49 , PPC_INS_BDNZLR = 50 , PPC_INS_BDNZLRL = 51 , PPC_INS_BDNZT = 52 , PPC_INS_BDNZTA = 53 , PPC_INS_BDNZTL = 54 , PPC_INS_BDNZTLA = 55 , PPC_INS_BDNZTLR = 56 , PPC_INS_BDNZTLRL = 57 , PPC_INS_BDZ = 58 , PPC_INS_BDZA = 59 , PPC_INS_BDZF = 60 , PPC_INS_BDZFA = 61 , PPC_INS_BDZFL = 62 , PPC_INS_BDZFLA = 63 , PPC_INS_BDZFLR = 64 , PPC_INS_BDZFLRL = 65 , PPC_INS_BDZL = 66 , PPC_INS_BDZLA = 67 , PPC_INS_BDZLR = 68 , PPC_INS_BDZLRL = 69 , PPC_INS_BDZT = 70 , PPC_INS_BDZTA = 71 , PPC_INS_BDZTL = 72 , PPC_INS_BDZTLA = 73 , PPC_INS_BDZTLR = 74 , PPC_INS_BDZTLRL = 75 , PPC_INS_BEQ = 76 , PPC_INS_BEQA = 77 , PPC_INS_BEQCTR = 78 , PPC_INS_BEQCTRL = 79 , PPC_INS_BEQL = 80 , PPC_INS_BEQLA = 81 , PPC_INS_BEQLR = 82 , PPC_INS_BEQLRL = 83 , PPC_INS_BF = 84 , PPC_INS_BFA = 85 , PPC_INS_BFCTR = 86 , PPC_INS_BFCTRL = 87 , PPC_INS_BFL = 88 , PPC_INS_BFLA = 89 , PPC_INS_BFLR = 90 , PPC_INS_BFLRL = 91 , PPC_INS_BGE = 92 , PPC_INS_BGEA = 93 , PPC_INS_BGECTR = 94 , PPC_INS_BGECTRL = 95 , PPC_INS_BGEL = 96 , PPC_INS_BGELA = 97 , PPC_INS_BGELR = 98 , PPC_INS_BGELRL = 99 , PPC_INS_BGT = 100 , PPC_INS_BGTA = 101 , PPC_INS_BGTCTR = 102 , PPC_INS_BGTCTRL = 103 , PPC_INS_BGTL = 104 , PPC_INS_BGTLA = 105 , PPC_INS_BGTLR = 106 , PPC_INS_BGTLRL = 107 , PPC_INS_BL = 108 , PPC_INS_BLA = 109 , PPC_INS_BLE = 110 , PPC_INS_BLEA = 111 , PPC_INS_BLECTR = 112 , PPC_INS_BLECTRL = 113 , PPC_INS_BLEL = 114 , PPC_INS_BLELA = 115 , PPC_INS_BLELR = 116 , PPC_INS_BLELRL = 117 , PPC_INS_BLR = 118 , PPC_INS_BLRL = 119 , PPC_INS_BLT = 120 , PPC_INS_BLTA = 121 , PPC_INS_BLTCTR = 122 , PPC_INS_BLTCTRL = 123 , PPC_INS_BLTL = 124 , PPC_INS_BLTLA = 125 , PPC_INS_BLTLR = 126 , PPC_INS_BLTLRL = 127 , PPC_INS_BNE = 128 , PPC_INS_BNEA = 129 , PPC_INS_BNECTR = 130 , PPC_INS_BNECTRL = 131 , PPC_INS_BNEL = 132 , PPC_INS_BNELA = 133 , PPC_INS_BNELR = 134 , PPC_INS_BNELRL = 135 , PPC_INS_BNG = 136 , PPC_INS_BNGA = 137 , PPC_INS_BNGCTR = 138 , PPC_INS_BNGCTRL = 139 , PPC_INS_BNGL = 140 , PPC_INS_BNGLA = 141 , PPC_INS_BNGLR = 142 , PPC_INS_BNGLRL = 143 , PPC_INS_BNL = 144 , PPC_INS_BNLA = 145 , PPC_INS_BNLCTR = 146 , PPC_INS_BNLCTRL = 147 , PPC_INS_BNLL = 148 , PPC_INS_BNLLA = 149 , PPC_INS_BNLLR = 150 , PPC_INS_BNLLRL = 151 , PPC_INS_BNS = 152 , PPC_INS_BNSA = 153 , PPC_INS_BNSCTR = 154 , PPC_INS_BNSCTRL = 155 , PPC_INS_BNSL = 156 , PPC_INS_BNSLA = 157 , PPC_INS_BNSLR = 158 , PPC_INS_BNSLRL = 159 , PPC_INS_BNU = 160 , PPC_INS_BNUA = 161 , PPC_INS_BNUCTR = 162 , PPC_INS_BNUCTRL = 163 , PPC_INS_BNUL = 164 , PPC_INS_BNULA = 165 , PPC_INS_BNULR = 166 , PPC_INS_BNULRL = 167 , PPC_INS_BPERMD = 168 , PPC_INS_BRINC = 169 , PPC_INS_BSO = 170 , PPC_INS_BSOA = 171 , PPC_INS_BSOCTR = 172 , PPC_INS_BSOCTRL = 173 , PPC_INS_BSOL = 174 , PPC_INS_BSOLA = 175 , PPC_INS_BSOLR = 176 , PPC_INS_BSOLRL = 177 , PPC_INS_BT = 178 , PPC_INS_BTA = 179 , PPC_INS_BTCTR = 180 , PPC_INS_BTCTRL = 181 , PPC_INS_BTL = 182 , PPC_INS_BTLA = 183 , PPC_INS_BTLR = 184 , PPC_INS_BTLRL = 185 , PPC_INS_BUN = 186 , PPC_INS_BUNA = 187 , PPC_INS_BUNCTR = 188 , PPC_INS_BUNCTRL = 189 , PPC_INS_BUNL = 190 , PPC_INS_BUNLA = 191 , PPC_INS_BUNLR = 192 , PPC_INS_BUNLRL = 193 , PPC_INS_CLRBHRB = 194 , PPC_INS_CLRLDI = 195 , PPC_INS_CLRLSLDI = 196 , PPC_INS_CLRLSLWI = 197 , PPC_INS_CLRLWI = 198 , PPC_INS_CLRRDI = 199 , PPC_INS_CLRRWI = 200 , PPC_INS_CMP = 201 , PPC_INS_CMPB = 202 , PPC_INS_CMPD = 203 , PPC_INS_CMPDI = 204 , PPC_INS_CMPEQB = 205 , PPC_INS_CMPI = 206 , PPC_INS_CMPL = 207 , PPC_INS_CMPLD = 208 , PPC_INS_CMPLDI = 209 , PPC_INS_CMPLI = 210 , PPC_INS_CMPLW = 211 , PPC_INS_CMPLWI = 212 , PPC_INS_CMPRB = 213 , PPC_INS_CMPW = 214 , PPC_INS_CMPWI = 215 , PPC_INS_CNTLZD = 216 , PPC_INS_CNTLZW = 217 , PPC_INS_CNTTZD = 218 , PPC_INS_CNTTZW = 219 , PPC_INS_COPY = 220 , PPC_INS_COPY_FIRST = 221 , PPC_INS_CP_ABORT = 222 , PPC_INS_CRAND = 223 , PPC_INS_CRANDC = 224 , PPC_INS_CRCLR = 225 , PPC_INS_CREQV = 226 , PPC_INS_CRMOVE = 227 , PPC_INS_CRNAND = 228 , PPC_INS_CRNOR = 229 , PPC_INS_CRNOT = 230 , PPC_INS_CROR = 231 , PPC_INS_CRORC = 232 , PPC_INS_CRSET = 233 , PPC_INS_CRXOR = 234 , PPC_INS_DARN = 235 , PPC_INS_DCBA = 236 , PPC_INS_DCBF = 237 , PPC_INS_DCBFEP = 238 , PPC_INS_DCBFL = 239 , PPC_INS_DCBFLP = 240 , PPC_INS_DCBI = 241 , PPC_INS_DCBST = 242 , PPC_INS_DCBSTEP = 243 , PPC_INS_DCBT = 244 , PPC_INS_DCBTCT = 245 , PPC_INS_DCBTDS = 246 , PPC_INS_DCBTEP = 247 , PPC_INS_DCBTST = 248 , PPC_INS_DCBTSTCT = 249 , PPC_INS_DCBTSTDS = 250 , PPC_INS_DCBTSTEP = 251 , PPC_INS_DCBTSTT = 252 , PPC_INS_DCBTT = 253 , PPC_INS_DCBZ = 254 , PPC_INS_DCBZEP = 255 , PPC_INS_DCBZL = 256 , PPC_INS_DCBZLEP = 257 , PPC_INS_DCCCI = 258 , PPC_INS_DCI = 259 , PPC_INS_DIVD = 260 , PPC_INS_DIVDE = 261 , PPC_INS_DIVDEU = 262 , PPC_INS_DIVDU = 263 , PPC_INS_DIVW = 264 , PPC_INS_DIVWE = 265 , PPC_INS_DIVWEU = 266 , PPC_INS_DIVWU = 267 , PPC_INS_DSS = 268 , PPC_INS_DSSALL = 269 , PPC_INS_DST = 270 , PPC_INS_DSTST = 271 , PPC_INS_DSTSTT = 272 , PPC_INS_DSTT = 273 , PPC_INS_EFDABS = 274 , PPC_INS_EFDADD = 275 , PPC_INS_EFDCFS = 276 , PPC_INS_EFDCFSF = 277 , PPC_INS_EFDCFSI = 278 , PPC_INS_EFDCFSID = 279 , PPC_INS_EFDCFUF = 280 , PPC_INS_EFDCFUI = 281 , PPC_INS_EFDCFUID = 282 , PPC_INS_EFDCMPEQ = 283 , PPC_INS_EFDCMPGT = 284 , PPC_INS_EFDCMPLT = 285 , PPC_INS_EFDCTSF = 286 , PPC_INS_EFDCTSI = 287 , PPC_INS_EFDCTSIDZ = 288 , PPC_INS_EFDCTSIZ = 289 , PPC_INS_EFDCTUF = 290 , PPC_INS_EFDCTUI = 291 , PPC_INS_EFDCTUIDZ = 292 , PPC_INS_EFDCTUIZ = 293 , PPC_INS_EFDDIV = 294 , PPC_INS_EFDMUL = 295 , PPC_INS_EFDNABS = 296 , PPC_INS_EFDNEG = 297 , PPC_INS_EFDSUB = 298 , PPC_INS_EFDTSTEQ = 299 , PPC_INS_EFDTSTGT = 300 , PPC_INS_EFDTSTLT = 301 , PPC_INS_EFSABS = 302 , PPC_INS_EFSADD = 303 , PPC_INS_EFSCFD = 304 , PPC_INS_EFSCFSF = 305 , PPC_INS_EFSCFSI = 306 , PPC_INS_EFSCFUF = 307 , PPC_INS_EFSCFUI = 308 , PPC_INS_EFSCMPEQ = 309 , PPC_INS_EFSCMPGT = 310 , PPC_INS_EFSCMPLT = 311 , PPC_INS_EFSCTSF = 312 , PPC_INS_EFSCTSI = 313 , PPC_INS_EFSCTSIZ = 314 , PPC_INS_EFSCTUF = 315 , PPC_INS_EFSCTUI = 316 , PPC_INS_EFSCTUIZ = 317 , PPC_INS_EFSDIV = 318 , PPC_INS_EFSMUL = 319 , PPC_INS_EFSNABS = 320 , PPC_INS_EFSNEG = 321 , PPC_INS_EFSSUB = 322 , PPC_INS_EFSTSTEQ = 323 , PPC_INS_EFSTSTGT = 324 , PPC_INS_EFSTSTLT = 325 , PPC_INS_EIEIO = 326 , PPC_INS_EQV = 327 , PPC_INS_EVABS = 328 , PPC_INS_EVADDIW = 329 , PPC_INS_EVADDSMIAAW = 330 , PPC_INS_EVADDSSIAAW = 331 , PPC_INS_EVADDUMIAAW = 332 , PPC_INS_EVADDUSIAAW = 333 , PPC_INS_EVADDW = 334 , PPC_INS_EVAND = 335 , PPC_INS_EVANDC = 336 , PPC_INS_EVCMPEQ = 337 , PPC_INS_EVCMPGTS = 338 , PPC_INS_EVCMPGTU = 339 , PPC_INS_EVCMPLTS = 340 , PPC_INS_EVCMPLTU = 341 , PPC_INS_EVCNTLSW = 342 , PPC_INS_EVCNTLZW = 343 , PPC_INS_EVDIVWS = 344 , PPC_INS_EVDIVWU = 345 , PPC_INS_EVEQV = 346 , PPC_INS_EVEXTSB = 347 , PPC_INS_EVEXTSH = 348 , PPC_INS_EVFSABS = 349 , PPC_INS_EVFSADD = 350 , PPC_INS_EVFSCFSF = 351 , PPC_INS_EVFSCFSI = 352 , PPC_INS_EVFSCFUF = 353 , PPC_INS_EVFSCFUI = 354 , PPC_INS_EVFSCMPEQ = 355 , PPC_INS_EVFSCMPGT = 356 , PPC_INS_EVFSCMPLT = 357 , PPC_INS_EVFSCTSF = 358 , PPC_INS_EVFSCTSI = 359 , PPC_INS_EVFSCTSIZ = 360 , PPC_INS_EVFSCTUI = 361 , PPC_INS_EVFSDIV = 362 , PPC_INS_EVFSMUL = 363 , PPC_INS_EVFSNABS = 364 , PPC_INS_EVFSNEG = 365 , PPC_INS_EVFSSUB = 366 , PPC_INS_EVFSTSTEQ = 367 , PPC_INS_EVFSTSTGT = 368 , PPC_INS_EVFSTSTLT = 369 , PPC_INS_EVLDD = 370 , PPC_INS_EVLDDX = 371 , PPC_INS_EVLDH = 372 , PPC_INS_EVLDHX = 373 , PPC_INS_EVLDW = 374 , PPC_INS_EVLDWX = 375 , PPC_INS_EVLHHESPLAT = 376 , PPC_INS_EVLHHESPLATX = 377 , PPC_INS_EVLHHOSSPLAT = 378 , PPC_INS_EVLHHOSSPLATX = 379 , PPC_INS_EVLHHOUSPLAT = 380 , PPC_INS_EVLHHOUSPLATX = 381 , PPC_INS_EVLWHE = 382 , PPC_INS_EVLWHEX = 383 , PPC_INS_EVLWHOS = 384 , PPC_INS_EVLWHOSX = 385 , PPC_INS_EVLWHOU = 386 , PPC_INS_EVLWHOUX = 387 , PPC_INS_EVLWHSPLAT = 388 , PPC_INS_EVLWHSPLATX = 389 , PPC_INS_EVLWWSPLAT = 390 , PPC_INS_EVLWWSPLATX = 391 , PPC_INS_EVMERGEHI = 392 , PPC_INS_EVMERGEHILO = 393 , PPC_INS_EVMERGELO = 394 , PPC_INS_EVMERGELOHI = 395 , PPC_INS_EVMHEGSMFAA = 396 , PPC_INS_EVMHEGSMFAN = 397 , PPC_INS_EVMHEGSMIAA = 398 , PPC_INS_EVMHEGSMIAN = 399 , PPC_INS_EVMHEGUMIAA = 400 , PPC_INS_EVMHEGUMIAN = 401 , PPC_INS_EVMHESMF = 402 , PPC_INS_EVMHESMFA = 403 , PPC_INS_EVMHESMFAAW = 404 , PPC_INS_EVMHESMFANW = 405 , PPC_INS_EVMHESMI = 406 , PPC_INS_EVMHESMIA = 407 , PPC_INS_EVMHESMIAAW = 408 , PPC_INS_EVMHESMIANW = 409 , PPC_INS_EVMHESSF = 410 , PPC_INS_EVMHESSFA = 411 , PPC_INS_EVMHESSFAAW = 412 , PPC_INS_EVMHESSFANW = 413 , PPC_INS_EVMHESSIAAW = 414 , PPC_INS_EVMHESSIANW = 415 , PPC_INS_EVMHEUMI = 416 , PPC_INS_EVMHEUMIA = 417 , PPC_INS_EVMHEUMIAAW = 418 , PPC_INS_EVMHEUMIANW = 419 , PPC_INS_EVMHEUSIAAW = 420 , PPC_INS_EVMHEUSIANW = 421 , PPC_INS_EVMHOGSMFAA = 422 , PPC_INS_EVMHOGSMFAN = 423 , PPC_INS_EVMHOGSMIAA = 424 , PPC_INS_EVMHOGSMIAN = 425 , PPC_INS_EVMHOGUMIAA = 426 , PPC_INS_EVMHOGUMIAN = 427 , PPC_INS_EVMHOSMF = 428 , PPC_INS_EVMHOSMFA = 429 , PPC_INS_EVMHOSMFAAW = 430 , PPC_INS_EVMHOSMFANW = 431 , PPC_INS_EVMHOSMI = 432 , PPC_INS_EVMHOSMIA = 433 , PPC_INS_EVMHOSMIAAW = 434 , PPC_INS_EVMHOSMIANW = 435 , PPC_INS_EVMHOSSF = 436 , PPC_INS_EVMHOSSFA = 437 , PPC_INS_EVMHOSSFAAW = 438 , PPC_INS_EVMHOSSFANW = 439 , PPC_INS_EVMHOSSIAAW = 440 , PPC_INS_EVMHOSSIANW = 441 , PPC_INS_EVMHOUMI = 442 , PPC_INS_EVMHOUMIA = 443 , PPC_INS_EVMHOUMIAAW = 444 , PPC_INS_EVMHOUMIANW = 445 , PPC_INS_EVMHOUSIAAW = 446 , PPC_INS_EVMHOUSIANW = 447 , PPC_INS_EVMRA = 448 , PPC_INS_EVMWHSMF = 449 , PPC_INS_EVMWHSMFA = 450 , PPC_INS_EVMWHSMI = 451 , PPC_INS_EVMWHSMIA = 452 , PPC_INS_EVMWHSSF = 453 , PPC_INS_EVMWHSSFA = 454 , PPC_INS_EVMWHUMI = 455 , PPC_INS_EVMWHUMIA = 456 , PPC_INS_EVMWLSMIAAW = 457 , PPC_INS_EVMWLSMIANW = 458 , PPC_INS_EVMWLSSIAAW = 459 , PPC_INS_EVMWLSSIANW = 460 , PPC_INS_EVMWLUMI = 461 , PPC_INS_EVMWLUMIA = 462 , PPC_INS_EVMWLUMIAAW = 463 , PPC_INS_EVMWLUMIANW = 464 , PPC_INS_EVMWLUSIAAW = 465 , PPC_INS_EVMWLUSIANW = 466 , PPC_INS_EVMWSMF = 467 , PPC_INS_EVMWSMFA = 468 , PPC_INS_EVMWSMFAA = 469 , PPC_INS_EVMWSMFAN = 470 , PPC_INS_EVMWSMI = 471 , PPC_INS_EVMWSMIA = 472 , PPC_INS_EVMWSMIAA = 473 , PPC_INS_EVMWSMIAN = 474 , PPC_INS_EVMWSSF = 475 , PPC_INS_EVMWSSFA = 476 , PPC_INS_EVMWSSFAA = 477 , PPC_INS_EVMWSSFAN = 478 , PPC_INS_EVMWUMI = 479 , PPC_INS_EVMWUMIA = 480 , PPC_INS_EVMWUMIAA = 481 , PPC_INS_EVMWUMIAN = 482 , PPC_INS_EVNAND = 483 , PPC_INS_EVNEG = 484 , PPC_INS_EVNOR = 485 , PPC_INS_EVOR = 486 , PPC_INS_EVORC = 487 , PPC_INS_EVRLW = 488 , PPC_INS_EVRLWI = 489 , PPC_INS_EVRNDW = 490 , PPC_INS_EVSEL = 491 , PPC_INS_EVSLW = 492 , PPC_INS_EVSLWI = 493 , PPC_INS_EVSPLATFI = 494 , PPC_INS_EVSPLATI = 495 , PPC_INS_EVSRWIS = 496 , PPC_INS_EVSRWIU = 497 , PPC_INS_EVSRWS = 498 , PPC_INS_EVSRWU = 499 , PPC_INS_EVSTDD = 500 , PPC_INS_EVSTDDX = 501 , PPC_INS_EVSTDH = 502 , PPC_INS_EVSTDHX = 503 , PPC_INS_EVSTDW = 504 , PPC_INS_EVSTDWX = 505 , PPC_INS_EVSTWHE = 506 , PPC_INS_EVSTWHEX = 507 , PPC_INS_EVSTWHO = 508 , PPC_INS_EVSTWHOX = 509 , PPC_INS_EVSTWWE = 510 , PPC_INS_EVSTWWEX = 511 , PPC_INS_EVSTWWO = 512 , PPC_INS_EVSTWWOX = 513 , PPC_INS_EVSUBFSMIAAW = 514 , PPC_INS_EVSUBFSSIAAW = 515 , PPC_INS_EVSUBFUMIAAW = 516 , PPC_INS_EVSUBFUSIAAW = 517 , PPC_INS_EVSUBFW = 518 , PPC_INS_EVSUBIFW = 519 , PPC_INS_EVXOR = 520 , PPC_INS_EXTLDI = 521 , PPC_INS_EXTLWI = 522 , PPC_INS_EXTRDI = 523 , PPC_INS_EXTRWI = 524 , PPC_INS_EXTSB = 525 , PPC_INS_EXTSH = 526 , PPC_INS_EXTSW = 527 , PPC_INS_EXTSWSLI = 528 , PPC_INS_FABS = 529 , PPC_INS_FADD = 530 , PPC_INS_FADDS = 531 , PPC_INS_FCFID = 532 , PPC_INS_FCFIDS = 533 , PPC_INS_FCFIDU = 534 , PPC_INS_FCFIDUS = 535 , PPC_INS_FCMPU = 536 , PPC_INS_FCPSGN = 537 , PPC_INS_FCTID = 538 , PPC_INS_FCTIDU = 539 , PPC_INS_FCTIDUZ = 540 , PPC_INS_FCTIDZ = 541 , PPC_INS_FCTIW = 542 , PPC_INS_FCTIWU = 543 , PPC_INS_FCTIWUZ = 544 , PPC_INS_FCTIWZ = 545 , PPC_INS_FDIV = 546 , PPC_INS_FDIVS = 547 , PPC_INS_FMADD = 548 , PPC_INS_FMADDS = 549 , PPC_INS_FMR = 550 , PPC_INS_FMSUB = 551 , PPC_INS_FMSUBS = 552 , PPC_INS_FMUL = 553 , PPC_INS_FMULS = 554 , PPC_INS_FNABS = 555 , PPC_INS_FNEG = 556 , PPC_INS_FNMADD = 557 , PPC_INS_FNMADDS = 558 , PPC_INS_FNMSUB = 559 , PPC_INS_FNMSUBS = 560 , PPC_INS_FRE = 561 , PPC_INS_FRES = 562 , PPC_INS_FRIM = 563 , PPC_INS_FRIN = 564 , PPC_INS_FRIP = 565 , PPC_INS_FRIZ = 566 , PPC_INS_FRSP = 567 , PPC_INS_FRSQRTE = 568 , PPC_INS_FRSQRTES = 569 , PPC_INS_FSEL = 570 , PPC_INS_FSQRT = 571 , PPC_INS_FSQRTS = 572 , PPC_INS_FSUB = 573 , PPC_INS_FSUBS = 574 , PPC_INS_FTDIV = 575 , PPC_INS_FTSQRT = 576 , PPC_INS_HRFID = 577 , PPC_INS_ICBI = 578 , PPC_INS_ICBIEP = 579 , PPC_INS_ICBLC = 580 , PPC_INS_ICBLQ = 581 , PPC_INS_ICBT = 582 , PPC_INS_ICBTLS = 583 , PPC_INS_ICCCI = 584 , PPC_INS_ICI = 585 , PPC_INS_INSLWI = 586 , PPC_INS_INSRDI = 587 , PPC_INS_INSRWI = 588 , PPC_INS_ISEL = 589 , PPC_INS_ISYNC = 590 , PPC_INS_LA = 591 , PPC_INS_LBARX = 592 , PPC_INS_LBEPX = 593 , PPC_INS_LBZ = 594 , PPC_INS_LBZCIX = 595 , PPC_INS_LBZU = 596 , PPC_INS_LBZUX = 597 , PPC_INS_LBZX = 598 , PPC_INS_LD = 599 , PPC_INS_LDARX = 600 , PPC_INS_LDAT = 601 , PPC_INS_LDBRX = 602 , PPC_INS_LDCIX = 603 , PPC_INS_LDMX = 604 , PPC_INS_LDU = 605 , PPC_INS_LDUX = 606 , PPC_INS_LDX = 607 , PPC_INS_LFD = 608 , PPC_INS_LFDEPX = 609 , PPC_INS_LFDU = 610 , PPC_INS_LFDUX = 611 , PPC_INS_LFDX = 612 , PPC_INS_LFIWAX = 613 , PPC_INS_LFIWZX = 614 , PPC_INS_LFS = 615 , PPC_INS_LFSU = 616 , PPC_INS_LFSUX = 617 , PPC_INS_LFSX = 618 , PPC_INS_LHA = 619 , PPC_INS_LHARX = 620 , PPC_INS_LHAU = 621 , PPC_INS_LHAUX = 622 , PPC_INS_LHAX = 623 , PPC_INS_LHBRX = 624 , PPC_INS_LHEPX = 625 , PPC_INS_LHZ = 626 , PPC_INS_LHZCIX = 627 , PPC_INS_LHZU = 628 , PPC_INS_LHZUX = 629 , PPC_INS_LHZX = 630 , PPC_INS_LI = 631 , PPC_INS_LIS = 632 , PPC_INS_LMW = 633 , PPC_INS_LNIA = 634 , PPC_INS_LSWI = 635 , PPC_INS_LVEBX = 636 , PPC_INS_LVEHX = 637 , PPC_INS_LVEWX = 638 , PPC_INS_LVSL = 639 , PPC_INS_LVSR = 640 , PPC_INS_LVX = 641 , PPC_INS_LVXL = 642 , PPC_INS_LWA = 643 , PPC_INS_LWARX = 644 , PPC_INS_LWAT = 645 , PPC_INS_LWAUX = 646 , PPC_INS_LWAX = 647 , PPC_INS_LWBRX = 648 , PPC_INS_LWEPX = 649 , PPC_INS_LWSYNC = 650 , PPC_INS_LWZ = 651 , PPC_INS_LWZCIX = 652 , PPC_INS_LWZU = 653 , PPC_INS_LWZUX = 654 , PPC_INS_LWZX = 655 , PPC_INS_LXSD = 656 , PPC_INS_LXSDX = 657 , PPC_INS_LXSIBZX = 658 , PPC_INS_LXSIHZX = 659 , PPC_INS_LXSIWAX = 660 , PPC_INS_LXSIWZX = 661 , PPC_INS_LXSSP = 662 , PPC_INS_LXSSPX = 663 , PPC_INS_LXV = 664 , PPC_INS_LXVB16X = 665 , PPC_INS_LXVD2X = 666 , PPC_INS_LXVDSX = 667 , PPC_INS_LXVH8X = 668 , PPC_INS_LXVL = 669 , PPC_INS_LXVLL = 670 , PPC_INS_LXVW4X = 671 , PPC_INS_LXVWSX = 672 , PPC_INS_LXVX = 673 , PPC_INS_MADDHD = 674 , PPC_INS_MADDHDU = 675 , PPC_INS_MADDLD = 676 , PPC_INS_MBAR = 677 , PPC_INS_MCRF = 678 , PPC_INS_MCRFS = 679 , PPC_INS_MCRXRX = 680 , PPC_INS_MFAMR = 681 , PPC_INS_MFASR = 682 , PPC_INS_MFBHRBE = 683 , PPC_INS_MFBR0 = 684 , PPC_INS_MFBR1 = 685 , PPC_INS_MFBR2 = 686 , PPC_INS_MFBR3 = 687 , PPC_INS_MFBR4 = 688 , PPC_INS_MFBR5 = 689 , PPC_INS_MFBR6 = 690 , PPC_INS_MFBR7 = 691 , PPC_INS_MFCFAR = 692 , PPC_INS_MFCR = 693 , PPC_INS_MFCTR = 694 , PPC_INS_MFDAR = 695 , PPC_INS_MFDBATL = 696 , PPC_INS_MFDBATU = 697 , PPC_INS_MFDCCR = 698 , PPC_INS_MFDCR = 699 , PPC_INS_MFDEAR = 700 , PPC_INS_MFDEC = 701 , PPC_INS_MFDSCR = 702 , PPC_INS_MFDSISR = 703 , PPC_INS_MFESR = 704 , PPC_INS_MFFPRD = 705 , PPC_INS_MFFS = 706 , PPC_INS_MFFSCDRN = 707 , PPC_INS_MFFSCDRNI = 708 , PPC_INS_MFFSCE = 709 , PPC_INS_MFFSCRN = 710 , PPC_INS_MFFSCRNI = 711 , PPC_INS_MFFSL = 712 , PPC_INS_MFIBATL = 713 , PPC_INS_MFIBATU = 714 , PPC_INS_MFICCR = 715 , PPC_INS_MFLR = 716 , PPC_INS_MFMSR = 717 , PPC_INS_MFOCRF = 718 , PPC_INS_MFPID = 719 , PPC_INS_MFPMR = 720 , PPC_INS_MFPVR = 721 , PPC_INS_MFRTCL = 722 , PPC_INS_MFRTCU = 723 , PPC_INS_MFSDR1 = 724 , PPC_INS_MFSPEFSCR = 725 , PPC_INS_MFSPR = 726 , PPC_INS_MFSPRG = 727 , PPC_INS_MFSPRG0 = 728 , PPC_INS_MFSPRG1 = 729 , PPC_INS_MFSPRG2 = 730 , PPC_INS_MFSPRG3 = 731 , PPC_INS_MFSPRG4 = 732 , PPC_INS_MFSPRG5 = 733 , PPC_INS_MFSPRG6 = 734 , PPC_INS_MFSPRG7 = 735 , PPC_INS_MFSR = 736 , PPC_INS_MFSRIN = 737 , PPC_INS_MFSRR0 = 738 , PPC_INS_MFSRR1 = 739 , PPC_INS_MFSRR2 = 740 , PPC_INS_MFSRR3 = 741 , PPC_INS_MFTB = 742 , PPC_INS_MFTBHI = 743 , PPC_INS_MFTBL = 744 , PPC_INS_MFTBLO = 745 , PPC_INS_MFTBU = 746 , PPC_INS_MFTCR = 747 , PPC_INS_MFVRD = 748 , PPC_INS_MFVRSAVE = 749 , PPC_INS_MFVSCR = 750 , PPC_INS_MFVSRD = 751 , PPC_INS_MFVSRLD = 752 , PPC_INS_MFVSRWZ = 753 , PPC_INS_MFXER = 754 , PPC_INS_MODSD = 755 , PPC_INS_MODSW = 756 , PPC_INS_MODUD = 757 , PPC_INS_MODUW = 758 , PPC_INS_MR = 759 , PPC_INS_MSGSYNC = 760 , PPC_INS_MSYNC = 761 , PPC_INS_MTAMR = 762 , PPC_INS_MTASR = 763 , PPC_INS_MTBR0 = 764 , PPC_INS_MTBR1 = 765 , PPC_INS_MTBR2 = 766 , PPC_INS_MTBR3 = 767 , PPC_INS_MTBR4 = 768 , PPC_INS_MTBR5 = 769 , PPC_INS_MTBR6 = 770 , PPC_INS_MTBR7 = 771 , PPC_INS_MTCFAR = 772 , PPC_INS_MTCR = 773 , PPC_INS_MTCRF = 774 , PPC_INS_MTCTR = 775 , PPC_INS_MTDAR = 776 , PPC_INS_MTDBATL = 777 , PPC_INS_MTDBATU = 778 , PPC_INS_MTDCCR = 779 , PPC_INS_MTDCR = 780 , PPC_INS_MTDEAR = 781 , PPC_INS_MTDEC = 782 , PPC_INS_MTDSCR = 783 , PPC_INS_MTDSISR = 784 , PPC_INS_MTESR = 785 , PPC_INS_MTFSB0 = 786 , PPC_INS_MTFSB1 = 787 , PPC_INS_MTFSF = 788 , PPC_INS_MTFSFI = 789 , PPC_INS_MTIBATL = 790 , PPC_INS_MTIBATU = 791 , PPC_INS_MTICCR = 792 , PPC_INS_MTLR = 793 , PPC_INS_MTMSR = 794 , PPC_INS_MTMSRD = 795 , PPC_INS_MTOCRF = 796 , PPC_INS_MTPID = 797 , PPC_INS_MTPMR = 798 , PPC_INS_MTSDR1 = 799 , PPC_INS_MTSPEFSCR = 800 , PPC_INS_MTSPR = 801 , PPC_INS_MTSPRG = 802 , PPC_INS_MTSPRG0 = 803 , PPC_INS_MTSPRG1 = 804 , PPC_INS_MTSPRG2 = 805 , PPC_INS_MTSPRG3 = 806 , PPC_INS_MTSPRG4 = 807 , PPC_INS_MTSPRG5 = 808 , PPC_INS_MTSPRG6 = 809 , PPC_INS_MTSPRG7 = 810 , PPC_INS_MTSR = 811 , PPC_INS_MTSRIN = 812 , PPC_INS_MTSRR0 = 813 , PPC_INS_MTSRR1 = 814 , PPC_INS_MTSRR2 = 815 , PPC_INS_MTSRR3 = 816 , PPC_INS_MTTBHI = 817 , PPC_INS_MTTBL = 818 , PPC_INS_MTTBLO = 819 , PPC_INS_MTTBU = 820 , PPC_INS_MTTCR = 821 , PPC_INS_MTVRSAVE = 822 , PPC_INS_MTVSCR = 823 , PPC_INS_MTVSRD = 824 , PPC_INS_MTVSRDD = 825 , PPC_INS_MTVSRWA = 826 , PPC_INS_MTVSRWS = 827 , PPC_INS_MTVSRWZ = 828 , PPC_INS_MTXER = 829 , PPC_INS_MULHD = 830 , PPC_INS_MULHDU = 831 , PPC_INS_MULHW = 832 , PPC_INS_MULHWU = 833 , PPC_INS_MULLD = 834 , PPC_INS_MULLI = 835 , PPC_INS_MULLW = 836 , PPC_INS_NAND = 837 , PPC_INS_NAP = 838 , PPC_INS_NEG = 839 , PPC_INS_NOP = 840 , PPC_INS_NOR = 841 , PPC_INS_NOT = 842 , PPC_INS_OR = 843 , PPC_INS_ORC = 844 , PPC_INS_ORI = 845 , PPC_INS_ORIS = 846 , PPC_INS_PASTE = 847 , PPC_INS_PASTE_LAST = 848 , PPC_INS_POPCNTB = 849 , PPC_INS_POPCNTD = 850 , PPC_INS_POPCNTW = 851 , PPC_INS_PTESYNC = 852 , PPC_INS_QVALIGNI = 853 , PPC_INS_QVESPLATI = 854 , PPC_INS_QVFABS = 855 , PPC_INS_QVFADD = 856 , PPC_INS_QVFADDS = 857 , PPC_INS_QVFAND = 858 , PPC_INS_QVFANDC = 859 , PPC_INS_QVFCFID = 860 , PPC_INS_QVFCFIDS = 861 , PPC_INS_QVFCFIDU = 862 , PPC_INS_QVFCFIDUS = 863 , PPC_INS_QVFCLR = 864 , PPC_INS_QVFCMPEQ = 865 , PPC_INS_QVFCMPGT = 866 , PPC_INS_QVFCMPLT = 867 , PPC_INS_QVFCPSGN = 868 , PPC_INS_QVFCTFB = 869 , PPC_INS_QVFCTID = 870 , PPC_INS_QVFCTIDU = 871 , PPC_INS_QVFCTIDUZ = 872 , PPC_INS_QVFCTIDZ = 873 , PPC_INS_QVFCTIW = 874 , PPC_INS_QVFCTIWU = 875 , PPC_INS_QVFCTIWUZ = 876 , PPC_INS_QVFCTIWZ = 877 , PPC_INS_QVFEQU = 878 , PPC_INS_QVFLOGICAL = 879 , PPC_INS_QVFMADD = 880 , PPC_INS_QVFMADDS = 881 , PPC_INS_QVFMR = 882 , PPC_INS_QVFMSUB = 883 , PPC_INS_QVFMSUBS = 884 , PPC_INS_QVFMUL = 885 , PPC_INS_QVFMULS = 886 , PPC_INS_QVFNABS = 887 , PPC_INS_QVFNAND = 888 , PPC_INS_QVFNEG = 889 , PPC_INS_QVFNMADD = 890 , PPC_INS_QVFNMADDS = 891 , PPC_INS_QVFNMSUB = 892 , PPC_INS_QVFNMSUBS = 893 , PPC_INS_QVFNOR = 894 , PPC_INS_QVFNOT = 895 , PPC_INS_QVFOR = 896 , PPC_INS_QVFORC = 897 , PPC_INS_QVFPERM = 898 , PPC_INS_QVFRE = 899 , PPC_INS_QVFRES = 900 , PPC_INS_QVFRIM = 901 , PPC_INS_QVFRIN = 902 , PPC_INS_QVFRIP = 903 , PPC_INS_QVFRIZ = 904 , PPC_INS_QVFRSP = 905 , PPC_INS_QVFRSQRTE = 906 , PPC_INS_QVFRSQRTES = 907 , PPC_INS_QVFSEL = 908 , PPC_INS_QVFSET = 909 , PPC_INS_QVFSUB = 910 , PPC_INS_QVFSUBS = 911 , PPC_INS_QVFTSTNAN = 912 , PPC_INS_QVFXMADD = 913 , PPC_INS_QVFXMADDS = 914 , PPC_INS_QVFXMUL = 915 , PPC_INS_QVFXMULS = 916 , PPC_INS_QVFXOR = 917 , PPC_INS_QVFXXCPNMADD = 918 , PPC_INS_QVFXXCPNMADDS = 919 , PPC_INS_QVFXXMADD = 920 , PPC_INS_QVFXXMADDS = 921 , PPC_INS_QVFXXNPMADD = 922 , PPC_INS_QVFXXNPMADDS = 923 , PPC_INS_QVGPCI = 924 , PPC_INS_QVLFCDUX = 925 , PPC_INS_QVLFCDUXA = 926 , PPC_INS_QVLFCDX = 927 , PPC_INS_QVLFCDXA = 928 , PPC_INS_QVLFCSUX = 929 , PPC_INS_QVLFCSUXA = 930 , PPC_INS_QVLFCSX = 931 , PPC_INS_QVLFCSXA = 932 , PPC_INS_QVLFDUX = 933 , PPC_INS_QVLFDUXA = 934 , PPC_INS_QVLFDX = 935 , PPC_INS_QVLFDXA = 936 , PPC_INS_QVLFIWAX = 937 , PPC_INS_QVLFIWAXA = 938 , PPC_INS_QVLFIWZX = 939 , PPC_INS_QVLFIWZXA = 940 , PPC_INS_QVLFSUX = 941 , PPC_INS_QVLFSUXA = 942 , PPC_INS_QVLFSX = 943 , PPC_INS_QVLFSXA = 944 , PPC_INS_QVLPCLDX = 945 , PPC_INS_QVLPCLSX = 946 , PPC_INS_QVLPCRDX = 947 , PPC_INS_QVLPCRSX = 948 , PPC_INS_QVSTFCDUX = 949 , PPC_INS_QVSTFCDUXA = 950 , PPC_INS_QVSTFCDUXI = 951 , PPC_INS_QVSTFCDUXIA = 952 , PPC_INS_QVSTFCDX = 953 , PPC_INS_QVSTFCDXA = 954 , PPC_INS_QVSTFCDXI = 955 , PPC_INS_QVSTFCDXIA = 956 , PPC_INS_QVSTFCSUX = 957 , PPC_INS_QVSTFCSUXA = 958 , PPC_INS_QVSTFCSUXI = 959 , PPC_INS_QVSTFCSUXIA = 960 , PPC_INS_QVSTFCSX = 961 , PPC_INS_QVSTFCSXA = 962 , PPC_INS_QVSTFCSXI = 963 , PPC_INS_QVSTFCSXIA = 964 , PPC_INS_QVSTFDUX = 965 , PPC_INS_QVSTFDUXA = 966 , PPC_INS_QVSTFDUXI = 967 , PPC_INS_QVSTFDUXIA = 968 , PPC_INS_QVSTFDX = 969 , PPC_INS_QVSTFDXA = 970 , PPC_INS_QVSTFDXI = 971 , PPC_INS_QVSTFDXIA = 972 , PPC_INS_QVSTFIWX = 973 , PPC_INS_QVSTFIWXA = 974 , PPC_INS_QVSTFSUX = 975 , PPC_INS_QVSTFSUXA = 976 , PPC_INS_QVSTFSUXI = 977 , PPC_INS_QVSTFSUXIA = 978 , PPC_INS_QVSTFSX = 979 , PPC_INS_QVSTFSXA = 980 , PPC_INS_QVSTFSXI = 981 , PPC_INS_QVSTFSXIA = 982 , PPC_INS_RFCI = 983 , PPC_INS_RFDI = 984 , PPC_INS_RFEBB = 985 , PPC_INS_RFI = 986 , PPC_INS_RFID = 987 , PPC_INS_RFMCI = 988 , PPC_INS_RLDCL = 989 , PPC_INS_RLDCR = 990 , PPC_INS_RLDIC = 991 , PPC_INS_RLDICL = 992 , PPC_INS_RLDICR = 993 , PPC_INS_RLDIMI = 994 , PPC_INS_RLWIMI = 995 , PPC_INS_RLWINM = 996 , PPC_INS_RLWNM = 997 , PPC_INS_ROTLD = 998 , PPC_INS_ROTLDI = 999 , PPC_INS_ROTLW = 1000 , PPC_INS_ROTLWI = 1001 , PPC_INS_ROTRDI = 1002 , PPC_INS_ROTRWI = 1003 , PPC_INS_SC = 1004 , PPC_INS_SETB = 1005 , PPC_INS_SLBIA = 1006 , PPC_INS_SLBIE = 1007 , PPC_INS_SLBIEG = 1008 , PPC_INS_SLBMFEE = 1009 , PPC_INS_SLBMFEV = 1010 , PPC_INS_SLBMTE = 1011 , PPC_INS_SLBSYNC = 1012 , PPC_INS_SLD = 1013 , PPC_INS_SLDI = 1014 , PPC_INS_SLW = 1015 , PPC_INS_SLWI = 1016 , PPC_INS_SRAD = 1017 , PPC_INS_SRADI = 1018 , PPC_INS_SRAW = 1019 , PPC_INS_SRAWI = 1020 , PPC_INS_SRD = 1021 , PPC_INS_SRDI = 1022 , PPC_INS_SRW = 1023 , PPC_INS_SRWI = 1024 , PPC_INS_STB = 1025 , PPC_INS_STBCIX = 1026 , PPC_INS_STBCX = 1027 , PPC_INS_STBEPX = 1028 , PPC_INS_STBU = 1029 , PPC_INS_STBUX = 1030 , PPC_INS_STBX = 1031 , PPC_INS_STD = 1032 , PPC_INS_STDAT = 1033 , PPC_INS_STDBRX = 1034 , PPC_INS_STDCIX = 1035 , PPC_INS_STDCX = 1036 , PPC_INS_STDU = 1037 , PPC_INS_STDUX = 1038 , PPC_INS_STDX = 1039 , PPC_INS_STFD = 1040 , PPC_INS_STFDEPX = 1041 , PPC_INS_STFDU = 1042 , PPC_INS_STFDUX = 1043 , PPC_INS_STFDX = 1044 , PPC_INS_STFIWX = 1045 , PPC_INS_STFS = 1046 , PPC_INS_STFSU = 1047 , PPC_INS_STFSUX = 1048 , PPC_INS_STFSX = 1049 , PPC_INS_STH = 1050 , PPC_INS_STHBRX = 1051 , PPC_INS_STHCIX = 1052 , PPC_INS_STHCX = 1053 , PPC_INS_STHEPX = 1054 , PPC_INS_STHU = 1055 , PPC_INS_STHUX = 1056 , PPC_INS_STHX = 1057 , PPC_INS_STMW = 1058 , PPC_INS_STOP = 1059 , PPC_INS_STSWI = 1060 , PPC_INS_STVEBX = 1061 , PPC_INS_STVEHX = 1062 , PPC_INS_STVEWX = 1063 , PPC_INS_STVX = 1064 , PPC_INS_STVXL = 1065 , PPC_INS_STW = 1066 , PPC_INS_STWAT = 1067 , PPC_INS_STWBRX = 1068 , PPC_INS_STWCIX = 1069 , PPC_INS_STWCX = 1070 , PPC_INS_STWEPX = 1071 , PPC_INS_STWU = 1072 , PPC_INS_STWUX = 1073 , PPC_INS_STWX = 1074 , PPC_INS_STXSD = 1075 , PPC_INS_STXSDX = 1076 , PPC_INS_STXSIBX = 1077 , PPC_INS_STXSIHX = 1078 , PPC_INS_STXSIWX = 1079 , PPC_INS_STXSSP = 1080 , PPC_INS_STXSSPX = 1081 , PPC_INS_STXV = 1082 , PPC_INS_STXVB16X = 1083 , PPC_INS_STXVD2X = 1084 , PPC_INS_STXVH8X = 1085 , PPC_INS_STXVL = 1086 , PPC_INS_STXVLL = 1087 , PPC_INS_STXVW4X = 1088 , PPC_INS_STXVX = 1089 , PPC_INS_SUB = 1090 , PPC_INS_SUBC = 1091 , PPC_INS_SUBF = 1092 , PPC_INS_SUBFC = 1093 , PPC_INS_SUBFE = 1094 , PPC_INS_SUBFIC = 1095 , PPC_INS_SUBFME = 1096 , PPC_INS_SUBFZE = 1097 , PPC_INS_SUBI = 1098 , PPC_INS_SUBIC = 1099 , PPC_INS_SUBIS = 1100 , PPC_INS_SUBPCIS = 1101 , PPC_INS_SYNC = 1102 , PPC_INS_TABORT = 1103 , PPC_INS_TABORTDC = 1104 , PPC_INS_TABORTDCI = 1105 , PPC_INS_TABORTWC = 1106 , PPC_INS_TABORTWCI = 1107 , PPC_INS_TBEGIN = 1108 , PPC_INS_TCHECK = 1109 , PPC_INS_TD = 1110 , PPC_INS_TDEQ = 1111 , PPC_INS_TDEQI = 1112 , PPC_INS_TDGE = 1113 , PPC_INS_TDGEI = 1114 , PPC_INS_TDGT = 1115 , PPC_INS_TDGTI = 1116 , PPC_INS_TDI = 1117 , PPC_INS_TDLE = 1118 , PPC_INS_TDLEI = 1119 , PPC_INS_TDLGE = 1120 , PPC_INS_TDLGEI = 1121 , PPC_INS_TDLGT = 1122 , PPC_INS_TDLGTI = 1123 , PPC_INS_TDLLE = 1124 , PPC_INS_TDLLEI = 1125 , PPC_INS_TDLLT = 1126 , PPC_INS_TDLLTI = 1127 , PPC_INS_TDLNG = 1128 , PPC_INS_TDLNGI = 1129 , PPC_INS_TDLNL = 1130 , PPC_INS_TDLNLI = 1131 , PPC_INS_TDLT = 1132 , PPC_INS_TDLTI = 1133 , PPC_INS_TDNE = 1134 , PPC_INS_TDNEI = 1135 , PPC_INS_TDNG = 1136 , PPC_INS_TDNGI = 1137 , PPC_INS_TDNL = 1138 , PPC_INS_TDNLI = 1139 , PPC_INS_TDU = 1140 , PPC_INS_TDUI = 1141 , PPC_INS_TEND = 1142 , PPC_INS_TLBIA = 1143 , PPC_INS_TLBIE = 1144 , PPC_INS_TLBIEL = 1145 , PPC_INS_TLBIVAX = 1146 , PPC_INS_TLBLD = 1147 , PPC_INS_TLBLI = 1148 , PPC_INS_TLBRE = 1149 , PPC_INS_TLBREHI = 1150 , PPC_INS_TLBRELO = 1151 , PPC_INS_TLBSX = 1152 , PPC_INS_TLBSYNC = 1153 , PPC_INS_TLBWE = 1154 , PPC_INS_TLBWEHI = 1155 , PPC_INS_TLBWELO = 1156 , PPC_INS_TRAP = 1157 , PPC_INS_TRECHKPT = 1158 , PPC_INS_TRECLAIM = 1159 , PPC_INS_TSR = 1160 , PPC_INS_TW = 1161 , PPC_INS_TWEQ = 1162 , PPC_INS_TWEQI = 1163 , PPC_INS_TWGE = 1164 , PPC_INS_TWGEI = 1165 , PPC_INS_TWGT = 1166 , PPC_INS_TWGTI = 1167 , PPC_INS_TWI = 1168 , PPC_INS_TWLE = 1169 , PPC_INS_TWLEI = 1170 , PPC_INS_TWLGE = 1171 , PPC_INS_TWLGEI = 1172 , PPC_INS_TWLGT = 1173 , PPC_INS_TWLGTI = 1174 , PPC_INS_TWLLE = 1175 , PPC_INS_TWLLEI = 1176 , PPC_INS_TWLLT = 1177 , PPC_INS_TWLLTI = 1178 , PPC_INS_TWLNG = 1179 , PPC_INS_TWLNGI = 1180 , PPC_INS_TWLNL = 1181 , PPC_INS_TWLNLI = 1182 , PPC_INS_TWLT = 1183 , PPC_INS_TWLTI = 1184 , PPC_INS_TWNE = 1185 , PPC_INS_TWNEI = 1186 , PPC_INS_TWNG = 1187 , PPC_INS_TWNGI = 1188 , PPC_INS_TWNL = 1189 , PPC_INS_TWNLI = 1190 , PPC_INS_TWU = 1191 , PPC_INS_TWUI = 1192 , PPC_INS_VABSDUB = 1193 , PPC_INS_VABSDUH = 1194 , PPC_INS_VABSDUW = 1195 , PPC_INS_VADDCUQ = 1196 , PPC_INS_VADDCUW = 1197 , PPC_INS_VADDECUQ = 1198 , PPC_INS_VADDEUQM = 1199 , PPC_INS_VADDFP = 1200 , PPC_INS_VADDSBS = 1201 , PPC_INS_VADDSHS = 1202 , PPC_INS_VADDSWS = 1203 , PPC_INS_VADDUBM = 1204 , PPC_INS_VADDUBS = 1205 , PPC_INS_VADDUDM = 1206 , PPC_INS_VADDUHM = 1207 , PPC_INS_VADDUHS = 1208 , PPC_INS_VADDUQM = 1209 , PPC_INS_VADDUWM = 1210 , PPC_INS_VADDUWS = 1211 , PPC_INS_VAND = 1212 , PPC_INS_VANDC = 1213 , PPC_INS_VAVGSB = 1214 , PPC_INS_VAVGSH = 1215 , PPC_INS_VAVGSW = 1216 , PPC_INS_VAVGUB = 1217 , PPC_INS_VAVGUH = 1218 , PPC_INS_VAVGUW = 1219 , PPC_INS_VBPERMD = 1220 , PPC_INS_VBPERMQ = 1221 , PPC_INS_VCFSX = 1222 , PPC_INS_VCFUX = 1223 , PPC_INS_VCIPHER = 1224 , PPC_INS_VCIPHERLAST = 1225 , PPC_INS_VCLZB = 1226 , PPC_INS_VCLZD = 1227 , PPC_INS_VCLZH = 1228 , PPC_INS_VCLZLSBB = 1229 , PPC_INS_VCLZW = 1230 , PPC_INS_VCMPBFP = 1231 , PPC_INS_VCMPEQFP = 1232 , PPC_INS_VCMPEQUB = 1233 , PPC_INS_VCMPEQUD = 1234 , PPC_INS_VCMPEQUH = 1235 , PPC_INS_VCMPEQUW = 1236 , PPC_INS_VCMPGEFP = 1237 , PPC_INS_VCMPGTFP = 1238 , PPC_INS_VCMPGTSB = 1239 , PPC_INS_VCMPGTSD = 1240 , PPC_INS_VCMPGTSH = 1241 , PPC_INS_VCMPGTSW = 1242 , PPC_INS_VCMPGTUB = 1243 , PPC_INS_VCMPGTUD = 1244 , PPC_INS_VCMPGTUH = 1245 , PPC_INS_VCMPGTUW = 1246 , PPC_INS_VCMPNEB = 1247 , PPC_INS_VCMPNEH = 1248 , PPC_INS_VCMPNEW = 1249 , PPC_INS_VCMPNEZB = 1250 , PPC_INS_VCMPNEZH = 1251 , PPC_INS_VCMPNEZW = 1252 , PPC_INS_VCTSXS = 1253 , PPC_INS_VCTUXS = 1254 , PPC_INS_VCTZB = 1255 , PPC_INS_VCTZD = 1256 , PPC_INS_VCTZH = 1257 , PPC_INS_VCTZLSBB = 1258 , PPC_INS_VCTZW = 1259 , PPC_INS_VEQV = 1260 , PPC_INS_VEXPTEFP = 1261 , PPC_INS_VEXTRACTD = 1262 , PPC_INS_VEXTRACTUB = 1263 , PPC_INS_VEXTRACTUH = 1264 , PPC_INS_VEXTRACTUW = 1265 , PPC_INS_VEXTSB2D = 1266 , PPC_INS_VEXTSB2W = 1267 , PPC_INS_VEXTSH2D = 1268 , PPC_INS_VEXTSH2W = 1269 , PPC_INS_VEXTSW2D = 1270 , PPC_INS_VEXTUBLX = 1271 , PPC_INS_VEXTUBRX = 1272 , PPC_INS_VEXTUHLX = 1273 , PPC_INS_VEXTUHRX = 1274 , PPC_INS_VEXTUWLX = 1275 , PPC_INS_VEXTUWRX = 1276 , PPC_INS_VGBBD = 1277 , PPC_INS_VINSERTB = 1278 , PPC_INS_VINSERTD = 1279 , PPC_INS_VINSERTH = 1280 , PPC_INS_VINSERTW = 1281 , PPC_INS_VLOGEFP = 1282 , PPC_INS_VMADDFP = 1283 , PPC_INS_VMAXFP = 1284 , PPC_INS_VMAXSB = 1285 , PPC_INS_VMAXSD = 1286 , PPC_INS_VMAXSH = 1287 , PPC_INS_VMAXSW = 1288 , PPC_INS_VMAXUB = 1289 , PPC_INS_VMAXUD = 1290 , PPC_INS_VMAXUH = 1291 , PPC_INS_VMAXUW = 1292 , PPC_INS_VMHADDSHS = 1293 , PPC_INS_VMHRADDSHS = 1294 , PPC_INS_VMINFP = 1295 , PPC_INS_VMINSB = 1296 , PPC_INS_VMINSD = 1297 , PPC_INS_VMINSH = 1298 , PPC_INS_VMINSW = 1299 , PPC_INS_VMINUB = 1300 , PPC_INS_VMINUD = 1301 , PPC_INS_VMINUH = 1302 , PPC_INS_VMINUW = 1303 , PPC_INS_VMLADDUHM = 1304 , PPC_INS_VMR = 1305 , PPC_INS_VMRGEW = 1306 , PPC_INS_VMRGHB = 1307 , PPC_INS_VMRGHH = 1308 , PPC_INS_VMRGHW = 1309 , PPC_INS_VMRGLB = 1310 , PPC_INS_VMRGLH = 1311 , PPC_INS_VMRGLW = 1312 , PPC_INS_VMRGOW = 1313 , PPC_INS_VMSUMMBM = 1314 , PPC_INS_VMSUMSHM = 1315 , PPC_INS_VMSUMSHS = 1316 , PPC_INS_VMSUMUBM = 1317 , PPC_INS_VMSUMUHM = 1318 , PPC_INS_VMSUMUHS = 1319 , PPC_INS_VMUL10CUQ = 1320 , PPC_INS_VMUL10ECUQ = 1321 , PPC_INS_VMUL10EUQ = 1322 , PPC_INS_VMUL10UQ = 1323 , PPC_INS_VMULESB = 1324 , PPC_INS_VMULESH = 1325 , PPC_INS_VMULESW = 1326 , PPC_INS_VMULEUB = 1327 , PPC_INS_VMULEUH = 1328 , PPC_INS_VMULEUW = 1329 , PPC_INS_VMULOSB = 1330 , PPC_INS_VMULOSH = 1331 , PPC_INS_VMULOSW = 1332 , PPC_INS_VMULOUB = 1333 , PPC_INS_VMULOUH = 1334 , PPC_INS_VMULOUW = 1335 , PPC_INS_VMULUWM = 1336 , PPC_INS_VNAND = 1337 , PPC_INS_VNCIPHER = 1338 , PPC_INS_VNCIPHERLAST = 1339 , PPC_INS_VNEGD = 1340 , PPC_INS_VNEGW = 1341 , PPC_INS_VNMSUBFP = 1342 , PPC_INS_VNOR = 1343 , PPC_INS_VNOT = 1344 , PPC_INS_VOR = 1345 , PPC_INS_VORC = 1346 , PPC_INS_VPERM = 1347 , PPC_INS_VPERMR = 1348 , PPC_INS_VPERMXOR = 1349 , PPC_INS_VPKPX = 1350 , PPC_INS_VPKSDSS = 1351 , PPC_INS_VPKSDUS = 1352 , PPC_INS_VPKSHSS = 1353 , PPC_INS_VPKSHUS = 1354 , PPC_INS_VPKSWSS = 1355 , PPC_INS_VPKSWUS = 1356 , PPC_INS_VPKUDUM = 1357 , PPC_INS_VPKUDUS = 1358 , PPC_INS_VPKUHUM = 1359 , PPC_INS_VPKUHUS = 1360 , PPC_INS_VPKUWUM = 1361 , PPC_INS_VPKUWUS = 1362 , PPC_INS_VPMSUMB = 1363 , PPC_INS_VPMSUMD = 1364 , PPC_INS_VPMSUMH = 1365 , PPC_INS_VPMSUMW = 1366 , PPC_INS_VPOPCNTB = 1367 , PPC_INS_VPOPCNTD = 1368 , PPC_INS_VPOPCNTH = 1369 , PPC_INS_VPOPCNTW = 1370 , PPC_INS_VPRTYBD = 1371 , PPC_INS_VPRTYBQ = 1372 , PPC_INS_VPRTYBW = 1373 , PPC_INS_VREFP = 1374 , PPC_INS_VRFIM = 1375 , PPC_INS_VRFIN = 1376 , PPC_INS_VRFIP = 1377 , PPC_INS_VRFIZ = 1378 , PPC_INS_VRLB = 1379 , PPC_INS_VRLD = 1380 , PPC_INS_VRLDMI = 1381 , PPC_INS_VRLDNM = 1382 , PPC_INS_VRLH = 1383 , PPC_INS_VRLW = 1384 , PPC_INS_VRLWMI = 1385 , PPC_INS_VRLWNM = 1386 , PPC_INS_VRSQRTEFP = 1387 , PPC_INS_VSBOX = 1388 , PPC_INS_VSEL = 1389 , PPC_INS_VSHASIGMAD = 1390 , PPC_INS_VSHASIGMAW = 1391 , PPC_INS_VSL = 1392 , PPC_INS_VSLB = 1393 , PPC_INS_VSLD = 1394 , PPC_INS_VSLDOI = 1395 , PPC_INS_VSLH = 1396 , PPC_INS_VSLO = 1397 , PPC_INS_VSLV = 1398 , PPC_INS_VSLW = 1399 , PPC_INS_VSPLTB = 1400 , PPC_INS_VSPLTH = 1401 , PPC_INS_VSPLTISB = 1402 , PPC_INS_VSPLTISH = 1403 , PPC_INS_VSPLTISW = 1404 , PPC_INS_VSPLTW = 1405 , PPC_INS_VSR = 1406 , PPC_INS_VSRAB = 1407 , PPC_INS_VSRAD = 1408 , PPC_INS_VSRAH = 1409 , PPC_INS_VSRAW = 1410 , PPC_INS_VSRB = 1411 , PPC_INS_VSRD = 1412 , PPC_INS_VSRH = 1413 , PPC_INS_VSRO = 1414 , PPC_INS_VSRV = 1415 , PPC_INS_VSRW = 1416 , PPC_INS_VSUBCUQ = 1417 , PPC_INS_VSUBCUW = 1418 , PPC_INS_VSUBECUQ = 1419 , PPC_INS_VSUBEUQM = 1420 , PPC_INS_VSUBFP = 1421 , PPC_INS_VSUBSBS = 1422 , PPC_INS_VSUBSHS = 1423 , PPC_INS_VSUBSWS = 1424 , PPC_INS_VSUBUBM = 1425 , PPC_INS_VSUBUBS = 1426 , PPC_INS_VSUBUDM = 1427 , PPC_INS_VSUBUHM = 1428 , PPC_INS_VSUBUHS = 1429 , PPC_INS_VSUBUQM = 1430 , PPC_INS_VSUBUWM = 1431 , PPC_INS_VSUBUWS = 1432 , PPC_INS_VSUM2SWS = 1433 , PPC_INS_VSUM4SBS = 1434 , PPC_INS_VSUM4SHS = 1435 , PPC_INS_VSUM4UBS = 1436 , PPC_INS_VSUMSWS = 1437 , PPC_INS_VUPKHPX = 1438 , PPC_INS_VUPKHSB = 1439 , PPC_INS_VUPKHSH = 1440 , PPC_INS_VUPKHSW = 1441 , PPC_INS_VUPKLPX = 1442 , PPC_INS_VUPKLSB = 1443 , PPC_INS_VUPKLSH = 1444 , PPC_INS_VUPKLSW = 1445 , PPC_INS_VXOR = 1446 , PPC_INS_WAIT = 1447 , PPC_INS_WAITIMPL = 1448 , PPC_INS_WAITRSV = 1449 , PPC_INS_WRTEE = 1450 , PPC_INS_WRTEEI = 1451 , PPC_INS_XNOP = 1452 , PPC_INS_XOR = 1453 , PPC_INS_XORI = 1454 , PPC_INS_XORIS = 1455 , PPC_INS_XSABSDP = 1456 , PPC_INS_XSABSQP = 1457 , PPC_INS_XSADDDP = 1458 , PPC_INS_XSADDQP = 1459 , PPC_INS_XSADDQPO = 1460 , PPC_INS_XSADDSP = 1461 , PPC_INS_XSCMPEQDP = 1462 , PPC_INS_XSCMPEXPDP = 1463 , PPC_INS_XSCMPEXPQP = 1464 , PPC_INS_XSCMPGEDP = 1465 , PPC_INS_XSCMPGTDP = 1466 , PPC_INS_XSCMPODP = 1467 , PPC_INS_XSCMPOQP = 1468 , PPC_INS_XSCMPUDP = 1469 , PPC_INS_XSCMPUQP = 1470 , PPC_INS_XSCPSGNDP = 1471 , PPC_INS_XSCPSGNQP = 1472 , PPC_INS_XSCVDPHP = 1473 , PPC_INS_XSCVDPQP = 1474 , PPC_INS_XSCVDPSP = 1475 , PPC_INS_XSCVDPSPN = 1476 , PPC_INS_XSCVDPSXDS = 1477 , PPC_INS_XSCVDPSXWS = 1478 , PPC_INS_XSCVDPUXDS = 1479 , PPC_INS_XSCVDPUXWS = 1480 , PPC_INS_XSCVHPDP = 1481 , PPC_INS_XSCVQPDP = 1482 , PPC_INS_XSCVQPDPO = 1483 , PPC_INS_XSCVQPSDZ = 1484 , PPC_INS_XSCVQPSWZ = 1485 , PPC_INS_XSCVQPUDZ = 1486 , PPC_INS_XSCVQPUWZ = 1487 , PPC_INS_XSCVSDQP = 1488 , PPC_INS_XSCVSPDP = 1489 , PPC_INS_XSCVSPDPN = 1490 , PPC_INS_XSCVSXDDP = 1491 , PPC_INS_XSCVSXDSP = 1492 , PPC_INS_XSCVUDQP = 1493 , PPC_INS_XSCVUXDDP = 1494 , PPC_INS_XSCVUXDSP = 1495 , PPC_INS_XSDIVDP = 1496 , PPC_INS_XSDIVQP = 1497 , PPC_INS_XSDIVQPO = 1498 , PPC_INS_XSDIVSP = 1499 , PPC_INS_XSIEXPDP = 1500 , PPC_INS_XSIEXPQP = 1501 , PPC_INS_XSMADDADP = 1502 , PPC_INS_XSMADDASP = 1503 , PPC_INS_XSMADDMDP = 1504 , PPC_INS_XSMADDMSP = 1505 , PPC_INS_XSMADDQP = 1506 , PPC_INS_XSMADDQPO = 1507 , PPC_INS_XSMAXCDP = 1508 , PPC_INS_XSMAXDP = 1509 , PPC_INS_XSMAXJDP = 1510 , PPC_INS_XSMINCDP = 1511 , PPC_INS_XSMINDP = 1512 , PPC_INS_XSMINJDP = 1513 , PPC_INS_XSMSUBADP = 1514 , PPC_INS_XSMSUBASP = 1515 , PPC_INS_XSMSUBMDP = 1516 , PPC_INS_XSMSUBMSP = 1517 , PPC_INS_XSMSUBQP = 1518 , PPC_INS_XSMSUBQPO = 1519 , PPC_INS_XSMULDP = 1520 , PPC_INS_XSMULQP = 1521 , PPC_INS_XSMULQPO = 1522 , PPC_INS_XSMULSP = 1523 , PPC_INS_XSNABSDP = 1524 , PPC_INS_XSNABSQP = 1525 , PPC_INS_XSNEGDP = 1526 , PPC_INS_XSNEGQP = 1527 , PPC_INS_XSNMADDADP = 1528 , PPC_INS_XSNMADDASP = 1529 , PPC_INS_XSNMADDMDP = 1530 , PPC_INS_XSNMADDMSP = 1531 , PPC_INS_XSNMADDQP = 1532 , PPC_INS_XSNMADDQPO = 1533 , PPC_INS_XSNMSUBADP = 1534 , PPC_INS_XSNMSUBASP = 1535 , PPC_INS_XSNMSUBMDP = 1536 , PPC_INS_XSNMSUBMSP = 1537 , PPC_INS_XSNMSUBQP = 1538 , PPC_INS_XSNMSUBQPO = 1539 , PPC_INS_XSRDPI = 1540 , PPC_INS_XSRDPIC = 1541 , PPC_INS_XSRDPIM = 1542 , PPC_INS_XSRDPIP = 1543 , PPC_INS_XSRDPIZ = 1544 , PPC_INS_XSREDP = 1545 , PPC_INS_XSRESP = 1546 , PPC_INS_XSRQPI = 1547 , PPC_INS_XSRQPIX = 1548 , PPC_INS_XSRQPXP = 1549 , PPC_INS_XSRSP = 1550 , PPC_INS_XSRSQRTEDP = 1551 , PPC_INS_XSRSQRTESP = 1552 , PPC_INS_XSSQRTDP = 1553 , PPC_INS_XSSQRTQP = 1554 , PPC_INS_XSSQRTQPO = 1555 , PPC_INS_XSSQRTSP = 1556 , PPC_INS_XSSUBDP = 1557 , PPC_INS_XSSUBQP = 1558 , PPC_INS_XSSUBQPO = 1559 , PPC_INS_XSSUBSP = 1560 , PPC_INS_XSTDIVDP = 1561 , PPC_INS_XSTSQRTDP = 1562 , PPC_INS_XSTSTDCDP = 1563 , PPC_INS_XSTSTDCQP = 1564 , PPC_INS_XSTSTDCSP = 1565 , PPC_INS_XSXEXPDP = 1566 , PPC_INS_XSXEXPQP = 1567 , PPC_INS_XSXSIGDP = 1568 , PPC_INS_XSXSIGQP = 1569 , PPC_INS_XVABSDP = 1570 , PPC_INS_XVABSSP = 1571 , PPC_INS_XVADDDP = 1572 , PPC_INS_XVADDSP = 1573 , PPC_INS_XVCMPEQDP = 1574 , PPC_INS_XVCMPEQSP = 1575 , PPC_INS_XVCMPGEDP = 1576 , PPC_INS_XVCMPGESP = 1577 , PPC_INS_XVCMPGTDP = 1578 , PPC_INS_XVCMPGTSP = 1579 , PPC_INS_XVCPSGNDP = 1580 , PPC_INS_XVCPSGNSP = 1581 , PPC_INS_XVCVDPSP = 1582 , PPC_INS_XVCVDPSXDS = 1583 , PPC_INS_XVCVDPSXWS = 1584 , PPC_INS_XVCVDPUXDS = 1585 , PPC_INS_XVCVDPUXWS = 1586 , PPC_INS_XVCVHPSP = 1587 , PPC_INS_XVCVSPDP = 1588 , PPC_INS_XVCVSPHP = 1589 , PPC_INS_XVCVSPSXDS = 1590 , PPC_INS_XVCVSPSXWS = 1591 , PPC_INS_XVCVSPUXDS = 1592 , PPC_INS_XVCVSPUXWS = 1593 , PPC_INS_XVCVSXDDP = 1594 , PPC_INS_XVCVSXDSP = 1595 , PPC_INS_XVCVSXWDP = 1596 , PPC_INS_XVCVSXWSP = 1597 , PPC_INS_XVCVUXDDP = 1598 , PPC_INS_XVCVUXDSP = 1599 , PPC_INS_XVCVUXWDP = 1600 , PPC_INS_XVCVUXWSP = 1601 , PPC_INS_XVDIVDP = 1602 , PPC_INS_XVDIVSP = 1603 , PPC_INS_XVIEXPDP = 1604 , PPC_INS_XVIEXPSP = 1605 , PPC_INS_XVMADDADP = 1606 , PPC_INS_XVMADDASP = 1607 , PPC_INS_XVMADDMDP = 1608 , PPC_INS_XVMADDMSP = 1609 , PPC_INS_XVMAXDP = 1610 , PPC_INS_XVMAXSP = 1611 , PPC_INS_XVMINDP = 1612 , PPC_INS_XVMINSP = 1613 , PPC_INS_XVMOVDP = 1614 , PPC_INS_XVMOVSP = 1615 , PPC_INS_XVMSUBADP = 1616 , PPC_INS_XVMSUBASP = 1617 , PPC_INS_XVMSUBMDP = 1618 , PPC_INS_XVMSUBMSP = 1619 , PPC_INS_XVMULDP = 1620 , PPC_INS_XVMULSP = 1621 , PPC_INS_XVNABSDP = 1622 , PPC_INS_XVNABSSP = 1623 , PPC_INS_XVNEGDP = 1624 , PPC_INS_XVNEGSP = 1625 , PPC_INS_XVNMADDADP = 1626 , PPC_INS_XVNMADDASP = 1627 , PPC_INS_XVNMADDMDP = 1628 , PPC_INS_XVNMADDMSP = 1629 , PPC_INS_XVNMSUBADP = 1630 , PPC_INS_XVNMSUBASP = 1631 , PPC_INS_XVNMSUBMDP = 1632 , PPC_INS_XVNMSUBMSP = 1633 , PPC_INS_XVRDPI = 1634 , PPC_INS_XVRDPIC = 1635 , PPC_INS_XVRDPIM = 1636 , PPC_INS_XVRDPIP = 1637 , PPC_INS_XVRDPIZ = 1638 , PPC_INS_XVREDP = 1639 , PPC_INS_XVRESP = 1640 , PPC_INS_XVRSPI = 1641 , PPC_INS_XVRSPIC = 1642 , PPC_INS_XVRSPIM = 1643 , PPC_INS_XVRSPIP = 1644 , PPC_INS_XVRSPIZ = 1645 , PPC_INS_XVRSQRTEDP = 1646 , PPC_INS_XVRSQRTESP = 1647 , PPC_INS_XVSQRTDP = 1648 , PPC_INS_XVSQRTSP = 1649 , PPC_INS_XVSUBDP = 1650 , PPC_INS_XVSUBSP = 1651 , PPC_INS_XVTDIVDP = 1652 , PPC_INS_XVTDIVSP = 1653 , PPC_INS_XVTSQRTDP = 1654 , PPC_INS_XVTSQRTSP = 1655 , PPC_INS_XVTSTDCDP = 1656 , PPC_INS_XVTSTDCSP = 1657 , PPC_INS_XVXEXPDP = 1658 , PPC_INS_XVXEXPSP = 1659 , PPC_INS_XVXSIGDP = 1660 , PPC_INS_XVXSIGSP = 1661 , PPC_INS_XXBRD = 1662 , PPC_INS_XXBRH = 1663 , PPC_INS_XXBRQ = 1664 , PPC_INS_XXBRW = 1665 , PPC_INS_XXEXTRACTUW = 1666 , PPC_INS_XXINSERTW = 1667 , PPC_INS_XXLAND = 1668 , PPC_INS_XXLANDC = 1669 , PPC_INS_XXLEQV = 1670 , PPC_INS_XXLNAND = 1671 , PPC_INS_XXLNOR = 1672 , PPC_INS_XXLOR = 1673 , PPC_INS_XXLORC = 1674 , PPC_INS_XXLXOR = 1675 , PPC_INS_XXMRGHD = 1676 , PPC_INS_XXMRGHW = 1677 , PPC_INS_XXMRGLD = 1678 , PPC_INS_XXMRGLW = 1679 , PPC_INS_XXPERM = 1680 , PPC_INS_XXPERMDI = 1681 , PPC_INS_XXPERMR = 1682 , PPC_INS_XXSEL = 1683 , PPC_INS_XXSLDWI = 1684 , PPC_INS_XXSPLTD = 1685 , PPC_INS_XXSPLTIB = 1686 , PPC_INS_XXSPLTW = 1687 , PPC_INS_XXSWAPD = 1688 , PPC_INS_DCBZ_L = 1689 , PPC_INS_PSQ_L = 1690 , PPC_INS_PSQ_LU = 1691 , PPC_INS_PSQ_LUX = 1692 , PPC_INS_PSQ_LX = 1693 , PPC_INS_PSQ_ST = 1694 , PPC_INS_PSQ_STU = 1695 , PPC_INS_PSQ_STUX = 1696 , PPC_INS_PSQ_STX = 1697 , PPC_INS_PS_ABS = 1698 , PPC_INS_PS_ADD = 1699 , PPC_INS_PS_CMPO0 = 1700 , PPC_INS_PS_CMPO1 = 1701 , PPC_INS_PS_CMPU0 = 1702 , PPC_INS_PS_CMPU1 = 1703 , PPC_INS_PS_DIV = 1704 , PPC_INS_PS_MADD = 1705 , PPC_INS_PS_MADDS0 = 1706 , PPC_INS_PS_MADDS1 = 1707 , PPC_INS_PS_MERGE00 = 1708 , PPC_INS_PS_MERGE01 = 1709 , PPC_INS_PS_MERGE10 = 1710 , PPC_INS_PS_MERGE11 = 1711 , PPC_INS_PS_MR = 1712 , PPC_INS_PS_MSUB = 1713 , PPC_INS_PS_MUL = 1714 , PPC_INS_PS_MULS0 = 1715 , PPC_INS_PS_MULS1 = 1716 , PPC_INS_PS_NABS = 1717 , PPC_INS_PS_NEG = 1718 , PPC_INS_PS_NMADD = 1719 , PPC_INS_PS_NMSUB = 1720 , PPC_INS_PS_RES = 1721 , PPC_INS_PS_RSQRTE = 1722 , PPC_INS_PS_SEL = 1723 , PPC_INS_PS_SUB = 1724 , PPC_INS_PS_SUM0 = 1725 , PPC_INS_PS_SUM1 = 1726 , PPC_INS_ENDING = 1727 , } # [repr (u32)] # [doc = " Group of PPC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn_group { # [doc = "< = CS_GRP_INVALID"] PPC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] PPC_GRP_JUMP = 1 , PPC_GRP_ALTIVEC = 128 , PPC_GRP_MODE32 = 129 , PPC_GRP_MODE64 = 130 , PPC_GRP_BOOKE = 131 , PPC_GRP_NOTBOOKE = 132 , PPC_GRP_SPE = 133 , PPC_GRP_VSX = 134 , PPC_GRP_E500 = 135 , PPC_GRP_PPC4XX = 136 , PPC_GRP_PPC6XX = 137 , PPC_GRP_ICBT = 138 , PPC_GRP_P8ALTIVEC = 139 , PPC_GRP_P8VECTOR = 140 , PPC_GRP_QPX = 141 , PPC_GRP_PS = 142 , PPC_GRP_ENDING = 143 , } # [repr (u32)] # [doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_cc { # [doc = "< invalid CC (default)"] SPARC_CC_INVALID = 0 , # [doc = "< Always"] SPARC_CC_ICC_A = 264 , # [doc = "< Never"] SPARC_CC_ICC_N = 256 , # [doc = "< Not Equal"] SPARC_CC_ICC_NE = 265 , # [doc = "< Equal"] SPARC_CC_ICC_E = 257 , # [doc = "< Greater"] SPARC_CC_ICC_G = 266 , # [doc = "< Less or Equal"] SPARC_CC_ICC_LE = 258 , # [doc = "< Greater or Equal"] SPARC_CC_ICC_GE = 267 , # [doc = "< Less"] SPARC_CC_ICC_L = 259 , # [doc = "< Greater Unsigned"] SPARC_CC_ICC_GU = 268 , # [doc = "< Less or Equal Unsigned"] SPARC_CC_ICC_LEU = 260 , # [doc = "< Carry Clear/Great or Equal Unsigned"] SPARC_CC_ICC_CC = 269 , # [doc = "< Carry Set/Less Unsigned"] SPARC_CC_ICC_CS = 261 , # [doc = "< Positive"] SPARC_CC_ICC_POS = 270 , # [doc = "< Negative"] SPARC_CC_ICC_NEG = 262 , # [doc = "< Overflow Clear"] SPARC_CC_ICC_VC = 271 , # [doc = "< Overflow Set"] SPARC_CC_ICC_VS = 263 , # [doc = "< Always"] SPARC_CC_FCC_A = 280 , # [doc = "< Never"] SPARC_CC_FCC_N = 272 , # [doc = "< Unordered"] SPARC_CC_FCC_U = 279 , # [doc = "< Greater"] SPARC_CC_FCC_G = 278 , # [doc = "< Unordered or Greater"] SPARC_CC_FCC_UG = 277 , # [doc = "< Less"] SPARC_CC_FCC_L = 276 , # [doc = "< Unordered or Less"] SPARC_CC_FCC_UL = 275 , # [doc = "< Less or Greater"] SPARC_CC_FCC_LG = 274 , # [doc = "< Not Equal"] SPARC_CC_FCC_NE = 273 , # [doc = "< Equal"] SPARC_CC_FCC_E = 281 , # [doc = "< Unordered or Equal"] SPARC_CC_FCC_UE = 282 , # [doc = "< Greater or Equal"] SPARC_CC_FCC_GE = 283 , # [doc = "< Unordered or Greater or Equal"] SPARC_CC_FCC_UGE = 284 , # [doc = "< Less or Equal"] SPARC_CC_FCC_LE = 285 , # [doc = "< Unordered or Less or Equal"] SPARC_CC_FCC_ULE = 286 , # [doc = "< Ordered"] SPARC_CC_FCC_O = 287 , } # [repr (u32)] # [doc = " Branch hint"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_hint { # [doc = "< no hint"] SPARC_HINT_INVALID = 0 , # [doc = "< annul delay slot instruction"] SPARC_HINT_A = 1 , # [doc = "< branch taken"] SPARC_HINT_PT = 2 , # [doc = "< branch NOT taken"] SPARC_HINT_PN = 4 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SPARC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SPARC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SPARC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SPARC_OP_MEM = 3 , } impl sparc_reg { pub const SPARC_REG_O6 : sparc_reg = sparc_reg :: SPARC_REG_SP ; } impl sparc_reg { pub const SPARC_REG_I6 : sparc_reg = sparc_reg :: SPARC_REG_FP ; } # [repr (u32)] # [doc = " SPARC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_reg { SPARC_REG_INVALID = 0 , SPARC_REG_F0 = 1 , SPARC_REG_F1 = 2 , SPARC_REG_F2 = 3 , SPARC_REG_F3 = 4 , SPARC_REG_F4 = 5 , SPARC_REG_F5 = 6 , SPARC_REG_F6 = 7 , SPARC_REG_F7 = 8 , SPARC_REG_F8 = 9 , SPARC_REG_F9 = 10 , SPARC_REG_F10 = 11 , SPARC_REG_F11 = 12 , SPARC_REG_F12 = 13 , SPARC_REG_F13 = 14 , SPARC_REG_F14 = 15 , SPARC_REG_F15 = 16 , SPARC_REG_F16 = 17 , SPARC_REG_F17 = 18 , SPARC_REG_F18 = 19 , SPARC_REG_F19 = 20 , SPARC_REG_F20 = 21 , SPARC_REG_F21 = 22 , SPARC_REG_F22 = 23 , SPARC_REG_F23 = 24 , SPARC_REG_F24 = 25 , SPARC_REG_F25 = 26 , SPARC_REG_F26 = 27 , SPARC_REG_F27 = 28 , SPARC_REG_F28 = 29 , SPARC_REG_F29 = 30 , SPARC_REG_F30 = 31 , SPARC_REG_F31 = 32 , SPARC_REG_F32 = 33 , SPARC_REG_F34 = 34 , SPARC_REG_F36 = 35 , SPARC_REG_F38 = 36 , SPARC_REG_F40 = 37 , SPARC_REG_F42 = 38 , SPARC_REG_F44 = 39 , SPARC_REG_F46 = 40 , SPARC_REG_F48 = 41 , SPARC_REG_F50 = 42 , SPARC_REG_F52 = 43 , SPARC_REG_F54 = 44 , SPARC_REG_F56 = 45 , SPARC_REG_F58 = 46 , SPARC_REG_F60 = 47 , SPARC_REG_F62 = 48 , SPARC_REG_FCC0 = 49 , SPARC_REG_FCC1 = 50 , SPARC_REG_FCC2 = 51 , SPARC_REG_FCC3 = 52 , SPARC_REG_FP = 53 , SPARC_REG_G0 = 54 , SPARC_REG_G1 = 55 , SPARC_REG_G2 = 56 , SPARC_REG_G3 = 57 , SPARC_REG_G4 = 58 , SPARC_REG_G5 = 59 , SPARC_REG_G6 = 60 , SPARC_REG_G7 = 61 , SPARC_REG_I0 = 62 , SPARC_REG_I1 = 63 , SPARC_REG_I2 = 64 , SPARC_REG_I3 = 65 , SPARC_REG_I4 = 66 , SPARC_REG_I5 = 67 , SPARC_REG_I7 = 68 , SPARC_REG_ICC = 69 , SPARC_REG_L0 = 70 , SPARC_REG_L1 = 71 , SPARC_REG_L2 = 72 , SPARC_REG_L3 = 73 , SPARC_REG_L4 = 74 , SPARC_REG_L5 = 75 , SPARC_REG_L6 = 76 , SPARC_REG_L7 = 77 , SPARC_REG_O0 = 78 , SPARC_REG_O1 = 79 , SPARC_REG_O2 = 80 , SPARC_REG_O3 = 81 , SPARC_REG_O4 = 82 , SPARC_REG_O5 = 83 , SPARC_REG_O7 = 84 , SPARC_REG_SP = 85 , SPARC_REG_Y = 86 , SPARC_REG_XCC = 87 , SPARC_REG_ENDING = 88 , } # [doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sparc_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sparc_op_mem"] [:: std :: mem :: size_of :: < sparc_op_mem > () - 8usize] ; ["Alignment of sparc_op_mem"] [:: std :: mem :: align_of :: < sparc_op_mem > () - 4usize] ; ["Offset of field: sparc_op_mem::base"] [:: std :: mem :: offset_of ! (sparc_op_mem , base) - 0usize] ; ["Offset of field: sparc_op_mem::index"] [:: std :: mem :: offset_of ! (sparc_op_mem , index) - 1usize] ; ["Offset of field: sparc_op_mem::disp"] [:: std :: mem :: offset_of ! (sparc_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc_op { # [doc = "< operand type"] pub type_ : sparc_op_type , pub __bindgen_anon_1 : cs_sparc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sparc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sparc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sparc_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op"] [:: std :: mem :: size_of :: < cs_sparc_op > () - 16usize] ; ["Alignment of cs_sparc_op"] [:: std :: mem :: align_of :: < cs_sparc_op > () - 8usize] ; ["Offset of field: cs_sparc_op::type_"] [:: std :: mem :: offset_of ! (cs_sparc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc { # [doc = "< code condition for this insn"] pub cc : sparc_cc , # [doc = "< branch hint: encoding as bitwise OR of sparc_hint."] pub hint : sparc_hint , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sparc_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc"] [:: std :: mem :: size_of :: < cs_sparc > () - 80usize] ; ["Alignment of cs_sparc"] [:: std :: mem :: align_of :: < cs_sparc > () - 8usize] ; ["Offset of field: cs_sparc::cc"] [:: std :: mem :: offset_of ! (cs_sparc , cc) - 0usize] ; ["Offset of field: cs_sparc::hint"] [:: std :: mem :: offset_of ! (cs_sparc , hint) - 4usize] ; ["Offset of field: cs_sparc::op_count"] [:: std :: mem :: offset_of ! (cs_sparc , op_count) - 8usize] ; ["Offset of field: cs_sparc::operands"] [:: std :: mem :: offset_of ! (cs_sparc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . hint , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SPARC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn { SPARC_INS_INVALID = 0 , SPARC_INS_ADDCC = 1 , SPARC_INS_ADDX = 2 , SPARC_INS_ADDXCC = 3 , SPARC_INS_ADDXC = 4 , SPARC_INS_ADDXCCC = 5 , SPARC_INS_ADD = 6 , SPARC_INS_ALIGNADDR = 7 , SPARC_INS_ALIGNADDRL = 8 , SPARC_INS_ANDCC = 9 , SPARC_INS_ANDNCC = 10 , SPARC_INS_ANDN = 11 , SPARC_INS_AND = 12 , SPARC_INS_ARRAY16 = 13 , SPARC_INS_ARRAY32 = 14 , SPARC_INS_ARRAY8 = 15 , SPARC_INS_B = 16 , SPARC_INS_JMP = 17 , SPARC_INS_BMASK = 18 , SPARC_INS_FB = 19 , SPARC_INS_BRGEZ = 20 , SPARC_INS_BRGZ = 21 , SPARC_INS_BRLEZ = 22 , SPARC_INS_BRLZ = 23 , SPARC_INS_BRNZ = 24 , SPARC_INS_BRZ = 25 , SPARC_INS_BSHUFFLE = 26 , SPARC_INS_CALL = 27 , SPARC_INS_CASX = 28 , SPARC_INS_CAS = 29 , SPARC_INS_CMASK16 = 30 , SPARC_INS_CMASK32 = 31 , SPARC_INS_CMASK8 = 32 , SPARC_INS_CMP = 33 , SPARC_INS_EDGE16 = 34 , SPARC_INS_EDGE16L = 35 , SPARC_INS_EDGE16LN = 36 , SPARC_INS_EDGE16N = 37 , SPARC_INS_EDGE32 = 38 , SPARC_INS_EDGE32L = 39 , SPARC_INS_EDGE32LN = 40 , SPARC_INS_EDGE32N = 41 , SPARC_INS_EDGE8 = 42 , SPARC_INS_EDGE8L = 43 , SPARC_INS_EDGE8LN = 44 , SPARC_INS_EDGE8N = 45 , SPARC_INS_FABSD = 46 , SPARC_INS_FABSQ = 47 , SPARC_INS_FABSS = 48 , SPARC_INS_FADDD = 49 , SPARC_INS_FADDQ = 50 , SPARC_INS_FADDS = 51 , SPARC_INS_FALIGNDATA = 52 , SPARC_INS_FAND = 53 , SPARC_INS_FANDNOT1 = 54 , SPARC_INS_FANDNOT1S = 55 , SPARC_INS_FANDNOT2 = 56 , SPARC_INS_FANDNOT2S = 57 , SPARC_INS_FANDS = 58 , SPARC_INS_FCHKSM16 = 59 , SPARC_INS_FCMPD = 60 , SPARC_INS_FCMPEQ16 = 61 , SPARC_INS_FCMPEQ32 = 62 , SPARC_INS_FCMPGT16 = 63 , SPARC_INS_FCMPGT32 = 64 , SPARC_INS_FCMPLE16 = 65 , SPARC_INS_FCMPLE32 = 66 , SPARC_INS_FCMPNE16 = 67 , SPARC_INS_FCMPNE32 = 68 , SPARC_INS_FCMPQ = 69 , SPARC_INS_FCMPS = 70 , SPARC_INS_FDIVD = 71 , SPARC_INS_FDIVQ = 72 , SPARC_INS_FDIVS = 73 , SPARC_INS_FDMULQ = 74 , SPARC_INS_FDTOI = 75 , SPARC_INS_FDTOQ = 76 , SPARC_INS_FDTOS = 77 , SPARC_INS_FDTOX = 78 , SPARC_INS_FEXPAND = 79 , SPARC_INS_FHADDD = 80 , SPARC_INS_FHADDS = 81 , SPARC_INS_FHSUBD = 82 , SPARC_INS_FHSUBS = 83 , SPARC_INS_FITOD = 84 , SPARC_INS_FITOQ = 85 , SPARC_INS_FITOS = 86 , SPARC_INS_FLCMPD = 87 , SPARC_INS_FLCMPS = 88 , SPARC_INS_FLUSHW = 89 , SPARC_INS_FMEAN16 = 90 , SPARC_INS_FMOVD = 91 , SPARC_INS_FMOVQ = 92 , SPARC_INS_FMOVRDGEZ = 93 , SPARC_INS_FMOVRQGEZ = 94 , SPARC_INS_FMOVRSGEZ = 95 , SPARC_INS_FMOVRDGZ = 96 , SPARC_INS_FMOVRQGZ = 97 , SPARC_INS_FMOVRSGZ = 98 , SPARC_INS_FMOVRDLEZ = 99 , SPARC_INS_FMOVRQLEZ = 100 , SPARC_INS_FMOVRSLEZ = 101 , SPARC_INS_FMOVRDLZ = 102 , SPARC_INS_FMOVRQLZ = 103 , SPARC_INS_FMOVRSLZ = 104 , SPARC_INS_FMOVRDNZ = 105 , SPARC_INS_FMOVRQNZ = 106 , SPARC_INS_FMOVRSNZ = 107 , SPARC_INS_FMOVRDZ = 108 , SPARC_INS_FMOVRQZ = 109 , SPARC_INS_FMOVRSZ = 110 , SPARC_INS_FMOVS = 111 , SPARC_INS_FMUL8SUX16 = 112 , SPARC_INS_FMUL8ULX16 = 113 , SPARC_INS_FMUL8X16 = 114 , SPARC_INS_FMUL8X16AL = 115 , SPARC_INS_FMUL8X16AU = 116 , SPARC_INS_FMULD = 117 , SPARC_INS_FMULD8SUX16 = 118 , SPARC_INS_FMULD8ULX16 = 119 , SPARC_INS_FMULQ = 120 , SPARC_INS_FMULS = 121 , SPARC_INS_FNADDD = 122 , SPARC_INS_FNADDS = 123 , SPARC_INS_FNAND = 124 , SPARC_INS_FNANDS = 125 , SPARC_INS_FNEGD = 126 , SPARC_INS_FNEGQ = 127 , SPARC_INS_FNEGS = 128 , SPARC_INS_FNHADDD = 129 , SPARC_INS_FNHADDS = 130 , SPARC_INS_FNOR = 131 , SPARC_INS_FNORS = 132 , SPARC_INS_FNOT1 = 133 , SPARC_INS_FNOT1S = 134 , SPARC_INS_FNOT2 = 135 , SPARC_INS_FNOT2S = 136 , SPARC_INS_FONE = 137 , SPARC_INS_FONES = 138 , SPARC_INS_FOR = 139 , SPARC_INS_FORNOT1 = 140 , SPARC_INS_FORNOT1S = 141 , SPARC_INS_FORNOT2 = 142 , SPARC_INS_FORNOT2S = 143 , SPARC_INS_FORS = 144 , SPARC_INS_FPACK16 = 145 , SPARC_INS_FPACK32 = 146 , SPARC_INS_FPACKFIX = 147 , SPARC_INS_FPADD16 = 148 , SPARC_INS_FPADD16S = 149 , SPARC_INS_FPADD32 = 150 , SPARC_INS_FPADD32S = 151 , SPARC_INS_FPADD64 = 152 , SPARC_INS_FPMERGE = 153 , SPARC_INS_FPSUB16 = 154 , SPARC_INS_FPSUB16S = 155 , SPARC_INS_FPSUB32 = 156 , SPARC_INS_FPSUB32S = 157 , SPARC_INS_FQTOD = 158 , SPARC_INS_FQTOI = 159 , SPARC_INS_FQTOS = 160 , SPARC_INS_FQTOX = 161 , SPARC_INS_FSLAS16 = 162 , SPARC_INS_FSLAS32 = 163 , SPARC_INS_FSLL16 = 164 , SPARC_INS_FSLL32 = 165 , SPARC_INS_FSMULD = 166 , SPARC_INS_FSQRTD = 167 , SPARC_INS_FSQRTQ = 168 , SPARC_INS_FSQRTS = 169 , SPARC_INS_FSRA16 = 170 , SPARC_INS_FSRA32 = 171 , SPARC_INS_FSRC1 = 172 , SPARC_INS_FSRC1S = 173 , SPARC_INS_FSRC2 = 174 , SPARC_INS_FSRC2S = 175 , SPARC_INS_FSRL16 = 176 , SPARC_INS_FSRL32 = 177 , SPARC_INS_FSTOD = 178 , SPARC_INS_FSTOI = 179 , SPARC_INS_FSTOQ = 180 , SPARC_INS_FSTOX = 181 , SPARC_INS_FSUBD = 182 , SPARC_INS_FSUBQ = 183 , SPARC_INS_FSUBS = 184 , SPARC_INS_FXNOR = 185 , SPARC_INS_FXNORS = 186 , SPARC_INS_FXOR = 187 , SPARC_INS_FXORS = 188 , SPARC_INS_FXTOD = 189 , SPARC_INS_FXTOQ = 190 , SPARC_INS_FXTOS = 191 , SPARC_INS_FZERO = 192 , SPARC_INS_FZEROS = 193 , SPARC_INS_JMPL = 194 , SPARC_INS_LDD = 195 , SPARC_INS_LD = 196 , SPARC_INS_LDQ = 197 , SPARC_INS_LDSB = 198 , SPARC_INS_LDSH = 199 , SPARC_INS_LDSW = 200 , SPARC_INS_LDUB = 201 , SPARC_INS_LDUH = 202 , SPARC_INS_LDX = 203 , SPARC_INS_LZCNT = 204 , SPARC_INS_MEMBAR = 205 , SPARC_INS_MOVDTOX = 206 , SPARC_INS_MOV = 207 , SPARC_INS_MOVRGEZ = 208 , SPARC_INS_MOVRGZ = 209 , SPARC_INS_MOVRLEZ = 210 , SPARC_INS_MOVRLZ = 211 , SPARC_INS_MOVRNZ = 212 , SPARC_INS_MOVRZ = 213 , SPARC_INS_MOVSTOSW = 214 , SPARC_INS_MOVSTOUW = 215 , SPARC_INS_MULX = 216 , SPARC_INS_NOP = 217 , SPARC_INS_ORCC = 218 , SPARC_INS_ORNCC = 219 , SPARC_INS_ORN = 220 , SPARC_INS_OR = 221 , SPARC_INS_PDIST = 222 , SPARC_INS_PDISTN = 223 , SPARC_INS_POPC = 224 , SPARC_INS_RD = 225 , SPARC_INS_RESTORE = 226 , SPARC_INS_RETT = 227 , SPARC_INS_SAVE = 228 , SPARC_INS_SDIVCC = 229 , SPARC_INS_SDIVX = 230 , SPARC_INS_SDIV = 231 , SPARC_INS_SETHI = 232 , SPARC_INS_SHUTDOWN = 233 , SPARC_INS_SIAM = 234 , SPARC_INS_SLLX = 235 , SPARC_INS_SLL = 236 , SPARC_INS_SMULCC = 237 , SPARC_INS_SMUL = 238 , SPARC_INS_SRAX = 239 , SPARC_INS_SRA = 240 , SPARC_INS_SRLX = 241 , SPARC_INS_SRL = 242 , SPARC_INS_STBAR = 243 , SPARC_INS_STB = 244 , SPARC_INS_STD = 245 , SPARC_INS_ST = 246 , SPARC_INS_STH = 247 , SPARC_INS_STQ = 248 , SPARC_INS_STX = 249 , SPARC_INS_SUBCC = 250 , SPARC_INS_SUBX = 251 , SPARC_INS_SUBXCC = 252 , SPARC_INS_SUB = 253 , SPARC_INS_SWAP = 254 , SPARC_INS_TADDCCTV = 255 , SPARC_INS_TADDCC = 256 , SPARC_INS_T = 257 , SPARC_INS_TSUBCCTV = 258 , SPARC_INS_TSUBCC = 259 , SPARC_INS_UDIVCC = 260 , SPARC_INS_UDIVX = 261 , SPARC_INS_UDIV = 262 , SPARC_INS_UMULCC = 263 , SPARC_INS_UMULXHI = 264 , SPARC_INS_UMUL = 265 , SPARC_INS_UNIMP = 266 , SPARC_INS_FCMPED = 267 , SPARC_INS_FCMPEQ = 268 , SPARC_INS_FCMPES = 269 , SPARC_INS_WR = 270 , SPARC_INS_XMULX = 271 , SPARC_INS_XMULXHI = 272 , SPARC_INS_XNORCC = 273 , SPARC_INS_XNOR = 274 , SPARC_INS_XORCC = 275 , SPARC_INS_XOR = 276 , SPARC_INS_RET = 277 , SPARC_INS_RETL = 278 , SPARC_INS_ENDING = 279 , } # [repr (u32)] # [doc = " Group of SPARC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn_group { # [doc = "< = CS_GRP_INVALID"] SPARC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SPARC_GRP_JUMP = 1 , SPARC_GRP_HARDQUAD = 128 , SPARC_GRP_V9 = 129 , SPARC_GRP_VIS = 130 , SPARC_GRP_VIS2 = 131 , SPARC_GRP_VIS3 = 132 , SPARC_GRP_32BIT = 133 , SPARC_GRP_64BIT = 134 , SPARC_GRP_ENDING = 135 , } # [repr (u32)] # [doc = " Enums corresponding to SystemZ condition codes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_cc { # [doc = "< invalid CC (default)"] SYSZ_CC_INVALID = 0 , SYSZ_CC_O = 1 , SYSZ_CC_H = 2 , SYSZ_CC_NLE = 3 , SYSZ_CC_L = 4 , SYSZ_CC_NHE = 5 , SYSZ_CC_LH = 6 , SYSZ_CC_NE = 7 , SYSZ_CC_E = 8 , SYSZ_CC_NLH = 9 , SYSZ_CC_HE = 10 , SYSZ_CC_NL = 11 , SYSZ_CC_LE = 12 , SYSZ_CC_NH = 13 , SYSZ_CC_NO = 14 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SYSZ_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SYSZ_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SYSZ_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SYSZ_OP_MEM = 3 , # [doc = "< Access register operand."] SYSZ_OP_ACREG = 64 , } # [repr (u32)] # [doc = " SystemZ registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_reg { SYSZ_REG_INVALID = 0 , SYSZ_REG_0 = 1 , SYSZ_REG_1 = 2 , SYSZ_REG_2 = 3 , SYSZ_REG_3 = 4 , SYSZ_REG_4 = 5 , SYSZ_REG_5 = 6 , SYSZ_REG_6 = 7 , SYSZ_REG_7 = 8 , SYSZ_REG_8 = 9 , SYSZ_REG_9 = 10 , SYSZ_REG_10 = 11 , SYSZ_REG_11 = 12 , SYSZ_REG_12 = 13 , SYSZ_REG_13 = 14 , SYSZ_REG_14 = 15 , SYSZ_REG_15 = 16 , SYSZ_REG_CC = 17 , SYSZ_REG_F0 = 18 , SYSZ_REG_F1 = 19 , SYSZ_REG_F2 = 20 , SYSZ_REG_F3 = 21 , SYSZ_REG_F4 = 22 , SYSZ_REG_F5 = 23 , SYSZ_REG_F6 = 24 , SYSZ_REG_F7 = 25 , SYSZ_REG_F8 = 26 , SYSZ_REG_F9 = 27 , SYSZ_REG_F10 = 28 , SYSZ_REG_F11 = 29 , SYSZ_REG_F12 = 30 , SYSZ_REG_F13 = 31 , SYSZ_REG_F14 = 32 , SYSZ_REG_F15 = 33 , SYSZ_REG_R0L = 34 , SYSZ_REG_A0 = 35 , SYSZ_REG_A1 = 36 , SYSZ_REG_A2 = 37 , SYSZ_REG_A3 = 38 , SYSZ_REG_A4 = 39 , SYSZ_REG_A5 = 40 , SYSZ_REG_A6 = 41 , SYSZ_REG_A7 = 42 , SYSZ_REG_A8 = 43 , SYSZ_REG_A9 = 44 , SYSZ_REG_A10 = 45 , SYSZ_REG_A11 = 46 , SYSZ_REG_A12 = 47 , SYSZ_REG_A13 = 48 , SYSZ_REG_A14 = 49 , SYSZ_REG_A15 = 50 , SYSZ_REG_C0 = 51 , SYSZ_REG_C1 = 52 , SYSZ_REG_C2 = 53 , SYSZ_REG_C3 = 54 , SYSZ_REG_C4 = 55 , SYSZ_REG_C5 = 56 , SYSZ_REG_C6 = 57 , SYSZ_REG_C7 = 58 , SYSZ_REG_C8 = 59 , SYSZ_REG_C9 = 60 , SYSZ_REG_C10 = 61 , SYSZ_REG_C11 = 62 , SYSZ_REG_C12 = 63 , SYSZ_REG_C13 = 64 , SYSZ_REG_C14 = 65 , SYSZ_REG_C15 = 66 , SYSZ_REG_V0 = 67 , SYSZ_REG_V1 = 68 , SYSZ_REG_V2 = 69 , SYSZ_REG_V3 = 70 , SYSZ_REG_V4 = 71 , SYSZ_REG_V5 = 72 , SYSZ_REG_V6 = 73 , SYSZ_REG_V7 = 74 , SYSZ_REG_V8 = 75 , SYSZ_REG_V9 = 76 , SYSZ_REG_V10 = 77 , SYSZ_REG_V11 = 78 , SYSZ_REG_V12 = 79 , SYSZ_REG_V13 = 80 , SYSZ_REG_V14 = 81 , SYSZ_REG_V15 = 82 , SYSZ_REG_V16 = 83 , SYSZ_REG_V17 = 84 , SYSZ_REG_V18 = 85 , SYSZ_REG_V19 = 86 , SYSZ_REG_V20 = 87 , SYSZ_REG_V21 = 88 , SYSZ_REG_V22 = 89 , SYSZ_REG_V23 = 90 , SYSZ_REG_V24 = 91 , SYSZ_REG_V25 = 92 , SYSZ_REG_V26 = 93 , SYSZ_REG_V27 = 94 , SYSZ_REG_V28 = 95 , SYSZ_REG_V29 = 96 , SYSZ_REG_V30 = 97 , SYSZ_REG_V31 = 98 , SYSZ_REG_F16 = 99 , SYSZ_REG_F17 = 100 , SYSZ_REG_F18 = 101 , SYSZ_REG_F19 = 102 , SYSZ_REG_F20 = 103 , SYSZ_REG_F21 = 104 , SYSZ_REG_F22 = 105 , SYSZ_REG_F23 = 106 , SYSZ_REG_F24 = 107 , SYSZ_REG_F25 = 108 , SYSZ_REG_F26 = 109 , SYSZ_REG_F27 = 110 , SYSZ_REG_F28 = 111 , SYSZ_REG_F29 = 112 , SYSZ_REG_F30 = 113 , SYSZ_REG_F31 = 114 , SYSZ_REG_F0Q = 115 , SYSZ_REG_F4Q = 116 , SYSZ_REG_ENDING = 117 , } # [doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sysz_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< BDLAddr operand"] pub length : u64 , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sysz_op_mem"] [:: std :: mem :: size_of :: < sysz_op_mem > () - 24usize] ; ["Alignment of sysz_op_mem"] [:: std :: mem :: align_of :: < sysz_op_mem > () - 8usize] ; ["Offset of field: sysz_op_mem::base"] [:: std :: mem :: offset_of ! (sysz_op_mem , base) - 0usize] ; ["Offset of field: sysz_op_mem::index"] [:: std :: mem :: offset_of ! (sysz_op_mem , index) - 1usize] ; ["Offset of field: sysz_op_mem::length"] [:: std :: mem :: offset_of ! (sysz_op_mem , length) - 8usize] ; ["Offset of field: sysz_op_mem::disp"] [:: std :: mem :: offset_of ! (sysz_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz_op { # [doc = "< operand type"] pub type_ : sysz_op_type , pub __bindgen_anon_1 : cs_sysz_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sysz_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sysz_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sysz_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sysz_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sysz_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op"] [:: std :: mem :: size_of :: < cs_sysz_op > () - 32usize] ; ["Alignment of cs_sysz_op"] [:: std :: mem :: align_of :: < cs_sysz_op > () - 8usize] ; ["Offset of field: cs_sysz_op::type_"] [:: std :: mem :: offset_of ! (cs_sysz_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz { # [doc = "< Code condition"] pub cc : sysz_cc , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sysz_op ; 6usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz"] [:: std :: mem :: size_of :: < cs_sysz > () - 200usize] ; ["Alignment of cs_sysz"] [:: std :: mem :: align_of :: < cs_sysz > () - 8usize] ; ["Offset of field: cs_sysz::cc"] [:: std :: mem :: offset_of ! (cs_sysz , cc) - 0usize] ; ["Offset of field: cs_sysz::op_count"] [:: std :: mem :: offset_of ! (cs_sysz , op_count) - 4usize] ; ["Offset of field: cs_sysz::operands"] [:: std :: mem :: offset_of ! (cs_sysz , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SystemZ instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn { SYSZ_INS_INVALID = 0 , SYSZ_INS_A = 1 , SYSZ_INS_ADB = 2 , SYSZ_INS_ADBR = 3 , SYSZ_INS_AEB = 4 , SYSZ_INS_AEBR = 5 , SYSZ_INS_AFI = 6 , SYSZ_INS_AG = 7 , SYSZ_INS_AGF = 8 , SYSZ_INS_AGFI = 9 , SYSZ_INS_AGFR = 10 , SYSZ_INS_AGHI = 11 , SYSZ_INS_AGHIK = 12 , SYSZ_INS_AGR = 13 , SYSZ_INS_AGRK = 14 , SYSZ_INS_AGSI = 15 , SYSZ_INS_AH = 16 , SYSZ_INS_AHI = 17 , SYSZ_INS_AHIK = 18 , SYSZ_INS_AHY = 19 , SYSZ_INS_AIH = 20 , SYSZ_INS_AL = 21 , SYSZ_INS_ALC = 22 , SYSZ_INS_ALCG = 23 , SYSZ_INS_ALCGR = 24 , SYSZ_INS_ALCR = 25 , SYSZ_INS_ALFI = 26 , SYSZ_INS_ALG = 27 , SYSZ_INS_ALGF = 28 , SYSZ_INS_ALGFI = 29 , SYSZ_INS_ALGFR = 30 , SYSZ_INS_ALGHSIK = 31 , SYSZ_INS_ALGR = 32 , SYSZ_INS_ALGRK = 33 , SYSZ_INS_ALHSIK = 34 , SYSZ_INS_ALR = 35 , SYSZ_INS_ALRK = 36 , SYSZ_INS_ALY = 37 , SYSZ_INS_AR = 38 , SYSZ_INS_ARK = 39 , SYSZ_INS_ASI = 40 , SYSZ_INS_AXBR = 41 , SYSZ_INS_AY = 42 , SYSZ_INS_BCR = 43 , SYSZ_INS_BRC = 44 , SYSZ_INS_BRCL = 45 , SYSZ_INS_CGIJ = 46 , SYSZ_INS_CGRJ = 47 , SYSZ_INS_CIJ = 48 , SYSZ_INS_CLGIJ = 49 , SYSZ_INS_CLGRJ = 50 , SYSZ_INS_CLIJ = 51 , SYSZ_INS_CLRJ = 52 , SYSZ_INS_CRJ = 53 , SYSZ_INS_BER = 54 , SYSZ_INS_JE = 55 , SYSZ_INS_JGE = 56 , SYSZ_INS_LOCE = 57 , SYSZ_INS_LOCGE = 58 , SYSZ_INS_LOCGRE = 59 , SYSZ_INS_LOCRE = 60 , SYSZ_INS_STOCE = 61 , SYSZ_INS_STOCGE = 62 , SYSZ_INS_BHR = 63 , SYSZ_INS_BHER = 64 , SYSZ_INS_JHE = 65 , SYSZ_INS_JGHE = 66 , SYSZ_INS_LOCHE = 67 , SYSZ_INS_LOCGHE = 68 , SYSZ_INS_LOCGRHE = 69 , SYSZ_INS_LOCRHE = 70 , SYSZ_INS_STOCHE = 71 , SYSZ_INS_STOCGHE = 72 , SYSZ_INS_JH = 73 , SYSZ_INS_JGH = 74 , SYSZ_INS_LOCH = 75 , SYSZ_INS_LOCGH = 76 , SYSZ_INS_LOCGRH = 77 , SYSZ_INS_LOCRH = 78 , SYSZ_INS_STOCH = 79 , SYSZ_INS_STOCGH = 80 , SYSZ_INS_CGIJNLH = 81 , SYSZ_INS_CGRJNLH = 82 , SYSZ_INS_CIJNLH = 83 , SYSZ_INS_CLGIJNLH = 84 , SYSZ_INS_CLGRJNLH = 85 , SYSZ_INS_CLIJNLH = 86 , SYSZ_INS_CLRJNLH = 87 , SYSZ_INS_CRJNLH = 88 , SYSZ_INS_CGIJE = 89 , SYSZ_INS_CGRJE = 90 , SYSZ_INS_CIJE = 91 , SYSZ_INS_CLGIJE = 92 , SYSZ_INS_CLGRJE = 93 , SYSZ_INS_CLIJE = 94 , SYSZ_INS_CLRJE = 95 , SYSZ_INS_CRJE = 96 , SYSZ_INS_CGIJNLE = 97 , SYSZ_INS_CGRJNLE = 98 , SYSZ_INS_CIJNLE = 99 , SYSZ_INS_CLGIJNLE = 100 , SYSZ_INS_CLGRJNLE = 101 , SYSZ_INS_CLIJNLE = 102 , SYSZ_INS_CLRJNLE = 103 , SYSZ_INS_CRJNLE = 104 , SYSZ_INS_CGIJH = 105 , SYSZ_INS_CGRJH = 106 , SYSZ_INS_CIJH = 107 , SYSZ_INS_CLGIJH = 108 , SYSZ_INS_CLGRJH = 109 , SYSZ_INS_CLIJH = 110 , SYSZ_INS_CLRJH = 111 , SYSZ_INS_CRJH = 112 , SYSZ_INS_CGIJNL = 113 , SYSZ_INS_CGRJNL = 114 , SYSZ_INS_CIJNL = 115 , SYSZ_INS_CLGIJNL = 116 , SYSZ_INS_CLGRJNL = 117 , SYSZ_INS_CLIJNL = 118 , SYSZ_INS_CLRJNL = 119 , SYSZ_INS_CRJNL = 120 , SYSZ_INS_CGIJHE = 121 , SYSZ_INS_CGRJHE = 122 , SYSZ_INS_CIJHE = 123 , SYSZ_INS_CLGIJHE = 124 , SYSZ_INS_CLGRJHE = 125 , SYSZ_INS_CLIJHE = 126 , SYSZ_INS_CLRJHE = 127 , SYSZ_INS_CRJHE = 128 , SYSZ_INS_CGIJNHE = 129 , SYSZ_INS_CGRJNHE = 130 , SYSZ_INS_CIJNHE = 131 , SYSZ_INS_CLGIJNHE = 132 , SYSZ_INS_CLGRJNHE = 133 , SYSZ_INS_CLIJNHE = 134 , SYSZ_INS_CLRJNHE = 135 , SYSZ_INS_CRJNHE = 136 , SYSZ_INS_CGIJL = 137 , SYSZ_INS_CGRJL = 138 , SYSZ_INS_CIJL = 139 , SYSZ_INS_CLGIJL = 140 , SYSZ_INS_CLGRJL = 141 , SYSZ_INS_CLIJL = 142 , SYSZ_INS_CLRJL = 143 , SYSZ_INS_CRJL = 144 , SYSZ_INS_CGIJNH = 145 , SYSZ_INS_CGRJNH = 146 , SYSZ_INS_CIJNH = 147 , SYSZ_INS_CLGIJNH = 148 , SYSZ_INS_CLGRJNH = 149 , SYSZ_INS_CLIJNH = 150 , SYSZ_INS_CLRJNH = 151 , SYSZ_INS_CRJNH = 152 , SYSZ_INS_CGIJLE = 153 , SYSZ_INS_CGRJLE = 154 , SYSZ_INS_CIJLE = 155 , SYSZ_INS_CLGIJLE = 156 , SYSZ_INS_CLGRJLE = 157 , SYSZ_INS_CLIJLE = 158 , SYSZ_INS_CLRJLE = 159 , SYSZ_INS_CRJLE = 160 , SYSZ_INS_CGIJNE = 161 , SYSZ_INS_CGRJNE = 162 , SYSZ_INS_CIJNE = 163 , SYSZ_INS_CLGIJNE = 164 , SYSZ_INS_CLGRJNE = 165 , SYSZ_INS_CLIJNE = 166 , SYSZ_INS_CLRJNE = 167 , SYSZ_INS_CRJNE = 168 , SYSZ_INS_CGIJLH = 169 , SYSZ_INS_CGRJLH = 170 , SYSZ_INS_CIJLH = 171 , SYSZ_INS_CLGIJLH = 172 , SYSZ_INS_CLGRJLH = 173 , SYSZ_INS_CLIJLH = 174 , SYSZ_INS_CLRJLH = 175 , SYSZ_INS_CRJLH = 176 , SYSZ_INS_BLR = 177 , SYSZ_INS_BLER = 178 , SYSZ_INS_JLE = 179 , SYSZ_INS_JGLE = 180 , SYSZ_INS_LOCLE = 181 , SYSZ_INS_LOCGLE = 182 , SYSZ_INS_LOCGRLE = 183 , SYSZ_INS_LOCRLE = 184 , SYSZ_INS_STOCLE = 185 , SYSZ_INS_STOCGLE = 186 , SYSZ_INS_BLHR = 187 , SYSZ_INS_JLH = 188 , SYSZ_INS_JGLH = 189 , SYSZ_INS_LOCLH = 190 , SYSZ_INS_LOCGLH = 191 , SYSZ_INS_LOCGRLH = 192 , SYSZ_INS_LOCRLH = 193 , SYSZ_INS_STOCLH = 194 , SYSZ_INS_STOCGLH = 195 , SYSZ_INS_JL = 196 , SYSZ_INS_JGL = 197 , SYSZ_INS_LOCL = 198 , SYSZ_INS_LOCGL = 199 , SYSZ_INS_LOCGRL = 200 , SYSZ_INS_LOCRL = 201 , SYSZ_INS_LOC = 202 , SYSZ_INS_LOCG = 203 , SYSZ_INS_LOCGR = 204 , SYSZ_INS_LOCR = 205 , SYSZ_INS_STOCL = 206 , SYSZ_INS_STOCGL = 207 , SYSZ_INS_BNER = 208 , SYSZ_INS_JNE = 209 , SYSZ_INS_JGNE = 210 , SYSZ_INS_LOCNE = 211 , SYSZ_INS_LOCGNE = 212 , SYSZ_INS_LOCGRNE = 213 , SYSZ_INS_LOCRNE = 214 , SYSZ_INS_STOCNE = 215 , SYSZ_INS_STOCGNE = 216 , SYSZ_INS_BNHR = 217 , SYSZ_INS_BNHER = 218 , SYSZ_INS_JNHE = 219 , SYSZ_INS_JGNHE = 220 , SYSZ_INS_LOCNHE = 221 , SYSZ_INS_LOCGNHE = 222 , SYSZ_INS_LOCGRNHE = 223 , SYSZ_INS_LOCRNHE = 224 , SYSZ_INS_STOCNHE = 225 , SYSZ_INS_STOCGNHE = 226 , SYSZ_INS_JNH = 227 , SYSZ_INS_JGNH = 228 , SYSZ_INS_LOCNH = 229 , SYSZ_INS_LOCGNH = 230 , SYSZ_INS_LOCGRNH = 231 , SYSZ_INS_LOCRNH = 232 , SYSZ_INS_STOCNH = 233 , SYSZ_INS_STOCGNH = 234 , SYSZ_INS_BNLR = 235 , SYSZ_INS_BNLER = 236 , SYSZ_INS_JNLE = 237 , SYSZ_INS_JGNLE = 238 , SYSZ_INS_LOCNLE = 239 , SYSZ_INS_LOCGNLE = 240 , SYSZ_INS_LOCGRNLE = 241 , SYSZ_INS_LOCRNLE = 242 , SYSZ_INS_STOCNLE = 243 , SYSZ_INS_STOCGNLE = 244 , SYSZ_INS_BNLHR = 245 , SYSZ_INS_JNLH = 246 , SYSZ_INS_JGNLH = 247 , SYSZ_INS_LOCNLH = 248 , SYSZ_INS_LOCGNLH = 249 , SYSZ_INS_LOCGRNLH = 250 , SYSZ_INS_LOCRNLH = 251 , SYSZ_INS_STOCNLH = 252 , SYSZ_INS_STOCGNLH = 253 , SYSZ_INS_JNL = 254 , SYSZ_INS_JGNL = 255 , SYSZ_INS_LOCNL = 256 , SYSZ_INS_LOCGNL = 257 , SYSZ_INS_LOCGRNL = 258 , SYSZ_INS_LOCRNL = 259 , SYSZ_INS_STOCNL = 260 , SYSZ_INS_STOCGNL = 261 , SYSZ_INS_BNOR = 262 , SYSZ_INS_JNO = 263 , SYSZ_INS_JGNO = 264 , SYSZ_INS_LOCNO = 265 , SYSZ_INS_LOCGNO = 266 , SYSZ_INS_LOCGRNO = 267 , SYSZ_INS_LOCRNO = 268 , SYSZ_INS_STOCNO = 269 , SYSZ_INS_STOCGNO = 270 , SYSZ_INS_BOR = 271 , SYSZ_INS_JO = 272 , SYSZ_INS_JGO = 273 , SYSZ_INS_LOCO = 274 , SYSZ_INS_LOCGO = 275 , SYSZ_INS_LOCGRO = 276 , SYSZ_INS_LOCRO = 277 , SYSZ_INS_STOCO = 278 , SYSZ_INS_STOCGO = 279 , SYSZ_INS_STOC = 280 , SYSZ_INS_STOCG = 281 , SYSZ_INS_BASR = 282 , SYSZ_INS_BR = 283 , SYSZ_INS_BRAS = 284 , SYSZ_INS_BRASL = 285 , SYSZ_INS_J = 286 , SYSZ_INS_JG = 287 , SYSZ_INS_BRCT = 288 , SYSZ_INS_BRCTG = 289 , SYSZ_INS_C = 290 , SYSZ_INS_CDB = 291 , SYSZ_INS_CDBR = 292 , SYSZ_INS_CDFBR = 293 , SYSZ_INS_CDGBR = 294 , SYSZ_INS_CDLFBR = 295 , SYSZ_INS_CDLGBR = 296 , SYSZ_INS_CEB = 297 , SYSZ_INS_CEBR = 298 , SYSZ_INS_CEFBR = 299 , SYSZ_INS_CEGBR = 300 , SYSZ_INS_CELFBR = 301 , SYSZ_INS_CELGBR = 302 , SYSZ_INS_CFDBR = 303 , SYSZ_INS_CFEBR = 304 , SYSZ_INS_CFI = 305 , SYSZ_INS_CFXBR = 306 , SYSZ_INS_CG = 307 , SYSZ_INS_CGDBR = 308 , SYSZ_INS_CGEBR = 309 , SYSZ_INS_CGF = 310 , SYSZ_INS_CGFI = 311 , SYSZ_INS_CGFR = 312 , SYSZ_INS_CGFRL = 313 , SYSZ_INS_CGH = 314 , SYSZ_INS_CGHI = 315 , SYSZ_INS_CGHRL = 316 , SYSZ_INS_CGHSI = 317 , SYSZ_INS_CGR = 318 , SYSZ_INS_CGRL = 319 , SYSZ_INS_CGXBR = 320 , SYSZ_INS_CH = 321 , SYSZ_INS_CHF = 322 , SYSZ_INS_CHHSI = 323 , SYSZ_INS_CHI = 324 , SYSZ_INS_CHRL = 325 , SYSZ_INS_CHSI = 326 , SYSZ_INS_CHY = 327 , SYSZ_INS_CIH = 328 , SYSZ_INS_CL = 329 , SYSZ_INS_CLC = 330 , SYSZ_INS_CLFDBR = 331 , SYSZ_INS_CLFEBR = 332 , SYSZ_INS_CLFHSI = 333 , SYSZ_INS_CLFI = 334 , SYSZ_INS_CLFXBR = 335 , SYSZ_INS_CLG = 336 , SYSZ_INS_CLGDBR = 337 , SYSZ_INS_CLGEBR = 338 , SYSZ_INS_CLGF = 339 , SYSZ_INS_CLGFI = 340 , SYSZ_INS_CLGFR = 341 , SYSZ_INS_CLGFRL = 342 , SYSZ_INS_CLGHRL = 343 , SYSZ_INS_CLGHSI = 344 , SYSZ_INS_CLGR = 345 , SYSZ_INS_CLGRL = 346 , SYSZ_INS_CLGXBR = 347 , SYSZ_INS_CLHF = 348 , SYSZ_INS_CLHHSI = 349 , SYSZ_INS_CLHRL = 350 , SYSZ_INS_CLI = 351 , SYSZ_INS_CLIH = 352 , SYSZ_INS_CLIY = 353 , SYSZ_INS_CLR = 354 , SYSZ_INS_CLRL = 355 , SYSZ_INS_CLST = 356 , SYSZ_INS_CLY = 357 , SYSZ_INS_CPSDR = 358 , SYSZ_INS_CR = 359 , SYSZ_INS_CRL = 360 , SYSZ_INS_CS = 361 , SYSZ_INS_CSG = 362 , SYSZ_INS_CSY = 363 , SYSZ_INS_CXBR = 364 , SYSZ_INS_CXFBR = 365 , SYSZ_INS_CXGBR = 366 , SYSZ_INS_CXLFBR = 367 , SYSZ_INS_CXLGBR = 368 , SYSZ_INS_CY = 369 , SYSZ_INS_DDB = 370 , SYSZ_INS_DDBR = 371 , SYSZ_INS_DEB = 372 , SYSZ_INS_DEBR = 373 , SYSZ_INS_DL = 374 , SYSZ_INS_DLG = 375 , SYSZ_INS_DLGR = 376 , SYSZ_INS_DLR = 377 , SYSZ_INS_DSG = 378 , SYSZ_INS_DSGF = 379 , SYSZ_INS_DSGFR = 380 , SYSZ_INS_DSGR = 381 , SYSZ_INS_DXBR = 382 , SYSZ_INS_EAR = 383 , SYSZ_INS_FIDBR = 384 , SYSZ_INS_FIDBRA = 385 , SYSZ_INS_FIEBR = 386 , SYSZ_INS_FIEBRA = 387 , SYSZ_INS_FIXBR = 388 , SYSZ_INS_FIXBRA = 389 , SYSZ_INS_FLOGR = 390 , SYSZ_INS_IC = 391 , SYSZ_INS_ICY = 392 , SYSZ_INS_IIHF = 393 , SYSZ_INS_IIHH = 394 , SYSZ_INS_IIHL = 395 , SYSZ_INS_IILF = 396 , SYSZ_INS_IILH = 397 , SYSZ_INS_IILL = 398 , SYSZ_INS_IPM = 399 , SYSZ_INS_L = 400 , SYSZ_INS_LA = 401 , SYSZ_INS_LAA = 402 , SYSZ_INS_LAAG = 403 , SYSZ_INS_LAAL = 404 , SYSZ_INS_LAALG = 405 , SYSZ_INS_LAN = 406 , SYSZ_INS_LANG = 407 , SYSZ_INS_LAO = 408 , SYSZ_INS_LAOG = 409 , SYSZ_INS_LARL = 410 , SYSZ_INS_LAX = 411 , SYSZ_INS_LAXG = 412 , SYSZ_INS_LAY = 413 , SYSZ_INS_LB = 414 , SYSZ_INS_LBH = 415 , SYSZ_INS_LBR = 416 , SYSZ_INS_LCDBR = 417 , SYSZ_INS_LCEBR = 418 , SYSZ_INS_LCGFR = 419 , SYSZ_INS_LCGR = 420 , SYSZ_INS_LCR = 421 , SYSZ_INS_LCXBR = 422 , SYSZ_INS_LD = 423 , SYSZ_INS_LDEB = 424 , SYSZ_INS_LDEBR = 425 , SYSZ_INS_LDGR = 426 , SYSZ_INS_LDR = 427 , SYSZ_INS_LDXBR = 428 , SYSZ_INS_LDXBRA = 429 , SYSZ_INS_LDY = 430 , SYSZ_INS_LE = 431 , SYSZ_INS_LEDBR = 432 , SYSZ_INS_LEDBRA = 433 , SYSZ_INS_LER = 434 , SYSZ_INS_LEXBR = 435 , SYSZ_INS_LEXBRA = 436 , SYSZ_INS_LEY = 437 , SYSZ_INS_LFH = 438 , SYSZ_INS_LG = 439 , SYSZ_INS_LGB = 440 , SYSZ_INS_LGBR = 441 , SYSZ_INS_LGDR = 442 , SYSZ_INS_LGF = 443 , SYSZ_INS_LGFI = 444 , SYSZ_INS_LGFR = 445 , SYSZ_INS_LGFRL = 446 , SYSZ_INS_LGH = 447 , SYSZ_INS_LGHI = 448 , SYSZ_INS_LGHR = 449 , SYSZ_INS_LGHRL = 450 , SYSZ_INS_LGR = 451 , SYSZ_INS_LGRL = 452 , SYSZ_INS_LH = 453 , SYSZ_INS_LHH = 454 , SYSZ_INS_LHI = 455 , SYSZ_INS_LHR = 456 , SYSZ_INS_LHRL = 457 , SYSZ_INS_LHY = 458 , SYSZ_INS_LLC = 459 , SYSZ_INS_LLCH = 460 , SYSZ_INS_LLCR = 461 , SYSZ_INS_LLGC = 462 , SYSZ_INS_LLGCR = 463 , SYSZ_INS_LLGF = 464 , SYSZ_INS_LLGFR = 465 , SYSZ_INS_LLGFRL = 466 , SYSZ_INS_LLGH = 467 , SYSZ_INS_LLGHR = 468 , SYSZ_INS_LLGHRL = 469 , SYSZ_INS_LLH = 470 , SYSZ_INS_LLHH = 471 , SYSZ_INS_LLHR = 472 , SYSZ_INS_LLHRL = 473 , SYSZ_INS_LLIHF = 474 , SYSZ_INS_LLIHH = 475 , SYSZ_INS_LLIHL = 476 , SYSZ_INS_LLILF = 477 , SYSZ_INS_LLILH = 478 , SYSZ_INS_LLILL = 479 , SYSZ_INS_LMG = 480 , SYSZ_INS_LNDBR = 481 , SYSZ_INS_LNEBR = 482 , SYSZ_INS_LNGFR = 483 , SYSZ_INS_LNGR = 484 , SYSZ_INS_LNR = 485 , SYSZ_INS_LNXBR = 486 , SYSZ_INS_LPDBR = 487 , SYSZ_INS_LPEBR = 488 , SYSZ_INS_LPGFR = 489 , SYSZ_INS_LPGR = 490 , SYSZ_INS_LPR = 491 , SYSZ_INS_LPXBR = 492 , SYSZ_INS_LR = 493 , SYSZ_INS_LRL = 494 , SYSZ_INS_LRV = 495 , SYSZ_INS_LRVG = 496 , SYSZ_INS_LRVGR = 497 , SYSZ_INS_LRVR = 498 , SYSZ_INS_LT = 499 , SYSZ_INS_LTDBR = 500 , SYSZ_INS_LTEBR = 501 , SYSZ_INS_LTG = 502 , SYSZ_INS_LTGF = 503 , SYSZ_INS_LTGFR = 504 , SYSZ_INS_LTGR = 505 , SYSZ_INS_LTR = 506 , SYSZ_INS_LTXBR = 507 , SYSZ_INS_LXDB = 508 , SYSZ_INS_LXDBR = 509 , SYSZ_INS_LXEB = 510 , SYSZ_INS_LXEBR = 511 , SYSZ_INS_LXR = 512 , SYSZ_INS_LY = 513 , SYSZ_INS_LZDR = 514 , SYSZ_INS_LZER = 515 , SYSZ_INS_LZXR = 516 , SYSZ_INS_MADB = 517 , SYSZ_INS_MADBR = 518 , SYSZ_INS_MAEB = 519 , SYSZ_INS_MAEBR = 520 , SYSZ_INS_MDB = 521 , SYSZ_INS_MDBR = 522 , SYSZ_INS_MDEB = 523 , SYSZ_INS_MDEBR = 524 , SYSZ_INS_MEEB = 525 , SYSZ_INS_MEEBR = 526 , SYSZ_INS_MGHI = 527 , SYSZ_INS_MH = 528 , SYSZ_INS_MHI = 529 , SYSZ_INS_MHY = 530 , SYSZ_INS_MLG = 531 , SYSZ_INS_MLGR = 532 , SYSZ_INS_MS = 533 , SYSZ_INS_MSDB = 534 , SYSZ_INS_MSDBR = 535 , SYSZ_INS_MSEB = 536 , SYSZ_INS_MSEBR = 537 , SYSZ_INS_MSFI = 538 , SYSZ_INS_MSG = 539 , SYSZ_INS_MSGF = 540 , SYSZ_INS_MSGFI = 541 , SYSZ_INS_MSGFR = 542 , SYSZ_INS_MSGR = 543 , SYSZ_INS_MSR = 544 , SYSZ_INS_MSY = 545 , SYSZ_INS_MVC = 546 , SYSZ_INS_MVGHI = 547 , SYSZ_INS_MVHHI = 548 , SYSZ_INS_MVHI = 549 , SYSZ_INS_MVI = 550 , SYSZ_INS_MVIY = 551 , SYSZ_INS_MVST = 552 , SYSZ_INS_MXBR = 553 , SYSZ_INS_MXDB = 554 , SYSZ_INS_MXDBR = 555 , SYSZ_INS_N = 556 , SYSZ_INS_NC = 557 , SYSZ_INS_NG = 558 , SYSZ_INS_NGR = 559 , SYSZ_INS_NGRK = 560 , SYSZ_INS_NI = 561 , SYSZ_INS_NIHF = 562 , SYSZ_INS_NIHH = 563 , SYSZ_INS_NIHL = 564 , SYSZ_INS_NILF = 565 , SYSZ_INS_NILH = 566 , SYSZ_INS_NILL = 567 , SYSZ_INS_NIY = 568 , SYSZ_INS_NR = 569 , SYSZ_INS_NRK = 570 , SYSZ_INS_NY = 571 , SYSZ_INS_O = 572 , SYSZ_INS_OC = 573 , SYSZ_INS_OG = 574 , SYSZ_INS_OGR = 575 , SYSZ_INS_OGRK = 576 , SYSZ_INS_OI = 577 , SYSZ_INS_OIHF = 578 , SYSZ_INS_OIHH = 579 , SYSZ_INS_OIHL = 580 , SYSZ_INS_OILF = 581 , SYSZ_INS_OILH = 582 , SYSZ_INS_OILL = 583 , SYSZ_INS_OIY = 584 , SYSZ_INS_OR = 585 , SYSZ_INS_ORK = 586 , SYSZ_INS_OY = 587 , SYSZ_INS_PFD = 588 , SYSZ_INS_PFDRL = 589 , SYSZ_INS_RISBG = 590 , SYSZ_INS_RISBHG = 591 , SYSZ_INS_RISBLG = 592 , SYSZ_INS_RLL = 593 , SYSZ_INS_RLLG = 594 , SYSZ_INS_RNSBG = 595 , SYSZ_INS_ROSBG = 596 , SYSZ_INS_RXSBG = 597 , SYSZ_INS_S = 598 , SYSZ_INS_SDB = 599 , SYSZ_INS_SDBR = 600 , SYSZ_INS_SEB = 601 , SYSZ_INS_SEBR = 602 , SYSZ_INS_SG = 603 , SYSZ_INS_SGF = 604 , SYSZ_INS_SGFR = 605 , SYSZ_INS_SGR = 606 , SYSZ_INS_SGRK = 607 , SYSZ_INS_SH = 608 , SYSZ_INS_SHY = 609 , SYSZ_INS_SL = 610 , SYSZ_INS_SLB = 611 , SYSZ_INS_SLBG = 612 , SYSZ_INS_SLBR = 613 , SYSZ_INS_SLFI = 614 , SYSZ_INS_SLG = 615 , SYSZ_INS_SLBGR = 616 , SYSZ_INS_SLGF = 617 , SYSZ_INS_SLGFI = 618 , SYSZ_INS_SLGFR = 619 , SYSZ_INS_SLGR = 620 , SYSZ_INS_SLGRK = 621 , SYSZ_INS_SLL = 622 , SYSZ_INS_SLLG = 623 , SYSZ_INS_SLLK = 624 , SYSZ_INS_SLR = 625 , SYSZ_INS_SLRK = 626 , SYSZ_INS_SLY = 627 , SYSZ_INS_SQDB = 628 , SYSZ_INS_SQDBR = 629 , SYSZ_INS_SQEB = 630 , SYSZ_INS_SQEBR = 631 , SYSZ_INS_SQXBR = 632 , SYSZ_INS_SR = 633 , SYSZ_INS_SRA = 634 , SYSZ_INS_SRAG = 635 , SYSZ_INS_SRAK = 636 , SYSZ_INS_SRK = 637 , SYSZ_INS_SRL = 638 , SYSZ_INS_SRLG = 639 , SYSZ_INS_SRLK = 640 , SYSZ_INS_SRST = 641 , SYSZ_INS_ST = 642 , SYSZ_INS_STC = 643 , SYSZ_INS_STCH = 644 , SYSZ_INS_STCY = 645 , SYSZ_INS_STD = 646 , SYSZ_INS_STDY = 647 , SYSZ_INS_STE = 648 , SYSZ_INS_STEY = 649 , SYSZ_INS_STFH = 650 , SYSZ_INS_STG = 651 , SYSZ_INS_STGRL = 652 , SYSZ_INS_STH = 653 , SYSZ_INS_STHH = 654 , SYSZ_INS_STHRL = 655 , SYSZ_INS_STHY = 656 , SYSZ_INS_STMG = 657 , SYSZ_INS_STRL = 658 , SYSZ_INS_STRV = 659 , SYSZ_INS_STRVG = 660 , SYSZ_INS_STY = 661 , SYSZ_INS_SXBR = 662 , SYSZ_INS_SY = 663 , SYSZ_INS_TM = 664 , SYSZ_INS_TMHH = 665 , SYSZ_INS_TMHL = 666 , SYSZ_INS_TMLH = 667 , SYSZ_INS_TMLL = 668 , SYSZ_INS_TMY = 669 , SYSZ_INS_X = 670 , SYSZ_INS_XC = 671 , SYSZ_INS_XG = 672 , SYSZ_INS_XGR = 673 , SYSZ_INS_XGRK = 674 , SYSZ_INS_XI = 675 , SYSZ_INS_XIHF = 676 , SYSZ_INS_XILF = 677 , SYSZ_INS_XIY = 678 , SYSZ_INS_XR = 679 , SYSZ_INS_XRK = 680 , SYSZ_INS_XY = 681 , SYSZ_INS_AD = 682 , SYSZ_INS_ADR = 683 , SYSZ_INS_ADTR = 684 , SYSZ_INS_ADTRA = 685 , SYSZ_INS_AE = 686 , SYSZ_INS_AER = 687 , SYSZ_INS_AGH = 688 , SYSZ_INS_AHHHR = 689 , SYSZ_INS_AHHLR = 690 , SYSZ_INS_ALGSI = 691 , SYSZ_INS_ALHHHR = 692 , SYSZ_INS_ALHHLR = 693 , SYSZ_INS_ALSI = 694 , SYSZ_INS_ALSIH = 695 , SYSZ_INS_ALSIHN = 696 , SYSZ_INS_AP = 697 , SYSZ_INS_AU = 698 , SYSZ_INS_AUR = 699 , SYSZ_INS_AW = 700 , SYSZ_INS_AWR = 701 , SYSZ_INS_AXR = 702 , SYSZ_INS_AXTR = 703 , SYSZ_INS_AXTRA = 704 , SYSZ_INS_B = 705 , SYSZ_INS_BAKR = 706 , SYSZ_INS_BAL = 707 , SYSZ_INS_BALR = 708 , SYSZ_INS_BAS = 709 , SYSZ_INS_BASSM = 710 , SYSZ_INS_BC = 711 , SYSZ_INS_BCT = 712 , SYSZ_INS_BCTG = 713 , SYSZ_INS_BCTGR = 714 , SYSZ_INS_BCTR = 715 , SYSZ_INS_BE = 716 , SYSZ_INS_BH = 717 , SYSZ_INS_BHE = 718 , SYSZ_INS_BI = 719 , SYSZ_INS_BIC = 720 , SYSZ_INS_BIE = 721 , SYSZ_INS_BIH = 722 , SYSZ_INS_BIHE = 723 , SYSZ_INS_BIL = 724 , SYSZ_INS_BILE = 725 , SYSZ_INS_BILH = 726 , SYSZ_INS_BIM = 727 , SYSZ_INS_BINE = 728 , SYSZ_INS_BINH = 729 , SYSZ_INS_BINHE = 730 , SYSZ_INS_BINL = 731 , SYSZ_INS_BINLE = 732 , SYSZ_INS_BINLH = 733 , SYSZ_INS_BINM = 734 , SYSZ_INS_BINO = 735 , SYSZ_INS_BINP = 736 , SYSZ_INS_BINZ = 737 , SYSZ_INS_BIO = 738 , SYSZ_INS_BIP = 739 , SYSZ_INS_BIZ = 740 , SYSZ_INS_BL = 741 , SYSZ_INS_BLE = 742 , SYSZ_INS_BLH = 743 , SYSZ_INS_BM = 744 , SYSZ_INS_BMR = 745 , SYSZ_INS_BNE = 746 , SYSZ_INS_BNH = 747 , SYSZ_INS_BNHE = 748 , SYSZ_INS_BNL = 749 , SYSZ_INS_BNLE = 750 , SYSZ_INS_BNLH = 751 , SYSZ_INS_BNM = 752 , SYSZ_INS_BNMR = 753 , SYSZ_INS_BNO = 754 , SYSZ_INS_BNP = 755 , SYSZ_INS_BNPR = 756 , SYSZ_INS_BNZ = 757 , SYSZ_INS_BNZR = 758 , SYSZ_INS_BO = 759 , SYSZ_INS_BP = 760 , SYSZ_INS_BPP = 761 , SYSZ_INS_BPR = 762 , SYSZ_INS_BPRP = 763 , SYSZ_INS_BRCTH = 764 , SYSZ_INS_BRXH = 765 , SYSZ_INS_BRXHG = 766 , SYSZ_INS_BRXLE = 767 , SYSZ_INS_BRXLG = 768 , SYSZ_INS_BSA = 769 , SYSZ_INS_BSG = 770 , SYSZ_INS_BSM = 771 , SYSZ_INS_BXH = 772 , SYSZ_INS_BXHG = 773 , SYSZ_INS_BXLE = 774 , SYSZ_INS_BXLEG = 775 , SYSZ_INS_BZ = 776 , SYSZ_INS_BZR = 777 , SYSZ_INS_CD = 778 , SYSZ_INS_CDFBRA = 779 , SYSZ_INS_CDFR = 780 , SYSZ_INS_CDFTR = 781 , SYSZ_INS_CDGBRA = 782 , SYSZ_INS_CDGR = 783 , SYSZ_INS_CDGTR = 784 , SYSZ_INS_CDGTRA = 785 , SYSZ_INS_CDLFTR = 786 , SYSZ_INS_CDLGTR = 787 , SYSZ_INS_CDPT = 788 , SYSZ_INS_CDR = 789 , SYSZ_INS_CDS = 790 , SYSZ_INS_CDSG = 791 , SYSZ_INS_CDSTR = 792 , SYSZ_INS_CDSY = 793 , SYSZ_INS_CDTR = 794 , SYSZ_INS_CDUTR = 795 , SYSZ_INS_CDZT = 796 , SYSZ_INS_CE = 797 , SYSZ_INS_CEDTR = 798 , SYSZ_INS_CEFBRA = 799 , SYSZ_INS_CEFR = 800 , SYSZ_INS_CEGBRA = 801 , SYSZ_INS_CEGR = 802 , SYSZ_INS_CER = 803 , SYSZ_INS_CEXTR = 804 , SYSZ_INS_CFC = 805 , SYSZ_INS_CFDBRA = 806 , SYSZ_INS_CFDR = 807 , SYSZ_INS_CFDTR = 808 , SYSZ_INS_CFEBRA = 809 , SYSZ_INS_CFER = 810 , SYSZ_INS_CFXBRA = 811 , SYSZ_INS_CFXR = 812 , SYSZ_INS_CFXTR = 813 , SYSZ_INS_CGDBRA = 814 , SYSZ_INS_CGDR = 815 , SYSZ_INS_CGDTR = 816 , SYSZ_INS_CGDTRA = 817 , SYSZ_INS_CGEBRA = 818 , SYSZ_INS_CGER = 819 , SYSZ_INS_CGIB = 820 , SYSZ_INS_CGIBE = 821 , SYSZ_INS_CGIBH = 822 , SYSZ_INS_CGIBHE = 823 , SYSZ_INS_CGIBL = 824 , SYSZ_INS_CGIBLE = 825 , SYSZ_INS_CGIBLH = 826 , SYSZ_INS_CGIBNE = 827 , SYSZ_INS_CGIBNH = 828 , SYSZ_INS_CGIBNHE = 829 , SYSZ_INS_CGIBNL = 830 , SYSZ_INS_CGIBNLE = 831 , SYSZ_INS_CGIBNLH = 832 , SYSZ_INS_CGIT = 833 , SYSZ_INS_CGITE = 834 , SYSZ_INS_CGITH = 835 , SYSZ_INS_CGITHE = 836 , SYSZ_INS_CGITL = 837 , SYSZ_INS_CGITLE = 838 , SYSZ_INS_CGITLH = 839 , SYSZ_INS_CGITNE = 840 , SYSZ_INS_CGITNH = 841 , SYSZ_INS_CGITNHE = 842 , SYSZ_INS_CGITNL = 843 , SYSZ_INS_CGITNLE = 844 , SYSZ_INS_CGITNLH = 845 , SYSZ_INS_CGRB = 846 , SYSZ_INS_CGRBE = 847 , SYSZ_INS_CGRBH = 848 , SYSZ_INS_CGRBHE = 849 , SYSZ_INS_CGRBL = 850 , SYSZ_INS_CGRBLE = 851 , SYSZ_INS_CGRBLH = 852 , SYSZ_INS_CGRBNE = 853 , SYSZ_INS_CGRBNH = 854 , SYSZ_INS_CGRBNHE = 855 , SYSZ_INS_CGRBNL = 856 , SYSZ_INS_CGRBNLE = 857 , SYSZ_INS_CGRBNLH = 858 , SYSZ_INS_CGRT = 859 , SYSZ_INS_CGRTE = 860 , SYSZ_INS_CGRTH = 861 , SYSZ_INS_CGRTHE = 862 , SYSZ_INS_CGRTL = 863 , SYSZ_INS_CGRTLE = 864 , SYSZ_INS_CGRTLH = 865 , SYSZ_INS_CGRTNE = 866 , SYSZ_INS_CGRTNH = 867 , SYSZ_INS_CGRTNHE = 868 , SYSZ_INS_CGRTNL = 869 , SYSZ_INS_CGRTNLE = 870 , SYSZ_INS_CGRTNLH = 871 , SYSZ_INS_CGXBRA = 872 , SYSZ_INS_CGXR = 873 , SYSZ_INS_CGXTR = 874 , SYSZ_INS_CGXTRA = 875 , SYSZ_INS_CHHR = 876 , SYSZ_INS_CHLR = 877 , SYSZ_INS_CIB = 878 , SYSZ_INS_CIBE = 879 , SYSZ_INS_CIBH = 880 , SYSZ_INS_CIBHE = 881 , SYSZ_INS_CIBL = 882 , SYSZ_INS_CIBLE = 883 , SYSZ_INS_CIBLH = 884 , SYSZ_INS_CIBNE = 885 , SYSZ_INS_CIBNH = 886 , SYSZ_INS_CIBNHE = 887 , SYSZ_INS_CIBNL = 888 , SYSZ_INS_CIBNLE = 889 , SYSZ_INS_CIBNLH = 890 , SYSZ_INS_CIT = 891 , SYSZ_INS_CITE = 892 , SYSZ_INS_CITH = 893 , SYSZ_INS_CITHE = 894 , SYSZ_INS_CITL = 895 , SYSZ_INS_CITLE = 896 , SYSZ_INS_CITLH = 897 , SYSZ_INS_CITNE = 898 , SYSZ_INS_CITNH = 899 , SYSZ_INS_CITNHE = 900 , SYSZ_INS_CITNL = 901 , SYSZ_INS_CITNLE = 902 , SYSZ_INS_CITNLH = 903 , SYSZ_INS_CKSM = 904 , SYSZ_INS_CLCL = 905 , SYSZ_INS_CLCLE = 906 , SYSZ_INS_CLCLU = 907 , SYSZ_INS_CLFDTR = 908 , SYSZ_INS_CLFIT = 909 , SYSZ_INS_CLFITE = 910 , SYSZ_INS_CLFITH = 911 , SYSZ_INS_CLFITHE = 912 , SYSZ_INS_CLFITL = 913 , SYSZ_INS_CLFITLE = 914 , SYSZ_INS_CLFITLH = 915 , SYSZ_INS_CLFITNE = 916 , SYSZ_INS_CLFITNH = 917 , SYSZ_INS_CLFITNHE = 918 , SYSZ_INS_CLFITNL = 919 , SYSZ_INS_CLFITNLE = 920 , SYSZ_INS_CLFITNLH = 921 , SYSZ_INS_CLFXTR = 922 , SYSZ_INS_CLGDTR = 923 , SYSZ_INS_CLGIB = 924 , SYSZ_INS_CLGIBE = 925 , SYSZ_INS_CLGIBH = 926 , SYSZ_INS_CLGIBHE = 927 , SYSZ_INS_CLGIBL = 928 , SYSZ_INS_CLGIBLE = 929 , SYSZ_INS_CLGIBLH = 930 , SYSZ_INS_CLGIBNE = 931 , SYSZ_INS_CLGIBNH = 932 , SYSZ_INS_CLGIBNHE = 933 , SYSZ_INS_CLGIBNL = 934 , SYSZ_INS_CLGIBNLE = 935 , SYSZ_INS_CLGIBNLH = 936 , SYSZ_INS_CLGIT = 937 , SYSZ_INS_CLGITE = 938 , SYSZ_INS_CLGITH = 939 , SYSZ_INS_CLGITHE = 940 , SYSZ_INS_CLGITL = 941 , SYSZ_INS_CLGITLE = 942 , SYSZ_INS_CLGITLH = 943 , SYSZ_INS_CLGITNE = 944 , SYSZ_INS_CLGITNH = 945 , SYSZ_INS_CLGITNHE = 946 , SYSZ_INS_CLGITNL = 947 , SYSZ_INS_CLGITNLE = 948 , SYSZ_INS_CLGITNLH = 949 , SYSZ_INS_CLGRB = 950 , SYSZ_INS_CLGRBE = 951 , SYSZ_INS_CLGRBH = 952 , SYSZ_INS_CLGRBHE = 953 , SYSZ_INS_CLGRBL = 954 , SYSZ_INS_CLGRBLE = 955 , SYSZ_INS_CLGRBLH = 956 , SYSZ_INS_CLGRBNE = 957 , SYSZ_INS_CLGRBNH = 958 , SYSZ_INS_CLGRBNHE = 959 , SYSZ_INS_CLGRBNL = 960 , SYSZ_INS_CLGRBNLE = 961 , SYSZ_INS_CLGRBNLH = 962 , SYSZ_INS_CLGRT = 963 , SYSZ_INS_CLGRTE = 964 , SYSZ_INS_CLGRTH = 965 , SYSZ_INS_CLGRTHE = 966 , SYSZ_INS_CLGRTL = 967 , SYSZ_INS_CLGRTLE = 968 , SYSZ_INS_CLGRTLH = 969 , SYSZ_INS_CLGRTNE = 970 , SYSZ_INS_CLGRTNH = 971 , SYSZ_INS_CLGRTNHE = 972 , SYSZ_INS_CLGRTNL = 973 , SYSZ_INS_CLGRTNLE = 974 , SYSZ_INS_CLGRTNLH = 975 , SYSZ_INS_CLGT = 976 , SYSZ_INS_CLGTE = 977 , SYSZ_INS_CLGTH = 978 , SYSZ_INS_CLGTHE = 979 , SYSZ_INS_CLGTL = 980 , SYSZ_INS_CLGTLE = 981 , SYSZ_INS_CLGTLH = 982 , SYSZ_INS_CLGTNE = 983 , SYSZ_INS_CLGTNH = 984 , SYSZ_INS_CLGTNHE = 985 , SYSZ_INS_CLGTNL = 986 , SYSZ_INS_CLGTNLE = 987 , SYSZ_INS_CLGTNLH = 988 , SYSZ_INS_CLGXTR = 989 , SYSZ_INS_CLHHR = 990 , SYSZ_INS_CLHLR = 991 , SYSZ_INS_CLIB = 992 , SYSZ_INS_CLIBE = 993 , SYSZ_INS_CLIBH = 994 , SYSZ_INS_CLIBHE = 995 , SYSZ_INS_CLIBL = 996 , SYSZ_INS_CLIBLE = 997 , SYSZ_INS_CLIBLH = 998 , SYSZ_INS_CLIBNE = 999 , SYSZ_INS_CLIBNH = 1000 , SYSZ_INS_CLIBNHE = 1001 , SYSZ_INS_CLIBNL = 1002 , SYSZ_INS_CLIBNLE = 1003 , SYSZ_INS_CLIBNLH = 1004 , SYSZ_INS_CLM = 1005 , SYSZ_INS_CLMH = 1006 , SYSZ_INS_CLMY = 1007 , SYSZ_INS_CLRB = 1008 , SYSZ_INS_CLRBE = 1009 , SYSZ_INS_CLRBH = 1010 , SYSZ_INS_CLRBHE = 1011 , SYSZ_INS_CLRBL = 1012 , SYSZ_INS_CLRBLE = 1013 , SYSZ_INS_CLRBLH = 1014 , SYSZ_INS_CLRBNE = 1015 , SYSZ_INS_CLRBNH = 1016 , SYSZ_INS_CLRBNHE = 1017 , SYSZ_INS_CLRBNL = 1018 , SYSZ_INS_CLRBNLE = 1019 , SYSZ_INS_CLRBNLH = 1020 , SYSZ_INS_CLRT = 1021 , SYSZ_INS_CLRTE = 1022 , SYSZ_INS_CLRTH = 1023 , SYSZ_INS_CLRTHE = 1024 , SYSZ_INS_CLRTL = 1025 , SYSZ_INS_CLRTLE = 1026 , SYSZ_INS_CLRTLH = 1027 , SYSZ_INS_CLRTNE = 1028 , SYSZ_INS_CLRTNH = 1029 , SYSZ_INS_CLRTNHE = 1030 , SYSZ_INS_CLRTNL = 1031 , SYSZ_INS_CLRTNLE = 1032 , SYSZ_INS_CLRTNLH = 1033 , SYSZ_INS_CLT = 1034 , SYSZ_INS_CLTE = 1035 , SYSZ_INS_CLTH = 1036 , SYSZ_INS_CLTHE = 1037 , SYSZ_INS_CLTL = 1038 , SYSZ_INS_CLTLE = 1039 , SYSZ_INS_CLTLH = 1040 , SYSZ_INS_CLTNE = 1041 , SYSZ_INS_CLTNH = 1042 , SYSZ_INS_CLTNHE = 1043 , SYSZ_INS_CLTNL = 1044 , SYSZ_INS_CLTNLE = 1045 , SYSZ_INS_CLTNLH = 1046 , SYSZ_INS_CMPSC = 1047 , SYSZ_INS_CP = 1048 , SYSZ_INS_CPDT = 1049 , SYSZ_INS_CPXT = 1050 , SYSZ_INS_CPYA = 1051 , SYSZ_INS_CRB = 1052 , SYSZ_INS_CRBE = 1053 , SYSZ_INS_CRBH = 1054 , SYSZ_INS_CRBHE = 1055 , SYSZ_INS_CRBL = 1056 , SYSZ_INS_CRBLE = 1057 , SYSZ_INS_CRBLH = 1058 , SYSZ_INS_CRBNE = 1059 , SYSZ_INS_CRBNH = 1060 , SYSZ_INS_CRBNHE = 1061 , SYSZ_INS_CRBNL = 1062 , SYSZ_INS_CRBNLE = 1063 , SYSZ_INS_CRBNLH = 1064 , SYSZ_INS_CRDTE = 1065 , SYSZ_INS_CRT = 1066 , SYSZ_INS_CRTE = 1067 , SYSZ_INS_CRTH = 1068 , SYSZ_INS_CRTHE = 1069 , SYSZ_INS_CRTL = 1070 , SYSZ_INS_CRTLE = 1071 , SYSZ_INS_CRTLH = 1072 , SYSZ_INS_CRTNE = 1073 , SYSZ_INS_CRTNH = 1074 , SYSZ_INS_CRTNHE = 1075 , SYSZ_INS_CRTNL = 1076 , SYSZ_INS_CRTNLE = 1077 , SYSZ_INS_CRTNLH = 1078 , SYSZ_INS_CSCH = 1079 , SYSZ_INS_CSDTR = 1080 , SYSZ_INS_CSP = 1081 , SYSZ_INS_CSPG = 1082 , SYSZ_INS_CSST = 1083 , SYSZ_INS_CSXTR = 1084 , SYSZ_INS_CU12 = 1085 , SYSZ_INS_CU14 = 1086 , SYSZ_INS_CU21 = 1087 , SYSZ_INS_CU24 = 1088 , SYSZ_INS_CU41 = 1089 , SYSZ_INS_CU42 = 1090 , SYSZ_INS_CUDTR = 1091 , SYSZ_INS_CUSE = 1092 , SYSZ_INS_CUTFU = 1093 , SYSZ_INS_CUUTF = 1094 , SYSZ_INS_CUXTR = 1095 , SYSZ_INS_CVB = 1096 , SYSZ_INS_CVBG = 1097 , SYSZ_INS_CVBY = 1098 , SYSZ_INS_CVD = 1099 , SYSZ_INS_CVDG = 1100 , SYSZ_INS_CVDY = 1101 , SYSZ_INS_CXFBRA = 1102 , SYSZ_INS_CXFR = 1103 , SYSZ_INS_CXFTR = 1104 , SYSZ_INS_CXGBRA = 1105 , SYSZ_INS_CXGR = 1106 , SYSZ_INS_CXGTR = 1107 , SYSZ_INS_CXGTRA = 1108 , SYSZ_INS_CXLFTR = 1109 , SYSZ_INS_CXLGTR = 1110 , SYSZ_INS_CXPT = 1111 , SYSZ_INS_CXR = 1112 , SYSZ_INS_CXSTR = 1113 , SYSZ_INS_CXTR = 1114 , SYSZ_INS_CXUTR = 1115 , SYSZ_INS_CXZT = 1116 , SYSZ_INS_CZDT = 1117 , SYSZ_INS_CZXT = 1118 , SYSZ_INS_D = 1119 , SYSZ_INS_DD = 1120 , SYSZ_INS_DDR = 1121 , SYSZ_INS_DDTR = 1122 , SYSZ_INS_DDTRA = 1123 , SYSZ_INS_DE = 1124 , SYSZ_INS_DER = 1125 , SYSZ_INS_DIAG = 1126 , SYSZ_INS_DIDBR = 1127 , SYSZ_INS_DIEBR = 1128 , SYSZ_INS_DP = 1129 , SYSZ_INS_DR = 1130 , SYSZ_INS_DXR = 1131 , SYSZ_INS_DXTR = 1132 , SYSZ_INS_DXTRA = 1133 , SYSZ_INS_ECAG = 1134 , SYSZ_INS_ECCTR = 1135 , SYSZ_INS_ECPGA = 1136 , SYSZ_INS_ECTG = 1137 , SYSZ_INS_ED = 1138 , SYSZ_INS_EDMK = 1139 , SYSZ_INS_EEDTR = 1140 , SYSZ_INS_EEXTR = 1141 , SYSZ_INS_EFPC = 1142 , SYSZ_INS_EPAIR = 1143 , SYSZ_INS_EPAR = 1144 , SYSZ_INS_EPCTR = 1145 , SYSZ_INS_EPSW = 1146 , SYSZ_INS_EREG = 1147 , SYSZ_INS_EREGG = 1148 , SYSZ_INS_ESAIR = 1149 , SYSZ_INS_ESAR = 1150 , SYSZ_INS_ESDTR = 1151 , SYSZ_INS_ESEA = 1152 , SYSZ_INS_ESTA = 1153 , SYSZ_INS_ESXTR = 1154 , SYSZ_INS_ETND = 1155 , SYSZ_INS_EX = 1156 , SYSZ_INS_EXRL = 1157 , SYSZ_INS_FIDR = 1158 , SYSZ_INS_FIDTR = 1159 , SYSZ_INS_FIER = 1160 , SYSZ_INS_FIXR = 1161 , SYSZ_INS_FIXTR = 1162 , SYSZ_INS_HDR = 1163 , SYSZ_INS_HER = 1164 , SYSZ_INS_HSCH = 1165 , SYSZ_INS_IAC = 1166 , SYSZ_INS_ICM = 1167 , SYSZ_INS_ICMH = 1168 , SYSZ_INS_ICMY = 1169 , SYSZ_INS_IDTE = 1170 , SYSZ_INS_IEDTR = 1171 , SYSZ_INS_IEXTR = 1172 , SYSZ_INS_IPK = 1173 , SYSZ_INS_IPTE = 1174 , SYSZ_INS_IRBM = 1175 , SYSZ_INS_ISKE = 1176 , SYSZ_INS_IVSK = 1177 , SYSZ_INS_JGM = 1178 , SYSZ_INS_JGNM = 1179 , SYSZ_INS_JGNP = 1180 , SYSZ_INS_JGNZ = 1181 , SYSZ_INS_JGP = 1182 , SYSZ_INS_JGZ = 1183 , SYSZ_INS_JM = 1184 , SYSZ_INS_JNM = 1185 , SYSZ_INS_JNP = 1186 , SYSZ_INS_JNZ = 1187 , SYSZ_INS_JP = 1188 , SYSZ_INS_JZ = 1189 , SYSZ_INS_KDB = 1190 , SYSZ_INS_KDBR = 1191 , SYSZ_INS_KDTR = 1192 , SYSZ_INS_KEB = 1193 , SYSZ_INS_KEBR = 1194 , SYSZ_INS_KIMD = 1195 , SYSZ_INS_KLMD = 1196 , SYSZ_INS_KM = 1197 , SYSZ_INS_KMA = 1198 , SYSZ_INS_KMAC = 1199 , SYSZ_INS_KMC = 1200 , SYSZ_INS_KMCTR = 1201 , SYSZ_INS_KMF = 1202 , SYSZ_INS_KMO = 1203 , SYSZ_INS_KXBR = 1204 , SYSZ_INS_KXTR = 1205 , SYSZ_INS_LAE = 1206 , SYSZ_INS_LAEY = 1207 , SYSZ_INS_LAM = 1208 , SYSZ_INS_LAMY = 1209 , SYSZ_INS_LASP = 1210 , SYSZ_INS_LAT = 1211 , SYSZ_INS_LCBB = 1212 , SYSZ_INS_LCCTL = 1213 , SYSZ_INS_LCDFR = 1214 , SYSZ_INS_LCDR = 1215 , SYSZ_INS_LCER = 1216 , SYSZ_INS_LCTL = 1217 , SYSZ_INS_LCTLG = 1218 , SYSZ_INS_LCXR = 1219 , SYSZ_INS_LDE = 1220 , SYSZ_INS_LDER = 1221 , SYSZ_INS_LDETR = 1222 , SYSZ_INS_LDXR = 1223 , SYSZ_INS_LDXTR = 1224 , SYSZ_INS_LEDR = 1225 , SYSZ_INS_LEDTR = 1226 , SYSZ_INS_LEXR = 1227 , SYSZ_INS_LFAS = 1228 , SYSZ_INS_LFHAT = 1229 , SYSZ_INS_LFPC = 1230 , SYSZ_INS_LGAT = 1231 , SYSZ_INS_LGG = 1232 , SYSZ_INS_LGSC = 1233 , SYSZ_INS_LLGFAT = 1234 , SYSZ_INS_LLGFSG = 1235 , SYSZ_INS_LLGT = 1236 , SYSZ_INS_LLGTAT = 1237 , SYSZ_INS_LLGTR = 1238 , SYSZ_INS_LLZRGF = 1239 , SYSZ_INS_LM = 1240 , SYSZ_INS_LMD = 1241 , SYSZ_INS_LMH = 1242 , SYSZ_INS_LMY = 1243 , SYSZ_INS_LNDFR = 1244 , SYSZ_INS_LNDR = 1245 , SYSZ_INS_LNER = 1246 , SYSZ_INS_LNXR = 1247 , SYSZ_INS_LOCFH = 1248 , SYSZ_INS_LOCFHE = 1249 , SYSZ_INS_LOCFHH = 1250 , SYSZ_INS_LOCFHHE = 1251 , SYSZ_INS_LOCFHL = 1252 , SYSZ_INS_LOCFHLE = 1253 , SYSZ_INS_LOCFHLH = 1254 , SYSZ_INS_LOCFHM = 1255 , SYSZ_INS_LOCFHNE = 1256 , SYSZ_INS_LOCFHNH = 1257 , SYSZ_INS_LOCFHNHE = 1258 , SYSZ_INS_LOCFHNL = 1259 , SYSZ_INS_LOCFHNLE = 1260 , SYSZ_INS_LOCFHNLH = 1261 , SYSZ_INS_LOCFHNM = 1262 , SYSZ_INS_LOCFHNO = 1263 , SYSZ_INS_LOCFHNP = 1264 , SYSZ_INS_LOCFHNZ = 1265 , SYSZ_INS_LOCFHO = 1266 , SYSZ_INS_LOCFHP = 1267 , SYSZ_INS_LOCFHR = 1268 , SYSZ_INS_LOCFHRE = 1269 , SYSZ_INS_LOCFHRH = 1270 , SYSZ_INS_LOCFHRHE = 1271 , SYSZ_INS_LOCFHRL = 1272 , SYSZ_INS_LOCFHRLE = 1273 , SYSZ_INS_LOCFHRLH = 1274 , SYSZ_INS_LOCFHRM = 1275 , SYSZ_INS_LOCFHRNE = 1276 , SYSZ_INS_LOCFHRNH = 1277 , SYSZ_INS_LOCFHRNHE = 1278 , SYSZ_INS_LOCFHRNL = 1279 , SYSZ_INS_LOCFHRNLE = 1280 , SYSZ_INS_LOCFHRNLH = 1281 , SYSZ_INS_LOCFHRNM = 1282 , SYSZ_INS_LOCFHRNO = 1283 , SYSZ_INS_LOCFHRNP = 1284 , SYSZ_INS_LOCFHRNZ = 1285 , SYSZ_INS_LOCFHRO = 1286 , SYSZ_INS_LOCFHRP = 1287 , SYSZ_INS_LOCFHRZ = 1288 , SYSZ_INS_LOCFHZ = 1289 , SYSZ_INS_LOCGHI = 1290 , SYSZ_INS_LOCGHIE = 1291 , SYSZ_INS_LOCGHIH = 1292 , SYSZ_INS_LOCGHIHE = 1293 , SYSZ_INS_LOCGHIL = 1294 , SYSZ_INS_LOCGHILE = 1295 , SYSZ_INS_LOCGHILH = 1296 , SYSZ_INS_LOCGHIM = 1297 , SYSZ_INS_LOCGHINE = 1298 , SYSZ_INS_LOCGHINH = 1299 , SYSZ_INS_LOCGHINHE = 1300 , SYSZ_INS_LOCGHINL = 1301 , SYSZ_INS_LOCGHINLE = 1302 , SYSZ_INS_LOCGHINLH = 1303 , SYSZ_INS_LOCGHINM = 1304 , SYSZ_INS_LOCGHINO = 1305 , SYSZ_INS_LOCGHINP = 1306 , SYSZ_INS_LOCGHINZ = 1307 , SYSZ_INS_LOCGHIO = 1308 , SYSZ_INS_LOCGHIP = 1309 , SYSZ_INS_LOCGHIZ = 1310 , SYSZ_INS_LOCGM = 1311 , SYSZ_INS_LOCGNM = 1312 , SYSZ_INS_LOCGNP = 1313 , SYSZ_INS_LOCGNZ = 1314 , SYSZ_INS_LOCGP = 1315 , SYSZ_INS_LOCGRM = 1316 , SYSZ_INS_LOCGRNM = 1317 , SYSZ_INS_LOCGRNP = 1318 , SYSZ_INS_LOCGRNZ = 1319 , SYSZ_INS_LOCGRP = 1320 , SYSZ_INS_LOCGRZ = 1321 , SYSZ_INS_LOCGZ = 1322 , SYSZ_INS_LOCHHI = 1323 , SYSZ_INS_LOCHHIE = 1324 , SYSZ_INS_LOCHHIH = 1325 , SYSZ_INS_LOCHHIHE = 1326 , SYSZ_INS_LOCHHIL = 1327 , SYSZ_INS_LOCHHILE = 1328 , SYSZ_INS_LOCHHILH = 1329 , SYSZ_INS_LOCHHIM = 1330 , SYSZ_INS_LOCHHINE = 1331 , SYSZ_INS_LOCHHINH = 1332 , SYSZ_INS_LOCHHINHE = 1333 , SYSZ_INS_LOCHHINL = 1334 , SYSZ_INS_LOCHHINLE = 1335 , SYSZ_INS_LOCHHINLH = 1336 , SYSZ_INS_LOCHHINM = 1337 , SYSZ_INS_LOCHHINO = 1338 , SYSZ_INS_LOCHHINP = 1339 , SYSZ_INS_LOCHHINZ = 1340 , SYSZ_INS_LOCHHIO = 1341 , SYSZ_INS_LOCHHIP = 1342 , SYSZ_INS_LOCHHIZ = 1343 , SYSZ_INS_LOCHI = 1344 , SYSZ_INS_LOCHIE = 1345 , SYSZ_INS_LOCHIH = 1346 , SYSZ_INS_LOCHIHE = 1347 , SYSZ_INS_LOCHIL = 1348 , SYSZ_INS_LOCHILE = 1349 , SYSZ_INS_LOCHILH = 1350 , SYSZ_INS_LOCHIM = 1351 , SYSZ_INS_LOCHINE = 1352 , SYSZ_INS_LOCHINH = 1353 , SYSZ_INS_LOCHINHE = 1354 , SYSZ_INS_LOCHINL = 1355 , SYSZ_INS_LOCHINLE = 1356 , SYSZ_INS_LOCHINLH = 1357 , SYSZ_INS_LOCHINM = 1358 , SYSZ_INS_LOCHINO = 1359 , SYSZ_INS_LOCHINP = 1360 , SYSZ_INS_LOCHINZ = 1361 , SYSZ_INS_LOCHIO = 1362 , SYSZ_INS_LOCHIP = 1363 , SYSZ_INS_LOCHIZ = 1364 , SYSZ_INS_LOCM = 1365 , SYSZ_INS_LOCNM = 1366 , SYSZ_INS_LOCNP = 1367 , SYSZ_INS_LOCNZ = 1368 , SYSZ_INS_LOCP = 1369 , SYSZ_INS_LOCRM = 1370 , SYSZ_INS_LOCRNM = 1371 , SYSZ_INS_LOCRNP = 1372 , SYSZ_INS_LOCRNZ = 1373 , SYSZ_INS_LOCRP = 1374 , SYSZ_INS_LOCRZ = 1375 , SYSZ_INS_LOCZ = 1376 , SYSZ_INS_LPCTL = 1377 , SYSZ_INS_LPD = 1378 , SYSZ_INS_LPDFR = 1379 , SYSZ_INS_LPDG = 1380 , SYSZ_INS_LPDR = 1381 , SYSZ_INS_LPER = 1382 , SYSZ_INS_LPP = 1383 , SYSZ_INS_LPQ = 1384 , SYSZ_INS_LPSW = 1385 , SYSZ_INS_LPSWE = 1386 , SYSZ_INS_LPTEA = 1387 , SYSZ_INS_LPXR = 1388 , SYSZ_INS_LRA = 1389 , SYSZ_INS_LRAG = 1390 , SYSZ_INS_LRAY = 1391 , SYSZ_INS_LRDR = 1392 , SYSZ_INS_LRER = 1393 , SYSZ_INS_LRVH = 1394 , SYSZ_INS_LSCTL = 1395 , SYSZ_INS_LTDR = 1396 , SYSZ_INS_LTDTR = 1397 , SYSZ_INS_LTER = 1398 , SYSZ_INS_LTXR = 1399 , SYSZ_INS_LTXTR = 1400 , SYSZ_INS_LURA = 1401 , SYSZ_INS_LURAG = 1402 , SYSZ_INS_LXD = 1403 , SYSZ_INS_LXDR = 1404 , SYSZ_INS_LXDTR = 1405 , SYSZ_INS_LXE = 1406 , SYSZ_INS_LXER = 1407 , SYSZ_INS_LZRF = 1408 , SYSZ_INS_LZRG = 1409 , SYSZ_INS_M = 1410 , SYSZ_INS_MAD = 1411 , SYSZ_INS_MADR = 1412 , SYSZ_INS_MAE = 1413 , SYSZ_INS_MAER = 1414 , SYSZ_INS_MAY = 1415 , SYSZ_INS_MAYH = 1416 , SYSZ_INS_MAYHR = 1417 , SYSZ_INS_MAYL = 1418 , SYSZ_INS_MAYLR = 1419 , SYSZ_INS_MAYR = 1420 , SYSZ_INS_MC = 1421 , SYSZ_INS_MD = 1422 , SYSZ_INS_MDE = 1423 , SYSZ_INS_MDER = 1424 , SYSZ_INS_MDR = 1425 , SYSZ_INS_MDTR = 1426 , SYSZ_INS_MDTRA = 1427 , SYSZ_INS_ME = 1428 , SYSZ_INS_MEE = 1429 , SYSZ_INS_MEER = 1430 , SYSZ_INS_MER = 1431 , SYSZ_INS_MFY = 1432 , SYSZ_INS_MG = 1433 , SYSZ_INS_MGH = 1434 , SYSZ_INS_MGRK = 1435 , SYSZ_INS_ML = 1436 , SYSZ_INS_MLR = 1437 , SYSZ_INS_MP = 1438 , SYSZ_INS_MR = 1439 , SYSZ_INS_MSC = 1440 , SYSZ_INS_MSCH = 1441 , SYSZ_INS_MSD = 1442 , SYSZ_INS_MSDR = 1443 , SYSZ_INS_MSE = 1444 , SYSZ_INS_MSER = 1445 , SYSZ_INS_MSGC = 1446 , SYSZ_INS_MSGRKC = 1447 , SYSZ_INS_MSRKC = 1448 , SYSZ_INS_MSTA = 1449 , SYSZ_INS_MVCDK = 1450 , SYSZ_INS_MVCIN = 1451 , SYSZ_INS_MVCK = 1452 , SYSZ_INS_MVCL = 1453 , SYSZ_INS_MVCLE = 1454 , SYSZ_INS_MVCLU = 1455 , SYSZ_INS_MVCOS = 1456 , SYSZ_INS_MVCP = 1457 , SYSZ_INS_MVCS = 1458 , SYSZ_INS_MVCSK = 1459 , SYSZ_INS_MVN = 1460 , SYSZ_INS_MVO = 1461 , SYSZ_INS_MVPG = 1462 , SYSZ_INS_MVZ = 1463 , SYSZ_INS_MXD = 1464 , SYSZ_INS_MXDR = 1465 , SYSZ_INS_MXR = 1466 , SYSZ_INS_MXTR = 1467 , SYSZ_INS_MXTRA = 1468 , SYSZ_INS_MY = 1469 , SYSZ_INS_MYH = 1470 , SYSZ_INS_MYHR = 1471 , SYSZ_INS_MYL = 1472 , SYSZ_INS_MYLR = 1473 , SYSZ_INS_MYR = 1474 , SYSZ_INS_NIAI = 1475 , SYSZ_INS_NTSTG = 1476 , SYSZ_INS_PACK = 1477 , SYSZ_INS_PALB = 1478 , SYSZ_INS_PC = 1479 , SYSZ_INS_PCC = 1480 , SYSZ_INS_PCKMO = 1481 , SYSZ_INS_PFMF = 1482 , SYSZ_INS_PFPO = 1483 , SYSZ_INS_PGIN = 1484 , SYSZ_INS_PGOUT = 1485 , SYSZ_INS_PKA = 1486 , SYSZ_INS_PKU = 1487 , SYSZ_INS_PLO = 1488 , SYSZ_INS_POPCNT = 1489 , SYSZ_INS_PPA = 1490 , SYSZ_INS_PPNO = 1491 , SYSZ_INS_PR = 1492 , SYSZ_INS_PRNO = 1493 , SYSZ_INS_PT = 1494 , SYSZ_INS_PTF = 1495 , SYSZ_INS_PTFF = 1496 , SYSZ_INS_PTI = 1497 , SYSZ_INS_PTLB = 1498 , SYSZ_INS_QADTR = 1499 , SYSZ_INS_QAXTR = 1500 , SYSZ_INS_QCTRI = 1501 , SYSZ_INS_QSI = 1502 , SYSZ_INS_RCHP = 1503 , SYSZ_INS_RISBGN = 1504 , SYSZ_INS_RP = 1505 , SYSZ_INS_RRBE = 1506 , SYSZ_INS_RRBM = 1507 , SYSZ_INS_RRDTR = 1508 , SYSZ_INS_RRXTR = 1509 , SYSZ_INS_RSCH = 1510 , SYSZ_INS_SAC = 1511 , SYSZ_INS_SACF = 1512 , SYSZ_INS_SAL = 1513 , SYSZ_INS_SAM24 = 1514 , SYSZ_INS_SAM31 = 1515 , SYSZ_INS_SAM64 = 1516 , SYSZ_INS_SAR = 1517 , SYSZ_INS_SCCTR = 1518 , SYSZ_INS_SCHM = 1519 , SYSZ_INS_SCK = 1520 , SYSZ_INS_SCKC = 1521 , SYSZ_INS_SCKPF = 1522 , SYSZ_INS_SD = 1523 , SYSZ_INS_SDR = 1524 , SYSZ_INS_SDTR = 1525 , SYSZ_INS_SDTRA = 1526 , SYSZ_INS_SE = 1527 , SYSZ_INS_SER = 1528 , SYSZ_INS_SFASR = 1529 , SYSZ_INS_SFPC = 1530 , SYSZ_INS_SGH = 1531 , SYSZ_INS_SHHHR = 1532 , SYSZ_INS_SHHLR = 1533 , SYSZ_INS_SIE = 1534 , SYSZ_INS_SIGA = 1535 , SYSZ_INS_SIGP = 1536 , SYSZ_INS_SLA = 1537 , SYSZ_INS_SLAG = 1538 , SYSZ_INS_SLAK = 1539 , SYSZ_INS_SLDA = 1540 , SYSZ_INS_SLDL = 1541 , SYSZ_INS_SLDT = 1542 , SYSZ_INS_SLHHHR = 1543 , SYSZ_INS_SLHHLR = 1544 , SYSZ_INS_SLXT = 1545 , SYSZ_INS_SP = 1546 , SYSZ_INS_SPCTR = 1547 , SYSZ_INS_SPKA = 1548 , SYSZ_INS_SPM = 1549 , SYSZ_INS_SPT = 1550 , SYSZ_INS_SPX = 1551 , SYSZ_INS_SQD = 1552 , SYSZ_INS_SQDR = 1553 , SYSZ_INS_SQE = 1554 , SYSZ_INS_SQER = 1555 , SYSZ_INS_SQXR = 1556 , SYSZ_INS_SRDA = 1557 , SYSZ_INS_SRDL = 1558 , SYSZ_INS_SRDT = 1559 , SYSZ_INS_SRNM = 1560 , SYSZ_INS_SRNMB = 1561 , SYSZ_INS_SRNMT = 1562 , SYSZ_INS_SRP = 1563 , SYSZ_INS_SRSTU = 1564 , SYSZ_INS_SRXT = 1565 , SYSZ_INS_SSAIR = 1566 , SYSZ_INS_SSAR = 1567 , SYSZ_INS_SSCH = 1568 , SYSZ_INS_SSKE = 1569 , SYSZ_INS_SSM = 1570 , SYSZ_INS_STAM = 1571 , SYSZ_INS_STAMY = 1572 , SYSZ_INS_STAP = 1573 , SYSZ_INS_STCK = 1574 , SYSZ_INS_STCKC = 1575 , SYSZ_INS_STCKE = 1576 , SYSZ_INS_STCKF = 1577 , SYSZ_INS_STCM = 1578 , SYSZ_INS_STCMH = 1579 , SYSZ_INS_STCMY = 1580 , SYSZ_INS_STCPS = 1581 , SYSZ_INS_STCRW = 1582 , SYSZ_INS_STCTG = 1583 , SYSZ_INS_STCTL = 1584 , SYSZ_INS_STFL = 1585 , SYSZ_INS_STFLE = 1586 , SYSZ_INS_STFPC = 1587 , SYSZ_INS_STGSC = 1588 , SYSZ_INS_STIDP = 1589 , SYSZ_INS_STM = 1590 , SYSZ_INS_STMH = 1591 , SYSZ_INS_STMY = 1592 , SYSZ_INS_STNSM = 1593 , SYSZ_INS_STOCFH = 1594 , SYSZ_INS_STOCFHE = 1595 , SYSZ_INS_STOCFHH = 1596 , SYSZ_INS_STOCFHHE = 1597 , SYSZ_INS_STOCFHL = 1598 , SYSZ_INS_STOCFHLE = 1599 , SYSZ_INS_STOCFHLH = 1600 , SYSZ_INS_STOCFHM = 1601 , SYSZ_INS_STOCFHNE = 1602 , SYSZ_INS_STOCFHNH = 1603 , SYSZ_INS_STOCFHNHE = 1604 , SYSZ_INS_STOCFHNL = 1605 , SYSZ_INS_STOCFHNLE = 1606 , SYSZ_INS_STOCFHNLH = 1607 , SYSZ_INS_STOCFHNM = 1608 , SYSZ_INS_STOCFHNO = 1609 , SYSZ_INS_STOCFHNP = 1610 , SYSZ_INS_STOCFHNZ = 1611 , SYSZ_INS_STOCFHO = 1612 , SYSZ_INS_STOCFHP = 1613 , SYSZ_INS_STOCFHZ = 1614 , SYSZ_INS_STOCGM = 1615 , SYSZ_INS_STOCGNM = 1616 , SYSZ_INS_STOCGNP = 1617 , SYSZ_INS_STOCGNZ = 1618 , SYSZ_INS_STOCGP = 1619 , SYSZ_INS_STOCGZ = 1620 , SYSZ_INS_STOCM = 1621 , SYSZ_INS_STOCNM = 1622 , SYSZ_INS_STOCNP = 1623 , SYSZ_INS_STOCNZ = 1624 , SYSZ_INS_STOCP = 1625 , SYSZ_INS_STOCZ = 1626 , SYSZ_INS_STOSM = 1627 , SYSZ_INS_STPQ = 1628 , SYSZ_INS_STPT = 1629 , SYSZ_INS_STPX = 1630 , SYSZ_INS_STRAG = 1631 , SYSZ_INS_STRVH = 1632 , SYSZ_INS_STSCH = 1633 , SYSZ_INS_STSI = 1634 , SYSZ_INS_STURA = 1635 , SYSZ_INS_STURG = 1636 , SYSZ_INS_SU = 1637 , SYSZ_INS_SUR = 1638 , SYSZ_INS_SVC = 1639 , SYSZ_INS_SW = 1640 , SYSZ_INS_SWR = 1641 , SYSZ_INS_SXR = 1642 , SYSZ_INS_SXTR = 1643 , SYSZ_INS_SXTRA = 1644 , SYSZ_INS_TABORT = 1645 , SYSZ_INS_TAM = 1646 , SYSZ_INS_TAR = 1647 , SYSZ_INS_TB = 1648 , SYSZ_INS_TBDR = 1649 , SYSZ_INS_TBEDR = 1650 , SYSZ_INS_TBEGIN = 1651 , SYSZ_INS_TBEGINC = 1652 , SYSZ_INS_TCDB = 1653 , SYSZ_INS_TCEB = 1654 , SYSZ_INS_TCXB = 1655 , SYSZ_INS_TDCDT = 1656 , SYSZ_INS_TDCET = 1657 , SYSZ_INS_TDCXT = 1658 , SYSZ_INS_TDGDT = 1659 , SYSZ_INS_TDGET = 1660 , SYSZ_INS_TDGXT = 1661 , SYSZ_INS_TEND = 1662 , SYSZ_INS_THDER = 1663 , SYSZ_INS_THDR = 1664 , SYSZ_INS_TP = 1665 , SYSZ_INS_TPI = 1666 , SYSZ_INS_TPROT = 1667 , SYSZ_INS_TR = 1668 , SYSZ_INS_TRACE = 1669 , SYSZ_INS_TRACG = 1670 , SYSZ_INS_TRAP2 = 1671 , SYSZ_INS_TRAP4 = 1672 , SYSZ_INS_TRE = 1673 , SYSZ_INS_TROO = 1674 , SYSZ_INS_TROT = 1675 , SYSZ_INS_TRT = 1676 , SYSZ_INS_TRTE = 1677 , SYSZ_INS_TRTO = 1678 , SYSZ_INS_TRTR = 1679 , SYSZ_INS_TRTRE = 1680 , SYSZ_INS_TRTT = 1681 , SYSZ_INS_TS = 1682 , SYSZ_INS_TSCH = 1683 , SYSZ_INS_UNPK = 1684 , SYSZ_INS_UNPKA = 1685 , SYSZ_INS_UNPKU = 1686 , SYSZ_INS_UPT = 1687 , SYSZ_INS_VA = 1688 , SYSZ_INS_VAB = 1689 , SYSZ_INS_VAC = 1690 , SYSZ_INS_VACC = 1691 , SYSZ_INS_VACCB = 1692 , SYSZ_INS_VACCC = 1693 , SYSZ_INS_VACCCQ = 1694 , SYSZ_INS_VACCF = 1695 , SYSZ_INS_VACCG = 1696 , SYSZ_INS_VACCH = 1697 , SYSZ_INS_VACCQ = 1698 , SYSZ_INS_VACQ = 1699 , SYSZ_INS_VAF = 1700 , SYSZ_INS_VAG = 1701 , SYSZ_INS_VAH = 1702 , SYSZ_INS_VAP = 1703 , SYSZ_INS_VAQ = 1704 , SYSZ_INS_VAVG = 1705 , SYSZ_INS_VAVGB = 1706 , SYSZ_INS_VAVGF = 1707 , SYSZ_INS_VAVGG = 1708 , SYSZ_INS_VAVGH = 1709 , SYSZ_INS_VAVGL = 1710 , SYSZ_INS_VAVGLB = 1711 , SYSZ_INS_VAVGLF = 1712 , SYSZ_INS_VAVGLG = 1713 , SYSZ_INS_VAVGLH = 1714 , SYSZ_INS_VBPERM = 1715 , SYSZ_INS_VCDG = 1716 , SYSZ_INS_VCDGB = 1717 , SYSZ_INS_VCDLG = 1718 , SYSZ_INS_VCDLGB = 1719 , SYSZ_INS_VCEQ = 1720 , SYSZ_INS_VCEQB = 1721 , SYSZ_INS_VCEQBS = 1722 , SYSZ_INS_VCEQF = 1723 , SYSZ_INS_VCEQFS = 1724 , SYSZ_INS_VCEQG = 1725 , SYSZ_INS_VCEQGS = 1726 , SYSZ_INS_VCEQH = 1727 , SYSZ_INS_VCEQHS = 1728 , SYSZ_INS_VCGD = 1729 , SYSZ_INS_VCGDB = 1730 , SYSZ_INS_VCH = 1731 , SYSZ_INS_VCHB = 1732 , SYSZ_INS_VCHBS = 1733 , SYSZ_INS_VCHF = 1734 , SYSZ_INS_VCHFS = 1735 , SYSZ_INS_VCHG = 1736 , SYSZ_INS_VCHGS = 1737 , SYSZ_INS_VCHH = 1738 , SYSZ_INS_VCHHS = 1739 , SYSZ_INS_VCHL = 1740 , SYSZ_INS_VCHLB = 1741 , SYSZ_INS_VCHLBS = 1742 , SYSZ_INS_VCHLF = 1743 , SYSZ_INS_VCHLFS = 1744 , SYSZ_INS_VCHLG = 1745 , SYSZ_INS_VCHLGS = 1746 , SYSZ_INS_VCHLH = 1747 , SYSZ_INS_VCHLHS = 1748 , SYSZ_INS_VCKSM = 1749 , SYSZ_INS_VCLGD = 1750 , SYSZ_INS_VCLGDB = 1751 , SYSZ_INS_VCLZ = 1752 , SYSZ_INS_VCLZB = 1753 , SYSZ_INS_VCLZF = 1754 , SYSZ_INS_VCLZG = 1755 , SYSZ_INS_VCLZH = 1756 , SYSZ_INS_VCP = 1757 , SYSZ_INS_VCTZ = 1758 , SYSZ_INS_VCTZB = 1759 , SYSZ_INS_VCTZF = 1760 , SYSZ_INS_VCTZG = 1761 , SYSZ_INS_VCTZH = 1762 , SYSZ_INS_VCVB = 1763 , SYSZ_INS_VCVBG = 1764 , SYSZ_INS_VCVD = 1765 , SYSZ_INS_VCVDG = 1766 , SYSZ_INS_VDP = 1767 , SYSZ_INS_VEC = 1768 , SYSZ_INS_VECB = 1769 , SYSZ_INS_VECF = 1770 , SYSZ_INS_VECG = 1771 , SYSZ_INS_VECH = 1772 , SYSZ_INS_VECL = 1773 , SYSZ_INS_VECLB = 1774 , SYSZ_INS_VECLF = 1775 , SYSZ_INS_VECLG = 1776 , SYSZ_INS_VECLH = 1777 , SYSZ_INS_VERIM = 1778 , SYSZ_INS_VERIMB = 1779 , SYSZ_INS_VERIMF = 1780 , SYSZ_INS_VERIMG = 1781 , SYSZ_INS_VERIMH = 1782 , SYSZ_INS_VERLL = 1783 , SYSZ_INS_VERLLB = 1784 , SYSZ_INS_VERLLF = 1785 , SYSZ_INS_VERLLG = 1786 , SYSZ_INS_VERLLH = 1787 , SYSZ_INS_VERLLV = 1788 , SYSZ_INS_VERLLVB = 1789 , SYSZ_INS_VERLLVF = 1790 , SYSZ_INS_VERLLVG = 1791 , SYSZ_INS_VERLLVH = 1792 , SYSZ_INS_VESL = 1793 , SYSZ_INS_VESLB = 1794 , SYSZ_INS_VESLF = 1795 , SYSZ_INS_VESLG = 1796 , SYSZ_INS_VESLH = 1797 , SYSZ_INS_VESLV = 1798 , SYSZ_INS_VESLVB = 1799 , SYSZ_INS_VESLVF = 1800 , SYSZ_INS_VESLVG = 1801 , SYSZ_INS_VESLVH = 1802 , SYSZ_INS_VESRA = 1803 , SYSZ_INS_VESRAB = 1804 , SYSZ_INS_VESRAF = 1805 , SYSZ_INS_VESRAG = 1806 , SYSZ_INS_VESRAH = 1807 , SYSZ_INS_VESRAV = 1808 , SYSZ_INS_VESRAVB = 1809 , SYSZ_INS_VESRAVF = 1810 , SYSZ_INS_VESRAVG = 1811 , SYSZ_INS_VESRAVH = 1812 , SYSZ_INS_VESRL = 1813 , SYSZ_INS_VESRLB = 1814 , SYSZ_INS_VESRLF = 1815 , SYSZ_INS_VESRLG = 1816 , SYSZ_INS_VESRLH = 1817 , SYSZ_INS_VESRLV = 1818 , SYSZ_INS_VESRLVB = 1819 , SYSZ_INS_VESRLVF = 1820 , SYSZ_INS_VESRLVG = 1821 , SYSZ_INS_VESRLVH = 1822 , SYSZ_INS_VFA = 1823 , SYSZ_INS_VFADB = 1824 , SYSZ_INS_VFAE = 1825 , SYSZ_INS_VFAEB = 1826 , SYSZ_INS_VFAEBS = 1827 , SYSZ_INS_VFAEF = 1828 , SYSZ_INS_VFAEFS = 1829 , SYSZ_INS_VFAEH = 1830 , SYSZ_INS_VFAEHS = 1831 , SYSZ_INS_VFAEZB = 1832 , SYSZ_INS_VFAEZBS = 1833 , SYSZ_INS_VFAEZF = 1834 , SYSZ_INS_VFAEZFS = 1835 , SYSZ_INS_VFAEZH = 1836 , SYSZ_INS_VFAEZHS = 1837 , SYSZ_INS_VFASB = 1838 , SYSZ_INS_VFCE = 1839 , SYSZ_INS_VFCEDB = 1840 , SYSZ_INS_VFCEDBS = 1841 , SYSZ_INS_VFCESB = 1842 , SYSZ_INS_VFCESBS = 1843 , SYSZ_INS_VFCH = 1844 , SYSZ_INS_VFCHDB = 1845 , SYSZ_INS_VFCHDBS = 1846 , SYSZ_INS_VFCHE = 1847 , SYSZ_INS_VFCHEDB = 1848 , SYSZ_INS_VFCHEDBS = 1849 , SYSZ_INS_VFCHESB = 1850 , SYSZ_INS_VFCHESBS = 1851 , SYSZ_INS_VFCHSB = 1852 , SYSZ_INS_VFCHSBS = 1853 , SYSZ_INS_VFD = 1854 , SYSZ_INS_VFDDB = 1855 , SYSZ_INS_VFDSB = 1856 , SYSZ_INS_VFEE = 1857 , SYSZ_INS_VFEEB = 1858 , SYSZ_INS_VFEEBS = 1859 , SYSZ_INS_VFEEF = 1860 , SYSZ_INS_VFEEFS = 1861 , SYSZ_INS_VFEEH = 1862 , SYSZ_INS_VFEEHS = 1863 , SYSZ_INS_VFEEZB = 1864 , SYSZ_INS_VFEEZBS = 1865 , SYSZ_INS_VFEEZF = 1866 , SYSZ_INS_VFEEZFS = 1867 , SYSZ_INS_VFEEZH = 1868 , SYSZ_INS_VFEEZHS = 1869 , SYSZ_INS_VFENE = 1870 , SYSZ_INS_VFENEB = 1871 , SYSZ_INS_VFENEBS = 1872 , SYSZ_INS_VFENEF = 1873 , SYSZ_INS_VFENEFS = 1874 , SYSZ_INS_VFENEH = 1875 , SYSZ_INS_VFENEHS = 1876 , SYSZ_INS_VFENEZB = 1877 , SYSZ_INS_VFENEZBS = 1878 , SYSZ_INS_VFENEZF = 1879 , SYSZ_INS_VFENEZFS = 1880 , SYSZ_INS_VFENEZH = 1881 , SYSZ_INS_VFENEZHS = 1882 , SYSZ_INS_VFI = 1883 , SYSZ_INS_VFIDB = 1884 , SYSZ_INS_VFISB = 1885 , SYSZ_INS_VFKEDB = 1886 , SYSZ_INS_VFKEDBS = 1887 , SYSZ_INS_VFKESB = 1888 , SYSZ_INS_VFKESBS = 1889 , SYSZ_INS_VFKHDB = 1890 , SYSZ_INS_VFKHDBS = 1891 , SYSZ_INS_VFKHEDB = 1892 , SYSZ_INS_VFKHEDBS = 1893 , SYSZ_INS_VFKHESB = 1894 , SYSZ_INS_VFKHESBS = 1895 , SYSZ_INS_VFKHSB = 1896 , SYSZ_INS_VFKHSBS = 1897 , SYSZ_INS_VFLCDB = 1898 , SYSZ_INS_VFLCSB = 1899 , SYSZ_INS_VFLL = 1900 , SYSZ_INS_VFLLS = 1901 , SYSZ_INS_VFLNDB = 1902 , SYSZ_INS_VFLNSB = 1903 , SYSZ_INS_VFLPDB = 1904 , SYSZ_INS_VFLPSB = 1905 , SYSZ_INS_VFLR = 1906 , SYSZ_INS_VFLRD = 1907 , SYSZ_INS_VFM = 1908 , SYSZ_INS_VFMA = 1909 , SYSZ_INS_VFMADB = 1910 , SYSZ_INS_VFMASB = 1911 , SYSZ_INS_VFMAX = 1912 , SYSZ_INS_VFMAXDB = 1913 , SYSZ_INS_VFMAXSB = 1914 , SYSZ_INS_VFMDB = 1915 , SYSZ_INS_VFMIN = 1916 , SYSZ_INS_VFMINDB = 1917 , SYSZ_INS_VFMINSB = 1918 , SYSZ_INS_VFMS = 1919 , SYSZ_INS_VFMSB = 1920 , SYSZ_INS_VFMSDB = 1921 , SYSZ_INS_VFMSSB = 1922 , SYSZ_INS_VFNMA = 1923 , SYSZ_INS_VFNMADB = 1924 , SYSZ_INS_VFNMASB = 1925 , SYSZ_INS_VFNMS = 1926 , SYSZ_INS_VFNMSDB = 1927 , SYSZ_INS_VFNMSSB = 1928 , SYSZ_INS_VFPSO = 1929 , SYSZ_INS_VFPSODB = 1930 , SYSZ_INS_VFPSOSB = 1931 , SYSZ_INS_VFS = 1932 , SYSZ_INS_VFSDB = 1933 , SYSZ_INS_VFSQ = 1934 , SYSZ_INS_VFSQDB = 1935 , SYSZ_INS_VFSQSB = 1936 , SYSZ_INS_VFSSB = 1937 , SYSZ_INS_VFTCI = 1938 , SYSZ_INS_VFTCIDB = 1939 , SYSZ_INS_VFTCISB = 1940 , SYSZ_INS_VGBM = 1941 , SYSZ_INS_VGEF = 1942 , SYSZ_INS_VGEG = 1943 , SYSZ_INS_VGFM = 1944 , SYSZ_INS_VGFMA = 1945 , SYSZ_INS_VGFMAB = 1946 , SYSZ_INS_VGFMAF = 1947 , SYSZ_INS_VGFMAG = 1948 , SYSZ_INS_VGFMAH = 1949 , SYSZ_INS_VGFMB = 1950 , SYSZ_INS_VGFMF = 1951 , SYSZ_INS_VGFMG = 1952 , SYSZ_INS_VGFMH = 1953 , SYSZ_INS_VGM = 1954 , SYSZ_INS_VGMB = 1955 , SYSZ_INS_VGMF = 1956 , SYSZ_INS_VGMG = 1957 , SYSZ_INS_VGMH = 1958 , SYSZ_INS_VISTR = 1959 , SYSZ_INS_VISTRB = 1960 , SYSZ_INS_VISTRBS = 1961 , SYSZ_INS_VISTRF = 1962 , SYSZ_INS_VISTRFS = 1963 , SYSZ_INS_VISTRH = 1964 , SYSZ_INS_VISTRHS = 1965 , SYSZ_INS_VL = 1966 , SYSZ_INS_VLBB = 1967 , SYSZ_INS_VLC = 1968 , SYSZ_INS_VLCB = 1969 , SYSZ_INS_VLCF = 1970 , SYSZ_INS_VLCG = 1971 , SYSZ_INS_VLCH = 1972 , SYSZ_INS_VLDE = 1973 , SYSZ_INS_VLDEB = 1974 , SYSZ_INS_VLEB = 1975 , SYSZ_INS_VLED = 1976 , SYSZ_INS_VLEDB = 1977 , SYSZ_INS_VLEF = 1978 , SYSZ_INS_VLEG = 1979 , SYSZ_INS_VLEH = 1980 , SYSZ_INS_VLEIB = 1981 , SYSZ_INS_VLEIF = 1982 , SYSZ_INS_VLEIG = 1983 , SYSZ_INS_VLEIH = 1984 , SYSZ_INS_VLGV = 1985 , SYSZ_INS_VLGVB = 1986 , SYSZ_INS_VLGVF = 1987 , SYSZ_INS_VLGVG = 1988 , SYSZ_INS_VLGVH = 1989 , SYSZ_INS_VLIP = 1990 , SYSZ_INS_VLL = 1991 , SYSZ_INS_VLLEZ = 1992 , SYSZ_INS_VLLEZB = 1993 , SYSZ_INS_VLLEZF = 1994 , SYSZ_INS_VLLEZG = 1995 , SYSZ_INS_VLLEZH = 1996 , SYSZ_INS_VLLEZLF = 1997 , SYSZ_INS_VLM = 1998 , SYSZ_INS_VLP = 1999 , SYSZ_INS_VLPB = 2000 , SYSZ_INS_VLPF = 2001 , SYSZ_INS_VLPG = 2002 , SYSZ_INS_VLPH = 2003 , SYSZ_INS_VLR = 2004 , SYSZ_INS_VLREP = 2005 , SYSZ_INS_VLREPB = 2006 , SYSZ_INS_VLREPF = 2007 , SYSZ_INS_VLREPG = 2008 , SYSZ_INS_VLREPH = 2009 , SYSZ_INS_VLRL = 2010 , SYSZ_INS_VLRLR = 2011 , SYSZ_INS_VLVG = 2012 , SYSZ_INS_VLVGB = 2013 , SYSZ_INS_VLVGF = 2014 , SYSZ_INS_VLVGG = 2015 , SYSZ_INS_VLVGH = 2016 , SYSZ_INS_VLVGP = 2017 , SYSZ_INS_VMAE = 2018 , SYSZ_INS_VMAEB = 2019 , SYSZ_INS_VMAEF = 2020 , SYSZ_INS_VMAEH = 2021 , SYSZ_INS_VMAH = 2022 , SYSZ_INS_VMAHB = 2023 , SYSZ_INS_VMAHF = 2024 , SYSZ_INS_VMAHH = 2025 , SYSZ_INS_VMAL = 2026 , SYSZ_INS_VMALB = 2027 , SYSZ_INS_VMALE = 2028 , SYSZ_INS_VMALEB = 2029 , SYSZ_INS_VMALEF = 2030 , SYSZ_INS_VMALEH = 2031 , SYSZ_INS_VMALF = 2032 , SYSZ_INS_VMALH = 2033 , SYSZ_INS_VMALHB = 2034 , SYSZ_INS_VMALHF = 2035 , SYSZ_INS_VMALHH = 2036 , SYSZ_INS_VMALHW = 2037 , SYSZ_INS_VMALO = 2038 , SYSZ_INS_VMALOB = 2039 , SYSZ_INS_VMALOF = 2040 , SYSZ_INS_VMALOH = 2041 , SYSZ_INS_VMAO = 2042 , SYSZ_INS_VMAOB = 2043 , SYSZ_INS_VMAOF = 2044 , SYSZ_INS_VMAOH = 2045 , SYSZ_INS_VME = 2046 , SYSZ_INS_VMEB = 2047 , SYSZ_INS_VMEF = 2048 , SYSZ_INS_VMEH = 2049 , SYSZ_INS_VMH = 2050 , SYSZ_INS_VMHB = 2051 , SYSZ_INS_VMHF = 2052 , SYSZ_INS_VMHH = 2053 , SYSZ_INS_VML = 2054 , SYSZ_INS_VMLB = 2055 , SYSZ_INS_VMLE = 2056 , SYSZ_INS_VMLEB = 2057 , SYSZ_INS_VMLEF = 2058 , SYSZ_INS_VMLEH = 2059 , SYSZ_INS_VMLF = 2060 , SYSZ_INS_VMLH = 2061 , SYSZ_INS_VMLHB = 2062 , SYSZ_INS_VMLHF = 2063 , SYSZ_INS_VMLHH = 2064 , SYSZ_INS_VMLHW = 2065 , SYSZ_INS_VMLO = 2066 , SYSZ_INS_VMLOB = 2067 , SYSZ_INS_VMLOF = 2068 , SYSZ_INS_VMLOH = 2069 , SYSZ_INS_VMN = 2070 , SYSZ_INS_VMNB = 2071 , SYSZ_INS_VMNF = 2072 , SYSZ_INS_VMNG = 2073 , SYSZ_INS_VMNH = 2074 , SYSZ_INS_VMNL = 2075 , SYSZ_INS_VMNLB = 2076 , SYSZ_INS_VMNLF = 2077 , SYSZ_INS_VMNLG = 2078 , SYSZ_INS_VMNLH = 2079 , SYSZ_INS_VMO = 2080 , SYSZ_INS_VMOB = 2081 , SYSZ_INS_VMOF = 2082 , SYSZ_INS_VMOH = 2083 , SYSZ_INS_VMP = 2084 , SYSZ_INS_VMRH = 2085 , SYSZ_INS_VMRHB = 2086 , SYSZ_INS_VMRHF = 2087 , SYSZ_INS_VMRHG = 2088 , SYSZ_INS_VMRHH = 2089 , SYSZ_INS_VMRL = 2090 , SYSZ_INS_VMRLB = 2091 , SYSZ_INS_VMRLF = 2092 , SYSZ_INS_VMRLG = 2093 , SYSZ_INS_VMRLH = 2094 , SYSZ_INS_VMSL = 2095 , SYSZ_INS_VMSLG = 2096 , SYSZ_INS_VMSP = 2097 , SYSZ_INS_VMX = 2098 , SYSZ_INS_VMXB = 2099 , SYSZ_INS_VMXF = 2100 , SYSZ_INS_VMXG = 2101 , SYSZ_INS_VMXH = 2102 , SYSZ_INS_VMXL = 2103 , SYSZ_INS_VMXLB = 2104 , SYSZ_INS_VMXLF = 2105 , SYSZ_INS_VMXLG = 2106 , SYSZ_INS_VMXLH = 2107 , SYSZ_INS_VN = 2108 , SYSZ_INS_VNC = 2109 , SYSZ_INS_VNN = 2110 , SYSZ_INS_VNO = 2111 , SYSZ_INS_VNX = 2112 , SYSZ_INS_VO = 2113 , SYSZ_INS_VOC = 2114 , SYSZ_INS_VONE = 2115 , SYSZ_INS_VPDI = 2116 , SYSZ_INS_VPERM = 2117 , SYSZ_INS_VPK = 2118 , SYSZ_INS_VPKF = 2119 , SYSZ_INS_VPKG = 2120 , SYSZ_INS_VPKH = 2121 , SYSZ_INS_VPKLS = 2122 , SYSZ_INS_VPKLSF = 2123 , SYSZ_INS_VPKLSFS = 2124 , SYSZ_INS_VPKLSG = 2125 , SYSZ_INS_VPKLSGS = 2126 , SYSZ_INS_VPKLSH = 2127 , SYSZ_INS_VPKLSHS = 2128 , SYSZ_INS_VPKS = 2129 , SYSZ_INS_VPKSF = 2130 , SYSZ_INS_VPKSFS = 2131 , SYSZ_INS_VPKSG = 2132 , SYSZ_INS_VPKSGS = 2133 , SYSZ_INS_VPKSH = 2134 , SYSZ_INS_VPKSHS = 2135 , SYSZ_INS_VPKZ = 2136 , SYSZ_INS_VPOPCT = 2137 , SYSZ_INS_VPOPCTB = 2138 , SYSZ_INS_VPOPCTF = 2139 , SYSZ_INS_VPOPCTG = 2140 , SYSZ_INS_VPOPCTH = 2141 , SYSZ_INS_VPSOP = 2142 , SYSZ_INS_VREP = 2143 , SYSZ_INS_VREPB = 2144 , SYSZ_INS_VREPF = 2145 , SYSZ_INS_VREPG = 2146 , SYSZ_INS_VREPH = 2147 , SYSZ_INS_VREPI = 2148 , SYSZ_INS_VREPIB = 2149 , SYSZ_INS_VREPIF = 2150 , SYSZ_INS_VREPIG = 2151 , SYSZ_INS_VREPIH = 2152 , SYSZ_INS_VRP = 2153 , SYSZ_INS_VS = 2154 , SYSZ_INS_VSB = 2155 , SYSZ_INS_VSBCBI = 2156 , SYSZ_INS_VSBCBIQ = 2157 , SYSZ_INS_VSBI = 2158 , SYSZ_INS_VSBIQ = 2159 , SYSZ_INS_VSCBI = 2160 , SYSZ_INS_VSCBIB = 2161 , SYSZ_INS_VSCBIF = 2162 , SYSZ_INS_VSCBIG = 2163 , SYSZ_INS_VSCBIH = 2164 , SYSZ_INS_VSCBIQ = 2165 , SYSZ_INS_VSCEF = 2166 , SYSZ_INS_VSCEG = 2167 , SYSZ_INS_VSDP = 2168 , SYSZ_INS_VSEG = 2169 , SYSZ_INS_VSEGB = 2170 , SYSZ_INS_VSEGF = 2171 , SYSZ_INS_VSEGH = 2172 , SYSZ_INS_VSEL = 2173 , SYSZ_INS_VSF = 2174 , SYSZ_INS_VSG = 2175 , SYSZ_INS_VSH = 2176 , SYSZ_INS_VSL = 2177 , SYSZ_INS_VSLB = 2178 , SYSZ_INS_VSLDB = 2179 , SYSZ_INS_VSP = 2180 , SYSZ_INS_VSQ = 2181 , SYSZ_INS_VSRA = 2182 , SYSZ_INS_VSRAB = 2183 , SYSZ_INS_VSRL = 2184 , SYSZ_INS_VSRLB = 2185 , SYSZ_INS_VSRP = 2186 , SYSZ_INS_VST = 2187 , SYSZ_INS_VSTEB = 2188 , SYSZ_INS_VSTEF = 2189 , SYSZ_INS_VSTEG = 2190 , SYSZ_INS_VSTEH = 2191 , SYSZ_INS_VSTL = 2192 , SYSZ_INS_VSTM = 2193 , SYSZ_INS_VSTRC = 2194 , SYSZ_INS_VSTRCB = 2195 , SYSZ_INS_VSTRCBS = 2196 , SYSZ_INS_VSTRCF = 2197 , SYSZ_INS_VSTRCFS = 2198 , SYSZ_INS_VSTRCH = 2199 , SYSZ_INS_VSTRCHS = 2200 , SYSZ_INS_VSTRCZB = 2201 , SYSZ_INS_VSTRCZBS = 2202 , SYSZ_INS_VSTRCZF = 2203 , SYSZ_INS_VSTRCZFS = 2204 , SYSZ_INS_VSTRCZH = 2205 , SYSZ_INS_VSTRCZHS = 2206 , SYSZ_INS_VSTRL = 2207 , SYSZ_INS_VSTRLR = 2208 , SYSZ_INS_VSUM = 2209 , SYSZ_INS_VSUMB = 2210 , SYSZ_INS_VSUMG = 2211 , SYSZ_INS_VSUMGF = 2212 , SYSZ_INS_VSUMGH = 2213 , SYSZ_INS_VSUMH = 2214 , SYSZ_INS_VSUMQ = 2215 , SYSZ_INS_VSUMQF = 2216 , SYSZ_INS_VSUMQG = 2217 , SYSZ_INS_VTM = 2218 , SYSZ_INS_VTP = 2219 , SYSZ_INS_VUPH = 2220 , SYSZ_INS_VUPHB = 2221 , SYSZ_INS_VUPHF = 2222 , SYSZ_INS_VUPHH = 2223 , SYSZ_INS_VUPKZ = 2224 , SYSZ_INS_VUPL = 2225 , SYSZ_INS_VUPLB = 2226 , SYSZ_INS_VUPLF = 2227 , SYSZ_INS_VUPLH = 2228 , SYSZ_INS_VUPLHB = 2229 , SYSZ_INS_VUPLHF = 2230 , SYSZ_INS_VUPLHH = 2231 , SYSZ_INS_VUPLHW = 2232 , SYSZ_INS_VUPLL = 2233 , SYSZ_INS_VUPLLB = 2234 , SYSZ_INS_VUPLLF = 2235 , SYSZ_INS_VUPLLH = 2236 , SYSZ_INS_VX = 2237 , SYSZ_INS_VZERO = 2238 , SYSZ_INS_WCDGB = 2239 , SYSZ_INS_WCDLGB = 2240 , SYSZ_INS_WCGDB = 2241 , SYSZ_INS_WCLGDB = 2242 , SYSZ_INS_WFADB = 2243 , SYSZ_INS_WFASB = 2244 , SYSZ_INS_WFAXB = 2245 , SYSZ_INS_WFC = 2246 , SYSZ_INS_WFCDB = 2247 , SYSZ_INS_WFCEDB = 2248 , SYSZ_INS_WFCEDBS = 2249 , SYSZ_INS_WFCESB = 2250 , SYSZ_INS_WFCESBS = 2251 , SYSZ_INS_WFCEXB = 2252 , SYSZ_INS_WFCEXBS = 2253 , SYSZ_INS_WFCHDB = 2254 , SYSZ_INS_WFCHDBS = 2255 , SYSZ_INS_WFCHEDB = 2256 , SYSZ_INS_WFCHEDBS = 2257 , SYSZ_INS_WFCHESB = 2258 , SYSZ_INS_WFCHESBS = 2259 , SYSZ_INS_WFCHEXB = 2260 , SYSZ_INS_WFCHEXBS = 2261 , SYSZ_INS_WFCHSB = 2262 , SYSZ_INS_WFCHSBS = 2263 , SYSZ_INS_WFCHXB = 2264 , SYSZ_INS_WFCHXBS = 2265 , SYSZ_INS_WFCSB = 2266 , SYSZ_INS_WFCXB = 2267 , SYSZ_INS_WFDDB = 2268 , SYSZ_INS_WFDSB = 2269 , SYSZ_INS_WFDXB = 2270 , SYSZ_INS_WFIDB = 2271 , SYSZ_INS_WFISB = 2272 , SYSZ_INS_WFIXB = 2273 , SYSZ_INS_WFK = 2274 , SYSZ_INS_WFKDB = 2275 , SYSZ_INS_WFKEDB = 2276 , SYSZ_INS_WFKEDBS = 2277 , SYSZ_INS_WFKESB = 2278 , SYSZ_INS_WFKESBS = 2279 , SYSZ_INS_WFKEXB = 2280 , SYSZ_INS_WFKEXBS = 2281 , SYSZ_INS_WFKHDB = 2282 , SYSZ_INS_WFKHDBS = 2283 , SYSZ_INS_WFKHEDB = 2284 , SYSZ_INS_WFKHEDBS = 2285 , SYSZ_INS_WFKHESB = 2286 , SYSZ_INS_WFKHESBS = 2287 , SYSZ_INS_WFKHEXB = 2288 , SYSZ_INS_WFKHEXBS = 2289 , SYSZ_INS_WFKHSB = 2290 , SYSZ_INS_WFKHSBS = 2291 , SYSZ_INS_WFKHXB = 2292 , SYSZ_INS_WFKHXBS = 2293 , SYSZ_INS_WFKSB = 2294 , SYSZ_INS_WFKXB = 2295 , SYSZ_INS_WFLCDB = 2296 , SYSZ_INS_WFLCSB = 2297 , SYSZ_INS_WFLCXB = 2298 , SYSZ_INS_WFLLD = 2299 , SYSZ_INS_WFLLS = 2300 , SYSZ_INS_WFLNDB = 2301 , SYSZ_INS_WFLNSB = 2302 , SYSZ_INS_WFLNXB = 2303 , SYSZ_INS_WFLPDB = 2304 , SYSZ_INS_WFLPSB = 2305 , SYSZ_INS_WFLPXB = 2306 , SYSZ_INS_WFLRD = 2307 , SYSZ_INS_WFLRX = 2308 , SYSZ_INS_WFMADB = 2309 , SYSZ_INS_WFMASB = 2310 , SYSZ_INS_WFMAXB = 2311 , SYSZ_INS_WFMAXDB = 2312 , SYSZ_INS_WFMAXSB = 2313 , SYSZ_INS_WFMAXXB = 2314 , SYSZ_INS_WFMDB = 2315 , SYSZ_INS_WFMINDB = 2316 , SYSZ_INS_WFMINSB = 2317 , SYSZ_INS_WFMINXB = 2318 , SYSZ_INS_WFMSB = 2319 , SYSZ_INS_WFMSDB = 2320 , SYSZ_INS_WFMSSB = 2321 , SYSZ_INS_WFMSXB = 2322 , SYSZ_INS_WFMXB = 2323 , SYSZ_INS_WFNMADB = 2324 , SYSZ_INS_WFNMASB = 2325 , SYSZ_INS_WFNMAXB = 2326 , SYSZ_INS_WFNMSDB = 2327 , SYSZ_INS_WFNMSSB = 2328 , SYSZ_INS_WFNMSXB = 2329 , SYSZ_INS_WFPSODB = 2330 , SYSZ_INS_WFPSOSB = 2331 , SYSZ_INS_WFPSOXB = 2332 , SYSZ_INS_WFSDB = 2333 , SYSZ_INS_WFSQDB = 2334 , SYSZ_INS_WFSQSB = 2335 , SYSZ_INS_WFSQXB = 2336 , SYSZ_INS_WFSSB = 2337 , SYSZ_INS_WFSXB = 2338 , SYSZ_INS_WFTCIDB = 2339 , SYSZ_INS_WFTCISB = 2340 , SYSZ_INS_WFTCIXB = 2341 , SYSZ_INS_WLDEB = 2342 , SYSZ_INS_WLEDB = 2343 , SYSZ_INS_XSCH = 2344 , SYSZ_INS_ZAP = 2345 , SYSZ_INS_ENDING = 2346 , } # [repr (u32)] # [doc = " Group of SystemZ instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn_group { # [doc = "< = CS_GRP_INVALID"] SYSZ_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SYSZ_GRP_JUMP = 1 , SYSZ_GRP_DISTINCTOPS = 128 , SYSZ_GRP_FPEXTENSION = 129 , SYSZ_GRP_HIGHWORD = 130 , SYSZ_GRP_INTERLOCKEDACCESS1 = 131 , SYSZ_GRP_LOADSTOREONCOND = 132 , SYSZ_GRP_DFPPACKEDCONVERSION = 133 , SYSZ_GRP_DFPZONEDCONVERSION = 134 , SYSZ_GRP_ENHANCEDDAT2 = 135 , SYSZ_GRP_EXECUTIONHINT = 136 , SYSZ_GRP_GUARDEDSTORAGE = 137 , SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 , SYSZ_GRP_LOADANDTRAP = 139 , SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 , SYSZ_GRP_LOADSTOREONCOND2 = 141 , SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 , SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 , SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 , SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 , SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 , SYSZ_GRP_NOVECTOR = 149 , SYSZ_GRP_POPULATIONCOUNT = 150 , SYSZ_GRP_PROCESSORASSIST = 151 , SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 , SYSZ_GRP_TRANSACTIONALEXECUTION = 153 , SYSZ_GRP_VECTOR = 154 , SYSZ_GRP_VECTORENHANCEMENTS1 = 155 , SYSZ_GRP_VECTORPACKEDDECIMAL = 156 , SYSZ_GRP_ENDING = 157 , } # [repr (u32)] # [doc = " X86 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_reg { X86_REG_INVALID = 0 , X86_REG_AH = 1 , X86_REG_AL = 2 , X86_REG_AX = 3 , X86_REG_BH = 4 , X86_REG_BL = 5 , X86_REG_BP = 6 , X86_REG_BPL = 7 , X86_REG_BX = 8 , X86_REG_CH = 9 , X86_REG_CL = 10 , X86_REG_CS = 11 , X86_REG_CX = 12 , X86_REG_DH = 13 , X86_REG_DI = 14 , X86_REG_DIL = 15 , X86_REG_DL = 16 , X86_REG_DS = 17 , X86_REG_DX = 18 , X86_REG_EAX = 19 , X86_REG_EBP = 20 , X86_REG_EBX = 21 , X86_REG_ECX = 22 , X86_REG_EDI = 23 , X86_REG_EDX = 24 , X86_REG_EFLAGS = 25 , X86_REG_EIP = 26 , X86_REG_EIZ = 27 , X86_REG_ES = 28 , X86_REG_ESI = 29 , X86_REG_ESP = 30 , X86_REG_FPSW = 31 , X86_REG_FS = 32 , X86_REG_GS = 33 , X86_REG_IP = 34 , X86_REG_RAX = 35 , X86_REG_RBP = 36 , X86_REG_RBX = 37 , X86_REG_RCX = 38 , X86_REG_RDI = 39 , X86_REG_RDX = 40 , X86_REG_RIP = 41 , X86_REG_RIZ = 42 , X86_REG_RSI = 43 , X86_REG_RSP = 44 , X86_REG_SI = 45 , X86_REG_SIL = 46 , X86_REG_SP = 47 , X86_REG_SPL = 48 , X86_REG_SS = 49 , X86_REG_CR0 = 50 , X86_REG_CR1 = 51 , X86_REG_CR2 = 52 , X86_REG_CR3 = 53 , X86_REG_CR4 = 54 , X86_REG_CR5 = 55 , X86_REG_CR6 = 56 , X86_REG_CR7 = 57 , X86_REG_CR8 = 58 , X86_REG_CR9 = 59 , X86_REG_CR10 = 60 , X86_REG_CR11 = 61 , X86_REG_CR12 = 62 , X86_REG_CR13 = 63 , X86_REG_CR14 = 64 , X86_REG_CR15 = 65 , X86_REG_DR0 = 66 , X86_REG_DR1 = 67 , X86_REG_DR2 = 68 , X86_REG_DR3 = 69 , X86_REG_DR4 = 70 , X86_REG_DR5 = 71 , X86_REG_DR6 = 72 , X86_REG_DR7 = 73 , X86_REG_DR8 = 74 , X86_REG_DR9 = 75 , X86_REG_DR10 = 76 , X86_REG_DR11 = 77 , X86_REG_DR12 = 78 , X86_REG_DR13 = 79 , X86_REG_DR14 = 80 , X86_REG_DR15 = 81 , X86_REG_FP0 = 82 , X86_REG_FP1 = 83 , X86_REG_FP2 = 84 , X86_REG_FP3 = 85 , X86_REG_FP4 = 86 , X86_REG_FP5 = 87 , X86_REG_FP6 = 88 , X86_REG_FP7 = 89 , X86_REG_K0 = 90 , X86_REG_K1 = 91 , X86_REG_K2 = 92 , X86_REG_K3 = 93 , X86_REG_K4 = 94 , X86_REG_K5 = 95 , X86_REG_K6 = 96 , X86_REG_K7 = 97 , X86_REG_MM0 = 98 , X86_REG_MM1 = 99 , X86_REG_MM2 = 100 , X86_REG_MM3 = 101 , X86_REG_MM4 = 102 , X86_REG_MM5 = 103 , X86_REG_MM6 = 104 , X86_REG_MM7 = 105 , X86_REG_R8 = 106 , X86_REG_R9 = 107 , X86_REG_R10 = 108 , X86_REG_R11 = 109 , X86_REG_R12 = 110 , X86_REG_R13 = 111 , X86_REG_R14 = 112 , X86_REG_R15 = 113 , X86_REG_ST0 = 114 , X86_REG_ST1 = 115 , X86_REG_ST2 = 116 , X86_REG_ST3 = 117 , X86_REG_ST4 = 118 , X86_REG_ST5 = 119 , X86_REG_ST6 = 120 , X86_REG_ST7 = 121 , X86_REG_XMM0 = 122 , X86_REG_XMM1 = 123 , X86_REG_XMM2 = 124 , X86_REG_XMM3 = 125 , X86_REG_XMM4 = 126 , X86_REG_XMM5 = 127 , X86_REG_XMM6 = 128 , X86_REG_XMM7 = 129 , X86_REG_XMM8 = 130 , X86_REG_XMM9 = 131 , X86_REG_XMM10 = 132 , X86_REG_XMM11 = 133 , X86_REG_XMM12 = 134 , X86_REG_XMM13 = 135 , X86_REG_XMM14 = 136 , X86_REG_XMM15 = 137 , X86_REG_XMM16 = 138 , X86_REG_XMM17 = 139 , X86_REG_XMM18 = 140 , X86_REG_XMM19 = 141 , X86_REG_XMM20 = 142 , X86_REG_XMM21 = 143 , X86_REG_XMM22 = 144 , X86_REG_XMM23 = 145 , X86_REG_XMM24 = 146 , X86_REG_XMM25 = 147 , X86_REG_XMM26 = 148 , X86_REG_XMM27 = 149 , X86_REG_XMM28 = 150 , X86_REG_XMM29 = 151 , X86_REG_XMM30 = 152 , X86_REG_XMM31 = 153 , X86_REG_YMM0 = 154 , X86_REG_YMM1 = 155 , X86_REG_YMM2 = 156 , X86_REG_YMM3 = 157 , X86_REG_YMM4 = 158 , X86_REG_YMM5 = 159 , X86_REG_YMM6 = 160 , X86_REG_YMM7 = 161 , X86_REG_YMM8 = 162 , X86_REG_YMM9 = 163 , X86_REG_YMM10 = 164 , X86_REG_YMM11 = 165 , X86_REG_YMM12 = 166 , X86_REG_YMM13 = 167 , X86_REG_YMM14 = 168 , X86_REG_YMM15 = 169 , X86_REG_YMM16 = 170 , X86_REG_YMM17 = 171 , X86_REG_YMM18 = 172 , X86_REG_YMM19 = 173 , X86_REG_YMM20 = 174 , X86_REG_YMM21 = 175 , X86_REG_YMM22 = 176 , X86_REG_YMM23 = 177 , X86_REG_YMM24 = 178 , X86_REG_YMM25 = 179 , X86_REG_YMM26 = 180 , X86_REG_YMM27 = 181 , X86_REG_YMM28 = 182 , X86_REG_YMM29 = 183 , X86_REG_YMM30 = 184 , X86_REG_YMM31 = 185 , X86_REG_ZMM0 = 186 , X86_REG_ZMM1 = 187 , X86_REG_ZMM2 = 188 , X86_REG_ZMM3 = 189 , X86_REG_ZMM4 = 190 , X86_REG_ZMM5 = 191 , X86_REG_ZMM6 = 192 , X86_REG_ZMM7 = 193 , X86_REG_ZMM8 = 194 , X86_REG_ZMM9 = 195 , X86_REG_ZMM10 = 196 , X86_REG_ZMM11 = 197 , X86_REG_ZMM12 = 198 , X86_REG_ZMM13 = 199 , X86_REG_ZMM14 = 200 , X86_REG_ZMM15 = 201 , X86_REG_ZMM16 = 202 , X86_REG_ZMM17 = 203 , X86_REG_ZMM18 = 204 , X86_REG_ZMM19 = 205 , X86_REG_ZMM20 = 206 , X86_REG_ZMM21 = 207 , X86_REG_ZMM22 = 208 , X86_REG_ZMM23 = 209 , X86_REG_ZMM24 = 210 , X86_REG_ZMM25 = 211 , X86_REG_ZMM26 = 212 , X86_REG_ZMM27 = 213 , X86_REG_ZMM28 = 214 , X86_REG_ZMM29 = 215 , X86_REG_ZMM30 = 216 , X86_REG_ZMM31 = 217 , X86_REG_R8B = 218 , X86_REG_R9B = 219 , X86_REG_R10B = 220 , X86_REG_R11B = 221 , X86_REG_R12B = 222 , X86_REG_R13B = 223 , X86_REG_R14B = 224 , X86_REG_R15B = 225 , X86_REG_R8D = 226 , X86_REG_R9D = 227 , X86_REG_R10D = 228 , X86_REG_R11D = 229 , X86_REG_R12D = 230 , X86_REG_R13D = 231 , X86_REG_R14D = 232 , X86_REG_R15D = 233 , X86_REG_R8W = 234 , X86_REG_R9W = 235 , X86_REG_R10W = 236 , X86_REG_R11W = 237 , X86_REG_R12W = 238 , X86_REG_R13W = 239 , X86_REG_R14W = 240 , X86_REG_R15W = 241 , X86_REG_BND0 = 242 , X86_REG_BND1 = 243 , X86_REG_BND2 = 244 , X86_REG_BND3 = 245 , X86_REG_ENDING = 246 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] X86_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] X86_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] X86_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] X86_OP_MEM = 3 , } # [repr (u32)] # [doc = " XOP Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_xop_cc { # [doc = "< Uninitialized."] X86_XOP_CC_INVALID = 0 , X86_XOP_CC_LT = 1 , X86_XOP_CC_LE = 2 , X86_XOP_CC_GT = 3 , X86_XOP_CC_GE = 4 , X86_XOP_CC_EQ = 5 , X86_XOP_CC_NEQ = 6 , X86_XOP_CC_FALSE = 7 , X86_XOP_CC_TRUE = 8 , } # [repr (u32)] # [doc = " AVX broadcast type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_bcast { # [doc = "< Uninitialized."] X86_AVX_BCAST_INVALID = 0 , # [doc = "< AVX512 broadcast type {1to2}"] X86_AVX_BCAST_2 = 1 , # [doc = "< AVX512 broadcast type {1to4}"] X86_AVX_BCAST_4 = 2 , # [doc = "< AVX512 broadcast type {1to8}"] X86_AVX_BCAST_8 = 3 , # [doc = "< AVX512 broadcast type {1to16}"] X86_AVX_BCAST_16 = 4 , } # [repr (u32)] # [doc = " SSE Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_sse_cc { # [doc = "< Uninitialized."] X86_SSE_CC_INVALID = 0 , X86_SSE_CC_EQ = 1 , X86_SSE_CC_LT = 2 , X86_SSE_CC_LE = 3 , X86_SSE_CC_UNORD = 4 , X86_SSE_CC_NEQ = 5 , X86_SSE_CC_NLT = 6 , X86_SSE_CC_NLE = 7 , X86_SSE_CC_ORD = 8 , } # [repr (u32)] # [doc = " AVX Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_cc { # [doc = "< Uninitialized."] X86_AVX_CC_INVALID = 0 , X86_AVX_CC_EQ = 1 , X86_AVX_CC_LT = 2 , X86_AVX_CC_LE = 3 , X86_AVX_CC_UNORD = 4 , X86_AVX_CC_NEQ = 5 , X86_AVX_CC_NLT = 6 , X86_AVX_CC_NLE = 7 , X86_AVX_CC_ORD = 8 , X86_AVX_CC_EQ_UQ = 9 , X86_AVX_CC_NGE = 10 , X86_AVX_CC_NGT = 11 , X86_AVX_CC_FALSE = 12 , X86_AVX_CC_NEQ_OQ = 13 , X86_AVX_CC_GE = 14 , X86_AVX_CC_GT = 15 , X86_AVX_CC_TRUE = 16 , X86_AVX_CC_EQ_OS = 17 , X86_AVX_CC_LT_OQ = 18 , X86_AVX_CC_LE_OQ = 19 , X86_AVX_CC_UNORD_S = 20 , X86_AVX_CC_NEQ_US = 21 , X86_AVX_CC_NLT_UQ = 22 , X86_AVX_CC_NLE_UQ = 23 , X86_AVX_CC_ORD_S = 24 , X86_AVX_CC_EQ_US = 25 , X86_AVX_CC_NGE_UQ = 26 , X86_AVX_CC_NGT_UQ = 27 , X86_AVX_CC_FALSE_OS = 28 , X86_AVX_CC_NEQ_OS = 29 , X86_AVX_CC_GE_OQ = 30 , X86_AVX_CC_GT_OQ = 31 , X86_AVX_CC_TRUE_US = 32 , } # [repr (u32)] # [doc = " AVX static rounding mode type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_rm { # [doc = "< Uninitialized."] X86_AVX_RM_INVALID = 0 , # [doc = "< Round to nearest"] X86_AVX_RM_RN = 1 , # [doc = "< Round down"] X86_AVX_RM_RD = 2 , # [doc = "< Round up"] X86_AVX_RM_RU = 3 , # [doc = "< Round toward zero"] X86_AVX_RM_RZ = 4 , } impl x86_prefix { pub const X86_PREFIX_REPE : x86_prefix = x86_prefix :: X86_PREFIX_REP ; } # [repr (u32)] # [doc = " Instruction prefixes - to be used in cs_x86.prefix[]"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_prefix { # [doc = "< lock (cs_x86.prefix[0]"] X86_PREFIX_LOCK = 240 , # [doc = "< rep (cs_x86.prefix[0]"] X86_PREFIX_REP = 243 , # [doc = "< repne/repnz (cs_x86.prefix[0]"] X86_PREFIX_REPNE = 242 , # [doc = "< segment override CS (cs_x86.prefix[1]"] X86_PREFIX_CS = 46 , # [doc = "< segment override SS (cs_x86.prefix[1]"] X86_PREFIX_SS = 54 , # [doc = "< segment override DS (cs_x86.prefix[1]"] X86_PREFIX_DS = 62 , # [doc = "< segment override ES (cs_x86.prefix[1]"] X86_PREFIX_ES = 38 , # [doc = "< segment override FS (cs_x86.prefix[1]"] X86_PREFIX_FS = 100 , # [doc = "< segment override GS (cs_x86.prefix[1]"] X86_PREFIX_GS = 101 , # [doc = "< operand-size override (cs_x86.prefix[2]"] X86_PREFIX_OPSIZE = 102 , # [doc = "< address-size override (cs_x86.prefix[3]"] X86_PREFIX_ADDRSIZE = 103 , } # [doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct x86_op_mem { # [doc = "< segment register (or X86_REG_INVALID if irrelevant)"] pub segment : x86_reg , # [doc = "< base register (or X86_REG_INVALID if irrelevant)"] pub base : x86_reg , # [doc = "< index register (or X86_REG_INVALID if irrelevant)"] pub index : x86_reg , # [doc = "< scale for index register"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of x86_op_mem"] [:: std :: mem :: size_of :: < x86_op_mem > () - 24usize] ; ["Alignment of x86_op_mem"] [:: std :: mem :: align_of :: < x86_op_mem > () - 8usize] ; ["Offset of field: x86_op_mem::segment"] [:: std :: mem :: offset_of ! (x86_op_mem , segment) - 0usize] ; ["Offset of field: x86_op_mem::base"] [:: std :: mem :: offset_of ! (x86_op_mem , base) - 4usize] ; ["Offset of field: x86_op_mem::index"] [:: std :: mem :: offset_of ! (x86_op_mem , index) - 8usize] ; ["Offset of field: x86_op_mem::scale"] [:: std :: mem :: offset_of ! (x86_op_mem , scale) - 12usize] ; ["Offset of field: x86_op_mem::disp"] [:: std :: mem :: offset_of ! (x86_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86_op { # [doc = "< operand type"] pub type_ : x86_op_type , pub __bindgen_anon_1 : cs_x86_op__bindgen_ty_1 , # [doc = " size of this operand (in bytes)."] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " AVX broadcast type, or 0 if irrelevant"] pub avx_bcast : x86_avx_bcast , # [doc = " AVX zero opmask {z}"] pub avx_zero_opmask : bool , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : x86_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : x86_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op"] [:: std :: mem :: size_of :: < cs_x86_op > () - 48usize] ; ["Alignment of cs_x86_op"] [:: std :: mem :: align_of :: < cs_x86_op > () - 8usize] ; ["Offset of field: cs_x86_op::type_"] [:: std :: mem :: offset_of ! (cs_x86_op , type_) - 0usize] ; ["Offset of field: cs_x86_op::size"] [:: std :: mem :: offset_of ! (cs_x86_op , size) - 32usize] ; ["Offset of field: cs_x86_op::access"] [:: std :: mem :: offset_of ! (cs_x86_op , access) - 33usize] ; ["Offset of field: cs_x86_op::avx_bcast"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_bcast) - 36usize] ; ["Offset of field: cs_x86_op::avx_zero_opmask"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_zero_opmask) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask) } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_x86_encoding { # [doc = " ModR/M offset, or 0 when irrelevant"] pub modrm_offset : u8 , # [doc = " Displacement offset, or 0 when irrelevant."] pub disp_offset : u8 , pub disp_size : u8 , # [doc = " Immediate offset, or 0 when irrelevant."] pub imm_offset : u8 , pub imm_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_encoding"] [:: std :: mem :: size_of :: < cs_x86_encoding > () - 5usize] ; ["Alignment of cs_x86_encoding"] [:: std :: mem :: align_of :: < cs_x86_encoding > () - 1usize] ; ["Offset of field: cs_x86_encoding::modrm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , modrm_offset) - 0usize] ; ["Offset of field: cs_x86_encoding::disp_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_offset) - 1usize] ; ["Offset of field: cs_x86_encoding::disp_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_size) - 2usize] ; ["Offset of field: cs_x86_encoding::imm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_offset) - 3usize] ; ["Offset of field: cs_x86_encoding::imm_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_size) - 4usize] ; } ; # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86 { # [doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"] pub prefix : [u8 ; 4usize] , # [doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."] pub opcode : [u8 ; 4usize] , # [doc = " REX prefix: only a non-zero value is relevant for x86_64"] pub rex : u8 , # [doc = " Address size, which can be overridden with above prefix[5]."] pub addr_size : u8 , # [doc = " ModR/M byte"] pub modrm : u8 , # [doc = " SIB value, or 0 when irrelevant."] pub sib : u8 , # [doc = " Displacement value, valid if encoding.disp_offset != 0"] pub disp : i64 , # [doc = " SIB index register, or X86_REG_INVALID when irrelevant."] pub sib_index : x86_reg , # [doc = " SIB scale, only applicable if sib_index is valid."] pub sib_scale : i8 , # [doc = " SIB base register, or X86_REG_INVALID when irrelevant."] pub sib_base : x86_reg , # [doc = " XOP Code Condition"] pub xop_cc : x86_xop_cc , # [doc = " SSE Code Condition"] pub sse_cc : x86_sse_cc , # [doc = " AVX Code Condition"] pub avx_cc : x86_avx_cc , # [doc = " AVX Suppress all Exception"] pub avx_sae : bool , # [doc = " AVX static rounding mode"] pub avx_rm : x86_avx_rm , pub __bindgen_anon_1 : cs_x86__bindgen_ty_1 , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_x86_op ; 8usize] , # [doc = "< encoding information"] pub encoding : cs_x86_encoding , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86__bindgen_ty_1 { # [doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"] pub eflags : u64 , # [doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"] pub fpu_flags : u64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_x86__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86__bindgen_ty_1::eflags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , eflags) - 0usize] ; ["Offset of field: cs_x86__bindgen_ty_1::fpu_flags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , fpu_flags) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86"] [:: std :: mem :: size_of :: < cs_x86 > () - 464usize] ; ["Alignment of cs_x86"] [:: std :: mem :: align_of :: < cs_x86 > () - 8usize] ; ["Offset of field: cs_x86::prefix"] [:: std :: mem :: offset_of ! (cs_x86 , prefix) - 0usize] ; ["Offset of field: cs_x86::opcode"] [:: std :: mem :: offset_of ! (cs_x86 , opcode) - 4usize] ; ["Offset of field: cs_x86::rex"] [:: std :: mem :: offset_of ! (cs_x86 , rex) - 8usize] ; ["Offset of field: cs_x86::addr_size"] [:: std :: mem :: offset_of ! (cs_x86 , addr_size) - 9usize] ; ["Offset of field: cs_x86::modrm"] [:: std :: mem :: offset_of ! (cs_x86 , modrm) - 10usize] ; ["Offset of field: cs_x86::sib"] [:: std :: mem :: offset_of ! (cs_x86 , sib) - 11usize] ; ["Offset of field: cs_x86::disp"] [:: std :: mem :: offset_of ! (cs_x86 , disp) - 16usize] ; ["Offset of field: cs_x86::sib_index"] [:: std :: mem :: offset_of ! (cs_x86 , sib_index) - 24usize] ; ["Offset of field: cs_x86::sib_scale"] [:: std :: mem :: offset_of ! (cs_x86 , sib_scale) - 28usize] ; ["Offset of field: cs_x86::sib_base"] [:: std :: mem :: offset_of ! (cs_x86 , sib_base) - 32usize] ; ["Offset of field: cs_x86::xop_cc"] [:: std :: mem :: offset_of ! (cs_x86 , xop_cc) - 36usize] ; ["Offset of field: cs_x86::sse_cc"] [:: std :: mem :: offset_of ! (cs_x86 , sse_cc) - 40usize] ; ["Offset of field: cs_x86::avx_cc"] [:: std :: mem :: offset_of ! (cs_x86 , avx_cc) - 44usize] ; ["Offset of field: cs_x86::avx_sae"] [:: std :: mem :: offset_of ! (cs_x86 , avx_sae) - 48usize] ; ["Offset of field: cs_x86::avx_rm"] [:: std :: mem :: offset_of ! (cs_x86 , avx_rm) - 52usize] ; ["Offset of field: cs_x86::op_count"] [:: std :: mem :: offset_of ! (cs_x86 , op_count) - 64usize] ; ["Offset of field: cs_x86::operands"] [:: std :: mem :: offset_of ! (cs_x86 , operands) - 72usize] ; ["Offset of field: cs_x86::encoding"] [:: std :: mem :: offset_of ! (cs_x86 , encoding) - 456usize] ; } ; impl :: std :: fmt :: Debug for cs_x86 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding) } } # [repr (u32)] # [doc = " X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn { X86_INS_INVALID = 0 , X86_INS_AAA = 1 , X86_INS_AAD = 2 , X86_INS_AAM = 3 , X86_INS_AAS = 4 , X86_INS_FABS = 5 , X86_INS_ADC = 6 , X86_INS_ADCX = 7 , X86_INS_ADD = 8 , X86_INS_ADDPD = 9 , X86_INS_ADDPS = 10 , X86_INS_ADDSD = 11 , X86_INS_ADDSS = 12 , X86_INS_ADDSUBPD = 13 , X86_INS_ADDSUBPS = 14 , X86_INS_FADD = 15 , X86_INS_FIADD = 16 , X86_INS_ADOX = 17 , X86_INS_AESDECLAST = 18 , X86_INS_AESDEC = 19 , X86_INS_AESENCLAST = 20 , X86_INS_AESENC = 21 , X86_INS_AESIMC = 22 , X86_INS_AESKEYGENASSIST = 23 , X86_INS_AND = 24 , X86_INS_ANDN = 25 , X86_INS_ANDNPD = 26 , X86_INS_ANDNPS = 27 , X86_INS_ANDPD = 28 , X86_INS_ANDPS = 29 , X86_INS_ARPL = 30 , X86_INS_BEXTR = 31 , X86_INS_BLCFILL = 32 , X86_INS_BLCI = 33 , X86_INS_BLCIC = 34 , X86_INS_BLCMSK = 35 , X86_INS_BLCS = 36 , X86_INS_BLENDPD = 37 , X86_INS_BLENDPS = 38 , X86_INS_BLENDVPD = 39 , X86_INS_BLENDVPS = 40 , X86_INS_BLSFILL = 41 , X86_INS_BLSI = 42 , X86_INS_BLSIC = 43 , X86_INS_BLSMSK = 44 , X86_INS_BLSR = 45 , X86_INS_BNDCL = 46 , X86_INS_BNDCN = 47 , X86_INS_BNDCU = 48 , X86_INS_BNDLDX = 49 , X86_INS_BNDMK = 50 , X86_INS_BNDMOV = 51 , X86_INS_BNDSTX = 52 , X86_INS_BOUND = 53 , X86_INS_BSF = 54 , X86_INS_BSR = 55 , X86_INS_BSWAP = 56 , X86_INS_BT = 57 , X86_INS_BTC = 58 , X86_INS_BTR = 59 , X86_INS_BTS = 60 , X86_INS_BZHI = 61 , X86_INS_CALL = 62 , X86_INS_CBW = 63 , X86_INS_CDQ = 64 , X86_INS_CDQE = 65 , X86_INS_FCHS = 66 , X86_INS_CLAC = 67 , X86_INS_CLC = 68 , X86_INS_CLD = 69 , X86_INS_CLDEMOTE = 70 , X86_INS_CLFLUSH = 71 , X86_INS_CLFLUSHOPT = 72 , X86_INS_CLGI = 73 , X86_INS_CLI = 74 , X86_INS_CLRSSBSY = 75 , X86_INS_CLTS = 76 , X86_INS_CLWB = 77 , X86_INS_CLZERO = 78 , X86_INS_CMC = 79 , X86_INS_CMOVA = 80 , X86_INS_CMOVAE = 81 , X86_INS_CMOVB = 82 , X86_INS_CMOVBE = 83 , X86_INS_FCMOVBE = 84 , X86_INS_FCMOVB = 85 , X86_INS_CMOVE = 86 , X86_INS_FCMOVE = 87 , X86_INS_CMOVG = 88 , X86_INS_CMOVGE = 89 , X86_INS_CMOVL = 90 , X86_INS_CMOVLE = 91 , X86_INS_FCMOVNBE = 92 , X86_INS_FCMOVNB = 93 , X86_INS_CMOVNE = 94 , X86_INS_FCMOVNE = 95 , X86_INS_CMOVNO = 96 , X86_INS_CMOVNP = 97 , X86_INS_FCMOVNU = 98 , X86_INS_FCMOVNP = 99 , X86_INS_CMOVNS = 100 , X86_INS_CMOVO = 101 , X86_INS_CMOVP = 102 , X86_INS_FCMOVU = 103 , X86_INS_CMOVS = 104 , X86_INS_CMP = 105 , X86_INS_CMPPD = 106 , X86_INS_CMPPS = 107 , X86_INS_CMPSB = 108 , X86_INS_CMPSD = 109 , X86_INS_CMPSQ = 110 , X86_INS_CMPSS = 111 , X86_INS_CMPSW = 112 , X86_INS_CMPXCHG16B = 113 , X86_INS_CMPXCHG = 114 , X86_INS_CMPXCHG8B = 115 , X86_INS_COMISD = 116 , X86_INS_COMISS = 117 , X86_INS_FCOMP = 118 , X86_INS_FCOMPI = 119 , X86_INS_FCOMI = 120 , X86_INS_FCOM = 121 , X86_INS_FCOS = 122 , X86_INS_CPUID = 123 , X86_INS_CQO = 124 , X86_INS_CRC32 = 125 , X86_INS_CVTDQ2PD = 126 , X86_INS_CVTDQ2PS = 127 , X86_INS_CVTPD2DQ = 128 , X86_INS_CVTPD2PS = 129 , X86_INS_CVTPS2DQ = 130 , X86_INS_CVTPS2PD = 131 , X86_INS_CVTSD2SI = 132 , X86_INS_CVTSD2SS = 133 , X86_INS_CVTSI2SD = 134 , X86_INS_CVTSI2SS = 135 , X86_INS_CVTSS2SD = 136 , X86_INS_CVTSS2SI = 137 , X86_INS_CVTTPD2DQ = 138 , X86_INS_CVTTPS2DQ = 139 , X86_INS_CVTTSD2SI = 140 , X86_INS_CVTTSS2SI = 141 , X86_INS_CWD = 142 , X86_INS_CWDE = 143 , X86_INS_DAA = 144 , X86_INS_DAS = 145 , X86_INS_DATA16 = 146 , X86_INS_DEC = 147 , X86_INS_DIV = 148 , X86_INS_DIVPD = 149 , X86_INS_DIVPS = 150 , X86_INS_FDIVR = 151 , X86_INS_FIDIVR = 152 , X86_INS_FDIVRP = 153 , X86_INS_DIVSD = 154 , X86_INS_DIVSS = 155 , X86_INS_FDIV = 156 , X86_INS_FIDIV = 157 , X86_INS_FDIVP = 158 , X86_INS_DPPD = 159 , X86_INS_DPPS = 160 , X86_INS_ENCLS = 161 , X86_INS_ENCLU = 162 , X86_INS_ENCLV = 163 , X86_INS_ENDBR32 = 164 , X86_INS_ENDBR64 = 165 , X86_INS_ENTER = 166 , X86_INS_EXTRACTPS = 167 , X86_INS_EXTRQ = 168 , X86_INS_F2XM1 = 169 , X86_INS_LCALL = 170 , X86_INS_LJMP = 171 , X86_INS_JMP = 172 , X86_INS_FBLD = 173 , X86_INS_FBSTP = 174 , X86_INS_FCOMPP = 175 , X86_INS_FDECSTP = 176 , X86_INS_FDISI8087_NOP = 177 , X86_INS_FEMMS = 178 , X86_INS_FENI8087_NOP = 179 , X86_INS_FFREE = 180 , X86_INS_FFREEP = 181 , X86_INS_FICOM = 182 , X86_INS_FICOMP = 183 , X86_INS_FINCSTP = 184 , X86_INS_FLDCW = 185 , X86_INS_FLDENV = 186 , X86_INS_FLDL2E = 187 , X86_INS_FLDL2T = 188 , X86_INS_FLDLG2 = 189 , X86_INS_FLDLN2 = 190 , X86_INS_FLDPI = 191 , X86_INS_FNCLEX = 192 , X86_INS_FNINIT = 193 , X86_INS_FNOP = 194 , X86_INS_FNSTCW = 195 , X86_INS_FNSTSW = 196 , X86_INS_FPATAN = 197 , X86_INS_FSTPNCE = 198 , X86_INS_FPREM = 199 , X86_INS_FPREM1 = 200 , X86_INS_FPTAN = 201 , X86_INS_FRNDINT = 202 , X86_INS_FRSTOR = 203 , X86_INS_FNSAVE = 204 , X86_INS_FSCALE = 205 , X86_INS_FSETPM = 206 , X86_INS_FSINCOS = 207 , X86_INS_FNSTENV = 208 , X86_INS_FXAM = 209 , X86_INS_FXRSTOR = 210 , X86_INS_FXRSTOR64 = 211 , X86_INS_FXSAVE = 212 , X86_INS_FXSAVE64 = 213 , X86_INS_FXTRACT = 214 , X86_INS_FYL2X = 215 , X86_INS_FYL2XP1 = 216 , X86_INS_GETSEC = 217 , X86_INS_GF2P8AFFINEINVQB = 218 , X86_INS_GF2P8AFFINEQB = 219 , X86_INS_GF2P8MULB = 220 , X86_INS_HADDPD = 221 , X86_INS_HADDPS = 222 , X86_INS_HLT = 223 , X86_INS_HSUBPD = 224 , X86_INS_HSUBPS = 225 , X86_INS_IDIV = 226 , X86_INS_FILD = 227 , X86_INS_IMUL = 228 , X86_INS_IN = 229 , X86_INS_INC = 230 , X86_INS_INCSSPD = 231 , X86_INS_INCSSPQ = 232 , X86_INS_INSB = 233 , X86_INS_INSERTPS = 234 , X86_INS_INSERTQ = 235 , X86_INS_INSD = 236 , X86_INS_INSW = 237 , X86_INS_INT = 238 , X86_INS_INT1 = 239 , X86_INS_INT3 = 240 , X86_INS_INTO = 241 , X86_INS_INVD = 242 , X86_INS_INVEPT = 243 , X86_INS_INVLPG = 244 , X86_INS_INVLPGA = 245 , X86_INS_INVPCID = 246 , X86_INS_INVVPID = 247 , X86_INS_IRET = 248 , X86_INS_IRETD = 249 , X86_INS_IRETQ = 250 , X86_INS_FISTTP = 251 , X86_INS_FIST = 252 , X86_INS_FISTP = 253 , X86_INS_JAE = 254 , X86_INS_JA = 255 , X86_INS_JBE = 256 , X86_INS_JB = 257 , X86_INS_JCXZ = 258 , X86_INS_JECXZ = 259 , X86_INS_JE = 260 , X86_INS_JGE = 261 , X86_INS_JG = 262 , X86_INS_JLE = 263 , X86_INS_JL = 264 , X86_INS_JNE = 265 , X86_INS_JNO = 266 , X86_INS_JNP = 267 , X86_INS_JNS = 268 , X86_INS_JO = 269 , X86_INS_JP = 270 , X86_INS_JRCXZ = 271 , X86_INS_JS = 272 , X86_INS_KADDB = 273 , X86_INS_KADDD = 274 , X86_INS_KADDQ = 275 , X86_INS_KADDW = 276 , X86_INS_KANDB = 277 , X86_INS_KANDD = 278 , X86_INS_KANDNB = 279 , X86_INS_KANDND = 280 , X86_INS_KANDNQ = 281 , X86_INS_KANDNW = 282 , X86_INS_KANDQ = 283 , X86_INS_KANDW = 284 , X86_INS_KMOVB = 285 , X86_INS_KMOVD = 286 , X86_INS_KMOVQ = 287 , X86_INS_KMOVW = 288 , X86_INS_KNOTB = 289 , X86_INS_KNOTD = 290 , X86_INS_KNOTQ = 291 , X86_INS_KNOTW = 292 , X86_INS_KORB = 293 , X86_INS_KORD = 294 , X86_INS_KORQ = 295 , X86_INS_KORTESTB = 296 , X86_INS_KORTESTD = 297 , X86_INS_KORTESTQ = 298 , X86_INS_KORTESTW = 299 , X86_INS_KORW = 300 , X86_INS_KSHIFTLB = 301 , X86_INS_KSHIFTLD = 302 , X86_INS_KSHIFTLQ = 303 , X86_INS_KSHIFTLW = 304 , X86_INS_KSHIFTRB = 305 , X86_INS_KSHIFTRD = 306 , X86_INS_KSHIFTRQ = 307 , X86_INS_KSHIFTRW = 308 , X86_INS_KTESTB = 309 , X86_INS_KTESTD = 310 , X86_INS_KTESTQ = 311 , X86_INS_KTESTW = 312 , X86_INS_KUNPCKBW = 313 , X86_INS_KUNPCKDQ = 314 , X86_INS_KUNPCKWD = 315 , X86_INS_KXNORB = 316 , X86_INS_KXNORD = 317 , X86_INS_KXNORQ = 318 , X86_INS_KXNORW = 319 , X86_INS_KXORB = 320 , X86_INS_KXORD = 321 , X86_INS_KXORQ = 322 , X86_INS_KXORW = 323 , X86_INS_LAHF = 324 , X86_INS_LAR = 325 , X86_INS_LDDQU = 326 , X86_INS_LDMXCSR = 327 , X86_INS_LDS = 328 , X86_INS_FLDZ = 329 , X86_INS_FLD1 = 330 , X86_INS_FLD = 331 , X86_INS_LEA = 332 , X86_INS_LEAVE = 333 , X86_INS_LES = 334 , X86_INS_LFENCE = 335 , X86_INS_LFS = 336 , X86_INS_LGDT = 337 , X86_INS_LGS = 338 , X86_INS_LIDT = 339 , X86_INS_LLDT = 340 , X86_INS_LLWPCB = 341 , X86_INS_LMSW = 342 , X86_INS_LOCK = 343 , X86_INS_LODSB = 344 , X86_INS_LODSD = 345 , X86_INS_LODSQ = 346 , X86_INS_LODSW = 347 , X86_INS_LOOP = 348 , X86_INS_LOOPE = 349 , X86_INS_LOOPNE = 350 , X86_INS_RETF = 351 , X86_INS_RETFQ = 352 , X86_INS_LSL = 353 , X86_INS_LSS = 354 , X86_INS_LTR = 355 , X86_INS_LWPINS = 356 , X86_INS_LWPVAL = 357 , X86_INS_LZCNT = 358 , X86_INS_MASKMOVDQU = 359 , X86_INS_MAXPD = 360 , X86_INS_MAXPS = 361 , X86_INS_MAXSD = 362 , X86_INS_MAXSS = 363 , X86_INS_MFENCE = 364 , X86_INS_MINPD = 365 , X86_INS_MINPS = 366 , X86_INS_MINSD = 367 , X86_INS_MINSS = 368 , X86_INS_CVTPD2PI = 369 , X86_INS_CVTPI2PD = 370 , X86_INS_CVTPI2PS = 371 , X86_INS_CVTPS2PI = 372 , X86_INS_CVTTPD2PI = 373 , X86_INS_CVTTPS2PI = 374 , X86_INS_EMMS = 375 , X86_INS_MASKMOVQ = 376 , X86_INS_MOVD = 377 , X86_INS_MOVQ = 378 , X86_INS_MOVDQ2Q = 379 , X86_INS_MOVNTQ = 380 , X86_INS_MOVQ2DQ = 381 , X86_INS_PABSB = 382 , X86_INS_PABSD = 383 , X86_INS_PABSW = 384 , X86_INS_PACKSSDW = 385 , X86_INS_PACKSSWB = 386 , X86_INS_PACKUSWB = 387 , X86_INS_PADDB = 388 , X86_INS_PADDD = 389 , X86_INS_PADDQ = 390 , X86_INS_PADDSB = 391 , X86_INS_PADDSW = 392 , X86_INS_PADDUSB = 393 , X86_INS_PADDUSW = 394 , X86_INS_PADDW = 395 , X86_INS_PALIGNR = 396 , X86_INS_PANDN = 397 , X86_INS_PAND = 398 , X86_INS_PAVGB = 399 , X86_INS_PAVGW = 400 , X86_INS_PCMPEQB = 401 , X86_INS_PCMPEQD = 402 , X86_INS_PCMPEQW = 403 , X86_INS_PCMPGTB = 404 , X86_INS_PCMPGTD = 405 , X86_INS_PCMPGTW = 406 , X86_INS_PEXTRW = 407 , X86_INS_PHADDD = 408 , X86_INS_PHADDSW = 409 , X86_INS_PHADDW = 410 , X86_INS_PHSUBD = 411 , X86_INS_PHSUBSW = 412 , X86_INS_PHSUBW = 413 , X86_INS_PINSRW = 414 , X86_INS_PMADDUBSW = 415 , X86_INS_PMADDWD = 416 , X86_INS_PMAXSW = 417 , X86_INS_PMAXUB = 418 , X86_INS_PMINSW = 419 , X86_INS_PMINUB = 420 , X86_INS_PMOVMSKB = 421 , X86_INS_PMULHRSW = 422 , X86_INS_PMULHUW = 423 , X86_INS_PMULHW = 424 , X86_INS_PMULLW = 425 , X86_INS_PMULUDQ = 426 , X86_INS_POR = 427 , X86_INS_PSADBW = 428 , X86_INS_PSHUFB = 429 , X86_INS_PSHUFW = 430 , X86_INS_PSIGNB = 431 , X86_INS_PSIGND = 432 , X86_INS_PSIGNW = 433 , X86_INS_PSLLD = 434 , X86_INS_PSLLQ = 435 , X86_INS_PSLLW = 436 , X86_INS_PSRAD = 437 , X86_INS_PSRAW = 438 , X86_INS_PSRLD = 439 , X86_INS_PSRLQ = 440 , X86_INS_PSRLW = 441 , X86_INS_PSUBB = 442 , X86_INS_PSUBD = 443 , X86_INS_PSUBQ = 444 , X86_INS_PSUBSB = 445 , X86_INS_PSUBSW = 446 , X86_INS_PSUBUSB = 447 , X86_INS_PSUBUSW = 448 , X86_INS_PSUBW = 449 , X86_INS_PUNPCKHBW = 450 , X86_INS_PUNPCKHDQ = 451 , X86_INS_PUNPCKHWD = 452 , X86_INS_PUNPCKLBW = 453 , X86_INS_PUNPCKLDQ = 454 , X86_INS_PUNPCKLWD = 455 , X86_INS_PXOR = 456 , X86_INS_MONITORX = 457 , X86_INS_MONITOR = 458 , X86_INS_MONTMUL = 459 , X86_INS_MOV = 460 , X86_INS_MOVABS = 461 , X86_INS_MOVAPD = 462 , X86_INS_MOVAPS = 463 , X86_INS_MOVBE = 464 , X86_INS_MOVDDUP = 465 , X86_INS_MOVDIR64B = 466 , X86_INS_MOVDIRI = 467 , X86_INS_MOVDQA = 468 , X86_INS_MOVDQU = 469 , X86_INS_MOVHLPS = 470 , X86_INS_MOVHPD = 471 , X86_INS_MOVHPS = 472 , X86_INS_MOVLHPS = 473 , X86_INS_MOVLPD = 474 , X86_INS_MOVLPS = 475 , X86_INS_MOVMSKPD = 476 , X86_INS_MOVMSKPS = 477 , X86_INS_MOVNTDQA = 478 , X86_INS_MOVNTDQ = 479 , X86_INS_MOVNTI = 480 , X86_INS_MOVNTPD = 481 , X86_INS_MOVNTPS = 482 , X86_INS_MOVNTSD = 483 , X86_INS_MOVNTSS = 484 , X86_INS_MOVSB = 485 , X86_INS_MOVSD = 486 , X86_INS_MOVSHDUP = 487 , X86_INS_MOVSLDUP = 488 , X86_INS_MOVSQ = 489 , X86_INS_MOVSS = 490 , X86_INS_MOVSW = 491 , X86_INS_MOVSX = 492 , X86_INS_MOVSXD = 493 , X86_INS_MOVUPD = 494 , X86_INS_MOVUPS = 495 , X86_INS_MOVZX = 496 , X86_INS_MPSADBW = 497 , X86_INS_MUL = 498 , X86_INS_MULPD = 499 , X86_INS_MULPS = 500 , X86_INS_MULSD = 501 , X86_INS_MULSS = 502 , X86_INS_MULX = 503 , X86_INS_FMUL = 504 , X86_INS_FIMUL = 505 , X86_INS_FMULP = 506 , X86_INS_MWAITX = 507 , X86_INS_MWAIT = 508 , X86_INS_NEG = 509 , X86_INS_NOP = 510 , X86_INS_NOT = 511 , X86_INS_OR = 512 , X86_INS_ORPD = 513 , X86_INS_ORPS = 514 , X86_INS_OUT = 515 , X86_INS_OUTSB = 516 , X86_INS_OUTSD = 517 , X86_INS_OUTSW = 518 , X86_INS_PACKUSDW = 519 , X86_INS_PAUSE = 520 , X86_INS_PAVGUSB = 521 , X86_INS_PBLENDVB = 522 , X86_INS_PBLENDW = 523 , X86_INS_PCLMULQDQ = 524 , X86_INS_PCMPEQQ = 525 , X86_INS_PCMPESTRI = 526 , X86_INS_PCMPESTRM = 527 , X86_INS_PCMPGTQ = 528 , X86_INS_PCMPISTRI = 529 , X86_INS_PCMPISTRM = 530 , X86_INS_PCONFIG = 531 , X86_INS_PDEP = 532 , X86_INS_PEXT = 533 , X86_INS_PEXTRB = 534 , X86_INS_PEXTRD = 535 , X86_INS_PEXTRQ = 536 , X86_INS_PF2ID = 537 , X86_INS_PF2IW = 538 , X86_INS_PFACC = 539 , X86_INS_PFADD = 540 , X86_INS_PFCMPEQ = 541 , X86_INS_PFCMPGE = 542 , X86_INS_PFCMPGT = 543 , X86_INS_PFMAX = 544 , X86_INS_PFMIN = 545 , X86_INS_PFMUL = 546 , X86_INS_PFNACC = 547 , X86_INS_PFPNACC = 548 , X86_INS_PFRCPIT1 = 549 , X86_INS_PFRCPIT2 = 550 , X86_INS_PFRCP = 551 , X86_INS_PFRSQIT1 = 552 , X86_INS_PFRSQRT = 553 , X86_INS_PFSUBR = 554 , X86_INS_PFSUB = 555 , X86_INS_PHMINPOSUW = 556 , X86_INS_PI2FD = 557 , X86_INS_PI2FW = 558 , X86_INS_PINSRB = 559 , X86_INS_PINSRD = 560 , X86_INS_PINSRQ = 561 , X86_INS_PMAXSB = 562 , X86_INS_PMAXSD = 563 , X86_INS_PMAXUD = 564 , X86_INS_PMAXUW = 565 , X86_INS_PMINSB = 566 , X86_INS_PMINSD = 567 , X86_INS_PMINUD = 568 , X86_INS_PMINUW = 569 , X86_INS_PMOVSXBD = 570 , X86_INS_PMOVSXBQ = 571 , X86_INS_PMOVSXBW = 572 , X86_INS_PMOVSXDQ = 573 , X86_INS_PMOVSXWD = 574 , X86_INS_PMOVSXWQ = 575 , X86_INS_PMOVZXBD = 576 , X86_INS_PMOVZXBQ = 577 , X86_INS_PMOVZXBW = 578 , X86_INS_PMOVZXDQ = 579 , X86_INS_PMOVZXWD = 580 , X86_INS_PMOVZXWQ = 581 , X86_INS_PMULDQ = 582 , X86_INS_PMULHRW = 583 , X86_INS_PMULLD = 584 , X86_INS_POP = 585 , X86_INS_POPAW = 586 , X86_INS_POPAL = 587 , X86_INS_POPCNT = 588 , X86_INS_POPF = 589 , X86_INS_POPFD = 590 , X86_INS_POPFQ = 591 , X86_INS_PREFETCH = 592 , X86_INS_PREFETCHNTA = 593 , X86_INS_PREFETCHT0 = 594 , X86_INS_PREFETCHT1 = 595 , X86_INS_PREFETCHT2 = 596 , X86_INS_PREFETCHW = 597 , X86_INS_PREFETCHWT1 = 598 , X86_INS_PSHUFD = 599 , X86_INS_PSHUFHW = 600 , X86_INS_PSHUFLW = 601 , X86_INS_PSLLDQ = 602 , X86_INS_PSRLDQ = 603 , X86_INS_PSWAPD = 604 , X86_INS_PTEST = 605 , X86_INS_PTWRITE = 606 , X86_INS_PUNPCKHQDQ = 607 , X86_INS_PUNPCKLQDQ = 608 , X86_INS_PUSH = 609 , X86_INS_PUSHAW = 610 , X86_INS_PUSHAL = 611 , X86_INS_PUSHF = 612 , X86_INS_PUSHFD = 613 , X86_INS_PUSHFQ = 614 , X86_INS_RCL = 615 , X86_INS_RCPPS = 616 , X86_INS_RCPSS = 617 , X86_INS_RCR = 618 , X86_INS_RDFSBASE = 619 , X86_INS_RDGSBASE = 620 , X86_INS_RDMSR = 621 , X86_INS_RDPID = 622 , X86_INS_RDPKRU = 623 , X86_INS_RDPMC = 624 , X86_INS_RDRAND = 625 , X86_INS_RDSEED = 626 , X86_INS_RDSSPD = 627 , X86_INS_RDSSPQ = 628 , X86_INS_RDTSC = 629 , X86_INS_RDTSCP = 630 , X86_INS_REPNE = 631 , X86_INS_REP = 632 , X86_INS_RET = 633 , X86_INS_REX64 = 634 , X86_INS_ROL = 635 , X86_INS_ROR = 636 , X86_INS_RORX = 637 , X86_INS_ROUNDPD = 638 , X86_INS_ROUNDPS = 639 , X86_INS_ROUNDSD = 640 , X86_INS_ROUNDSS = 641 , X86_INS_RSM = 642 , X86_INS_RSQRTPS = 643 , X86_INS_RSQRTSS = 644 , X86_INS_RSTORSSP = 645 , X86_INS_SAHF = 646 , X86_INS_SAL = 647 , X86_INS_SALC = 648 , X86_INS_SAR = 649 , X86_INS_SARX = 650 , X86_INS_SAVEPREVSSP = 651 , X86_INS_SBB = 652 , X86_INS_SCASB = 653 , X86_INS_SCASD = 654 , X86_INS_SCASQ = 655 , X86_INS_SCASW = 656 , X86_INS_SETAE = 657 , X86_INS_SETA = 658 , X86_INS_SETBE = 659 , X86_INS_SETB = 660 , X86_INS_SETE = 661 , X86_INS_SETGE = 662 , X86_INS_SETG = 663 , X86_INS_SETLE = 664 , X86_INS_SETL = 665 , X86_INS_SETNE = 666 , X86_INS_SETNO = 667 , X86_INS_SETNP = 668 , X86_INS_SETNS = 669 , X86_INS_SETO = 670 , X86_INS_SETP = 671 , X86_INS_SETSSBSY = 672 , X86_INS_SETS = 673 , X86_INS_SFENCE = 674 , X86_INS_SGDT = 675 , X86_INS_SHA1MSG1 = 676 , X86_INS_SHA1MSG2 = 677 , X86_INS_SHA1NEXTE = 678 , X86_INS_SHA1RNDS4 = 679 , X86_INS_SHA256MSG1 = 680 , X86_INS_SHA256MSG2 = 681 , X86_INS_SHA256RNDS2 = 682 , X86_INS_SHL = 683 , X86_INS_SHLD = 684 , X86_INS_SHLX = 685 , X86_INS_SHR = 686 , X86_INS_SHRD = 687 , X86_INS_SHRX = 688 , X86_INS_SHUFPD = 689 , X86_INS_SHUFPS = 690 , X86_INS_SIDT = 691 , X86_INS_FSIN = 692 , X86_INS_SKINIT = 693 , X86_INS_SLDT = 694 , X86_INS_SLWPCB = 695 , X86_INS_SMSW = 696 , X86_INS_SQRTPD = 697 , X86_INS_SQRTPS = 698 , X86_INS_SQRTSD = 699 , X86_INS_SQRTSS = 700 , X86_INS_FSQRT = 701 , X86_INS_STAC = 702 , X86_INS_STC = 703 , X86_INS_STD = 704 , X86_INS_STGI = 705 , X86_INS_STI = 706 , X86_INS_STMXCSR = 707 , X86_INS_STOSB = 708 , X86_INS_STOSD = 709 , X86_INS_STOSQ = 710 , X86_INS_STOSW = 711 , X86_INS_STR = 712 , X86_INS_FST = 713 , X86_INS_FSTP = 714 , X86_INS_SUB = 715 , X86_INS_SUBPD = 716 , X86_INS_SUBPS = 717 , X86_INS_FSUBR = 718 , X86_INS_FISUBR = 719 , X86_INS_FSUBRP = 720 , X86_INS_SUBSD = 721 , X86_INS_SUBSS = 722 , X86_INS_FSUB = 723 , X86_INS_FISUB = 724 , X86_INS_FSUBP = 725 , X86_INS_SWAPGS = 726 , X86_INS_SYSCALL = 727 , X86_INS_SYSENTER = 728 , X86_INS_SYSEXIT = 729 , X86_INS_SYSEXITQ = 730 , X86_INS_SYSRET = 731 , X86_INS_SYSRETQ = 732 , X86_INS_T1MSKC = 733 , X86_INS_TEST = 734 , X86_INS_TPAUSE = 735 , X86_INS_FTST = 736 , X86_INS_TZCNT = 737 , X86_INS_TZMSK = 738 , X86_INS_UCOMISD = 739 , X86_INS_UCOMISS = 740 , X86_INS_FUCOMPI = 741 , X86_INS_FUCOMI = 742 , X86_INS_FUCOMPP = 743 , X86_INS_FUCOMP = 744 , X86_INS_FUCOM = 745 , X86_INS_UD0 = 746 , X86_INS_UD1 = 747 , X86_INS_UD2 = 748 , X86_INS_UMONITOR = 749 , X86_INS_UMWAIT = 750 , X86_INS_UNPCKHPD = 751 , X86_INS_UNPCKHPS = 752 , X86_INS_UNPCKLPD = 753 , X86_INS_UNPCKLPS = 754 , X86_INS_V4FMADDPS = 755 , X86_INS_V4FMADDSS = 756 , X86_INS_V4FNMADDPS = 757 , X86_INS_V4FNMADDSS = 758 , X86_INS_VADDPD = 759 , X86_INS_VADDPS = 760 , X86_INS_VADDSD = 761 , X86_INS_VADDSS = 762 , X86_INS_VADDSUBPD = 763 , X86_INS_VADDSUBPS = 764 , X86_INS_VAESDECLAST = 765 , X86_INS_VAESDEC = 766 , X86_INS_VAESENCLAST = 767 , X86_INS_VAESENC = 768 , X86_INS_VAESIMC = 769 , X86_INS_VAESKEYGENASSIST = 770 , X86_INS_VALIGND = 771 , X86_INS_VALIGNQ = 772 , X86_INS_VANDNPD = 773 , X86_INS_VANDNPS = 774 , X86_INS_VANDPD = 775 , X86_INS_VANDPS = 776 , X86_INS_VBLENDMPD = 777 , X86_INS_VBLENDMPS = 778 , X86_INS_VBLENDPD = 779 , X86_INS_VBLENDPS = 780 , X86_INS_VBLENDVPD = 781 , X86_INS_VBLENDVPS = 782 , X86_INS_VBROADCASTF128 = 783 , X86_INS_VBROADCASTF32X2 = 784 , X86_INS_VBROADCASTF32X4 = 785 , X86_INS_VBROADCASTF32X8 = 786 , X86_INS_VBROADCASTF64X2 = 787 , X86_INS_VBROADCASTF64X4 = 788 , X86_INS_VBROADCASTI128 = 789 , X86_INS_VBROADCASTI32X2 = 790 , X86_INS_VBROADCASTI32X4 = 791 , X86_INS_VBROADCASTI32X8 = 792 , X86_INS_VBROADCASTI64X2 = 793 , X86_INS_VBROADCASTI64X4 = 794 , X86_INS_VBROADCASTSD = 795 , X86_INS_VBROADCASTSS = 796 , X86_INS_VCMP = 797 , X86_INS_VCMPPD = 798 , X86_INS_VCMPPS = 799 , X86_INS_VCMPSD = 800 , X86_INS_VCMPSS = 801 , X86_INS_VCOMISD = 802 , X86_INS_VCOMISS = 803 , X86_INS_VCOMPRESSPD = 804 , X86_INS_VCOMPRESSPS = 805 , X86_INS_VCVTDQ2PD = 806 , X86_INS_VCVTDQ2PS = 807 , X86_INS_VCVTPD2DQ = 808 , X86_INS_VCVTPD2PS = 809 , X86_INS_VCVTPD2QQ = 810 , X86_INS_VCVTPD2UDQ = 811 , X86_INS_VCVTPD2UQQ = 812 , X86_INS_VCVTPH2PS = 813 , X86_INS_VCVTPS2DQ = 814 , X86_INS_VCVTPS2PD = 815 , X86_INS_VCVTPS2PH = 816 , X86_INS_VCVTPS2QQ = 817 , X86_INS_VCVTPS2UDQ = 818 , X86_INS_VCVTPS2UQQ = 819 , X86_INS_VCVTQQ2PD = 820 , X86_INS_VCVTQQ2PS = 821 , X86_INS_VCVTSD2SI = 822 , X86_INS_VCVTSD2SS = 823 , X86_INS_VCVTSD2USI = 824 , X86_INS_VCVTSI2SD = 825 , X86_INS_VCVTSI2SS = 826 , X86_INS_VCVTSS2SD = 827 , X86_INS_VCVTSS2SI = 828 , X86_INS_VCVTSS2USI = 829 , X86_INS_VCVTTPD2DQ = 830 , X86_INS_VCVTTPD2QQ = 831 , X86_INS_VCVTTPD2UDQ = 832 , X86_INS_VCVTTPD2UQQ = 833 , X86_INS_VCVTTPS2DQ = 834 , X86_INS_VCVTTPS2QQ = 835 , X86_INS_VCVTTPS2UDQ = 836 , X86_INS_VCVTTPS2UQQ = 837 , X86_INS_VCVTTSD2SI = 838 , X86_INS_VCVTTSD2USI = 839 , X86_INS_VCVTTSS2SI = 840 , X86_INS_VCVTTSS2USI = 841 , X86_INS_VCVTUDQ2PD = 842 , X86_INS_VCVTUDQ2PS = 843 , X86_INS_VCVTUQQ2PD = 844 , X86_INS_VCVTUQQ2PS = 845 , X86_INS_VCVTUSI2SD = 846 , X86_INS_VCVTUSI2SS = 847 , X86_INS_VDBPSADBW = 848 , X86_INS_VDIVPD = 849 , X86_INS_VDIVPS = 850 , X86_INS_VDIVSD = 851 , X86_INS_VDIVSS = 852 , X86_INS_VDPPD = 853 , X86_INS_VDPPS = 854 , X86_INS_VERR = 855 , X86_INS_VERW = 856 , X86_INS_VEXP2PD = 857 , X86_INS_VEXP2PS = 858 , X86_INS_VEXPANDPD = 859 , X86_INS_VEXPANDPS = 860 , X86_INS_VEXTRACTF128 = 861 , X86_INS_VEXTRACTF32X4 = 862 , X86_INS_VEXTRACTF32X8 = 863 , X86_INS_VEXTRACTF64X2 = 864 , X86_INS_VEXTRACTF64X4 = 865 , X86_INS_VEXTRACTI128 = 866 , X86_INS_VEXTRACTI32X4 = 867 , X86_INS_VEXTRACTI32X8 = 868 , X86_INS_VEXTRACTI64X2 = 869 , X86_INS_VEXTRACTI64X4 = 870 , X86_INS_VEXTRACTPS = 871 , X86_INS_VFIXUPIMMPD = 872 , X86_INS_VFIXUPIMMPS = 873 , X86_INS_VFIXUPIMMSD = 874 , X86_INS_VFIXUPIMMSS = 875 , X86_INS_VFMADD132PD = 876 , X86_INS_VFMADD132PS = 877 , X86_INS_VFMADD132SD = 878 , X86_INS_VFMADD132SS = 879 , X86_INS_VFMADD213PD = 880 , X86_INS_VFMADD213PS = 881 , X86_INS_VFMADD213SD = 882 , X86_INS_VFMADD213SS = 883 , X86_INS_VFMADD231PD = 884 , X86_INS_VFMADD231PS = 885 , X86_INS_VFMADD231SD = 886 , X86_INS_VFMADD231SS = 887 , X86_INS_VFMADDPD = 888 , X86_INS_VFMADDPS = 889 , X86_INS_VFMADDSD = 890 , X86_INS_VFMADDSS = 891 , X86_INS_VFMADDSUB132PD = 892 , X86_INS_VFMADDSUB132PS = 893 , X86_INS_VFMADDSUB213PD = 894 , X86_INS_VFMADDSUB213PS = 895 , X86_INS_VFMADDSUB231PD = 896 , X86_INS_VFMADDSUB231PS = 897 , X86_INS_VFMADDSUBPD = 898 , X86_INS_VFMADDSUBPS = 899 , X86_INS_VFMSUB132PD = 900 , X86_INS_VFMSUB132PS = 901 , X86_INS_VFMSUB132SD = 902 , X86_INS_VFMSUB132SS = 903 , X86_INS_VFMSUB213PD = 904 , X86_INS_VFMSUB213PS = 905 , X86_INS_VFMSUB213SD = 906 , X86_INS_VFMSUB213SS = 907 , X86_INS_VFMSUB231PD = 908 , X86_INS_VFMSUB231PS = 909 , X86_INS_VFMSUB231SD = 910 , X86_INS_VFMSUB231SS = 911 , X86_INS_VFMSUBADD132PD = 912 , X86_INS_VFMSUBADD132PS = 913 , X86_INS_VFMSUBADD213PD = 914 , X86_INS_VFMSUBADD213PS = 915 , X86_INS_VFMSUBADD231PD = 916 , X86_INS_VFMSUBADD231PS = 917 , X86_INS_VFMSUBADDPD = 918 , X86_INS_VFMSUBADDPS = 919 , X86_INS_VFMSUBPD = 920 , X86_INS_VFMSUBPS = 921 , X86_INS_VFMSUBSD = 922 , X86_INS_VFMSUBSS = 923 , X86_INS_VFNMADD132PD = 924 , X86_INS_VFNMADD132PS = 925 , X86_INS_VFNMADD132SD = 926 , X86_INS_VFNMADD132SS = 927 , X86_INS_VFNMADD213PD = 928 , X86_INS_VFNMADD213PS = 929 , X86_INS_VFNMADD213SD = 930 , X86_INS_VFNMADD213SS = 931 , X86_INS_VFNMADD231PD = 932 , X86_INS_VFNMADD231PS = 933 , X86_INS_VFNMADD231SD = 934 , X86_INS_VFNMADD231SS = 935 , X86_INS_VFNMADDPD = 936 , X86_INS_VFNMADDPS = 937 , X86_INS_VFNMADDSD = 938 , X86_INS_VFNMADDSS = 939 , X86_INS_VFNMSUB132PD = 940 , X86_INS_VFNMSUB132PS = 941 , X86_INS_VFNMSUB132SD = 942 , X86_INS_VFNMSUB132SS = 943 , X86_INS_VFNMSUB213PD = 944 , X86_INS_VFNMSUB213PS = 945 , X86_INS_VFNMSUB213SD = 946 , X86_INS_VFNMSUB213SS = 947 , X86_INS_VFNMSUB231PD = 948 , X86_INS_VFNMSUB231PS = 949 , X86_INS_VFNMSUB231SD = 950 , X86_INS_VFNMSUB231SS = 951 , X86_INS_VFNMSUBPD = 952 , X86_INS_VFNMSUBPS = 953 , X86_INS_VFNMSUBSD = 954 , X86_INS_VFNMSUBSS = 955 , X86_INS_VFPCLASSPD = 956 , X86_INS_VFPCLASSPS = 957 , X86_INS_VFPCLASSSD = 958 , X86_INS_VFPCLASSSS = 959 , X86_INS_VFRCZPD = 960 , X86_INS_VFRCZPS = 961 , X86_INS_VFRCZSD = 962 , X86_INS_VFRCZSS = 963 , X86_INS_VGATHERDPD = 964 , X86_INS_VGATHERDPS = 965 , X86_INS_VGATHERPF0DPD = 966 , X86_INS_VGATHERPF0DPS = 967 , X86_INS_VGATHERPF0QPD = 968 , X86_INS_VGATHERPF0QPS = 969 , X86_INS_VGATHERPF1DPD = 970 , X86_INS_VGATHERPF1DPS = 971 , X86_INS_VGATHERPF1QPD = 972 , X86_INS_VGATHERPF1QPS = 973 , X86_INS_VGATHERQPD = 974 , X86_INS_VGATHERQPS = 975 , X86_INS_VGETEXPPD = 976 , X86_INS_VGETEXPPS = 977 , X86_INS_VGETEXPSD = 978 , X86_INS_VGETEXPSS = 979 , X86_INS_VGETMANTPD = 980 , X86_INS_VGETMANTPS = 981 , X86_INS_VGETMANTSD = 982 , X86_INS_VGETMANTSS = 983 , X86_INS_VGF2P8AFFINEINVQB = 984 , X86_INS_VGF2P8AFFINEQB = 985 , X86_INS_VGF2P8MULB = 986 , X86_INS_VHADDPD = 987 , X86_INS_VHADDPS = 988 , X86_INS_VHSUBPD = 989 , X86_INS_VHSUBPS = 990 , X86_INS_VINSERTF128 = 991 , X86_INS_VINSERTF32X4 = 992 , X86_INS_VINSERTF32X8 = 993 , X86_INS_VINSERTF64X2 = 994 , X86_INS_VINSERTF64X4 = 995 , X86_INS_VINSERTI128 = 996 , X86_INS_VINSERTI32X4 = 997 , X86_INS_VINSERTI32X8 = 998 , X86_INS_VINSERTI64X2 = 999 , X86_INS_VINSERTI64X4 = 1000 , X86_INS_VINSERTPS = 1001 , X86_INS_VLDDQU = 1002 , X86_INS_VLDMXCSR = 1003 , X86_INS_VMASKMOVDQU = 1004 , X86_INS_VMASKMOVPD = 1005 , X86_INS_VMASKMOVPS = 1006 , X86_INS_VMAXPD = 1007 , X86_INS_VMAXPS = 1008 , X86_INS_VMAXSD = 1009 , X86_INS_VMAXSS = 1010 , X86_INS_VMCALL = 1011 , X86_INS_VMCLEAR = 1012 , X86_INS_VMFUNC = 1013 , X86_INS_VMINPD = 1014 , X86_INS_VMINPS = 1015 , X86_INS_VMINSD = 1016 , X86_INS_VMINSS = 1017 , X86_INS_VMLAUNCH = 1018 , X86_INS_VMLOAD = 1019 , X86_INS_VMMCALL = 1020 , X86_INS_VMOVQ = 1021 , X86_INS_VMOVAPD = 1022 , X86_INS_VMOVAPS = 1023 , X86_INS_VMOVDDUP = 1024 , X86_INS_VMOVD = 1025 , X86_INS_VMOVDQA32 = 1026 , X86_INS_VMOVDQA64 = 1027 , X86_INS_VMOVDQA = 1028 , X86_INS_VMOVDQU16 = 1029 , X86_INS_VMOVDQU32 = 1030 , X86_INS_VMOVDQU64 = 1031 , X86_INS_VMOVDQU8 = 1032 , X86_INS_VMOVDQU = 1033 , X86_INS_VMOVHLPS = 1034 , X86_INS_VMOVHPD = 1035 , X86_INS_VMOVHPS = 1036 , X86_INS_VMOVLHPS = 1037 , X86_INS_VMOVLPD = 1038 , X86_INS_VMOVLPS = 1039 , X86_INS_VMOVMSKPD = 1040 , X86_INS_VMOVMSKPS = 1041 , X86_INS_VMOVNTDQA = 1042 , X86_INS_VMOVNTDQ = 1043 , X86_INS_VMOVNTPD = 1044 , X86_INS_VMOVNTPS = 1045 , X86_INS_VMOVSD = 1046 , X86_INS_VMOVSHDUP = 1047 , X86_INS_VMOVSLDUP = 1048 , X86_INS_VMOVSS = 1049 , X86_INS_VMOVUPD = 1050 , X86_INS_VMOVUPS = 1051 , X86_INS_VMPSADBW = 1052 , X86_INS_VMPTRLD = 1053 , X86_INS_VMPTRST = 1054 , X86_INS_VMREAD = 1055 , X86_INS_VMRESUME = 1056 , X86_INS_VMRUN = 1057 , X86_INS_VMSAVE = 1058 , X86_INS_VMULPD = 1059 , X86_INS_VMULPS = 1060 , X86_INS_VMULSD = 1061 , X86_INS_VMULSS = 1062 , X86_INS_VMWRITE = 1063 , X86_INS_VMXOFF = 1064 , X86_INS_VMXON = 1065 , X86_INS_VORPD = 1066 , X86_INS_VORPS = 1067 , X86_INS_VP4DPWSSDS = 1068 , X86_INS_VP4DPWSSD = 1069 , X86_INS_VPABSB = 1070 , X86_INS_VPABSD = 1071 , X86_INS_VPABSQ = 1072 , X86_INS_VPABSW = 1073 , X86_INS_VPACKSSDW = 1074 , X86_INS_VPACKSSWB = 1075 , X86_INS_VPACKUSDW = 1076 , X86_INS_VPACKUSWB = 1077 , X86_INS_VPADDB = 1078 , X86_INS_VPADDD = 1079 , X86_INS_VPADDQ = 1080 , X86_INS_VPADDSB = 1081 , X86_INS_VPADDSW = 1082 , X86_INS_VPADDUSB = 1083 , X86_INS_VPADDUSW = 1084 , X86_INS_VPADDW = 1085 , X86_INS_VPALIGNR = 1086 , X86_INS_VPANDD = 1087 , X86_INS_VPANDND = 1088 , X86_INS_VPANDNQ = 1089 , X86_INS_VPANDN = 1090 , X86_INS_VPANDQ = 1091 , X86_INS_VPAND = 1092 , X86_INS_VPAVGB = 1093 , X86_INS_VPAVGW = 1094 , X86_INS_VPBLENDD = 1095 , X86_INS_VPBLENDMB = 1096 , X86_INS_VPBLENDMD = 1097 , X86_INS_VPBLENDMQ = 1098 , X86_INS_VPBLENDMW = 1099 , X86_INS_VPBLENDVB = 1100 , X86_INS_VPBLENDW = 1101 , X86_INS_VPBROADCASTB = 1102 , X86_INS_VPBROADCASTD = 1103 , X86_INS_VPBROADCASTMB2Q = 1104 , X86_INS_VPBROADCASTMW2D = 1105 , X86_INS_VPBROADCASTQ = 1106 , X86_INS_VPBROADCASTW = 1107 , X86_INS_VPCLMULQDQ = 1108 , X86_INS_VPCMOV = 1109 , X86_INS_VPCMP = 1110 , X86_INS_VPCMPB = 1111 , X86_INS_VPCMPD = 1112 , X86_INS_VPCMPEQB = 1113 , X86_INS_VPCMPEQD = 1114 , X86_INS_VPCMPEQQ = 1115 , X86_INS_VPCMPEQW = 1116 , X86_INS_VPCMPESTRI = 1117 , X86_INS_VPCMPESTRM = 1118 , X86_INS_VPCMPGTB = 1119 , X86_INS_VPCMPGTD = 1120 , X86_INS_VPCMPGTQ = 1121 , X86_INS_VPCMPGTW = 1122 , X86_INS_VPCMPISTRI = 1123 , X86_INS_VPCMPISTRM = 1124 , X86_INS_VPCMPQ = 1125 , X86_INS_VPCMPUB = 1126 , X86_INS_VPCMPUD = 1127 , X86_INS_VPCMPUQ = 1128 , X86_INS_VPCMPUW = 1129 , X86_INS_VPCMPW = 1130 , X86_INS_VPCOM = 1131 , X86_INS_VPCOMB = 1132 , X86_INS_VPCOMD = 1133 , X86_INS_VPCOMPRESSB = 1134 , X86_INS_VPCOMPRESSD = 1135 , X86_INS_VPCOMPRESSQ = 1136 , X86_INS_VPCOMPRESSW = 1137 , X86_INS_VPCOMQ = 1138 , X86_INS_VPCOMUB = 1139 , X86_INS_VPCOMUD = 1140 , X86_INS_VPCOMUQ = 1141 , X86_INS_VPCOMUW = 1142 , X86_INS_VPCOMW = 1143 , X86_INS_VPCONFLICTD = 1144 , X86_INS_VPCONFLICTQ = 1145 , X86_INS_VPDPBUSDS = 1146 , X86_INS_VPDPBUSD = 1147 , X86_INS_VPDPWSSDS = 1148 , X86_INS_VPDPWSSD = 1149 , X86_INS_VPERM2F128 = 1150 , X86_INS_VPERM2I128 = 1151 , X86_INS_VPERMB = 1152 , X86_INS_VPERMD = 1153 , X86_INS_VPERMI2B = 1154 , X86_INS_VPERMI2D = 1155 , X86_INS_VPERMI2PD = 1156 , X86_INS_VPERMI2PS = 1157 , X86_INS_VPERMI2Q = 1158 , X86_INS_VPERMI2W = 1159 , X86_INS_VPERMIL2PD = 1160 , X86_INS_VPERMILPD = 1161 , X86_INS_VPERMIL2PS = 1162 , X86_INS_VPERMILPS = 1163 , X86_INS_VPERMPD = 1164 , X86_INS_VPERMPS = 1165 , X86_INS_VPERMQ = 1166 , X86_INS_VPERMT2B = 1167 , X86_INS_VPERMT2D = 1168 , X86_INS_VPERMT2PD = 1169 , X86_INS_VPERMT2PS = 1170 , X86_INS_VPERMT2Q = 1171 , X86_INS_VPERMT2W = 1172 , X86_INS_VPERMW = 1173 , X86_INS_VPEXPANDB = 1174 , X86_INS_VPEXPANDD = 1175 , X86_INS_VPEXPANDQ = 1176 , X86_INS_VPEXPANDW = 1177 , X86_INS_VPEXTRB = 1178 , X86_INS_VPEXTRD = 1179 , X86_INS_VPEXTRQ = 1180 , X86_INS_VPEXTRW = 1181 , X86_INS_VPGATHERDD = 1182 , X86_INS_VPGATHERDQ = 1183 , X86_INS_VPGATHERQD = 1184 , X86_INS_VPGATHERQQ = 1185 , X86_INS_VPHADDBD = 1186 , X86_INS_VPHADDBQ = 1187 , X86_INS_VPHADDBW = 1188 , X86_INS_VPHADDDQ = 1189 , X86_INS_VPHADDD = 1190 , X86_INS_VPHADDSW = 1191 , X86_INS_VPHADDUBD = 1192 , X86_INS_VPHADDUBQ = 1193 , X86_INS_VPHADDUBW = 1194 , X86_INS_VPHADDUDQ = 1195 , X86_INS_VPHADDUWD = 1196 , X86_INS_VPHADDUWQ = 1197 , X86_INS_VPHADDWD = 1198 , X86_INS_VPHADDWQ = 1199 , X86_INS_VPHADDW = 1200 , X86_INS_VPHMINPOSUW = 1201 , X86_INS_VPHSUBBW = 1202 , X86_INS_VPHSUBDQ = 1203 , X86_INS_VPHSUBD = 1204 , X86_INS_VPHSUBSW = 1205 , X86_INS_VPHSUBWD = 1206 , X86_INS_VPHSUBW = 1207 , X86_INS_VPINSRB = 1208 , X86_INS_VPINSRD = 1209 , X86_INS_VPINSRQ = 1210 , X86_INS_VPINSRW = 1211 , X86_INS_VPLZCNTD = 1212 , X86_INS_VPLZCNTQ = 1213 , X86_INS_VPMACSDD = 1214 , X86_INS_VPMACSDQH = 1215 , X86_INS_VPMACSDQL = 1216 , X86_INS_VPMACSSDD = 1217 , X86_INS_VPMACSSDQH = 1218 , X86_INS_VPMACSSDQL = 1219 , X86_INS_VPMACSSWD = 1220 , X86_INS_VPMACSSWW = 1221 , X86_INS_VPMACSWD = 1222 , X86_INS_VPMACSWW = 1223 , X86_INS_VPMADCSSWD = 1224 , X86_INS_VPMADCSWD = 1225 , X86_INS_VPMADD52HUQ = 1226 , X86_INS_VPMADD52LUQ = 1227 , X86_INS_VPMADDUBSW = 1228 , X86_INS_VPMADDWD = 1229 , X86_INS_VPMASKMOVD = 1230 , X86_INS_VPMASKMOVQ = 1231 , X86_INS_VPMAXSB = 1232 , X86_INS_VPMAXSD = 1233 , X86_INS_VPMAXSQ = 1234 , X86_INS_VPMAXSW = 1235 , X86_INS_VPMAXUB = 1236 , X86_INS_VPMAXUD = 1237 , X86_INS_VPMAXUQ = 1238 , X86_INS_VPMAXUW = 1239 , X86_INS_VPMINSB = 1240 , X86_INS_VPMINSD = 1241 , X86_INS_VPMINSQ = 1242 , X86_INS_VPMINSW = 1243 , X86_INS_VPMINUB = 1244 , X86_INS_VPMINUD = 1245 , X86_INS_VPMINUQ = 1246 , X86_INS_VPMINUW = 1247 , X86_INS_VPMOVB2M = 1248 , X86_INS_VPMOVD2M = 1249 , X86_INS_VPMOVDB = 1250 , X86_INS_VPMOVDW = 1251 , X86_INS_VPMOVM2B = 1252 , X86_INS_VPMOVM2D = 1253 , X86_INS_VPMOVM2Q = 1254 , X86_INS_VPMOVM2W = 1255 , X86_INS_VPMOVMSKB = 1256 , X86_INS_VPMOVQ2M = 1257 , X86_INS_VPMOVQB = 1258 , X86_INS_VPMOVQD = 1259 , X86_INS_VPMOVQW = 1260 , X86_INS_VPMOVSDB = 1261 , X86_INS_VPMOVSDW = 1262 , X86_INS_VPMOVSQB = 1263 , X86_INS_VPMOVSQD = 1264 , X86_INS_VPMOVSQW = 1265 , X86_INS_VPMOVSWB = 1266 , X86_INS_VPMOVSXBD = 1267 , X86_INS_VPMOVSXBQ = 1268 , X86_INS_VPMOVSXBW = 1269 , X86_INS_VPMOVSXDQ = 1270 , X86_INS_VPMOVSXWD = 1271 , X86_INS_VPMOVSXWQ = 1272 , X86_INS_VPMOVUSDB = 1273 , X86_INS_VPMOVUSDW = 1274 , X86_INS_VPMOVUSQB = 1275 , X86_INS_VPMOVUSQD = 1276 , X86_INS_VPMOVUSQW = 1277 , X86_INS_VPMOVUSWB = 1278 , X86_INS_VPMOVW2M = 1279 , X86_INS_VPMOVWB = 1280 , X86_INS_VPMOVZXBD = 1281 , X86_INS_VPMOVZXBQ = 1282 , X86_INS_VPMOVZXBW = 1283 , X86_INS_VPMOVZXDQ = 1284 , X86_INS_VPMOVZXWD = 1285 , X86_INS_VPMOVZXWQ = 1286 , X86_INS_VPMULDQ = 1287 , X86_INS_VPMULHRSW = 1288 , X86_INS_VPMULHUW = 1289 , X86_INS_VPMULHW = 1290 , X86_INS_VPMULLD = 1291 , X86_INS_VPMULLQ = 1292 , X86_INS_VPMULLW = 1293 , X86_INS_VPMULTISHIFTQB = 1294 , X86_INS_VPMULUDQ = 1295 , X86_INS_VPOPCNTB = 1296 , X86_INS_VPOPCNTD = 1297 , X86_INS_VPOPCNTQ = 1298 , X86_INS_VPOPCNTW = 1299 , X86_INS_VPORD = 1300 , X86_INS_VPORQ = 1301 , X86_INS_VPOR = 1302 , X86_INS_VPPERM = 1303 , X86_INS_VPROLD = 1304 , X86_INS_VPROLQ = 1305 , X86_INS_VPROLVD = 1306 , X86_INS_VPROLVQ = 1307 , X86_INS_VPRORD = 1308 , X86_INS_VPRORQ = 1309 , X86_INS_VPRORVD = 1310 , X86_INS_VPRORVQ = 1311 , X86_INS_VPROTB = 1312 , X86_INS_VPROTD = 1313 , X86_INS_VPROTQ = 1314 , X86_INS_VPROTW = 1315 , X86_INS_VPSADBW = 1316 , X86_INS_VPSCATTERDD = 1317 , X86_INS_VPSCATTERDQ = 1318 , X86_INS_VPSCATTERQD = 1319 , X86_INS_VPSCATTERQQ = 1320 , X86_INS_VPSHAB = 1321 , X86_INS_VPSHAD = 1322 , X86_INS_VPSHAQ = 1323 , X86_INS_VPSHAW = 1324 , X86_INS_VPSHLB = 1325 , X86_INS_VPSHLDD = 1326 , X86_INS_VPSHLDQ = 1327 , X86_INS_VPSHLDVD = 1328 , X86_INS_VPSHLDVQ = 1329 , X86_INS_VPSHLDVW = 1330 , X86_INS_VPSHLDW = 1331 , X86_INS_VPSHLD = 1332 , X86_INS_VPSHLQ = 1333 , X86_INS_VPSHLW = 1334 , X86_INS_VPSHRDD = 1335 , X86_INS_VPSHRDQ = 1336 , X86_INS_VPSHRDVD = 1337 , X86_INS_VPSHRDVQ = 1338 , X86_INS_VPSHRDVW = 1339 , X86_INS_VPSHRDW = 1340 , X86_INS_VPSHUFBITQMB = 1341 , X86_INS_VPSHUFB = 1342 , X86_INS_VPSHUFD = 1343 , X86_INS_VPSHUFHW = 1344 , X86_INS_VPSHUFLW = 1345 , X86_INS_VPSIGNB = 1346 , X86_INS_VPSIGND = 1347 , X86_INS_VPSIGNW = 1348 , X86_INS_VPSLLDQ = 1349 , X86_INS_VPSLLD = 1350 , X86_INS_VPSLLQ = 1351 , X86_INS_VPSLLVD = 1352 , X86_INS_VPSLLVQ = 1353 , X86_INS_VPSLLVW = 1354 , X86_INS_VPSLLW = 1355 , X86_INS_VPSRAD = 1356 , X86_INS_VPSRAQ = 1357 , X86_INS_VPSRAVD = 1358 , X86_INS_VPSRAVQ = 1359 , X86_INS_VPSRAVW = 1360 , X86_INS_VPSRAW = 1361 , X86_INS_VPSRLDQ = 1362 , X86_INS_VPSRLD = 1363 , X86_INS_VPSRLQ = 1364 , X86_INS_VPSRLVD = 1365 , X86_INS_VPSRLVQ = 1366 , X86_INS_VPSRLVW = 1367 , X86_INS_VPSRLW = 1368 , X86_INS_VPSUBB = 1369 , X86_INS_VPSUBD = 1370 , X86_INS_VPSUBQ = 1371 , X86_INS_VPSUBSB = 1372 , X86_INS_VPSUBSW = 1373 , X86_INS_VPSUBUSB = 1374 , X86_INS_VPSUBUSW = 1375 , X86_INS_VPSUBW = 1376 , X86_INS_VPTERNLOGD = 1377 , X86_INS_VPTERNLOGQ = 1378 , X86_INS_VPTESTMB = 1379 , X86_INS_VPTESTMD = 1380 , X86_INS_VPTESTMQ = 1381 , X86_INS_VPTESTMW = 1382 , X86_INS_VPTESTNMB = 1383 , X86_INS_VPTESTNMD = 1384 , X86_INS_VPTESTNMQ = 1385 , X86_INS_VPTESTNMW = 1386 , X86_INS_VPTEST = 1387 , X86_INS_VPUNPCKHBW = 1388 , X86_INS_VPUNPCKHDQ = 1389 , X86_INS_VPUNPCKHQDQ = 1390 , X86_INS_VPUNPCKHWD = 1391 , X86_INS_VPUNPCKLBW = 1392 , X86_INS_VPUNPCKLDQ = 1393 , X86_INS_VPUNPCKLQDQ = 1394 , X86_INS_VPUNPCKLWD = 1395 , X86_INS_VPXORD = 1396 , X86_INS_VPXORQ = 1397 , X86_INS_VPXOR = 1398 , X86_INS_VRANGEPD = 1399 , X86_INS_VRANGEPS = 1400 , X86_INS_VRANGESD = 1401 , X86_INS_VRANGESS = 1402 , X86_INS_VRCP14PD = 1403 , X86_INS_VRCP14PS = 1404 , X86_INS_VRCP14SD = 1405 , X86_INS_VRCP14SS = 1406 , X86_INS_VRCP28PD = 1407 , X86_INS_VRCP28PS = 1408 , X86_INS_VRCP28SD = 1409 , X86_INS_VRCP28SS = 1410 , X86_INS_VRCPPS = 1411 , X86_INS_VRCPSS = 1412 , X86_INS_VREDUCEPD = 1413 , X86_INS_VREDUCEPS = 1414 , X86_INS_VREDUCESD = 1415 , X86_INS_VREDUCESS = 1416 , X86_INS_VRNDSCALEPD = 1417 , X86_INS_VRNDSCALEPS = 1418 , X86_INS_VRNDSCALESD = 1419 , X86_INS_VRNDSCALESS = 1420 , X86_INS_VROUNDPD = 1421 , X86_INS_VROUNDPS = 1422 , X86_INS_VROUNDSD = 1423 , X86_INS_VROUNDSS = 1424 , X86_INS_VRSQRT14PD = 1425 , X86_INS_VRSQRT14PS = 1426 , X86_INS_VRSQRT14SD = 1427 , X86_INS_VRSQRT14SS = 1428 , X86_INS_VRSQRT28PD = 1429 , X86_INS_VRSQRT28PS = 1430 , X86_INS_VRSQRT28SD = 1431 , X86_INS_VRSQRT28SS = 1432 , X86_INS_VRSQRTPS = 1433 , X86_INS_VRSQRTSS = 1434 , X86_INS_VSCALEFPD = 1435 , X86_INS_VSCALEFPS = 1436 , X86_INS_VSCALEFSD = 1437 , X86_INS_VSCALEFSS = 1438 , X86_INS_VSCATTERDPD = 1439 , X86_INS_VSCATTERDPS = 1440 , X86_INS_VSCATTERPF0DPD = 1441 , X86_INS_VSCATTERPF0DPS = 1442 , X86_INS_VSCATTERPF0QPD = 1443 , X86_INS_VSCATTERPF0QPS = 1444 , X86_INS_VSCATTERPF1DPD = 1445 , X86_INS_VSCATTERPF1DPS = 1446 , X86_INS_VSCATTERPF1QPD = 1447 , X86_INS_VSCATTERPF1QPS = 1448 , X86_INS_VSCATTERQPD = 1449 , X86_INS_VSCATTERQPS = 1450 , X86_INS_VSHUFF32X4 = 1451 , X86_INS_VSHUFF64X2 = 1452 , X86_INS_VSHUFI32X4 = 1453 , X86_INS_VSHUFI64X2 = 1454 , X86_INS_VSHUFPD = 1455 , X86_INS_VSHUFPS = 1456 , X86_INS_VSQRTPD = 1457 , X86_INS_VSQRTPS = 1458 , X86_INS_VSQRTSD = 1459 , X86_INS_VSQRTSS = 1460 , X86_INS_VSTMXCSR = 1461 , X86_INS_VSUBPD = 1462 , X86_INS_VSUBPS = 1463 , X86_INS_VSUBSD = 1464 , X86_INS_VSUBSS = 1465 , X86_INS_VTESTPD = 1466 , X86_INS_VTESTPS = 1467 , X86_INS_VUCOMISD = 1468 , X86_INS_VUCOMISS = 1469 , X86_INS_VUNPCKHPD = 1470 , X86_INS_VUNPCKHPS = 1471 , X86_INS_VUNPCKLPD = 1472 , X86_INS_VUNPCKLPS = 1473 , X86_INS_VXORPD = 1474 , X86_INS_VXORPS = 1475 , X86_INS_VZEROALL = 1476 , X86_INS_VZEROUPPER = 1477 , X86_INS_WAIT = 1478 , X86_INS_WBINVD = 1479 , X86_INS_WBNOINVD = 1480 , X86_INS_WRFSBASE = 1481 , X86_INS_WRGSBASE = 1482 , X86_INS_WRMSR = 1483 , X86_INS_WRPKRU = 1484 , X86_INS_WRSSD = 1485 , X86_INS_WRSSQ = 1486 , X86_INS_WRUSSD = 1487 , X86_INS_WRUSSQ = 1488 , X86_INS_XABORT = 1489 , X86_INS_XACQUIRE = 1490 , X86_INS_XADD = 1491 , X86_INS_XBEGIN = 1492 , X86_INS_XCHG = 1493 , X86_INS_FXCH = 1494 , X86_INS_XCRYPTCBC = 1495 , X86_INS_XCRYPTCFB = 1496 , X86_INS_XCRYPTCTR = 1497 , X86_INS_XCRYPTECB = 1498 , X86_INS_XCRYPTOFB = 1499 , X86_INS_XEND = 1500 , X86_INS_XGETBV = 1501 , X86_INS_XLATB = 1502 , X86_INS_XOR = 1503 , X86_INS_XORPD = 1504 , X86_INS_XORPS = 1505 , X86_INS_XRELEASE = 1506 , X86_INS_XRSTOR = 1507 , X86_INS_XRSTOR64 = 1508 , X86_INS_XRSTORS = 1509 , X86_INS_XRSTORS64 = 1510 , X86_INS_XSAVE = 1511 , X86_INS_XSAVE64 = 1512 , X86_INS_XSAVEC = 1513 , X86_INS_XSAVEC64 = 1514 , X86_INS_XSAVEOPT = 1515 , X86_INS_XSAVEOPT64 = 1516 , X86_INS_XSAVES = 1517 , X86_INS_XSAVES64 = 1518 , X86_INS_XSETBV = 1519 , X86_INS_XSHA1 = 1520 , X86_INS_XSHA256 = 1521 , X86_INS_XSTORE = 1522 , X86_INS_XTEST = 1523 , X86_INS_ENDING = 1524 , } # [repr (u32)] # [doc = " Group of X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn_group { # [doc = "< = CS_GRP_INVALID"] X86_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] X86_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] X86_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] X86_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] X86_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] X86_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] X86_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] X86_GRP_BRANCH_RELATIVE = 7 , # [doc = "< all virtualization instructions (VT-x + AMD-V)"] X86_GRP_VM = 128 , X86_GRP_3DNOW = 129 , X86_GRP_AES = 130 , X86_GRP_ADX = 131 , X86_GRP_AVX = 132 , X86_GRP_AVX2 = 133 , X86_GRP_AVX512 = 134 , X86_GRP_BMI = 135 , X86_GRP_BMI2 = 136 , X86_GRP_CMOV = 137 , X86_GRP_F16C = 138 , X86_GRP_FMA = 139 , X86_GRP_FMA4 = 140 , X86_GRP_FSGSBASE = 141 , X86_GRP_HLE = 142 , X86_GRP_MMX = 143 , X86_GRP_MODE32 = 144 , X86_GRP_MODE64 = 145 , X86_GRP_RTM = 146 , X86_GRP_SHA = 147 , X86_GRP_SSE1 = 148 , X86_GRP_SSE2 = 149 , X86_GRP_SSE3 = 150 , X86_GRP_SSE41 = 151 , X86_GRP_SSE42 = 152 , X86_GRP_SSE4A = 153 , X86_GRP_SSSE3 = 154 , X86_GRP_PCLMUL = 155 , X86_GRP_XOP = 156 , X86_GRP_CDI = 157 , X86_GRP_ERI = 158 , X86_GRP_TBM = 159 , X86_GRP_16BITMODE = 160 , X86_GRP_NOT64BITMODE = 161 , X86_GRP_SGX = 162 , X86_GRP_DQI = 163 , X86_GRP_BWI = 164 , X86_GRP_PFI = 165 , X86_GRP_VLX = 166 , X86_GRP_SMAP = 167 , X86_GRP_NOVLX = 168 , X86_GRP_FPU = 169 , X86_GRP_ENDING = 170 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] XCORE_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] XCORE_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] XCORE_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] XCORE_OP_MEM = 3 , } # [repr (u32)] # [doc = " XCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_reg { XCORE_REG_INVALID = 0 , XCORE_REG_CP = 1 , XCORE_REG_DP = 2 , XCORE_REG_LR = 3 , XCORE_REG_SP = 4 , XCORE_REG_R0 = 5 , XCORE_REG_R1 = 6 , XCORE_REG_R2 = 7 , XCORE_REG_R3 = 8 , XCORE_REG_R4 = 9 , XCORE_REG_R5 = 10 , XCORE_REG_R6 = 11 , XCORE_REG_R7 = 12 , XCORE_REG_R8 = 13 , XCORE_REG_R9 = 14 , XCORE_REG_R10 = 15 , XCORE_REG_R11 = 16 , # [doc = "< pc"] XCORE_REG_PC = 17 , # [doc = "< save pc"] XCORE_REG_SCP = 18 , XCORE_REG_SSR = 19 , XCORE_REG_ET = 20 , XCORE_REG_ED = 21 , XCORE_REG_SED = 22 , XCORE_REG_KEP = 23 , XCORE_REG_KSP = 24 , XCORE_REG_ID = 25 , XCORE_REG_ENDING = 26 , } # [doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct xcore_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , # [doc = "< +1: forward, -1: backward"] pub direct : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of xcore_op_mem"] [:: std :: mem :: size_of :: < xcore_op_mem > () - 12usize] ; ["Alignment of xcore_op_mem"] [:: std :: mem :: align_of :: < xcore_op_mem > () - 4usize] ; ["Offset of field: xcore_op_mem::base"] [:: std :: mem :: offset_of ! (xcore_op_mem , base) - 0usize] ; ["Offset of field: xcore_op_mem::index"] [:: std :: mem :: offset_of ! (xcore_op_mem , index) - 1usize] ; ["Offset of field: xcore_op_mem::disp"] [:: std :: mem :: offset_of ! (xcore_op_mem , disp) - 4usize] ; ["Offset of field: xcore_op_mem::direct"] [:: std :: mem :: offset_of ! (xcore_op_mem , direct) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore_op { # [doc = "< operand type"] pub type_ : xcore_op_type , pub __bindgen_anon_1 : cs_xcore_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_xcore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : xcore_reg , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : xcore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_xcore_op__bindgen_ty_1 > () - 12usize] ; ["Alignment of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_xcore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op"] [:: std :: mem :: size_of :: < cs_xcore_op > () - 16usize] ; ["Alignment of cs_xcore_op"] [:: std :: mem :: align_of :: < cs_xcore_op > () - 4usize] ; ["Offset of field: cs_xcore_op::type_"] [:: std :: mem :: offset_of ! (cs_xcore_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_xcore_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore"] [:: std :: mem :: size_of :: < cs_xcore > () - 132usize] ; ["Alignment of cs_xcore"] [:: std :: mem :: align_of :: < cs_xcore > () - 4usize] ; ["Offset of field: cs_xcore::op_count"] [:: std :: mem :: offset_of ! (cs_xcore , op_count) - 0usize] ; ["Offset of field: cs_xcore::operands"] [:: std :: mem :: offset_of ! (cs_xcore , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " XCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn { XCORE_INS_INVALID = 0 , XCORE_INS_ADD = 1 , XCORE_INS_ANDNOT = 2 , XCORE_INS_AND = 3 , XCORE_INS_ASHR = 4 , XCORE_INS_BAU = 5 , XCORE_INS_BITREV = 6 , XCORE_INS_BLA = 7 , XCORE_INS_BLAT = 8 , XCORE_INS_BL = 9 , XCORE_INS_BF = 10 , XCORE_INS_BT = 11 , XCORE_INS_BU = 12 , XCORE_INS_BRU = 13 , XCORE_INS_BYTEREV = 14 , XCORE_INS_CHKCT = 15 , XCORE_INS_CLRE = 16 , XCORE_INS_CLRPT = 17 , XCORE_INS_CLRSR = 18 , XCORE_INS_CLZ = 19 , XCORE_INS_CRC8 = 20 , XCORE_INS_CRC32 = 21 , XCORE_INS_DCALL = 22 , XCORE_INS_DENTSP = 23 , XCORE_INS_DGETREG = 24 , XCORE_INS_DIVS = 25 , XCORE_INS_DIVU = 26 , XCORE_INS_DRESTSP = 27 , XCORE_INS_DRET = 28 , XCORE_INS_ECALLF = 29 , XCORE_INS_ECALLT = 30 , XCORE_INS_EDU = 31 , XCORE_INS_EEF = 32 , XCORE_INS_EET = 33 , XCORE_INS_EEU = 34 , XCORE_INS_ENDIN = 35 , XCORE_INS_ENTSP = 36 , XCORE_INS_EQ = 37 , XCORE_INS_EXTDP = 38 , XCORE_INS_EXTSP = 39 , XCORE_INS_FREER = 40 , XCORE_INS_FREET = 41 , XCORE_INS_GETD = 42 , XCORE_INS_GET = 43 , XCORE_INS_GETN = 44 , XCORE_INS_GETR = 45 , XCORE_INS_GETSR = 46 , XCORE_INS_GETST = 47 , XCORE_INS_GETTS = 48 , XCORE_INS_INCT = 49 , XCORE_INS_INIT = 50 , XCORE_INS_INPW = 51 , XCORE_INS_INSHR = 52 , XCORE_INS_INT = 53 , XCORE_INS_IN = 54 , XCORE_INS_KCALL = 55 , XCORE_INS_KENTSP = 56 , XCORE_INS_KRESTSP = 57 , XCORE_INS_KRET = 58 , XCORE_INS_LADD = 59 , XCORE_INS_LD16S = 60 , XCORE_INS_LD8U = 61 , XCORE_INS_LDA16 = 62 , XCORE_INS_LDAP = 63 , XCORE_INS_LDAW = 64 , XCORE_INS_LDC = 65 , XCORE_INS_LDW = 66 , XCORE_INS_LDIVU = 67 , XCORE_INS_LMUL = 68 , XCORE_INS_LSS = 69 , XCORE_INS_LSUB = 70 , XCORE_INS_LSU = 71 , XCORE_INS_MACCS = 72 , XCORE_INS_MACCU = 73 , XCORE_INS_MJOIN = 74 , XCORE_INS_MKMSK = 75 , XCORE_INS_MSYNC = 76 , XCORE_INS_MUL = 77 , XCORE_INS_NEG = 78 , XCORE_INS_NOT = 79 , XCORE_INS_OR = 80 , XCORE_INS_OUTCT = 81 , XCORE_INS_OUTPW = 82 , XCORE_INS_OUTSHR = 83 , XCORE_INS_OUTT = 84 , XCORE_INS_OUT = 85 , XCORE_INS_PEEK = 86 , XCORE_INS_REMS = 87 , XCORE_INS_REMU = 88 , XCORE_INS_RETSP = 89 , XCORE_INS_SETCLK = 90 , XCORE_INS_SET = 91 , XCORE_INS_SETC = 92 , XCORE_INS_SETD = 93 , XCORE_INS_SETEV = 94 , XCORE_INS_SETN = 95 , XCORE_INS_SETPSC = 96 , XCORE_INS_SETPT = 97 , XCORE_INS_SETRDY = 98 , XCORE_INS_SETSR = 99 , XCORE_INS_SETTW = 100 , XCORE_INS_SETV = 101 , XCORE_INS_SEXT = 102 , XCORE_INS_SHL = 103 , XCORE_INS_SHR = 104 , XCORE_INS_SSYNC = 105 , XCORE_INS_ST16 = 106 , XCORE_INS_ST8 = 107 , XCORE_INS_STW = 108 , XCORE_INS_SUB = 109 , XCORE_INS_SYNCR = 110 , XCORE_INS_TESTCT = 111 , XCORE_INS_TESTLCL = 112 , XCORE_INS_TESTWCT = 113 , XCORE_INS_TSETMR = 114 , XCORE_INS_START = 115 , XCORE_INS_WAITEF = 116 , XCORE_INS_WAITET = 117 , XCORE_INS_WAITEU = 118 , XCORE_INS_XOR = 119 , XCORE_INS_ZEXT = 120 , XCORE_INS_ENDING = 121 , } # [repr (u32)] # [doc = " Group of XCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn_group { # [doc = "< = CS_GRP_INVALID"] XCORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] XCORE_GRP_JUMP = 1 , XCORE_GRP_ENDING = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] TMS320C64X_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] TMS320C64X_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] TMS320C64X_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] TMS320C64X_OP_MEM = 3 , # [doc = "< Register pair for double word ops"] TMS320C64X_OP_REGPAIR = 64 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0 , TMS320C64X_MEM_DISP_CONSTANT = 1 , TMS320C64X_MEM_DISP_REGISTER = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0 , TMS320C64X_MEM_DIR_FW = 1 , TMS320C64X_MEM_DIR_BW = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0 , TMS320C64X_MEM_MOD_NO = 1 , TMS320C64X_MEM_MOD_PRE = 2 , TMS320C64X_MEM_MOD_POST = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tms320c64x_op_mem { # [doc = "< base register"] pub base : :: std :: os :: raw :: c_uint , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_uint , # [doc = "< unit of base and offset register"] pub unit : :: std :: os :: raw :: c_uint , # [doc = "< offset scaled"] pub scaled : :: std :: os :: raw :: c_uint , # [doc = "< displacement type"] pub disptype : :: std :: os :: raw :: c_uint , # [doc = "< direction"] pub direction : :: std :: os :: raw :: c_uint , # [doc = "< modification"] pub modify : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tms320c64x_op_mem"] [:: std :: mem :: size_of :: < tms320c64x_op_mem > () - 28usize] ; ["Alignment of tms320c64x_op_mem"] [:: std :: mem :: align_of :: < tms320c64x_op_mem > () - 4usize] ; ["Offset of field: tms320c64x_op_mem::base"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , base) - 0usize] ; ["Offset of field: tms320c64x_op_mem::disp"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disp) - 4usize] ; ["Offset of field: tms320c64x_op_mem::unit"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , unit) - 8usize] ; ["Offset of field: tms320c64x_op_mem::scaled"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , scaled) - 12usize] ; ["Offset of field: tms320c64x_op_mem::disptype"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disptype) - 16usize] ; ["Offset of field: tms320c64x_op_mem::direction"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , direction) - 20usize] ; ["Offset of field: tms320c64x_op_mem::modify"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , modify) - 24usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x_op { # [doc = "< operand type"] pub type_ : tms320c64x_op_type , pub __bindgen_anon_1 : cs_tms320c64x_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tms320c64x_op__bindgen_ty_1 { # [doc = "< register value for REG operand or first register for REGPAIR operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tms320c64x_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 28usize] ; ["Alignment of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op"] [:: std :: mem :: size_of :: < cs_tms320c64x_op > () - 32usize] ; ["Alignment of cs_tms320c64x_op"] [:: std :: mem :: align_of :: < cs_tms320c64x_op > () - 4usize] ; ["Offset of field: cs_tms320c64x_op::type_"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x { pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tms320c64x_op ; 8usize] , pub condition : cs_tms320c64x__bindgen_ty_1 , pub funit : cs_tms320c64x__bindgen_ty_2 , pub parallel : :: std :: os :: raw :: c_uint , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub zero : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::zero"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , zero) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_2 { pub unit : :: std :: os :: raw :: c_uint , pub side : :: std :: os :: raw :: c_uint , pub crosspath : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_2 > () - 12usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_2 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::unit"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , unit) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::side"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , side) - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::crosspath"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , crosspath) - 8usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x"] [:: std :: mem :: size_of :: < cs_tms320c64x > () - 284usize] ; ["Alignment of cs_tms320c64x"] [:: std :: mem :: align_of :: < cs_tms320c64x > () - 4usize] ; ["Offset of field: cs_tms320c64x::op_count"] [:: std :: mem :: offset_of ! (cs_tms320c64x , op_count) - 0usize] ; ["Offset of field: cs_tms320c64x::operands"] [:: std :: mem :: offset_of ! (cs_tms320c64x , operands) - 4usize] ; ["Offset of field: cs_tms320c64x::condition"] [:: std :: mem :: offset_of ! (cs_tms320c64x , condition) - 260usize] ; ["Offset of field: cs_tms320c64x::funit"] [:: std :: mem :: offset_of ! (cs_tms320c64x , funit) - 268usize] ; ["Offset of field: cs_tms320c64x::parallel"] [:: std :: mem :: offset_of ! (cs_tms320c64x , parallel) - 280usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel) } } impl tms320c64x_reg { pub const TMS320C64X_REG_EFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ECR ; } impl tms320c64x_reg { pub const TMS320C64X_REG_IFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ISR ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0 , TMS320C64X_REG_AMR = 1 , TMS320C64X_REG_CSR = 2 , TMS320C64X_REG_DIER = 3 , TMS320C64X_REG_DNUM = 4 , TMS320C64X_REG_ECR = 5 , TMS320C64X_REG_GFPGFR = 6 , TMS320C64X_REG_GPLYA = 7 , TMS320C64X_REG_GPLYB = 8 , TMS320C64X_REG_ICR = 9 , TMS320C64X_REG_IER = 10 , TMS320C64X_REG_IERR = 11 , TMS320C64X_REG_ILC = 12 , TMS320C64X_REG_IRP = 13 , TMS320C64X_REG_ISR = 14 , TMS320C64X_REG_ISTP = 15 , TMS320C64X_REG_ITSR = 16 , TMS320C64X_REG_NRP = 17 , TMS320C64X_REG_NTSR = 18 , TMS320C64X_REG_REP = 19 , TMS320C64X_REG_RILC = 20 , TMS320C64X_REG_SSR = 21 , TMS320C64X_REG_TSCH = 22 , TMS320C64X_REG_TSCL = 23 , TMS320C64X_REG_TSR = 24 , TMS320C64X_REG_A0 = 25 , TMS320C64X_REG_A1 = 26 , TMS320C64X_REG_A2 = 27 , TMS320C64X_REG_A3 = 28 , TMS320C64X_REG_A4 = 29 , TMS320C64X_REG_A5 = 30 , TMS320C64X_REG_A6 = 31 , TMS320C64X_REG_A7 = 32 , TMS320C64X_REG_A8 = 33 , TMS320C64X_REG_A9 = 34 , TMS320C64X_REG_A10 = 35 , TMS320C64X_REG_A11 = 36 , TMS320C64X_REG_A12 = 37 , TMS320C64X_REG_A13 = 38 , TMS320C64X_REG_A14 = 39 , TMS320C64X_REG_A15 = 40 , TMS320C64X_REG_A16 = 41 , TMS320C64X_REG_A17 = 42 , TMS320C64X_REG_A18 = 43 , TMS320C64X_REG_A19 = 44 , TMS320C64X_REG_A20 = 45 , TMS320C64X_REG_A21 = 46 , TMS320C64X_REG_A22 = 47 , TMS320C64X_REG_A23 = 48 , TMS320C64X_REG_A24 = 49 , TMS320C64X_REG_A25 = 50 , TMS320C64X_REG_A26 = 51 , TMS320C64X_REG_A27 = 52 , TMS320C64X_REG_A28 = 53 , TMS320C64X_REG_A29 = 54 , TMS320C64X_REG_A30 = 55 , TMS320C64X_REG_A31 = 56 , TMS320C64X_REG_B0 = 57 , TMS320C64X_REG_B1 = 58 , TMS320C64X_REG_B2 = 59 , TMS320C64X_REG_B3 = 60 , TMS320C64X_REG_B4 = 61 , TMS320C64X_REG_B5 = 62 , TMS320C64X_REG_B6 = 63 , TMS320C64X_REG_B7 = 64 , TMS320C64X_REG_B8 = 65 , TMS320C64X_REG_B9 = 66 , TMS320C64X_REG_B10 = 67 , TMS320C64X_REG_B11 = 68 , TMS320C64X_REG_B12 = 69 , TMS320C64X_REG_B13 = 70 , TMS320C64X_REG_B14 = 71 , TMS320C64X_REG_B15 = 72 , TMS320C64X_REG_B16 = 73 , TMS320C64X_REG_B17 = 74 , TMS320C64X_REG_B18 = 75 , TMS320C64X_REG_B19 = 76 , TMS320C64X_REG_B20 = 77 , TMS320C64X_REG_B21 = 78 , TMS320C64X_REG_B22 = 79 , TMS320C64X_REG_B23 = 80 , TMS320C64X_REG_B24 = 81 , TMS320C64X_REG_B25 = 82 , TMS320C64X_REG_B26 = 83 , TMS320C64X_REG_B27 = 84 , TMS320C64X_REG_B28 = 85 , TMS320C64X_REG_B29 = 86 , TMS320C64X_REG_B30 = 87 , TMS320C64X_REG_B31 = 88 , TMS320C64X_REG_PCE1 = 89 , TMS320C64X_REG_ENDING = 90 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0 , TMS320C64X_INS_ABS = 1 , TMS320C64X_INS_ABS2 = 2 , TMS320C64X_INS_ADD = 3 , TMS320C64X_INS_ADD2 = 4 , TMS320C64X_INS_ADD4 = 5 , TMS320C64X_INS_ADDAB = 6 , TMS320C64X_INS_ADDAD = 7 , TMS320C64X_INS_ADDAH = 8 , TMS320C64X_INS_ADDAW = 9 , TMS320C64X_INS_ADDK = 10 , TMS320C64X_INS_ADDKPC = 11 , TMS320C64X_INS_ADDU = 12 , TMS320C64X_INS_AND = 13 , TMS320C64X_INS_ANDN = 14 , TMS320C64X_INS_AVG2 = 15 , TMS320C64X_INS_AVGU4 = 16 , TMS320C64X_INS_B = 17 , TMS320C64X_INS_BDEC = 18 , TMS320C64X_INS_BITC4 = 19 , TMS320C64X_INS_BNOP = 20 , TMS320C64X_INS_BPOS = 21 , TMS320C64X_INS_CLR = 22 , TMS320C64X_INS_CMPEQ = 23 , TMS320C64X_INS_CMPEQ2 = 24 , TMS320C64X_INS_CMPEQ4 = 25 , TMS320C64X_INS_CMPGT = 26 , TMS320C64X_INS_CMPGT2 = 27 , TMS320C64X_INS_CMPGTU4 = 28 , TMS320C64X_INS_CMPLT = 29 , TMS320C64X_INS_CMPLTU = 30 , TMS320C64X_INS_DEAL = 31 , TMS320C64X_INS_DOTP2 = 32 , TMS320C64X_INS_DOTPN2 = 33 , TMS320C64X_INS_DOTPNRSU2 = 34 , TMS320C64X_INS_DOTPRSU2 = 35 , TMS320C64X_INS_DOTPSU4 = 36 , TMS320C64X_INS_DOTPU4 = 37 , TMS320C64X_INS_EXT = 38 , TMS320C64X_INS_EXTU = 39 , TMS320C64X_INS_GMPGTU = 40 , TMS320C64X_INS_GMPY4 = 41 , TMS320C64X_INS_LDB = 42 , TMS320C64X_INS_LDBU = 43 , TMS320C64X_INS_LDDW = 44 , TMS320C64X_INS_LDH = 45 , TMS320C64X_INS_LDHU = 46 , TMS320C64X_INS_LDNDW = 47 , TMS320C64X_INS_LDNW = 48 , TMS320C64X_INS_LDW = 49 , TMS320C64X_INS_LMBD = 50 , TMS320C64X_INS_MAX2 = 51 , TMS320C64X_INS_MAXU4 = 52 , TMS320C64X_INS_MIN2 = 53 , TMS320C64X_INS_MINU4 = 54 , TMS320C64X_INS_MPY = 55 , TMS320C64X_INS_MPY2 = 56 , TMS320C64X_INS_MPYH = 57 , TMS320C64X_INS_MPYHI = 58 , TMS320C64X_INS_MPYHIR = 59 , TMS320C64X_INS_MPYHL = 60 , TMS320C64X_INS_MPYHLU = 61 , TMS320C64X_INS_MPYHSLU = 62 , TMS320C64X_INS_MPYHSU = 63 , TMS320C64X_INS_MPYHU = 64 , TMS320C64X_INS_MPYHULS = 65 , TMS320C64X_INS_MPYHUS = 66 , TMS320C64X_INS_MPYLH = 67 , TMS320C64X_INS_MPYLHU = 68 , TMS320C64X_INS_MPYLI = 69 , TMS320C64X_INS_MPYLIR = 70 , TMS320C64X_INS_MPYLSHU = 71 , TMS320C64X_INS_MPYLUHS = 72 , TMS320C64X_INS_MPYSU = 73 , TMS320C64X_INS_MPYSU4 = 74 , TMS320C64X_INS_MPYU = 75 , TMS320C64X_INS_MPYU4 = 76 , TMS320C64X_INS_MPYUS = 77 , TMS320C64X_INS_MVC = 78 , TMS320C64X_INS_MVD = 79 , TMS320C64X_INS_MVK = 80 , TMS320C64X_INS_MVKL = 81 , TMS320C64X_INS_MVKLH = 82 , TMS320C64X_INS_NOP = 83 , TMS320C64X_INS_NORM = 84 , TMS320C64X_INS_OR = 85 , TMS320C64X_INS_PACK2 = 86 , TMS320C64X_INS_PACKH2 = 87 , TMS320C64X_INS_PACKH4 = 88 , TMS320C64X_INS_PACKHL2 = 89 , TMS320C64X_INS_PACKL4 = 90 , TMS320C64X_INS_PACKLH2 = 91 , TMS320C64X_INS_ROTL = 92 , TMS320C64X_INS_SADD = 93 , TMS320C64X_INS_SADD2 = 94 , TMS320C64X_INS_SADDU4 = 95 , TMS320C64X_INS_SADDUS2 = 96 , TMS320C64X_INS_SAT = 97 , TMS320C64X_INS_SET = 98 , TMS320C64X_INS_SHFL = 99 , TMS320C64X_INS_SHL = 100 , TMS320C64X_INS_SHLMB = 101 , TMS320C64X_INS_SHR = 102 , TMS320C64X_INS_SHR2 = 103 , TMS320C64X_INS_SHRMB = 104 , TMS320C64X_INS_SHRU = 105 , TMS320C64X_INS_SHRU2 = 106 , TMS320C64X_INS_SMPY = 107 , TMS320C64X_INS_SMPY2 = 108 , TMS320C64X_INS_SMPYH = 109 , TMS320C64X_INS_SMPYHL = 110 , TMS320C64X_INS_SMPYLH = 111 , TMS320C64X_INS_SPACK2 = 112 , TMS320C64X_INS_SPACKU4 = 113 , TMS320C64X_INS_SSHL = 114 , TMS320C64X_INS_SSHVL = 115 , TMS320C64X_INS_SSHVR = 116 , TMS320C64X_INS_SSUB = 117 , TMS320C64X_INS_STB = 118 , TMS320C64X_INS_STDW = 119 , TMS320C64X_INS_STH = 120 , TMS320C64X_INS_STNDW = 121 , TMS320C64X_INS_STNW = 122 , TMS320C64X_INS_STW = 123 , TMS320C64X_INS_SUB = 124 , TMS320C64X_INS_SUB2 = 125 , TMS320C64X_INS_SUB4 = 126 , TMS320C64X_INS_SUBAB = 127 , TMS320C64X_INS_SUBABS4 = 128 , TMS320C64X_INS_SUBAH = 129 , TMS320C64X_INS_SUBAW = 130 , TMS320C64X_INS_SUBC = 131 , TMS320C64X_INS_SUBU = 132 , TMS320C64X_INS_SWAP4 = 133 , TMS320C64X_INS_UNPKHU4 = 134 , TMS320C64X_INS_UNPKLU4 = 135 , TMS320C64X_INS_XOR = 136 , TMS320C64X_INS_XPND2 = 137 , TMS320C64X_INS_XPND4 = 138 , TMS320C64X_INS_IDLE = 139 , TMS320C64X_INS_MV = 140 , TMS320C64X_INS_NEG = 141 , TMS320C64X_INS_NOT = 142 , TMS320C64X_INS_SWAP2 = 143 , TMS320C64X_INS_ZERO = 144 , TMS320C64X_INS_ENDING = 145 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn_group { # [doc = "< = CS_GRP_INVALID"] TMS320C64X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] TMS320C64X_GRP_JUMP = 1 , TMS320C64X_GRP_FUNIT_D = 128 , TMS320C64X_GRP_FUNIT_L = 129 , TMS320C64X_GRP_FUNIT_M = 130 , TMS320C64X_GRP_FUNIT_S = 131 , TMS320C64X_GRP_FUNIT_NO = 132 , TMS320C64X_GRP_ENDING = 133 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0 , TMS320C64X_FUNIT_D = 1 , TMS320C64X_FUNIT_L = 2 , TMS320C64X_FUNIT_M = 3 , TMS320C64X_FUNIT_S = 4 , TMS320C64X_FUNIT_NO = 5 , } # [repr (u32)] # [doc = " M680X registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_reg { M680X_REG_INVALID = 0 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_A = 1 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_B = 2 , # [doc = "< HD6309"] M680X_REG_E = 3 , # [doc = "< HD6309"] M680X_REG_F = 4 , # [doc = "< HD6309"] M680X_REG_0 = 5 , # [doc = "< M6801/3/9, HD6301/9"] M680X_REG_D = 6 , # [doc = "< HD6309"] M680X_REG_W = 7 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_CC = 8 , # [doc = "< M6809/M6309"] M680X_REG_DP = 9 , # [doc = "< M6309"] M680X_REG_MD = 10 , # [doc = "< M6808"] M680X_REG_HX = 11 , # [doc = "< M6808"] M680X_REG_H = 12 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_X = 13 , # [doc = "< M6809/M6309"] M680X_REG_Y = 14 , # [doc = "< M6809/M6309"] M680X_REG_S = 15 , # [doc = "< M6809/M6309"] M680X_REG_U = 16 , # [doc = "< M6309"] M680X_REG_V = 17 , # [doc = "< M6309"] M680X_REG_Q = 18 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_PC = 19 , # [doc = "< CPU12"] M680X_REG_TMP2 = 20 , # [doc = "< CPU12"] M680X_REG_TMP3 = 21 , # [doc = "< <-- mark the end of the list of registers"] M680X_REG_ENDING = 22 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M680X_OP_INVALID = 0 , # [doc = "< = Register operand."] M680X_OP_REGISTER = 1 , # [doc = "< = Immediate operand."] M680X_OP_IMMEDIATE = 2 , # [doc = "< = Indexed addressing operand."] M680X_OP_INDEXED = 3 , # [doc = "< = Extended addressing operand."] M680X_OP_EXTENDED = 4 , # [doc = "< = Direct addressing operand."] M680X_OP_DIRECT = 5 , # [doc = "< = Relative addressing operand."] M680X_OP_RELATIVE = 6 , # [doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."] M680X_OP_CONSTANT = 7 , } # [doc = " Instruction's operand referring to indexed addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_idx { # [doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"] pub base_reg : m680x_reg , # [doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"] pub offset_reg : m680x_reg , # [doc = "< 5-,8- or 16-bit offset. See also offset_bits."] pub offset : i16 , # [doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"] pub offset_addr : u16 , # [doc = "< offset width in bits for indexed addressing"] pub offset_bits : u8 , # [doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"] pub inc_dec : i8 , # [doc = "< 8-bit flags (see above)"] pub flags : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_idx"] [:: std :: mem :: size_of :: < m680x_op_idx > () - 16usize] ; ["Alignment of m680x_op_idx"] [:: std :: mem :: align_of :: < m680x_op_idx > () - 4usize] ; ["Offset of field: m680x_op_idx::base_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , base_reg) - 0usize] ; ["Offset of field: m680x_op_idx::offset_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_reg) - 4usize] ; ["Offset of field: m680x_op_idx::offset"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset) - 8usize] ; ["Offset of field: m680x_op_idx::offset_addr"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_addr) - 10usize] ; ["Offset of field: m680x_op_idx::offset_bits"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_bits) - 12usize] ; ["Offset of field: m680x_op_idx::inc_dec"] [:: std :: mem :: offset_of ! (m680x_op_idx , inc_dec) - 13usize] ; ["Offset of field: m680x_op_idx::flags"] [:: std :: mem :: offset_of ! (m680x_op_idx , flags) - 14usize] ; } ; # [doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_rel { # [doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."] pub address : u16 , # [doc = "< the offset/displacement value"] pub offset : i16 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_rel"] [:: std :: mem :: size_of :: < m680x_op_rel > () - 4usize] ; ["Alignment of m680x_op_rel"] [:: std :: mem :: align_of :: < m680x_op_rel > () - 2usize] ; ["Offset of field: m680x_op_rel::address"] [:: std :: mem :: offset_of ! (m680x_op_rel , address) - 0usize] ; ["Offset of field: m680x_op_rel::offset"] [:: std :: mem :: offset_of ! (m680x_op_rel , offset) - 2usize] ; } ; # [doc = " Instruction's operand referring to extended addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_ext { # [doc = "< The absolute address"] pub address : u16 , # [doc = "< true if extended indirect addressing"] pub indirect : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_ext"] [:: std :: mem :: size_of :: < m680x_op_ext > () - 4usize] ; ["Alignment of m680x_op_ext"] [:: std :: mem :: align_of :: < m680x_op_ext > () - 2usize] ; ["Offset of field: m680x_op_ext::address"] [:: std :: mem :: offset_of ! (m680x_op_ext , address) - 0usize] ; ["Offset of field: m680x_op_ext::indirect"] [:: std :: mem :: offset_of ! (m680x_op_ext , indirect) - 2usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x_op { pub type_ : m680x_op_type , pub __bindgen_anon_1 : cs_m680x_op__bindgen_ty_1 , # [doc = "< size of this operand (in bytes)"] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m680x_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< register value for REG operand"] pub reg : m680x_reg , # [doc = "< Indexed addressing operand"] pub idx : m680x_op_idx , # [doc = "< Relative address. operand (Bcc/LBcc)"] pub rel : m680x_op_rel , # [doc = "< Extended address"] pub ext : m680x_op_ext , # [doc = "<</ Direct address (lower 8-bit)"] pub direct_addr : u8 , # [doc = "< constant value (bit index, page nr.)"] pub const_val : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m680x_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m680x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::idx"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , idx) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::rel"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , rel) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , ext) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::direct_addr"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , direct_addr) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::const_val"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , const_val) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op"] [:: std :: mem :: size_of :: < cs_m680x_op > () - 24usize] ; ["Alignment of cs_m680x_op"] [:: std :: mem :: align_of :: < cs_m680x_op > () - 4usize] ; ["Offset of field: cs_m680x_op::type_"] [:: std :: mem :: offset_of ! (cs_m680x_op , type_) - 0usize] ; ["Offset of field: cs_m680x_op::size"] [:: std :: mem :: offset_of ! (cs_m680x_op , size) - 20usize] ; ["Offset of field: cs_m680x_op::access"] [:: std :: mem :: offset_of ! (cs_m680x_op , access) - 21usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access) } } # [repr (u32)] # [doc = " Group of M680X instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_group_type { M680X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M680X_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] M680X_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] M680X_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] M680X_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] M680X_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEDGE; not used"] M680X_GRP_PRIV = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M680X_GRP_BRAREL = 7 , M680X_GRP_ENDING = 8 , } # [doc = " The M680X instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x { # [doc = "< See: M680X instruction flags"] pub flags : u8 , # [doc = "< number of operands for the instruction or 0"] pub op_count : u8 , # [doc = "< operands for this insn."] pub operands : [cs_m680x_op ; 9usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x"] [:: std :: mem :: size_of :: < cs_m680x > () - 220usize] ; ["Alignment of cs_m680x"] [:: std :: mem :: align_of :: < cs_m680x > () - 4usize] ; ["Offset of field: cs_m680x::flags"] [:: std :: mem :: offset_of ! (cs_m680x , flags) - 0usize] ; ["Offset of field: cs_m680x::op_count"] [:: std :: mem :: offset_of ! (cs_m680x , op_count) - 1usize] ; ["Offset of field: cs_m680x::operands"] [:: std :: mem :: offset_of ! (cs_m680x , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " M680X instruction IDs"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_insn { M680X_INS_INVLD = 0 , # [doc = "< M6800/1/2/3"] M680X_INS_ABA = 1 , M680X_INS_ABX = 2 , M680X_INS_ABY = 3 , M680X_INS_ADC = 4 , M680X_INS_ADCA = 5 , M680X_INS_ADCB = 6 , M680X_INS_ADCD = 7 , M680X_INS_ADCR = 8 , M680X_INS_ADD = 9 , M680X_INS_ADDA = 10 , M680X_INS_ADDB = 11 , M680X_INS_ADDD = 12 , M680X_INS_ADDE = 13 , M680X_INS_ADDF = 14 , M680X_INS_ADDR = 15 , M680X_INS_ADDW = 16 , M680X_INS_AIM = 17 , M680X_INS_AIS = 18 , M680X_INS_AIX = 19 , M680X_INS_AND = 20 , M680X_INS_ANDA = 21 , M680X_INS_ANDB = 22 , M680X_INS_ANDCC = 23 , M680X_INS_ANDD = 24 , M680X_INS_ANDR = 25 , M680X_INS_ASL = 26 , M680X_INS_ASLA = 27 , M680X_INS_ASLB = 28 , # [doc = "< or LSLD"] M680X_INS_ASLD = 29 , M680X_INS_ASR = 30 , M680X_INS_ASRA = 31 , M680X_INS_ASRB = 32 , M680X_INS_ASRD = 33 , M680X_INS_ASRX = 34 , M680X_INS_BAND = 35 , # [doc = "< or BHS"] M680X_INS_BCC = 36 , M680X_INS_BCLR = 37 , # [doc = "< or BLO"] M680X_INS_BCS = 38 , M680X_INS_BEOR = 39 , M680X_INS_BEQ = 40 , M680X_INS_BGE = 41 , M680X_INS_BGND = 42 , M680X_INS_BGT = 43 , M680X_INS_BHCC = 44 , M680X_INS_BHCS = 45 , M680X_INS_BHI = 46 , M680X_INS_BIAND = 47 , M680X_INS_BIEOR = 48 , M680X_INS_BIH = 49 , M680X_INS_BIL = 50 , M680X_INS_BIOR = 51 , M680X_INS_BIT = 52 , M680X_INS_BITA = 53 , M680X_INS_BITB = 54 , M680X_INS_BITD = 55 , M680X_INS_BITMD = 56 , M680X_INS_BLE = 57 , M680X_INS_BLS = 58 , M680X_INS_BLT = 59 , M680X_INS_BMC = 60 , M680X_INS_BMI = 61 , M680X_INS_BMS = 62 , M680X_INS_BNE = 63 , M680X_INS_BOR = 64 , M680X_INS_BPL = 65 , M680X_INS_BRCLR = 66 , M680X_INS_BRSET = 67 , M680X_INS_BRA = 68 , M680X_INS_BRN = 69 , M680X_INS_BSET = 70 , M680X_INS_BSR = 71 , M680X_INS_BVC = 72 , M680X_INS_BVS = 73 , M680X_INS_CALL = 74 , # [doc = "< M6800/1/2/3"] M680X_INS_CBA = 75 , M680X_INS_CBEQ = 76 , M680X_INS_CBEQA = 77 , M680X_INS_CBEQX = 78 , # [doc = "< M6800/1/2/3"] M680X_INS_CLC = 79 , # [doc = "< M6800/1/2/3"] M680X_INS_CLI = 80 , M680X_INS_CLR = 81 , M680X_INS_CLRA = 82 , M680X_INS_CLRB = 83 , M680X_INS_CLRD = 84 , M680X_INS_CLRE = 85 , M680X_INS_CLRF = 86 , M680X_INS_CLRH = 87 , M680X_INS_CLRW = 88 , M680X_INS_CLRX = 89 , # [doc = "< M6800/1/2/3"] M680X_INS_CLV = 90 , M680X_INS_CMP = 91 , M680X_INS_CMPA = 92 , M680X_INS_CMPB = 93 , M680X_INS_CMPD = 94 , M680X_INS_CMPE = 95 , M680X_INS_CMPF = 96 , M680X_INS_CMPR = 97 , M680X_INS_CMPS = 98 , M680X_INS_CMPU = 99 , M680X_INS_CMPW = 100 , M680X_INS_CMPX = 101 , M680X_INS_CMPY = 102 , M680X_INS_COM = 103 , M680X_INS_COMA = 104 , M680X_INS_COMB = 105 , M680X_INS_COMD = 106 , M680X_INS_COME = 107 , M680X_INS_COMF = 108 , M680X_INS_COMW = 109 , M680X_INS_COMX = 110 , M680X_INS_CPD = 111 , M680X_INS_CPHX = 112 , M680X_INS_CPS = 113 , # [doc = "< M6800/1/2/3"] M680X_INS_CPX = 114 , M680X_INS_CPY = 115 , M680X_INS_CWAI = 116 , M680X_INS_DAA = 117 , M680X_INS_DBEQ = 118 , M680X_INS_DBNE = 119 , M680X_INS_DBNZ = 120 , M680X_INS_DBNZA = 121 , M680X_INS_DBNZX = 122 , M680X_INS_DEC = 123 , M680X_INS_DECA = 124 , M680X_INS_DECB = 125 , M680X_INS_DECD = 126 , M680X_INS_DECE = 127 , M680X_INS_DECF = 128 , M680X_INS_DECW = 129 , M680X_INS_DECX = 130 , # [doc = "< M6800/1/2/3"] M680X_INS_DES = 131 , # [doc = "< M6800/1/2/3"] M680X_INS_DEX = 132 , M680X_INS_DEY = 133 , M680X_INS_DIV = 134 , M680X_INS_DIVD = 135 , M680X_INS_DIVQ = 136 , M680X_INS_EDIV = 137 , M680X_INS_EDIVS = 138 , M680X_INS_EIM = 139 , M680X_INS_EMACS = 140 , M680X_INS_EMAXD = 141 , M680X_INS_EMAXM = 142 , M680X_INS_EMIND = 143 , M680X_INS_EMINM = 144 , M680X_INS_EMUL = 145 , M680X_INS_EMULS = 146 , M680X_INS_EOR = 147 , M680X_INS_EORA = 148 , M680X_INS_EORB = 149 , M680X_INS_EORD = 150 , M680X_INS_EORR = 151 , M680X_INS_ETBL = 152 , M680X_INS_EXG = 153 , M680X_INS_FDIV = 154 , M680X_INS_IBEQ = 155 , M680X_INS_IBNE = 156 , M680X_INS_IDIV = 157 , M680X_INS_IDIVS = 158 , M680X_INS_ILLGL = 159 , M680X_INS_INC = 160 , M680X_INS_INCA = 161 , M680X_INS_INCB = 162 , M680X_INS_INCD = 163 , M680X_INS_INCE = 164 , M680X_INS_INCF = 165 , M680X_INS_INCW = 166 , M680X_INS_INCX = 167 , # [doc = "< M6800/1/2/3"] M680X_INS_INS = 168 , # [doc = "< M6800/1/2/3"] M680X_INS_INX = 169 , M680X_INS_INY = 170 , M680X_INS_JMP = 171 , M680X_INS_JSR = 172 , # [doc = "< or LBHS"] M680X_INS_LBCC = 173 , # [doc = "< or LBLO"] M680X_INS_LBCS = 174 , M680X_INS_LBEQ = 175 , M680X_INS_LBGE = 176 , M680X_INS_LBGT = 177 , M680X_INS_LBHI = 178 , M680X_INS_LBLE = 179 , M680X_INS_LBLS = 180 , M680X_INS_LBLT = 181 , M680X_INS_LBMI = 182 , M680X_INS_LBNE = 183 , M680X_INS_LBPL = 184 , M680X_INS_LBRA = 185 , M680X_INS_LBRN = 186 , M680X_INS_LBSR = 187 , M680X_INS_LBVC = 188 , M680X_INS_LBVS = 189 , M680X_INS_LDA = 190 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAA = 191 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAB = 192 , M680X_INS_LDB = 193 , M680X_INS_LDBT = 194 , M680X_INS_LDD = 195 , M680X_INS_LDE = 196 , M680X_INS_LDF = 197 , M680X_INS_LDHX = 198 , M680X_INS_LDMD = 199 , M680X_INS_LDQ = 200 , M680X_INS_LDS = 201 , M680X_INS_LDU = 202 , M680X_INS_LDW = 203 , M680X_INS_LDX = 204 , M680X_INS_LDY = 205 , M680X_INS_LEAS = 206 , M680X_INS_LEAU = 207 , M680X_INS_LEAX = 208 , M680X_INS_LEAY = 209 , M680X_INS_LSL = 210 , M680X_INS_LSLA = 211 , M680X_INS_LSLB = 212 , M680X_INS_LSLD = 213 , M680X_INS_LSLX = 214 , M680X_INS_LSR = 215 , M680X_INS_LSRA = 216 , M680X_INS_LSRB = 217 , # [doc = "< or ASRD"] M680X_INS_LSRD = 218 , M680X_INS_LSRW = 219 , M680X_INS_LSRX = 220 , M680X_INS_MAXA = 221 , M680X_INS_MAXM = 222 , M680X_INS_MEM = 223 , M680X_INS_MINA = 224 , M680X_INS_MINM = 225 , M680X_INS_MOV = 226 , M680X_INS_MOVB = 227 , M680X_INS_MOVW = 228 , M680X_INS_MUL = 229 , M680X_INS_MULD = 230 , M680X_INS_NEG = 231 , M680X_INS_NEGA = 232 , M680X_INS_NEGB = 233 , M680X_INS_NEGD = 234 , M680X_INS_NEGX = 235 , M680X_INS_NOP = 236 , M680X_INS_NSA = 237 , M680X_INS_OIM = 238 , M680X_INS_ORA = 239 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAA = 240 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAB = 241 , M680X_INS_ORB = 242 , M680X_INS_ORCC = 243 , M680X_INS_ORD = 244 , M680X_INS_ORR = 245 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHA = 246 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHB = 247 , M680X_INS_PSHC = 248 , M680X_INS_PSHD = 249 , M680X_INS_PSHH = 250 , M680X_INS_PSHS = 251 , M680X_INS_PSHSW = 252 , M680X_INS_PSHU = 253 , M680X_INS_PSHUW = 254 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHX = 255 , M680X_INS_PSHY = 256 , # [doc = "< M6800/1/2/3"] M680X_INS_PULA = 257 , # [doc = "< M6800/1/2/3"] M680X_INS_PULB = 258 , M680X_INS_PULC = 259 , M680X_INS_PULD = 260 , M680X_INS_PULH = 261 , M680X_INS_PULS = 262 , M680X_INS_PULSW = 263 , M680X_INS_PULU = 264 , M680X_INS_PULUW = 265 , # [doc = "< M6800/1/2/3"] M680X_INS_PULX = 266 , M680X_INS_PULY = 267 , M680X_INS_REV = 268 , M680X_INS_REVW = 269 , M680X_INS_ROL = 270 , M680X_INS_ROLA = 271 , M680X_INS_ROLB = 272 , M680X_INS_ROLD = 273 , M680X_INS_ROLW = 274 , M680X_INS_ROLX = 275 , M680X_INS_ROR = 276 , M680X_INS_RORA = 277 , M680X_INS_RORB = 278 , M680X_INS_RORD = 279 , M680X_INS_RORW = 280 , M680X_INS_RORX = 281 , M680X_INS_RSP = 282 , M680X_INS_RTC = 283 , M680X_INS_RTI = 284 , M680X_INS_RTS = 285 , # [doc = "< M6800/1/2/3"] M680X_INS_SBA = 286 , M680X_INS_SBC = 287 , M680X_INS_SBCA = 288 , M680X_INS_SBCB = 289 , M680X_INS_SBCD = 290 , M680X_INS_SBCR = 291 , M680X_INS_SEC = 292 , M680X_INS_SEI = 293 , M680X_INS_SEV = 294 , M680X_INS_SEX = 295 , M680X_INS_SEXW = 296 , M680X_INS_SLP = 297 , M680X_INS_STA = 298 , # [doc = "< M6800/1/2/3"] M680X_INS_STAA = 299 , # [doc = "< M6800/1/2/3"] M680X_INS_STAB = 300 , M680X_INS_STB = 301 , M680X_INS_STBT = 302 , M680X_INS_STD = 303 , M680X_INS_STE = 304 , M680X_INS_STF = 305 , M680X_INS_STOP = 306 , M680X_INS_STHX = 307 , M680X_INS_STQ = 308 , M680X_INS_STS = 309 , M680X_INS_STU = 310 , M680X_INS_STW = 311 , M680X_INS_STX = 312 , M680X_INS_STY = 313 , M680X_INS_SUB = 314 , M680X_INS_SUBA = 315 , M680X_INS_SUBB = 316 , M680X_INS_SUBD = 317 , M680X_INS_SUBE = 318 , M680X_INS_SUBF = 319 , M680X_INS_SUBR = 320 , M680X_INS_SUBW = 321 , M680X_INS_SWI = 322 , M680X_INS_SWI2 = 323 , M680X_INS_SWI3 = 324 , M680X_INS_SYNC = 325 , # [doc = "< M6800/1/2/3"] M680X_INS_TAB = 326 , # [doc = "< M6800/1/2/3"] M680X_INS_TAP = 327 , M680X_INS_TAX = 328 , # [doc = "< M6800/1/2/3"] M680X_INS_TBA = 329 , M680X_INS_TBEQ = 330 , M680X_INS_TBL = 331 , M680X_INS_TBNE = 332 , M680X_INS_TEST = 333 , M680X_INS_TFM = 334 , M680X_INS_TFR = 335 , M680X_INS_TIM = 336 , # [doc = "< M6800/1/2/3"] M680X_INS_TPA = 337 , M680X_INS_TST = 338 , M680X_INS_TSTA = 339 , M680X_INS_TSTB = 340 , M680X_INS_TSTD = 341 , M680X_INS_TSTE = 342 , M680X_INS_TSTF = 343 , M680X_INS_TSTW = 344 , M680X_INS_TSTX = 345 , # [doc = "< M6800/1/2/3"] M680X_INS_TSX = 346 , M680X_INS_TSY = 347 , M680X_INS_TXA = 348 , # [doc = "< M6800/1/2/3"] M680X_INS_TXS = 349 , M680X_INS_TYS = 350 , # [doc = "< M6800/1/2/3"] M680X_INS_WAI = 351 , M680X_INS_WAIT = 352 , M680X_INS_WAV = 353 , M680X_INS_WAVR = 354 , # [doc = "< HD6301"] M680X_INS_XGDX = 355 , M680X_INS_XGDY = 356 , M680X_INS_ENDING = 357 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_evm { # [doc = "< number of items popped from the stack"] pub pop : :: std :: os :: raw :: c_uchar , # [doc = "< number of items pushed into the stack"] pub push : :: std :: os :: raw :: c_uchar , # [doc = "< gas fee for the instruction"] pub fee : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_evm"] [:: std :: mem :: size_of :: < cs_evm > () - 8usize] ; ["Alignment of cs_evm"] [:: std :: mem :: align_of :: < cs_evm > () - 4usize] ; ["Offset of field: cs_evm::pop"] [:: std :: mem :: offset_of ! (cs_evm , pop) - 0usize] ; ["Offset of field: cs_evm::push"] [:: std :: mem :: offset_of ! (cs_evm , push) - 1usize] ; ["Offset of field: cs_evm::fee"] [:: std :: mem :: offset_of ! (cs_evm , fee) - 4usize] ; } ; # [repr (u32)] # [doc = " EVM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn { EVM_INS_STOP = 0 , EVM_INS_ADD = 1 , EVM_INS_MUL = 2 , EVM_INS_SUB = 3 , EVM_INS_DIV = 4 , EVM_INS_SDIV = 5 , EVM_INS_MOD = 6 , EVM_INS_SMOD = 7 , EVM_INS_ADDMOD = 8 , EVM_INS_MULMOD = 9 , EVM_INS_EXP = 10 , EVM_INS_SIGNEXTEND = 11 , EVM_INS_LT = 16 , EVM_INS_GT = 17 , EVM_INS_SLT = 18 , EVM_INS_SGT = 19 , EVM_INS_EQ = 20 , EVM_INS_ISZERO = 21 , EVM_INS_AND = 22 , EVM_INS_OR = 23 , EVM_INS_XOR = 24 , EVM_INS_NOT = 25 , EVM_INS_BYTE = 26 , EVM_INS_SHA3 = 32 , EVM_INS_ADDRESS = 48 , EVM_INS_BALANCE = 49 , EVM_INS_ORIGIN = 50 , EVM_INS_CALLER = 51 , EVM_INS_CALLVALUE = 52 , EVM_INS_CALLDATALOAD = 53 , EVM_INS_CALLDATASIZE = 54 , EVM_INS_CALLDATACOPY = 55 , EVM_INS_CODESIZE = 56 , EVM_INS_CODECOPY = 57 , EVM_INS_GASPRICE = 58 , EVM_INS_EXTCODESIZE = 59 , EVM_INS_EXTCODECOPY = 60 , EVM_INS_RETURNDATASIZE = 61 , EVM_INS_RETURNDATACOPY = 62 , EVM_INS_BLOCKHASH = 64 , EVM_INS_COINBASE = 65 , EVM_INS_TIMESTAMP = 66 , EVM_INS_NUMBER = 67 , EVM_INS_DIFFICULTY = 68 , EVM_INS_GASLIMIT = 69 , EVM_INS_POP = 80 , EVM_INS_MLOAD = 81 , EVM_INS_MSTORE = 82 , EVM_INS_MSTORE8 = 83 , EVM_INS_SLOAD = 84 , EVM_INS_SSTORE = 85 , EVM_INS_JUMP = 86 , EVM_INS_JUMPI = 87 , EVM_INS_PC = 88 , EVM_INS_MSIZE = 89 , EVM_INS_GAS = 90 , EVM_INS_JUMPDEST = 91 , EVM_INS_PUSH1 = 96 , EVM_INS_PUSH2 = 97 , EVM_INS_PUSH3 = 98 , EVM_INS_PUSH4 = 99 , EVM_INS_PUSH5 = 100 , EVM_INS_PUSH6 = 101 , EVM_INS_PUSH7 = 102 , EVM_INS_PUSH8 = 103 , EVM_INS_PUSH9 = 104 , EVM_INS_PUSH10 = 105 , EVM_INS_PUSH11 = 106 , EVM_INS_PUSH12 = 107 , EVM_INS_PUSH13 = 108 , EVM_INS_PUSH14 = 109 , EVM_INS_PUSH15 = 110 , EVM_INS_PUSH16 = 111 , EVM_INS_PUSH17 = 112 , EVM_INS_PUSH18 = 113 , EVM_INS_PUSH19 = 114 , EVM_INS_PUSH20 = 115 , EVM_INS_PUSH21 = 116 , EVM_INS_PUSH22 = 117 , EVM_INS_PUSH23 = 118 , EVM_INS_PUSH24 = 119 , EVM_INS_PUSH25 = 120 , EVM_INS_PUSH26 = 121 , EVM_INS_PUSH27 = 122 , EVM_INS_PUSH28 = 123 , EVM_INS_PUSH29 = 124 , EVM_INS_PUSH30 = 125 , EVM_INS_PUSH31 = 126 , EVM_INS_PUSH32 = 127 , EVM_INS_DUP1 = 128 , EVM_INS_DUP2 = 129 , EVM_INS_DUP3 = 130 , EVM_INS_DUP4 = 131 , EVM_INS_DUP5 = 132 , EVM_INS_DUP6 = 133 , EVM_INS_DUP7 = 134 , EVM_INS_DUP8 = 135 , EVM_INS_DUP9 = 136 , EVM_INS_DUP10 = 137 , EVM_INS_DUP11 = 138 , EVM_INS_DUP12 = 139 , EVM_INS_DUP13 = 140 , EVM_INS_DUP14 = 141 , EVM_INS_DUP15 = 142 , EVM_INS_DUP16 = 143 , EVM_INS_SWAP1 = 144 , EVM_INS_SWAP2 = 145 , EVM_INS_SWAP3 = 146 , EVM_INS_SWAP4 = 147 , EVM_INS_SWAP5 = 148 , EVM_INS_SWAP6 = 149 , EVM_INS_SWAP7 = 150 , EVM_INS_SWAP8 = 151 , EVM_INS_SWAP9 = 152 , EVM_INS_SWAP10 = 153 , EVM_INS_SWAP11 = 154 , EVM_INS_SWAP12 = 155 , EVM_INS_SWAP13 = 156 , EVM_INS_SWAP14 = 157 , EVM_INS_SWAP15 = 158 , EVM_INS_SWAP16 = 159 , EVM_INS_LOG0 = 160 , EVM_INS_LOG1 = 161 , EVM_INS_LOG2 = 162 , EVM_INS_LOG3 = 163 , EVM_INS_LOG4 = 164 , EVM_INS_CREATE = 240 , EVM_INS_CALL = 241 , EVM_INS_CALLCODE = 242 , EVM_INS_RETURN = 243 , EVM_INS_DELEGATECALL = 244 , EVM_INS_CALLBLACKBOX = 245 , EVM_INS_STATICCALL = 250 , EVM_INS_REVERT = 253 , EVM_INS_SUICIDE = 255 , EVM_INS_INVALID = 512 , EVM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of EVM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn_group { # [doc = "< = CS_GRP_INVALID"] EVM_GRP_INVALID = 0 , # [doc = "< all jump instructions"] EVM_GRP_JUMP = 1 , # [doc = "< math instructions"] EVM_GRP_MATH = 8 , # [doc = "< instructions write to stack"] EVM_GRP_STACK_WRITE = 9 , # [doc = "< instructions read from stack"] EVM_GRP_STACK_READ = 10 , # [doc = "< instructions write to memory"] EVM_GRP_MEM_WRITE = 11 , # [doc = "< instructions read from memory"] EVM_GRP_MEM_READ = 12 , # [doc = "< instructions write to storage"] EVM_GRP_STORE_WRITE = 13 , # [doc = "< instructions read from storage"] EVM_GRP_STORE_READ = 14 , # [doc = "< instructions halt execution"] EVM_GRP_HALT = 15 , # [doc = "< <-- mark the end of the list of groups"] EVM_GRP_ENDING = 16 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_op_type { RISCV_OP_INVALID = 0 , RISCV_OP_REG = 1 , RISCV_OP_IMM = 2 , RISCV_OP_MEM = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct riscv_op_mem { pub base : :: std :: os :: raw :: c_uint , pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of riscv_op_mem"] [:: std :: mem :: size_of :: < riscv_op_mem > () - 16usize] ; ["Alignment of riscv_op_mem"] [:: std :: mem :: align_of :: < riscv_op_mem > () - 8usize] ; ["Offset of field: riscv_op_mem::base"] [:: std :: mem :: offset_of ! (riscv_op_mem , base) - 0usize] ; ["Offset of field: riscv_op_mem::disp"] [:: std :: mem :: offset_of ! (riscv_op_mem , disp) - 8usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv_op { pub type_ : riscv_op_type , pub __bindgen_anon_1 : cs_riscv_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_riscv_op__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub imm : i64 , pub mem : riscv_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_riscv_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_riscv_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op"] [:: std :: mem :: size_of :: < cs_riscv_op > () - 24usize] ; ["Alignment of cs_riscv_op"] [:: std :: mem :: align_of :: < cs_riscv_op > () - 8usize] ; ["Offset of field: cs_riscv_op::type_"] [:: std :: mem :: offset_of ! (cs_riscv_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv { pub need_effective_addr : bool , pub op_count : u8 , pub operands : [cs_riscv_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv"] [:: std :: mem :: size_of :: < cs_riscv > () - 200usize] ; ["Alignment of cs_riscv"] [:: std :: mem :: align_of :: < cs_riscv > () - 8usize] ; ["Offset of field: cs_riscv::need_effective_addr"] [:: std :: mem :: offset_of ! (cs_riscv , need_effective_addr) - 0usize] ; ["Offset of field: cs_riscv::op_count"] [:: std :: mem :: offset_of ! (cs_riscv , op_count) - 1usize] ; ["Offset of field: cs_riscv::operands"] [:: std :: mem :: offset_of ! (cs_riscv , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}" , self . need_effective_addr , self . op_count , self . operands) } } impl riscv_reg { pub const RISCV_REG_ZERO : riscv_reg = riscv_reg :: RISCV_REG_X0 ; } impl riscv_reg { pub const RISCV_REG_RA : riscv_reg = riscv_reg :: RISCV_REG_X1 ; } impl riscv_reg { pub const RISCV_REG_SP : riscv_reg = riscv_reg :: RISCV_REG_X2 ; } impl riscv_reg { pub const RISCV_REG_GP : riscv_reg = riscv_reg :: RISCV_REG_X3 ; } impl riscv_reg { pub const RISCV_REG_TP : riscv_reg = riscv_reg :: RISCV_REG_X4 ; } impl riscv_reg { pub const RISCV_REG_T0 : riscv_reg = riscv_reg :: RISCV_REG_X5 ; } impl riscv_reg { pub const RISCV_REG_T1 : riscv_reg = riscv_reg :: RISCV_REG_X6 ; } impl riscv_reg { pub const RISCV_REG_T2 : riscv_reg = riscv_reg :: RISCV_REG_X7 ; } impl riscv_reg { pub const RISCV_REG_S0 : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_FP : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_S1 : riscv_reg = riscv_reg :: RISCV_REG_X9 ; } impl riscv_reg { pub const RISCV_REG_A0 : riscv_reg = riscv_reg :: RISCV_REG_X10 ; } impl riscv_reg { pub const RISCV_REG_A1 : riscv_reg = riscv_reg :: RISCV_REG_X11 ; } impl riscv_reg { pub const RISCV_REG_A2 : riscv_reg = riscv_reg :: RISCV_REG_X12 ; } impl riscv_reg { pub const RISCV_REG_A3 : riscv_reg = riscv_reg :: RISCV_REG_X13 ; } impl riscv_reg { pub const RISCV_REG_A4 : riscv_reg = riscv_reg :: RISCV_REG_X14 ; } impl riscv_reg { pub const RISCV_REG_A5 : riscv_reg = riscv_reg :: RISCV_REG_X15 ; } impl riscv_reg { pub const RISCV_REG_A6 : riscv_reg = riscv_reg :: RISCV_REG_X16 ; } impl riscv_reg { pub const RISCV_REG_A7 : riscv_reg = riscv_reg :: RISCV_REG_X17 ; } impl riscv_reg { pub const RISCV_REG_S2 : riscv_reg = riscv_reg :: RISCV_REG_X18 ; } impl riscv_reg { pub const RISCV_REG_S3 : riscv_reg = riscv_reg :: RISCV_REG_X19 ; } impl riscv_reg { pub const RISCV_REG_S4 : riscv_reg = riscv_reg :: RISCV_REG_X20 ; } impl riscv_reg { pub const RISCV_REG_S5 : riscv_reg = riscv_reg :: RISCV_REG_X21 ; } impl riscv_reg { pub const RISCV_REG_S6 : riscv_reg = riscv_reg :: RISCV_REG_X22 ; } impl riscv_reg { pub const RISCV_REG_S7 : riscv_reg = riscv_reg :: RISCV_REG_X23 ; } impl riscv_reg { pub const RISCV_REG_S8 : riscv_reg = riscv_reg :: RISCV_REG_X24 ; } impl riscv_reg { pub const RISCV_REG_S9 : riscv_reg = riscv_reg :: RISCV_REG_X25 ; } impl riscv_reg { pub const RISCV_REG_S10 : riscv_reg = riscv_reg :: RISCV_REG_X26 ; } impl riscv_reg { pub const RISCV_REG_S11 : riscv_reg = riscv_reg :: RISCV_REG_X27 ; } impl riscv_reg { pub const RISCV_REG_T3 : riscv_reg = riscv_reg :: RISCV_REG_X28 ; } impl riscv_reg { pub const RISCV_REG_T4 : riscv_reg = riscv_reg :: RISCV_REG_X29 ; } impl riscv_reg { pub const RISCV_REG_T5 : riscv_reg = riscv_reg :: RISCV_REG_X30 ; } impl riscv_reg { pub const RISCV_REG_T6 : riscv_reg = riscv_reg :: RISCV_REG_X31 ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_reg { RISCV_REG_INVALID = 0 , RISCV_REG_X0 = 1 , RISCV_REG_X1 = 2 , RISCV_REG_X2 = 3 , RISCV_REG_X3 = 4 , RISCV_REG_X4 = 5 , RISCV_REG_X5 = 6 , RISCV_REG_X6 = 7 , RISCV_REG_X7 = 8 , RISCV_REG_X8 = 9 , RISCV_REG_X9 = 10 , RISCV_REG_X10 = 11 , RISCV_REG_X11 = 12 , RISCV_REG_X12 = 13 , RISCV_REG_X13 = 14 , RISCV_REG_X14 = 15 , RISCV_REG_X15 = 16 , RISCV_REG_X16 = 17 , RISCV_REG_X17 = 18 , RISCV_REG_X18 = 19 , RISCV_REG_X19 = 20 , RISCV_REG_X20 = 21 , RISCV_REG_X21 = 22 , RISCV_REG_X22 = 23 , RISCV_REG_X23 = 24 , RISCV_REG_X24 = 25 , RISCV_REG_X25 = 26 , RISCV_REG_X26 = 27 , RISCV_REG_X27 = 28 , RISCV_REG_X28 = 29 , RISCV_REG_X29 = 30 , RISCV_REG_X30 = 31 , RISCV_REG_X31 = 32 , RISCV_REG_F0_32 = 33 , RISCV_REG_F0_64 = 34 , RISCV_REG_F1_32 = 35 , RISCV_REG_F1_64 = 36 , RISCV_REG_F2_32 = 37 , RISCV_REG_F2_64 = 38 , RISCV_REG_F3_32 = 39 , RISCV_REG_F3_64 = 40 , RISCV_REG_F4_32 = 41 , RISCV_REG_F4_64 = 42 , RISCV_REG_F5_32 = 43 , RISCV_REG_F5_64 = 44 , RISCV_REG_F6_32 = 45 , RISCV_REG_F6_64 = 46 , RISCV_REG_F7_32 = 47 , RISCV_REG_F7_64 = 48 , RISCV_REG_F8_32 = 49 , RISCV_REG_F8_64 = 50 , RISCV_REG_F9_32 = 51 , RISCV_REG_F9_64 = 52 , RISCV_REG_F10_32 = 53 , RISCV_REG_F10_64 = 54 , RISCV_REG_F11_32 = 55 , RISCV_REG_F11_64 = 56 , RISCV_REG_F12_32 = 57 , RISCV_REG_F12_64 = 58 , RISCV_REG_F13_32 = 59 , RISCV_REG_F13_64 = 60 , RISCV_REG_F14_32 = 61 , RISCV_REG_F14_64 = 62 , RISCV_REG_F15_32 = 63 , RISCV_REG_F15_64 = 64 , RISCV_REG_F16_32 = 65 , RISCV_REG_F16_64 = 66 , RISCV_REG_F17_32 = 67 , RISCV_REG_F17_64 = 68 , RISCV_REG_F18_32 = 69 , RISCV_REG_F18_64 = 70 , RISCV_REG_F19_32 = 71 , RISCV_REG_F19_64 = 72 , RISCV_REG_F20_32 = 73 , RISCV_REG_F20_64 = 74 , RISCV_REG_F21_32 = 75 , RISCV_REG_F21_64 = 76 , RISCV_REG_F22_32 = 77 , RISCV_REG_F22_64 = 78 , RISCV_REG_F23_32 = 79 , RISCV_REG_F23_64 = 80 , RISCV_REG_F24_32 = 81 , RISCV_REG_F24_64 = 82 , RISCV_REG_F25_32 = 83 , RISCV_REG_F25_64 = 84 , RISCV_REG_F26_32 = 85 , RISCV_REG_F26_64 = 86 , RISCV_REG_F27_32 = 87 , RISCV_REG_F27_64 = 88 , RISCV_REG_F28_32 = 89 , RISCV_REG_F28_64 = 90 , RISCV_REG_F29_32 = 91 , RISCV_REG_F29_64 = 92 , RISCV_REG_F30_32 = 93 , RISCV_REG_F30_64 = 94 , RISCV_REG_F31_32 = 95 , RISCV_REG_F31_64 = 96 , RISCV_REG_ENDING = 97 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn { RISCV_INS_INVALID = 0 , RISCV_INS_ADD = 1 , RISCV_INS_ADDI = 2 , RISCV_INS_ADDIW = 3 , RISCV_INS_ADDW = 4 , RISCV_INS_AMOADD_D = 5 , RISCV_INS_AMOADD_D_AQ = 6 , RISCV_INS_AMOADD_D_AQ_RL = 7 , RISCV_INS_AMOADD_D_RL = 8 , RISCV_INS_AMOADD_W = 9 , RISCV_INS_AMOADD_W_AQ = 10 , RISCV_INS_AMOADD_W_AQ_RL = 11 , RISCV_INS_AMOADD_W_RL = 12 , RISCV_INS_AMOAND_D = 13 , RISCV_INS_AMOAND_D_AQ = 14 , RISCV_INS_AMOAND_D_AQ_RL = 15 , RISCV_INS_AMOAND_D_RL = 16 , RISCV_INS_AMOAND_W = 17 , RISCV_INS_AMOAND_W_AQ = 18 , RISCV_INS_AMOAND_W_AQ_RL = 19 , RISCV_INS_AMOAND_W_RL = 20 , RISCV_INS_AMOMAXU_D = 21 , RISCV_INS_AMOMAXU_D_AQ = 22 , RISCV_INS_AMOMAXU_D_AQ_RL = 23 , RISCV_INS_AMOMAXU_D_RL = 24 , RISCV_INS_AMOMAXU_W = 25 , RISCV_INS_AMOMAXU_W_AQ = 26 , RISCV_INS_AMOMAXU_W_AQ_RL = 27 , RISCV_INS_AMOMAXU_W_RL = 28 , RISCV_INS_AMOMAX_D = 29 , RISCV_INS_AMOMAX_D_AQ = 30 , RISCV_INS_AMOMAX_D_AQ_RL = 31 , RISCV_INS_AMOMAX_D_RL = 32 , RISCV_INS_AMOMAX_W = 33 , RISCV_INS_AMOMAX_W_AQ = 34 , RISCV_INS_AMOMAX_W_AQ_RL = 35 , RISCV_INS_AMOMAX_W_RL = 36 , RISCV_INS_AMOMINU_D = 37 , RISCV_INS_AMOMINU_D_AQ = 38 , RISCV_INS_AMOMINU_D_AQ_RL = 39 , RISCV_INS_AMOMINU_D_RL = 40 , RISCV_INS_AMOMINU_W = 41 , RISCV_INS_AMOMINU_W_AQ = 42 , RISCV_INS_AMOMINU_W_AQ_RL = 43 , RISCV_INS_AMOMINU_W_RL = 44 , RISCV_INS_AMOMIN_D = 45 , RISCV_INS_AMOMIN_D_AQ = 46 , RISCV_INS_AMOMIN_D_AQ_RL = 47 , RISCV_INS_AMOMIN_D_RL = 48 , RISCV_INS_AMOMIN_W = 49 , RISCV_INS_AMOMIN_W_AQ = 50 , RISCV_INS_AMOMIN_W_AQ_RL = 51 , RISCV_INS_AMOMIN_W_RL = 52 , RISCV_INS_AMOOR_D = 53 , RISCV_INS_AMOOR_D_AQ = 54 , RISCV_INS_AMOOR_D_AQ_RL = 55 , RISCV_INS_AMOOR_D_RL = 56 , RISCV_INS_AMOOR_W = 57 , RISCV_INS_AMOOR_W_AQ = 58 , RISCV_INS_AMOOR_W_AQ_RL = 59 , RISCV_INS_AMOOR_W_RL = 60 , RISCV_INS_AMOSWAP_D = 61 , RISCV_INS_AMOSWAP_D_AQ = 62 , RISCV_INS_AMOSWAP_D_AQ_RL = 63 , RISCV_INS_AMOSWAP_D_RL = 64 , RISCV_INS_AMOSWAP_W = 65 , RISCV_INS_AMOSWAP_W_AQ = 66 , RISCV_INS_AMOSWAP_W_AQ_RL = 67 , RISCV_INS_AMOSWAP_W_RL = 68 , RISCV_INS_AMOXOR_D = 69 , RISCV_INS_AMOXOR_D_AQ = 70 , RISCV_INS_AMOXOR_D_AQ_RL = 71 , RISCV_INS_AMOXOR_D_RL = 72 , RISCV_INS_AMOXOR_W = 73 , RISCV_INS_AMOXOR_W_AQ = 74 , RISCV_INS_AMOXOR_W_AQ_RL = 75 , RISCV_INS_AMOXOR_W_RL = 76 , RISCV_INS_AND = 77 , RISCV_INS_ANDI = 78 , RISCV_INS_AUIPC = 79 , RISCV_INS_BEQ = 80 , RISCV_INS_BGE = 81 , RISCV_INS_BGEU = 82 , RISCV_INS_BLT = 83 , RISCV_INS_BLTU = 84 , RISCV_INS_BNE = 85 , RISCV_INS_CSRRC = 86 , RISCV_INS_CSRRCI = 87 , RISCV_INS_CSRRS = 88 , RISCV_INS_CSRRSI = 89 , RISCV_INS_CSRRW = 90 , RISCV_INS_CSRRWI = 91 , RISCV_INS_C_ADD = 92 , RISCV_INS_C_ADDI = 93 , RISCV_INS_C_ADDI16SP = 94 , RISCV_INS_C_ADDI4SPN = 95 , RISCV_INS_C_ADDIW = 96 , RISCV_INS_C_ADDW = 97 , RISCV_INS_C_AND = 98 , RISCV_INS_C_ANDI = 99 , RISCV_INS_C_BEQZ = 100 , RISCV_INS_C_BNEZ = 101 , RISCV_INS_C_EBREAK = 102 , RISCV_INS_C_FLD = 103 , RISCV_INS_C_FLDSP = 104 , RISCV_INS_C_FLW = 105 , RISCV_INS_C_FLWSP = 106 , RISCV_INS_C_FSD = 107 , RISCV_INS_C_FSDSP = 108 , RISCV_INS_C_FSW = 109 , RISCV_INS_C_FSWSP = 110 , RISCV_INS_C_J = 111 , RISCV_INS_C_JAL = 112 , RISCV_INS_C_JALR = 113 , RISCV_INS_C_JR = 114 , RISCV_INS_C_LD = 115 , RISCV_INS_C_LDSP = 116 , RISCV_INS_C_LI = 117 , RISCV_INS_C_LUI = 118 , RISCV_INS_C_LW = 119 , RISCV_INS_C_LWSP = 120 , RISCV_INS_C_MV = 121 , RISCV_INS_C_NOP = 122 , RISCV_INS_C_OR = 123 , RISCV_INS_C_SD = 124 , RISCV_INS_C_SDSP = 125 , RISCV_INS_C_SLLI = 126 , RISCV_INS_C_SRAI = 127 , RISCV_INS_C_SRLI = 128 , RISCV_INS_C_SUB = 129 , RISCV_INS_C_SUBW = 130 , RISCV_INS_C_SW = 131 , RISCV_INS_C_SWSP = 132 , RISCV_INS_C_UNIMP = 133 , RISCV_INS_C_XOR = 134 , RISCV_INS_DIV = 135 , RISCV_INS_DIVU = 136 , RISCV_INS_DIVUW = 137 , RISCV_INS_DIVW = 138 , RISCV_INS_EBREAK = 139 , RISCV_INS_ECALL = 140 , RISCV_INS_FADD_D = 141 , RISCV_INS_FADD_S = 142 , RISCV_INS_FCLASS_D = 143 , RISCV_INS_FCLASS_S = 144 , RISCV_INS_FCVT_D_L = 145 , RISCV_INS_FCVT_D_LU = 146 , RISCV_INS_FCVT_D_S = 147 , RISCV_INS_FCVT_D_W = 148 , RISCV_INS_FCVT_D_WU = 149 , RISCV_INS_FCVT_LU_D = 150 , RISCV_INS_FCVT_LU_S = 151 , RISCV_INS_FCVT_L_D = 152 , RISCV_INS_FCVT_L_S = 153 , RISCV_INS_FCVT_S_D = 154 , RISCV_INS_FCVT_S_L = 155 , RISCV_INS_FCVT_S_LU = 156 , RISCV_INS_FCVT_S_W = 157 , RISCV_INS_FCVT_S_WU = 158 , RISCV_INS_FCVT_WU_D = 159 , RISCV_INS_FCVT_WU_S = 160 , RISCV_INS_FCVT_W_D = 161 , RISCV_INS_FCVT_W_S = 162 , RISCV_INS_FDIV_D = 163 , RISCV_INS_FDIV_S = 164 , RISCV_INS_FENCE = 165 , RISCV_INS_FENCE_I = 166 , RISCV_INS_FENCE_TSO = 167 , RISCV_INS_FEQ_D = 168 , RISCV_INS_FEQ_S = 169 , RISCV_INS_FLD = 170 , RISCV_INS_FLE_D = 171 , RISCV_INS_FLE_S = 172 , RISCV_INS_FLT_D = 173 , RISCV_INS_FLT_S = 174 , RISCV_INS_FLW = 175 , RISCV_INS_FMADD_D = 176 , RISCV_INS_FMADD_S = 177 , RISCV_INS_FMAX_D = 178 , RISCV_INS_FMAX_S = 179 , RISCV_INS_FMIN_D = 180 , RISCV_INS_FMIN_S = 181 , RISCV_INS_FMSUB_D = 182 , RISCV_INS_FMSUB_S = 183 , RISCV_INS_FMUL_D = 184 , RISCV_INS_FMUL_S = 185 , RISCV_INS_FMV_D_X = 186 , RISCV_INS_FMV_W_X = 187 , RISCV_INS_FMV_X_D = 188 , RISCV_INS_FMV_X_W = 189 , RISCV_INS_FNMADD_D = 190 , RISCV_INS_FNMADD_S = 191 , RISCV_INS_FNMSUB_D = 192 , RISCV_INS_FNMSUB_S = 193 , RISCV_INS_FSD = 194 , RISCV_INS_FSGNJN_D = 195 , RISCV_INS_FSGNJN_S = 196 , RISCV_INS_FSGNJX_D = 197 , RISCV_INS_FSGNJX_S = 198 , RISCV_INS_FSGNJ_D = 199 , RISCV_INS_FSGNJ_S = 200 , RISCV_INS_FSQRT_D = 201 , RISCV_INS_FSQRT_S = 202 , RISCV_INS_FSUB_D = 203 , RISCV_INS_FSUB_S = 204 , RISCV_INS_FSW = 205 , RISCV_INS_JAL = 206 , RISCV_INS_JALR = 207 , RISCV_INS_LB = 208 , RISCV_INS_LBU = 209 , RISCV_INS_LD = 210 , RISCV_INS_LH = 211 , RISCV_INS_LHU = 212 , RISCV_INS_LR_D = 213 , RISCV_INS_LR_D_AQ = 214 , RISCV_INS_LR_D_AQ_RL = 215 , RISCV_INS_LR_D_RL = 216 , RISCV_INS_LR_W = 217 , RISCV_INS_LR_W_AQ = 218 , RISCV_INS_LR_W_AQ_RL = 219 , RISCV_INS_LR_W_RL = 220 , RISCV_INS_LUI = 221 , RISCV_INS_LW = 222 , RISCV_INS_LWU = 223 , RISCV_INS_MRET = 224 , RISCV_INS_MUL = 225 , RISCV_INS_MULH = 226 , RISCV_INS_MULHSU = 227 , RISCV_INS_MULHU = 228 , RISCV_INS_MULW = 229 , RISCV_INS_OR = 230 , RISCV_INS_ORI = 231 , RISCV_INS_REM = 232 , RISCV_INS_REMU = 233 , RISCV_INS_REMUW = 234 , RISCV_INS_REMW = 235 , RISCV_INS_SB = 236 , RISCV_INS_SC_D = 237 , RISCV_INS_SC_D_AQ = 238 , RISCV_INS_SC_D_AQ_RL = 239 , RISCV_INS_SC_D_RL = 240 , RISCV_INS_SC_W = 241 , RISCV_INS_SC_W_AQ = 242 , RISCV_INS_SC_W_AQ_RL = 243 , RISCV_INS_SC_W_RL = 244 , RISCV_INS_SD = 245 , RISCV_INS_SFENCE_VMA = 246 , RISCV_INS_SH = 247 , RISCV_INS_SLL = 248 , RISCV_INS_SLLI = 249 , RISCV_INS_SLLIW = 250 , RISCV_INS_SLLW = 251 , RISCV_INS_SLT = 252 , RISCV_INS_SLTI = 253 , RISCV_INS_SLTIU = 254 , RISCV_INS_SLTU = 255 , RISCV_INS_SRA = 256 , RISCV_INS_SRAI = 257 , RISCV_INS_SRAIW = 258 , RISCV_INS_SRAW = 259 , RISCV_INS_SRET = 260 , RISCV_INS_SRL = 261 , RISCV_INS_SRLI = 262 , RISCV_INS_SRLIW = 263 , RISCV_INS_SRLW = 264 , RISCV_INS_SUB = 265 , RISCV_INS_SUBW = 266 , RISCV_INS_SW = 267 , RISCV_INS_UNIMP = 268 , RISCV_INS_URET = 269 , RISCV_INS_WFI = 270 , RISCV_INS_XOR = 271 , RISCV_INS_XORI = 272 , RISCV_INS_ENDING = 273 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn_group { # [doc = "< = CS_GRP_INVALID"] RISCV_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] RISCV_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] RISCV_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] RISCV_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] RISCV_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] RISCV_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] RISCV_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] RISCV_GRP_BRANCH_RELATIVE = 7 , RISCV_GRP_ISRV32 = 128 , RISCV_GRP_ISRV64 = 129 , RISCV_GRP_HASSTDEXTA = 130 , RISCV_GRP_HASSTDEXTC = 131 , RISCV_GRP_HASSTDEXTD = 132 , RISCV_GRP_HASSTDEXTF = 133 , RISCV_GRP_HASSTDEXTM = 134 , RISCV_GRP_ENDING = 135 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_op_type { WASM_OP_INVALID = 0 , WASM_OP_NONE = 1 , WASM_OP_INT7 = 2 , WASM_OP_VARUINT32 = 3 , WASM_OP_VARUINT64 = 4 , WASM_OP_UINT32 = 5 , WASM_OP_UINT64 = 6 , WASM_OP_IMM = 7 , WASM_OP_BRTABLE = 8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_wasm_brtable { pub length : u32 , pub address : u64 , pub default_target : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_brtable"] [:: std :: mem :: size_of :: < cs_wasm_brtable > () - 24usize] ; ["Alignment of cs_wasm_brtable"] [:: std :: mem :: align_of :: < cs_wasm_brtable > () - 8usize] ; ["Offset of field: cs_wasm_brtable::length"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , length) - 0usize] ; ["Offset of field: cs_wasm_brtable::address"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , address) - 8usize] ; ["Offset of field: cs_wasm_brtable::default_target"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , default_target) - 16usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm_op { pub type_ : wasm_op_type , pub size : u32 , pub __bindgen_anon_1 : cs_wasm_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_wasm_op__bindgen_ty_1 { pub int7 : i8 , pub varuint32 : u32 , pub varuint64 : u64 , pub uint32 : u32 , pub uint64 : u64 , pub immediate : [u32 ; 2usize] , pub brtable : cs_wasm_brtable , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_wasm_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_wasm_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::int7"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , int7) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::immediate"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , immediate) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::brtable"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , brtable) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op"] [:: std :: mem :: size_of :: < cs_wasm_op > () - 32usize] ; ["Alignment of cs_wasm_op"] [:: std :: mem :: align_of :: < cs_wasm_op > () - 8usize] ; ["Offset of field: cs_wasm_op::type_"] [:: std :: mem :: offset_of ! (cs_wasm_op , type_) - 0usize] ; ["Offset of field: cs_wasm_op::size"] [:: std :: mem :: offset_of ! (cs_wasm_op , size) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . size , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm { pub op_count : u8 , pub operands : [cs_wasm_op ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm"] [:: std :: mem :: size_of :: < cs_wasm > () - 72usize] ; ["Alignment of cs_wasm"] [:: std :: mem :: align_of :: < cs_wasm > () - 8usize] ; ["Offset of field: cs_wasm::op_count"] [:: std :: mem :: offset_of ! (cs_wasm , op_count) - 0usize] ; ["Offset of field: cs_wasm::operands"] [:: std :: mem :: offset_of ! (cs_wasm , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " WASM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn { WASM_INS_UNREACHABLE = 0 , WASM_INS_NOP = 1 , WASM_INS_BLOCK = 2 , WASM_INS_LOOP = 3 , WASM_INS_IF = 4 , WASM_INS_ELSE = 5 , WASM_INS_END = 11 , WASM_INS_BR = 12 , WASM_INS_BR_IF = 13 , WASM_INS_BR_TABLE = 14 , WASM_INS_RETURN = 15 , WASM_INS_CALL = 16 , WASM_INS_CALL_INDIRECT = 17 , WASM_INS_DROP = 26 , WASM_INS_SELECT = 27 , WASM_INS_GET_LOCAL = 32 , WASM_INS_SET_LOCAL = 33 , WASM_INS_TEE_LOCAL = 34 , WASM_INS_GET_GLOBAL = 35 , WASM_INS_SET_GLOBAL = 36 , WASM_INS_I32_LOAD = 40 , WASM_INS_I64_LOAD = 41 , WASM_INS_F32_LOAD = 42 , WASM_INS_F64_LOAD = 43 , WASM_INS_I32_LOAD8_S = 44 , WASM_INS_I32_LOAD8_U = 45 , WASM_INS_I32_LOAD16_S = 46 , WASM_INS_I32_LOAD16_U = 47 , WASM_INS_I64_LOAD8_S = 48 , WASM_INS_I64_LOAD8_U = 49 , WASM_INS_I64_LOAD16_S = 50 , WASM_INS_I64_LOAD16_U = 51 , WASM_INS_I64_LOAD32_S = 52 , WASM_INS_I64_LOAD32_U = 53 , WASM_INS_I32_STORE = 54 , WASM_INS_I64_STORE = 55 , WASM_INS_F32_STORE = 56 , WASM_INS_F64_STORE = 57 , WASM_INS_I32_STORE8 = 58 , WASM_INS_I32_STORE16 = 59 , WASM_INS_I64_STORE8 = 60 , WASM_INS_I64_STORE16 = 61 , WASM_INS_I64_STORE32 = 62 , WASM_INS_CURRENT_MEMORY = 63 , WASM_INS_GROW_MEMORY = 64 , WASM_INS_I32_CONST = 65 , WASM_INS_I64_CONST = 66 , WASM_INS_F32_CONST = 67 , WASM_INS_F64_CONST = 68 , WASM_INS_I32_EQZ = 69 , WASM_INS_I32_EQ = 70 , WASM_INS_I32_NE = 71 , WASM_INS_I32_LT_S = 72 , WASM_INS_I32_LT_U = 73 , WASM_INS_I32_GT_S = 74 , WASM_INS_I32_GT_U = 75 , WASM_INS_I32_LE_S = 76 , WASM_INS_I32_LE_U = 77 , WASM_INS_I32_GE_S = 78 , WASM_INS_I32_GE_U = 79 , WASM_INS_I64_EQZ = 80 , WASM_INS_I64_EQ = 81 , WASM_INS_I64_NE = 82 , WASM_INS_I64_LT_S = 83 , WASM_INS_I64_LT_U = 84 , WASN_INS_I64_GT_S = 85 , WASM_INS_I64_GT_U = 86 , WASM_INS_I64_LE_S = 87 , WASM_INS_I64_LE_U = 88 , WASM_INS_I64_GE_S = 89 , WASM_INS_I64_GE_U = 90 , WASM_INS_F32_EQ = 91 , WASM_INS_F32_NE = 92 , WASM_INS_F32_LT = 93 , WASM_INS_F32_GT = 94 , WASM_INS_F32_LE = 95 , WASM_INS_F32_GE = 96 , WASM_INS_F64_EQ = 97 , WASM_INS_F64_NE = 98 , WASM_INS_F64_LT = 99 , WASM_INS_F64_GT = 100 , WASM_INS_F64_LE = 101 , WASM_INS_F64_GE = 102 , WASM_INS_I32_CLZ = 103 , WASM_INS_I32_CTZ = 104 , WASM_INS_I32_POPCNT = 105 , WASM_INS_I32_ADD = 106 , WASM_INS_I32_SUB = 107 , WASM_INS_I32_MUL = 108 , WASM_INS_I32_DIV_S = 109 , WASM_INS_I32_DIV_U = 110 , WASM_INS_I32_REM_S = 111 , WASM_INS_I32_REM_U = 112 , WASM_INS_I32_AND = 113 , WASM_INS_I32_OR = 114 , WASM_INS_I32_XOR = 115 , WASM_INS_I32_SHL = 116 , WASM_INS_I32_SHR_S = 117 , WASM_INS_I32_SHR_U = 118 , WASM_INS_I32_ROTL = 119 , WASM_INS_I32_ROTR = 120 , WASM_INS_I64_CLZ = 121 , WASM_INS_I64_CTZ = 122 , WASM_INS_I64_POPCNT = 123 , WASM_INS_I64_ADD = 124 , WASM_INS_I64_SUB = 125 , WASM_INS_I64_MUL = 126 , WASM_INS_I64_DIV_S = 127 , WASM_INS_I64_DIV_U = 128 , WASM_INS_I64_REM_S = 129 , WASM_INS_I64_REM_U = 130 , WASM_INS_I64_AND = 131 , WASM_INS_I64_OR = 132 , WASM_INS_I64_XOR = 133 , WASM_INS_I64_SHL = 134 , WASM_INS_I64_SHR_S = 135 , WASM_INS_I64_SHR_U = 136 , WASM_INS_I64_ROTL = 137 , WASM_INS_I64_ROTR = 138 , WASM_INS_F32_ABS = 139 , WASM_INS_F32_NEG = 140 , WASM_INS_F32_CEIL = 141 , WASM_INS_F32_FLOOR = 142 , WASM_INS_F32_TRUNC = 143 , WASM_INS_F32_NEAREST = 144 , WASM_INS_F32_SQRT = 145 , WASM_INS_F32_ADD = 146 , WASM_INS_F32_SUB = 147 , WASM_INS_F32_MUL = 148 , WASM_INS_F32_DIV = 149 , WASM_INS_F32_MIN = 150 , WASM_INS_F32_MAX = 151 , WASM_INS_F32_COPYSIGN = 152 , WASM_INS_F64_ABS = 153 , WASM_INS_F64_NEG = 154 , WASM_INS_F64_CEIL = 155 , WASM_INS_F64_FLOOR = 156 , WASM_INS_F64_TRUNC = 157 , WASM_INS_F64_NEAREST = 158 , WASM_INS_F64_SQRT = 159 , WASM_INS_F64_ADD = 160 , WASM_INS_F64_SUB = 161 , WASM_INS_F64_MUL = 162 , WASM_INS_F64_DIV = 163 , WASM_INS_F64_MIN = 164 , WASM_INS_F64_MAX = 165 , WASM_INS_F64_COPYSIGN = 166 , WASM_INS_I32_WARP_I64 = 167 , WASP_INS_I32_TRUNC_S_F32 = 168 , WASM_INS_I32_TRUNC_U_F32 = 169 , WASM_INS_I32_TRUNC_S_F64 = 170 , WASM_INS_I32_TRUNC_U_F64 = 171 , WASM_INS_I64_EXTEND_S_I32 = 172 , WASM_INS_I64_EXTEND_U_I32 = 173 , WASM_INS_I64_TRUNC_S_F32 = 174 , WASM_INS_I64_TRUNC_U_F32 = 175 , WASM_INS_I64_TRUNC_S_F64 = 176 , WASM_INS_I64_TRUNC_U_F64 = 177 , WASM_INS_F32_CONVERT_S_I32 = 178 , WASM_INS_F32_CONVERT_U_I32 = 179 , WASM_INS_F32_CONVERT_S_I64 = 180 , WASM_INS_F32_CONVERT_U_I64 = 181 , WASM_INS_F32_DEMOTE_F64 = 182 , WASM_INS_F64_CONVERT_S_I32 = 183 , WASM_INS_F64_CONVERT_U_I32 = 184 , WASM_INS_F64_CONVERT_S_I64 = 185 , WASM_INS_F64_CONVERT_U_I64 = 186 , WASM_INS_F64_PROMOTE_F32 = 187 , WASM_INS_I32_REINTERPRET_F32 = 188 , WASM_INS_I64_REINTERPRET_F64 = 189 , WASM_INS_F32_REINTERPRET_I32 = 190 , WASM_INS_F64_REINTERPRET_I64 = 191 , WASM_INS_INVALID = 512 , WASM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of WASM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn_group { # [doc = "< = CS_GRP_INVALID"] WASM_GRP_INVALID = 0 , WASM_GRP_NUMBERIC = 8 , WASM_GRP_PARAMETRIC = 9 , WASM_GRP_VARIABLE = 10 , WASM_GRP_MEMORY = 11 , WASM_GRP_CONTROL = 12 , # [doc = "< <-- mark the end of the list of groups"] WASM_GRP_ENDING = 13 , } # [repr (u32)] # [doc = " MOS65XX registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_reg { MOS65XX_REG_INVALID = 0 , # [doc = "< accumulator"] MOS65XX_REG_ACC = 1 , # [doc = "< X index register"] MOS65XX_REG_X = 2 , # [doc = "< Y index register"] MOS65XX_REG_Y = 3 , # [doc = "< status register"] MOS65XX_REG_P = 4 , # [doc = "< stack pointer register"] MOS65XX_REG_SP = 5 , # [doc = "< direct page register"] MOS65XX_REG_DP = 6 , # [doc = "< data bank register"] MOS65XX_REG_B = 7 , # [doc = "< program bank register"] MOS65XX_REG_K = 8 , MOS65XX_REG_ENDING = 9 , } # [repr (u32)] # [doc = " MOS65XX Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_address_mode { # [doc = "< No address mode."] MOS65XX_AM_NONE = 0 , # [doc = "< implied addressing (no addressing mode)"] MOS65XX_AM_IMP = 1 , # [doc = "< accumulator addressing"] MOS65XX_AM_ACC = 2 , # [doc = "< 8/16 Bit immediate value"] MOS65XX_AM_IMM = 3 , # [doc = "< relative addressing used by branches"] MOS65XX_AM_REL = 4 , # [doc = "< interrupt addressing"] MOS65XX_AM_INT = 5 , # [doc = "< memory block addressing"] MOS65XX_AM_BLOCK = 6 , # [doc = "< zeropage addressing"] MOS65XX_AM_ZP = 7 , # [doc = "< indexed zeropage addressing by the X index register"] MOS65XX_AM_ZP_X = 8 , # [doc = "< indexed zeropage addressing by the Y index register"] MOS65XX_AM_ZP_Y = 9 , # [doc = "< zero page address, branch relative address"] MOS65XX_AM_ZP_REL = 10 , # [doc = "< indirect zeropage addressing"] MOS65XX_AM_ZP_IND = 11 , # [doc = "< indexed zeropage indirect addressing by the X index register"] MOS65XX_AM_ZP_X_IND = 12 , # [doc = "< indirect zeropage indexed addressing by the Y index register"] MOS65XX_AM_ZP_IND_Y = 13 , # [doc = "< zeropage indirect long addressing"] MOS65XX_AM_ZP_IND_LONG = 14 , # [doc = "< zeropage indirect long addressing indexed by Y register"] MOS65XX_AM_ZP_IND_LONG_Y = 15 , # [doc = "< absolute addressing"] MOS65XX_AM_ABS = 16 , # [doc = "< indexed absolute addressing by the X index register"] MOS65XX_AM_ABS_X = 17 , # [doc = "< indexed absolute addressing by the Y index register"] MOS65XX_AM_ABS_Y = 18 , # [doc = "< absolute indirect addressing"] MOS65XX_AM_ABS_IND = 19 , # [doc = "< indexed absolute indirect addressing by the X index register"] MOS65XX_AM_ABS_X_IND = 20 , # [doc = "< absolute indirect long addressing"] MOS65XX_AM_ABS_IND_LONG = 21 , # [doc = "< absolute long address mode"] MOS65XX_AM_ABS_LONG = 22 , # [doc = "< absolute long address mode, indexed by X register"] MOS65XX_AM_ABS_LONG_X = 23 , # [doc = "< stack relative addressing"] MOS65XX_AM_SR = 24 , # [doc = "< indirect stack relative addressing indexed by the Y index register"] MOS65XX_AM_SR_IND_Y = 25 , } # [repr (u32)] # [doc = " MOS65XX instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_insn { MOS65XX_INS_INVALID = 0 , MOS65XX_INS_ADC = 1 , MOS65XX_INS_AND = 2 , MOS65XX_INS_ASL = 3 , MOS65XX_INS_BBR = 4 , MOS65XX_INS_BBS = 5 , MOS65XX_INS_BCC = 6 , MOS65XX_INS_BCS = 7 , MOS65XX_INS_BEQ = 8 , MOS65XX_INS_BIT = 9 , MOS65XX_INS_BMI = 10 , MOS65XX_INS_BNE = 11 , MOS65XX_INS_BPL = 12 , MOS65XX_INS_BRA = 13 , MOS65XX_INS_BRK = 14 , MOS65XX_INS_BRL = 15 , MOS65XX_INS_BVC = 16 , MOS65XX_INS_BVS = 17 , MOS65XX_INS_CLC = 18 , MOS65XX_INS_CLD = 19 , MOS65XX_INS_CLI = 20 , MOS65XX_INS_CLV = 21 , MOS65XX_INS_CMP = 22 , MOS65XX_INS_COP = 23 , MOS65XX_INS_CPX = 24 , MOS65XX_INS_CPY = 25 , MOS65XX_INS_DEC = 26 , MOS65XX_INS_DEX = 27 , MOS65XX_INS_DEY = 28 , MOS65XX_INS_EOR = 29 , MOS65XX_INS_INC = 30 , MOS65XX_INS_INX = 31 , MOS65XX_INS_INY = 32 , MOS65XX_INS_JML = 33 , MOS65XX_INS_JMP = 34 , MOS65XX_INS_JSL = 35 , MOS65XX_INS_JSR = 36 , MOS65XX_INS_LDA = 37 , MOS65XX_INS_LDX = 38 , MOS65XX_INS_LDY = 39 , MOS65XX_INS_LSR = 40 , MOS65XX_INS_MVN = 41 , MOS65XX_INS_MVP = 42 , MOS65XX_INS_NOP = 43 , MOS65XX_INS_ORA = 44 , MOS65XX_INS_PEA = 45 , MOS65XX_INS_PEI = 46 , MOS65XX_INS_PER = 47 , MOS65XX_INS_PHA = 48 , MOS65XX_INS_PHB = 49 , MOS65XX_INS_PHD = 50 , MOS65XX_INS_PHK = 51 , MOS65XX_INS_PHP = 52 , MOS65XX_INS_PHX = 53 , MOS65XX_INS_PHY = 54 , MOS65XX_INS_PLA = 55 , MOS65XX_INS_PLB = 56 , MOS65XX_INS_PLD = 57 , MOS65XX_INS_PLP = 58 , MOS65XX_INS_PLX = 59 , MOS65XX_INS_PLY = 60 , MOS65XX_INS_REP = 61 , MOS65XX_INS_RMB = 62 , MOS65XX_INS_ROL = 63 , MOS65XX_INS_ROR = 64 , MOS65XX_INS_RTI = 65 , MOS65XX_INS_RTL = 66 , MOS65XX_INS_RTS = 67 , MOS65XX_INS_SBC = 68 , MOS65XX_INS_SEC = 69 , MOS65XX_INS_SED = 70 , MOS65XX_INS_SEI = 71 , MOS65XX_INS_SEP = 72 , MOS65XX_INS_SMB = 73 , MOS65XX_INS_STA = 74 , MOS65XX_INS_STP = 75 , MOS65XX_INS_STX = 76 , MOS65XX_INS_STY = 77 , MOS65XX_INS_STZ = 78 , MOS65XX_INS_TAX = 79 , MOS65XX_INS_TAY = 80 , MOS65XX_INS_TCD = 81 , MOS65XX_INS_TCS = 82 , MOS65XX_INS_TDC = 83 , MOS65XX_INS_TRB = 84 , MOS65XX_INS_TSB = 85 , MOS65XX_INS_TSC = 86 , MOS65XX_INS_TSX = 87 , MOS65XX_INS_TXA = 88 , MOS65XX_INS_TXS = 89 , MOS65XX_INS_TXY = 90 , MOS65XX_INS_TYA = 91 , MOS65XX_INS_TYX = 92 , MOS65XX_INS_WAI = 93 , MOS65XX_INS_WDM = 94 , MOS65XX_INS_XBA = 95 , MOS65XX_INS_XCE = 96 , MOS65XX_INS_ENDING = 97 , } # [repr (u32)] # [doc = " Group of MOS65XX instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_group_type { # [doc = "< CS_GRP_INVALID"] MOS65XX_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MOS65XX_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MOS65XX_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MOS65XX_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MOS65XX_GRP_BRANCH_RELATIVE = 6 , MOS65XX_GRP_ENDING = 7 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MOS65XX_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MOS65XX_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MOS65XX_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MOS65XX_OP_MEM = 3 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx_op { # [doc = "< operand type"] pub type_ : mos65xx_op_type , pub __bindgen_anon_1 : cs_mos65xx_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mos65xx_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : mos65xx_reg , # [doc = "< immediate value for IMM operand"] pub imm : u16 , # [doc = "< address for MEM operand"] pub mem : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Alignment of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op"] [:: std :: mem :: size_of :: < cs_mos65xx_op > () - 8usize] ; ["Alignment of cs_mos65xx_op"] [:: std :: mem :: align_of :: < cs_mos65xx_op > () - 4usize] ; ["Offset of field: cs_mos65xx_op::type_"] [:: std :: mem :: offset_of ! (cs_mos65xx_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The MOS65XX address mode and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx { pub am : mos65xx_address_mode , pub modifies_flags : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mos65xx_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx"] [:: std :: mem :: size_of :: < cs_mos65xx > () - 32usize] ; ["Alignment of cs_mos65xx"] [:: std :: mem :: align_of :: < cs_mos65xx > () - 4usize] ; ["Offset of field: cs_mos65xx::am"] [:: std :: mem :: offset_of ! (cs_mos65xx , am) - 0usize] ; ["Offset of field: cs_mos65xx::modifies_flags"] [:: std :: mem :: offset_of ! (cs_mos65xx , modifies_flags) - 4usize] ; ["Offset of field: cs_mos65xx::op_count"] [:: std :: mem :: offset_of ! (cs_mos65xx , op_count) - 5usize] ; ["Offset of field: cs_mos65xx::operands"] [:: std :: mem :: offset_of ! (cs_mos65xx , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . am , self . modifies_flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_op_type { BPF_OP_INVALID = 0 , BPF_OP_REG = 1 , BPF_OP_IMM = 2 , BPF_OP_OFF = 3 , BPF_OP_MEM = 4 , # [doc = "< M[k] in cBPF"] BPF_OP_MMEM = 5 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] BPF_OP_MSH = 6 , # [doc = "< cBPF's extension (not eBPF)"] BPF_OP_EXT = 7 , } # [repr (u32)] # [doc = " BPF registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_reg { BPF_REG_INVALID = 0 , BPF_REG_A = 1 , BPF_REG_X = 2 , BPF_REG_R0 = 3 , BPF_REG_R1 = 4 , BPF_REG_R2 = 5 , BPF_REG_R3 = 6 , BPF_REG_R4 = 7 , BPF_REG_R5 = 8 , BPF_REG_R6 = 9 , BPF_REG_R7 = 10 , BPF_REG_R8 = 11 , BPF_REG_R9 = 12 , BPF_REG_R10 = 13 , BPF_REG_ENDING = 14 , } # [doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct bpf_op_mem { # [doc = "< base register"] pub base : bpf_reg , # [doc = "< offset value"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of bpf_op_mem"] [:: std :: mem :: size_of :: < bpf_op_mem > () - 8usize] ; ["Alignment of bpf_op_mem"] [:: std :: mem :: align_of :: < bpf_op_mem > () - 4usize] ; ["Offset of field: bpf_op_mem::base"] [:: std :: mem :: offset_of ! (bpf_op_mem , base) - 0usize] ; ["Offset of field: bpf_op_mem::disp"] [:: std :: mem :: offset_of ! (bpf_op_mem , disp) - 4usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_ext_type { BPF_EXT_INVALID = 0 , BPF_EXT_LEN = 1 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf_op { pub type_ : bpf_op_type , pub __bindgen_anon_1 : cs_bpf_op__bindgen_ty_1 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_bpf_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : u8 , # [doc = "< immediate value IMM operand"] pub imm : u64 , # [doc = "< offset value, used in jump & call"] pub off : u32 , # [doc = "< base/disp value for MEM operand"] pub mem : bpf_op_mem , # [doc = "< M[k] in cBPF"] pub mmem : u32 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] pub msh : u32 , # [doc = "< cBPF's extension (not eBPF)"] pub ext : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::off"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , off) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mmem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mmem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::msh"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , msh) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , ext) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op"] [:: std :: mem :: size_of :: < cs_bpf_op > () - 24usize] ; ["Alignment of cs_bpf_op"] [:: std :: mem :: align_of :: < cs_bpf_op > () - 8usize] ; ["Offset of field: cs_bpf_op::type_"] [:: std :: mem :: offset_of ! (cs_bpf_op , type_) - 0usize] ; ["Offset of field: cs_bpf_op::access"] [:: std :: mem :: offset_of ! (cs_bpf_op , access) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf { pub op_count : u8 , pub operands : [cs_bpf_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf"] [:: std :: mem :: size_of :: < cs_bpf > () - 104usize] ; ["Alignment of cs_bpf"] [:: std :: mem :: align_of :: < cs_bpf > () - 8usize] ; ["Offset of field: cs_bpf::op_count"] [:: std :: mem :: offset_of ! (cs_bpf , op_count) - 0usize] ; ["Offset of field: cs_bpf::operands"] [:: std :: mem :: offset_of ! (cs_bpf , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } impl bpf_insn { pub const BPF_INS_LD : bpf_insn = bpf_insn :: BPF_INS_LDW ; } impl bpf_insn { pub const BPF_INS_LDX : bpf_insn = bpf_insn :: BPF_INS_LDXW ; } impl bpf_insn { pub const BPF_INS_ST : bpf_insn = bpf_insn :: BPF_INS_STW ; } impl bpf_insn { pub const BPF_INS_STX : bpf_insn = bpf_insn :: BPF_INS_STXW ; } # [repr (u32)] # [doc = " BPF instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn { BPF_INS_INVALID = 0 , BPF_INS_ADD = 1 , BPF_INS_SUB = 2 , BPF_INS_MUL = 3 , BPF_INS_DIV = 4 , BPF_INS_OR = 5 , BPF_INS_AND = 6 , BPF_INS_LSH = 7 , BPF_INS_RSH = 8 , BPF_INS_NEG = 9 , BPF_INS_MOD = 10 , BPF_INS_XOR = 11 , # [doc = "< eBPF only"] BPF_INS_MOV = 12 , # [doc = "< eBPF only"] BPF_INS_ARSH = 13 , BPF_INS_ADD64 = 14 , BPF_INS_SUB64 = 15 , BPF_INS_MUL64 = 16 , BPF_INS_DIV64 = 17 , BPF_INS_OR64 = 18 , BPF_INS_AND64 = 19 , BPF_INS_LSH64 = 20 , BPF_INS_RSH64 = 21 , BPF_INS_NEG64 = 22 , BPF_INS_MOD64 = 23 , BPF_INS_XOR64 = 24 , BPF_INS_MOV64 = 25 , BPF_INS_ARSH64 = 26 , BPF_INS_LE16 = 27 , BPF_INS_LE32 = 28 , BPF_INS_LE64 = 29 , BPF_INS_BE16 = 30 , BPF_INS_BE32 = 31 , BPF_INS_BE64 = 32 , # [doc = "< eBPF only"] BPF_INS_LDW = 33 , BPF_INS_LDH = 34 , BPF_INS_LDB = 35 , # [doc = "< eBPF only: load 64-bit imm"] BPF_INS_LDDW = 36 , # [doc = "< eBPF only"] BPF_INS_LDXW = 37 , # [doc = "< eBPF only"] BPF_INS_LDXH = 38 , # [doc = "< eBPF only"] BPF_INS_LDXB = 39 , # [doc = "< eBPF only"] BPF_INS_LDXDW = 40 , # [doc = "< eBPF only"] BPF_INS_STW = 41 , # [doc = "< eBPF only"] BPF_INS_STH = 42 , # [doc = "< eBPF only"] BPF_INS_STB = 43 , # [doc = "< eBPF only"] BPF_INS_STDW = 44 , # [doc = "< eBPF only"] BPF_INS_STXW = 45 , # [doc = "< eBPF only"] BPF_INS_STXH = 46 , # [doc = "< eBPF only"] BPF_INS_STXB = 47 , # [doc = "< eBPF only"] BPF_INS_STXDW = 48 , # [doc = "< eBPF only"] BPF_INS_XADDW = 49 , # [doc = "< eBPF only"] BPF_INS_XADDDW = 50 , BPF_INS_JMP = 51 , BPF_INS_JEQ = 52 , BPF_INS_JGT = 53 , BPF_INS_JGE = 54 , BPF_INS_JSET = 55 , # [doc = "< eBPF only"] BPF_INS_JNE = 56 , # [doc = "< eBPF only"] BPF_INS_JSGT = 57 , # [doc = "< eBPF only"] BPF_INS_JSGE = 58 , # [doc = "< eBPF only"] BPF_INS_CALL = 59 , # [doc = "< eBPF only"] BPF_INS_CALLX = 60 , # [doc = "< eBPF only"] BPF_INS_EXIT = 61 , # [doc = "< eBPF only"] BPF_INS_JLT = 62 , # [doc = "< eBPF only"] BPF_INS_JLE = 63 , # [doc = "< eBPF only"] BPF_INS_JSLT = 64 , # [doc = "< eBPF only"] BPF_INS_JSLE = 65 , BPF_INS_RET = 66 , BPF_INS_TAX = 67 , BPF_INS_TXA = 68 , BPF_INS_ENDING = 69 , } # [repr (u32)] # [doc = " Group of BPF instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn_group { # [doc = "< = CS_GRP_INVALID"] BPF_GRP_INVALID = 0 , BPF_GRP_LOAD = 1 , BPF_GRP_STORE = 2 , BPF_GRP_ALU = 3 , BPF_GRP_JUMP = 4 , # [doc = "< eBPF only"] BPF_GRP_CALL = 5 , BPF_GRP_RETURN = 6 , # [doc = "< cBPF only"] BPF_GRP_MISC = 7 , BPF_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " SH registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_reg { SH_REG_INVALID = 0 , SH_REG_R0 = 1 , SH_REG_R1 = 2 , SH_REG_R2 = 3 , SH_REG_R3 = 4 , SH_REG_R4 = 5 , SH_REG_R5 = 6 , SH_REG_R6 = 7 , SH_REG_R7 = 8 , SH_REG_R8 = 9 , SH_REG_R9 = 10 , SH_REG_R10 = 11 , SH_REG_R11 = 12 , SH_REG_R12 = 13 , SH_REG_R13 = 14 , SH_REG_R14 = 15 , SH_REG_R15 = 16 , SH_REG_R0_BANK = 17 , SH_REG_R1_BANK = 18 , SH_REG_R2_BANK = 19 , SH_REG_R3_BANK = 20 , SH_REG_R4_BANK = 21 , SH_REG_R5_BANK = 22 , SH_REG_R6_BANK = 23 , SH_REG_R7_BANK = 24 , SH_REG_FR0 = 25 , SH_REG_FR1 = 26 , SH_REG_FR2 = 27 , SH_REG_FR3 = 28 , SH_REG_FR4 = 29 , SH_REG_FR5 = 30 , SH_REG_FR6 = 31 , SH_REG_FR7 = 32 , SH_REG_FR8 = 33 , SH_REG_FR9 = 34 , SH_REG_FR10 = 35 , SH_REG_FR11 = 36 , SH_REG_FR12 = 37 , SH_REG_FR13 = 38 , SH_REG_FR14 = 39 , SH_REG_FR15 = 40 , SH_REG_DR0 = 41 , SH_REG_DR2 = 42 , SH_REG_DR4 = 43 , SH_REG_DR6 = 44 , SH_REG_DR8 = 45 , SH_REG_DR10 = 46 , SH_REG_DR12 = 47 , SH_REG_DR14 = 48 , SH_REG_XD0 = 49 , SH_REG_XD2 = 50 , SH_REG_XD4 = 51 , SH_REG_XD6 = 52 , SH_REG_XD8 = 53 , SH_REG_XD10 = 54 , SH_REG_XD12 = 55 , SH_REG_XD14 = 56 , SH_REG_XF0 = 57 , SH_REG_XF1 = 58 , SH_REG_XF2 = 59 , SH_REG_XF3 = 60 , SH_REG_XF4 = 61 , SH_REG_XF5 = 62 , SH_REG_XF6 = 63 , SH_REG_XF7 = 64 , SH_REG_XF8 = 65 , SH_REG_XF9 = 66 , SH_REG_XF10 = 67 , SH_REG_XF11 = 68 , SH_REG_XF12 = 69 , SH_REG_XF13 = 70 , SH_REG_XF14 = 71 , SH_REG_XF15 = 72 , SH_REG_FV0 = 73 , SH_REG_FV4 = 74 , SH_REG_FV8 = 75 , SH_REG_FV12 = 76 , SH_REG_XMATRX = 77 , SH_REG_PC = 78 , SH_REG_PR = 79 , SH_REG_MACH = 80 , SH_REG_MACL = 81 , SH_REG_SR = 82 , SH_REG_GBR = 83 , SH_REG_SSR = 84 , SH_REG_SPC = 85 , SH_REG_SGR = 86 , SH_REG_DBR = 87 , SH_REG_VBR = 88 , SH_REG_TBR = 89 , SH_REG_RS = 90 , SH_REG_RE = 91 , SH_REG_MOD = 92 , SH_REG_FPUL = 93 , SH_REG_FPSCR = 94 , SH_REG_DSP_X0 = 95 , SH_REG_DSP_X1 = 96 , SH_REG_DSP_Y0 = 97 , SH_REG_DSP_Y1 = 98 , SH_REG_DSP_A0 = 99 , SH_REG_DSP_A1 = 100 , SH_REG_DSP_A0G = 101 , SH_REG_DSP_A1G = 102 , SH_REG_DSP_M0 = 103 , SH_REG_DSP_M1 = 104 , SH_REG_DSP_DSR = 105 , SH_REG_DSP_RSV0 = 106 , SH_REG_DSP_RSV1 = 107 , SH_REG_DSP_RSV2 = 108 , SH_REG_DSP_RSV3 = 109 , SH_REG_DSP_RSV4 = 110 , SH_REG_DSP_RSV5 = 111 , SH_REG_DSP_RSV6 = 112 , SH_REG_DSP_RSV7 = 113 , SH_REG_DSP_RSV8 = 114 , SH_REG_DSP_RSV9 = 115 , SH_REG_DSP_RSVA = 116 , SH_REG_DSP_RSVB = 117 , SH_REG_DSP_RSVC = 118 , SH_REG_DSP_RSVD = 119 , SH_REG_DSP_RSVE = 120 , SH_REG_DSP_RSVF = 121 , SH_REG_ENDING = 122 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SH_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SH_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SH_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SH_OP_MEM = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_mem_type { SH_OP_MEM_INVALID = 0 , # [doc = " <= Invalid"] SH_OP_MEM_REG_IND = 1 , # [doc = " <= Register indirect"] SH_OP_MEM_REG_POST = 2 , # [doc = " <= Register post increment"] SH_OP_MEM_REG_PRE = 3 , # [doc = " <= Register pre decrement"] SH_OP_MEM_REG_DISP = 4 , # [doc = " <= displacement"] SH_OP_MEM_REG_R0 = 5 , # [doc = " <= R0 indexed"] SH_OP_MEM_GBR_DISP = 6 , # [doc = " <= GBR based displacement"] SH_OP_MEM_GBR_R0 = 7 , # [doc = " <= GBR based R0 indexed"] SH_OP_MEM_PCR = 8 , # [doc = " <= PC relative"] SH_OP_MEM_TBR_DISP = 9 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_mem { pub address : sh_op_mem_type , # [doc = " <= memory address"] pub reg : sh_reg , # [doc = " <= base register"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_mem"] [:: std :: mem :: size_of :: < sh_op_mem > () - 12usize] ; ["Alignment of sh_op_mem"] [:: std :: mem :: align_of :: < sh_op_mem > () - 4usize] ; ["Offset of field: sh_op_mem::address"] [:: std :: mem :: offset_of ! (sh_op_mem , address) - 0usize] ; ["Offset of field: sh_op_mem::reg"] [:: std :: mem :: offset_of ! (sh_op_mem , reg) - 4usize] ; ["Offset of field: sh_op_mem::disp"] [:: std :: mem :: offset_of ! (sh_op_mem , disp) - 8usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn_type { SH_INS_DSP_INVALID = 0 , SH_INS_DSP_DOUBLE = 1 , SH_INS_DSP_SINGLE = 2 , SH_INS_DSP_PARALLEL = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn { SH_INS_DSP_NOP = 1 , SH_INS_DSP_MOV = 2 , SH_INS_DSP_PSHL = 3 , SH_INS_DSP_PSHA = 4 , SH_INS_DSP_PMULS = 5 , SH_INS_DSP_PCLR_PMULS = 6 , SH_INS_DSP_PSUB_PMULS = 7 , SH_INS_DSP_PADD_PMULS = 8 , SH_INS_DSP_PSUBC = 9 , SH_INS_DSP_PADDC = 10 , SH_INS_DSP_PCMP = 11 , SH_INS_DSP_PABS = 12 , SH_INS_DSP_PRND = 13 , SH_INS_DSP_PSUB = 14 , SH_INS_DSP_PSUBr = 15 , SH_INS_DSP_PADD = 16 , SH_INS_DSP_PAND = 17 , SH_INS_DSP_PXOR = 18 , SH_INS_DSP_POR = 19 , SH_INS_DSP_PDEC = 20 , SH_INS_DSP_PINC = 21 , SH_INS_DSP_PCLR = 22 , SH_INS_DSP_PDMSB = 23 , SH_INS_DSP_PNEG = 24 , SH_INS_DSP_PCOPY = 25 , SH_INS_DSP_PSTS = 26 , SH_INS_DSP_PLDS = 27 , SH_INS_DSP_PSWAP = 28 , SH_INS_DSP_PWAD = 29 , SH_INS_DSP_PWSB = 30 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_operand { SH_OP_DSP_INVALID = 0 , SH_OP_DSP_REG_PRE = 1 , SH_OP_DSP_REG_IND = 2 , SH_OP_DSP_REG_POST = 3 , SH_OP_DSP_REG_INDEX = 4 , SH_OP_DSP_REG = 5 , SH_OP_DSP_IMM = 6 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_cc { SH_DSP_CC_INVALID = 0 , SH_DSP_CC_NONE = 1 , SH_DSP_CC_DCT = 2 , SH_DSP_CC_DCF = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_dsp { pub insn : sh_dsp_insn , pub operand : [sh_dsp_operand ; 2usize] , pub r : [sh_reg ; 6usize] , pub cc : sh_dsp_cc , pub imm : u8 , pub size : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_dsp"] [:: std :: mem :: size_of :: < sh_op_dsp > () - 48usize] ; ["Alignment of sh_op_dsp"] [:: std :: mem :: align_of :: < sh_op_dsp > () - 4usize] ; ["Offset of field: sh_op_dsp::insn"] [:: std :: mem :: offset_of ! (sh_op_dsp , insn) - 0usize] ; ["Offset of field: sh_op_dsp::operand"] [:: std :: mem :: offset_of ! (sh_op_dsp , operand) - 4usize] ; ["Offset of field: sh_op_dsp::r"] [:: std :: mem :: offset_of ! (sh_op_dsp , r) - 12usize] ; ["Offset of field: sh_op_dsp::cc"] [:: std :: mem :: offset_of ! (sh_op_dsp , cc) - 36usize] ; ["Offset of field: sh_op_dsp::imm"] [:: std :: mem :: offset_of ! (sh_op_dsp , imm) - 40usize] ; ["Offset of field: sh_op_dsp::size"] [:: std :: mem :: offset_of ! (sh_op_dsp , size) - 44usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh_op { pub type_ : sh_op_type , pub __bindgen_anon_1 : cs_sh_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sh_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< register value for REG operand"] pub reg : sh_reg , # [doc = "< data when operand is targeting memory"] pub mem : sh_op_mem , # [doc = "< dsp instruction"] pub dsp : sh_op_dsp , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sh_op__bindgen_ty_1 > () - 48usize] ; ["Alignment of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sh_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::dsp"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , dsp) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op"] [:: std :: mem :: size_of :: < cs_sh_op > () - 56usize] ; ["Alignment of cs_sh_op"] [:: std :: mem :: align_of :: < cs_sh_op > () - 8usize] ; ["Offset of field: cs_sh_op::type_"] [:: std :: mem :: offset_of ! (cs_sh_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (u32)] # [doc = " SH instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn { SH_INS_INVALID = 0 , SH_INS_ADD_r = 1 , SH_INS_ADD = 2 , SH_INS_ADDC = 3 , SH_INS_ADDV = 4 , SH_INS_AND = 5 , SH_INS_BAND = 6 , SH_INS_BANDNOT = 7 , SH_INS_BCLR = 8 , SH_INS_BF = 9 , SH_INS_BF_S = 10 , SH_INS_BLD = 11 , SH_INS_BLDNOT = 12 , SH_INS_BOR = 13 , SH_INS_BORNOT = 14 , SH_INS_BRA = 15 , SH_INS_BRAF = 16 , SH_INS_BSET = 17 , SH_INS_BSR = 18 , SH_INS_BSRF = 19 , SH_INS_BST = 20 , SH_INS_BT = 21 , SH_INS_BT_S = 22 , SH_INS_BXOR = 23 , SH_INS_CLIPS = 24 , SH_INS_CLIPU = 25 , SH_INS_CLRDMXY = 26 , SH_INS_CLRMAC = 27 , SH_INS_CLRS = 28 , SH_INS_CLRT = 29 , SH_INS_CMP_EQ = 30 , SH_INS_CMP_GE = 31 , SH_INS_CMP_GT = 32 , SH_INS_CMP_HI = 33 , SH_INS_CMP_HS = 34 , SH_INS_CMP_PL = 35 , SH_INS_CMP_PZ = 36 , SH_INS_CMP_STR = 37 , SH_INS_DIV0S = 38 , SH_INS_DIV0U = 39 , SH_INS_DIV1 = 40 , SH_INS_DIVS = 41 , SH_INS_DIVU = 42 , SH_INS_DMULS_L = 43 , SH_INS_DMULU_L = 44 , SH_INS_DT = 45 , SH_INS_EXTS_B = 46 , SH_INS_EXTS_W = 47 , SH_INS_EXTU_B = 48 , SH_INS_EXTU_W = 49 , SH_INS_FABS = 50 , SH_INS_FADD = 51 , SH_INS_FCMP_EQ = 52 , SH_INS_FCMP_GT = 53 , SH_INS_FCNVDS = 54 , SH_INS_FCNVSD = 55 , SH_INS_FDIV = 56 , SH_INS_FIPR = 57 , SH_INS_FLDI0 = 58 , SH_INS_FLDI1 = 59 , SH_INS_FLDS = 60 , SH_INS_FLOAT = 61 , SH_INS_FMAC = 62 , SH_INS_FMOV = 63 , SH_INS_FMUL = 64 , SH_INS_FNEG = 65 , SH_INS_FPCHG = 66 , SH_INS_FRCHG = 67 , SH_INS_FSCA = 68 , SH_INS_FSCHG = 69 , SH_INS_FSQRT = 70 , SH_INS_FSRRA = 71 , SH_INS_FSTS = 72 , SH_INS_FSUB = 73 , SH_INS_FTRC = 74 , SH_INS_FTRV = 75 , SH_INS_ICBI = 76 , SH_INS_JMP = 77 , SH_INS_JSR = 78 , SH_INS_JSR_N = 79 , SH_INS_LDBANK = 80 , SH_INS_LDC = 81 , SH_INS_LDRC = 82 , SH_INS_LDRE = 83 , SH_INS_LDRS = 84 , SH_INS_LDS = 85 , SH_INS_LDTLB = 86 , SH_INS_MAC_L = 87 , SH_INS_MAC_W = 88 , SH_INS_MOV = 89 , SH_INS_MOVA = 90 , SH_INS_MOVCA = 91 , SH_INS_MOVCO = 92 , SH_INS_MOVI20 = 93 , SH_INS_MOVI20S = 94 , SH_INS_MOVLI = 95 , SH_INS_MOVML = 96 , SH_INS_MOVMU = 97 , SH_INS_MOVRT = 98 , SH_INS_MOVT = 99 , SH_INS_MOVU = 100 , SH_INS_MOVUA = 101 , SH_INS_MUL_L = 102 , SH_INS_MULR = 103 , SH_INS_MULS_W = 104 , SH_INS_MULU_W = 105 , SH_INS_NEG = 106 , SH_INS_NEGC = 107 , SH_INS_NOP = 108 , SH_INS_NOT = 109 , SH_INS_NOTT = 110 , SH_INS_OCBI = 111 , SH_INS_OCBP = 112 , SH_INS_OCBWB = 113 , SH_INS_OR = 114 , SH_INS_PREF = 115 , SH_INS_PREFI = 116 , SH_INS_RESBANK = 117 , SH_INS_ROTCL = 118 , SH_INS_ROTCR = 119 , SH_INS_ROTL = 120 , SH_INS_ROTR = 121 , SH_INS_RTE = 122 , SH_INS_RTS = 123 , SH_INS_RTS_N = 124 , SH_INS_RTV_N = 125 , SH_INS_SETDMX = 126 , SH_INS_SETDMY = 127 , SH_INS_SETRC = 128 , SH_INS_SETS = 129 , SH_INS_SETT = 130 , SH_INS_SHAD = 131 , SH_INS_SHAL = 132 , SH_INS_SHAR = 133 , SH_INS_SHLD = 134 , SH_INS_SHLL = 135 , SH_INS_SHLL16 = 136 , SH_INS_SHLL2 = 137 , SH_INS_SHLL8 = 138 , SH_INS_SHLR = 139 , SH_INS_SHLR16 = 140 , SH_INS_SHLR2 = 141 , SH_INS_SHLR8 = 142 , SH_INS_SLEEP = 143 , SH_INS_STBANK = 144 , SH_INS_STC = 145 , SH_INS_STS = 146 , SH_INS_SUB = 147 , SH_INS_SUBC = 148 , SH_INS_SUBV = 149 , SH_INS_SWAP_B = 150 , SH_INS_SWAP_W = 151 , SH_INS_SYNCO = 152 , SH_INS_TAS = 153 , SH_INS_TRAPA = 154 , SH_INS_TST = 155 , SH_INS_XOR = 156 , SH_INS_XTRCT = 157 , SH_INS_DSP = 158 , SH_INS_ENDING = 159 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh { pub insn : sh_insn , pub size : u8 , pub op_count : u8 , pub operands : [cs_sh_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh"] [:: std :: mem :: size_of :: < cs_sh > () - 176usize] ; ["Alignment of cs_sh"] [:: std :: mem :: align_of :: < cs_sh > () - 8usize] ; ["Offset of field: cs_sh::insn"] [:: std :: mem :: offset_of ! (cs_sh , insn) - 0usize] ; ["Offset of field: cs_sh::size"] [:: std :: mem :: offset_of ! (cs_sh , size) - 4usize] ; ["Offset of field: cs_sh::op_count"] [:: std :: mem :: offset_of ! (cs_sh , op_count) - 5usize] ; ["Offset of field: cs_sh::operands"] [:: std :: mem :: offset_of ! (cs_sh , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sh { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh {{ insn: {:?}, size: {:?}, op_count: {:?}, operands: {:?} }}" , self . insn , self . size , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Group of SH instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn_group { # [doc = "< CS_GRUP_INVALID"] SH_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SH_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] SH_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] SH_GRP_INT = 3 , # [doc = "< = CS_GRP_RET"] SH_GRP_RET = 4 , # [doc = "< = CS_GRP_IRET"] SH_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] SH_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] SH_GRP_BRANCH_RELATIVE = 7 , SH_GRP_SH1 = 8 , SH_GRP_SH2 = 9 , SH_GRP_SH2E = 10 , SH_GRP_SH2DSP = 11 , SH_GRP_SH2A = 12 , SH_GRP_SH2AFPU = 13 , SH_GRP_SH3 = 14 , SH_GRP_SH3DSP = 15 , SH_GRP_SH4 = 16 , SH_GRP_SH4A = 17 , SH_GRP_ENDING = 18 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_op_type { # [doc = "< CS_OP_INVALID (Uninitialized)."] TRICORE_OP_INVALID = 0 , # [doc = "< CS_OP_REG (Register operand)."] TRICORE_OP_REG = 1 , # [doc = "< CS_OP_IMM (Immediate operand)."] TRICORE_OP_IMM = 2 , # [doc = "< CS_OP_MEM (Memory operand)."] TRICORE_OP_MEM = 3 , } # [doc = " Instruction's operand referring to memory\n This is associated with TRICORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tricore_op_mem { # [doc = "< base register"] pub base : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tricore_op_mem"] [:: std :: mem :: size_of :: < tricore_op_mem > () - 8usize] ; ["Alignment of tricore_op_mem"] [:: std :: mem :: align_of :: < tricore_op_mem > () - 4usize] ; ["Offset of field: tricore_op_mem::base"] [:: std :: mem :: offset_of ! (tricore_op_mem , base) - 0usize] ; ["Offset of field: tricore_op_mem::disp"] [:: std :: mem :: offset_of ! (tricore_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore_op { # [doc = "< operand type"] pub type_ : tricore_op_type , pub __bindgen_anon_1 : cs_tricore_op__bindgen_ty_1 , # [doc = "< How is this operand accessed? (READ, WRITE or READ|WRITE)"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tricore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tricore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tricore_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tricore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op"] [:: std :: mem :: size_of :: < cs_tricore_op > () - 16usize] ; ["Alignment of cs_tricore_op"] [:: std :: mem :: align_of :: < cs_tricore_op > () - 4usize] ; ["Offset of field: cs_tricore_op::type_"] [:: std :: mem :: offset_of ! (cs_tricore_op , type_) - 0usize] ; ["Offset of field: cs_tricore_op::access"] [:: std :: mem :: offset_of ! (cs_tricore_op , access) - 12usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore { # [doc = "< number of operands of this instruction."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tricore_op ; 8usize] , # [doc = "< whether the flags register is updated."] pub update_flags : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore"] [:: std :: mem :: size_of :: < cs_tricore > () - 136usize] ; ["Alignment of cs_tricore"] [:: std :: mem :: align_of :: < cs_tricore > () - 4usize] ; ["Offset of field: cs_tricore::op_count"] [:: std :: mem :: offset_of ! (cs_tricore , op_count) - 0usize] ; ["Offset of field: cs_tricore::operands"] [:: std :: mem :: offset_of ! (cs_tricore , operands) - 4usize] ; ["Offset of field: cs_tricore::update_flags"] [:: std :: mem :: offset_of ! (cs_tricore , update_flags) - 132usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore {{ op_count: {:?}, operands: {:?}, update_flags: {:?} }}" , self . op_count , self . operands , self . update_flags) } } # [repr (u32)] # [doc = " TriCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_reg { TRICORE_REG_INVALID = 0 , TRICORE_REG_FCX = 1 , TRICORE_REG_PC = 2 , TRICORE_REG_PCXI = 3 , TRICORE_REG_PSW = 4 , TRICORE_REG_A0 = 5 , TRICORE_REG_A1 = 6 , TRICORE_REG_A2 = 7 , TRICORE_REG_A3 = 8 , TRICORE_REG_A4 = 9 , TRICORE_REG_A5 = 10 , TRICORE_REG_A6 = 11 , TRICORE_REG_A7 = 12 , TRICORE_REG_A8 = 13 , TRICORE_REG_A9 = 14 , TRICORE_REG_A10 = 15 , TRICORE_REG_A11 = 16 , TRICORE_REG_A12 = 17 , TRICORE_REG_A13 = 18 , TRICORE_REG_A14 = 19 , TRICORE_REG_A15 = 20 , TRICORE_REG_D0 = 21 , TRICORE_REG_D1 = 22 , TRICORE_REG_D2 = 23 , TRICORE_REG_D3 = 24 , TRICORE_REG_D4 = 25 , TRICORE_REG_D5 = 26 , TRICORE_REG_D6 = 27 , TRICORE_REG_D7 = 28 , TRICORE_REG_D8 = 29 , TRICORE_REG_D9 = 30 , TRICORE_REG_D10 = 31 , TRICORE_REG_D11 = 32 , TRICORE_REG_D12 = 33 , TRICORE_REG_D13 = 34 , TRICORE_REG_D14 = 35 , TRICORE_REG_D15 = 36 , TRICORE_REG_E0 = 37 , TRICORE_REG_E2 = 38 , TRICORE_REG_E4 = 39 , TRICORE_REG_E6 = 40 , TRICORE_REG_E8 = 41 , TRICORE_REG_E10 = 42 , TRICORE_REG_E12 = 43 , TRICORE_REG_E14 = 44 , TRICORE_REG_P0 = 45 , TRICORE_REG_P2 = 46 , TRICORE_REG_P4 = 47 , TRICORE_REG_P6 = 48 , TRICORE_REG_P8 = 49 , TRICORE_REG_P10 = 50 , TRICORE_REG_P12 = 51 , TRICORE_REG_P14 = 52 , TRICORE_REG_A0_A1 = 53 , TRICORE_REG_A2_A3 = 54 , TRICORE_REG_A4_A5 = 55 , TRICORE_REG_A6_A7 = 56 , TRICORE_REG_A8_A9 = 57 , TRICORE_REG_A10_A11 = 58 , TRICORE_REG_A12_A13 = 59 , TRICORE_REG_A14_A15 = 60 , TRICORE_REG_ENDING = 61 , } # [repr (u32)] # [doc = " TriCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn { TRICORE_INS_INVALID = 0 , TRICORE_INS_XOR_T = 1 , TRICORE_INS_ABSDIFS_B = 2 , TRICORE_INS_ABSDIFS_H = 3 , TRICORE_INS_ABSDIFS = 4 , TRICORE_INS_ABSDIF_B = 5 , TRICORE_INS_ABSDIF_H = 6 , TRICORE_INS_ABSDIF = 7 , TRICORE_INS_ABSS_B = 8 , TRICORE_INS_ABSS_H = 9 , TRICORE_INS_ABSS = 10 , TRICORE_INS_ABS_B = 11 , TRICORE_INS_ABS_H = 12 , TRICORE_INS_ABS = 13 , TRICORE_INS_ADDC = 14 , TRICORE_INS_ADDIH_A = 15 , TRICORE_INS_ADDIH = 16 , TRICORE_INS_ADDI = 17 , TRICORE_INS_ADDSC_AT = 18 , TRICORE_INS_ADDSC_A = 19 , TRICORE_INS_ADDS_BU = 20 , TRICORE_INS_ADDS_B = 21 , TRICORE_INS_ADDS_H = 22 , TRICORE_INS_ADDS_HU = 23 , TRICORE_INS_ADDS_U = 24 , TRICORE_INS_ADDS = 25 , TRICORE_INS_ADDX = 26 , TRICORE_INS_ADD_A = 27 , TRICORE_INS_ADD_B = 28 , TRICORE_INS_ADD_F = 29 , TRICORE_INS_ADD_H = 30 , TRICORE_INS_ADD = 31 , TRICORE_INS_ANDN_T = 32 , TRICORE_INS_ANDN = 33 , TRICORE_INS_AND_ANDN_T = 34 , TRICORE_INS_AND_AND_T = 35 , TRICORE_INS_AND_EQ = 36 , TRICORE_INS_AND_GE_U = 37 , TRICORE_INS_AND_GE = 38 , TRICORE_INS_AND_LT_U = 39 , TRICORE_INS_AND_LT = 40 , TRICORE_INS_AND_NE = 41 , TRICORE_INS_AND_NOR_T = 42 , TRICORE_INS_AND_OR_T = 43 , TRICORE_INS_AND_T = 44 , TRICORE_INS_AND = 45 , TRICORE_INS_BISR = 46 , TRICORE_INS_BMERGE = 47 , TRICORE_INS_BSPLIT = 48 , TRICORE_INS_CACHEA_I = 49 , TRICORE_INS_CACHEA_WI = 50 , TRICORE_INS_CACHEA_W = 51 , TRICORE_INS_CACHEI_I = 52 , TRICORE_INS_CACHEI_WI = 53 , TRICORE_INS_CACHEI_W = 54 , TRICORE_INS_CADDN_A = 55 , TRICORE_INS_CADDN = 56 , TRICORE_INS_CADD_A = 57 , TRICORE_INS_CADD = 58 , TRICORE_INS_CALLA = 59 , TRICORE_INS_CALLI = 60 , TRICORE_INS_CALL = 61 , TRICORE_INS_CLO_B = 62 , TRICORE_INS_CLO_H = 63 , TRICORE_INS_CLO = 64 , TRICORE_INS_CLS_B = 65 , TRICORE_INS_CLS_H = 66 , TRICORE_INS_CLS = 67 , TRICORE_INS_CLZ_B = 68 , TRICORE_INS_CLZ_H = 69 , TRICORE_INS_CLZ = 70 , TRICORE_INS_CMOVN = 71 , TRICORE_INS_CMOV = 72 , TRICORE_INS_CMPSWAP_W = 73 , TRICORE_INS_CMP_F = 74 , TRICORE_INS_CRC32B_W = 75 , TRICORE_INS_CRC32L_W = 76 , TRICORE_INS_CRC32_B = 77 , TRICORE_INS_CRCN = 78 , TRICORE_INS_CSUBN_A = 79 , TRICORE_INS_CSUBN = 80 , TRICORE_INS_CSUB_A = 81 , TRICORE_INS_CSUB = 82 , TRICORE_INS_DEBUG = 83 , TRICORE_INS_DEXTR = 84 , TRICORE_INS_DIFSC_A = 85 , TRICORE_INS_DISABLE = 86 , TRICORE_INS_DIV_F = 87 , TRICORE_INS_DIV_U = 88 , TRICORE_INS_DIV = 89 , TRICORE_INS_DSYNC = 90 , TRICORE_INS_DVADJ = 91 , TRICORE_INS_DVINIT_BU = 92 , TRICORE_INS_DVINIT_B = 93 , TRICORE_INS_DVINIT_HU = 94 , TRICORE_INS_DVINIT_H = 95 , TRICORE_INS_DVINIT_U = 96 , TRICORE_INS_DVINIT = 97 , TRICORE_INS_DVSTEP_U = 98 , TRICORE_INS_DVSTEP = 99 , TRICORE_INS_ENABLE = 100 , TRICORE_INS_EQANY_B = 101 , TRICORE_INS_EQANY_H = 102 , TRICORE_INS_EQZ_A = 103 , TRICORE_INS_EQ_A = 104 , TRICORE_INS_EQ_B = 105 , TRICORE_INS_EQ_H = 106 , TRICORE_INS_EQ_W = 107 , TRICORE_INS_EQ = 108 , TRICORE_INS_EXTR_U = 109 , TRICORE_INS_EXTR = 110 , TRICORE_INS_FCALLA = 111 , TRICORE_INS_FCALLI = 112 , TRICORE_INS_FCALL = 113 , TRICORE_INS_FRET = 114 , TRICORE_INS_FTOHP = 115 , TRICORE_INS_FTOIZ = 116 , TRICORE_INS_FTOI = 117 , TRICORE_INS_FTOQ31Z = 118 , TRICORE_INS_FTOQ31 = 119 , TRICORE_INS_FTOUZ = 120 , TRICORE_INS_FTOU = 121 , TRICORE_INS_GE_A = 122 , TRICORE_INS_GE_U = 123 , TRICORE_INS_GE = 124 , TRICORE_INS_HPTOF = 125 , TRICORE_INS_IMASK = 126 , TRICORE_INS_INSERT = 127 , TRICORE_INS_INSN_T = 128 , TRICORE_INS_INS_T = 129 , TRICORE_INS_ISYNC = 130 , TRICORE_INS_ITOF = 131 , TRICORE_INS_IXMAX_U = 132 , TRICORE_INS_IXMAX = 133 , TRICORE_INS_IXMIN_U = 134 , TRICORE_INS_IXMIN = 135 , TRICORE_INS_JA = 136 , TRICORE_INS_JEQ_A = 137 , TRICORE_INS_JEQ = 138 , TRICORE_INS_JGEZ = 139 , TRICORE_INS_JGE_U = 140 , TRICORE_INS_JGE = 141 , TRICORE_INS_JGTZ = 142 , TRICORE_INS_JI = 143 , TRICORE_INS_JLA = 144 , TRICORE_INS_JLEZ = 145 , TRICORE_INS_JLI = 146 , TRICORE_INS_JLTZ = 147 , TRICORE_INS_JLT_U = 148 , TRICORE_INS_JLT = 149 , TRICORE_INS_JL = 150 , TRICORE_INS_JNED = 151 , TRICORE_INS_JNEI = 152 , TRICORE_INS_JNE_A = 153 , TRICORE_INS_JNE = 154 , TRICORE_INS_JNZ_A = 155 , TRICORE_INS_JNZ_T = 156 , TRICORE_INS_JNZ = 157 , TRICORE_INS_JZ_A = 158 , TRICORE_INS_JZ_T = 159 , TRICORE_INS_JZ = 160 , TRICORE_INS_J = 161 , TRICORE_INS_LDLCX = 162 , TRICORE_INS_LDMST = 163 , TRICORE_INS_LDUCX = 164 , TRICORE_INS_LD_A = 165 , TRICORE_INS_LD_BU = 166 , TRICORE_INS_LD_B = 167 , TRICORE_INS_LD_DA = 168 , TRICORE_INS_LD_D = 169 , TRICORE_INS_LD_HU = 170 , TRICORE_INS_LD_H = 171 , TRICORE_INS_LD_Q = 172 , TRICORE_INS_LD_W = 173 , TRICORE_INS_LEA = 174 , TRICORE_INS_LHA = 175 , TRICORE_INS_LOOPU = 176 , TRICORE_INS_LOOP = 177 , TRICORE_INS_LT_A = 178 , TRICORE_INS_LT_B = 179 , TRICORE_INS_LT_BU = 180 , TRICORE_INS_LT_H = 181 , TRICORE_INS_LT_HU = 182 , TRICORE_INS_LT_U = 183 , TRICORE_INS_LT_W = 184 , TRICORE_INS_LT_WU = 185 , TRICORE_INS_LT = 186 , TRICORE_INS_MADDMS_H = 187 , TRICORE_INS_MADDMS_U = 188 , TRICORE_INS_MADDMS = 189 , TRICORE_INS_MADDM_H = 190 , TRICORE_INS_MADDM_Q = 191 , TRICORE_INS_MADDM_U = 192 , TRICORE_INS_MADDM = 193 , TRICORE_INS_MADDRS_H = 194 , TRICORE_INS_MADDRS_Q = 195 , TRICORE_INS_MADDR_H = 196 , TRICORE_INS_MADDR_Q = 197 , TRICORE_INS_MADDSUMS_H = 198 , TRICORE_INS_MADDSUM_H = 199 , TRICORE_INS_MADDSURS_H = 200 , TRICORE_INS_MADDSUR_H = 201 , TRICORE_INS_MADDSUS_H = 202 , TRICORE_INS_MADDSU_H = 203 , TRICORE_INS_MADDS_H = 204 , TRICORE_INS_MADDS_Q = 205 , TRICORE_INS_MADDS_U = 206 , TRICORE_INS_MADDS = 207 , TRICORE_INS_MADD_F = 208 , TRICORE_INS_MADD_H = 209 , TRICORE_INS_MADD_Q = 210 , TRICORE_INS_MADD_U = 211 , TRICORE_INS_MADD = 212 , TRICORE_INS_MAX_B = 213 , TRICORE_INS_MAX_BU = 214 , TRICORE_INS_MAX_H = 215 , TRICORE_INS_MAX_HU = 216 , TRICORE_INS_MAX_U = 217 , TRICORE_INS_MAX = 218 , TRICORE_INS_MFCR = 219 , TRICORE_INS_MIN_B = 220 , TRICORE_INS_MIN_BU = 221 , TRICORE_INS_MIN_H = 222 , TRICORE_INS_MIN_HU = 223 , TRICORE_INS_MIN_U = 224 , TRICORE_INS_MIN = 225 , TRICORE_INS_MOVH_A = 226 , TRICORE_INS_MOVH = 227 , TRICORE_INS_MOVZ_A = 228 , TRICORE_INS_MOV_AA = 229 , TRICORE_INS_MOV_A = 230 , TRICORE_INS_MOV_D = 231 , TRICORE_INS_MOV_U = 232 , TRICORE_INS_MOV = 233 , TRICORE_INS_MSUBADMS_H = 234 , TRICORE_INS_MSUBADM_H = 235 , TRICORE_INS_MSUBADRS_H = 236 , TRICORE_INS_MSUBADR_H = 237 , TRICORE_INS_MSUBADS_H = 238 , TRICORE_INS_MSUBAD_H = 239 , TRICORE_INS_MSUBMS_H = 240 , TRICORE_INS_MSUBMS_U = 241 , TRICORE_INS_MSUBMS = 242 , TRICORE_INS_MSUBM_H = 243 , TRICORE_INS_MSUBM_Q = 244 , TRICORE_INS_MSUBM_U = 245 , TRICORE_INS_MSUBM = 246 , TRICORE_INS_MSUBRS_H = 247 , TRICORE_INS_MSUBRS_Q = 248 , TRICORE_INS_MSUBR_H = 249 , TRICORE_INS_MSUBR_Q = 250 , TRICORE_INS_MSUBS_H = 251 , TRICORE_INS_MSUBS_Q = 252 , TRICORE_INS_MSUBS_U = 253 , TRICORE_INS_MSUBS = 254 , TRICORE_INS_MSUB_F = 255 , TRICORE_INS_MSUB_H = 256 , TRICORE_INS_MSUB_Q = 257 , TRICORE_INS_MSUB_U = 258 , TRICORE_INS_MSUB = 259 , TRICORE_INS_MTCR = 260 , TRICORE_INS_MULMS_H = 261 , TRICORE_INS_MULM_H = 262 , TRICORE_INS_MULM_U = 263 , TRICORE_INS_MULM = 264 , TRICORE_INS_MULR_H = 265 , TRICORE_INS_MULR_Q = 266 , TRICORE_INS_MULS_U = 267 , TRICORE_INS_MULS = 268 , TRICORE_INS_MUL_F = 269 , TRICORE_INS_MUL_H = 270 , TRICORE_INS_MUL_Q = 271 , TRICORE_INS_MUL_U = 272 , TRICORE_INS_MUL = 273 , TRICORE_INS_NAND_T = 274 , TRICORE_INS_NAND = 275 , TRICORE_INS_NEZ_A = 276 , TRICORE_INS_NE_A = 277 , TRICORE_INS_NE = 278 , TRICORE_INS_NOP = 279 , TRICORE_INS_NOR_T = 280 , TRICORE_INS_NOR = 281 , TRICORE_INS_NOT = 282 , TRICORE_INS_ORN_T = 283 , TRICORE_INS_ORN = 284 , TRICORE_INS_OR_ANDN_T = 285 , TRICORE_INS_OR_AND_T = 286 , TRICORE_INS_OR_EQ = 287 , TRICORE_INS_OR_GE_U = 288 , TRICORE_INS_OR_GE = 289 , TRICORE_INS_OR_LT_U = 290 , TRICORE_INS_OR_LT = 291 , TRICORE_INS_OR_NE = 292 , TRICORE_INS_OR_NOR_T = 293 , TRICORE_INS_OR_OR_T = 294 , TRICORE_INS_OR_T = 295 , TRICORE_INS_OR = 296 , TRICORE_INS_PACK = 297 , TRICORE_INS_PARITY = 298 , TRICORE_INS_POPCNT_W = 299 , TRICORE_INS_Q31TOF = 300 , TRICORE_INS_QSEED_F = 301 , TRICORE_INS_RESTORE = 302 , TRICORE_INS_RET = 303 , TRICORE_INS_RFE = 304 , TRICORE_INS_RFM = 305 , TRICORE_INS_RSLCX = 306 , TRICORE_INS_RSTV = 307 , TRICORE_INS_RSUBS_U = 308 , TRICORE_INS_RSUBS = 309 , TRICORE_INS_RSUB = 310 , TRICORE_INS_SAT_BU = 311 , TRICORE_INS_SAT_B = 312 , TRICORE_INS_SAT_HU = 313 , TRICORE_INS_SAT_H = 314 , TRICORE_INS_SELN_A = 315 , TRICORE_INS_SELN = 316 , TRICORE_INS_SEL_A = 317 , TRICORE_INS_SEL = 318 , TRICORE_INS_SHAS = 319 , TRICORE_INS_SHA_B = 320 , TRICORE_INS_SHA_H = 321 , TRICORE_INS_SHA = 322 , TRICORE_INS_SHUFFLE = 323 , TRICORE_INS_SH_ANDN_T = 324 , TRICORE_INS_SH_AND_T = 325 , TRICORE_INS_SH_B = 326 , TRICORE_INS_SH_EQ = 327 , TRICORE_INS_SH_GE_U = 328 , TRICORE_INS_SH_GE = 329 , TRICORE_INS_SH_H = 330 , TRICORE_INS_SH_LT_U = 331 , TRICORE_INS_SH_LT = 332 , TRICORE_INS_SH_NAND_T = 333 , TRICORE_INS_SH_NE = 334 , TRICORE_INS_SH_NOR_T = 335 , TRICORE_INS_SH_ORN_T = 336 , TRICORE_INS_SH_OR_T = 337 , TRICORE_INS_SH_XNOR_T = 338 , TRICORE_INS_SH_XOR_T = 339 , TRICORE_INS_SH = 340 , TRICORE_INS_STLCX = 341 , TRICORE_INS_STUCX = 342 , TRICORE_INS_ST_A = 343 , TRICORE_INS_ST_B = 344 , TRICORE_INS_ST_DA = 345 , TRICORE_INS_ST_D = 346 , TRICORE_INS_ST_H = 347 , TRICORE_INS_ST_Q = 348 , TRICORE_INS_ST_T = 349 , TRICORE_INS_ST_W = 350 , TRICORE_INS_SUBC = 351 , TRICORE_INS_SUBSC_A = 352 , TRICORE_INS_SUBS_BU = 353 , TRICORE_INS_SUBS_B = 354 , TRICORE_INS_SUBS_HU = 355 , TRICORE_INS_SUBS_H = 356 , TRICORE_INS_SUBS_U = 357 , TRICORE_INS_SUBS = 358 , TRICORE_INS_SUBX = 359 , TRICORE_INS_SUB_A = 360 , TRICORE_INS_SUB_B = 361 , TRICORE_INS_SUB_F = 362 , TRICORE_INS_SUB_H = 363 , TRICORE_INS_SUB = 364 , TRICORE_INS_SVLCX = 365 , TRICORE_INS_SWAPMSK_W = 366 , TRICORE_INS_SWAP_A = 367 , TRICORE_INS_SWAP_W = 368 , TRICORE_INS_SYSCALL = 369 , TRICORE_INS_TLBDEMAP = 370 , TRICORE_INS_TLBFLUSH_A = 371 , TRICORE_INS_TLBFLUSH_B = 372 , TRICORE_INS_TLBMAP = 373 , TRICORE_INS_TLBPROBE_A = 374 , TRICORE_INS_TLBPROBE_I = 375 , TRICORE_INS_TRAPSV = 376 , TRICORE_INS_TRAPV = 377 , TRICORE_INS_UNPACK = 378 , TRICORE_INS_UPDFL = 379 , TRICORE_INS_UTOF = 380 , TRICORE_INS_WAIT = 381 , TRICORE_INS_XNOR_T = 382 , TRICORE_INS_XNOR = 383 , TRICORE_INS_XOR_EQ = 384 , TRICORE_INS_XOR_GE_U = 385 , TRICORE_INS_XOR_GE = 386 , TRICORE_INS_XOR_LT_U = 387 , TRICORE_INS_XOR_LT = 388 , TRICORE_INS_XOR_NE = 389 , TRICORE_INS_XOR = 390 , TRICORE_INS_ENDING = 391 , } # [repr (u32)] # [doc = " Group of TriCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn_group { # [doc = "< = CS_GRP_INVALID"] TRICORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_CALL"] TRICORE_GRP_CALL = 1 , # [doc = "< = CS_GRP_JUMP"] TRICORE_GRP_JUMP = 2 , # [doc = "< mark the end of the list of groups"] TRICORE_GRP_ENDING = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_feature_t { TRICORE_FEATURE_INVALID = 0 , TRICORE_FEATURE_HasV110 = 128 , TRICORE_FEATURE_HasV120_UP = 129 , TRICORE_FEATURE_HasV130_UP = 130 , TRICORE_FEATURE_HasV161 = 131 , TRICORE_FEATURE_HasV160_UP = 132 , TRICORE_FEATURE_HasV131_UP = 133 , TRICORE_FEATURE_HasV161_UP = 134 , TRICORE_FEATURE_HasV162 = 135 , TRICORE_FEATURE_HasV162_UP = 136 , # [doc = "< mark the end of the list of features"] TRICORE_FEATURE_ENDING = 137 , } pub use self :: tricore_feature_t as tricore_feature ; # [doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_detail { pub regs_read : [u16 ; 20usize] , # [doc = "< number of implicit registers read by this insn"] pub regs_read_count : u8 , pub regs_write : [u16 ; 20usize] , # [doc = "< number of implicit registers modified by this insn"] pub regs_write_count : u8 , # [doc = "< list of group this instruction belong to"] pub groups : [u8 ; 8usize] , # [doc = "< number of groups this insn belongs to"] pub groups_count : u8 , # [doc = "< Instruction has writeback operands."] pub writeback : bool , pub __bindgen_anon_1 : cs_detail__bindgen_ty_1 , } # [doc = " Architecture-specific instruction info"] # [repr (C)] # [derive (Copy , Clone)] pub union cs_detail__bindgen_ty_1 { # [doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"] pub x86 : cs_x86 , # [doc = "< ARM64 architecture (aka AArch64)"] pub arm64 : cs_arm64 , # [doc = "< ARM architecture (including Thumb/Thumb2)"] pub arm : cs_arm , # [doc = "< M68K architecture"] pub m68k : cs_m68k , # [doc = "< MIPS architecture"] pub mips : cs_mips , # [doc = "< PowerPC architecture"] pub ppc : cs_ppc , # [doc = "< Sparc architecture"] pub sparc : cs_sparc , # [doc = "< SystemZ architecture"] pub sysz : cs_sysz , # [doc = "< XCore architecture"] pub xcore : cs_xcore , # [doc = "< TMS320C64x architecture"] pub tms320c64x : cs_tms320c64x , # [doc = "< M680X architecture"] pub m680x : cs_m680x , # [doc = "< Ethereum architecture"] pub evm : cs_evm , # [doc = "< MOS65XX architecture (including MOS6502)"] pub mos65xx : cs_mos65xx , # [doc = "< Web Assembly architecture"] pub wasm : cs_wasm , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] pub bpf : cs_bpf , # [doc = "< RISCV architecture"] pub riscv : cs_riscv , # [doc = "< SH architecture"] pub sh : cs_sh , # [doc = "< TriCore architecture"] pub tricore : cs_tricore , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_detail__bindgen_ty_1 > () - 1768usize] ; ["Alignment of cs_detail__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_detail__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_detail__bindgen_ty_1::x86"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , x86) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm64"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm64) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m68k"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m68k) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mips"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mips) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::ppc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , ppc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sparc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sparc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sysz"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sysz) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::xcore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , xcore) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tms320c64x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tms320c64x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m680x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m680x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::evm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , evm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mos65xx"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mos65xx) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::wasm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , wasm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::bpf"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , bpf) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::riscv"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , riscv) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sh"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sh) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tricore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tricore) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_detail__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail"] [:: std :: mem :: size_of :: < cs_detail > () - 1864usize] ; ["Alignment of cs_detail"] [:: std :: mem :: align_of :: < cs_detail > () - 8usize] ; ["Offset of field: cs_detail::regs_read"] [:: std :: mem :: offset_of ! (cs_detail , regs_read) - 0usize] ; ["Offset of field: cs_detail::regs_read_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_read_count) - 40usize] ; ["Offset of field: cs_detail::regs_write"] [:: std :: mem :: offset_of ! (cs_detail , regs_write) - 42usize] ; ["Offset of field: cs_detail::regs_write_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_write_count) - 82usize] ; ["Offset of field: cs_detail::groups"] [:: std :: mem :: offset_of ! (cs_detail , groups) - 83usize] ; ["Offset of field: cs_detail::groups_count"] [:: std :: mem :: offset_of ! (cs_detail , groups_count) - 91usize] ; ["Offset of field: cs_detail::writeback"] [:: std :: mem :: offset_of ! (cs_detail , writeback) - 92usize] ; } ; impl :: std :: fmt :: Debug for cs_detail { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, writeback: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . writeback , self . __bindgen_anon_1) } } # [doc = " Detail information of disassembled instruction"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_insn { # [doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub address : u64 , # [doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub size : u16 , # [doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub bytes : [u8 ; 24usize] , # [doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub mnemonic : [:: std :: os :: raw :: c_char ; 32usize] , # [doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub op_str : [:: std :: os :: raw :: c_char ; 160usize] , # [doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."] pub detail : * mut cs_detail , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_insn"] [:: std :: mem :: size_of :: < cs_insn > () - 248usize] ; ["Alignment of cs_insn"] [:: std :: mem :: align_of :: < cs_insn > () - 8usize] ; ["Offset of field: cs_insn::id"] [:: std :: mem :: offset_of ! (cs_insn , id) - 0usize] ; ["Offset of field: cs_insn::address"] [:: std :: mem :: offset_of ! (cs_insn , address) - 8usize] ; ["Offset of field: cs_insn::size"] [:: std :: mem :: offset_of ! (cs_insn , size) - 16usize] ; ["Offset of field: cs_insn::bytes"] [:: std :: mem :: offset_of ! (cs_insn , bytes) - 18usize] ; ["Offset of field: cs_insn::mnemonic"] [:: std :: mem :: offset_of ! (cs_insn , mnemonic) - 42usize] ; ["Offset of field: cs_insn::op_str"] [:: std :: mem :: offset_of ! (cs_insn , op_str) - 74usize] ; ["Offset of field: cs_insn::detail"] [:: std :: mem :: offset_of ! (cs_insn , detail) - 240usize] ; } ; # [repr (u32)] # [doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_err { # [doc = "< No error: everything was fine"] CS_ERR_OK = 0 , # [doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"] CS_ERR_MEM = 1 , # [doc = "< Unsupported architecture: cs_open()"] CS_ERR_ARCH = 2 , # [doc = "< Invalid handle: cs_op_count(), cs_op_index()"] CS_ERR_HANDLE = 3 , # [doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"] CS_ERR_CSH = 4 , # [doc = "< Invalid/unsupported mode: cs_open()"] CS_ERR_MODE = 5 , # [doc = "< Invalid/unsupported option: cs_option()"] CS_ERR_OPTION = 6 , # [doc = "< Information is unavailable because detail option is OFF"] CS_ERR_DETAIL = 7 , # [doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"] CS_ERR_MEMSETUP = 8 , # [doc = "< Unsupported version (bindings)"] CS_ERR_VERSION = 9 , # [doc = "< Access irrelevant data in \"diet\" engine"] CS_ERR_DIET = 10 , # [doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"] CS_ERR_SKIPDATA = 11 , # [doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_ATT = 12 , # [doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_INTEL = 13 , # [doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_MASM = 14 , } unsafe extern "C" { # [doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."] pub fn cs_version (major : * mut :: std :: os :: raw :: c_int , minor : * mut :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_uint ; } unsafe extern "C" { # [doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."] pub fn cs_support (query : :: std :: os :: raw :: c_int) -> bool ; } unsafe extern "C" { # [doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_open (arch : cs_arch , mode : cs_mode , handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_close (handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"] pub fn cs_option (handle : csh , type_ : cs_opt_type , value : usize) -> cs_err ; } unsafe extern "C" { # [doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"] pub fn cs_errno (handle : csh) -> cs_err ; } unsafe extern "C" { # [doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"] pub fn cs_strerror (code : cs_err) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm (handle : csh , code : * const u8 , code_size : usize , address : u64 , count : usize , insn : * mut * mut cs_insn) -> usize ; } unsafe extern "C" { # [doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."] pub fn cs_free (insn : * mut cs_insn , count : usize) ; } unsafe extern "C" { # [doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"] pub fn cs_malloc (handle : csh) -> * mut cs_insn ; } unsafe extern "C" { # [doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm_iter (handle : csh , code : * mut * const u8 , size : * mut usize , address : * mut u64 , insn : * mut cs_insn) -> bool ; } unsafe extern "C" { # [doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."] pub fn cs_reg_name (handle : csh , reg_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."] pub fn cs_insn_name (handle : csh , insn_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."] pub fn cs_group_name (handle : csh , group_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."] pub fn cs_insn_group (handle : csh , insn : * const cs_insn , group_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."] pub fn cs_reg_read (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."] pub fn cs_reg_write (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."] pub fn cs_op_count (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."] pub fn cs_op_index (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint , position : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } # [doc = " Type of array to keep the list of registers"] pub type cs_regs = [u16 ; 64usize] ; unsafe extern "C" { # [doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_regs_access (handle : csh , insn : * const cs_insn , regs_read : * mut u16 , regs_read_count : * mut u8 , regs_write : * mut u16 , regs_write_count : * mut u8) -> cs_err ; } pub type __builtin_va_list = [__va_list_tag ; 1usize] ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __va_list_tag { pub gp_offset : :: std :: os :: raw :: c_uint , pub fp_offset : :: std :: os :: raw :: c_uint , pub overflow_arg_area : * mut :: std :: os :: raw :: c_void , pub reg_save_area : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __va_list_tag"] [:: std :: mem :: size_of :: < __va_list_tag > () - 24usize] ; ["Alignment of __va_list_tag"] [:: std :: mem :: align_of :: < __va_list_tag > () - 8usize] ; ["Offset of field: __va_list_tag::gp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , gp_offset) - 0usize] ; ["Offset of field: __va_list_tag::fp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , fp_offset) - 4usize] ; ["Offset of field: __va_list_tag::overflow_arg_area"] [:: std :: mem :: offset_of ! (__va_list_tag , overflow_arg_area) - 8usize] ; ["Offset of field: __va_list_tag::reg_save_area"] [:: std :: mem :: offset_of ! (__va_list_tag , reg_save_area) - 16usize] ; } ;
[INFO] [stdout] 3 + # [repr (C)] # [derive (Copy , Clone , Debug , Default , Eq , Hash , Ord , PartialEq , PartialOrd)] pub struct __BindgenBitfieldUnit < Storage > { storage : Storage , } impl < Storage > __BindgenBitfieldUnit < Storage > { # [inline] pub const fn new (storage : Storage) -> Self { Self { storage } } } impl < Storage > __BindgenBitfieldUnit < Storage > where Storage : AsRef < [u8] > + AsMut < [u8] >, { # [inline] fn extract_bit (byte : u8 , index : usize) -> bool { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; byte & mask == mask } # [inline] pub fn get_bit (& self , index : usize) -> bool { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = self . storage . as_ref () [byte_index] ; Self :: extract_bit (byte , index) } # [inline] pub unsafe fn raw_get_bit (this : * const Self , index : usize) -> bool { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { * (core :: ptr :: addr_of ! ((* this) . storage) as * const u8) . offset (byte_index as isize) } ; Self :: extract_bit (byte , index) } # [inline] fn change_bit (byte : u8 , index : usize , val : bool) -> u8 { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; if val { byte | mask } else { byte & ! mask } } # [inline] pub fn set_bit (& mut self , index : usize , val : bool) { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = & mut self . storage . as_mut () [byte_index] ; * byte = Self :: change_bit (* byte , index , val) ; } # [inline] pub unsafe fn raw_set_bit (this : * mut Self , index : usize , val : bool) { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { (core :: ptr :: addr_of_mut ! ((* this) . storage) as * mut u8) . offset (byte_index as isize) } ; unsafe { * byte = Self :: change_bit (* byte , index , val) } ; } # [inline] pub fn get (& self , bit_offset : usize , bit_width : u8) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if self . get_bit (i + bit_offset) { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub unsafe fn raw_get (this : * const Self , bit_offset : usize , bit_width : u8 ,) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if unsafe { Self :: raw_get_bit (this , i + bit_offset) } { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub fn set (& mut self , bit_offset : usize , bit_width : u8 , val : u64) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; self . set_bit (index + bit_offset , val_bit_is_set) ; } } # [inline] pub unsafe fn raw_set (this : * mut Self , bit_offset : usize , bit_width : u8 , val : u64 ,) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; unsafe { Self :: raw_set_bit (this , index + bit_offset , val_bit_is_set) } ; } } } # [derive (PartialEq , Copy , Clone , Hash , Debug , Default)] # [repr (C)] pub struct __BindgenComplex < T > { pub re : T , pub im : T } pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __GLIBC_USE_ISOC2Y : u32 = 0 ; pub const __GLIBC_USE_ISOC23 : u32 = 0 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 202405 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_XOPEN2K24 : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const __TIMESIZE : u32 = 64 ; pub const __USE_TIME_BITS64 : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_GETS : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_SCANF : u32 = 0 ; pub const __GLIBC_USE_C23_STRTOL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_60559_BFP__ : u32 = 201404 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_IEC_60559_COMPLEX__ : u32 = 201404 ; pub const __STDC_ISO_10646__ : u32 = 201706 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 43 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __glibc_c99_flexarr_available : u32 = 1 ; pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI : u32 = 0 ; pub const __HAVE_GENERIC_SELECTION : u32 = 1 ; pub const __GLIBC_USE_LIB_EXT2 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_TYPES_EXT : u32 = 0 ; pub const _STDLIB_H : u32 = 1 ; pub const WNOHANG : u32 = 1 ; pub const WUNTRACED : u32 = 2 ; pub const WSTOPPED : u32 = 2 ; pub const WEXITED : u32 = 4 ; pub const WCONTINUED : u32 = 8 ; pub const WNOWAIT : u32 = 16777216 ; pub const __WNOTHREAD : u32 = 536870912 ; pub const __WALL : u32 = 1073741824 ; pub const __WCLONE : u32 = 2147483648 ; pub const __W_CONTINUED : u32 = 65535 ; pub const __WCOREFLAG : u32 = 128 ; pub const __HAVE_FLOAT128 : u32 = 1 ; pub const __HAVE_DISTINCT_FLOAT128 : u32 = 1 ; pub const __HAVE_FLOAT64X : u32 = 1 ; pub const __HAVE_FLOAT64X_LONG_DOUBLE : u32 = 1 ; pub const __HAVE_FLOAT16 : u32 = 0 ; pub const __HAVE_FLOAT32 : u32 = 1 ; pub const __HAVE_FLOAT64 : u32 = 1 ; pub const __HAVE_FLOAT32X : u32 = 1 ; pub const __HAVE_FLOAT128X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT16 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT128X : u32 = 0 ; pub const __HAVE_FLOATN_NOT_TYPEDEF : u32 = 0 ; pub const __ldiv_t_defined : u32 = 1 ; pub const __lldiv_t_defined : u32 = 1 ; pub const RAND_MAX : u32 = 2147483647 ; pub const EXIT_FAILURE : u32 = 1 ; pub const EXIT_SUCCESS : u32 = 0 ; pub const _SYS_TYPES_H : u32 = 1 ; pub const _BITS_TYPES_H : u32 = 1 ; pub const _BITS_TYPESIZES_H : u32 = 1 ; pub const __OFF_T_MATCHES_OFF64_T : u32 = 1 ; pub const __INO_T_MATCHES_INO64_T : u32 = 1 ; pub const __RLIM_T_MATCHES_RLIM64_T : u32 = 1 ; pub const __STATFS_MATCHES_STATFS64 : u32 = 1 ; pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 : u32 = 1 ; pub const __FD_SETSIZE : u32 = 1024 ; pub const _BITS_TIME64_H : u32 = 1 ; pub const __clock_t_defined : u32 = 1 ; pub const __clockid_t_defined : u32 = 1 ; pub const __time_t_defined : u32 = 1 ; pub const __timer_t_defined : u32 = 1 ; pub const _BITS_STDINT_INTN_H : u32 = 1 ; pub const __BIT_TYPES_DEFINED__ : u32 = 1 ; pub const _ENDIAN_H : u32 = 1 ; pub const _BITS_ENDIAN_H : u32 = 1 ; pub const __LITTLE_ENDIAN : u32 = 1234 ; pub const __BIG_ENDIAN : u32 = 4321 ; pub const __PDP_ENDIAN : u32 = 3412 ; pub const _BITS_ENDIANNESS_H : u32 = 1 ; pub const __BYTE_ORDER : u32 = 1234 ; pub const __FLOAT_WORD_ORDER : u32 = 1234 ; pub const LITTLE_ENDIAN : u32 = 1234 ; pub const BIG_ENDIAN : u32 = 4321 ; pub const PDP_ENDIAN : u32 = 3412 ; pub const BYTE_ORDER : u32 = 1234 ; pub const _BITS_BYTESWAP_H : u32 = 1 ; pub const _BITS_UINTN_IDENTITY_H : u32 = 1 ; pub const _SYS_SELECT_H : u32 = 1 ; pub const __sigset_t_defined : u32 = 1 ; pub const __timeval_defined : u32 = 1 ; pub const _STRUCT_TIMESPEC : u32 = 1 ; pub const FD_SETSIZE : u32 = 1024 ; pub const _BITS_PTHREADTYPES_COMMON_H : u32 = 1 ; pub const _THREAD_SHARED_TYPES_H : u32 = 1 ; pub const _BITS_PTHREADTYPES_ARCH_H : u32 = 1 ; pub const __SIZEOF_PTHREAD_MUTEX_T : u32 = 40 ; pub const __SIZEOF_PTHREAD_ATTR_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_RWLOCK_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_BARRIER_T : u32 = 32 ; pub const __SIZEOF_PTHREAD_MUTEXATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_COND_T : u32 = 48 ; pub const __SIZEOF_PTHREAD_CONDATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_RWLOCKATTR_T : u32 = 8 ; pub const __SIZEOF_PTHREAD_BARRIERATTR_T : u32 = 4 ; pub const _THREAD_MUTEX_INTERNAL_H : u32 = 1 ; pub const __PTHREAD_MUTEX_HAVE_PREV : u32 = 1 ; pub const __have_pthread_attr_t : u32 = 1 ; pub const _ALLOCA_H : u32 = 1 ; pub const _STDIO_H : u32 = 1 ; pub const _____fpos_t_defined : u32 = 1 ; pub const ____mbstate_t_defined : u32 = 1 ; pub const _____fpos64_t_defined : u32 = 1 ; pub const ____FILE_defined : u32 = 1 ; pub const __FILE_defined : u32 = 1 ; pub const __struct_FILE_defined : u32 = 1 ; pub const _IO_EOF_SEEN : u32 = 16 ; pub const _IO_ERR_SEEN : u32 = 32 ; pub const _IO_USER_LOCK : u32 = 32768 ; pub const __cookie_io_functions_t_defined : u32 = 1 ; pub const _IOFBF : u32 = 0 ; pub const _IOLBF : u32 = 1 ; pub const _IONBF : u32 = 2 ; pub const BUFSIZ : u32 = 8192 ; pub const EOF : i32 = - 1 ; pub const SEEK_SET : u32 = 0 ; pub const SEEK_CUR : u32 = 1 ; pub const SEEK_END : u32 = 2 ; pub const P_tmpdir : & [u8 ; 5] = b"/tmp\0" ; pub const L_tmpnam : u32 = 20 ; pub const TMP_MAX : u32 = 238328 ; pub const _BITS_STDIO_LIM_H : u32 = 1 ; pub const FILENAME_MAX : u32 = 4096 ; pub const L_ctermid : u32 = 9 ; pub const FOPEN_MAX : u32 = 16 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const _INTTYPES_H : u32 = 1 ; pub const _STDINT_H : u32 = 1 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const _BITS_STDINT_UINTN_H : u32 = 1 ; pub const _BITS_STDINT_LEAST_H : u32 = 1 ; pub const INT8_MIN : i32 = - 128 ; pub const INT16_MIN : i32 = - 32768 ; pub const INT32_MIN : i32 = - 2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = - 128 ; pub const INT_LEAST16_MIN : i32 = - 32768 ; pub const INT_LEAST32_MIN : i32 = - 2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = - 128 ; pub const INT_FAST16_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST32_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = - 1 ; pub const UINT_FAST32_MAX : i32 = - 1 ; pub const INTPTR_MIN : i64 = - 9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = - 1 ; pub const PTRDIFF_MIN : i64 = - 9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = - 2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = - 1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const ____gwchar_t_defined : u32 = 1 ; pub const __PRI64_PREFIX : & [u8 ; 2] = b"l\0" ; pub const __PRIPTR_PREFIX : & [u8 ; 2] = b"l\0" ; pub const PRId8 : & [u8 ; 4] = b"hhd\0" ; pub const PRId16 : & [u8 ; 3] = b"hd\0" ; pub const PRId32 : & [u8 ; 2] = b"d\0" ; pub const PRId64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const PRIdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const PRIdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIi8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIi16 : & [u8 ; 3] = b"hi\0" ; pub const PRIi32 : & [u8 ; 2] = b"i\0" ; pub const PRIi64 : & [u8 ; 3] = b"li\0" ; pub const PRIiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const PRIiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const PRIiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiFAST16 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST32 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIo8 : & [u8 ; 4] = b"hho\0" ; pub const PRIo16 : & [u8 ; 3] = b"ho\0" ; pub const PRIo32 : & [u8 ; 2] = b"o\0" ; pub const PRIo64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const PRIoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const PRIoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIu8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIu16 : & [u8 ; 3] = b"hu\0" ; pub const PRIu32 : & [u8 ; 2] = b"u\0" ; pub const PRIu64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const PRIuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const PRIuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIx8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIx16 : & [u8 ; 3] = b"hx\0" ; pub const PRIx32 : & [u8 ; 2] = b"x\0" ; pub const PRIx64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const PRIxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const PRIxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIX8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIX16 : & [u8 ; 3] = b"hX\0" ; pub const PRIX32 : & [u8 ; 2] = b"X\0" ; pub const PRIX64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXLEAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXLEAST16 : & [u8 ; 3] = b"hX\0" ; pub const PRIXLEAST32 : & [u8 ; 2] = b"X\0" ; pub const PRIXLEAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXFAST16 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST32 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIdMAX : & [u8 ; 3] = b"ld\0" ; pub const PRIiMAX : & [u8 ; 3] = b"li\0" ; pub const PRIoMAX : & [u8 ; 3] = b"lo\0" ; pub const PRIuMAX : & [u8 ; 3] = b"lu\0" ; pub const PRIxMAX : & [u8 ; 3] = b"lx\0" ; pub const PRIXMAX : & [u8 ; 3] = b"lX\0" ; pub const PRIdPTR : & [u8 ; 3] = b"ld\0" ; pub const PRIiPTR : & [u8 ; 3] = b"li\0" ; pub const PRIoPTR : & [u8 ; 3] = b"lo\0" ; pub const PRIuPTR : & [u8 ; 3] = b"lu\0" ; pub const PRIxPTR : & [u8 ; 3] = b"lx\0" ; pub const PRIXPTR : & [u8 ; 3] = b"lX\0" ; pub const SCNd8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNd16 : & [u8 ; 3] = b"hd\0" ; pub const SCNd32 : & [u8 ; 2] = b"d\0" ; pub const SCNd64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const SCNdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const SCNdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNi8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNi16 : & [u8 ; 3] = b"hi\0" ; pub const SCNi32 : & [u8 ; 2] = b"i\0" ; pub const SCNi64 : & [u8 ; 3] = b"li\0" ; pub const SCNiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const SCNiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const SCNiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiFAST16 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST32 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNu8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNu16 : & [u8 ; 3] = b"hu\0" ; pub const SCNu32 : & [u8 ; 2] = b"u\0" ; pub const SCNu64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const SCNuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const SCNuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNo8 : & [u8 ; 4] = b"hho\0" ; pub const SCNo16 : & [u8 ; 3] = b"ho\0" ; pub const SCNo32 : & [u8 ; 2] = b"o\0" ; pub const SCNo64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const SCNoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const SCNoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNx8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNx16 : & [u8 ; 3] = b"hx\0" ; pub const SCNx32 : & [u8 ; 2] = b"x\0" ; pub const SCNx64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const SCNxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const SCNxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNdMAX : & [u8 ; 3] = b"ld\0" ; pub const SCNiMAX : & [u8 ; 3] = b"li\0" ; pub const SCNoMAX : & [u8 ; 3] = b"lo\0" ; pub const SCNuMAX : & [u8 ; 3] = b"lu\0" ; pub const SCNxMAX : & [u8 ; 3] = b"lx\0" ; pub const SCNdPTR : & [u8 ; 3] = b"ld\0" ; pub const SCNiPTR : & [u8 ; 3] = b"li\0" ; pub const SCNoPTR : & [u8 ; 3] = b"lo\0" ; pub const SCNuPTR : & [u8 ; 3] = b"lu\0" ; pub const SCNxPTR : & [u8 ; 3] = b"lx\0" ; pub const CS_API_MAJOR : u32 = 5 ; pub const CS_API_MINOR : u32 = 0 ; pub const CS_NEXT_VERSION : u32 = 5 ; pub const CS_VERSION_MAJOR : u32 = 5 ; pub const CS_VERSION_MINOR : u32 = 0 ; pub const CS_VERSION_EXTRA : u32 = 7 ; pub const CS_MNEMONIC_SIZE : u32 = 32 ; pub const M68K_OPERAND_COUNT : u32 = 4 ; pub const X86_EFLAGS_MODIFY_AF : u32 = 1 ; pub const X86_EFLAGS_MODIFY_CF : u32 = 2 ; pub const X86_EFLAGS_MODIFY_SF : u32 = 4 ; pub const X86_EFLAGS_MODIFY_ZF : u32 = 8 ; pub const X86_EFLAGS_MODIFY_PF : u32 = 16 ; pub const X86_EFLAGS_MODIFY_OF : u32 = 32 ; pub const X86_EFLAGS_MODIFY_TF : u32 = 64 ; pub const X86_EFLAGS_MODIFY_IF : u32 = 128 ; pub const X86_EFLAGS_MODIFY_DF : u32 = 256 ; pub const X86_EFLAGS_MODIFY_NT : u32 = 512 ; pub const X86_EFLAGS_MODIFY_RF : u32 = 1024 ; pub const X86_EFLAGS_PRIOR_OF : u32 = 2048 ; pub const X86_EFLAGS_PRIOR_SF : u32 = 4096 ; pub const X86_EFLAGS_PRIOR_ZF : u32 = 8192 ; pub const X86_EFLAGS_PRIOR_AF : u32 = 16384 ; pub const X86_EFLAGS_PRIOR_PF : u32 = 32768 ; pub const X86_EFLAGS_PRIOR_CF : u32 = 65536 ; pub const X86_EFLAGS_PRIOR_TF : u32 = 131072 ; pub const X86_EFLAGS_PRIOR_IF : u32 = 262144 ; pub const X86_EFLAGS_PRIOR_DF : u32 = 524288 ; pub const X86_EFLAGS_PRIOR_NT : u32 = 1048576 ; pub const X86_EFLAGS_RESET_OF : u32 = 2097152 ; pub const X86_EFLAGS_RESET_CF : u32 = 4194304 ; pub const X86_EFLAGS_RESET_DF : u32 = 8388608 ; pub const X86_EFLAGS_RESET_IF : u32 = 16777216 ; pub const X86_EFLAGS_RESET_SF : u32 = 33554432 ; pub const X86_EFLAGS_RESET_AF : u32 = 67108864 ; pub const X86_EFLAGS_RESET_TF : u32 = 134217728 ; pub const X86_EFLAGS_RESET_NT : u32 = 268435456 ; pub const X86_EFLAGS_RESET_PF : u32 = 536870912 ; pub const X86_EFLAGS_SET_CF : u32 = 1073741824 ; pub const X86_EFLAGS_SET_DF : u32 = 2147483648 ; pub const X86_EFLAGS_SET_IF : u64 = 4294967296 ; pub const X86_EFLAGS_TEST_OF : u64 = 8589934592 ; pub const X86_EFLAGS_TEST_SF : u64 = 17179869184 ; pub const X86_EFLAGS_TEST_ZF : u64 = 34359738368 ; pub const X86_EFLAGS_TEST_PF : u64 = 68719476736 ; pub const X86_EFLAGS_TEST_CF : u64 = 137438953472 ; pub const X86_EFLAGS_TEST_NT : u64 = 274877906944 ; pub const X86_EFLAGS_TEST_DF : u64 = 549755813888 ; pub const X86_EFLAGS_UNDEFINED_OF : u64 = 1099511627776 ; pub const X86_EFLAGS_UNDEFINED_SF : u64 = 2199023255552 ; pub const X86_EFLAGS_UNDEFINED_ZF : u64 = 4398046511104 ; pub const X86_EFLAGS_UNDEFINED_PF : u64 = 8796093022208 ; pub const X86_EFLAGS_UNDEFINED_AF : u64 = 17592186044416 ; pub const X86_EFLAGS_UNDEFINED_CF : u64 = 35184372088832 ; pub const X86_EFLAGS_RESET_RF : u64 = 70368744177664 ; pub const X86_EFLAGS_TEST_RF : u64 = 140737488355328 ; pub const X86_EFLAGS_TEST_IF : u64 = 281474976710656 ; pub const X86_EFLAGS_TEST_TF : u64 = 562949953421312 ; pub const X86_EFLAGS_TEST_AF : u64 = 1125899906842624 ; pub const X86_EFLAGS_RESET_ZF : u64 = 2251799813685248 ; pub const X86_EFLAGS_SET_OF : u64 = 4503599627370496 ; pub const X86_EFLAGS_SET_SF : u64 = 9007199254740992 ; pub const X86_EFLAGS_SET_ZF : u64 = 18014398509481984 ; pub const X86_EFLAGS_SET_AF : u64 = 36028797018963968 ; pub const X86_EFLAGS_SET_PF : u64 = 72057594037927936 ; pub const X86_EFLAGS_RESET_0F : u64 = 144115188075855872 ; pub const X86_EFLAGS_RESET_AC : u64 = 288230376151711744 ; pub const X86_FPU_FLAGS_MODIFY_C0 : u32 = 1 ; pub const X86_FPU_FLAGS_MODIFY_C1 : u32 = 2 ; pub const X86_FPU_FLAGS_MODIFY_C2 : u32 = 4 ; pub const X86_FPU_FLAGS_MODIFY_C3 : u32 = 8 ; pub const X86_FPU_FLAGS_RESET_C0 : u32 = 16 ; pub const X86_FPU_FLAGS_RESET_C1 : u32 = 32 ; pub const X86_FPU_FLAGS_RESET_C2 : u32 = 64 ; pub const X86_FPU_FLAGS_RESET_C3 : u32 = 128 ; pub const X86_FPU_FLAGS_SET_C0 : u32 = 256 ; pub const X86_FPU_FLAGS_SET_C1 : u32 = 512 ; pub const X86_FPU_FLAGS_SET_C2 : u32 = 1024 ; pub const X86_FPU_FLAGS_SET_C3 : u32 = 2048 ; pub const X86_FPU_FLAGS_UNDEFINED_C0 : u32 = 4096 ; pub const X86_FPU_FLAGS_UNDEFINED_C1 : u32 = 8192 ; pub const X86_FPU_FLAGS_UNDEFINED_C2 : u32 = 16384 ; pub const X86_FPU_FLAGS_UNDEFINED_C3 : u32 = 32768 ; pub const X86_FPU_FLAGS_TEST_C0 : u32 = 65536 ; pub const X86_FPU_FLAGS_TEST_C1 : u32 = 131072 ; pub const X86_FPU_FLAGS_TEST_C2 : u32 = 262144 ; pub const X86_FPU_FLAGS_TEST_C3 : u32 = 524288 ; pub const M680X_OPERAND_COUNT : u32 = 9 ; pub const M680X_OFFSET_NONE : u32 = 0 ; pub const M680X_OFFSET_BITS_5 : u32 = 5 ; pub const M680X_OFFSET_BITS_8 : u32 = 8 ; pub const M680X_OFFSET_BITS_9 : u32 = 9 ; pub const M680X_OFFSET_BITS_16 : u32 = 16 ; pub const M680X_IDX_INDIRECT : u32 = 1 ; pub const M680X_IDX_NO_COMMA : u32 = 2 ; pub const M680X_IDX_POST_INC_DEC : u32 = 4 ; pub const M680X_FIRST_OP_IN_MNEM : u32 = 1 ; pub const M680X_SECOND_OP_IN_MNEM : u32 = 2 ; pub const TRICORE_OP_COUNT : u32 = 8 ; pub const MAX_IMPL_W_REGS : u32 = 20 ; pub const MAX_IMPL_R_REGS : u32 = 20 ; pub const MAX_NUM_GROUPS : u32 = 8 ; pub type __gnuc_va_list = __builtin_va_list ; pub type va_list = __builtin_va_list ; pub type wchar_t = :: std :: os :: raw :: c_int ; pub type __cfloat128 = __BindgenComplex < u128 > ; pub type _Float128 = u128 ; pub type _Float32 = f32 ; pub type _Float64 = f64 ; pub type _Float32x = f64 ; pub type _Float64x = u128 ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct div_t { pub quot : :: std :: os :: raw :: c_int , pub rem : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of div_t"] [:: std :: mem :: size_of :: < div_t > () - 8usize] ; ["Alignment of div_t"] [:: std :: mem :: align_of :: < div_t > () - 4usize] ; ["Offset of field: div_t::quot"] [:: std :: mem :: offset_of ! (div_t , quot) - 0usize] ; ["Offset of field: div_t::rem"] [:: std :: mem :: offset_of ! (div_t , rem) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ldiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ldiv_t"] [:: std :: mem :: size_of :: < ldiv_t > () - 16usize] ; ["Alignment of ldiv_t"] [:: std :: mem :: align_of :: < ldiv_t > () - 8usize] ; ["Offset of field: ldiv_t::quot"] [:: std :: mem :: offset_of ! (ldiv_t , quot) - 0usize] ; ["Offset of field: ldiv_t::rem"] [:: std :: mem :: offset_of ! (ldiv_t , rem) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct lldiv_t { pub quot : :: std :: os :: raw :: c_longlong , pub rem : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of lldiv_t"] [:: std :: mem :: size_of :: < lldiv_t > () - 16usize] ; ["Alignment of lldiv_t"] [:: std :: mem :: align_of :: < lldiv_t > () - 8usize] ; ["Offset of field: lldiv_t::quot"] [:: std :: mem :: offset_of ! (lldiv_t , quot) - 0usize] ; ["Offset of field: lldiv_t::rem"] [:: std :: mem :: offset_of ! (lldiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn __ctype_get_mb_cur_max () -> usize ; } unsafe extern "C" { pub fn atof (__nptr : * const :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn atoi (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn atol (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn atoll (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtod (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn strtof (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f32 ; } unsafe extern "C" { pub fn strtold (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> u128 ; } unsafe extern "C" { pub fn strtol (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn strtoul (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn strtoq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtouq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn strtoll (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtoull (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn l64a (__n : :: std :: os :: raw :: c_long) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn a64l (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } pub type __u_char = :: std :: os :: raw :: c_uchar ; pub type __u_short = :: std :: os :: raw :: c_ushort ; pub type __u_int = :: std :: os :: raw :: c_uint ; pub type __u_long = :: std :: os :: raw :: c_ulong ; pub type __int8_t = :: std :: os :: raw :: c_schar ; pub type __uint8_t = :: std :: os :: raw :: c_uchar ; pub type __int16_t = :: std :: os :: raw :: c_short ; pub type __uint16_t = :: std :: os :: raw :: c_ushort ; pub type __int32_t = :: std :: os :: raw :: c_int ; pub type __uint32_t = :: std :: os :: raw :: c_uint ; pub type __int64_t = :: std :: os :: raw :: c_long ; pub type __uint64_t = :: std :: os :: raw :: c_ulong ; pub type __int_least8_t = __int8_t ; pub type __uint_least8_t = __uint8_t ; pub type __int_least16_t = __int16_t ; pub type __uint_least16_t = __uint16_t ; pub type __int_least32_t = __int32_t ; pub type __uint_least32_t = __uint32_t ; pub type __int_least64_t = __int64_t ; pub type __uint_least64_t = __uint64_t ; pub type __quad_t = :: std :: os :: raw :: c_long ; pub type __u_quad_t = :: std :: os :: raw :: c_ulong ; pub type __intmax_t = :: std :: os :: raw :: c_long ; pub type __uintmax_t = :: std :: os :: raw :: c_ulong ; pub type __dev_t = :: std :: os :: raw :: c_ulong ; pub type __uid_t = :: std :: os :: raw :: c_uint ; pub type __gid_t = :: std :: os :: raw :: c_uint ; pub type __ino_t = :: std :: os :: raw :: c_ulong ; pub type __ino64_t = :: std :: os :: raw :: c_ulong ; pub type __mode_t = :: std :: os :: raw :: c_uint ; pub type __nlink_t = :: std :: os :: raw :: c_ulong ; pub type __off_t = :: std :: os :: raw :: c_long ; pub type __off64_t = :: std :: os :: raw :: c_long ; pub type __pid_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __fsid_t { pub __val : [:: std :: os :: raw :: c_int ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __fsid_t"] [:: std :: mem :: size_of :: < __fsid_t > () - 8usize] ; ["Alignment of __fsid_t"] [:: std :: mem :: align_of :: < __fsid_t > () - 4usize] ; ["Offset of field: __fsid_t::__val"] [:: std :: mem :: offset_of ! (__fsid_t , __val) - 0usize] ; } ; pub type __clock_t = :: std :: os :: raw :: c_long ; pub type __rlim_t = :: std :: os :: raw :: c_ulong ; pub type __rlim64_t = :: std :: os :: raw :: c_ulong ; pub type __id_t = :: std :: os :: raw :: c_uint ; pub type __time_t = :: std :: os :: raw :: c_long ; pub type __useconds_t = :: std :: os :: raw :: c_uint ; pub type __suseconds_t = :: std :: os :: raw :: c_long ; pub type __suseconds64_t = :: std :: os :: raw :: c_long ; pub type __daddr_t = :: std :: os :: raw :: c_int ; pub type __key_t = :: std :: os :: raw :: c_int ; pub type __clockid_t = :: std :: os :: raw :: c_int ; pub type __timer_t = * mut :: std :: os :: raw :: c_void ; pub type __blksize_t = :: std :: os :: raw :: c_long ; pub type __blkcnt_t = :: std :: os :: raw :: c_long ; pub type __blkcnt64_t = :: std :: os :: raw :: c_long ; pub type __fsblkcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsblkcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsword_t = :: std :: os :: raw :: c_long ; pub type __ssize_t = :: std :: os :: raw :: c_long ; pub type __syscall_slong_t = :: std :: os :: raw :: c_long ; pub type __syscall_ulong_t = :: std :: os :: raw :: c_ulong ; pub type __loff_t = __off64_t ; pub type __caddr_t = * mut :: std :: os :: raw :: c_char ; pub type __intptr_t = :: std :: os :: raw :: c_long ; pub type __socklen_t = :: std :: os :: raw :: c_uint ; pub type __sig_atomic_t = :: std :: os :: raw :: c_int ; pub type u_char = __u_char ; pub type u_short = __u_short ; pub type u_int = __u_int ; pub type u_long = __u_long ; pub type quad_t = __quad_t ; pub type u_quad_t = __u_quad_t ; pub type fsid_t = __fsid_t ; pub type loff_t = __loff_t ; pub type ino_t = __ino_t ; pub type dev_t = __dev_t ; pub type gid_t = __gid_t ; pub type mode_t = __mode_t ; pub type nlink_t = __nlink_t ; pub type uid_t = __uid_t ; pub type off_t = __off_t ; pub type pid_t = __pid_t ; pub type id_t = __id_t ; pub type daddr_t = __daddr_t ; pub type caddr_t = __caddr_t ; pub type key_t = __key_t ; pub type clock_t = __clock_t ; pub type clockid_t = __clockid_t ; pub type time_t = __time_t ; pub type timer_t = __timer_t ; pub type ulong = :: std :: os :: raw :: c_ulong ; pub type ushort = :: std :: os :: raw :: c_ushort ; pub type uint = :: std :: os :: raw :: c_uint ; pub type u_int8_t = __uint8_t ; pub type u_int16_t = __uint16_t ; pub type u_int32_t = __uint32_t ; pub type u_int64_t = __uint64_t ; pub type register_t = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __sigset_t { pub __val : [:: std :: os :: raw :: c_ulong ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __sigset_t"] [:: std :: mem :: size_of :: < __sigset_t > () - 128usize] ; ["Alignment of __sigset_t"] [:: std :: mem :: align_of :: < __sigset_t > () - 8usize] ; ["Offset of field: __sigset_t::__val"] [:: std :: mem :: offset_of ! (__sigset_t , __val) - 0usize] ; } ; pub type sigset_t = __sigset_t ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timeval { pub tv_sec : __time_t , pub tv_usec : __suseconds_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timeval"] [:: std :: mem :: size_of :: < timeval > () - 16usize] ; ["Alignment of timeval"] [:: std :: mem :: align_of :: < timeval > () - 8usize] ; ["Offset of field: timeval::tv_sec"] [:: std :: mem :: offset_of ! (timeval , tv_sec) - 0usize] ; ["Offset of field: timeval::tv_usec"] [:: std :: mem :: offset_of ! (timeval , tv_usec) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timespec { pub tv_sec : __time_t , pub tv_nsec : __syscall_slong_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timespec"] [:: std :: mem :: size_of :: < timespec > () - 16usize] ; ["Alignment of timespec"] [:: std :: mem :: align_of :: < timespec > () - 8usize] ; ["Offset of field: timespec::tv_sec"] [:: std :: mem :: offset_of ! (timespec , tv_sec) - 0usize] ; ["Offset of field: timespec::tv_nsec"] [:: std :: mem :: offset_of ! (timespec , tv_nsec) - 8usize] ; } ; pub type suseconds_t = __suseconds_t ; pub type __fd_mask = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct fd_set { pub __fds_bits : [__fd_mask ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of fd_set"] [:: std :: mem :: size_of :: < fd_set > () - 128usize] ; ["Alignment of fd_set"] [:: std :: mem :: align_of :: < fd_set > () - 8usize] ; ["Offset of field: fd_set::__fds_bits"] [:: std :: mem :: offset_of ! (fd_set , __fds_bits) - 0usize] ; } ; pub type fd_mask = __fd_mask ; unsafe extern "C" { pub fn select (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * mut timeval) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pselect (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * const timespec , __sigmask : * const __sigset_t) -> :: std :: os :: raw :: c_int ; } pub type blksize_t = __blksize_t ; pub type blkcnt_t = __blkcnt_t ; pub type fsblkcnt_t = __fsblkcnt_t ; pub type fsfilcnt_t = __fsfilcnt_t ; # [repr (C)] # [derive (Copy , Clone)] pub union __atomic_wide_counter { pub __value64 : :: std :: os :: raw :: c_ulonglong , pub __value32 : __atomic_wide_counter__bindgen_ty_1 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __atomic_wide_counter__bindgen_ty_1 { pub __low : :: std :: os :: raw :: c_uint , pub __high : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: size_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 8usize] ; ["Alignment of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: align_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__low"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __low) - 0usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__high"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __high) - 4usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter"] [:: std :: mem :: size_of :: < __atomic_wide_counter > () - 8usize] ; ["Alignment of __atomic_wide_counter"] [:: std :: mem :: align_of :: < __atomic_wide_counter > () - 8usize] ; ["Offset of field: __atomic_wide_counter::__value64"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value64) - 0usize] ; ["Offset of field: __atomic_wide_counter::__value32"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value32) - 0usize] ; } ; impl :: std :: fmt :: Debug for __atomic_wide_counter { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__atomic_wide_counter {{ union }}") } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_list { pub __prev : * mut __pthread_internal_list , pub __next : * mut __pthread_internal_list , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_list"] [:: std :: mem :: size_of :: < __pthread_internal_list > () - 16usize] ; ["Alignment of __pthread_internal_list"] [:: std :: mem :: align_of :: < __pthread_internal_list > () - 8usize] ; ["Offset of field: __pthread_internal_list::__prev"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __prev) - 0usize] ; ["Offset of field: __pthread_internal_list::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __next) - 8usize] ; } ; pub type __pthread_list_t = __pthread_internal_list ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_slist { pub __next : * mut __pthread_internal_slist , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_slist"] [:: std :: mem :: size_of :: < __pthread_internal_slist > () - 8usize] ; ["Alignment of __pthread_internal_slist"] [:: std :: mem :: align_of :: < __pthread_internal_slist > () - 8usize] ; ["Offset of field: __pthread_internal_slist::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_slist , __next) - 0usize] ; } ; pub type __pthread_slist_t = __pthread_internal_slist ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_mutex_s { pub __lock : :: std :: os :: raw :: c_int , pub __count : :: std :: os :: raw :: c_uint , pub __owner : :: std :: os :: raw :: c_int , pub __nusers : :: std :: os :: raw :: c_uint , pub __kind : :: std :: os :: raw :: c_int , pub __spins : :: std :: os :: raw :: c_short , pub __unused : :: std :: os :: raw :: c_short , pub __list : __pthread_list_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_mutex_s"] [:: std :: mem :: size_of :: < __pthread_mutex_s > () - 40usize] ; ["Alignment of __pthread_mutex_s"] [:: std :: mem :: align_of :: < __pthread_mutex_s > () - 8usize] ; ["Offset of field: __pthread_mutex_s::__lock"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __lock) - 0usize] ; ["Offset of field: __pthread_mutex_s::__count"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __count) - 4usize] ; ["Offset of field: __pthread_mutex_s::__owner"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __owner) - 8usize] ; ["Offset of field: __pthread_mutex_s::__nusers"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __nusers) - 12usize] ; ["Offset of field: __pthread_mutex_s::__kind"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __kind) - 16usize] ; ["Offset of field: __pthread_mutex_s::__spins"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __spins) - 20usize] ; ["Offset of field: __pthread_mutex_s::__unused"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __unused) - 22usize] ; ["Offset of field: __pthread_mutex_s::__list"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __list) - 24usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_rwlock_arch_t { pub __readers : :: std :: os :: raw :: c_uint , pub __writers : :: std :: os :: raw :: c_uint , pub __wrphase_futex : :: std :: os :: raw :: c_uint , pub __writers_futex : :: std :: os :: raw :: c_uint , pub __pad3 : :: std :: os :: raw :: c_uint , pub __pad4 : :: std :: os :: raw :: c_uint , pub __cur_writer : :: std :: os :: raw :: c_int , pub __shared : :: std :: os :: raw :: c_int , pub __pad1 : :: std :: os :: raw :: c_ulong , pub __pad2 : :: std :: os :: raw :: c_ulong , pub __flags : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_rwlock_arch_t"] [:: std :: mem :: size_of :: < __pthread_rwlock_arch_t > () - 56usize] ; ["Alignment of __pthread_rwlock_arch_t"] [:: std :: mem :: align_of :: < __pthread_rwlock_arch_t > () - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__readers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __readers) - 0usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers) - 4usize] ; ["Offset of field: __pthread_rwlock_arch_t::__wrphase_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __wrphase_futex) - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers_futex) - 12usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad3"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad3) - 16usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad4"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad4) - 20usize] ; ["Offset of field: __pthread_rwlock_arch_t::__cur_writer"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __cur_writer) - 24usize] ; ["Offset of field: __pthread_rwlock_arch_t::__shared"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __shared) - 28usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad1"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad1) - 32usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad2"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad2) - 40usize] ; ["Offset of field: __pthread_rwlock_arch_t::__flags"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __flags) - 48usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct __pthread_cond_s { pub __wseq : __atomic_wide_counter , pub __g1_start : __atomic_wide_counter , pub __g_size : [:: std :: os :: raw :: c_uint ; 2usize] , pub __g1_orig_size : :: std :: os :: raw :: c_uint , pub __wrefs : :: std :: os :: raw :: c_uint , pub __g_signals : [:: std :: os :: raw :: c_uint ; 2usize] , pub __unused_initialized_1 : :: std :: os :: raw :: c_uint , pub __unused_initialized_2 : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_cond_s"] [:: std :: mem :: size_of :: < __pthread_cond_s > () - 48usize] ; ["Alignment of __pthread_cond_s"] [:: std :: mem :: align_of :: < __pthread_cond_s > () - 8usize] ; ["Offset of field: __pthread_cond_s::__wseq"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wseq) - 0usize] ; ["Offset of field: __pthread_cond_s::__g1_start"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_start) - 8usize] ; ["Offset of field: __pthread_cond_s::__g_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_size) - 16usize] ; ["Offset of field: __pthread_cond_s::__g1_orig_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_orig_size) - 24usize] ; ["Offset of field: __pthread_cond_s::__wrefs"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wrefs) - 28usize] ; ["Offset of field: __pthread_cond_s::__g_signals"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_signals) - 32usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_1"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_1) - 40usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_2"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_2) - 44usize] ; } ; impl :: std :: fmt :: Debug for __pthread_cond_s { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__pthread_cond_s {{ __wseq: {:?}, __g1_start: {:?}, __g_size: {:?}, __g1_orig_size: {:?}, __wrefs: {:?}, __g_signals: {:?}, __unused_initialized_1: {:?}, __unused_initialized_2: {:?} }}" , self . __wseq , self . __g1_start , self . __g_size , self . __g1_orig_size , self . __wrefs , self . __g_signals , self . __unused_initialized_1 , self . __unused_initialized_2) } } pub type __tss_t = :: std :: os :: raw :: c_uint ; pub type __thrd_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __once_flag { pub __data : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __once_flag"] [:: std :: mem :: size_of :: < __once_flag > () - 4usize] ; ["Alignment of __once_flag"] [:: std :: mem :: align_of :: < __once_flag > () - 4usize] ; ["Offset of field: __once_flag::__data"] [:: std :: mem :: offset_of ! (__once_flag , __data) - 0usize] ; } ; pub type pthread_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutexattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutexattr_t"] [:: std :: mem :: size_of :: < pthread_mutexattr_t > () - 4usize] ; ["Alignment of pthread_mutexattr_t"] [:: std :: mem :: align_of :: < pthread_mutexattr_t > () - 4usize] ; ["Offset of field: pthread_mutexattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __size) - 0usize] ; ["Offset of field: pthread_mutexattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutexattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutexattr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_condattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_condattr_t"] [:: std :: mem :: size_of :: < pthread_condattr_t > () - 4usize] ; ["Alignment of pthread_condattr_t"] [:: std :: mem :: align_of :: < pthread_condattr_t > () - 4usize] ; ["Offset of field: pthread_condattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __size) - 0usize] ; ["Offset of field: pthread_condattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_condattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_condattr_t {{ union }}") } } pub type pthread_key_t = :: std :: os :: raw :: c_uint ; pub type pthread_once_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_attr_t { pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_attr_t"] [:: std :: mem :: size_of :: < pthread_attr_t > () - 56usize] ; ["Alignment of pthread_attr_t"] [:: std :: mem :: align_of :: < pthread_attr_t > () - 8usize] ; ["Offset of field: pthread_attr_t::__size"] [:: std :: mem :: offset_of ! (pthread_attr_t , __size) - 0usize] ; ["Offset of field: pthread_attr_t::__align"] [:: std :: mem :: offset_of ! (pthread_attr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_attr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_attr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutex_t { pub __data : __pthread_mutex_s , pub __size : [:: std :: os :: raw :: c_char ; 40usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutex_t"] [:: std :: mem :: size_of :: < pthread_mutex_t > () - 40usize] ; ["Alignment of pthread_mutex_t"] [:: std :: mem :: align_of :: < pthread_mutex_t > () - 8usize] ; ["Offset of field: pthread_mutex_t::__data"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __data) - 0usize] ; ["Offset of field: pthread_mutex_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __size) - 0usize] ; ["Offset of field: pthread_mutex_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutex_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutex_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_cond_t { pub __data : __pthread_cond_s , pub __size : [:: std :: os :: raw :: c_char ; 48usize] , pub __align : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_cond_t"] [:: std :: mem :: size_of :: < pthread_cond_t > () - 48usize] ; ["Alignment of pthread_cond_t"] [:: std :: mem :: align_of :: < pthread_cond_t > () - 8usize] ; ["Offset of field: pthread_cond_t::__data"] [:: std :: mem :: offset_of ! (pthread_cond_t , __data) - 0usize] ; ["Offset of field: pthread_cond_t::__size"] [:: std :: mem :: offset_of ! (pthread_cond_t , __size) - 0usize] ; ["Offset of field: pthread_cond_t::__align"] [:: std :: mem :: offset_of ! (pthread_cond_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_cond_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_cond_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlock_t { pub __data : __pthread_rwlock_arch_t , pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlock_t"] [:: std :: mem :: size_of :: < pthread_rwlock_t > () - 56usize] ; ["Alignment of pthread_rwlock_t"] [:: std :: mem :: align_of :: < pthread_rwlock_t > () - 8usize] ; ["Offset of field: pthread_rwlock_t::__data"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __data) - 0usize] ; ["Offset of field: pthread_rwlock_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __size) - 0usize] ; ["Offset of field: pthread_rwlock_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlock_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlock_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlockattr_t { pub __size : [:: std :: os :: raw :: c_char ; 8usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlockattr_t"] [:: std :: mem :: size_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Alignment of pthread_rwlockattr_t"] [:: std :: mem :: align_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Offset of field: pthread_rwlockattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __size) - 0usize] ; ["Offset of field: pthread_rwlockattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlockattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlockattr_t {{ union }}") } } pub type pthread_spinlock_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrier_t { pub __size : [:: std :: os :: raw :: c_char ; 32usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrier_t"] [:: std :: mem :: size_of :: < pthread_barrier_t > () - 32usize] ; ["Alignment of pthread_barrier_t"] [:: std :: mem :: align_of :: < pthread_barrier_t > () - 8usize] ; ["Offset of field: pthread_barrier_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __size) - 0usize] ; ["Offset of field: pthread_barrier_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrier_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrier_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrierattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrierattr_t"] [:: std :: mem :: size_of :: < pthread_barrierattr_t > () - 4usize] ; ["Alignment of pthread_barrierattr_t"] [:: std :: mem :: align_of :: < pthread_barrierattr_t > () - 4usize] ; ["Offset of field: pthread_barrierattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __size) - 0usize] ; ["Offset of field: pthread_barrierattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrierattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrierattr_t {{ union }}") } } unsafe extern "C" { pub fn random () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srandom (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn initstate (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn setstate (__statebuf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct random_data { pub fptr : * mut i32 , pub rptr : * mut i32 , pub state : * mut i32 , pub rand_type : :: std :: os :: raw :: c_int , pub rand_deg : :: std :: os :: raw :: c_int , pub rand_sep : :: std :: os :: raw :: c_int , pub end_ptr : * mut i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of random_data"] [:: std :: mem :: size_of :: < random_data > () - 48usize] ; ["Alignment of random_data"] [:: std :: mem :: align_of :: < random_data > () - 8usize] ; ["Offset of field: random_data::fptr"] [:: std :: mem :: offset_of ! (random_data , fptr) - 0usize] ; ["Offset of field: random_data::rptr"] [:: std :: mem :: offset_of ! (random_data , rptr) - 8usize] ; ["Offset of field: random_data::state"] [:: std :: mem :: offset_of ! (random_data , state) - 16usize] ; ["Offset of field: random_data::rand_type"] [:: std :: mem :: offset_of ! (random_data , rand_type) - 24usize] ; ["Offset of field: random_data::rand_deg"] [:: std :: mem :: offset_of ! (random_data , rand_deg) - 28usize] ; ["Offset of field: random_data::rand_sep"] [:: std :: mem :: offset_of ! (random_data , rand_sep) - 32usize] ; ["Offset of field: random_data::end_ptr"] [:: std :: mem :: offset_of ! (random_data , end_ptr) - 40usize] ; } ; unsafe extern "C" { pub fn random_r (__buf : * mut random_data , __result : * mut i32) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srandom_r (__seed : :: std :: os :: raw :: c_uint , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn initstate_r (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setstate_r (__statebuf : * mut :: std :: os :: raw :: c_char , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rand () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn rand_r (__seed : * mut :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn drand48 () -> f64 ; } unsafe extern "C" { pub fn erand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> f64 ; } unsafe extern "C" { pub fn lrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn nrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn mrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn jrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srand48 (__seedval : :: std :: os :: raw :: c_long) ; } unsafe extern "C" { pub fn seed48 (__seed16v : * mut :: std :: os :: raw :: c_ushort) -> * mut :: std :: os :: raw :: c_ushort ; } unsafe extern "C" { pub fn lcong48 (__param : * mut :: std :: os :: raw :: c_ushort) ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct drand48_data { pub __x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __old_x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __c : :: std :: os :: raw :: c_ushort , pub __init : :: std :: os :: raw :: c_ushort , pub __a : :: std :: os :: raw :: c_ulonglong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of drand48_data"] [:: std :: mem :: size_of :: < drand48_data > () - 24usize] ; ["Alignment of drand48_data"] [:: std :: mem :: align_of :: < drand48_data > () - 8usize] ; ["Offset of field: drand48_data::__x"] [:: std :: mem :: offset_of ! (drand48_data , __x) - 0usize] ; ["Offset of field: drand48_data::__old_x"] [:: std :: mem :: offset_of ! (drand48_data , __old_x) - 6usize] ; ["Offset of field: drand48_data::__c"] [:: std :: mem :: offset_of ! (drand48_data , __c) - 12usize] ; ["Offset of field: drand48_data::__init"] [:: std :: mem :: offset_of ! (drand48_data , __init) - 14usize] ; ["Offset of field: drand48_data::__a"] [:: std :: mem :: offset_of ! (drand48_data , __a) - 16usize] ; } ; unsafe extern "C" { pub fn drand48_r (__buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn erand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn nrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn jrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand48_r (__seedval : :: std :: os :: raw :: c_long , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn seed48_r (__seed16v : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lcong48_r (__param : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn arc4random () -> __uint32_t ; } unsafe extern "C" { pub fn arc4random_buf (__buf : * mut :: std :: os :: raw :: c_void , __size : usize) ; } unsafe extern "C" { pub fn arc4random_uniform (__upper_bound : __uint32_t) -> __uint32_t ; } unsafe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn calloc (__nmemb : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn free (__ptr : * mut :: std :: os :: raw :: c_void) ; } unsafe extern "C" { pub fn reallocarray (__ptr : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn alloca (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn valloc (__size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn posix_memalign (__memptr : * mut * mut :: std :: os :: raw :: c_void , __alignment : usize , __size : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn aligned_alloc (__alignment : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn abort () -> ! ; } unsafe extern "C" { pub fn atexit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn at_quick_exit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn on_exit (__func : :: std :: option :: Option < unsafe extern "C" fn (__status : :: std :: os :: raw :: c_int , __arg : * mut :: std :: os :: raw :: c_void) > , __arg : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn quick_exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn _Exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn getenv (__name : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn putenv (__string : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setenv (__name : * const :: std :: os :: raw :: c_char , __value : * const :: std :: os :: raw :: c_char , __replace : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn unsetenv (__name : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearenv () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mktemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn mkstemp (__template : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkstemps (__template : * mut :: std :: os :: raw :: c_char , __suffixlen : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkdtemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn system (__command : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn realpath (__name : * const :: std :: os :: raw :: c_char , __resolved : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } pub type __compar_fn_t = :: std :: option :: Option < unsafe extern "C" fn (arg1 : * const :: std :: os :: raw :: c_void , arg2 : * const :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; unsafe extern "C" { pub fn bsearch (__key : * const :: std :: os :: raw :: c_void , __base : * const :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn qsort (__base : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) ; } unsafe extern "C" { pub fn abs (__x : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn labs (__x : :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn llabs (__x : :: std :: os :: raw :: c_longlong) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn div (__numer : :: std :: os :: raw :: c_int , __denom : :: std :: os :: raw :: c_int) -> div_t ; } unsafe extern "C" { pub fn ldiv (__numer : :: std :: os :: raw :: c_long , __denom : :: std :: os :: raw :: c_long) -> ldiv_t ; } unsafe extern "C" { pub fn lldiv (__numer : :: std :: os :: raw :: c_longlong , __denom : :: std :: os :: raw :: c_longlong) -> lldiv_t ; } unsafe extern "C" { pub fn ecvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn gcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qecvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qfcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qgcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn ecvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fcvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qecvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qfcvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mblen (__s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbtowc (__pwc : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn wctomb (__s : * mut :: std :: os :: raw :: c_char , __wchar : wchar_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbstowcs (__pwcs : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> usize ; } unsafe extern "C" { pub fn wcstombs (__s : * mut :: std :: os :: raw :: c_char , __pwcs : * const wchar_t , __n : usize) -> usize ; } unsafe extern "C" { pub fn rpmatch (__response : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getsubopt (__optionp : * mut * mut :: std :: os :: raw :: c_char , __tokens : * const * mut :: std :: os :: raw :: c_char , __valuep : * mut * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getloadavg (__loadavg : * mut f64 , __nelem : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } # [repr (C)] # [derive (Copy , Clone)] pub struct __mbstate_t { pub __count : :: std :: os :: raw :: c_int , pub __value : __mbstate_t__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union __mbstate_t__bindgen_ty_1 { pub __wch : :: std :: os :: raw :: c_uint , pub __wchb : [:: std :: os :: raw :: c_char ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: size_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Alignment of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: align_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wch"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wch) - 0usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wchb"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wchb) - 0usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t"] [:: std :: mem :: size_of :: < __mbstate_t > () - 8usize] ; ["Alignment of __mbstate_t"] [:: std :: mem :: align_of :: < __mbstate_t > () - 4usize] ; ["Offset of field: __mbstate_t::__count"] [:: std :: mem :: offset_of ! (__mbstate_t , __count) - 0usize] ; ["Offset of field: __mbstate_t::__value"] [:: std :: mem :: offset_of ! (__mbstate_t , __value) - 4usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t {{ __count: {:?}, __value: {:?} }}" , self . __count , self . __value) } } # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos_t { pub __pos : __off_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos_t"] [:: std :: mem :: size_of :: < _G_fpos_t > () - 16usize] ; ["Alignment of _G_fpos_t"] [:: std :: mem :: align_of :: < _G_fpos_t > () - 8usize] ; ["Offset of field: _G_fpos_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos_t , __pos) - 0usize] ; ["Offset of field: _G_fpos_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos_t = _G_fpos_t ; # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos64_t { pub __pos : __off64_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos64_t"] [:: std :: mem :: size_of :: < _G_fpos64_t > () - 16usize] ; ["Alignment of _G_fpos64_t"] [:: std :: mem :: align_of :: < _G_fpos64_t > () - 8usize] ; ["Offset of field: _G_fpos64_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __pos) - 0usize] ; ["Offset of field: _G_fpos64_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos64_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos64_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos64_t = _G_fpos64_t ; pub type __FILE = _IO_FILE ; pub type FILE = _IO_FILE ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_marker { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_codecvt { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_wide_data { _unused : [u8 ; 0] , } pub type _IO_lock_t = :: std :: os :: raw :: c_void ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_FILE { pub _flags : :: std :: os :: raw :: c_int , pub _IO_read_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_read_end : * mut :: std :: os :: raw :: c_char , pub _IO_read_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_write_end : * mut :: std :: os :: raw :: c_char , pub _IO_buf_base : * mut :: std :: os :: raw :: c_char , pub _IO_buf_end : * mut :: std :: os :: raw :: c_char , pub _IO_save_base : * mut :: std :: os :: raw :: c_char , pub _IO_backup_base : * mut :: std :: os :: raw :: c_char , pub _IO_save_end : * mut :: std :: os :: raw :: c_char , pub _markers : * mut _IO_marker , pub _chain : * mut _IO_FILE , pub _fileno : :: std :: os :: raw :: c_int , pub _bitfield_align_1 : [u32 ; 0] , pub _bitfield_1 : __BindgenBitfieldUnit < [u8 ; 3usize] > , pub _short_backupbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _old_offset : __off_t , pub _cur_column : :: std :: os :: raw :: c_ushort , pub _vtable_offset : :: std :: os :: raw :: c_schar , pub _shortbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _lock : * mut _IO_lock_t , pub _offset : __off64_t , pub _codecvt : * mut _IO_codecvt , pub _wide_data : * mut _IO_wide_data , pub _freeres_list : * mut _IO_FILE , pub _freeres_buf : * mut :: std :: os :: raw :: c_void , pub _prevchain : * mut * mut _IO_FILE , pub _mode : :: std :: os :: raw :: c_int , pub _unused3 : :: std :: os :: raw :: c_int , pub _total_written : __uint64_t , pub _unused2 : [:: std :: os :: raw :: c_char ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_FILE"] [:: std :: mem :: size_of :: < _IO_FILE > () - 216usize] ; ["Alignment of _IO_FILE"] [:: std :: mem :: align_of :: < _IO_FILE > () - 8usize] ; ["Offset of field: _IO_FILE::_flags"] [:: std :: mem :: offset_of ! (_IO_FILE , _flags) - 0usize] ; ["Offset of field: _IO_FILE::_IO_read_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_ptr) - 8usize] ; ["Offset of field: _IO_FILE::_IO_read_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_end) - 16usize] ; ["Offset of field: _IO_FILE::_IO_read_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_base) - 24usize] ; ["Offset of field: _IO_FILE::_IO_write_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_base) - 32usize] ; ["Offset of field: _IO_FILE::_IO_write_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_ptr) - 40usize] ; ["Offset of field: _IO_FILE::_IO_write_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_end) - 48usize] ; ["Offset of field: _IO_FILE::_IO_buf_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_base) - 56usize] ; ["Offset of field: _IO_FILE::_IO_buf_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_end) - 64usize] ; ["Offset of field: _IO_FILE::_IO_save_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_base) - 72usize] ; ["Offset of field: _IO_FILE::_IO_backup_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_backup_base) - 80usize] ; ["Offset of field: _IO_FILE::_IO_save_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_end) - 88usize] ; ["Offset of field: _IO_FILE::_markers"] [:: std :: mem :: offset_of ! (_IO_FILE , _markers) - 96usize] ; ["Offset of field: _IO_FILE::_chain"] [:: std :: mem :: offset_of ! (_IO_FILE , _chain) - 104usize] ; ["Offset of field: _IO_FILE::_fileno"] [:: std :: mem :: offset_of ! (_IO_FILE , _fileno) - 112usize] ; ["Offset of field: _IO_FILE::_short_backupbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _short_backupbuf) - 119usize] ; ["Offset of field: _IO_FILE::_old_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _old_offset) - 120usize] ; ["Offset of field: _IO_FILE::_cur_column"] [:: std :: mem :: offset_of ! (_IO_FILE , _cur_column) - 128usize] ; ["Offset of field: _IO_FILE::_vtable_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _vtable_offset) - 130usize] ; ["Offset of field: _IO_FILE::_shortbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _shortbuf) - 131usize] ; ["Offset of field: _IO_FILE::_lock"] [:: std :: mem :: offset_of ! (_IO_FILE , _lock) - 136usize] ; ["Offset of field: _IO_FILE::_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _offset) - 144usize] ; ["Offset of field: _IO_FILE::_codecvt"] [:: std :: mem :: offset_of ! (_IO_FILE , _codecvt) - 152usize] ; ["Offset of field: _IO_FILE::_wide_data"] [:: std :: mem :: offset_of ! (_IO_FILE , _wide_data) - 160usize] ; ["Offset of field: _IO_FILE::_freeres_list"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_list) - 168usize] ; ["Offset of field: _IO_FILE::_freeres_buf"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_buf) - 176usize] ; ["Offset of field: _IO_FILE::_prevchain"] [:: std :: mem :: offset_of ! (_IO_FILE , _prevchain) - 184usize] ; ["Offset of field: _IO_FILE::_mode"] [:: std :: mem :: offset_of ! (_IO_FILE , _mode) - 192usize] ; ["Offset of field: _IO_FILE::_unused3"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused3) - 196usize] ; ["Offset of field: _IO_FILE::_total_written"] [:: std :: mem :: offset_of ! (_IO_FILE , _total_written) - 200usize] ; ["Offset of field: _IO_FILE::_unused2"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused2) - 208usize] ; } ; impl _IO_FILE { # [inline] pub fn _flags2 (& self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set__flags2 (& mut self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; self . _bitfield_1 . set (0usize , 24u8 , val as u64) } } # [inline] pub unsafe fn _flags2_raw (this : * const Self) -> :: std :: os :: raw :: c_int { unsafe { u32::cast_signed (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } } # [inline] pub unsafe fn set__flags2_raw (this : * mut Self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_set (:: std :: ptr :: addr_of_mut ! ((* this) . _bitfield_1) , 0usize , 24u8 , val as u64 ,) } } # [inline] pub fn new_bitfield_1 (_flags2 : :: std :: os :: raw :: c_int) -> __BindgenBitfieldUnit < [u8 ; 3usize] > { let mut __bindgen_bitfield_unit : __BindgenBitfieldUnit < [u8 ; 3usize] > = Default :: default () ; __bindgen_bitfield_unit . set (0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_unit } } pub type cookie_read_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * mut :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_write_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * const :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_seek_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __pos : * mut __off64_t , __w : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int > ; pub type cookie_close_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_cookie_io_functions_t { pub read : cookie_read_function_t , pub write : cookie_write_function_t , pub seek : cookie_seek_function_t , pub close : cookie_close_function_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_cookie_io_functions_t"] [:: std :: mem :: size_of :: < _IO_cookie_io_functions_t > () - 32usize] ; ["Alignment of _IO_cookie_io_functions_t"] [:: std :: mem :: align_of :: < _IO_cookie_io_functions_t > () - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::read"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , read) - 0usize] ; ["Offset of field: _IO_cookie_io_functions_t::write"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , write) - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::seek"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , seek) - 16usize] ; ["Offset of field: _IO_cookie_io_functions_t::close"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , close) - 24usize] ; } ; pub type cookie_io_functions_t = _IO_cookie_io_functions_t ; pub type fpos_t = __fpos_t ; unsafe extern "C" { pub static mut stdin : * mut FILE ; } unsafe extern "C" { pub static mut stdout : * mut FILE ; } unsafe extern "C" { pub static mut stderr : * mut FILE ; } unsafe extern "C" { pub fn remove (__filename : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rename (__old : * const :: std :: os :: raw :: c_char , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn renameat (__oldfd : :: std :: os :: raw :: c_int , __old : * const :: std :: os :: raw :: c_char , __newfd : :: std :: os :: raw :: c_int , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn tmpfile () -> * mut FILE ; } unsafe extern "C" { pub fn tmpnam (arg1 : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tmpnam_r (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tempnam (__dir : * const :: std :: os :: raw :: c_char , __pfx : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fflush (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fflush_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn freopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> * mut FILE ; } unsafe extern "C" { pub fn fdopen (__fd : :: std :: os :: raw :: c_int , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn fopencookie (__magic_cookie : * mut :: std :: os :: raw :: c_void , __modes : * const :: std :: os :: raw :: c_char , __io_funcs : cookie_io_functions_t) -> * mut FILE ; } unsafe extern "C" { pub fn fmemopen (__s : * mut :: std :: os :: raw :: c_void , __len : usize , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn open_memstream (__bufloc : * mut * mut :: std :: os :: raw :: c_char , __sizeloc : * mut usize) -> * mut FILE ; } unsafe extern "C" { pub fn setbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn setvbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __modes : :: std :: os :: raw :: c_int , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setbuffer (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __size : usize) ; } unsafe extern "C" { pub fn setlinebuf (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fprintf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn printf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfprintf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vprintf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn snprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsnprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vasprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __f : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vdprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn dprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fscanf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn scanf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_fscanf"] pub fn fscanf1 (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_scanf"] pub fn scanf1 (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_sscanf"] pub fn sscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfscanf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vscanf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vfscanf"] pub fn vfscanf1 (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vscanf"] pub fn vscanf1 (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vsscanf"] pub fn vsscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar_unlocked () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar_unlocked (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getw (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putw (__w : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgets (__s : * mut :: std :: os :: raw :: c_char , __n : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn __getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getline (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn fputs (__s : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn puts (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ungetc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fread (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __stream : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fwrite (__ptr : * const :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __s : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fread_unlocked (__ptr : * mut :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fwrite_unlocked (__ptr : * const :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fseek (__stream : * mut FILE , __off : :: std :: os :: raw :: c_long , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftell (__stream : * mut FILE) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn rewind (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fseeko (__stream : * mut FILE , __off : __off_t , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftello (__stream : * mut FILE) -> __off_t ; } unsafe extern "C" { pub fn fgetpos (__stream : * mut FILE , __pos : * mut fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fsetpos (__stream : * mut FILE , __pos : * const fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr_unlocked (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn perror (__s : * const :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn fileno (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fileno_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn popen (__command : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn ctermid (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn flockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn ftrylockfile (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn funlockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn __uflow (arg1 : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __overflow (arg1 : * mut FILE , arg2 : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } pub type int_least8_t = __int_least8_t ; pub type int_least16_t = __int_least16_t ; pub type int_least32_t = __int_least32_t ; pub type int_least64_t = __int_least64_t ; pub type uint_least8_t = __uint_least8_t ; pub type uint_least16_t = __uint_least16_t ; pub type uint_least32_t = __uint_least32_t ; pub type uint_least64_t = __uint_least64_t ; pub type int_fast8_t = :: std :: os :: raw :: c_schar ; pub type int_fast16_t = :: std :: os :: raw :: c_long ; pub type int_fast32_t = :: std :: os :: raw :: c_long ; pub type int_fast64_t = :: std :: os :: raw :: c_long ; pub type uint_fast8_t = :: std :: os :: raw :: c_uchar ; pub type uint_fast16_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast32_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast64_t = :: std :: os :: raw :: c_ulong ; pub type intmax_t = __intmax_t ; pub type uintmax_t = __uintmax_t ; pub type __gwchar_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct imaxdiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of imaxdiv_t"] [:: std :: mem :: size_of :: < imaxdiv_t > () - 16usize] ; ["Alignment of imaxdiv_t"] [:: std :: mem :: align_of :: < imaxdiv_t > () - 8usize] ; ["Offset of field: imaxdiv_t::quot"] [:: std :: mem :: offset_of ! (imaxdiv_t , quot) - 0usize] ; ["Offset of field: imaxdiv_t::rem"] [:: std :: mem :: offset_of ! (imaxdiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn imaxabs (__n : intmax_t) -> intmax_t ; } unsafe extern "C" { pub fn imaxdiv (__numer : intmax_t , __denom : intmax_t) -> imaxdiv_t ; } unsafe extern "C" { pub fn strtoimax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn strtoumax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } unsafe extern "C" { pub fn wcstoimax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn wcstoumax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } pub type csh = usize ; # [repr (u32)] # [doc = " Architecture type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_arch { # [doc = "< ARM architecture (including Thumb, Thumb-2)"] CS_ARCH_ARM = 0 , # [doc = "< ARM-64, also called AArch64"] CS_ARCH_ARM64 = 1 , # [doc = "< Mips architecture"] CS_ARCH_MIPS = 2 , # [doc = "< X86 architecture (including x86 & x86-64)"] CS_ARCH_X86 = 3 , # [doc = "< PowerPC architecture"] CS_ARCH_PPC = 4 , # [doc = "< Sparc architecture"] CS_ARCH_SPARC = 5 , # [doc = "< SystemZ architecture"] CS_ARCH_SYSZ = 6 , # [doc = "< XCore architecture"] CS_ARCH_XCORE = 7 , # [doc = "< 68K architecture"] CS_ARCH_M68K = 8 , # [doc = "< TMS320C64x architecture"] CS_ARCH_TMS320C64X = 9 , # [doc = "< 680X architecture"] CS_ARCH_M680X = 10 , # [doc = "< Ethereum architecture"] CS_ARCH_EVM = 11 , # [doc = "< MOS65XX architecture (including MOS6502)"] CS_ARCH_MOS65XX = 12 , # [doc = "< WebAssembly architecture"] CS_ARCH_WASM = 13 , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] CS_ARCH_BPF = 14 , # [doc = "< RISCV architecture"] CS_ARCH_RISCV = 15 , # [doc = "< SH architecture"] CS_ARCH_SH = 16 , # [doc = "< TriCore architecture"] CS_ARCH_TRICORE = 17 , CS_ARCH_MAX = 18 , CS_ARCH_ALL = 65535 , } # [doc = "< little-endian mode (default mode)"] pub const cs_mode_CS_MODE_LITTLE_ENDIAN : cs_mode = 0 ; # [doc = "< 32-bit ARM"] pub const cs_mode_CS_MODE_ARM : cs_mode = 0 ; # [doc = "< 16-bit mode (X86)"] pub const cs_mode_CS_MODE_16 : cs_mode = 2 ; # [doc = "< 32-bit mode (X86)"] pub const cs_mode_CS_MODE_32 : cs_mode = 4 ; # [doc = "< 64-bit mode (X86, PPC)"] pub const cs_mode_CS_MODE_64 : cs_mode = 8 ; # [doc = "< ARM's Thumb mode, including Thumb-2"] pub const cs_mode_CS_MODE_THUMB : cs_mode = 16 ; # [doc = "< ARM's Cortex-M series"] pub const cs_mode_CS_MODE_MCLASS : cs_mode = 32 ; # [doc = "< ARMv8 A32 encodings for ARM"] pub const cs_mode_CS_MODE_V8 : cs_mode = 64 ; # [doc = "< MicroMips mode (MIPS)"] pub const cs_mode_CS_MODE_MICRO : cs_mode = 16 ; # [doc = "< Mips III ISA"] pub const cs_mode_CS_MODE_MIPS3 : cs_mode = 32 ; # [doc = "< Mips32r6 ISA"] pub const cs_mode_CS_MODE_MIPS32R6 : cs_mode = 64 ; # [doc = "< Mips II ISA"] pub const cs_mode_CS_MODE_MIPS2 : cs_mode = 128 ; # [doc = "< SparcV9 mode (Sparc)"] pub const cs_mode_CS_MODE_V9 : cs_mode = 16 ; # [doc = "< Quad Processing eXtensions mode (PPC)"] pub const cs_mode_CS_MODE_QPX : cs_mode = 16 ; # [doc = "< Signal Processing Engine mode (PPC)"] pub const cs_mode_CS_MODE_SPE : cs_mode = 32 ; # [doc = "< Book-E mode (PPC)"] pub const cs_mode_CS_MODE_BOOKE : cs_mode = 64 ; # [doc = "< Paired-singles mode (PPC)"] pub const cs_mode_CS_MODE_PS : cs_mode = 128 ; # [doc = "< M68K 68000 mode"] pub const cs_mode_CS_MODE_M68K_000 : cs_mode = 2 ; # [doc = "< M68K 68010 mode"] pub const cs_mode_CS_MODE_M68K_010 : cs_mode = 4 ; # [doc = "< M68K 68020 mode"] pub const cs_mode_CS_MODE_M68K_020 : cs_mode = 8 ; # [doc = "< M68K 68030 mode"] pub const cs_mode_CS_MODE_M68K_030 : cs_mode = 16 ; # [doc = "< M68K 68040 mode"] pub const cs_mode_CS_MODE_M68K_040 : cs_mode = 32 ; # [doc = "< M68K 68060 mode"] pub const cs_mode_CS_MODE_M68K_060 : cs_mode = 64 ; # [doc = "< big-endian mode"] pub const cs_mode_CS_MODE_BIG_ENDIAN : cs_mode = 2147483648 ; # [doc = "< Mips32 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS32 : cs_mode = 4 ; # [doc = "< Mips64 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS64 : cs_mode = 8 ; # [doc = "< M680X Hitachi 6301,6303 mode"] pub const cs_mode_CS_MODE_M680X_6301 : cs_mode = 2 ; # [doc = "< M680X Hitachi 6309 mode"] pub const cs_mode_CS_MODE_M680X_6309 : cs_mode = 4 ; # [doc = "< M680X Motorola 6800,6802 mode"] pub const cs_mode_CS_MODE_M680X_6800 : cs_mode = 8 ; # [doc = "< M680X Motorola 6801,6803 mode"] pub const cs_mode_CS_MODE_M680X_6801 : cs_mode = 16 ; # [doc = "< M680X Motorola/Freescale 6805 mode"] pub const cs_mode_CS_MODE_M680X_6805 : cs_mode = 32 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"] pub const cs_mode_CS_MODE_M680X_6808 : cs_mode = 64 ; # [doc = "< M680X Motorola 6809 mode"] pub const cs_mode_CS_MODE_M680X_6809 : cs_mode = 128 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"] pub const cs_mode_CS_MODE_M680X_6811 : cs_mode = 256 ; # [doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"] pub const cs_mode_CS_MODE_M680X_CPU12 : cs_mode = 512 ; # [doc = "< M680X Freescale/NXP HCS08 mode"] pub const cs_mode_CS_MODE_M680X_HCS08 : cs_mode = 1024 ; # [doc = "< Classic BPF mode (default)"] pub const cs_mode_CS_MODE_BPF_CLASSIC : cs_mode = 0 ; # [doc = "< Extended BPF mode"] pub const cs_mode_CS_MODE_BPF_EXTENDED : cs_mode = 1 ; # [doc = "< RISCV RV32G"] pub const cs_mode_CS_MODE_RISCV32 : cs_mode = 1 ; # [doc = "< RISCV RV64G"] pub const cs_mode_CS_MODE_RISCV64 : cs_mode = 2 ; # [doc = "< RISCV compressed instructure mode"] pub const cs_mode_CS_MODE_RISCVC : cs_mode = 4 ; # [doc = "< MOS65XXX MOS 6502"] pub const cs_mode_CS_MODE_MOS65XX_6502 : cs_mode = 2 ; # [doc = "< MOS65XXX WDC 65c02"] pub const cs_mode_CS_MODE_MOS65XX_65C02 : cs_mode = 4 ; # [doc = "< MOS65XXX WDC W65c02"] pub const cs_mode_CS_MODE_MOS65XX_W65C02 : cs_mode = 8 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m/x"] pub const cs_mode_CS_MODE_MOS65XX_65816 : cs_mode = 16 ; # [doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_M : cs_mode = 32 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_X : cs_mode = 64 ; pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_MX : cs_mode = 96 ; # [doc = "< SH2"] pub const cs_mode_CS_MODE_SH2 : cs_mode = 2 ; # [doc = "< SH2A"] pub const cs_mode_CS_MODE_SH2A : cs_mode = 4 ; # [doc = "< SH3"] pub const cs_mode_CS_MODE_SH3 : cs_mode = 8 ; # [doc = "< SH4"] pub const cs_mode_CS_MODE_SH4 : cs_mode = 16 ; # [doc = "< SH4A"] pub const cs_mode_CS_MODE_SH4A : cs_mode = 32 ; # [doc = "< w/ FPU"] pub const cs_mode_CS_MODE_SHFPU : cs_mode = 64 ; # [doc = "< w/ DSP"] pub const cs_mode_CS_MODE_SHDSP : cs_mode = 128 ; # [doc = "< Tricore 1.1"] pub const cs_mode_CS_MODE_TRICORE_110 : cs_mode = 2 ; # [doc = "< Tricore 1.2"] pub const cs_mode_CS_MODE_TRICORE_120 : cs_mode = 4 ; # [doc = "< Tricore 1.3"] pub const cs_mode_CS_MODE_TRICORE_130 : cs_mode = 8 ; # [doc = "< Tricore 1.3.1"] pub const cs_mode_CS_MODE_TRICORE_131 : cs_mode = 16 ; # [doc = "< Tricore 1.6"] pub const cs_mode_CS_MODE_TRICORE_160 : cs_mode = 32 ; # [doc = "< Tricore 1.6.1"] pub const cs_mode_CS_MODE_TRICORE_161 : cs_mode = 64 ; # [doc = "< Tricore 1.6.2"] pub const cs_mode_CS_MODE_TRICORE_162 : cs_mode = 128 ; # [doc = " Mode type"] pub type cs_mode = :: std :: os :: raw :: c_uint ; pub type cs_malloc_t = :: std :: option :: Option < unsafe extern "C" fn (size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_calloc_t = :: std :: option :: Option < unsafe extern "C" fn (nmemb : usize , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_realloc_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_free_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void) > ; pub type cs_vsnprintf_t = :: std :: option :: Option < unsafe extern "C" fn (str_ : * mut :: std :: os :: raw :: c_char , size : usize , format : * const :: std :: os :: raw :: c_char , ap : * mut __va_list_tag) -> :: std :: os :: raw :: c_int > ; # [doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mem { pub malloc : cs_malloc_t , pub calloc : cs_calloc_t , pub realloc : cs_realloc_t , pub free : cs_free_t , pub vsnprintf : cs_vsnprintf_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mem"] [:: std :: mem :: size_of :: < cs_opt_mem > () - 40usize] ; ["Alignment of cs_opt_mem"] [:: std :: mem :: align_of :: < cs_opt_mem > () - 8usize] ; ["Offset of field: cs_opt_mem::malloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , malloc) - 0usize] ; ["Offset of field: cs_opt_mem::calloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , calloc) - 8usize] ; ["Offset of field: cs_opt_mem::realloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , realloc) - 16usize] ; ["Offset of field: cs_opt_mem::free"] [:: std :: mem :: offset_of ! (cs_opt_mem , free) - 24usize] ; ["Offset of field: cs_opt_mem::vsnprintf"] [:: std :: mem :: offset_of ! (cs_opt_mem , vsnprintf) - 32usize] ; } ; # [doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mnem { # [doc = " ID of instruction to be customized."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Customized instruction mnemonic."] pub mnemonic : * const :: std :: os :: raw :: c_char , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mnem"] [:: std :: mem :: size_of :: < cs_opt_mnem > () - 16usize] ; ["Alignment of cs_opt_mnem"] [:: std :: mem :: align_of :: < cs_opt_mnem > () - 8usize] ; ["Offset of field: cs_opt_mnem::id"] [:: std :: mem :: offset_of ! (cs_opt_mnem , id) - 0usize] ; ["Offset of field: cs_opt_mnem::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_mnem , mnemonic) - 8usize] ; } ; # [repr (u32)] # [doc = " Runtime option for the disassembled engine"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_type { # [doc = "< No option specified"] CS_OPT_INVALID = 0 , # [doc = "< Assembly output syntax"] CS_OPT_SYNTAX = 1 , # [doc = "< Break down instruction structure into details"] CS_OPT_DETAIL = 2 , # [doc = "< Change engine's mode at run-time"] CS_OPT_MODE = 3 , # [doc = "< User-defined dynamic memory related functions"] CS_OPT_MEM = 4 , # [doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."] CS_OPT_SKIPDATA = 5 , # [doc = "< Setup user-defined function for SKIPDATA option"] CS_OPT_SKIPDATA_SETUP = 6 , # [doc = "< Customize instruction mnemonic"] CS_OPT_MNEMONIC = 7 , # [doc = "< print immediate operands in unsigned form"] CS_OPT_UNSIGNED = 8 , # [doc = "< ARM, prints branch immediates without offset."] CS_OPT_NO_BRANCH_OFFSET = 9 , } impl cs_opt_value { pub const CS_OPT_SYNTAX_DEFAULT : cs_opt_value = cs_opt_value :: CS_OPT_OFF ; } impl cs_opt_value { pub const CS_OPT_SYNTAX_NOREGNAME : cs_opt_value = cs_opt_value :: CS_OPT_ON ; } # [repr (u32)] # [doc = " Runtime option value (associated with option type above)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_value { # [doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."] CS_OPT_OFF = 0 , # [doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."] CS_OPT_ON = 3 , # [doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_INTEL = 1 , # [doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_ATT = 2 , # [doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_MASM = 4 , # [doc = "< MOS65XX use $ as hex prefix"] CS_OPT_SYNTAX_MOTOROLA = 5 , } # [repr (u32)] # [doc = " Common instruction operand types - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_op_type { # [doc = "< uninitialized/invalid operand."] CS_OP_INVALID = 0 , # [doc = "< Register operand."] CS_OP_REG = 1 , # [doc = "< Immediate operand."] CS_OP_IMM = 2 , # [doc = "< Memory operand. Can be ORed with another operand type."] CS_OP_MEM = 3 , # [doc = "< Floating-Point operand."] CS_OP_FP = 4 , } # [repr (u32)] # [doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_ac_type { # [doc = "< Uninitialized/invalid access type."] CS_AC_INVALID = 0 , # [doc = "< Operand read from memory or register."] CS_AC_READ = 1 , # [doc = "< Operand write to memory or register."] CS_AC_WRITE = 2 , } # [repr (u32)] # [doc = " Common instruction groups - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_group_type { # [doc = "< uninitialized/invalid group."] CS_GRP_INVALID = 0 , # [doc = "< all jump instructions (conditional+direct+indirect jumps)"] CS_GRP_JUMP = 1 , # [doc = "< all call instructions"] CS_GRP_CALL = 2 , # [doc = "< all return instructions"] CS_GRP_RET = 3 , # [doc = "< all interrupt instructions (int+syscall)"] CS_GRP_INT = 4 , # [doc = "< all interrupt return instructions"] CS_GRP_IRET = 5 , # [doc = "< all privileged instructions"] CS_GRP_PRIVILEGE = 6 , # [doc = "< all relative branching instructions"] CS_GRP_BRANCH_RELATIVE = 7 , } # [doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."] pub type cs_skipdata_cb_t = :: std :: option :: Option < unsafe extern "C" fn (code : * const u8 , code_size : usize , offset : usize , user_data : * mut :: std :: os :: raw :: c_void) -> usize > ; # [doc = " User-customized setup for SKIPDATA option"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_skipdata { # [doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."] pub mnemonic : * const :: std :: os :: raw :: c_char , # [doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes.\n TriCore: 2 bytes."] pub callback : cs_skipdata_cb_t , # [doc = " User-defined data to be passed to @callback function pointer."] pub user_data : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_skipdata"] [:: std :: mem :: size_of :: < cs_opt_skipdata > () - 24usize] ; ["Alignment of cs_opt_skipdata"] [:: std :: mem :: align_of :: < cs_opt_skipdata > () - 8usize] ; ["Offset of field: cs_opt_skipdata::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , mnemonic) - 0usize] ; ["Offset of field: cs_opt_skipdata::callback"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , callback) - 8usize] ; ["Offset of field: cs_opt_skipdata::user_data"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , user_data) - 16usize] ; } ; # [repr (u32)] # [doc = " ARM shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_shifter { ARM_SFT_INVALID = 0 , # [doc = "< shift with immediate const"] ARM_SFT_ASR = 1 , # [doc = "< shift with immediate const"] ARM_SFT_LSL = 2 , # [doc = "< shift with immediate const"] ARM_SFT_LSR = 3 , # [doc = "< shift with immediate const"] ARM_SFT_ROR = 4 , # [doc = "< shift with immediate const"] ARM_SFT_RRX = 5 , # [doc = "< shift with register"] ARM_SFT_ASR_REG = 6 , # [doc = "< shift with register"] ARM_SFT_LSL_REG = 7 , # [doc = "< shift with register"] ARM_SFT_LSR_REG = 8 , # [doc = "< shift with register"] ARM_SFT_ROR_REG = 9 , # [doc = "< shift with register"] ARM_SFT_RRX_REG = 10 , } # [repr (u32)] # [doc = " ARM condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cc { ARM_CC_INVALID = 0 , # [doc = "< Equal                      Equal"] ARM_CC_EQ = 1 , # [doc = "< Not equal                  Not equal, or unordered"] ARM_CC_NE = 2 , # [doc = "< Carry set                  >, ==, or unordered"] ARM_CC_HS = 3 , # [doc = "< Carry clear                Less than"] ARM_CC_LO = 4 , # [doc = "< Minus, negative            Less than"] ARM_CC_MI = 5 , # [doc = "< Plus, positive or zero     >, ==, or unordered"] ARM_CC_PL = 6 , # [doc = "< Overflow                   Unordered"] ARM_CC_VS = 7 , # [doc = "< No overflow                Not unordered"] ARM_CC_VC = 8 , # [doc = "< Unsigned higher            Greater than, or unordered"] ARM_CC_HI = 9 , # [doc = "< Unsigned lower or same     Less than or equal"] ARM_CC_LS = 10 , # [doc = "< Greater than or equal      Greater than or equal"] ARM_CC_GE = 11 , # [doc = "< Less than                  Less than, or unordered"] ARM_CC_LT = 12 , # [doc = "< Greater than               Greater than"] ARM_CC_GT = 13 , # [doc = "< Less than or equal         <, ==, or unordered"] ARM_CC_LE = 14 , # [doc = "< Always (unconditional)     Always (unconditional)"] ARM_CC_AL = 15 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_sysreg { # [doc = " Special registers for MSR"] ARM_SYSREG_INVALID = 0 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_C = 1 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_X = 2 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_S = 4 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_F = 8 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_C = 16 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_X = 32 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_S = 64 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_F = 128 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR = 256 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_G = 257 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQ = 258 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQG = 259 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR = 260 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_G = 261 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQG = 262 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQ = 263 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR = 264 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_G = 265 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQG = 266 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQ = 267 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR = 268 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_G = 269 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQG = 270 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQ = 271 , # [doc = " Special registers for MSR"] ARM_SYSREG_IPSR = 272 , # [doc = " Special registers for MSR"] ARM_SYSREG_EPSR = 273 , # [doc = " Special registers for MSR"] ARM_SYSREG_IEPSR = 274 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP = 275 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP = 276 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK = 277 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI = 278 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_MAX = 279 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK = 280 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL = 281 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM = 282 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM = 283 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP_NS = 284 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP_NS = 285 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM_NS = 286 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM_NS = 287 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK_NS = 288 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_NS = 289 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK_NS = 290 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL_NS = 291 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_NS = 292 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_USR = 293 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_USR = 294 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_USR = 295 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_USR = 296 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_USR = 297 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_USR = 298 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_USR = 299 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_FIQ = 300 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_FIQ = 301 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_FIQ = 302 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_FIQ = 303 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_FIQ = 304 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_FIQ = 305 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_FIQ = 306 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_IRQ = 307 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_IRQ = 308 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_SVC = 309 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_SVC = 310 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_ABT = 311 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_ABT = 312 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_UND = 313 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_UND = 314 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_MON = 315 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_MON = 316 , # [doc = " Special registers for MSR"] ARM_SYSREG_ELR_HYP = 317 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_HYP = 318 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_FIQ = 319 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_IRQ = 320 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_SVC = 321 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_ABT = 322 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_UND = 323 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_MON = 324 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_HYP = 325 , } # [repr (u32)] # [doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_mem_barrier { ARM_MB_INVALID = 0 , ARM_MB_RESERVED_0 = 1 , ARM_MB_OSHLD = 2 , ARM_MB_OSHST = 3 , ARM_MB_OSH = 4 , ARM_MB_RESERVED_4 = 5 , ARM_MB_NSHLD = 6 , ARM_MB_NSHST = 7 , ARM_MB_NSH = 8 , ARM_MB_RESERVED_8 = 9 , ARM_MB_ISHLD = 10 , ARM_MB_ISHST = 11 , ARM_MB_ISH = 12 , ARM_MB_RESERVED_12 = 13 , ARM_MB_LD = 14 , ARM_MB_ST = 15 , ARM_MB_SY = 16 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM_OP_FP = 4 , # [doc = "< C-Immediate (coprocessor registers)"] ARM_OP_CIMM = 64 , # [doc = "< P-Immediate (coprocessor registers)"] ARM_OP_PIMM = 65 , # [doc = "< operand for SETEND instruction"] ARM_OP_SETEND = 66 , # [doc = "< MSR/MRS special register operand"] ARM_OP_SYSREG = 67 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_setend_type { # [doc = "< Uninitialized."] ARM_SETEND_INVALID = 0 , # [doc = "< BE operand."] ARM_SETEND_BE = 1 , # [doc = "< LE operand"] ARM_SETEND_LE = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0 , ARM_CPSMODE_IE = 2 , ARM_CPSMODE_ID = 3 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0 , ARM_CPSFLAG_F = 1 , ARM_CPSFLAG_I = 2 , ARM_CPSFLAG_A = 4 , # [doc = "< no flag"] ARM_CPSFLAG_NONE = 16 , } # [repr (u32)] # [doc = " Data type for elements of vector instructions."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0 , ARM_VECTORDATA_I8 = 1 , ARM_VECTORDATA_I16 = 2 , ARM_VECTORDATA_I32 = 3 , ARM_VECTORDATA_I64 = 4 , ARM_VECTORDATA_S8 = 5 , ARM_VECTORDATA_S16 = 6 , ARM_VECTORDATA_S32 = 7 , ARM_VECTORDATA_S64 = 8 , ARM_VECTORDATA_U8 = 9 , ARM_VECTORDATA_U16 = 10 , ARM_VECTORDATA_U32 = 11 , ARM_VECTORDATA_U64 = 12 , ARM_VECTORDATA_P8 = 13 , ARM_VECTORDATA_F16 = 14 , ARM_VECTORDATA_F32 = 15 , ARM_VECTORDATA_F64 = 16 , ARM_VECTORDATA_F16F64 = 17 , ARM_VECTORDATA_F64F16 = 18 , ARM_VECTORDATA_F32F16 = 19 , ARM_VECTORDATA_F16F32 = 20 , ARM_VECTORDATA_F64F32 = 21 , ARM_VECTORDATA_F32F64 = 22 , ARM_VECTORDATA_S32F32 = 23 , ARM_VECTORDATA_U32F32 = 24 , ARM_VECTORDATA_F32S32 = 25 , ARM_VECTORDATA_F32U32 = 26 , ARM_VECTORDATA_F64S16 = 27 , ARM_VECTORDATA_F32S16 = 28 , ARM_VECTORDATA_F64S32 = 29 , ARM_VECTORDATA_S16F64 = 30 , ARM_VECTORDATA_S16F32 = 31 , ARM_VECTORDATA_S32F64 = 32 , ARM_VECTORDATA_U16F64 = 33 , ARM_VECTORDATA_U16F32 = 34 , ARM_VECTORDATA_U32F64 = 35 , ARM_VECTORDATA_F64U16 = 36 , ARM_VECTORDATA_F32U16 = 37 , ARM_VECTORDATA_F64U32 = 38 , ARM_VECTORDATA_F16U16 = 39 , ARM_VECTORDATA_U16F16 = 40 , ARM_VECTORDATA_F16U32 = 41 , ARM_VECTORDATA_U32F16 = 42 , } impl arm_reg { pub const ARM_REG_R13 : arm_reg = arm_reg :: ARM_REG_SP ; } impl arm_reg { pub const ARM_REG_R14 : arm_reg = arm_reg :: ARM_REG_LR ; } impl arm_reg { pub const ARM_REG_R15 : arm_reg = arm_reg :: ARM_REG_PC ; } impl arm_reg { pub const ARM_REG_SB : arm_reg = arm_reg :: ARM_REG_R9 ; } impl arm_reg { pub const ARM_REG_SL : arm_reg = arm_reg :: ARM_REG_R10 ; } impl arm_reg { pub const ARM_REG_FP : arm_reg = arm_reg :: ARM_REG_R11 ; } impl arm_reg { pub const ARM_REG_IP : arm_reg = arm_reg :: ARM_REG_R12 ; } # [repr (u32)] # [doc = " ARM registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_reg { ARM_REG_INVALID = 0 , ARM_REG_APSR = 1 , ARM_REG_APSR_NZCV = 2 , ARM_REG_CPSR = 3 , ARM_REG_FPEXC = 4 , ARM_REG_FPINST = 5 , ARM_REG_FPSCR = 6 , ARM_REG_FPSCR_NZCV = 7 , ARM_REG_FPSID = 8 , ARM_REG_ITSTATE = 9 , ARM_REG_LR = 10 , ARM_REG_PC = 11 , ARM_REG_SP = 12 , ARM_REG_SPSR = 13 , ARM_REG_D0 = 14 , ARM_REG_D1 = 15 , ARM_REG_D2 = 16 , ARM_REG_D3 = 17 , ARM_REG_D4 = 18 , ARM_REG_D5 = 19 , ARM_REG_D6 = 20 , ARM_REG_D7 = 21 , ARM_REG_D8 = 22 , ARM_REG_D9 = 23 , ARM_REG_D10 = 24 , ARM_REG_D11 = 25 , ARM_REG_D12 = 26 , ARM_REG_D13 = 27 , ARM_REG_D14 = 28 , ARM_REG_D15 = 29 , ARM_REG_D16 = 30 , ARM_REG_D17 = 31 , ARM_REG_D18 = 32 , ARM_REG_D19 = 33 , ARM_REG_D20 = 34 , ARM_REG_D21 = 35 , ARM_REG_D22 = 36 , ARM_REG_D23 = 37 , ARM_REG_D24 = 38 , ARM_REG_D25 = 39 , ARM_REG_D26 = 40 , ARM_REG_D27 = 41 , ARM_REG_D28 = 42 , ARM_REG_D29 = 43 , ARM_REG_D30 = 44 , ARM_REG_D31 = 45 , ARM_REG_FPINST2 = 46 , ARM_REG_MVFR0 = 47 , ARM_REG_MVFR1 = 48 , ARM_REG_MVFR2 = 49 , ARM_REG_Q0 = 50 , ARM_REG_Q1 = 51 , ARM_REG_Q2 = 52 , ARM_REG_Q3 = 53 , ARM_REG_Q4 = 54 , ARM_REG_Q5 = 55 , ARM_REG_Q6 = 56 , ARM_REG_Q7 = 57 , ARM_REG_Q8 = 58 , ARM_REG_Q9 = 59 , ARM_REG_Q10 = 60 , ARM_REG_Q11 = 61 , ARM_REG_Q12 = 62 , ARM_REG_Q13 = 63 , ARM_REG_Q14 = 64 , ARM_REG_Q15 = 65 , ARM_REG_R0 = 66 , ARM_REG_R1 = 67 , ARM_REG_R2 = 68 , ARM_REG_R3 = 69 , ARM_REG_R4 = 70 , ARM_REG_R5 = 71 , ARM_REG_R6 = 72 , ARM_REG_R7 = 73 , ARM_REG_R8 = 74 , ARM_REG_R9 = 75 , ARM_REG_R10 = 76 , ARM_REG_R11 = 77 , ARM_REG_R12 = 78 , ARM_REG_S0 = 79 , ARM_REG_S1 = 80 , ARM_REG_S2 = 81 , ARM_REG_S3 = 82 , ARM_REG_S4 = 83 , ARM_REG_S5 = 84 , ARM_REG_S6 = 85 , ARM_REG_S7 = 86 , ARM_REG_S8 = 87 , ARM_REG_S9 = 88 , ARM_REG_S10 = 89 , ARM_REG_S11 = 90 , ARM_REG_S12 = 91 , ARM_REG_S13 = 92 , ARM_REG_S14 = 93 , ARM_REG_S15 = 94 , ARM_REG_S16 = 95 , ARM_REG_S17 = 96 , ARM_REG_S18 = 97 , ARM_REG_S19 = 98 , ARM_REG_S20 = 99 , ARM_REG_S21 = 100 , ARM_REG_S22 = 101 , ARM_REG_S23 = 102 , ARM_REG_S24 = 103 , ARM_REG_S25 = 104 , ARM_REG_S26 = 105 , ARM_REG_S27 = 106 , ARM_REG_S28 = 107 , ARM_REG_S29 = 108 , ARM_REG_S30 = 109 , ARM_REG_S31 = 110 , ARM_REG_ENDING = 111 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm_op_mem { # [doc = "< base register"] pub base : arm_reg , # [doc = "< index register"] pub index : arm_reg , # [doc = "< scale for index register (can be 1, or -1)"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_int , # [doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"] pub lshift : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm_op_mem"] [:: std :: mem :: size_of :: < arm_op_mem > () - 20usize] ; ["Alignment of arm_op_mem"] [:: std :: mem :: align_of :: < arm_op_mem > () - 4usize] ; ["Offset of field: arm_op_mem::base"] [:: std :: mem :: offset_of ! (arm_op_mem , base) - 0usize] ; ["Offset of field: arm_op_mem::index"] [:: std :: mem :: offset_of ! (arm_op_mem , index) - 4usize] ; ["Offset of field: arm_op_mem::scale"] [:: std :: mem :: offset_of ! (arm_op_mem , scale) - 8usize] ; ["Offset of field: arm_op_mem::disp"] [:: std :: mem :: offset_of ! (arm_op_mem , disp) - 12usize] ; ["Offset of field: arm_op_mem::lshift"] [:: std :: mem :: offset_of ! (arm_op_mem , lshift) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm_op { # [doc = "< Vector Index for some vector operands (or -1 if irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , pub shift : cs_arm_op__bindgen_ty_1 , # [doc = "< operand type"] pub type_ : arm_op_type , pub __bindgen_anon_1 : cs_arm_op__bindgen_ty_2 , # [doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."] pub subtracted : bool , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"] pub neon_lane : i8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm_op__bindgen_ty_1 { pub type_ : arm_shifter , pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm_op__bindgen_ty_2 { # [doc = "< register value for REG/SYSREG operand"] pub reg : :: std :: os :: raw :: c_int , # [doc = "< immediate value for C-IMM, P-IMM or IMM operand"] pub imm : i32 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm_op_mem , # [doc = "< SETEND instruction's operand type"] pub setend : arm_setend_type , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_2 > () - 24usize] ; ["Alignment of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::setend"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , setend) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op"] [:: std :: mem :: size_of :: < cs_arm_op > () - 48usize] ; ["Alignment of cs_arm_op"] [:: std :: mem :: align_of :: < cs_arm_op > () - 8usize] ; ["Offset of field: cs_arm_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm_op , vector_index) - 0usize] ; ["Offset of field: cs_arm_op::shift"] [:: std :: mem :: offset_of ! (cs_arm_op , shift) - 4usize] ; ["Offset of field: cs_arm_op::type_"] [:: std :: mem :: offset_of ! (cs_arm_op , type_) - 12usize] ; ["Offset of field: cs_arm_op::subtracted"] [:: std :: mem :: offset_of ! (cs_arm_op , subtracted) - 40usize] ; ["Offset of field: cs_arm_op::access"] [:: std :: mem :: offset_of ! (cs_arm_op , access) - 41usize] ; ["Offset of field: cs_arm_op::neon_lane"] [:: std :: mem :: offset_of ! (cs_arm_op , neon_lane) - 42usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm { # [doc = "< User-mode registers to be loaded (for LDM/STM instructions)"] pub usermode : bool , # [doc = "< Scalar size for vector instructions"] pub vector_size : :: std :: os :: raw :: c_int , # [doc = "< Data type for elements of vector instructions"] pub vector_data : arm_vectordata_type , # [doc = "< CPS mode for CPS instruction"] pub cps_mode : arm_cpsmode_type , # [doc = "< CPS mode for CPS instruction"] pub cps_flag : arm_cpsflag_type , # [doc = "< conditional code for this insn"] pub cc : arm_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn write-back?"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = "< Option for some memory barrier instructions"] pub mem_barrier : arm_mem_barrier , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm_op ; 36usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm"] [:: std :: mem :: size_of :: < cs_arm > () - 1768usize] ; ["Alignment of cs_arm"] [:: std :: mem :: align_of :: < cs_arm > () - 8usize] ; ["Offset of field: cs_arm::usermode"] [:: std :: mem :: offset_of ! (cs_arm , usermode) - 0usize] ; ["Offset of field: cs_arm::vector_size"] [:: std :: mem :: offset_of ! (cs_arm , vector_size) - 4usize] ; ["Offset of field: cs_arm::vector_data"] [:: std :: mem :: offset_of ! (cs_arm , vector_data) - 8usize] ; ["Offset of field: cs_arm::cps_mode"] [:: std :: mem :: offset_of ! (cs_arm , cps_mode) - 12usize] ; ["Offset of field: cs_arm::cps_flag"] [:: std :: mem :: offset_of ! (cs_arm , cps_flag) - 16usize] ; ["Offset of field: cs_arm::cc"] [:: std :: mem :: offset_of ! (cs_arm , cc) - 20usize] ; ["Offset of field: cs_arm::update_flags"] [:: std :: mem :: offset_of ! (cs_arm , update_flags) - 24usize] ; ["Offset of field: cs_arm::writeback"] [:: std :: mem :: offset_of ! (cs_arm , writeback) - 25usize] ; ["Offset of field: cs_arm::post_index"] [:: std :: mem :: offset_of ! (cs_arm , post_index) - 26usize] ; ["Offset of field: cs_arm::mem_barrier"] [:: std :: mem :: offset_of ! (cs_arm , mem_barrier) - 28usize] ; ["Offset of field: cs_arm::op_count"] [:: std :: mem :: offset_of ! (cs_arm , op_count) - 32usize] ; ["Offset of field: cs_arm::operands"] [:: std :: mem :: offset_of ! (cs_arm , operands) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_arm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . post_index , self . mem_barrier , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn { ARM_INS_INVALID = 0 , ARM_INS_ADC = 1 , ARM_INS_ADD = 2 , ARM_INS_ADDW = 3 , ARM_INS_ADR = 4 , ARM_INS_AESD = 5 , ARM_INS_AESE = 6 , ARM_INS_AESIMC = 7 , ARM_INS_AESMC = 8 , ARM_INS_AND = 9 , ARM_INS_ASR = 10 , ARM_INS_B = 11 , ARM_INS_BFC = 12 , ARM_INS_BFI = 13 , ARM_INS_BIC = 14 , ARM_INS_BKPT = 15 , ARM_INS_BL = 16 , ARM_INS_BLX = 17 , ARM_INS_BLXNS = 18 , ARM_INS_BX = 19 , ARM_INS_BXJ = 20 , ARM_INS_BXNS = 21 , ARM_INS_CBNZ = 22 , ARM_INS_CBZ = 23 , ARM_INS_CDP = 24 , ARM_INS_CDP2 = 25 , ARM_INS_CLREX = 26 , ARM_INS_CLZ = 27 , ARM_INS_CMN = 28 , ARM_INS_CMP = 29 , ARM_INS_CPS = 30 , ARM_INS_CRC32B = 31 , ARM_INS_CRC32CB = 32 , ARM_INS_CRC32CH = 33 , ARM_INS_CRC32CW = 34 , ARM_INS_CRC32H = 35 , ARM_INS_CRC32W = 36 , ARM_INS_CSDB = 37 , ARM_INS_DBG = 38 , ARM_INS_DCPS1 = 39 , ARM_INS_DCPS2 = 40 , ARM_INS_DCPS3 = 41 , ARM_INS_DFB = 42 , ARM_INS_DMB = 43 , ARM_INS_DSB = 44 , ARM_INS_EOR = 45 , ARM_INS_ERET = 46 , ARM_INS_ESB = 47 , ARM_INS_FADDD = 48 , ARM_INS_FADDS = 49 , ARM_INS_FCMPZD = 50 , ARM_INS_FCMPZS = 51 , ARM_INS_FCONSTD = 52 , ARM_INS_FCONSTS = 53 , ARM_INS_FLDMDBX = 54 , ARM_INS_FLDMIAX = 55 , ARM_INS_FMDHR = 56 , ARM_INS_FMDLR = 57 , ARM_INS_FMSTAT = 58 , ARM_INS_FSTMDBX = 59 , ARM_INS_FSTMIAX = 60 , ARM_INS_FSUBD = 61 , ARM_INS_FSUBS = 62 , ARM_INS_HINT = 63 , ARM_INS_HLT = 64 , ARM_INS_HVC = 65 , ARM_INS_ISB = 66 , ARM_INS_IT = 67 , ARM_INS_LDA = 68 , ARM_INS_LDAB = 69 , ARM_INS_LDAEX = 70 , ARM_INS_LDAEXB = 71 , ARM_INS_LDAEXD = 72 , ARM_INS_LDAEXH = 73 , ARM_INS_LDAH = 74 , ARM_INS_LDC = 75 , ARM_INS_LDC2 = 76 , ARM_INS_LDC2L = 77 , ARM_INS_LDCL = 78 , ARM_INS_LDM = 79 , ARM_INS_LDMDA = 80 , ARM_INS_LDMDB = 81 , ARM_INS_LDMIB = 82 , ARM_INS_LDR = 83 , ARM_INS_LDRB = 84 , ARM_INS_LDRBT = 85 , ARM_INS_LDRD = 86 , ARM_INS_LDREX = 87 , ARM_INS_LDREXB = 88 , ARM_INS_LDREXD = 89 , ARM_INS_LDREXH = 90 , ARM_INS_LDRH = 91 , ARM_INS_LDRHT = 92 , ARM_INS_LDRSB = 93 , ARM_INS_LDRSBT = 94 , ARM_INS_LDRSH = 95 , ARM_INS_LDRSHT = 96 , ARM_INS_LDRT = 97 , ARM_INS_LSL = 98 , ARM_INS_LSR = 99 , ARM_INS_MCR = 100 , ARM_INS_MCR2 = 101 , ARM_INS_MCRR = 102 , ARM_INS_MCRR2 = 103 , ARM_INS_MLA = 104 , ARM_INS_MLS = 105 , ARM_INS_MOV = 106 , ARM_INS_MOVS = 107 , ARM_INS_MOVT = 108 , ARM_INS_MOVW = 109 , ARM_INS_MRC = 110 , ARM_INS_MRC2 = 111 , ARM_INS_MRRC = 112 , ARM_INS_MRRC2 = 113 , ARM_INS_MRS = 114 , ARM_INS_MSR = 115 , ARM_INS_MUL = 116 , ARM_INS_MVN = 117 , ARM_INS_NEG = 118 , ARM_INS_NOP = 119 , ARM_INS_ORN = 120 , ARM_INS_ORR = 121 , ARM_INS_PKHBT = 122 , ARM_INS_PKHTB = 123 , ARM_INS_PLD = 124 , ARM_INS_PLDW = 125 , ARM_INS_PLI = 126 , ARM_INS_POP = 127 , ARM_INS_PUSH = 128 , ARM_INS_QADD = 129 , ARM_INS_QADD16 = 130 , ARM_INS_QADD8 = 131 , ARM_INS_QASX = 132 , ARM_INS_QDADD = 133 , ARM_INS_QDSUB = 134 , ARM_INS_QSAX = 135 , ARM_INS_QSUB = 136 , ARM_INS_QSUB16 = 137 , ARM_INS_QSUB8 = 138 , ARM_INS_RBIT = 139 , ARM_INS_REV = 140 , ARM_INS_REV16 = 141 , ARM_INS_REVSH = 142 , ARM_INS_RFEDA = 143 , ARM_INS_RFEDB = 144 , ARM_INS_RFEIA = 145 , ARM_INS_RFEIB = 146 , ARM_INS_ROR = 147 , ARM_INS_RRX = 148 , ARM_INS_RSB = 149 , ARM_INS_RSC = 150 , ARM_INS_SADD16 = 151 , ARM_INS_SADD8 = 152 , ARM_INS_SASX = 153 , ARM_INS_SBC = 154 , ARM_INS_SBFX = 155 , ARM_INS_SDIV = 156 , ARM_INS_SEL = 157 , ARM_INS_SETEND = 158 , ARM_INS_SETPAN = 159 , ARM_INS_SEV = 160 , ARM_INS_SEVL = 161 , ARM_INS_SG = 162 , ARM_INS_SHA1C = 163 , ARM_INS_SHA1H = 164 , ARM_INS_SHA1M = 165 , ARM_INS_SHA1P = 166 , ARM_INS_SHA1SU0 = 167 , ARM_INS_SHA1SU1 = 168 , ARM_INS_SHA256H = 169 , ARM_INS_SHA256H2 = 170 , ARM_INS_SHA256SU0 = 171 , ARM_INS_SHA256SU1 = 172 , ARM_INS_SHADD16 = 173 , ARM_INS_SHADD8 = 174 , ARM_INS_SHASX = 175 , ARM_INS_SHSAX = 176 , ARM_INS_SHSUB16 = 177 , ARM_INS_SHSUB8 = 178 , ARM_INS_SMC = 179 , ARM_INS_SMLABB = 180 , ARM_INS_SMLABT = 181 , ARM_INS_SMLAD = 182 , ARM_INS_SMLADX = 183 , ARM_INS_SMLAL = 184 , ARM_INS_SMLALBB = 185 , ARM_INS_SMLALBT = 186 , ARM_INS_SMLALD = 187 , ARM_INS_SMLALDX = 188 , ARM_INS_SMLALTB = 189 , ARM_INS_SMLALTT = 190 , ARM_INS_SMLATB = 191 , ARM_INS_SMLATT = 192 , ARM_INS_SMLAWB = 193 , ARM_INS_SMLAWT = 194 , ARM_INS_SMLSD = 195 , ARM_INS_SMLSDX = 196 , ARM_INS_SMLSLD = 197 , ARM_INS_SMLSLDX = 198 , ARM_INS_SMMLA = 199 , ARM_INS_SMMLAR = 200 , ARM_INS_SMMLS = 201 , ARM_INS_SMMLSR = 202 , ARM_INS_SMMUL = 203 , ARM_INS_SMMULR = 204 , ARM_INS_SMUAD = 205 , ARM_INS_SMUADX = 206 , ARM_INS_SMULBB = 207 , ARM_INS_SMULBT = 208 , ARM_INS_SMULL = 209 , ARM_INS_SMULTB = 210 , ARM_INS_SMULTT = 211 , ARM_INS_SMULWB = 212 , ARM_INS_SMULWT = 213 , ARM_INS_SMUSD = 214 , ARM_INS_SMUSDX = 215 , ARM_INS_SRSDA = 216 , ARM_INS_SRSDB = 217 , ARM_INS_SRSIA = 218 , ARM_INS_SRSIB = 219 , ARM_INS_SSAT = 220 , ARM_INS_SSAT16 = 221 , ARM_INS_SSAX = 222 , ARM_INS_SSUB16 = 223 , ARM_INS_SSUB8 = 224 , ARM_INS_STC = 225 , ARM_INS_STC2 = 226 , ARM_INS_STC2L = 227 , ARM_INS_STCL = 228 , ARM_INS_STL = 229 , ARM_INS_STLB = 230 , ARM_INS_STLEX = 231 , ARM_INS_STLEXB = 232 , ARM_INS_STLEXD = 233 , ARM_INS_STLEXH = 234 , ARM_INS_STLH = 235 , ARM_INS_STM = 236 , ARM_INS_STMDA = 237 , ARM_INS_STMDB = 238 , ARM_INS_STMIB = 239 , ARM_INS_STR = 240 , ARM_INS_STRB = 241 , ARM_INS_STRBT = 242 , ARM_INS_STRD = 243 , ARM_INS_STREX = 244 , ARM_INS_STREXB = 245 , ARM_INS_STREXD = 246 , ARM_INS_STREXH = 247 , ARM_INS_STRH = 248 , ARM_INS_STRHT = 249 , ARM_INS_STRT = 250 , ARM_INS_SUB = 251 , ARM_INS_SUBS = 252 , ARM_INS_SUBW = 253 , ARM_INS_SVC = 254 , ARM_INS_SWP = 255 , ARM_INS_SWPB = 256 , ARM_INS_SXTAB = 257 , ARM_INS_SXTAB16 = 258 , ARM_INS_SXTAH = 259 , ARM_INS_SXTB = 260 , ARM_INS_SXTB16 = 261 , ARM_INS_SXTH = 262 , ARM_INS_TBB = 263 , ARM_INS_TBH = 264 , ARM_INS_TEQ = 265 , ARM_INS_TRAP = 266 , ARM_INS_TSB = 267 , ARM_INS_TST = 268 , ARM_INS_TT = 269 , ARM_INS_TTA = 270 , ARM_INS_TTAT = 271 , ARM_INS_TTT = 272 , ARM_INS_UADD16 = 273 , ARM_INS_UADD8 = 274 , ARM_INS_UASX = 275 , ARM_INS_UBFX = 276 , ARM_INS_UDF = 277 , ARM_INS_UDIV = 278 , ARM_INS_UHADD16 = 279 , ARM_INS_UHADD8 = 280 , ARM_INS_UHASX = 281 , ARM_INS_UHSAX = 282 , ARM_INS_UHSUB16 = 283 , ARM_INS_UHSUB8 = 284 , ARM_INS_UMAAL = 285 , ARM_INS_UMLAL = 286 , ARM_INS_UMULL = 287 , ARM_INS_UQADD16 = 288 , ARM_INS_UQADD8 = 289 , ARM_INS_UQASX = 290 , ARM_INS_UQSAX = 291 , ARM_INS_UQSUB16 = 292 , ARM_INS_UQSUB8 = 293 , ARM_INS_USAD8 = 294 , ARM_INS_USADA8 = 295 , ARM_INS_USAT = 296 , ARM_INS_USAT16 = 297 , ARM_INS_USAX = 298 , ARM_INS_USUB16 = 299 , ARM_INS_USUB8 = 300 , ARM_INS_UXTAB = 301 , ARM_INS_UXTAB16 = 302 , ARM_INS_UXTAH = 303 , ARM_INS_UXTB = 304 , ARM_INS_UXTB16 = 305 , ARM_INS_UXTH = 306 , ARM_INS_VABA = 307 , ARM_INS_VABAL = 308 , ARM_INS_VABD = 309 , ARM_INS_VABDL = 310 , ARM_INS_VABS = 311 , ARM_INS_VACGE = 312 , ARM_INS_VACGT = 313 , ARM_INS_VACLE = 314 , ARM_INS_VACLT = 315 , ARM_INS_VADD = 316 , ARM_INS_VADDHN = 317 , ARM_INS_VADDL = 318 , ARM_INS_VADDW = 319 , ARM_INS_VAND = 320 , ARM_INS_VBIC = 321 , ARM_INS_VBIF = 322 , ARM_INS_VBIT = 323 , ARM_INS_VBSL = 324 , ARM_INS_VCADD = 325 , ARM_INS_VCEQ = 326 , ARM_INS_VCGE = 327 , ARM_INS_VCGT = 328 , ARM_INS_VCLE = 329 , ARM_INS_VCLS = 330 , ARM_INS_VCLT = 331 , ARM_INS_VCLZ = 332 , ARM_INS_VCMLA = 333 , ARM_INS_VCMP = 334 , ARM_INS_VCMPE = 335 , ARM_INS_VCNT = 336 , ARM_INS_VCVT = 337 , ARM_INS_VCVTA = 338 , ARM_INS_VCVTB = 339 , ARM_INS_VCVTM = 340 , ARM_INS_VCVTN = 341 , ARM_INS_VCVTP = 342 , ARM_INS_VCVTR = 343 , ARM_INS_VCVTT = 344 , ARM_INS_VDIV = 345 , ARM_INS_VDUP = 346 , ARM_INS_VEOR = 347 , ARM_INS_VEXT = 348 , ARM_INS_VFMA = 349 , ARM_INS_VFMS = 350 , ARM_INS_VFNMA = 351 , ARM_INS_VFNMS = 352 , ARM_INS_VHADD = 353 , ARM_INS_VHSUB = 354 , ARM_INS_VINS = 355 , ARM_INS_VJCVT = 356 , ARM_INS_VLD1 = 357 , ARM_INS_VLD2 = 358 , ARM_INS_VLD3 = 359 , ARM_INS_VLD4 = 360 , ARM_INS_VLDMDB = 361 , ARM_INS_VLDMIA = 362 , ARM_INS_VLDR = 363 , ARM_INS_VLLDM = 364 , ARM_INS_VLSTM = 365 , ARM_INS_VMAX = 366 , ARM_INS_VMAXNM = 367 , ARM_INS_VMIN = 368 , ARM_INS_VMINNM = 369 , ARM_INS_VMLA = 370 , ARM_INS_VMLAL = 371 , ARM_INS_VMLS = 372 , ARM_INS_VMLSL = 373 , ARM_INS_VMOV = 374 , ARM_INS_VMOVL = 375 , ARM_INS_VMOVN = 376 , ARM_INS_VMOVX = 377 , ARM_INS_VMRS = 378 , ARM_INS_VMSR = 379 , ARM_INS_VMUL = 380 , ARM_INS_VMULL = 381 , ARM_INS_VMVN = 382 , ARM_INS_VNEG = 383 , ARM_INS_VNMLA = 384 , ARM_INS_VNMLS = 385 , ARM_INS_VNMUL = 386 , ARM_INS_VORN = 387 , ARM_INS_VORR = 388 , ARM_INS_VPADAL = 389 , ARM_INS_VPADD = 390 , ARM_INS_VPADDL = 391 , ARM_INS_VPMAX = 392 , ARM_INS_VPMIN = 393 , ARM_INS_VPOP = 394 , ARM_INS_VPUSH = 395 , ARM_INS_VQABS = 396 , ARM_INS_VQADD = 397 , ARM_INS_VQDMLAL = 398 , ARM_INS_VQDMLSL = 399 , ARM_INS_VQDMULH = 400 , ARM_INS_VQDMULL = 401 , ARM_INS_VQMOVN = 402 , ARM_INS_VQMOVUN = 403 , ARM_INS_VQNEG = 404 , ARM_INS_VQRDMLAH = 405 , ARM_INS_VQRDMLSH = 406 , ARM_INS_VQRDMULH = 407 , ARM_INS_VQRSHL = 408 , ARM_INS_VQRSHRN = 409 , ARM_INS_VQRSHRUN = 410 , ARM_INS_VQSHL = 411 , ARM_INS_VQSHLU = 412 , ARM_INS_VQSHRN = 413 , ARM_INS_VQSHRUN = 414 , ARM_INS_VQSUB = 415 , ARM_INS_VRADDHN = 416 , ARM_INS_VRECPE = 417 , ARM_INS_VRECPS = 418 , ARM_INS_VREV16 = 419 , ARM_INS_VREV32 = 420 , ARM_INS_VREV64 = 421 , ARM_INS_VRHADD = 422 , ARM_INS_VRINTA = 423 , ARM_INS_VRINTM = 424 , ARM_INS_VRINTN = 425 , ARM_INS_VRINTP = 426 , ARM_INS_VRINTR = 427 , ARM_INS_VRINTX = 428 , ARM_INS_VRINTZ = 429 , ARM_INS_VRSHL = 430 , ARM_INS_VRSHR = 431 , ARM_INS_VRSHRN = 432 , ARM_INS_VRSQRTE = 433 , ARM_INS_VRSQRTS = 434 , ARM_INS_VRSRA = 435 , ARM_INS_VRSUBHN = 436 , ARM_INS_VSDOT = 437 , ARM_INS_VSELEQ = 438 , ARM_INS_VSELGE = 439 , ARM_INS_VSELGT = 440 , ARM_INS_VSELVS = 441 , ARM_INS_VSHL = 442 , ARM_INS_VSHLL = 443 , ARM_INS_VSHR = 444 , ARM_INS_VSHRN = 445 , ARM_INS_VSLI = 446 , ARM_INS_VSQRT = 447 , ARM_INS_VSRA = 448 , ARM_INS_VSRI = 449 , ARM_INS_VST1 = 450 , ARM_INS_VST2 = 451 , ARM_INS_VST3 = 452 , ARM_INS_VST4 = 453 , ARM_INS_VSTMDB = 454 , ARM_INS_VSTMIA = 455 , ARM_INS_VSTR = 456 , ARM_INS_VSUB = 457 , ARM_INS_VSUBHN = 458 , ARM_INS_VSUBL = 459 , ARM_INS_VSUBW = 460 , ARM_INS_VSWP = 461 , ARM_INS_VTBL = 462 , ARM_INS_VTBX = 463 , ARM_INS_VTRN = 464 , ARM_INS_VTST = 465 , ARM_INS_VUDOT = 466 , ARM_INS_VUZP = 467 , ARM_INS_VZIP = 468 , ARM_INS_WFE = 469 , ARM_INS_WFI = 470 , ARM_INS_YIELD = 471 , ARM_INS_ENDING = 472 , } # [repr (u32)] # [doc = " Group of ARM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] ARM_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] ARM_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM_GRP_BRANCH_RELATIVE = 7 , ARM_GRP_CRYPTO = 128 , ARM_GRP_DATABARRIER = 129 , ARM_GRP_DIVIDE = 130 , ARM_GRP_FPARMV8 = 131 , ARM_GRP_MULTPRO = 132 , ARM_GRP_NEON = 133 , ARM_GRP_T2EXTRACTPACK = 134 , ARM_GRP_THUMB2DSP = 135 , ARM_GRP_TRUSTZONE = 136 , ARM_GRP_V4T = 137 , ARM_GRP_V5T = 138 , ARM_GRP_V5TE = 139 , ARM_GRP_V6 = 140 , ARM_GRP_V6T2 = 141 , ARM_GRP_V7 = 142 , ARM_GRP_V8 = 143 , ARM_GRP_VFP2 = 144 , ARM_GRP_VFP3 = 145 , ARM_GRP_VFP4 = 146 , ARM_GRP_ARM = 147 , ARM_GRP_MCLASS = 148 , ARM_GRP_NOTMCLASS = 149 , ARM_GRP_THUMB = 150 , ARM_GRP_THUMB1ONLY = 151 , ARM_GRP_THUMB2 = 152 , ARM_GRP_PREV8 = 153 , ARM_GRP_FPVMLX = 154 , ARM_GRP_MULOPS = 155 , ARM_GRP_CRC = 156 , ARM_GRP_DPVFP = 157 , ARM_GRP_V6M = 158 , ARM_GRP_VIRTUALIZATION = 159 , ARM_GRP_ENDING = 160 , } # [repr (u32)] # [doc = " ARM64 shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_shifter { ARM64_SFT_INVALID = 0 , ARM64_SFT_LSL = 1 , ARM64_SFT_MSL = 2 , ARM64_SFT_LSR = 3 , ARM64_SFT_ASR = 4 , ARM64_SFT_ROR = 5 , } # [repr (u32)] # [doc = " ARM64 extender type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_extender { ARM64_EXT_INVALID = 0 , ARM64_EXT_UXTB = 1 , ARM64_EXT_UXTH = 2 , ARM64_EXT_UXTW = 3 , ARM64_EXT_UXTX = 4 , ARM64_EXT_SXTB = 5 , ARM64_EXT_SXTH = 6 , ARM64_EXT_SXTW = 7 , ARM64_EXT_SXTX = 8 , } # [repr (u32)] # [doc = " ARM64 condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_cc { ARM64_CC_INVALID = 0 , # [doc = "< Equal"] ARM64_CC_EQ = 1 , # [doc = "< Not equal:                 Not equal, or unordered"] ARM64_CC_NE = 2 , # [doc = "< Unsigned higher or same:   >, ==, or unordered"] ARM64_CC_HS = 3 , # [doc = "< Unsigned lower or same:    Less than"] ARM64_CC_LO = 4 , # [doc = "< Minus, negative:           Less than"] ARM64_CC_MI = 5 , # [doc = "< Plus, positive or zero:    >, ==, or unordered"] ARM64_CC_PL = 6 , # [doc = "< Overflow:                  Unordered"] ARM64_CC_VS = 7 , # [doc = "< No overflow:               Ordered"] ARM64_CC_VC = 8 , # [doc = "< Unsigned higher:           Greater than, or unordered"] ARM64_CC_HI = 9 , # [doc = "< Unsigned lower or same:    Less than or equal"] ARM64_CC_LS = 10 , # [doc = "< Greater than or equal:     Greater than or equal"] ARM64_CC_GE = 11 , # [doc = "< Less than:                 Less than, or unordered"] ARM64_CC_LT = 12 , # [doc = "< Signed greater than:       Greater than"] ARM64_CC_GT = 13 , # [doc = "< Signed less than or equal: <, ==, or unordered"] ARM64_CC_LE = 14 , # [doc = "< Always (unconditional):    Always (unconditional)"] ARM64_CC_AL = 15 , # [doc = "< Always (unconditional):   Always (unconditional)"] ARM64_CC_NV = 16 , } impl arm64_sysreg { pub const ARM64_SYSREG_DBGDTRTX_EL0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_DBGDTRRX_EL0 ; } impl arm64_sysreg { pub const ARM64_SYSREG_TRCEXTINSELR0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TRCEXTINSELR ; } impl arm64_sysreg { pub const ARM64_SYSREG_VSCTLR_EL2 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TTBR0_EL2 ; } # [repr (u32)] # [doc = " System registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sysreg { ARM64_SYSREG_INVALID = 0 , ARM64_SYSREG_ACCDATA_EL1 = 50821 , ARM64_SYSREG_ACTLR_EL1 = 49281 , ARM64_SYSREG_ACTLR_EL2 = 57473 , ARM64_SYSREG_ACTLR_EL3 = 61569 , ARM64_SYSREG_AFSR0_EL1 = 49800 , ARM64_SYSREG_AFSR0_EL12 = 60040 , ARM64_SYSREG_AFSR0_EL2 = 57992 , ARM64_SYSREG_AFSR0_EL3 = 62088 , ARM64_SYSREG_AFSR1_EL1 = 49801 , ARM64_SYSREG_AFSR1_EL12 = 60041 , ARM64_SYSREG_AFSR1_EL2 = 57993 , ARM64_SYSREG_AFSR1_EL3 = 62089 , ARM64_SYSREG_AIDR_EL1 = 51207 , ARM64_SYSREG_AMAIR_EL1 = 50456 , ARM64_SYSREG_AMAIR_EL12 = 60696 , ARM64_SYSREG_AMAIR_EL2 = 58648 , ARM64_SYSREG_AMAIR_EL3 = 62744 , ARM64_SYSREG_AMCFGR_EL0 = 56977 , ARM64_SYSREG_AMCGCR_EL0 = 56978 , ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980 , ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984 , ARM64_SYSREG_AMCNTENSET0_EL0 = 56981 , ARM64_SYSREG_AMCNTENSET1_EL0 = 56985 , ARM64_SYSREG_AMCR_EL0 = 56976 , ARM64_SYSREG_AMEVCNTR00_EL0 = 56992 , ARM64_SYSREG_AMEVCNTR01_EL0 = 56993 , ARM64_SYSREG_AMEVCNTR02_EL0 = 56994 , ARM64_SYSREG_AMEVCNTR03_EL0 = 56995 , ARM64_SYSREG_AMEVCNTR10_EL0 = 57056 , ARM64_SYSREG_AMEVCNTR110_EL0 = 57066 , ARM64_SYSREG_AMEVCNTR111_EL0 = 57067 , ARM64_SYSREG_AMEVCNTR112_EL0 = 57068 , ARM64_SYSREG_AMEVCNTR113_EL0 = 57069 , ARM64_SYSREG_AMEVCNTR114_EL0 = 57070 , ARM64_SYSREG_AMEVCNTR115_EL0 = 57071 , ARM64_SYSREG_AMEVCNTR11_EL0 = 57057 , ARM64_SYSREG_AMEVCNTR12_EL0 = 57058 , ARM64_SYSREG_AMEVCNTR13_EL0 = 57059 , ARM64_SYSREG_AMEVCNTR14_EL0 = 57060 , ARM64_SYSREG_AMEVCNTR15_EL0 = 57061 , ARM64_SYSREG_AMEVCNTR16_EL0 = 57062 , ARM64_SYSREG_AMEVCNTR17_EL0 = 57063 , ARM64_SYSREG_AMEVCNTR18_EL0 = 57064 , ARM64_SYSREG_AMEVCNTR19_EL0 = 57065 , ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 59072 , ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 59082 , ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 59083 , ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 59084 , ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 59085 , ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 59086 , ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 59087 , ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 59073 , ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 59074 , ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 59075 , ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 59076 , ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 59077 , ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 59078 , ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 59079 , ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 59080 , ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 59081 , ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 59088 , ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 59098 , ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 59099 , ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 59100 , ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 59101 , ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 59102 , ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 59103 , ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 59089 , ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 59090 , ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 59091 , ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 59092 , ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 59093 , ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 59094 , ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 59095 , ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 59096 , ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 59097 , ARM64_SYSREG_AMEVTYPER00_EL0 = 57008 , ARM64_SYSREG_AMEVTYPER01_EL0 = 57009 , ARM64_SYSREG_AMEVTYPER02_EL0 = 57010 , ARM64_SYSREG_AMEVTYPER03_EL0 = 57011 , ARM64_SYSREG_AMEVTYPER10_EL0 = 57072 , ARM64_SYSREG_AMEVTYPER110_EL0 = 57082 , ARM64_SYSREG_AMEVTYPER111_EL0 = 57083 , ARM64_SYSREG_AMEVTYPER112_EL0 = 57084 , ARM64_SYSREG_AMEVTYPER113_EL0 = 57085 , ARM64_SYSREG_AMEVTYPER114_EL0 = 57086 , ARM64_SYSREG_AMEVTYPER115_EL0 = 57087 , ARM64_SYSREG_AMEVTYPER11_EL0 = 57073 , ARM64_SYSREG_AMEVTYPER12_EL0 = 57074 , ARM64_SYSREG_AMEVTYPER13_EL0 = 57075 , ARM64_SYSREG_AMEVTYPER14_EL0 = 57076 , ARM64_SYSREG_AMEVTYPER15_EL0 = 57077 , ARM64_SYSREG_AMEVTYPER16_EL0 = 57078 , ARM64_SYSREG_AMEVTYPER17_EL0 = 57079 , ARM64_SYSREG_AMEVTYPER18_EL0 = 57080 , ARM64_SYSREG_AMEVTYPER19_EL0 = 57081 , ARM64_SYSREG_AMUSERENR_EL0 = 56979 , ARM64_SYSREG_APDAKEYHI_EL1 = 49425 , ARM64_SYSREG_APDAKEYLO_EL1 = 49424 , ARM64_SYSREG_APDBKEYHI_EL1 = 49427 , ARM64_SYSREG_APDBKEYLO_EL1 = 49426 , ARM64_SYSREG_APGAKEYHI_EL1 = 49433 , ARM64_SYSREG_APGAKEYLO_EL1 = 49432 , ARM64_SYSREG_APIAKEYHI_EL1 = 49417 , ARM64_SYSREG_APIAKEYLO_EL1 = 49416 , ARM64_SYSREG_APIBKEYHI_EL1 = 49419 , ARM64_SYSREG_APIBKEYLO_EL1 = 49418 , ARM64_SYSREG_BRBCR_EL1 = 35968 , ARM64_SYSREG_BRBCR_EL12 = 44160 , ARM64_SYSREG_BRBCR_EL2 = 42112 , ARM64_SYSREG_BRBFCR_EL1 = 35969 , ARM64_SYSREG_BRBIDR0_EL1 = 35984 , ARM64_SYSREG_BRBINF0_EL1 = 35840 , ARM64_SYSREG_BRBINF10_EL1 = 35920 , ARM64_SYSREG_BRBINF11_EL1 = 35928 , ARM64_SYSREG_BRBINF12_EL1 = 35936 , ARM64_SYSREG_BRBINF13_EL1 = 35944 , ARM64_SYSREG_BRBINF14_EL1 = 35952 , ARM64_SYSREG_BRBINF15_EL1 = 35960 , ARM64_SYSREG_BRBINF16_EL1 = 35844 , ARM64_SYSREG_BRBINF17_EL1 = 35852 , ARM64_SYSREG_BRBINF18_EL1 = 35860 , ARM64_SYSREG_BRBINF19_EL1 = 35868 , ARM64_SYSREG_BRBINF1_EL1 = 35848 , ARM64_SYSREG_BRBINF20_EL1 = 35876 , ARM64_SYSREG_BRBINF21_EL1 = 35884 , ARM64_SYSREG_BRBINF22_EL1 = 35892 , ARM64_SYSREG_BRBINF23_EL1 = 35900 , ARM64_SYSREG_BRBINF24_EL1 = 35908 , ARM64_SYSREG_BRBINF25_EL1 = 35916 , ARM64_SYSREG_BRBINF26_EL1 = 35924 , ARM64_SYSREG_BRBINF27_EL1 = 35932 , ARM64_SYSREG_BRBINF28_EL1 = 35940 , ARM64_SYSREG_BRBINF29_EL1 = 35948 , ARM64_SYSREG_BRBINF2_EL1 = 35856 , ARM64_SYSREG_BRBINF30_EL1 = 35956 , ARM64_SYSREG_BRBINF31_EL1 = 35964 , ARM64_SYSREG_BRBINF3_EL1 = 35864 , ARM64_SYSREG_BRBINF4_EL1 = 35872 , ARM64_SYSREG_BRBINF5_EL1 = 35880 , ARM64_SYSREG_BRBINF6_EL1 = 35888 , ARM64_SYSREG_BRBINF7_EL1 = 35896 , ARM64_SYSREG_BRBINF8_EL1 = 35904 , ARM64_SYSREG_BRBINF9_EL1 = 35912 , ARM64_SYSREG_BRBINFINJ_EL1 = 35976 , ARM64_SYSREG_BRBSRC0_EL1 = 35841 , ARM64_SYSREG_BRBSRC10_EL1 = 35921 , ARM64_SYSREG_BRBSRC11_EL1 = 35929 , ARM64_SYSREG_BRBSRC12_EL1 = 35937 , ARM64_SYSREG_BRBSRC13_EL1 = 35945 , ARM64_SYSREG_BRBSRC14_EL1 = 35953 , ARM64_SYSREG_BRBSRC15_EL1 = 35961 , ARM64_SYSREG_BRBSRC16_EL1 = 35845 , ARM64_SYSREG_BRBSRC17_EL1 = 35853 , ARM64_SYSREG_BRBSRC18_EL1 = 35861 , ARM64_SYSREG_BRBSRC19_EL1 = 35869 , ARM64_SYSREG_BRBSRC1_EL1 = 35849 , ARM64_SYSREG_BRBSRC20_EL1 = 35877 , ARM64_SYSREG_BRBSRC21_EL1 = 35885 , ARM64_SYSREG_BRBSRC22_EL1 = 35893 , ARM64_SYSREG_BRBSRC23_EL1 = 35901 , ARM64_SYSREG_BRBSRC24_EL1 = 35909 , ARM64_SYSREG_BRBSRC25_EL1 = 35917 , ARM64_SYSREG_BRBSRC26_EL1 = 35925 , ARM64_SYSREG_BRBSRC27_EL1 = 35933 , ARM64_SYSREG_BRBSRC28_EL1 = 35941 , ARM64_SYSREG_BRBSRC29_EL1 = 35949 , ARM64_SYSREG_BRBSRC2_EL1 = 35857 , ARM64_SYSREG_BRBSRC30_EL1 = 35957 , ARM64_SYSREG_BRBSRC31_EL1 = 35965 , ARM64_SYSREG_BRBSRC3_EL1 = 35865 , ARM64_SYSREG_BRBSRC4_EL1 = 35873 , ARM64_SYSREG_BRBSRC5_EL1 = 35881 , ARM64_SYSREG_BRBSRC6_EL1 = 35889 , ARM64_SYSREG_BRBSRC7_EL1 = 35897 , ARM64_SYSREG_BRBSRC8_EL1 = 35905 , ARM64_SYSREG_BRBSRC9_EL1 = 35913 , ARM64_SYSREG_BRBSRCINJ_EL1 = 35977 , ARM64_SYSREG_BRBTGT0_EL1 = 35842 , ARM64_SYSREG_BRBTGT10_EL1 = 35922 , ARM64_SYSREG_BRBTGT11_EL1 = 35930 , ARM64_SYSREG_BRBTGT12_EL1 = 35938 , ARM64_SYSREG_BRBTGT13_EL1 = 35946 , ARM64_SYSREG_BRBTGT14_EL1 = 35954 , ARM64_SYSREG_BRBTGT15_EL1 = 35962 , ARM64_SYSREG_BRBTGT16_EL1 = 35846 , ARM64_SYSREG_BRBTGT17_EL1 = 35854 , ARM64_SYSREG_BRBTGT18_EL1 = 35862 , ARM64_SYSREG_BRBTGT19_EL1 = 35870 , ARM64_SYSREG_BRBTGT1_EL1 = 35850 , ARM64_SYSREG_BRBTGT20_EL1 = 35878 , ARM64_SYSREG_BRBTGT21_EL1 = 35886 , ARM64_SYSREG_BRBTGT22_EL1 = 35894 , ARM64_SYSREG_BRBTGT23_EL1 = 35902 , ARM64_SYSREG_BRBTGT24_EL1 = 35910 , ARM64_SYSREG_BRBTGT25_EL1 = 35918 , ARM64_SYSREG_BRBTGT26_EL1 = 35926 , ARM64_SYSREG_BRBTGT27_EL1 = 35934 , ARM64_SYSREG_BRBTGT28_EL1 = 35942 , ARM64_SYSREG_BRBTGT29_EL1 = 35950 , ARM64_SYSREG_BRBTGT2_EL1 = 35858 , ARM64_SYSREG_BRBTGT30_EL1 = 35958 , ARM64_SYSREG_BRBTGT31_EL1 = 35966 , ARM64_SYSREG_BRBTGT3_EL1 = 35866 , ARM64_SYSREG_BRBTGT4_EL1 = 35874 , ARM64_SYSREG_BRBTGT5_EL1 = 35882 , ARM64_SYSREG_BRBTGT6_EL1 = 35890 , ARM64_SYSREG_BRBTGT7_EL1 = 35898 , ARM64_SYSREG_BRBTGT8_EL1 = 35906 , ARM64_SYSREG_BRBTGT9_EL1 = 35914 , ARM64_SYSREG_BRBTGTINJ_EL1 = 35978 , ARM64_SYSREG_BRBTS_EL1 = 35970 , ARM64_SYSREG_CCSIDR2_EL1 = 51202 , ARM64_SYSREG_CCSIDR_EL1 = 51200 , ARM64_SYSREG_CLIDR_EL1 = 51201 , ARM64_SYSREG_CNTFRQ_EL0 = 57088 , ARM64_SYSREG_CNTHCTL_EL2 = 59144 , ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177 , ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178 , ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176 , ARM64_SYSREG_CNTHP_CTL_EL2 = 59153 , ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154 , ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152 , ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169 , ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170 , ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168 , ARM64_SYSREG_CNTHV_CTL_EL2 = 59161 , ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162 , ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160 , ARM64_SYSREG_CNTISCALE_EL2 = 59141 , ARM64_SYSREG_CNTKCTL_EL1 = 50952 , ARM64_SYSREG_CNTKCTL_EL12 = 61192 , ARM64_SYSREG_CNTPCTSS_EL0 = 57093 , ARM64_SYSREG_CNTPCT_EL0 = 57089 , ARM64_SYSREG_CNTPOFF_EL2 = 59142 , ARM64_SYSREG_CNTPS_CTL_EL1 = 65297 , ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298 , ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296 , ARM64_SYSREG_CNTP_CTL_EL0 = 57105 , ARM64_SYSREG_CNTP_CTL_EL02 = 61201 , ARM64_SYSREG_CNTP_CVAL_EL0 = 57106 , ARM64_SYSREG_CNTP_CVAL_EL02 = 61202 , ARM64_SYSREG_CNTP_TVAL_EL0 = 57104 , ARM64_SYSREG_CNTP_TVAL_EL02 = 61200 , ARM64_SYSREG_CNTSCALE_EL2 = 59140 , ARM64_SYSREG_CNTVCTSS_EL0 = 57094 , ARM64_SYSREG_CNTVCT_EL0 = 57090 , ARM64_SYSREG_CNTVFRQ_EL2 = 59143 , ARM64_SYSREG_CNTVOFF_EL2 = 59139 , ARM64_SYSREG_CNTV_CTL_EL0 = 57113 , ARM64_SYSREG_CNTV_CTL_EL02 = 61209 , ARM64_SYSREG_CNTV_CVAL_EL0 = 57114 , ARM64_SYSREG_CNTV_CVAL_EL02 = 61210 , ARM64_SYSREG_CNTV_TVAL_EL0 = 57112 , ARM64_SYSREG_CNTV_TVAL_EL02 = 61208 , ARM64_SYSREG_CONTEXTIDR_EL1 = 50817 , ARM64_SYSREG_CONTEXTIDR_EL12 = 61057 , ARM64_SYSREG_CONTEXTIDR_EL2 = 59009 , ARM64_SYSREG_CPACR_EL1 = 49282 , ARM64_SYSREG_CPACR_EL12 = 59522 , ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424 , ARM64_SYSREG_CPTR_EL2 = 57482 , ARM64_SYSREG_CPTR_EL3 = 61578 , ARM64_SYSREG_CSSELR_EL1 = 53248 , ARM64_SYSREG_CTR_EL0 = 55297 , ARM64_SYSREG_CURRENTEL = 49682 , ARM64_SYSREG_DACR32_EL2 = 57728 , ARM64_SYSREG_DAIF = 55825 , ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782 , ARM64_SYSREG_DBGBCR0_EL1 = 32773 , ARM64_SYSREG_DBGBCR10_EL1 = 32853 , ARM64_SYSREG_DBGBCR11_EL1 = 32861 , ARM64_SYSREG_DBGBCR12_EL1 = 32869 , ARM64_SYSREG_DBGBCR13_EL1 = 32877 , ARM64_SYSREG_DBGBCR14_EL1 = 32885 , ARM64_SYSREG_DBGBCR15_EL1 = 32893 , ARM64_SYSREG_DBGBCR1_EL1 = 32781 , ARM64_SYSREG_DBGBCR2_EL1 = 32789 , ARM64_SYSREG_DBGBCR3_EL1 = 32797 , ARM64_SYSREG_DBGBCR4_EL1 = 32805 , ARM64_SYSREG_DBGBCR5_EL1 = 32813 , ARM64_SYSREG_DBGBCR6_EL1 = 32821 , ARM64_SYSREG_DBGBCR7_EL1 = 32829 , ARM64_SYSREG_DBGBCR8_EL1 = 32837 , ARM64_SYSREG_DBGBCR9_EL1 = 32845 , ARM64_SYSREG_DBGBVR0_EL1 = 32772 , ARM64_SYSREG_DBGBVR10_EL1 = 32852 , ARM64_SYSREG_DBGBVR11_EL1 = 32860 , ARM64_SYSREG_DBGBVR12_EL1 = 32868 , ARM64_SYSREG_DBGBVR13_EL1 = 32876 , ARM64_SYSREG_DBGBVR14_EL1 = 32884 , ARM64_SYSREG_DBGBVR15_EL1 = 32892 , ARM64_SYSREG_DBGBVR1_EL1 = 32780 , ARM64_SYSREG_DBGBVR2_EL1 = 32788 , ARM64_SYSREG_DBGBVR3_EL1 = 32796 , ARM64_SYSREG_DBGBVR4_EL1 = 32804 , ARM64_SYSREG_DBGBVR5_EL1 = 32812 , ARM64_SYSREG_DBGBVR6_EL1 = 32820 , ARM64_SYSREG_DBGBVR7_EL1 = 32828 , ARM64_SYSREG_DBGBVR8_EL1 = 32836 , ARM64_SYSREG_DBGBVR9_EL1 = 32844 , ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742 , ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734 , ARM64_SYSREG_DBGDTRRX_EL0 = 38952 , ARM64_SYSREG_DBGDTR_EL0 = 38944 , ARM64_SYSREG_DBGPRCR_EL1 = 32932 , ARM64_SYSREG_DBGVCR32_EL2 = 41016 , ARM64_SYSREG_DBGWCR0_EL1 = 32775 , ARM64_SYSREG_DBGWCR10_EL1 = 32855 , ARM64_SYSREG_DBGWCR11_EL1 = 32863 , ARM64_SYSREG_DBGWCR12_EL1 = 32871 , ARM64_SYSREG_DBGWCR13_EL1 = 32879 , ARM64_SYSREG_DBGWCR14_EL1 = 32887 , ARM64_SYSREG_DBGWCR15_EL1 = 32895 , ARM64_SYSREG_DBGWCR1_EL1 = 32783 , ARM64_SYSREG_DBGWCR2_EL1 = 32791 , ARM64_SYSREG_DBGWCR3_EL1 = 32799 , ARM64_SYSREG_DBGWCR4_EL1 = 32807 , ARM64_SYSREG_DBGWCR5_EL1 = 32815 , ARM64_SYSREG_DBGWCR6_EL1 = 32823 , ARM64_SYSREG_DBGWCR7_EL1 = 32831 , ARM64_SYSREG_DBGWCR8_EL1 = 32839 , ARM64_SYSREG_DBGWCR9_EL1 = 32847 , ARM64_SYSREG_DBGWVR0_EL1 = 32774 , ARM64_SYSREG_DBGWVR10_EL1 = 32854 , ARM64_SYSREG_DBGWVR11_EL1 = 32862 , ARM64_SYSREG_DBGWVR12_EL1 = 32870 , ARM64_SYSREG_DBGWVR13_EL1 = 32878 , ARM64_SYSREG_DBGWVR14_EL1 = 32886 , ARM64_SYSREG_DBGWVR15_EL1 = 32894 , ARM64_SYSREG_DBGWVR1_EL1 = 32782 , ARM64_SYSREG_DBGWVR2_EL1 = 32790 , ARM64_SYSREG_DBGWVR3_EL1 = 32798 , ARM64_SYSREG_DBGWVR4_EL1 = 32806 , ARM64_SYSREG_DBGWVR5_EL1 = 32814 , ARM64_SYSREG_DBGWVR6_EL1 = 32822 , ARM64_SYSREG_DBGWVR7_EL1 = 32830 , ARM64_SYSREG_DBGWVR8_EL1 = 32838 , ARM64_SYSREG_DBGWVR9_EL1 = 32846 , ARM64_SYSREG_DCZID_EL0 = 55303 , ARM64_SYSREG_DISR_EL1 = 50697 , ARM64_SYSREG_DIT = 55829 , ARM64_SYSREG_DLR_EL0 = 55849 , ARM64_SYSREG_DSPSR_EL0 = 55848 , ARM64_SYSREG_ELR_EL1 = 49665 , ARM64_SYSREG_ELR_EL12 = 59905 , ARM64_SYSREG_ELR_EL2 = 57857 , ARM64_SYSREG_ELR_EL3 = 61953 , ARM64_SYSREG_ERRIDR_EL1 = 49816 , ARM64_SYSREG_ERRSELR_EL1 = 49817 , ARM64_SYSREG_ERXADDR_EL1 = 49827 , ARM64_SYSREG_ERXCTLR_EL1 = 49825 , ARM64_SYSREG_ERXFR_EL1 = 49824 , ARM64_SYSREG_ERXMISC0_EL1 = 49832 , ARM64_SYSREG_ERXMISC1_EL1 = 49833 , ARM64_SYSREG_ERXMISC2_EL1 = 49834 , ARM64_SYSREG_ERXMISC3_EL1 = 49835 , ARM64_SYSREG_ERXPFGCDN_EL1 = 49830 , ARM64_SYSREG_ERXPFGCTL_EL1 = 49829 , ARM64_SYSREG_ERXPFGF_EL1 = 49828 , ARM64_SYSREG_ERXSTATUS_EL1 = 49826 , ARM64_SYSREG_ESR_EL1 = 49808 , ARM64_SYSREG_ESR_EL12 = 60048 , ARM64_SYSREG_ESR_EL2 = 58000 , ARM64_SYSREG_ESR_EL3 = 62096 , ARM64_SYSREG_FAR_EL1 = 49920 , ARM64_SYSREG_FAR_EL12 = 60160 , ARM64_SYSREG_FAR_EL2 = 58112 , ARM64_SYSREG_FAR_EL3 = 62208 , ARM64_SYSREG_FPCR = 55840 , ARM64_SYSREG_FPEXC32_EL2 = 58008 , ARM64_SYSREG_FPSR = 55841 , ARM64_SYSREG_GCR_EL1 = 49286 , ARM64_SYSREG_GMID_EL1 = 51204 , ARM64_SYSREG_GPCCR_EL3 = 61710 , ARM64_SYSREG_GPTBR_EL3 = 61708 , ARM64_SYSREG_HACR_EL2 = 57487 , ARM64_SYSREG_HCRX_EL2 = 57490 , ARM64_SYSREG_HCR_EL2 = 57480 , ARM64_SYSREG_HDFGRTR_EL2 = 57740 , ARM64_SYSREG_HDFGWTR_EL2 = 57741 , ARM64_SYSREG_HFGITR_EL2 = 57486 , ARM64_SYSREG_HFGRTR_EL2 = 57484 , ARM64_SYSREG_HFGWTR_EL2 = 57485 , ARM64_SYSREG_HPFAR_EL2 = 58116 , ARM64_SYSREG_HSTR_EL2 = 57483 , ARM64_SYSREG_ICC_AP0R0_EL1 = 50756 , ARM64_SYSREG_ICC_AP0R1_EL1 = 50757 , ARM64_SYSREG_ICC_AP0R2_EL1 = 50758 , ARM64_SYSREG_ICC_AP0R3_EL1 = 50759 , ARM64_SYSREG_ICC_AP1R0_EL1 = 50760 , ARM64_SYSREG_ICC_AP1R1_EL1 = 50761 , ARM64_SYSREG_ICC_AP1R2_EL1 = 50762 , ARM64_SYSREG_ICC_AP1R3_EL1 = 50763 , ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782 , ARM64_SYSREG_ICC_BPR0_EL1 = 50755 , ARM64_SYSREG_ICC_BPR1_EL1 = 50787 , ARM64_SYSREG_ICC_CTLR_EL1 = 50788 , ARM64_SYSREG_ICC_CTLR_EL3 = 63076 , ARM64_SYSREG_ICC_DIR_EL1 = 50777 , ARM64_SYSREG_ICC_EOIR0_EL1 = 50753 , ARM64_SYSREG_ICC_EOIR1_EL1 = 50785 , ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754 , ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786 , ARM64_SYSREG_ICC_IAR0_EL1 = 50752 , ARM64_SYSREG_ICC_IAR1_EL1 = 50784 , ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790 , ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791 , ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079 , ARM64_SYSREG_ICC_PMR_EL1 = 49712 , ARM64_SYSREG_ICC_RPR_EL1 = 50779 , ARM64_SYSREG_ICC_SGI0R_EL1 = 50783 , ARM64_SYSREG_ICC_SGI1R_EL1 = 50781 , ARM64_SYSREG_ICC_SRE_EL1 = 50789 , ARM64_SYSREG_ICC_SRE_EL2 = 58957 , ARM64_SYSREG_ICC_SRE_EL3 = 63077 , ARM64_SYSREG_ICH_AP0R0_EL2 = 58944 , ARM64_SYSREG_ICH_AP0R1_EL2 = 58945 , ARM64_SYSREG_ICH_AP0R2_EL2 = 58946 , ARM64_SYSREG_ICH_AP0R3_EL2 = 58947 , ARM64_SYSREG_ICH_AP1R0_EL2 = 58952 , ARM64_SYSREG_ICH_AP1R1_EL2 = 58953 , ARM64_SYSREG_ICH_AP1R2_EL2 = 58954 , ARM64_SYSREG_ICH_AP1R3_EL2 = 58955 , ARM64_SYSREG_ICH_EISR_EL2 = 58971 , ARM64_SYSREG_ICH_ELRSR_EL2 = 58973 , ARM64_SYSREG_ICH_HCR_EL2 = 58968 , ARM64_SYSREG_ICH_LR0_EL2 = 58976 , ARM64_SYSREG_ICH_LR10_EL2 = 58986 , ARM64_SYSREG_ICH_LR11_EL2 = 58987 , ARM64_SYSREG_ICH_LR12_EL2 = 58988 , ARM64_SYSREG_ICH_LR13_EL2 = 58989 , ARM64_SYSREG_ICH_LR14_EL2 = 58990 , ARM64_SYSREG_ICH_LR15_EL2 = 58991 , ARM64_SYSREG_ICH_LR1_EL2 = 58977 , ARM64_SYSREG_ICH_LR2_EL2 = 58978 , ARM64_SYSREG_ICH_LR3_EL2 = 58979 , ARM64_SYSREG_ICH_LR4_EL2 = 58980 , ARM64_SYSREG_ICH_LR5_EL2 = 58981 , ARM64_SYSREG_ICH_LR6_EL2 = 58982 , ARM64_SYSREG_ICH_LR7_EL2 = 58983 , ARM64_SYSREG_ICH_LR8_EL2 = 58984 , ARM64_SYSREG_ICH_LR9_EL2 = 58985 , ARM64_SYSREG_ICH_MISR_EL2 = 58970 , ARM64_SYSREG_ICH_VMCR_EL2 = 58975 , ARM64_SYSREG_ICH_VTR_EL2 = 58969 , ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196 , ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197 , ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192 , ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193 , ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200 , ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201 , ARM64_SYSREG_ID_AA64ISAR2_EL1 = 49202 , ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208 , ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209 , ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210 , ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184 , ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185 , ARM64_SYSREG_ID_AA64SMFR0_EL1 = 49189 , ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188 , ARM64_SYSREG_ID_AFR0_EL1 = 49163 , ARM64_SYSREG_ID_DFR0_EL1 = 49162 , ARM64_SYSREG_ID_ISAR0_EL1 = 49168 , ARM64_SYSREG_ID_ISAR1_EL1 = 49169 , ARM64_SYSREG_ID_ISAR2_EL1 = 49170 , ARM64_SYSREG_ID_ISAR3_EL1 = 49171 , ARM64_SYSREG_ID_ISAR4_EL1 = 49172 , ARM64_SYSREG_ID_ISAR5_EL1 = 49173 , ARM64_SYSREG_ID_ISAR6_EL1 = 49175 , ARM64_SYSREG_ID_MMFR0_EL1 = 49164 , ARM64_SYSREG_ID_MMFR1_EL1 = 49165 , ARM64_SYSREG_ID_MMFR2_EL1 = 49166 , ARM64_SYSREG_ID_MMFR3_EL1 = 49167 , ARM64_SYSREG_ID_MMFR4_EL1 = 49174 , ARM64_SYSREG_ID_MMFR5_EL1 = 49182 , ARM64_SYSREG_ID_PFR0_EL1 = 49160 , ARM64_SYSREG_ID_PFR1_EL1 = 49161 , ARM64_SYSREG_ID_PFR2_EL1 = 49180 , ARM64_SYSREG_IFSR32_EL2 = 57985 , ARM64_SYSREG_ISR_EL1 = 50696 , ARM64_SYSREG_LORC_EL1 = 50467 , ARM64_SYSREG_LOREA_EL1 = 50465 , ARM64_SYSREG_LORID_EL1 = 50471 , ARM64_SYSREG_LORN_EL1 = 50466 , ARM64_SYSREG_LORSA_EL1 = 50464 , ARM64_SYSREG_MAIR_EL1 = 50448 , ARM64_SYSREG_MAIR_EL12 = 60688 , ARM64_SYSREG_MAIR_EL2 = 58640 , ARM64_SYSREG_MAIR_EL3 = 62736 , ARM64_SYSREG_MDCCINT_EL1 = 32784 , ARM64_SYSREG_MDCCSR_EL0 = 38920 , ARM64_SYSREG_MDCR_EL2 = 57481 , ARM64_SYSREG_MDCR_EL3 = 61593 , ARM64_SYSREG_MDRAR_EL1 = 32896 , ARM64_SYSREG_MDSCR_EL1 = 32786 , ARM64_SYSREG_MFAR_EL3 = 62213 , ARM64_SYSREG_MIDR_EL1 = 49152 , ARM64_SYSREG_MPAM0_EL1 = 50473 , ARM64_SYSREG_MPAM1_EL1 = 50472 , ARM64_SYSREG_MPAM1_EL12 = 60712 , ARM64_SYSREG_MPAM2_EL2 = 58664 , ARM64_SYSREG_MPAM3_EL3 = 62760 , ARM64_SYSREG_MPAMHCR_EL2 = 58656 , ARM64_SYSREG_MPAMIDR_EL1 = 50468 , ARM64_SYSREG_MPAMSM_EL1 = 50475 , ARM64_SYSREG_MPAMVPM0_EL2 = 58672 , ARM64_SYSREG_MPAMVPM1_EL2 = 58673 , ARM64_SYSREG_MPAMVPM2_EL2 = 58674 , ARM64_SYSREG_MPAMVPM3_EL2 = 58675 , ARM64_SYSREG_MPAMVPM4_EL2 = 58676 , ARM64_SYSREG_MPAMVPM5_EL2 = 58677 , ARM64_SYSREG_MPAMVPM6_EL2 = 58678 , ARM64_SYSREG_MPAMVPM7_EL2 = 58679 , ARM64_SYSREG_MPAMVPMV_EL2 = 58657 , ARM64_SYSREG_MPIDR_EL1 = 49157 , ARM64_SYSREG_MPUIR_EL1 = 49156 , ARM64_SYSREG_MPUIR_EL2 = 57348 , ARM64_SYSREG_MVFR0_EL1 = 49176 , ARM64_SYSREG_MVFR1_EL1 = 49177 , ARM64_SYSREG_MVFR2_EL1 = 49178 , ARM64_SYSREG_NZCV = 55824 , ARM64_SYSREG_OSDLR_EL1 = 32924 , ARM64_SYSREG_OSDTRRX_EL1 = 32770 , ARM64_SYSREG_OSDTRTX_EL1 = 32794 , ARM64_SYSREG_OSECCR_EL1 = 32818 , ARM64_SYSREG_OSLAR_EL1 = 32900 , ARM64_SYSREG_OSLSR_EL1 = 32908 , ARM64_SYSREG_PAN = 49683 , ARM64_SYSREG_PAR_EL1 = 50080 , ARM64_SYSREG_PMBIDR_EL1 = 50391 , ARM64_SYSREG_PMBLIMITR_EL1 = 50384 , ARM64_SYSREG_PMBPTR_EL1 = 50385 , ARM64_SYSREG_PMBSR_EL1 = 50387 , ARM64_SYSREG_PMCCFILTR_EL0 = 57215 , ARM64_SYSREG_PMCCNTR_EL0 = 56552 , ARM64_SYSREG_PMCEID0_EL0 = 56550 , ARM64_SYSREG_PMCEID1_EL0 = 56551 , ARM64_SYSREG_PMCNTENCLR_EL0 = 56546 , ARM64_SYSREG_PMCNTENSET_EL0 = 56545 , ARM64_SYSREG_PMCR_EL0 = 56544 , ARM64_SYSREG_PMEVCNTR0_EL0 = 57152 , ARM64_SYSREG_PMEVCNTR10_EL0 = 57162 , ARM64_SYSREG_PMEVCNTR11_EL0 = 57163 , ARM64_SYSREG_PMEVCNTR12_EL0 = 57164 , ARM64_SYSREG_PMEVCNTR13_EL0 = 57165 , ARM64_SYSREG_PMEVCNTR14_EL0 = 57166 , ARM64_SYSREG_PMEVCNTR15_EL0 = 57167 , ARM64_SYSREG_PMEVCNTR16_EL0 = 57168 , ARM64_SYSREG_PMEVCNTR17_EL0 = 57169 , ARM64_SYSREG_PMEVCNTR18_EL0 = 57170 , ARM64_SYSREG_PMEVCNTR19_EL0 = 57171 , ARM64_SYSREG_PMEVCNTR1_EL0 = 57153 , ARM64_SYSREG_PMEVCNTR20_EL0 = 57172 , ARM64_SYSREG_PMEVCNTR21_EL0 = 57173 , ARM64_SYSREG_PMEVCNTR22_EL0 = 57174 , ARM64_SYSREG_PMEVCNTR23_EL0 = 57175 , ARM64_SYSREG_PMEVCNTR24_EL0 = 57176 , ARM64_SYSREG_PMEVCNTR25_EL0 = 57177 , ARM64_SYSREG_PMEVCNTR26_EL0 = 57178 , ARM64_SYSREG_PMEVCNTR27_EL0 = 57179 , ARM64_SYSREG_PMEVCNTR28_EL0 = 57180 , ARM64_SYSREG_PMEVCNTR29_EL0 = 57181 , ARM64_SYSREG_PMEVCNTR2_EL0 = 57154 , ARM64_SYSREG_PMEVCNTR30_EL0 = 57182 , ARM64_SYSREG_PMEVCNTR3_EL0 = 57155 , ARM64_SYSREG_PMEVCNTR4_EL0 = 57156 , ARM64_SYSREG_PMEVCNTR5_EL0 = 57157 , ARM64_SYSREG_PMEVCNTR6_EL0 = 57158 , ARM64_SYSREG_PMEVCNTR7_EL0 = 57159 , ARM64_SYSREG_PMEVCNTR8_EL0 = 57160 , ARM64_SYSREG_PMEVCNTR9_EL0 = 57161 , ARM64_SYSREG_PMEVTYPER0_EL0 = 57184 , ARM64_SYSREG_PMEVTYPER10_EL0 = 57194 , ARM64_SYSREG_PMEVTYPER11_EL0 = 57195 , ARM64_SYSREG_PMEVTYPER12_EL0 = 57196 , ARM64_SYSREG_PMEVTYPER13_EL0 = 57197 , ARM64_SYSREG_PMEVTYPER14_EL0 = 57198 , ARM64_SYSREG_PMEVTYPER15_EL0 = 57199 , ARM64_SYSREG_PMEVTYPER16_EL0 = 57200 , ARM64_SYSREG_PMEVTYPER17_EL0 = 57201 , ARM64_SYSREG_PMEVTYPER18_EL0 = 57202 , ARM64_SYSREG_PMEVTYPER19_EL0 = 57203 , ARM64_SYSREG_PMEVTYPER1_EL0 = 57185 , ARM64_SYSREG_PMEVTYPER20_EL0 = 57204 , ARM64_SYSREG_PMEVTYPER21_EL0 = 57205 , ARM64_SYSREG_PMEVTYPER22_EL0 = 57206 , ARM64_SYSREG_PMEVTYPER23_EL0 = 57207 , ARM64_SYSREG_PMEVTYPER24_EL0 = 57208 , ARM64_SYSREG_PMEVTYPER25_EL0 = 57209 , ARM64_SYSREG_PMEVTYPER26_EL0 = 57210 , ARM64_SYSREG_PMEVTYPER27_EL0 = 57211 , ARM64_SYSREG_PMEVTYPER28_EL0 = 57212 , ARM64_SYSREG_PMEVTYPER29_EL0 = 57213 , ARM64_SYSREG_PMEVTYPER2_EL0 = 57186 , ARM64_SYSREG_PMEVTYPER30_EL0 = 57214 , ARM64_SYSREG_PMEVTYPER3_EL0 = 57187 , ARM64_SYSREG_PMEVTYPER4_EL0 = 57188 , ARM64_SYSREG_PMEVTYPER5_EL0 = 57189 , ARM64_SYSREG_PMEVTYPER6_EL0 = 57190 , ARM64_SYSREG_PMEVTYPER7_EL0 = 57191 , ARM64_SYSREG_PMEVTYPER8_EL0 = 57192 , ARM64_SYSREG_PMEVTYPER9_EL0 = 57193 , ARM64_SYSREG_PMINTENCLR_EL1 = 50418 , ARM64_SYSREG_PMINTENSET_EL1 = 50417 , ARM64_SYSREG_PMMIR_EL1 = 50422 , ARM64_SYSREG_PMOVSCLR_EL0 = 56547 , ARM64_SYSREG_PMOVSSET_EL0 = 56563 , ARM64_SYSREG_PMSCR_EL1 = 50376 , ARM64_SYSREG_PMSCR_EL12 = 60616 , ARM64_SYSREG_PMSCR_EL2 = 58568 , ARM64_SYSREG_PMSELR_EL0 = 56549 , ARM64_SYSREG_PMSEVFR_EL1 = 50381 , ARM64_SYSREG_PMSFCR_EL1 = 50380 , ARM64_SYSREG_PMSICR_EL1 = 50378 , ARM64_SYSREG_PMSIDR_EL1 = 50383 , ARM64_SYSREG_PMSIRR_EL1 = 50379 , ARM64_SYSREG_PMSLATFR_EL1 = 50382 , ARM64_SYSREG_PMSNEVFR_EL1 = 50377 , ARM64_SYSREG_PMSWINC_EL0 = 56548 , ARM64_SYSREG_PMUSERENR_EL0 = 56560 , ARM64_SYSREG_PMXEVCNTR_EL0 = 56554 , ARM64_SYSREG_PMXEVTYPER_EL0 = 56553 , ARM64_SYSREG_PRBAR10_EL1 = 50024 , ARM64_SYSREG_PRBAR10_EL2 = 58216 , ARM64_SYSREG_PRBAR11_EL1 = 50028 , ARM64_SYSREG_PRBAR11_EL2 = 58220 , ARM64_SYSREG_PRBAR12_EL1 = 50032 , ARM64_SYSREG_PRBAR12_EL2 = 58224 , ARM64_SYSREG_PRBAR13_EL1 = 50036 , ARM64_SYSREG_PRBAR13_EL2 = 58228 , ARM64_SYSREG_PRBAR14_EL1 = 50040 , ARM64_SYSREG_PRBAR14_EL2 = 58232 , ARM64_SYSREG_PRBAR15_EL1 = 50044 , ARM64_SYSREG_PRBAR15_EL2 = 58236 , ARM64_SYSREG_PRBAR1_EL1 = 49988 , ARM64_SYSREG_PRBAR1_EL2 = 58180 , ARM64_SYSREG_PRBAR2_EL1 = 49992 , ARM64_SYSREG_PRBAR2_EL2 = 58184 , ARM64_SYSREG_PRBAR3_EL1 = 49996 , ARM64_SYSREG_PRBAR3_EL2 = 58188 , ARM64_SYSREG_PRBAR4_EL1 = 50000 , ARM64_SYSREG_PRBAR4_EL2 = 58192 , ARM64_SYSREG_PRBAR5_EL1 = 50004 , ARM64_SYSREG_PRBAR5_EL2 = 58196 , ARM64_SYSREG_PRBAR6_EL1 = 50008 , ARM64_SYSREG_PRBAR6_EL2 = 58200 , ARM64_SYSREG_PRBAR7_EL1 = 50012 , ARM64_SYSREG_PRBAR7_EL2 = 58204 , ARM64_SYSREG_PRBAR8_EL1 = 50016 , ARM64_SYSREG_PRBAR8_EL2 = 58208 , ARM64_SYSREG_PRBAR9_EL1 = 50020 , ARM64_SYSREG_PRBAR9_EL2 = 58212 , ARM64_SYSREG_PRBAR_EL1 = 49984 , ARM64_SYSREG_PRBAR_EL2 = 58176 , ARM64_SYSREG_PRENR_EL1 = 49929 , ARM64_SYSREG_PRENR_EL2 = 58121 , ARM64_SYSREG_PRLAR10_EL1 = 50025 , ARM64_SYSREG_PRLAR10_EL2 = 58217 , ARM64_SYSREG_PRLAR11_EL1 = 50029 , ARM64_SYSREG_PRLAR11_EL2 = 58221 , ARM64_SYSREG_PRLAR12_EL1 = 50033 , ARM64_SYSREG_PRLAR12_EL2 = 58225 , ARM64_SYSREG_PRLAR13_EL1 = 50037 , ARM64_SYSREG_PRLAR13_EL2 = 58229 , ARM64_SYSREG_PRLAR14_EL1 = 50041 , ARM64_SYSREG_PRLAR14_EL2 = 58233 , ARM64_SYSREG_PRLAR15_EL1 = 50045 , ARM64_SYSREG_PRLAR15_EL2 = 58237 , ARM64_SYSREG_PRLAR1_EL1 = 49989 , ARM64_SYSREG_PRLAR1_EL2 = 58181 , ARM64_SYSREG_PRLAR2_EL1 = 49993 , ARM64_SYSREG_PRLAR2_EL2 = 58185 , ARM64_SYSREG_PRLAR3_EL1 = 49997 , ARM64_SYSREG_PRLAR3_EL2 = 58189 , ARM64_SYSREG_PRLAR4_EL1 = 50001 , ARM64_SYSREG_PRLAR4_EL2 = 58193 , ARM64_SYSREG_PRLAR5_EL1 = 50005 , ARM64_SYSREG_PRLAR5_EL2 = 58197 , ARM64_SYSREG_PRLAR6_EL1 = 50009 , ARM64_SYSREG_PRLAR6_EL2 = 58201 , ARM64_SYSREG_PRLAR7_EL1 = 50013 , ARM64_SYSREG_PRLAR7_EL2 = 58205 , ARM64_SYSREG_PRLAR8_EL1 = 50017 , ARM64_SYSREG_PRLAR8_EL2 = 58209 , ARM64_SYSREG_PRLAR9_EL1 = 50021 , ARM64_SYSREG_PRLAR9_EL2 = 58213 , ARM64_SYSREG_PRLAR_EL1 = 49985 , ARM64_SYSREG_PRLAR_EL2 = 58177 , ARM64_SYSREG_PRSELR_EL1 = 49937 , ARM64_SYSREG_PRSELR_EL2 = 58129 , ARM64_SYSREG_REVIDR_EL1 = 49158 , ARM64_SYSREG_RGSR_EL1 = 49285 , ARM64_SYSREG_RMR_EL1 = 50690 , ARM64_SYSREG_RMR_EL2 = 58882 , ARM64_SYSREG_RMR_EL3 = 62978 , ARM64_SYSREG_RNDR = 55584 , ARM64_SYSREG_RNDRRS = 55585 , ARM64_SYSREG_RVBAR_EL1 = 50689 , ARM64_SYSREG_RVBAR_EL2 = 58881 , ARM64_SYSREG_RVBAR_EL3 = 62977 , ARM64_SYSREG_SCR_EL3 = 61576 , ARM64_SYSREG_SCTLR_EL1 = 49280 , ARM64_SYSREG_SCTLR_EL12 = 59520 , ARM64_SYSREG_SCTLR_EL2 = 57472 , ARM64_SYSREG_SCTLR_EL3 = 61568 , ARM64_SYSREG_SCXTNUM_EL0 = 56967 , ARM64_SYSREG_SCXTNUM_EL1 = 50823 , ARM64_SYSREG_SCXTNUM_EL12 = 61063 , ARM64_SYSREG_SCXTNUM_EL2 = 59015 , ARM64_SYSREG_SCXTNUM_EL3 = 63111 , ARM64_SYSREG_SDER32_EL2 = 57497 , ARM64_SYSREG_SDER32_EL3 = 61577 , ARM64_SYSREG_SMCR_EL1 = 49302 , ARM64_SYSREG_SMCR_EL12 = 59542 , ARM64_SYSREG_SMCR_EL2 = 57494 , ARM64_SYSREG_SMCR_EL3 = 61590 , ARM64_SYSREG_SMIDR_EL1 = 51206 , ARM64_SYSREG_SMPRIMAP_EL2 = 57493 , ARM64_SYSREG_SMPRI_EL1 = 49300 , ARM64_SYSREG_SPSEL = 49680 , ARM64_SYSREG_SPSR_ABT = 57881 , ARM64_SYSREG_SPSR_EL1 = 49664 , ARM64_SYSREG_SPSR_EL12 = 59904 , ARM64_SYSREG_SPSR_EL2 = 57856 , ARM64_SYSREG_SPSR_EL3 = 61952 , ARM64_SYSREG_SPSR_FIQ = 57883 , ARM64_SYSREG_SPSR_IRQ = 57880 , ARM64_SYSREG_SPSR_UND = 57882 , ARM64_SYSREG_SP_EL0 = 49672 , ARM64_SYSREG_SP_EL1 = 57864 , ARM64_SYSREG_SP_EL2 = 61960 , ARM64_SYSREG_SSBS = 55830 , ARM64_SYSREG_SVCR = 55826 , ARM64_SYSREG_TCO = 55831 , ARM64_SYSREG_TCR_EL1 = 49410 , ARM64_SYSREG_TCR_EL12 = 59650 , ARM64_SYSREG_TCR_EL2 = 57602 , ARM64_SYSREG_TCR_EL3 = 61698 , ARM64_SYSREG_TEECR32_EL1 = 36864 , ARM64_SYSREG_TEEHBR32_EL1 = 36992 , ARM64_SYSREG_TFSRE0_EL1 = 49841 , ARM64_SYSREG_TFSR_EL1 = 49840 , ARM64_SYSREG_TFSR_EL12 = 60080 , ARM64_SYSREG_TFSR_EL2 = 58032 , ARM64_SYSREG_TFSR_EL3 = 62128 , ARM64_SYSREG_TPIDR2_EL0 = 56965 , ARM64_SYSREG_TPIDRRO_EL0 = 56963 , ARM64_SYSREG_TPIDR_EL0 = 56962 , ARM64_SYSREG_TPIDR_EL1 = 50820 , ARM64_SYSREG_TPIDR_EL2 = 59010 , ARM64_SYSREG_TPIDR_EL3 = 63106 , ARM64_SYSREG_TRBBASER_EL1 = 50394 , ARM64_SYSREG_TRBIDR_EL1 = 50399 , ARM64_SYSREG_TRBLIMITR_EL1 = 50392 , ARM64_SYSREG_TRBMAR_EL1 = 50396 , ARM64_SYSREG_TRBPTR_EL1 = 50393 , ARM64_SYSREG_TRBSR_EL1 = 50395 , ARM64_SYSREG_TRBTRG_EL1 = 50398 , ARM64_SYSREG_TRCACATR0 = 35074 , ARM64_SYSREG_TRCACATR1 = 35090 , ARM64_SYSREG_TRCACATR10 = 35107 , ARM64_SYSREG_TRCACATR11 = 35123 , ARM64_SYSREG_TRCACATR12 = 35139 , ARM64_SYSREG_TRCACATR13 = 35155 , ARM64_SYSREG_TRCACATR14 = 35171 , ARM64_SYSREG_TRCACATR15 = 35187 , ARM64_SYSREG_TRCACATR2 = 35106 , ARM64_SYSREG_TRCACATR3 = 35122 , ARM64_SYSREG_TRCACATR4 = 35138 , ARM64_SYSREG_TRCACATR5 = 35154 , ARM64_SYSREG_TRCACATR6 = 35170 , ARM64_SYSREG_TRCACATR7 = 35186 , ARM64_SYSREG_TRCACATR8 = 35075 , ARM64_SYSREG_TRCACATR9 = 35091 , ARM64_SYSREG_TRCACVR0 = 35072 , ARM64_SYSREG_TRCACVR1 = 35088 , ARM64_SYSREG_TRCACVR10 = 35105 , ARM64_SYSREG_TRCACVR11 = 35121 , ARM64_SYSREG_TRCACVR12 = 35137 , ARM64_SYSREG_TRCACVR13 = 35153 , ARM64_SYSREG_TRCACVR14 = 35169 , ARM64_SYSREG_TRCACVR15 = 35185 , ARM64_SYSREG_TRCACVR2 = 35104 , ARM64_SYSREG_TRCACVR3 = 35120 , ARM64_SYSREG_TRCACVR4 = 35136 , ARM64_SYSREG_TRCACVR5 = 35152 , ARM64_SYSREG_TRCACVR6 = 35168 , ARM64_SYSREG_TRCACVR7 = 35184 , ARM64_SYSREG_TRCACVR8 = 35073 , ARM64_SYSREG_TRCACVR9 = 35089 , ARM64_SYSREG_TRCAUTHSTATUS = 35830 , ARM64_SYSREG_TRCAUXCTLR = 34864 , ARM64_SYSREG_TRCBBCTLR = 34936 , ARM64_SYSREG_TRCCCCTLR = 34928 , ARM64_SYSREG_TRCCIDCCTLR0 = 35202 , ARM64_SYSREG_TRCCIDCCTLR1 = 35210 , ARM64_SYSREG_TRCCIDCVR0 = 35200 , ARM64_SYSREG_TRCCIDCVR1 = 35216 , ARM64_SYSREG_TRCCIDCVR2 = 35232 , ARM64_SYSREG_TRCCIDCVR3 = 35248 , ARM64_SYSREG_TRCCIDCVR4 = 35264 , ARM64_SYSREG_TRCCIDCVR5 = 35280 , ARM64_SYSREG_TRCCIDCVR6 = 35296 , ARM64_SYSREG_TRCCIDCVR7 = 35312 , ARM64_SYSREG_TRCCIDR0 = 35815 , ARM64_SYSREG_TRCCIDR1 = 35823 , ARM64_SYSREG_TRCCIDR2 = 35831 , ARM64_SYSREG_TRCCIDR3 = 35839 , ARM64_SYSREG_TRCCLAIMCLR = 35790 , ARM64_SYSREG_TRCCLAIMSET = 35782 , ARM64_SYSREG_TRCCNTCTLR0 = 34853 , ARM64_SYSREG_TRCCNTCTLR1 = 34861 , ARM64_SYSREG_TRCCNTCTLR2 = 34869 , ARM64_SYSREG_TRCCNTCTLR3 = 34877 , ARM64_SYSREG_TRCCNTRLDVR0 = 34821 , ARM64_SYSREG_TRCCNTRLDVR1 = 34829 , ARM64_SYSREG_TRCCNTRLDVR2 = 34837 , ARM64_SYSREG_TRCCNTRLDVR3 = 34845 , ARM64_SYSREG_TRCCNTVR0 = 34885 , ARM64_SYSREG_TRCCNTVR1 = 34893 , ARM64_SYSREG_TRCCNTVR2 = 34901 , ARM64_SYSREG_TRCCNTVR3 = 34909 , ARM64_SYSREG_TRCCONFIGR = 34848 , ARM64_SYSREG_TRCDEVAFF0 = 35798 , ARM64_SYSREG_TRCDEVAFF1 = 35806 , ARM64_SYSREG_TRCDEVARCH = 35838 , ARM64_SYSREG_TRCDEVID = 35735 , ARM64_SYSREG_TRCDEVTYPE = 35743 , ARM64_SYSREG_TRCDVCMR0 = 35078 , ARM64_SYSREG_TRCDVCMR1 = 35110 , ARM64_SYSREG_TRCDVCMR2 = 35142 , ARM64_SYSREG_TRCDVCMR3 = 35174 , ARM64_SYSREG_TRCDVCMR4 = 35079 , ARM64_SYSREG_TRCDVCMR5 = 35111 , ARM64_SYSREG_TRCDVCMR6 = 35143 , ARM64_SYSREG_TRCDVCMR7 = 35175 , ARM64_SYSREG_TRCDVCVR0 = 35076 , ARM64_SYSREG_TRCDVCVR1 = 35108 , ARM64_SYSREG_TRCDVCVR2 = 35140 , ARM64_SYSREG_TRCDVCVR3 = 35172 , ARM64_SYSREG_TRCDVCVR4 = 35077 , ARM64_SYSREG_TRCDVCVR5 = 35109 , ARM64_SYSREG_TRCDVCVR6 = 35141 , ARM64_SYSREG_TRCDVCVR7 = 35173 , ARM64_SYSREG_TRCEVENTCTL0R = 34880 , ARM64_SYSREG_TRCEVENTCTL1R = 34888 , ARM64_SYSREG_TRCEXTINSELR = 34884 , ARM64_SYSREG_TRCEXTINSELR1 = 34892 , ARM64_SYSREG_TRCEXTINSELR2 = 34900 , ARM64_SYSREG_TRCEXTINSELR3 = 34908 , ARM64_SYSREG_TRCIDR0 = 34887 , ARM64_SYSREG_TRCIDR1 = 34895 , ARM64_SYSREG_TRCIDR10 = 34838 , ARM64_SYSREG_TRCIDR11 = 34846 , ARM64_SYSREG_TRCIDR12 = 34854 , ARM64_SYSREG_TRCIDR13 = 34862 , ARM64_SYSREG_TRCIDR2 = 34903 , ARM64_SYSREG_TRCIDR3 = 34911 , ARM64_SYSREG_TRCIDR4 = 34919 , ARM64_SYSREG_TRCIDR5 = 34927 , ARM64_SYSREG_TRCIDR6 = 34935 , ARM64_SYSREG_TRCIDR7 = 34943 , ARM64_SYSREG_TRCIDR8 = 34822 , ARM64_SYSREG_TRCIDR9 = 34830 , ARM64_SYSREG_TRCIMSPEC0 = 34823 , ARM64_SYSREG_TRCIMSPEC1 = 34831 , ARM64_SYSREG_TRCIMSPEC2 = 34839 , ARM64_SYSREG_TRCIMSPEC3 = 34847 , ARM64_SYSREG_TRCIMSPEC4 = 34855 , ARM64_SYSREG_TRCIMSPEC5 = 34863 , ARM64_SYSREG_TRCIMSPEC6 = 34871 , ARM64_SYSREG_TRCIMSPEC7 = 34879 , ARM64_SYSREG_TRCITCTRL = 35716 , ARM64_SYSREG_TRCLAR = 35814 , ARM64_SYSREG_TRCLSR = 35822 , ARM64_SYSREG_TRCOSLAR = 34948 , ARM64_SYSREG_TRCOSLSR = 34956 , ARM64_SYSREG_TRCPDCR = 34980 , ARM64_SYSREG_TRCPDSR = 34988 , ARM64_SYSREG_TRCPIDR0 = 35783 , ARM64_SYSREG_TRCPIDR1 = 35791 , ARM64_SYSREG_TRCPIDR2 = 35799 , ARM64_SYSREG_TRCPIDR3 = 35807 , ARM64_SYSREG_TRCPIDR4 = 35751 , ARM64_SYSREG_TRCPIDR5 = 35759 , ARM64_SYSREG_TRCPIDR6 = 35767 , ARM64_SYSREG_TRCPIDR7 = 35775 , ARM64_SYSREG_TRCPRGCTLR = 34824 , ARM64_SYSREG_TRCPROCSELR = 34832 , ARM64_SYSREG_TRCQCTLR = 34825 , ARM64_SYSREG_TRCRSCTLR10 = 35024 , ARM64_SYSREG_TRCRSCTLR11 = 35032 , ARM64_SYSREG_TRCRSCTLR12 = 35040 , ARM64_SYSREG_TRCRSCTLR13 = 35048 , ARM64_SYSREG_TRCRSCTLR14 = 35056 , ARM64_SYSREG_TRCRSCTLR15 = 35064 , ARM64_SYSREG_TRCRSCTLR16 = 34945 , ARM64_SYSREG_TRCRSCTLR17 = 34953 , ARM64_SYSREG_TRCRSCTLR18 = 34961 , ARM64_SYSREG_TRCRSCTLR19 = 34969 , ARM64_SYSREG_TRCRSCTLR2 = 34960 , ARM64_SYSREG_TRCRSCTLR20 = 34977 , ARM64_SYSREG_TRCRSCTLR21 = 34985 , ARM64_SYSREG_TRCRSCTLR22 = 34993 , ARM64_SYSREG_TRCRSCTLR23 = 35001 , ARM64_SYSREG_TRCRSCTLR24 = 35009 , ARM64_SYSREG_TRCRSCTLR25 = 35017 , ARM64_SYSREG_TRCRSCTLR26 = 35025 , ARM64_SYSREG_TRCRSCTLR27 = 35033 , ARM64_SYSREG_TRCRSCTLR28 = 35041 , ARM64_SYSREG_TRCRSCTLR29 = 35049 , ARM64_SYSREG_TRCRSCTLR3 = 34968 , ARM64_SYSREG_TRCRSCTLR30 = 35057 , ARM64_SYSREG_TRCRSCTLR31 = 35065 , ARM64_SYSREG_TRCRSCTLR4 = 34976 , ARM64_SYSREG_TRCRSCTLR5 = 34984 , ARM64_SYSREG_TRCRSCTLR6 = 34992 , ARM64_SYSREG_TRCRSCTLR7 = 35000 , ARM64_SYSREG_TRCRSCTLR8 = 35008 , ARM64_SYSREG_TRCRSCTLR9 = 35016 , ARM64_SYSREG_TRCRSR = 34896 , ARM64_SYSREG_TRCSEQEVR0 = 34820 , ARM64_SYSREG_TRCSEQEVR1 = 34828 , ARM64_SYSREG_TRCSEQEVR2 = 34836 , ARM64_SYSREG_TRCSEQRSTEVR = 34868 , ARM64_SYSREG_TRCSEQSTR = 34876 , ARM64_SYSREG_TRCSSCCR0 = 34946 , ARM64_SYSREG_TRCSSCCR1 = 34954 , ARM64_SYSREG_TRCSSCCR2 = 34962 , ARM64_SYSREG_TRCSSCCR3 = 34970 , ARM64_SYSREG_TRCSSCCR4 = 34978 , ARM64_SYSREG_TRCSSCCR5 = 34986 , ARM64_SYSREG_TRCSSCCR6 = 34994 , ARM64_SYSREG_TRCSSCCR7 = 35002 , ARM64_SYSREG_TRCSSCSR0 = 35010 , ARM64_SYSREG_TRCSSCSR1 = 35018 , ARM64_SYSREG_TRCSSCSR2 = 35026 , ARM64_SYSREG_TRCSSCSR3 = 35034 , ARM64_SYSREG_TRCSSCSR4 = 35042 , ARM64_SYSREG_TRCSSCSR5 = 35050 , ARM64_SYSREG_TRCSSCSR6 = 35058 , ARM64_SYSREG_TRCSSCSR7 = 35066 , ARM64_SYSREG_TRCSSPCICR0 = 34947 , ARM64_SYSREG_TRCSSPCICR1 = 34955 , ARM64_SYSREG_TRCSSPCICR2 = 34963 , ARM64_SYSREG_TRCSSPCICR3 = 34971 , ARM64_SYSREG_TRCSSPCICR4 = 34979 , ARM64_SYSREG_TRCSSPCICR5 = 34987 , ARM64_SYSREG_TRCSSPCICR6 = 34995 , ARM64_SYSREG_TRCSSPCICR7 = 35003 , ARM64_SYSREG_TRCSTALLCTLR = 34904 , ARM64_SYSREG_TRCSTATR = 34840 , ARM64_SYSREG_TRCSYNCPR = 34920 , ARM64_SYSREG_TRCTRACEIDR = 34817 , ARM64_SYSREG_TRCTSCTLR = 34912 , ARM64_SYSREG_TRCVDARCCTLR = 34898 , ARM64_SYSREG_TRCVDCTLR = 34882 , ARM64_SYSREG_TRCVDSACCTLR = 34890 , ARM64_SYSREG_TRCVICTLR = 34818 , ARM64_SYSREG_TRCVIIECTLR = 34826 , ARM64_SYSREG_TRCVIPCSSCTLR = 34842 , ARM64_SYSREG_TRCVISSCTLR = 34834 , ARM64_SYSREG_TRCVMIDCCTLR0 = 35218 , ARM64_SYSREG_TRCVMIDCCTLR1 = 35226 , ARM64_SYSREG_TRCVMIDCVR0 = 35201 , ARM64_SYSREG_TRCVMIDCVR1 = 35217 , ARM64_SYSREG_TRCVMIDCVR2 = 35233 , ARM64_SYSREG_TRCVMIDCVR3 = 35249 , ARM64_SYSREG_TRCVMIDCVR4 = 35265 , ARM64_SYSREG_TRCVMIDCVR5 = 35281 , ARM64_SYSREG_TRCVMIDCVR6 = 35297 , ARM64_SYSREG_TRCVMIDCVR7 = 35313 , ARM64_SYSREG_TRFCR_EL1 = 49297 , ARM64_SYSREG_TRFCR_EL12 = 59537 , ARM64_SYSREG_TRFCR_EL2 = 57489 , ARM64_SYSREG_TTBR0_EL1 = 49408 , ARM64_SYSREG_TTBR0_EL12 = 59648 , ARM64_SYSREG_TTBR0_EL2 = 57600 , ARM64_SYSREG_TTBR0_EL3 = 61696 , ARM64_SYSREG_TTBR1_EL1 = 49409 , ARM64_SYSREG_TTBR1_EL12 = 59649 , ARM64_SYSREG_TTBR1_EL2 = 57601 , ARM64_SYSREG_UAO = 49684 , ARM64_SYSREG_VBAR_EL1 = 50688 , ARM64_SYSREG_VBAR_EL12 = 60928 , ARM64_SYSREG_VBAR_EL2 = 58880 , ARM64_SYSREG_VBAR_EL3 = 62976 , ARM64_SYSREG_VDISR_EL2 = 58889 , ARM64_SYSREG_VMPIDR_EL2 = 57349 , ARM64_SYSREG_VNCR_EL2 = 57616 , ARM64_SYSREG_VPIDR_EL2 = 57344 , ARM64_SYSREG_VSESR_EL2 = 58003 , ARM64_SYSREG_VSTCR_EL2 = 57650 , ARM64_SYSREG_VSTTBR_EL2 = 57648 , ARM64_SYSREG_VTCR_EL2 = 57610 , ARM64_SYSREG_VTTBR_EL2 = 57608 , ARM64_SYSREG_ZCR_EL1 = 49296 , ARM64_SYSREG_ZCR_EL12 = 59536 , ARM64_SYSREG_ZCR_EL2 = 57488 , ARM64_SYSREG_ZCR_EL3 = 61584 , } # [repr (u32)] # [doc = " System PState Field (MSR instruction)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_pstate { ARM64_PSTATE_INVALID = 0 , ARM64_PSTATE_SPSEL = 5 , ARM64_PSTATE_DAIFSET = 30 , ARM64_PSTATE_DAIFCLR = 31 , ARM64_PSTATE_PAN = 4 , ARM64_PSTATE_UAO = 3 , ARM64_PSTATE_DIT = 26 , } # [repr (u32)] # [doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_vas { ARM64_VAS_INVALID = 0 , ARM64_VAS_16B = 1 , ARM64_VAS_8B = 2 , ARM64_VAS_4B = 3 , ARM64_VAS_1B = 4 , ARM64_VAS_8H = 5 , ARM64_VAS_4H = 6 , ARM64_VAS_2H = 7 , ARM64_VAS_1H = 8 , ARM64_VAS_4S = 9 , ARM64_VAS_2S = 10 , ARM64_VAS_1S = 11 , ARM64_VAS_2D = 12 , ARM64_VAS_1D = 13 , ARM64_VAS_1Q = 14 , } # [repr (u32)] # [doc = " Memory barrier operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0 , ARM64_BARRIER_OSHLD = 1 , ARM64_BARRIER_OSHST = 2 , ARM64_BARRIER_OSH = 3 , ARM64_BARRIER_NSHLD = 5 , ARM64_BARRIER_NSHST = 6 , ARM64_BARRIER_NSH = 7 , ARM64_BARRIER_ISHLD = 9 , ARM64_BARRIER_ISHST = 10 , ARM64_BARRIER_ISH = 11 , ARM64_BARRIER_LD = 13 , ARM64_BARRIER_ST = 14 , ARM64_BARRIER_SY = 15 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM64_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM64_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM64_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM64_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM64_OP_FP = 4 , # [doc = "< C-Immediate"] ARM64_OP_CIMM = 64 , # [doc = "< MRS register operand."] ARM64_OP_REG_MRS = 65 , # [doc = "< MSR register operand."] ARM64_OP_REG_MSR = 66 , # [doc = "< PState operand."] ARM64_OP_PSTATE = 67 , # [doc = "< SYS operand for IC/DC/AT/TLBI instructions."] ARM64_OP_SYS = 68 , # [doc = "< SVCR operand for MSR SVCR instructions."] ARM64_OP_SVCR = 69 , # [doc = "< Prefetch operand (PRFM)."] ARM64_OP_PREFETCH = 70 , # [doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."] ARM64_OP_BARRIER = 71 , # [doc = "< SME instruction operand with with index."] ARM64_OP_SME_INDEX = 72 , } # [repr (u32)] # [doc = " SYS operands (IC/DC/AC/TLBI)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sys_op { ARM64_SYS_INVALID = 0 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1 = 1 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1IS = 2 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1ISNXS = 3 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1NXS = 4 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OS = 5 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OSNXS = 6 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2 = 7 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2IS = 8 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2ISNXS = 9 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2NXS = 10 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OS = 11 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OSNXS = 12 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3 = 13 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3IS = 14 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3ISNXS = 15 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3NXS = 16 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OS = 17 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OSNXS = 18 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1 = 19 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1IS = 20 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1ISNXS = 21 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1NXS = 22 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OS = 23 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OSNXS = 24 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1 = 25 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1IS = 26 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1ISNXS = 27 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1NXS = 28 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OS = 29 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OSNXS = 30 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1 = 31 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1IS = 32 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1ISNXS = 33 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1NXS = 34 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OS = 35 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OSNXS = 36 , # [doc = " TLBI operations"] ARM64_TLBI_PAALL = 37 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLNXS = 38 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOS = 39 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOSNXS = 40 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1 = 41 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1IS = 42 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1ISNXS = 43 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1NXS = 44 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OS = 45 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OSNXS = 46 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1 = 47 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1IS = 48 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1ISNXS = 49 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1NXS = 50 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OS = 51 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OSNXS = 52 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOS = 53 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOSNXS = 54 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOS = 55 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOSNXS = 56 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1 = 57 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1IS = 58 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1ISNXS = 59 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1NXS = 60 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OS = 61 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OSNXS = 62 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1 = 63 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1IS = 64 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1ISNXS = 65 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1NXS = 66 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OS = 67 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OSNXS = 68 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1 = 69 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1IS = 70 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1ISNXS = 71 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1NXS = 72 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OS = 73 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OSNXS = 74 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2 = 75 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2IS = 76 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2ISNXS = 77 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2NXS = 78 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OS = 79 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OSNXS = 80 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3 = 81 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3IS = 82 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3ISNXS = 83 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3NXS = 84 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OS = 85 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OSNXS = 86 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1 = 87 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1IS = 88 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1ISNXS = 89 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1NXS = 90 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OS = 91 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OSNXS = 92 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2 = 93 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2IS = 94 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2ISNXS = 95 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2NXS = 96 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OS = 97 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OSNXS = 98 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3 = 99 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3IS = 100 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3ISNXS = 101 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3NXS = 102 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OS = 103 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OSNXS = 104 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1 = 105 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1IS = 106 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1ISNXS = 107 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1NXS = 108 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OS = 109 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OSNXS = 110 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1 = 111 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1IS = 112 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1ISNXS = 113 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1NXS = 114 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OS = 115 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OSNXS = 116 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1 = 117 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1IS = 118 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1ISNXS = 119 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1NXS = 120 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OS = 121 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OSNXS = 122 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2 = 123 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2IS = 124 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2ISNXS = 125 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2NXS = 126 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OS = 127 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OSNXS = 128 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3 = 129 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3IS = 130 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3ISNXS = 131 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3NXS = 132 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OS = 133 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OSNXS = 134 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1 = 135 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1IS = 136 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1ISNXS = 137 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1NXS = 138 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OS = 139 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OSNXS = 140 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2 = 141 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2IS = 142 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2ISNXS = 143 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2NXS = 144 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OS = 145 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OSNXS = 146 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3 = 147 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3IS = 148 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3ISNXS = 149 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3NXS = 150 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OS = 151 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OSNXS = 152 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1 = 153 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1IS = 154 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1ISNXS = 155 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1NXS = 156 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OS = 157 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OSNXS = 158 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1 = 159 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1IS = 160 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1ISNXS = 161 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1NXS = 162 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OS = 163 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OSNXS = 164 , # [doc = " AT operations"] ARM64_AT_S1E1R = 165 , # [doc = " AT operations"] ARM64_AT_S1E2R = 166 , # [doc = " AT operations"] ARM64_AT_S1E3R = 167 , # [doc = " AT operations"] ARM64_AT_S1E1W = 168 , # [doc = " AT operations"] ARM64_AT_S1E2W = 169 , # [doc = " AT operations"] ARM64_AT_S1E3W = 170 , # [doc = " AT operations"] ARM64_AT_S1E0R = 171 , # [doc = " AT operations"] ARM64_AT_S1E0W = 172 , # [doc = " AT operations"] ARM64_AT_S12E1R = 173 , # [doc = " AT operations"] ARM64_AT_S12E1W = 174 , # [doc = " AT operations"] ARM64_AT_S12E0R = 175 , # [doc = " AT operations"] ARM64_AT_S12E0W = 176 , # [doc = " AT operations"] ARM64_AT_S1E1RP = 177 , # [doc = " AT operations"] ARM64_AT_S1E1WP = 178 , # [doc = " DC operations"] ARM64_DC_CGDSW = 179 , # [doc = " DC operations"] ARM64_DC_CGDVAC = 180 , # [doc = " DC operations"] ARM64_DC_CGDVADP = 181 , # [doc = " DC operations"] ARM64_DC_CGDVAP = 182 , # [doc = " DC operations"] ARM64_DC_CGSW = 183 , # [doc = " DC operations"] ARM64_DC_CGVAC = 184 , # [doc = " DC operations"] ARM64_DC_CGVADP = 185 , # [doc = " DC operations"] ARM64_DC_CGVAP = 186 , # [doc = " DC operations"] ARM64_DC_CIGDSW = 187 , # [doc = " DC operations"] ARM64_DC_CIGDVAC = 188 , # [doc = " DC operations"] ARM64_DC_CIGSW = 189 , # [doc = " DC operations"] ARM64_DC_CIGVAC = 190 , # [doc = " DC operations"] ARM64_DC_CISW = 191 , # [doc = " DC operations"] ARM64_DC_CIVAC = 192 , # [doc = " DC operations"] ARM64_DC_CSW = 193 , # [doc = " DC operations"] ARM64_DC_CVAC = 194 , # [doc = " DC operations"] ARM64_DC_CVADP = 195 , # [doc = " DC operations"] ARM64_DC_CVAP = 196 , # [doc = " DC operations"] ARM64_DC_CVAU = 197 , # [doc = " DC operations"] ARM64_DC_GVA = 198 , # [doc = " DC operations"] ARM64_DC_GZVA = 199 , # [doc = " DC operations"] ARM64_DC_IGDSW = 200 , # [doc = " DC operations"] ARM64_DC_IGDVAC = 201 , # [doc = " DC operations"] ARM64_DC_IGSW = 202 , # [doc = " DC operations"] ARM64_DC_IGVAC = 203 , # [doc = " DC operations"] ARM64_DC_ISW = 204 , # [doc = " DC operations"] ARM64_DC_IVAC = 205 , # [doc = " DC operations"] ARM64_DC_ZVA = 206 , # [doc = " IC operations"] ARM64_IC_IALLUIS = 207 , # [doc = " IC operations"] ARM64_IC_IALLU = 208 , # [doc = " IC operations"] ARM64_IC_IVAU = 209 , } # [repr (u32)] # [doc = " SVCR operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_svcr_op { ARM64_SVCR_INVALID = 0 , ARM64_SVCR_SVCRSM = 1 , ARM64_SVCR_SVCRSMZA = 3 , ARM64_SVCR_SVCRZA = 2 , } # [repr (u32)] # [doc = " Prefetch operations (PRFM)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0 , ARM64_PRFM_PLDL1KEEP = 1 , ARM64_PRFM_PLDL1STRM = 2 , ARM64_PRFM_PLDL2KEEP = 3 , ARM64_PRFM_PLDL2STRM = 4 , ARM64_PRFM_PLDL3KEEP = 5 , ARM64_PRFM_PLDL3STRM = 6 , ARM64_PRFM_PLIL1KEEP = 9 , ARM64_PRFM_PLIL1STRM = 10 , ARM64_PRFM_PLIL2KEEP = 11 , ARM64_PRFM_PLIL2STRM = 12 , ARM64_PRFM_PLIL3KEEP = 13 , ARM64_PRFM_PLIL3STRM = 14 , ARM64_PRFM_PSTL1KEEP = 17 , ARM64_PRFM_PSTL1STRM = 18 , ARM64_PRFM_PSTL2KEEP = 19 , ARM64_PRFM_PSTL2STRM = 20 , ARM64_PRFM_PSTL3KEEP = 21 , ARM64_PRFM_PSTL3STRM = 22 , } impl arm64_reg { pub const ARM64_REG_IP0 : arm64_reg = arm64_reg :: ARM64_REG_X16 ; } impl arm64_reg { pub const ARM64_REG_IP1 : arm64_reg = arm64_reg :: ARM64_REG_X17 ; } impl arm64_reg { pub const ARM64_REG_X29 : arm64_reg = arm64_reg :: ARM64_REG_FP ; } impl arm64_reg { pub const ARM64_REG_X30 : arm64_reg = arm64_reg :: ARM64_REG_LR ; } # [repr (u32)] # [doc = " ARM64 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_reg { ARM64_REG_INVALID = 0 , ARM64_REG_FFR = 1 , ARM64_REG_FP = 2 , ARM64_REG_LR = 3 , ARM64_REG_NZCV = 4 , ARM64_REG_SP = 5 , ARM64_REG_VG = 6 , ARM64_REG_WSP = 7 , ARM64_REG_WZR = 8 , ARM64_REG_XZR = 9 , ARM64_REG_ZA = 10 , ARM64_REG_B0 = 11 , ARM64_REG_B1 = 12 , ARM64_REG_B2 = 13 , ARM64_REG_B3 = 14 , ARM64_REG_B4 = 15 , ARM64_REG_B5 = 16 , ARM64_REG_B6 = 17 , ARM64_REG_B7 = 18 , ARM64_REG_B8 = 19 , ARM64_REG_B9 = 20 , ARM64_REG_B10 = 21 , ARM64_REG_B11 = 22 , ARM64_REG_B12 = 23 , ARM64_REG_B13 = 24 , ARM64_REG_B14 = 25 , ARM64_REG_B15 = 26 , ARM64_REG_B16 = 27 , ARM64_REG_B17 = 28 , ARM64_REG_B18 = 29 , ARM64_REG_B19 = 30 , ARM64_REG_B20 = 31 , ARM64_REG_B21 = 32 , ARM64_REG_B22 = 33 , ARM64_REG_B23 = 34 , ARM64_REG_B24 = 35 , ARM64_REG_B25 = 36 , ARM64_REG_B26 = 37 , ARM64_REG_B27 = 38 , ARM64_REG_B28 = 39 , ARM64_REG_B29 = 40 , ARM64_REG_B30 = 41 , ARM64_REG_B31 = 42 , ARM64_REG_D0 = 43 , ARM64_REG_D1 = 44 , ARM64_REG_D2 = 45 , ARM64_REG_D3 = 46 , ARM64_REG_D4 = 47 , ARM64_REG_D5 = 48 , ARM64_REG_D6 = 49 , ARM64_REG_D7 = 50 , ARM64_REG_D8 = 51 , ARM64_REG_D9 = 52 , ARM64_REG_D10 = 53 , ARM64_REG_D11 = 54 , ARM64_REG_D12 = 55 , ARM64_REG_D13 = 56 , ARM64_REG_D14 = 57 , ARM64_REG_D15 = 58 , ARM64_REG_D16 = 59 , ARM64_REG_D17 = 60 , ARM64_REG_D18 = 61 , ARM64_REG_D19 = 62 , ARM64_REG_D20 = 63 , ARM64_REG_D21 = 64 , ARM64_REG_D22 = 65 , ARM64_REG_D23 = 66 , ARM64_REG_D24 = 67 , ARM64_REG_D25 = 68 , ARM64_REG_D26 = 69 , ARM64_REG_D27 = 70 , ARM64_REG_D28 = 71 , ARM64_REG_D29 = 72 , ARM64_REG_D30 = 73 , ARM64_REG_D31 = 74 , ARM64_REG_H0 = 75 , ARM64_REG_H1 = 76 , ARM64_REG_H2 = 77 , ARM64_REG_H3 = 78 , ARM64_REG_H4 = 79 , ARM64_REG_H5 = 80 , ARM64_REG_H6 = 81 , ARM64_REG_H7 = 82 , ARM64_REG_H8 = 83 , ARM64_REG_H9 = 84 , ARM64_REG_H10 = 85 , ARM64_REG_H11 = 86 , ARM64_REG_H12 = 87 , ARM64_REG_H13 = 88 , ARM64_REG_H14 = 89 , ARM64_REG_H15 = 90 , ARM64_REG_H16 = 91 , ARM64_REG_H17 = 92 , ARM64_REG_H18 = 93 , ARM64_REG_H19 = 94 , ARM64_REG_H20 = 95 , ARM64_REG_H21 = 96 , ARM64_REG_H22 = 97 , ARM64_REG_H23 = 98 , ARM64_REG_H24 = 99 , ARM64_REG_H25 = 100 , ARM64_REG_H26 = 101 , ARM64_REG_H27 = 102 , ARM64_REG_H28 = 103 , ARM64_REG_H29 = 104 , ARM64_REG_H30 = 105 , ARM64_REG_H31 = 106 , ARM64_REG_P0 = 107 , ARM64_REG_P1 = 108 , ARM64_REG_P2 = 109 , ARM64_REG_P3 = 110 , ARM64_REG_P4 = 111 , ARM64_REG_P5 = 112 , ARM64_REG_P6 = 113 , ARM64_REG_P7 = 114 , ARM64_REG_P8 = 115 , ARM64_REG_P9 = 116 , ARM64_REG_P10 = 117 , ARM64_REG_P11 = 118 , ARM64_REG_P12 = 119 , ARM64_REG_P13 = 120 , ARM64_REG_P14 = 121 , ARM64_REG_P15 = 122 , ARM64_REG_Q0 = 123 , ARM64_REG_Q1 = 124 , ARM64_REG_Q2 = 125 , ARM64_REG_Q3 = 126 , ARM64_REG_Q4 = 127 , ARM64_REG_Q5 = 128 , ARM64_REG_Q6 = 129 , ARM64_REG_Q7 = 130 , ARM64_REG_Q8 = 131 , ARM64_REG_Q9 = 132 , ARM64_REG_Q10 = 133 , ARM64_REG_Q11 = 134 , ARM64_REG_Q12 = 135 , ARM64_REG_Q13 = 136 , ARM64_REG_Q14 = 137 , ARM64_REG_Q15 = 138 , ARM64_REG_Q16 = 139 , ARM64_REG_Q17 = 140 , ARM64_REG_Q18 = 141 , ARM64_REG_Q19 = 142 , ARM64_REG_Q20 = 143 , ARM64_REG_Q21 = 144 , ARM64_REG_Q22 = 145 , ARM64_REG_Q23 = 146 , ARM64_REG_Q24 = 147 , ARM64_REG_Q25 = 148 , ARM64_REG_Q26 = 149 , ARM64_REG_Q27 = 150 , ARM64_REG_Q28 = 151 , ARM64_REG_Q29 = 152 , ARM64_REG_Q30 = 153 , ARM64_REG_Q31 = 154 , ARM64_REG_S0 = 155 , ARM64_REG_S1 = 156 , ARM64_REG_S2 = 157 , ARM64_REG_S3 = 158 , ARM64_REG_S4 = 159 , ARM64_REG_S5 = 160 , ARM64_REG_S6 = 161 , ARM64_REG_S7 = 162 , ARM64_REG_S8 = 163 , ARM64_REG_S9 = 164 , ARM64_REG_S10 = 165 , ARM64_REG_S11 = 166 , ARM64_REG_S12 = 167 , ARM64_REG_S13 = 168 , ARM64_REG_S14 = 169 , ARM64_REG_S15 = 170 , ARM64_REG_S16 = 171 , ARM64_REG_S17 = 172 , ARM64_REG_S18 = 173 , ARM64_REG_S19 = 174 , ARM64_REG_S20 = 175 , ARM64_REG_S21 = 176 , ARM64_REG_S22 = 177 , ARM64_REG_S23 = 178 , ARM64_REG_S24 = 179 , ARM64_REG_S25 = 180 , ARM64_REG_S26 = 181 , ARM64_REG_S27 = 182 , ARM64_REG_S28 = 183 , ARM64_REG_S29 = 184 , ARM64_REG_S30 = 185 , ARM64_REG_S31 = 186 , ARM64_REG_W0 = 187 , ARM64_REG_W1 = 188 , ARM64_REG_W2 = 189 , ARM64_REG_W3 = 190 , ARM64_REG_W4 = 191 , ARM64_REG_W5 = 192 , ARM64_REG_W6 = 193 , ARM64_REG_W7 = 194 , ARM64_REG_W8 = 195 , ARM64_REG_W9 = 196 , ARM64_REG_W10 = 197 , ARM64_REG_W11 = 198 , ARM64_REG_W12 = 199 , ARM64_REG_W13 = 200 , ARM64_REG_W14 = 201 , ARM64_REG_W15 = 202 , ARM64_REG_W16 = 203 , ARM64_REG_W17 = 204 , ARM64_REG_W18 = 205 , ARM64_REG_W19 = 206 , ARM64_REG_W20 = 207 , ARM64_REG_W21 = 208 , ARM64_REG_W22 = 209 , ARM64_REG_W23 = 210 , ARM64_REG_W24 = 211 , ARM64_REG_W25 = 212 , ARM64_REG_W26 = 213 , ARM64_REG_W27 = 214 , ARM64_REG_W28 = 215 , ARM64_REG_W29 = 216 , ARM64_REG_W30 = 217 , ARM64_REG_X0 = 218 , ARM64_REG_X1 = 219 , ARM64_REG_X2 = 220 , ARM64_REG_X3 = 221 , ARM64_REG_X4 = 222 , ARM64_REG_X5 = 223 , ARM64_REG_X6 = 224 , ARM64_REG_X7 = 225 , ARM64_REG_X8 = 226 , ARM64_REG_X9 = 227 , ARM64_REG_X10 = 228 , ARM64_REG_X11 = 229 , ARM64_REG_X12 = 230 , ARM64_REG_X13 = 231 , ARM64_REG_X14 = 232 , ARM64_REG_X15 = 233 , ARM64_REG_X16 = 234 , ARM64_REG_X17 = 235 , ARM64_REG_X18 = 236 , ARM64_REG_X19 = 237 , ARM64_REG_X20 = 238 , ARM64_REG_X21 = 239 , ARM64_REG_X22 = 240 , ARM64_REG_X23 = 241 , ARM64_REG_X24 = 242 , ARM64_REG_X25 = 243 , ARM64_REG_X26 = 244 , ARM64_REG_X27 = 245 , ARM64_REG_X28 = 246 , ARM64_REG_Z0 = 247 , ARM64_REG_Z1 = 248 , ARM64_REG_Z2 = 249 , ARM64_REG_Z3 = 250 , ARM64_REG_Z4 = 251 , ARM64_REG_Z5 = 252 , ARM64_REG_Z6 = 253 , ARM64_REG_Z7 = 254 , ARM64_REG_Z8 = 255 , ARM64_REG_Z9 = 256 , ARM64_REG_Z10 = 257 , ARM64_REG_Z11 = 258 , ARM64_REG_Z12 = 259 , ARM64_REG_Z13 = 260 , ARM64_REG_Z14 = 261 , ARM64_REG_Z15 = 262 , ARM64_REG_Z16 = 263 , ARM64_REG_Z17 = 264 , ARM64_REG_Z18 = 265 , ARM64_REG_Z19 = 266 , ARM64_REG_Z20 = 267 , ARM64_REG_Z21 = 268 , ARM64_REG_Z22 = 269 , ARM64_REG_Z23 = 270 , ARM64_REG_Z24 = 271 , ARM64_REG_Z25 = 272 , ARM64_REG_Z26 = 273 , ARM64_REG_Z27 = 274 , ARM64_REG_Z28 = 275 , ARM64_REG_Z29 = 276 , ARM64_REG_Z30 = 277 , ARM64_REG_Z31 = 278 , ARM64_REG_ZAB0 = 279 , ARM64_REG_ZAD0 = 280 , ARM64_REG_ZAD1 = 281 , ARM64_REG_ZAD2 = 282 , ARM64_REG_ZAD3 = 283 , ARM64_REG_ZAD4 = 284 , ARM64_REG_ZAD5 = 285 , ARM64_REG_ZAD6 = 286 , ARM64_REG_ZAD7 = 287 , ARM64_REG_ZAH0 = 288 , ARM64_REG_ZAH1 = 289 , ARM64_REG_ZAQ0 = 290 , ARM64_REG_ZAQ1 = 291 , ARM64_REG_ZAQ2 = 292 , ARM64_REG_ZAQ3 = 293 , ARM64_REG_ZAQ4 = 294 , ARM64_REG_ZAQ5 = 295 , ARM64_REG_ZAQ6 = 296 , ARM64_REG_ZAQ7 = 297 , ARM64_REG_ZAQ8 = 298 , ARM64_REG_ZAQ9 = 299 , ARM64_REG_ZAQ10 = 300 , ARM64_REG_ZAQ11 = 301 , ARM64_REG_ZAQ12 = 302 , ARM64_REG_ZAQ13 = 303 , ARM64_REG_ZAQ14 = 304 , ARM64_REG_ZAQ15 = 305 , ARM64_REG_ZAS0 = 306 , ARM64_REG_ZAS1 = 307 , ARM64_REG_ZAS2 = 308 , ARM64_REG_ZAS3 = 309 , ARM64_REG_V0 = 310 , ARM64_REG_V1 = 311 , ARM64_REG_V2 = 312 , ARM64_REG_V3 = 313 , ARM64_REG_V4 = 314 , ARM64_REG_V5 = 315 , ARM64_REG_V6 = 316 , ARM64_REG_V7 = 317 , ARM64_REG_V8 = 318 , ARM64_REG_V9 = 319 , ARM64_REG_V10 = 320 , ARM64_REG_V11 = 321 , ARM64_REG_V12 = 322 , ARM64_REG_V13 = 323 , ARM64_REG_V14 = 324 , ARM64_REG_V15 = 325 , ARM64_REG_V16 = 326 , ARM64_REG_V17 = 327 , ARM64_REG_V18 = 328 , ARM64_REG_V19 = 329 , ARM64_REG_V20 = 330 , ARM64_REG_V21 = 331 , ARM64_REG_V22 = 332 , ARM64_REG_V23 = 333 , ARM64_REG_V24 = 334 , ARM64_REG_V25 = 335 , ARM64_REG_V26 = 336 , ARM64_REG_V27 = 337 , ARM64_REG_V28 = 338 , ARM64_REG_V29 = 339 , ARM64_REG_V30 = 340 , ARM64_REG_V31 = 341 , ARM64_REG_ENDING = 342 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_mem { # [doc = "< base register"] pub base : arm64_reg , # [doc = "< index register"] pub index : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_mem"] [:: std :: mem :: size_of :: < arm64_op_mem > () - 12usize] ; ["Alignment of arm64_op_mem"] [:: std :: mem :: align_of :: < arm64_op_mem > () - 4usize] ; ["Offset of field: arm64_op_mem::base"] [:: std :: mem :: offset_of ! (arm64_op_mem , base) - 0usize] ; ["Offset of field: arm64_op_mem::index"] [:: std :: mem :: offset_of ! (arm64_op_mem , index) - 4usize] ; ["Offset of field: arm64_op_mem::disp"] [:: std :: mem :: offset_of ! (arm64_op_mem , disp) - 8usize] ; } ; # [doc = " SME Instruction's operand has index\n This is associated with ARM64_OP_SME_INDEX operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_sme_index { # [doc = "< register being indexed"] pub reg : arm64_reg , # [doc = "< base register"] pub base : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_sme_index"] [:: std :: mem :: size_of :: < arm64_op_sme_index > () - 12usize] ; ["Alignment of arm64_op_sme_index"] [:: std :: mem :: align_of :: < arm64_op_sme_index > () - 4usize] ; ["Offset of field: arm64_op_sme_index::reg"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , reg) - 0usize] ; ["Offset of field: arm64_op_sme_index::base"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , base) - 4usize] ; ["Offset of field: arm64_op_sme_index::disp"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64_op { # [doc = "< Vector Index for some vector operands (or -1 if\n< irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , # [doc = "< Vector Arrangement Specifier"] pub vas : arm64_vas , pub shift : cs_arm64_op__bindgen_ty_1 , # [doc = "< extender type of this operand"] pub ext : arm64_extender , # [doc = "< operand type"] pub type_ : arm64_op_type , # [doc = "< MSR/MRS SVCR instruction variant."] pub svcr : arm64_svcr_op , pub __bindgen_anon_1 : cs_arm64_op__bindgen_ty_2 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm64_op__bindgen_ty_1 { # [doc = "< shifter type of this operand"] pub type_ : arm64_shifter , # [doc = "< shifter value of this operand"] pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm64_op__bindgen_ty_2 { # [doc = "< register value for REG operand"] pub reg : arm64_reg , # [doc = "< immediate value, or index for C-IMM or IMM operand"] pub imm : i64 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm64_op_mem , # [doc = "< PState field of MSR instruction."] pub pstate : arm64_pstate , # [doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op,\n< arm64_dc_op, arm64_at_op, arm64_tlbi_op)"] pub sys : arm64_sys_op , # [doc = "< PRFM operation."] pub prefetch : arm64_prefetch_op , # [doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."] pub barrier : arm64_barrier_op , # [doc = "< base/disp value for matrix tile slice\n< instructions."] pub sme_index : arm64_op_sme_index , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_2 > () - 16usize] ; ["Alignment of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::pstate"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , pstate) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sys"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sys) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::prefetch"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , prefetch) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::barrier"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , barrier) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sme_index"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sme_index) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op"] [:: std :: mem :: size_of :: < cs_arm64_op > () - 56usize] ; ["Alignment of cs_arm64_op"] [:: std :: mem :: align_of :: < cs_arm64_op > () - 8usize] ; ["Offset of field: cs_arm64_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm64_op , vector_index) - 0usize] ; ["Offset of field: cs_arm64_op::vas"] [:: std :: mem :: offset_of ! (cs_arm64_op , vas) - 4usize] ; ["Offset of field: cs_arm64_op::shift"] [:: std :: mem :: offset_of ! (cs_arm64_op , shift) - 8usize] ; ["Offset of field: cs_arm64_op::ext"] [:: std :: mem :: offset_of ! (cs_arm64_op , ext) - 16usize] ; ["Offset of field: cs_arm64_op::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op , type_) - 20usize] ; ["Offset of field: cs_arm64_op::svcr"] [:: std :: mem :: offset_of ! (cs_arm64_op , svcr) - 24usize] ; ["Offset of field: cs_arm64_op::access"] [:: std :: mem :: offset_of ! (cs_arm64_op , access) - 48usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, svcr: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . svcr , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64 { # [doc = "< conditional code for this insn"] pub cc : arm64_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn request writeback? 'True' means 'yes'"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm64_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64"] [:: std :: mem :: size_of :: < cs_arm64 > () - 456usize] ; ["Alignment of cs_arm64"] [:: std :: mem :: align_of :: < cs_arm64 > () - 8usize] ; ["Offset of field: cs_arm64::cc"] [:: std :: mem :: offset_of ! (cs_arm64 , cc) - 0usize] ; ["Offset of field: cs_arm64::update_flags"] [:: std :: mem :: offset_of ! (cs_arm64 , update_flags) - 4usize] ; ["Offset of field: cs_arm64::writeback"] [:: std :: mem :: offset_of ! (cs_arm64 , writeback) - 5usize] ; ["Offset of field: cs_arm64::post_index"] [:: std :: mem :: offset_of ! (cs_arm64 , post_index) - 6usize] ; ["Offset of field: cs_arm64::op_count"] [:: std :: mem :: offset_of ! (cs_arm64 , op_count) - 7usize] ; ["Offset of field: cs_arm64::operands"] [:: std :: mem :: offset_of ! (cs_arm64 , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . post_index , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM64 instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn { ARM64_INS_INVALID = 0 , ARM64_INS_ABS = 1 , ARM64_INS_ADC = 2 , ARM64_INS_ADCLB = 3 , ARM64_INS_ADCLT = 4 , ARM64_INS_ADCS = 5 , ARM64_INS_ADD = 6 , ARM64_INS_ADDG = 7 , ARM64_INS_ADDHA = 8 , ARM64_INS_ADDHN = 9 , ARM64_INS_ADDHN2 = 10 , ARM64_INS_ADDHNB = 11 , ARM64_INS_ADDHNT = 12 , ARM64_INS_ADDP = 13 , ARM64_INS_ADDPL = 14 , ARM64_INS_ADDS = 15 , ARM64_INS_ADDV = 16 , ARM64_INS_ADDVA = 17 , ARM64_INS_ADDVL = 18 , ARM64_INS_ADR = 19 , ARM64_INS_ADRP = 20 , ARM64_INS_AESD = 21 , ARM64_INS_AESE = 22 , ARM64_INS_AESIMC = 23 , ARM64_INS_AESMC = 24 , ARM64_INS_AND = 25 , ARM64_INS_ANDS = 26 , ARM64_INS_ANDV = 27 , ARM64_INS_ASR = 28 , ARM64_INS_ASRD = 29 , ARM64_INS_ASRR = 30 , ARM64_INS_ASRV = 31 , ARM64_INS_AUTDA = 32 , ARM64_INS_AUTDB = 33 , ARM64_INS_AUTDZA = 34 , ARM64_INS_AUTDZB = 35 , ARM64_INS_AUTIA = 36 , ARM64_INS_AUTIA1716 = 37 , ARM64_INS_AUTIASP = 38 , ARM64_INS_AUTIAZ = 39 , ARM64_INS_AUTIB = 40 , ARM64_INS_AUTIB1716 = 41 , ARM64_INS_AUTIBSP = 42 , ARM64_INS_AUTIBZ = 43 , ARM64_INS_AUTIZA = 44 , ARM64_INS_AUTIZB = 45 , ARM64_INS_AXFLAG = 46 , ARM64_INS_B = 47 , ARM64_INS_BC = 48 , ARM64_INS_BCAX = 49 , ARM64_INS_BDEP = 50 , ARM64_INS_BEXT = 51 , ARM64_INS_BFCVT = 52 , ARM64_INS_BFCVTN = 53 , ARM64_INS_BFCVTN2 = 54 , ARM64_INS_BFCVTNT = 55 , ARM64_INS_BFDOT = 56 , ARM64_INS_BFM = 57 , ARM64_INS_BFMLALB = 58 , ARM64_INS_BFMLALT = 59 , ARM64_INS_BFMMLA = 60 , ARM64_INS_BFMOPA = 61 , ARM64_INS_BFMOPS = 62 , ARM64_INS_BGRP = 63 , ARM64_INS_BIC = 64 , ARM64_INS_BICS = 65 , ARM64_INS_BIF = 66 , ARM64_INS_BIT = 67 , ARM64_INS_BL = 68 , ARM64_INS_BLR = 69 , ARM64_INS_BLRAA = 70 , ARM64_INS_BLRAAZ = 71 , ARM64_INS_BLRAB = 72 , ARM64_INS_BLRABZ = 73 , ARM64_INS_BR = 74 , ARM64_INS_BRAA = 75 , ARM64_INS_BRAAZ = 76 , ARM64_INS_BRAB = 77 , ARM64_INS_BRABZ = 78 , ARM64_INS_BRB = 79 , ARM64_INS_BRK = 80 , ARM64_INS_BRKA = 81 , ARM64_INS_BRKAS = 82 , ARM64_INS_BRKB = 83 , ARM64_INS_BRKBS = 84 , ARM64_INS_BRKN = 85 , ARM64_INS_BRKNS = 86 , ARM64_INS_BRKPA = 87 , ARM64_INS_BRKPAS = 88 , ARM64_INS_BRKPB = 89 , ARM64_INS_BRKPBS = 90 , ARM64_INS_BSL = 91 , ARM64_INS_BSL1N = 92 , ARM64_INS_BSL2N = 93 , ARM64_INS_BTI = 94 , ARM64_INS_CADD = 95 , ARM64_INS_CAS = 96 , ARM64_INS_CASA = 97 , ARM64_INS_CASAB = 98 , ARM64_INS_CASAH = 99 , ARM64_INS_CASAL = 100 , ARM64_INS_CASALB = 101 , ARM64_INS_CASALH = 102 , ARM64_INS_CASB = 103 , ARM64_INS_CASH = 104 , ARM64_INS_CASL = 105 , ARM64_INS_CASLB = 106 , ARM64_INS_CASLH = 107 , ARM64_INS_CASP = 108 , ARM64_INS_CASPA = 109 , ARM64_INS_CASPAL = 110 , ARM64_INS_CASPL = 111 , ARM64_INS_CBNZ = 112 , ARM64_INS_CBZ = 113 , ARM64_INS_CCMN = 114 , ARM64_INS_CCMP = 115 , ARM64_INS_CDOT = 116 , ARM64_INS_CFINV = 117 , ARM64_INS_CINC = 118 , ARM64_INS_CINV = 119 , ARM64_INS_CLASTA = 120 , ARM64_INS_CLASTB = 121 , ARM64_INS_CLREX = 122 , ARM64_INS_CLS = 123 , ARM64_INS_CLZ = 124 , ARM64_INS_CMEQ = 125 , ARM64_INS_CMGE = 126 , ARM64_INS_CMGT = 127 , ARM64_INS_CMHI = 128 , ARM64_INS_CMHS = 129 , ARM64_INS_CMLA = 130 , ARM64_INS_CMLE = 131 , ARM64_INS_CMLO = 132 , ARM64_INS_CMLS = 133 , ARM64_INS_CMLT = 134 , ARM64_INS_CMN = 135 , ARM64_INS_CMP = 136 , ARM64_INS_CMPEQ = 137 , ARM64_INS_CMPGE = 138 , ARM64_INS_CMPGT = 139 , ARM64_INS_CMPHI = 140 , ARM64_INS_CMPHS = 141 , ARM64_INS_CMPLE = 142 , ARM64_INS_CMPLO = 143 , ARM64_INS_CMPLS = 144 , ARM64_INS_CMPLT = 145 , ARM64_INS_CMPNE = 146 , ARM64_INS_CMPP = 147 , ARM64_INS_CMTST = 148 , ARM64_INS_CNEG = 149 , ARM64_INS_CNOT = 150 , ARM64_INS_CNT = 151 , ARM64_INS_CNTB = 152 , ARM64_INS_CNTD = 153 , ARM64_INS_CNTH = 154 , ARM64_INS_CNTP = 155 , ARM64_INS_CNTW = 156 , ARM64_INS_COMPACT = 157 , ARM64_INS_CPY = 158 , ARM64_INS_CPYE = 159 , ARM64_INS_CPYEN = 160 , ARM64_INS_CPYERN = 161 , ARM64_INS_CPYERT = 162 , ARM64_INS_CPYERTN = 163 , ARM64_INS_CPYERTRN = 164 , ARM64_INS_CPYERTWN = 165 , ARM64_INS_CPYET = 166 , ARM64_INS_CPYETN = 167 , ARM64_INS_CPYETRN = 168 , ARM64_INS_CPYETWN = 169 , ARM64_INS_CPYEWN = 170 , ARM64_INS_CPYEWT = 171 , ARM64_INS_CPYEWTN = 172 , ARM64_INS_CPYEWTRN = 173 , ARM64_INS_CPYEWTWN = 174 , ARM64_INS_CPYFE = 175 , ARM64_INS_CPYFEN = 176 , ARM64_INS_CPYFERN = 177 , ARM64_INS_CPYFERT = 178 , ARM64_INS_CPYFERTN = 179 , ARM64_INS_CPYFERTRN = 180 , ARM64_INS_CPYFERTWN = 181 , ARM64_INS_CPYFET = 182 , ARM64_INS_CPYFETN = 183 , ARM64_INS_CPYFETRN = 184 , ARM64_INS_CPYFETWN = 185 , ARM64_INS_CPYFEWN = 186 , ARM64_INS_CPYFEWT = 187 , ARM64_INS_CPYFEWTN = 188 , ARM64_INS_CPYFEWTRN = 189 , ARM64_INS_CPYFEWTWN = 190 , ARM64_INS_CPYFM = 191 , ARM64_INS_CPYFMN = 192 , ARM64_INS_CPYFMRN = 193 , ARM64_INS_CPYFMRT = 194 , ARM64_INS_CPYFMRTN = 195 , ARM64_INS_CPYFMRTRN = 196 , ARM64_INS_CPYFMRTWN = 197 , ARM64_INS_CPYFMT = 198 , ARM64_INS_CPYFMTN = 199 , ARM64_INS_CPYFMTRN = 200 , ARM64_INS_CPYFMTWN = 201 , ARM64_INS_CPYFMWN = 202 , ARM64_INS_CPYFMWT = 203 , ARM64_INS_CPYFMWTN = 204 , ARM64_INS_CPYFMWTRN = 205 , ARM64_INS_CPYFMWTWN = 206 , ARM64_INS_CPYFP = 207 , ARM64_INS_CPYFPN = 208 , ARM64_INS_CPYFPRN = 209 , ARM64_INS_CPYFPRT = 210 , ARM64_INS_CPYFPRTN = 211 , ARM64_INS_CPYFPRTRN = 212 , ARM64_INS_CPYFPRTWN = 213 , ARM64_INS_CPYFPT = 214 , ARM64_INS_CPYFPTN = 215 , ARM64_INS_CPYFPTRN = 216 , ARM64_INS_CPYFPTWN = 217 , ARM64_INS_CPYFPWN = 218 , ARM64_INS_CPYFPWT = 219 , ARM64_INS_CPYFPWTN = 220 , ARM64_INS_CPYFPWTRN = 221 , ARM64_INS_CPYFPWTWN = 222 , ARM64_INS_CPYM = 223 , ARM64_INS_CPYMN = 224 , ARM64_INS_CPYMRN = 225 , ARM64_INS_CPYMRT = 226 , ARM64_INS_CPYMRTN = 227 , ARM64_INS_CPYMRTRN = 228 , ARM64_INS_CPYMRTWN = 229 , ARM64_INS_CPYMT = 230 , ARM64_INS_CPYMTN = 231 , ARM64_INS_CPYMTRN = 232 , ARM64_INS_CPYMTWN = 233 , ARM64_INS_CPYMWN = 234 , ARM64_INS_CPYMWT = 235 , ARM64_INS_CPYMWTN = 236 , ARM64_INS_CPYMWTRN = 237 , ARM64_INS_CPYMWTWN = 238 , ARM64_INS_CPYP = 239 , ARM64_INS_CPYPN = 240 , ARM64_INS_CPYPRN = 241 , ARM64_INS_CPYPRT = 242 , ARM64_INS_CPYPRTN = 243 , ARM64_INS_CPYPRTRN = 244 , ARM64_INS_CPYPRTWN = 245 , ARM64_INS_CPYPT = 246 , ARM64_INS_CPYPTN = 247 , ARM64_INS_CPYPTRN = 248 , ARM64_INS_CPYPTWN = 249 , ARM64_INS_CPYPWN = 250 , ARM64_INS_CPYPWT = 251 , ARM64_INS_CPYPWTN = 252 , ARM64_INS_CPYPWTRN = 253 , ARM64_INS_CPYPWTWN = 254 , ARM64_INS_CRC32B = 255 , ARM64_INS_CRC32CB = 256 , ARM64_INS_CRC32CH = 257 , ARM64_INS_CRC32CW = 258 , ARM64_INS_CRC32CX = 259 , ARM64_INS_CRC32H = 260 , ARM64_INS_CRC32W = 261 , ARM64_INS_CRC32X = 262 , ARM64_INS_CSDB = 263 , ARM64_INS_CSEL = 264 , ARM64_INS_CSET = 265 , ARM64_INS_CSETM = 266 , ARM64_INS_CSINC = 267 , ARM64_INS_CSINV = 268 , ARM64_INS_CSNEG = 269 , ARM64_INS_CTERMEQ = 270 , ARM64_INS_CTERMNE = 271 , ARM64_INS_DCPS1 = 272 , ARM64_INS_DCPS2 = 273 , ARM64_INS_DCPS3 = 274 , ARM64_INS_DECB = 275 , ARM64_INS_DECD = 276 , ARM64_INS_DECH = 277 , ARM64_INS_DECP = 278 , ARM64_INS_DECW = 279 , ARM64_INS_DFB = 280 , ARM64_INS_DGH = 281 , ARM64_INS_DMB = 282 , ARM64_INS_DRPS = 283 , ARM64_INS_DSB = 284 , ARM64_INS_DUP = 285 , ARM64_INS_DUPM = 286 , ARM64_INS_EON = 287 , ARM64_INS_EOR = 288 , ARM64_INS_EOR3 = 289 , ARM64_INS_EORBT = 290 , ARM64_INS_EORS = 291 , ARM64_INS_EORTB = 292 , ARM64_INS_EORV = 293 , ARM64_INS_ERET = 294 , ARM64_INS_ERETAA = 295 , ARM64_INS_ERETAB = 296 , ARM64_INS_ESB = 297 , ARM64_INS_EXT = 298 , ARM64_INS_EXTR = 299 , ARM64_INS_FABD = 300 , ARM64_INS_FABS = 301 , ARM64_INS_FACGE = 302 , ARM64_INS_FACGT = 303 , ARM64_INS_FACLE = 304 , ARM64_INS_FACLT = 305 , ARM64_INS_FADD = 306 , ARM64_INS_FADDA = 307 , ARM64_INS_FADDP = 308 , ARM64_INS_FADDV = 309 , ARM64_INS_FCADD = 310 , ARM64_INS_FCCMP = 311 , ARM64_INS_FCCMPE = 312 , ARM64_INS_FCMEQ = 313 , ARM64_INS_FCMGE = 314 , ARM64_INS_FCMGT = 315 , ARM64_INS_FCMLA = 316 , ARM64_INS_FCMLE = 317 , ARM64_INS_FCMLT = 318 , ARM64_INS_FCMNE = 319 , ARM64_INS_FCMP = 320 , ARM64_INS_FCMPE = 321 , ARM64_INS_FCMUO = 322 , ARM64_INS_FCPY = 323 , ARM64_INS_FCSEL = 324 , ARM64_INS_FCVT = 325 , ARM64_INS_FCVTAS = 326 , ARM64_INS_FCVTAU = 327 , ARM64_INS_FCVTL = 328 , ARM64_INS_FCVTL2 = 329 , ARM64_INS_FCVTLT = 330 , ARM64_INS_FCVTMS = 331 , ARM64_INS_FCVTMU = 332 , ARM64_INS_FCVTN = 333 , ARM64_INS_FCVTN2 = 334 , ARM64_INS_FCVTNS = 335 , ARM64_INS_FCVTNT = 336 , ARM64_INS_FCVTNU = 337 , ARM64_INS_FCVTPS = 338 , ARM64_INS_FCVTPU = 339 , ARM64_INS_FCVTX = 340 , ARM64_INS_FCVTXN = 341 , ARM64_INS_FCVTXN2 = 342 , ARM64_INS_FCVTXNT = 343 , ARM64_INS_FCVTZS = 344 , ARM64_INS_FCVTZU = 345 , ARM64_INS_FDIV = 346 , ARM64_INS_FDIVR = 347 , ARM64_INS_FDUP = 348 , ARM64_INS_FEXPA = 349 , ARM64_INS_FJCVTZS = 350 , ARM64_INS_FLOGB = 351 , ARM64_INS_FMAD = 352 , ARM64_INS_FMADD = 353 , ARM64_INS_FMAX = 354 , ARM64_INS_FMAXNM = 355 , ARM64_INS_FMAXNMP = 356 , ARM64_INS_FMAXNMV = 357 , ARM64_INS_FMAXP = 358 , ARM64_INS_FMAXV = 359 , ARM64_INS_FMIN = 360 , ARM64_INS_FMINNM = 361 , ARM64_INS_FMINNMP = 362 , ARM64_INS_FMINNMV = 363 , ARM64_INS_FMINP = 364 , ARM64_INS_FMINV = 365 , ARM64_INS_FMLA = 366 , ARM64_INS_FMLAL = 367 , ARM64_INS_FMLAL2 = 368 , ARM64_INS_FMLALB = 369 , ARM64_INS_FMLALT = 370 , ARM64_INS_FMLS = 371 , ARM64_INS_FMLSL = 372 , ARM64_INS_FMLSL2 = 373 , ARM64_INS_FMLSLB = 374 , ARM64_INS_FMLSLT = 375 , ARM64_INS_FMMLA = 376 , ARM64_INS_FMOPA = 377 , ARM64_INS_FMOPS = 378 , ARM64_INS_FMOV = 379 , ARM64_INS_FMSB = 380 , ARM64_INS_FMSUB = 381 , ARM64_INS_FMUL = 382 , ARM64_INS_FMULX = 383 , ARM64_INS_FNEG = 384 , ARM64_INS_FNMAD = 385 , ARM64_INS_FNMADD = 386 , ARM64_INS_FNMLA = 387 , ARM64_INS_FNMLS = 388 , ARM64_INS_FNMSB = 389 , ARM64_INS_FNMSUB = 390 , ARM64_INS_FNMUL = 391 , ARM64_INS_FRECPE = 392 , ARM64_INS_FRECPS = 393 , ARM64_INS_FRECPX = 394 , ARM64_INS_FRINT32X = 395 , ARM64_INS_FRINT32Z = 396 , ARM64_INS_FRINT64X = 397 , ARM64_INS_FRINT64Z = 398 , ARM64_INS_FRINTA = 399 , ARM64_INS_FRINTI = 400 , ARM64_INS_FRINTM = 401 , ARM64_INS_FRINTN = 402 , ARM64_INS_FRINTP = 403 , ARM64_INS_FRINTX = 404 , ARM64_INS_FRINTZ = 405 , ARM64_INS_FRSQRTE = 406 , ARM64_INS_FRSQRTS = 407 , ARM64_INS_FSCALE = 408 , ARM64_INS_FSQRT = 409 , ARM64_INS_FSUB = 410 , ARM64_INS_FSUBR = 411 , ARM64_INS_FTMAD = 412 , ARM64_INS_FTSMUL = 413 , ARM64_INS_FTSSEL = 414 , ARM64_INS_GMI = 415 , ARM64_INS_HINT = 416 , ARM64_INS_HISTCNT = 417 , ARM64_INS_HISTSEG = 418 , ARM64_INS_HLT = 419 , ARM64_INS_HVC = 420 , ARM64_INS_INCB = 421 , ARM64_INS_INCD = 422 , ARM64_INS_INCH = 423 , ARM64_INS_INCP = 424 , ARM64_INS_INCW = 425 , ARM64_INS_INDEX = 426 , ARM64_INS_INS = 427 , ARM64_INS_INSR = 428 , ARM64_INS_IRG = 429 , ARM64_INS_ISB = 430 , ARM64_INS_LASTA = 431 , ARM64_INS_LASTB = 432 , ARM64_INS_LD1 = 433 , ARM64_INS_LD1B = 434 , ARM64_INS_LD1D = 435 , ARM64_INS_LD1H = 436 , ARM64_INS_LD1Q = 437 , ARM64_INS_LD1R = 438 , ARM64_INS_LD1RB = 439 , ARM64_INS_LD1RD = 440 , ARM64_INS_LD1RH = 441 , ARM64_INS_LD1ROB = 442 , ARM64_INS_LD1ROD = 443 , ARM64_INS_LD1ROH = 444 , ARM64_INS_LD1ROW = 445 , ARM64_INS_LD1RQB = 446 , ARM64_INS_LD1RQD = 447 , ARM64_INS_LD1RQH = 448 , ARM64_INS_LD1RQW = 449 , ARM64_INS_LD1RSB = 450 , ARM64_INS_LD1RSH = 451 , ARM64_INS_LD1RSW = 452 , ARM64_INS_LD1RW = 453 , ARM64_INS_LD1SB = 454 , ARM64_INS_LD1SH = 455 , ARM64_INS_LD1SW = 456 , ARM64_INS_LD1W = 457 , ARM64_INS_LD2 = 458 , ARM64_INS_LD2B = 459 , ARM64_INS_LD2D = 460 , ARM64_INS_LD2H = 461 , ARM64_INS_LD2R = 462 , ARM64_INS_LD2W = 463 , ARM64_INS_LD3 = 464 , ARM64_INS_LD3B = 465 , ARM64_INS_LD3D = 466 , ARM64_INS_LD3H = 467 , ARM64_INS_LD3R = 468 , ARM64_INS_LD3W = 469 , ARM64_INS_LD4 = 470 , ARM64_INS_LD4B = 471 , ARM64_INS_LD4D = 472 , ARM64_INS_LD4H = 473 , ARM64_INS_LD4R = 474 , ARM64_INS_LD4W = 475 , ARM64_INS_LD64B = 476 , ARM64_INS_LDADD = 477 , ARM64_INS_LDADDA = 478 , ARM64_INS_LDADDAB = 479 , ARM64_INS_LDADDAH = 480 , ARM64_INS_LDADDAL = 481 , ARM64_INS_LDADDALB = 482 , ARM64_INS_LDADDALH = 483 , ARM64_INS_LDADDB = 484 , ARM64_INS_LDADDH = 485 , ARM64_INS_LDADDL = 486 , ARM64_INS_LDADDLB = 487 , ARM64_INS_LDADDLH = 488 , ARM64_INS_LDAPR = 489 , ARM64_INS_LDAPRB = 490 , ARM64_INS_LDAPRH = 491 , ARM64_INS_LDAPUR = 492 , ARM64_INS_LDAPURB = 493 , ARM64_INS_LDAPURH = 494 , ARM64_INS_LDAPURSB = 495 , ARM64_INS_LDAPURSH = 496 , ARM64_INS_LDAPURSW = 497 , ARM64_INS_LDAR = 498 , ARM64_INS_LDARB = 499 , ARM64_INS_LDARH = 500 , ARM64_INS_LDAXP = 501 , ARM64_INS_LDAXR = 502 , ARM64_INS_LDAXRB = 503 , ARM64_INS_LDAXRH = 504 , ARM64_INS_LDCLR = 505 , ARM64_INS_LDCLRA = 506 , ARM64_INS_LDCLRAB = 507 , ARM64_INS_LDCLRAH = 508 , ARM64_INS_LDCLRAL = 509 , ARM64_INS_LDCLRALB = 510 , ARM64_INS_LDCLRALH = 511 , ARM64_INS_LDCLRB = 512 , ARM64_INS_LDCLRH = 513 , ARM64_INS_LDCLRL = 514 , ARM64_INS_LDCLRLB = 515 , ARM64_INS_LDCLRLH = 516 , ARM64_INS_LDEOR = 517 , ARM64_INS_LDEORA = 518 , ARM64_INS_LDEORAB = 519 , ARM64_INS_LDEORAH = 520 , ARM64_INS_LDEORAL = 521 , ARM64_INS_LDEORALB = 522 , ARM64_INS_LDEORALH = 523 , ARM64_INS_LDEORB = 524 , ARM64_INS_LDEORH = 525 , ARM64_INS_LDEORL = 526 , ARM64_INS_LDEORLB = 527 , ARM64_INS_LDEORLH = 528 , ARM64_INS_LDFF1B = 529 , ARM64_INS_LDFF1D = 530 , ARM64_INS_LDFF1H = 531 , ARM64_INS_LDFF1SB = 532 , ARM64_INS_LDFF1SH = 533 , ARM64_INS_LDFF1SW = 534 , ARM64_INS_LDFF1W = 535 , ARM64_INS_LDG = 536 , ARM64_INS_LDGM = 537 , ARM64_INS_LDLAR = 538 , ARM64_INS_LDLARB = 539 , ARM64_INS_LDLARH = 540 , ARM64_INS_LDNF1B = 541 , ARM64_INS_LDNF1D = 542 , ARM64_INS_LDNF1H = 543 , ARM64_INS_LDNF1SB = 544 , ARM64_INS_LDNF1SH = 545 , ARM64_INS_LDNF1SW = 546 , ARM64_INS_LDNF1W = 547 , ARM64_INS_LDNP = 548 , ARM64_INS_LDNT1B = 549 , ARM64_INS_LDNT1D = 550 , ARM64_INS_LDNT1H = 551 , ARM64_INS_LDNT1SB = 552 , ARM64_INS_LDNT1SH = 553 , ARM64_INS_LDNT1SW = 554 , ARM64_INS_LDNT1W = 555 , ARM64_INS_LDP = 556 , ARM64_INS_LDPSW = 557 , ARM64_INS_LDR = 558 , ARM64_INS_LDRAA = 559 , ARM64_INS_LDRAB = 560 , ARM64_INS_LDRB = 561 , ARM64_INS_LDRH = 562 , ARM64_INS_LDRSB = 563 , ARM64_INS_LDRSH = 564 , ARM64_INS_LDRSW = 565 , ARM64_INS_LDSET = 566 , ARM64_INS_LDSETA = 567 , ARM64_INS_LDSETAB = 568 , ARM64_INS_LDSETAH = 569 , ARM64_INS_LDSETAL = 570 , ARM64_INS_LDSETALB = 571 , ARM64_INS_LDSETALH = 572 , ARM64_INS_LDSETB = 573 , ARM64_INS_LDSETH = 574 , ARM64_INS_LDSETL = 575 , ARM64_INS_LDSETLB = 576 , ARM64_INS_LDSETLH = 577 , ARM64_INS_LDSMAX = 578 , ARM64_INS_LDSMAXA = 579 , ARM64_INS_LDSMAXAB = 580 , ARM64_INS_LDSMAXAH = 581 , ARM64_INS_LDSMAXAL = 582 , ARM64_INS_LDSMAXALB = 583 , ARM64_INS_LDSMAXALH = 584 , ARM64_INS_LDSMAXB = 585 , ARM64_INS_LDSMAXH = 586 , ARM64_INS_LDSMAXL = 587 , ARM64_INS_LDSMAXLB = 588 , ARM64_INS_LDSMAXLH = 589 , ARM64_INS_LDSMIN = 590 , ARM64_INS_LDSMINA = 591 , ARM64_INS_LDSMINAB = 592 , ARM64_INS_LDSMINAH = 593 , ARM64_INS_LDSMINAL = 594 , ARM64_INS_LDSMINALB = 595 , ARM64_INS_LDSMINALH = 596 , ARM64_INS_LDSMINB = 597 , ARM64_INS_LDSMINH = 598 , ARM64_INS_LDSMINL = 599 , ARM64_INS_LDSMINLB = 600 , ARM64_INS_LDSMINLH = 601 , ARM64_INS_LDTR = 602 , ARM64_INS_LDTRB = 603 , ARM64_INS_LDTRH = 604 , ARM64_INS_LDTRSB = 605 , ARM64_INS_LDTRSH = 606 , ARM64_INS_LDTRSW = 607 , ARM64_INS_LDUMAX = 608 , ARM64_INS_LDUMAXA = 609 , ARM64_INS_LDUMAXAB = 610 , ARM64_INS_LDUMAXAH = 611 , ARM64_INS_LDUMAXAL = 612 , ARM64_INS_LDUMAXALB = 613 , ARM64_INS_LDUMAXALH = 614 , ARM64_INS_LDUMAXB = 615 , ARM64_INS_LDUMAXH = 616 , ARM64_INS_LDUMAXL = 617 , ARM64_INS_LDUMAXLB = 618 , ARM64_INS_LDUMAXLH = 619 , ARM64_INS_LDUMIN = 620 , ARM64_INS_LDUMINA = 621 , ARM64_INS_LDUMINAB = 622 , ARM64_INS_LDUMINAH = 623 , ARM64_INS_LDUMINAL = 624 , ARM64_INS_LDUMINALB = 625 , ARM64_INS_LDUMINALH = 626 , ARM64_INS_LDUMINB = 627 , ARM64_INS_LDUMINH = 628 , ARM64_INS_LDUMINL = 629 , ARM64_INS_LDUMINLB = 630 , ARM64_INS_LDUMINLH = 631 , ARM64_INS_LDUR = 632 , ARM64_INS_LDURB = 633 , ARM64_INS_LDURH = 634 , ARM64_INS_LDURSB = 635 , ARM64_INS_LDURSH = 636 , ARM64_INS_LDURSW = 637 , ARM64_INS_LDXP = 638 , ARM64_INS_LDXR = 639 , ARM64_INS_LDXRB = 640 , ARM64_INS_LDXRH = 641 , ARM64_INS_LSL = 642 , ARM64_INS_LSLR = 643 , ARM64_INS_LSLV = 644 , ARM64_INS_LSR = 645 , ARM64_INS_LSRR = 646 , ARM64_INS_LSRV = 647 , ARM64_INS_MAD = 648 , ARM64_INS_MADD = 649 , ARM64_INS_MATCH = 650 , ARM64_INS_MLA = 651 , ARM64_INS_MLS = 652 , ARM64_INS_MNEG = 653 , ARM64_INS_MOV = 654 , ARM64_INS_MOVA = 655 , ARM64_INS_MOVI = 656 , ARM64_INS_MOVK = 657 , ARM64_INS_MOVN = 658 , ARM64_INS_MOVPRFX = 659 , ARM64_INS_MOVS = 660 , ARM64_INS_MOVZ = 661 , ARM64_INS_MRS = 662 , ARM64_INS_MSB = 663 , ARM64_INS_MSR = 664 , ARM64_INS_MSUB = 665 , ARM64_INS_MUL = 666 , ARM64_INS_MVN = 667 , ARM64_INS_MVNI = 668 , ARM64_INS_NAND = 669 , ARM64_INS_NANDS = 670 , ARM64_INS_NBSL = 671 , ARM64_INS_NEG = 672 , ARM64_INS_NEGS = 673 , ARM64_INS_NGC = 674 , ARM64_INS_NGCS = 675 , ARM64_INS_NMATCH = 676 , ARM64_INS_NOP = 677 , ARM64_INS_NOR = 678 , ARM64_INS_NORS = 679 , ARM64_INS_NOT = 680 , ARM64_INS_NOTS = 681 , ARM64_INS_ORN = 682 , ARM64_INS_ORNS = 683 , ARM64_INS_ORR = 684 , ARM64_INS_ORRS = 685 , ARM64_INS_ORV = 686 , ARM64_INS_PACDA = 687 , ARM64_INS_PACDB = 688 , ARM64_INS_PACDZA = 689 , ARM64_INS_PACDZB = 690 , ARM64_INS_PACGA = 691 , ARM64_INS_PACIA = 692 , ARM64_INS_PACIA1716 = 693 , ARM64_INS_PACIASP = 694 , ARM64_INS_PACIAZ = 695 , ARM64_INS_PACIB = 696 , ARM64_INS_PACIB1716 = 697 , ARM64_INS_PACIBSP = 698 , ARM64_INS_PACIBZ = 699 , ARM64_INS_PACIZA = 700 , ARM64_INS_PACIZB = 701 , ARM64_INS_PFALSE = 702 , ARM64_INS_PFIRST = 703 , ARM64_INS_PMUL = 704 , ARM64_INS_PMULL = 705 , ARM64_INS_PMULL2 = 706 , ARM64_INS_PMULLB = 707 , ARM64_INS_PMULLT = 708 , ARM64_INS_PNEXT = 709 , ARM64_INS_PRFB = 710 , ARM64_INS_PRFD = 711 , ARM64_INS_PRFH = 712 , ARM64_INS_PRFM = 713 , ARM64_INS_PRFUM = 714 , ARM64_INS_PRFW = 715 , ARM64_INS_PSB = 716 , ARM64_INS_PSEL = 717 , ARM64_INS_PSSBB = 718 , ARM64_INS_PTEST = 719 , ARM64_INS_PTRUE = 720 , ARM64_INS_PTRUES = 721 , ARM64_INS_PUNPKHI = 722 , ARM64_INS_PUNPKLO = 723 , ARM64_INS_RADDHN = 724 , ARM64_INS_RADDHN2 = 725 , ARM64_INS_RADDHNB = 726 , ARM64_INS_RADDHNT = 727 , ARM64_INS_RAX1 = 728 , ARM64_INS_RBIT = 729 , ARM64_INS_RDFFR = 730 , ARM64_INS_RDFFRS = 731 , ARM64_INS_RDVL = 732 , ARM64_INS_RET = 733 , ARM64_INS_RETAA = 734 , ARM64_INS_RETAB = 735 , ARM64_INS_REV = 736 , ARM64_INS_REV16 = 737 , ARM64_INS_REV32 = 738 , ARM64_INS_REV64 = 739 , ARM64_INS_REVB = 740 , ARM64_INS_REVD = 741 , ARM64_INS_REVH = 742 , ARM64_INS_REVW = 743 , ARM64_INS_RMIF = 744 , ARM64_INS_ROR = 745 , ARM64_INS_RORV = 746 , ARM64_INS_RSHRN = 747 , ARM64_INS_RSHRN2 = 748 , ARM64_INS_RSHRNB = 749 , ARM64_INS_RSHRNT = 750 , ARM64_INS_RSUBHN = 751 , ARM64_INS_RSUBHN2 = 752 , ARM64_INS_RSUBHNB = 753 , ARM64_INS_RSUBHNT = 754 , ARM64_INS_SABA = 755 , ARM64_INS_SABAL = 756 , ARM64_INS_SABAL2 = 757 , ARM64_INS_SABALB = 758 , ARM64_INS_SABALT = 759 , ARM64_INS_SABD = 760 , ARM64_INS_SABDL = 761 , ARM64_INS_SABDL2 = 762 , ARM64_INS_SABDLB = 763 , ARM64_INS_SABDLT = 764 , ARM64_INS_SADALP = 765 , ARM64_INS_SADDL = 766 , ARM64_INS_SADDL2 = 767 , ARM64_INS_SADDLB = 768 , ARM64_INS_SADDLBT = 769 , ARM64_INS_SADDLP = 770 , ARM64_INS_SADDLT = 771 , ARM64_INS_SADDLV = 772 , ARM64_INS_SADDV = 773 , ARM64_INS_SADDW = 774 , ARM64_INS_SADDW2 = 775 , ARM64_INS_SADDWB = 776 , ARM64_INS_SADDWT = 777 , ARM64_INS_SB = 778 , ARM64_INS_SBC = 779 , ARM64_INS_SBCLB = 780 , ARM64_INS_SBCLT = 781 , ARM64_INS_SBCS = 782 , ARM64_INS_SBFM = 783 , ARM64_INS_SCLAMP = 784 , ARM64_INS_SCVTF = 785 , ARM64_INS_SDIV = 786 , ARM64_INS_SDIVR = 787 , ARM64_INS_SDOT = 788 , ARM64_INS_SEL = 789 , ARM64_INS_SETE = 790 , ARM64_INS_SETEN = 791 , ARM64_INS_SETET = 792 , ARM64_INS_SETETN = 793 , ARM64_INS_SETF16 = 794 , ARM64_INS_SETF8 = 795 , ARM64_INS_SETFFR = 796 , ARM64_INS_SETGE = 797 , ARM64_INS_SETGEN = 798 , ARM64_INS_SETGET = 799 , ARM64_INS_SETGETN = 800 , ARM64_INS_SETGM = 801 , ARM64_INS_SETGMN = 802 , ARM64_INS_SETGMT = 803 , ARM64_INS_SETGMTN = 804 , ARM64_INS_SETGP = 805 , ARM64_INS_SETGPN = 806 , ARM64_INS_SETGPT = 807 , ARM64_INS_SETGPTN = 808 , ARM64_INS_SETM = 809 , ARM64_INS_SETMN = 810 , ARM64_INS_SETMT = 811 , ARM64_INS_SETMTN = 812 , ARM64_INS_SETP = 813 , ARM64_INS_SETPN = 814 , ARM64_INS_SETPT = 815 , ARM64_INS_SETPTN = 816 , ARM64_INS_SEV = 817 , ARM64_INS_SEVL = 818 , ARM64_INS_SHA1C = 819 , ARM64_INS_SHA1H = 820 , ARM64_INS_SHA1M = 821 , ARM64_INS_SHA1P = 822 , ARM64_INS_SHA1SU0 = 823 , ARM64_INS_SHA1SU1 = 824 , ARM64_INS_SHA256H = 825 , ARM64_INS_SHA256H2 = 826 , ARM64_INS_SHA256SU0 = 827 , ARM64_INS_SHA256SU1 = 828 , ARM64_INS_SHA512H = 829 , ARM64_INS_SHA512H2 = 830 , ARM64_INS_SHA512SU0 = 831 , ARM64_INS_SHA512SU1 = 832 , ARM64_INS_SHADD = 833 , ARM64_INS_SHL = 834 , ARM64_INS_SHLL = 835 , ARM64_INS_SHLL2 = 836 , ARM64_INS_SHRN = 837 , ARM64_INS_SHRN2 = 838 , ARM64_INS_SHRNB = 839 , ARM64_INS_SHRNT = 840 , ARM64_INS_SHSUB = 841 , ARM64_INS_SHSUBR = 842 , ARM64_INS_SLI = 843 , ARM64_INS_SM3PARTW1 = 844 , ARM64_INS_SM3PARTW2 = 845 , ARM64_INS_SM3SS1 = 846 , ARM64_INS_SM3TT1A = 847 , ARM64_INS_SM3TT1B = 848 , ARM64_INS_SM3TT2A = 849 , ARM64_INS_SM3TT2B = 850 , ARM64_INS_SM4E = 851 , ARM64_INS_SM4EKEY = 852 , ARM64_INS_SMADDL = 853 , ARM64_INS_SMAX = 854 , ARM64_INS_SMAXP = 855 , ARM64_INS_SMAXV = 856 , ARM64_INS_SMC = 857 , ARM64_INS_SMIN = 858 , ARM64_INS_SMINP = 859 , ARM64_INS_SMINV = 860 , ARM64_INS_SMLAL = 861 , ARM64_INS_SMLAL2 = 862 , ARM64_INS_SMLALB = 863 , ARM64_INS_SMLALT = 864 , ARM64_INS_SMLSL = 865 , ARM64_INS_SMLSL2 = 866 , ARM64_INS_SMLSLB = 867 , ARM64_INS_SMLSLT = 868 , ARM64_INS_SMMLA = 869 , ARM64_INS_SMNEGL = 870 , ARM64_INS_SMOPA = 871 , ARM64_INS_SMOPS = 872 , ARM64_INS_SMOV = 873 , ARM64_INS_SMSTART = 874 , ARM64_INS_SMSTOP = 875 , ARM64_INS_SMSUBL = 876 , ARM64_INS_SMULH = 877 , ARM64_INS_SMULL = 878 , ARM64_INS_SMULL2 = 879 , ARM64_INS_SMULLB = 880 , ARM64_INS_SMULLT = 881 , ARM64_INS_SPLICE = 882 , ARM64_INS_SQABS = 883 , ARM64_INS_SQADD = 884 , ARM64_INS_SQCADD = 885 , ARM64_INS_SQDECB = 886 , ARM64_INS_SQDECD = 887 , ARM64_INS_SQDECH = 888 , ARM64_INS_SQDECP = 889 , ARM64_INS_SQDECW = 890 , ARM64_INS_SQDMLAL = 891 , ARM64_INS_SQDMLAL2 = 892 , ARM64_INS_SQDMLALB = 893 , ARM64_INS_SQDMLALBT = 894 , ARM64_INS_SQDMLALT = 895 , ARM64_INS_SQDMLSL = 896 , ARM64_INS_SQDMLSL2 = 897 , ARM64_INS_SQDMLSLB = 898 , ARM64_INS_SQDMLSLBT = 899 , ARM64_INS_SQDMLSLT = 900 , ARM64_INS_SQDMULH = 901 , ARM64_INS_SQDMULL = 902 , ARM64_INS_SQDMULL2 = 903 , ARM64_INS_SQDMULLB = 904 , ARM64_INS_SQDMULLT = 905 , ARM64_INS_SQINCB = 906 , ARM64_INS_SQINCD = 907 , ARM64_INS_SQINCH = 908 , ARM64_INS_SQINCP = 909 , ARM64_INS_SQINCW = 910 , ARM64_INS_SQNEG = 911 , ARM64_INS_SQRDCMLAH = 912 , ARM64_INS_SQRDMLAH = 913 , ARM64_INS_SQRDMLSH = 914 , ARM64_INS_SQRDMULH = 915 , ARM64_INS_SQRSHL = 916 , ARM64_INS_SQRSHLR = 917 , ARM64_INS_SQRSHRN = 918 , ARM64_INS_SQRSHRN2 = 919 , ARM64_INS_SQRSHRNB = 920 , ARM64_INS_SQRSHRNT = 921 , ARM64_INS_SQRSHRUN = 922 , ARM64_INS_SQRSHRUN2 = 923 , ARM64_INS_SQRSHRUNB = 924 , ARM64_INS_SQRSHRUNT = 925 , ARM64_INS_SQSHL = 926 , ARM64_INS_SQSHLR = 927 , ARM64_INS_SQSHLU = 928 , ARM64_INS_SQSHRN = 929 , ARM64_INS_SQSHRN2 = 930 , ARM64_INS_SQSHRNB = 931 , ARM64_INS_SQSHRNT = 932 , ARM64_INS_SQSHRUN = 933 , ARM64_INS_SQSHRUN2 = 934 , ARM64_INS_SQSHRUNB = 935 , ARM64_INS_SQSHRUNT = 936 , ARM64_INS_SQSUB = 937 , ARM64_INS_SQSUBR = 938 , ARM64_INS_SQXTN = 939 , ARM64_INS_SQXTN2 = 940 , ARM64_INS_SQXTNB = 941 , ARM64_INS_SQXTNT = 942 , ARM64_INS_SQXTUN = 943 , ARM64_INS_SQXTUN2 = 944 , ARM64_INS_SQXTUNB = 945 , ARM64_INS_SQXTUNT = 946 , ARM64_INS_SRHADD = 947 , ARM64_INS_SRI = 948 , ARM64_INS_SRSHL = 949 , ARM64_INS_SRSHLR = 950 , ARM64_INS_SRSHR = 951 , ARM64_INS_SRSRA = 952 , ARM64_INS_SSBB = 953 , ARM64_INS_SSHL = 954 , ARM64_INS_SSHLL = 955 , ARM64_INS_SSHLL2 = 956 , ARM64_INS_SSHLLB = 957 , ARM64_INS_SSHLLT = 958 , ARM64_INS_SSHR = 959 , ARM64_INS_SSRA = 960 , ARM64_INS_SSUBL = 961 , ARM64_INS_SSUBL2 = 962 , ARM64_INS_SSUBLB = 963 , ARM64_INS_SSUBLBT = 964 , ARM64_INS_SSUBLT = 965 , ARM64_INS_SSUBLTB = 966 , ARM64_INS_SSUBW = 967 , ARM64_INS_SSUBW2 = 968 , ARM64_INS_SSUBWB = 969 , ARM64_INS_SSUBWT = 970 , ARM64_INS_ST1 = 971 , ARM64_INS_ST1B = 972 , ARM64_INS_ST1D = 973 , ARM64_INS_ST1H = 974 , ARM64_INS_ST1Q = 975 , ARM64_INS_ST1W = 976 , ARM64_INS_ST2 = 977 , ARM64_INS_ST2B = 978 , ARM64_INS_ST2D = 979 , ARM64_INS_ST2G = 980 , ARM64_INS_ST2H = 981 , ARM64_INS_ST2W = 982 , ARM64_INS_ST3 = 983 , ARM64_INS_ST3B = 984 , ARM64_INS_ST3D = 985 , ARM64_INS_ST3H = 986 , ARM64_INS_ST3W = 987 , ARM64_INS_ST4 = 988 , ARM64_INS_ST4B = 989 , ARM64_INS_ST4D = 990 , ARM64_INS_ST4H = 991 , ARM64_INS_ST4W = 992 , ARM64_INS_ST64B = 993 , ARM64_INS_ST64BV = 994 , ARM64_INS_ST64BV0 = 995 , ARM64_INS_STADD = 996 , ARM64_INS_STADDB = 997 , ARM64_INS_STADDH = 998 , ARM64_INS_STADDL = 999 , ARM64_INS_STADDLB = 1000 , ARM64_INS_STADDLH = 1001 , ARM64_INS_STCLR = 1002 , ARM64_INS_STCLRB = 1003 , ARM64_INS_STCLRH = 1004 , ARM64_INS_STCLRL = 1005 , ARM64_INS_STCLRLB = 1006 , ARM64_INS_STCLRLH = 1007 , ARM64_INS_STEOR = 1008 , ARM64_INS_STEORB = 1009 , ARM64_INS_STEORH = 1010 , ARM64_INS_STEORL = 1011 , ARM64_INS_STEORLB = 1012 , ARM64_INS_STEORLH = 1013 , ARM64_INS_STG = 1014 , ARM64_INS_STGM = 1015 , ARM64_INS_STGP = 1016 , ARM64_INS_STLLR = 1017 , ARM64_INS_STLLRB = 1018 , ARM64_INS_STLLRH = 1019 , ARM64_INS_STLR = 1020 , ARM64_INS_STLRB = 1021 , ARM64_INS_STLRH = 1022 , ARM64_INS_STLUR = 1023 , ARM64_INS_STLURB = 1024 , ARM64_INS_STLURH = 1025 , ARM64_INS_STLXP = 1026 , ARM64_INS_STLXR = 1027 , ARM64_INS_STLXRB = 1028 , ARM64_INS_STLXRH = 1029 , ARM64_INS_STNP = 1030 , ARM64_INS_STNT1B = 1031 , ARM64_INS_STNT1D = 1032 , ARM64_INS_STNT1H = 1033 , ARM64_INS_STNT1W = 1034 , ARM64_INS_STP = 1035 , ARM64_INS_STR = 1036 , ARM64_INS_STRB = 1037 , ARM64_INS_STRH = 1038 , ARM64_INS_STSET = 1039 , ARM64_INS_STSETB = 1040 , ARM64_INS_STSETH = 1041 , ARM64_INS_STSETL = 1042 , ARM64_INS_STSETLB = 1043 , ARM64_INS_STSETLH = 1044 , ARM64_INS_STSMAX = 1045 , ARM64_INS_STSMAXB = 1046 , ARM64_INS_STSMAXH = 1047 , ARM64_INS_STSMAXL = 1048 , ARM64_INS_STSMAXLB = 1049 , ARM64_INS_STSMAXLH = 1050 , ARM64_INS_STSMIN = 1051 , ARM64_INS_STSMINB = 1052 , ARM64_INS_STSMINH = 1053 , ARM64_INS_STSMINL = 1054 , ARM64_INS_STSMINLB = 1055 , ARM64_INS_STSMINLH = 1056 , ARM64_INS_STTR = 1057 , ARM64_INS_STTRB = 1058 , ARM64_INS_STTRH = 1059 , ARM64_INS_STUMAX = 1060 , ARM64_INS_STUMAXB = 1061 , ARM64_INS_STUMAXH = 1062 , ARM64_INS_STUMAXL = 1063 , ARM64_INS_STUMAXLB = 1064 , ARM64_INS_STUMAXLH = 1065 , ARM64_INS_STUMIN = 1066 , ARM64_INS_STUMINB = 1067 , ARM64_INS_STUMINH = 1068 , ARM64_INS_STUMINL = 1069 , ARM64_INS_STUMINLB = 1070 , ARM64_INS_STUMINLH = 1071 , ARM64_INS_STUR = 1072 , ARM64_INS_STURB = 1073 , ARM64_INS_STURH = 1074 , ARM64_INS_STXP = 1075 , ARM64_INS_STXR = 1076 , ARM64_INS_STXRB = 1077 , ARM64_INS_STXRH = 1078 , ARM64_INS_STZ2G = 1079 , ARM64_INS_STZG = 1080 , ARM64_INS_STZGM = 1081 , ARM64_INS_SUB = 1082 , ARM64_INS_SUBG = 1083 , ARM64_INS_SUBHN = 1084 , ARM64_INS_SUBHN2 = 1085 , ARM64_INS_SUBHNB = 1086 , ARM64_INS_SUBHNT = 1087 , ARM64_INS_SUBP = 1088 , ARM64_INS_SUBPS = 1089 , ARM64_INS_SUBR = 1090 , ARM64_INS_SUBS = 1091 , ARM64_INS_SUDOT = 1092 , ARM64_INS_SUMOPA = 1093 , ARM64_INS_SUMOPS = 1094 , ARM64_INS_SUNPKHI = 1095 , ARM64_INS_SUNPKLO = 1096 , ARM64_INS_SUQADD = 1097 , ARM64_INS_SVC = 1098 , ARM64_INS_SWP = 1099 , ARM64_INS_SWPA = 1100 , ARM64_INS_SWPAB = 1101 , ARM64_INS_SWPAH = 1102 , ARM64_INS_SWPAL = 1103 , ARM64_INS_SWPALB = 1104 , ARM64_INS_SWPALH = 1105 , ARM64_INS_SWPB = 1106 , ARM64_INS_SWPH = 1107 , ARM64_INS_SWPL = 1108 , ARM64_INS_SWPLB = 1109 , ARM64_INS_SWPLH = 1110 , ARM64_INS_SXTB = 1111 , ARM64_INS_SXTH = 1112 , ARM64_INS_SXTL = 1113 , ARM64_INS_SXTL2 = 1114 , ARM64_INS_SXTW = 1115 , ARM64_INS_SYS = 1116 , ARM64_INS_SYSL = 1117 , ARM64_INS_TBL = 1118 , ARM64_INS_TBNZ = 1119 , ARM64_INS_TBX = 1120 , ARM64_INS_TBZ = 1121 , ARM64_INS_TCANCEL = 1122 , ARM64_INS_TCOMMIT = 1123 , ARM64_INS_TRN1 = 1124 , ARM64_INS_TRN2 = 1125 , ARM64_INS_TSB = 1126 , ARM64_INS_TST = 1127 , ARM64_INS_TSTART = 1128 , ARM64_INS_TTEST = 1129 , ARM64_INS_UABA = 1130 , ARM64_INS_UABAL = 1131 , ARM64_INS_UABAL2 = 1132 , ARM64_INS_UABALB = 1133 , ARM64_INS_UABALT = 1134 , ARM64_INS_UABD = 1135 , ARM64_INS_UABDL = 1136 , ARM64_INS_UABDL2 = 1137 , ARM64_INS_UABDLB = 1138 , ARM64_INS_UABDLT = 1139 , ARM64_INS_UADALP = 1140 , ARM64_INS_UADDL = 1141 , ARM64_INS_UADDL2 = 1142 , ARM64_INS_UADDLB = 1143 , ARM64_INS_UADDLP = 1144 , ARM64_INS_UADDLT = 1145 , ARM64_INS_UADDLV = 1146 , ARM64_INS_UADDV = 1147 , ARM64_INS_UADDW = 1148 , ARM64_INS_UADDW2 = 1149 , ARM64_INS_UADDWB = 1150 , ARM64_INS_UADDWT = 1151 , ARM64_INS_UBFM = 1152 , ARM64_INS_UCLAMP = 1153 , ARM64_INS_UCVTF = 1154 , ARM64_INS_UDF = 1155 , ARM64_INS_UDIV = 1156 , ARM64_INS_UDIVR = 1157 , ARM64_INS_UDOT = 1158 , ARM64_INS_UHADD = 1159 , ARM64_INS_UHSUB = 1160 , ARM64_INS_UHSUBR = 1161 , ARM64_INS_UMADDL = 1162 , ARM64_INS_UMAX = 1163 , ARM64_INS_UMAXP = 1164 , ARM64_INS_UMAXV = 1165 , ARM64_INS_UMIN = 1166 , ARM64_INS_UMINP = 1167 , ARM64_INS_UMINV = 1168 , ARM64_INS_UMLAL = 1169 , ARM64_INS_UMLAL2 = 1170 , ARM64_INS_UMLALB = 1171 , ARM64_INS_UMLALT = 1172 , ARM64_INS_UMLSL = 1173 , ARM64_INS_UMLSL2 = 1174 , ARM64_INS_UMLSLB = 1175 , ARM64_INS_UMLSLT = 1176 , ARM64_INS_UMMLA = 1177 , ARM64_INS_UMNEGL = 1178 , ARM64_INS_UMOPA = 1179 , ARM64_INS_UMOPS = 1180 , ARM64_INS_UMOV = 1181 , ARM64_INS_UMSUBL = 1182 , ARM64_INS_UMULH = 1183 , ARM64_INS_UMULL = 1184 , ARM64_INS_UMULL2 = 1185 , ARM64_INS_UMULLB = 1186 , ARM64_INS_UMULLT = 1187 , ARM64_INS_UQADD = 1188 , ARM64_INS_UQDECB = 1189 , ARM64_INS_UQDECD = 1190 , ARM64_INS_UQDECH = 1191 , ARM64_INS_UQDECP = 1192 , ARM64_INS_UQDECW = 1193 , ARM64_INS_UQINCB = 1194 , ARM64_INS_UQINCD = 1195 , ARM64_INS_UQINCH = 1196 , ARM64_INS_UQINCP = 1197 , ARM64_INS_UQINCW = 1198 , ARM64_INS_UQRSHL = 1199 , ARM64_INS_UQRSHLR = 1200 , ARM64_INS_UQRSHRN = 1201 , ARM64_INS_UQRSHRN2 = 1202 , ARM64_INS_UQRSHRNB = 1203 , ARM64_INS_UQRSHRNT = 1204 , ARM64_INS_UQSHL = 1205 , ARM64_INS_UQSHLR = 1206 , ARM64_INS_UQSHRN = 1207 , ARM64_INS_UQSHRN2 = 1208 , ARM64_INS_UQSHRNB = 1209 , ARM64_INS_UQSHRNT = 1210 , ARM64_INS_UQSUB = 1211 , ARM64_INS_UQSUBR = 1212 , ARM64_INS_UQXTN = 1213 , ARM64_INS_UQXTN2 = 1214 , ARM64_INS_UQXTNB = 1215 , ARM64_INS_UQXTNT = 1216 , ARM64_INS_URECPE = 1217 , ARM64_INS_URHADD = 1218 , ARM64_INS_URSHL = 1219 , ARM64_INS_URSHLR = 1220 , ARM64_INS_URSHR = 1221 , ARM64_INS_URSQRTE = 1222 , ARM64_INS_URSRA = 1223 , ARM64_INS_USDOT = 1224 , ARM64_INS_USHL = 1225 , ARM64_INS_USHLL = 1226 , ARM64_INS_USHLL2 = 1227 , ARM64_INS_USHLLB = 1228 , ARM64_INS_USHLLT = 1229 , ARM64_INS_USHR = 1230 , ARM64_INS_USMMLA = 1231 , ARM64_INS_USMOPA = 1232 , ARM64_INS_USMOPS = 1233 , ARM64_INS_USQADD = 1234 , ARM64_INS_USRA = 1235 , ARM64_INS_USUBL = 1236 , ARM64_INS_USUBL2 = 1237 , ARM64_INS_USUBLB = 1238 , ARM64_INS_USUBLT = 1239 , ARM64_INS_USUBW = 1240 , ARM64_INS_USUBW2 = 1241 , ARM64_INS_USUBWB = 1242 , ARM64_INS_USUBWT = 1243 , ARM64_INS_UUNPKHI = 1244 , ARM64_INS_UUNPKLO = 1245 , ARM64_INS_UXTB = 1246 , ARM64_INS_UXTH = 1247 , ARM64_INS_UXTL = 1248 , ARM64_INS_UXTL2 = 1249 , ARM64_INS_UXTW = 1250 , ARM64_INS_UZP1 = 1251 , ARM64_INS_UZP2 = 1252 , ARM64_INS_WFE = 1253 , ARM64_INS_WFET = 1254 , ARM64_INS_WFI = 1255 , ARM64_INS_WFIT = 1256 , ARM64_INS_WHILEGE = 1257 , ARM64_INS_WHILEGT = 1258 , ARM64_INS_WHILEHI = 1259 , ARM64_INS_WHILEHS = 1260 , ARM64_INS_WHILELE = 1261 , ARM64_INS_WHILELO = 1262 , ARM64_INS_WHILELS = 1263 , ARM64_INS_WHILELT = 1264 , ARM64_INS_WHILERW = 1265 , ARM64_INS_WHILEWR = 1266 , ARM64_INS_WRFFR = 1267 , ARM64_INS_XAFLAG = 1268 , ARM64_INS_XAR = 1269 , ARM64_INS_XPACD = 1270 , ARM64_INS_XPACI = 1271 , ARM64_INS_XPACLRI = 1272 , ARM64_INS_XTN = 1273 , ARM64_INS_XTN2 = 1274 , ARM64_INS_YIELD = 1275 , ARM64_INS_ZERO = 1276 , ARM64_INS_ZIP1 = 1277 , ARM64_INS_ZIP2 = 1278 , ARM64_INS_SBFIZ = 1279 , ARM64_INS_UBFIZ = 1280 , ARM64_INS_SBFX = 1281 , ARM64_INS_UBFX = 1282 , ARM64_INS_BFI = 1283 , ARM64_INS_BFXIL = 1284 , ARM64_INS_IC = 1285 , ARM64_INS_DC = 1286 , ARM64_INS_AT = 1287 , ARM64_INS_TLBI = 1288 , ARM64_INS_ENDING = 1289 , } # [repr (u32)] # [doc = " Group of ARM64 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM64_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM64_GRP_JUMP = 1 , ARM64_GRP_CALL = 2 , ARM64_GRP_RET = 3 , ARM64_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM64_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM64_GRP_BRANCH_RELATIVE = 7 , ARM64_GRP_PAC = 8 , ARM64_GRP_CRYPTO = 128 , ARM64_GRP_FPARMV8 = 129 , ARM64_GRP_NEON = 130 , ARM64_GRP_CRC = 131 , ARM64_GRP_AES = 132 , ARM64_GRP_DOTPROD = 133 , ARM64_GRP_FULLFP16 = 134 , ARM64_GRP_LSE = 135 , ARM64_GRP_RCPC = 136 , ARM64_GRP_RDM = 137 , ARM64_GRP_SHA2 = 138 , ARM64_GRP_SHA3 = 139 , ARM64_GRP_SM4 = 140 , ARM64_GRP_SVE = 141 , ARM64_GRP_SVE2 = 142 , ARM64_GRP_SVE2AES = 143 , ARM64_GRP_SVE2BitPerm = 144 , ARM64_GRP_SVE2SHA3 = 145 , ARM64_GRP_SVE2SM4 = 146 , ARM64_GRP_SME = 147 , ARM64_GRP_SMEF64 = 148 , ARM64_GRP_SMEI64 = 149 , ARM64_GRP_MatMulFP32 = 150 , ARM64_GRP_MatMulFP64 = 151 , ARM64_GRP_MatMulInt8 = 152 , ARM64_GRP_V8_1A = 153 , ARM64_GRP_V8_3A = 154 , ARM64_GRP_V8_4A = 155 , ARM64_GRP_ENDING = 156 , } # [repr (u32)] # [doc = " M68K registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_reg { M68K_REG_INVALID = 0 , M68K_REG_D0 = 1 , M68K_REG_D1 = 2 , M68K_REG_D2 = 3 , M68K_REG_D3 = 4 , M68K_REG_D4 = 5 , M68K_REG_D5 = 6 , M68K_REG_D6 = 7 , M68K_REG_D7 = 8 , M68K_REG_A0 = 9 , M68K_REG_A1 = 10 , M68K_REG_A2 = 11 , M68K_REG_A3 = 12 , M68K_REG_A4 = 13 , M68K_REG_A5 = 14 , M68K_REG_A6 = 15 , M68K_REG_A7 = 16 , M68K_REG_FP0 = 17 , M68K_REG_FP1 = 18 , M68K_REG_FP2 = 19 , M68K_REG_FP3 = 20 , M68K_REG_FP4 = 21 , M68K_REG_FP5 = 22 , M68K_REG_FP6 = 23 , M68K_REG_FP7 = 24 , M68K_REG_PC = 25 , M68K_REG_SR = 26 , M68K_REG_CCR = 27 , M68K_REG_SFC = 28 , M68K_REG_DFC = 29 , M68K_REG_USP = 30 , M68K_REG_VBR = 31 , M68K_REG_CACR = 32 , M68K_REG_CAAR = 33 , M68K_REG_MSP = 34 , M68K_REG_ISP = 35 , M68K_REG_TC = 36 , M68K_REG_ITT0 = 37 , M68K_REG_ITT1 = 38 , M68K_REG_DTT0 = 39 , M68K_REG_DTT1 = 40 , M68K_REG_MMUSR = 41 , M68K_REG_URP = 42 , M68K_REG_SRP = 43 , M68K_REG_FPCR = 44 , M68K_REG_FPSR = 45 , M68K_REG_FPIAR = 46 , M68K_REG_ENDING = 47 , } # [repr (u32)] # [doc = " M68K Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_address_mode { # [doc = "< No address mode."] M68K_AM_NONE = 0 , # [doc = "< Register Direct - Data"] M68K_AM_REG_DIRECT_DATA = 1 , # [doc = "< Register Direct - Address"] M68K_AM_REG_DIRECT_ADDR = 2 , # [doc = "< Register Indirect - Address"] M68K_AM_REGI_ADDR = 3 , # [doc = "< Register Indirect - Address with Postincrement"] M68K_AM_REGI_ADDR_POST_INC = 4 , # [doc = "< Register Indirect - Address with Predecrement"] M68K_AM_REGI_ADDR_PRE_DEC = 5 , # [doc = "< Register Indirect - Address with Displacement"] M68K_AM_REGI_ADDR_DISP = 6 , # [doc = "< Address Register Indirect With Index- 8-bit displacement"] M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 , # [doc = "< Address Register Indirect With Index- Base displacement"] M68K_AM_AREGI_INDEX_BASE_DISP = 8 , # [doc = "< Memory indirect - Postindex"] M68K_AM_MEMI_POST_INDEX = 9 , # [doc = "< Memory indirect - Preindex"] M68K_AM_MEMI_PRE_INDEX = 10 , # [doc = "< Program Counter Indirect - with Displacement"] M68K_AM_PCI_DISP = 11 , # [doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"] M68K_AM_PCI_INDEX_8_BIT_DISP = 12 , # [doc = "< Program Counter Indirect with Index - with Base Displacement"] M68K_AM_PCI_INDEX_BASE_DISP = 13 , # [doc = "< Program Counter Memory Indirect - Postindexed"] M68K_AM_PC_MEMI_POST_INDEX = 14 , # [doc = "< Program Counter Memory Indirect - Preindexed"] M68K_AM_PC_MEMI_PRE_INDEX = 15 , # [doc = "< Absolute Data Addressing  - Short"] M68K_AM_ABSOLUTE_DATA_SHORT = 16 , # [doc = "< Absolute Data Addressing  - Long"] M68K_AM_ABSOLUTE_DATA_LONG = 17 , # [doc = "< Immediate value"] M68K_AM_IMMEDIATE = 18 , # [doc = "< Address as displacement from (PC+2) used by branches"] M68K_AM_BRANCH_DISPLACEMENT = 19 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] M68K_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] M68K_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] M68K_OP_MEM = 3 , # [doc = "< single precision Floating-Point operand"] M68K_OP_FP_SINGLE = 4 , # [doc = "< double precision Floating-Point operand"] M68K_OP_FP_DOUBLE = 5 , # [doc = "< Register bits move"] M68K_OP_REG_BITS = 6 , # [doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"] M68K_OP_REG_PAIR = 7 , # [doc = "< Branch displacement"] M68K_OP_BR_DISP = 8 , } # [doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_mem { # [doc = "< base register (or M68K_REG_INVALID if irrelevant)"] pub base_reg : m68k_reg , # [doc = "< index register (or M68K_REG_INVALID if irrelevant)"] pub index_reg : m68k_reg , # [doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"] pub in_base_reg : m68k_reg , # [doc = "< indirect displacement"] pub in_disp : u32 , # [doc = "< other displacement"] pub out_disp : u32 , # [doc = "< displacement value"] pub disp : i16 , # [doc = "< scale for index register"] pub scale : u8 , # [doc = "< set to true if the two values below should be used"] pub bitfield : u8 , # [doc = "< used for bf* instructions"] pub width : u8 , # [doc = "< used for bf* instructions"] pub offset : u8 , # [doc = "< 0 = w, 1 = l"] pub index_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_mem"] [:: std :: mem :: size_of :: < m68k_op_mem > () - 28usize] ; ["Alignment of m68k_op_mem"] [:: std :: mem :: align_of :: < m68k_op_mem > () - 4usize] ; ["Offset of field: m68k_op_mem::base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , base_reg) - 0usize] ; ["Offset of field: m68k_op_mem::index_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_reg) - 4usize] ; ["Offset of field: m68k_op_mem::in_base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_base_reg) - 8usize] ; ["Offset of field: m68k_op_mem::in_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_disp) - 12usize] ; ["Offset of field: m68k_op_mem::out_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , out_disp) - 16usize] ; ["Offset of field: m68k_op_mem::disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , disp) - 20usize] ; ["Offset of field: m68k_op_mem::scale"] [:: std :: mem :: offset_of ! (m68k_op_mem , scale) - 22usize] ; ["Offset of field: m68k_op_mem::bitfield"] [:: std :: mem :: offset_of ! (m68k_op_mem , bitfield) - 23usize] ; ["Offset of field: m68k_op_mem::width"] [:: std :: mem :: offset_of ! (m68k_op_mem , width) - 24usize] ; ["Offset of field: m68k_op_mem::offset"] [:: std :: mem :: offset_of ! (m68k_op_mem , offset) - 25usize] ; ["Offset of field: m68k_op_mem::index_size"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_size) - 26usize] ; } ; # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_br_disp_size { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_BR_DISP_SIZE_INVALID = 0 , # [doc = "< signed 8-bit displacement"] M68K_OP_BR_DISP_SIZE_BYTE = 1 , # [doc = "< signed 16-bit displacement"] M68K_OP_BR_DISP_SIZE_WORD = 2 , # [doc = "< signed 32-bit displacement"] M68K_OP_BR_DISP_SIZE_LONG = 4 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_br_disp { # [doc = "< displacement value"] pub disp : i32 , # [doc = "< Size from m68k_op_br_disp_size type above"] pub disp_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_br_disp"] [:: std :: mem :: size_of :: < m68k_op_br_disp > () - 8usize] ; ["Alignment of m68k_op_br_disp"] [:: std :: mem :: align_of :: < m68k_op_br_disp > () - 4usize] ; ["Offset of field: m68k_op_br_disp::disp"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp) - 0usize] ; ["Offset of field: m68k_op_br_disp::disp_size"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp_size) - 4usize] ; } ; # [doc = " Register pair in one operand."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_m68k_op_reg_pair { pub reg_0 : m68k_reg , pub reg_1 : m68k_reg , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op_reg_pair"] [:: std :: mem :: size_of :: < cs_m68k_op_reg_pair > () - 8usize] ; ["Alignment of cs_m68k_op_reg_pair"] [:: std :: mem :: align_of :: < cs_m68k_op_reg_pair > () - 4usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_0"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_0) - 0usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_1"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_1) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k_op { pub __bindgen_anon_1 : cs_m68k_op__bindgen_ty_1 , # [doc = "< data when operand is targeting memory"] pub mem : m68k_op_mem , # [doc = "< data when operand is a branch displacement"] pub br_disp : m68k_op_br_disp , # [doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"] pub register_bits : u32 , pub type_ : m68k_op_type , # [doc = "< M68K addressing mode for this op"] pub address_mode : m68k_address_mode , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m68k_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< double imm"] pub dimm : f64 , # [doc = "< float imm"] pub simm : f32 , # [doc = "< register value for REG operand"] pub reg : m68k_reg , # [doc = "< register pair in one operand"] pub reg_pair : cs_m68k_op_reg_pair , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::dimm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , dimm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::simm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , simm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg_pair"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg_pair) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op"] [:: std :: mem :: size_of :: < cs_m68k_op > () - 56usize] ; ["Alignment of cs_m68k_op"] [:: std :: mem :: align_of :: < cs_m68k_op > () - 8usize] ; ["Offset of field: cs_m68k_op::mem"] [:: std :: mem :: offset_of ! (cs_m68k_op , mem) - 8usize] ; ["Offset of field: cs_m68k_op::br_disp"] [:: std :: mem :: offset_of ! (cs_m68k_op , br_disp) - 36usize] ; ["Offset of field: cs_m68k_op::register_bits"] [:: std :: mem :: offset_of ! (cs_m68k_op , register_bits) - 44usize] ; ["Offset of field: cs_m68k_op::type_"] [:: std :: mem :: offset_of ! (cs_m68k_op , type_) - 48usize] ; ["Offset of field: cs_m68k_op::address_mode"] [:: std :: mem :: offset_of ! (cs_m68k_op , address_mode) - 52usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode) } } # [repr (u32)] # [doc = " Operation size of the CPU instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_cpu_size { # [doc = "< unsized or unspecified"] M68K_CPU_SIZE_NONE = 0 , # [doc = "< 1 byte in size"] M68K_CPU_SIZE_BYTE = 1 , # [doc = "< 2 bytes in size"] M68K_CPU_SIZE_WORD = 2 , # [doc = "< 4 bytes in size"] M68K_CPU_SIZE_LONG = 4 , } # [repr (u32)] # [doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_fpu_size { # [doc = "< unsized like fsave/frestore"] M68K_FPU_SIZE_NONE = 0 , # [doc = "< 4 byte in size (single float)"] M68K_FPU_SIZE_SINGLE = 4 , # [doc = "< 8 byte in size (double)"] M68K_FPU_SIZE_DOUBLE = 8 , # [doc = "< 12 byte in size (extended real format)"] M68K_FPU_SIZE_EXTENDED = 12 , } # [repr (u32)] # [doc = " Type of size that is being used for the current instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0 , M68K_SIZE_TYPE_CPU = 1 , M68K_SIZE_TYPE_FPU = 2 , } # [doc = " Operation size of the current instruction (NOT the actually size of instruction)"] # [repr (C)] # [derive (Copy , Clone)] pub struct m68k_op_size { pub type_ : m68k_size_type , pub __bindgen_anon_1 : m68k_op_size__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union m68k_op_size__bindgen_ty_1 { pub cpu_size : m68k_cpu_size , pub fpu_size : m68k_fpu_size , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: size_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Alignment of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: align_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::cpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , cpu_size) - 0usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::fpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , fpu_size) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size"] [:: std :: mem :: size_of :: < m68k_op_size > () - 8usize] ; ["Alignment of m68k_op_size"] [:: std :: mem :: align_of :: < m68k_op_size > () - 4usize] ; ["Offset of field: m68k_op_size::type_"] [:: std :: mem :: offset_of ! (m68k_op_size , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The M68K instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k { # [doc = "< operands for this instruction."] pub operands : [cs_m68k_op ; 4usize] , # [doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"] pub op_size : m68k_op_size , # [doc = "< number of operands for the instruction"] pub op_count : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k"] [:: std :: mem :: size_of :: < cs_m68k > () - 240usize] ; ["Alignment of cs_m68k"] [:: std :: mem :: align_of :: < cs_m68k > () - 8usize] ; ["Offset of field: cs_m68k::operands"] [:: std :: mem :: offset_of ! (cs_m68k , operands) - 0usize] ; ["Offset of field: cs_m68k::op_size"] [:: std :: mem :: offset_of ! (cs_m68k , op_size) - 224usize] ; ["Offset of field: cs_m68k::op_count"] [:: std :: mem :: offset_of ! (cs_m68k , op_count) - 232usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}" , self . operands , self . op_size , self . op_count) } } # [repr (u32)] # [doc = " M68K instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_insn { M68K_INS_INVALID = 0 , M68K_INS_ABCD = 1 , M68K_INS_ADD = 2 , M68K_INS_ADDA = 3 , M68K_INS_ADDI = 4 , M68K_INS_ADDQ = 5 , M68K_INS_ADDX = 6 , M68K_INS_AND = 7 , M68K_INS_ANDI = 8 , M68K_INS_ASL = 9 , M68K_INS_ASR = 10 , M68K_INS_BHS = 11 , M68K_INS_BLO = 12 , M68K_INS_BHI = 13 , M68K_INS_BLS = 14 , M68K_INS_BCC = 15 , M68K_INS_BCS = 16 , M68K_INS_BNE = 17 , M68K_INS_BEQ = 18 , M68K_INS_BVC = 19 , M68K_INS_BVS = 20 , M68K_INS_BPL = 21 , M68K_INS_BMI = 22 , M68K_INS_BGE = 23 , M68K_INS_BLT = 24 , M68K_INS_BGT = 25 , M68K_INS_BLE = 26 , M68K_INS_BRA = 27 , M68K_INS_BSR = 28 , M68K_INS_BCHG = 29 , M68K_INS_BCLR = 30 , M68K_INS_BSET = 31 , M68K_INS_BTST = 32 , M68K_INS_BFCHG = 33 , M68K_INS_BFCLR = 34 , M68K_INS_BFEXTS = 35 , M68K_INS_BFEXTU = 36 , M68K_INS_BFFFO = 37 , M68K_INS_BFINS = 38 , M68K_INS_BFSET = 39 , M68K_INS_BFTST = 40 , M68K_INS_BKPT = 41 , M68K_INS_CALLM = 42 , M68K_INS_CAS = 43 , M68K_INS_CAS2 = 44 , M68K_INS_CHK = 45 , M68K_INS_CHK2 = 46 , M68K_INS_CLR = 47 , M68K_INS_CMP = 48 , M68K_INS_CMPA = 49 , M68K_INS_CMPI = 50 , M68K_INS_CMPM = 51 , M68K_INS_CMP2 = 52 , M68K_INS_CINVL = 53 , M68K_INS_CINVP = 54 , M68K_INS_CINVA = 55 , M68K_INS_CPUSHL = 56 , M68K_INS_CPUSHP = 57 , M68K_INS_CPUSHA = 58 , M68K_INS_DBT = 59 , M68K_INS_DBF = 60 , M68K_INS_DBHI = 61 , M68K_INS_DBLS = 62 , M68K_INS_DBCC = 63 , M68K_INS_DBCS = 64 , M68K_INS_DBNE = 65 , M68K_INS_DBEQ = 66 , M68K_INS_DBVC = 67 , M68K_INS_DBVS = 68 , M68K_INS_DBPL = 69 , M68K_INS_DBMI = 70 , M68K_INS_DBGE = 71 , M68K_INS_DBLT = 72 , M68K_INS_DBGT = 73 , M68K_INS_DBLE = 74 , M68K_INS_DBRA = 75 , M68K_INS_DIVS = 76 , M68K_INS_DIVSL = 77 , M68K_INS_DIVU = 78 , M68K_INS_DIVUL = 79 , M68K_INS_EOR = 80 , M68K_INS_EORI = 81 , M68K_INS_EXG = 82 , M68K_INS_EXT = 83 , M68K_INS_EXTB = 84 , M68K_INS_FABS = 85 , M68K_INS_FSABS = 86 , M68K_INS_FDABS = 87 , M68K_INS_FACOS = 88 , M68K_INS_FADD = 89 , M68K_INS_FSADD = 90 , M68K_INS_FDADD = 91 , M68K_INS_FASIN = 92 , M68K_INS_FATAN = 93 , M68K_INS_FATANH = 94 , M68K_INS_FBF = 95 , M68K_INS_FBEQ = 96 , M68K_INS_FBOGT = 97 , M68K_INS_FBOGE = 98 , M68K_INS_FBOLT = 99 , M68K_INS_FBOLE = 100 , M68K_INS_FBOGL = 101 , M68K_INS_FBOR = 102 , M68K_INS_FBUN = 103 , M68K_INS_FBUEQ = 104 , M68K_INS_FBUGT = 105 , M68K_INS_FBUGE = 106 , M68K_INS_FBULT = 107 , M68K_INS_FBULE = 108 , M68K_INS_FBNE = 109 , M68K_INS_FBT = 110 , M68K_INS_FBSF = 111 , M68K_INS_FBSEQ = 112 , M68K_INS_FBGT = 113 , M68K_INS_FBGE = 114 , M68K_INS_FBLT = 115 , M68K_INS_FBLE = 116 , M68K_INS_FBGL = 117 , M68K_INS_FBGLE = 118 , M68K_INS_FBNGLE = 119 , M68K_INS_FBNGL = 120 , M68K_INS_FBNLE = 121 , M68K_INS_FBNLT = 122 , M68K_INS_FBNGE = 123 , M68K_INS_FBNGT = 124 , M68K_INS_FBSNE = 125 , M68K_INS_FBST = 126 , M68K_INS_FCMP = 127 , M68K_INS_FCOS = 128 , M68K_INS_FCOSH = 129 , M68K_INS_FDBF = 130 , M68K_INS_FDBEQ = 131 , M68K_INS_FDBOGT = 132 , M68K_INS_FDBOGE = 133 , M68K_INS_FDBOLT = 134 , M68K_INS_FDBOLE = 135 , M68K_INS_FDBOGL = 136 , M68K_INS_FDBOR = 137 , M68K_INS_FDBUN = 138 , M68K_INS_FDBUEQ = 139 , M68K_INS_FDBUGT = 140 , M68K_INS_FDBUGE = 141 , M68K_INS_FDBULT = 142 , M68K_INS_FDBULE = 143 , M68K_INS_FDBNE = 144 , M68K_INS_FDBT = 145 , M68K_INS_FDBSF = 146 , M68K_INS_FDBSEQ = 147 , M68K_INS_FDBGT = 148 , M68K_INS_FDBGE = 149 , M68K_INS_FDBLT = 150 , M68K_INS_FDBLE = 151 , M68K_INS_FDBGL = 152 , M68K_INS_FDBGLE = 153 , M68K_INS_FDBNGLE = 154 , M68K_INS_FDBNGL = 155 , M68K_INS_FDBNLE = 156 , M68K_INS_FDBNLT = 157 , M68K_INS_FDBNGE = 158 , M68K_INS_FDBNGT = 159 , M68K_INS_FDBSNE = 160 , M68K_INS_FDBST = 161 , M68K_INS_FDIV = 162 , M68K_INS_FSDIV = 163 , M68K_INS_FDDIV = 164 , M68K_INS_FETOX = 165 , M68K_INS_FETOXM1 = 166 , M68K_INS_FGETEXP = 167 , M68K_INS_FGETMAN = 168 , M68K_INS_FINT = 169 , M68K_INS_FINTRZ = 170 , M68K_INS_FLOG10 = 171 , M68K_INS_FLOG2 = 172 , M68K_INS_FLOGN = 173 , M68K_INS_FLOGNP1 = 174 , M68K_INS_FMOD = 175 , M68K_INS_FMOVE = 176 , M68K_INS_FSMOVE = 177 , M68K_INS_FDMOVE = 178 , M68K_INS_FMOVECR = 179 , M68K_INS_FMOVEM = 180 , M68K_INS_FMUL = 181 , M68K_INS_FSMUL = 182 , M68K_INS_FDMUL = 183 , M68K_INS_FNEG = 184 , M68K_INS_FSNEG = 185 , M68K_INS_FDNEG = 186 , M68K_INS_FNOP = 187 , M68K_INS_FREM = 188 , M68K_INS_FRESTORE = 189 , M68K_INS_FSAVE = 190 , M68K_INS_FSCALE = 191 , M68K_INS_FSGLDIV = 192 , M68K_INS_FSGLMUL = 193 , M68K_INS_FSIN = 194 , M68K_INS_FSINCOS = 195 , M68K_INS_FSINH = 196 , M68K_INS_FSQRT = 197 , M68K_INS_FSSQRT = 198 , M68K_INS_FDSQRT = 199 , M68K_INS_FSF = 200 , M68K_INS_FSBEQ = 201 , M68K_INS_FSOGT = 202 , M68K_INS_FSOGE = 203 , M68K_INS_FSOLT = 204 , M68K_INS_FSOLE = 205 , M68K_INS_FSOGL = 206 , M68K_INS_FSOR = 207 , M68K_INS_FSUN = 208 , M68K_INS_FSUEQ = 209 , M68K_INS_FSUGT = 210 , M68K_INS_FSUGE = 211 , M68K_INS_FSULT = 212 , M68K_INS_FSULE = 213 , M68K_INS_FSNE = 214 , M68K_INS_FST = 215 , M68K_INS_FSSF = 216 , M68K_INS_FSSEQ = 217 , M68K_INS_FSGT = 218 , M68K_INS_FSGE = 219 , M68K_INS_FSLT = 220 , M68K_INS_FSLE = 221 , M68K_INS_FSGL = 222 , M68K_INS_FSGLE = 223 , M68K_INS_FSNGLE = 224 , M68K_INS_FSNGL = 225 , M68K_INS_FSNLE = 226 , M68K_INS_FSNLT = 227 , M68K_INS_FSNGE = 228 , M68K_INS_FSNGT = 229 , M68K_INS_FSSNE = 230 , M68K_INS_FSST = 231 , M68K_INS_FSUB = 232 , M68K_INS_FSSUB = 233 , M68K_INS_FDSUB = 234 , M68K_INS_FTAN = 235 , M68K_INS_FTANH = 236 , M68K_INS_FTENTOX = 237 , M68K_INS_FTRAPF = 238 , M68K_INS_FTRAPEQ = 239 , M68K_INS_FTRAPOGT = 240 , M68K_INS_FTRAPOGE = 241 , M68K_INS_FTRAPOLT = 242 , M68K_INS_FTRAPOLE = 243 , M68K_INS_FTRAPOGL = 244 , M68K_INS_FTRAPOR = 245 , M68K_INS_FTRAPUN = 246 , M68K_INS_FTRAPUEQ = 247 , M68K_INS_FTRAPUGT = 248 , M68K_INS_FTRAPUGE = 249 , M68K_INS_FTRAPULT = 250 , M68K_INS_FTRAPULE = 251 , M68K_INS_FTRAPNE = 252 , M68K_INS_FTRAPT = 253 , M68K_INS_FTRAPSF = 254 , M68K_INS_FTRAPSEQ = 255 , M68K_INS_FTRAPGT = 256 , M68K_INS_FTRAPGE = 257 , M68K_INS_FTRAPLT = 258 , M68K_INS_FTRAPLE = 259 , M68K_INS_FTRAPGL = 260 , M68K_INS_FTRAPGLE = 261 , M68K_INS_FTRAPNGLE = 262 , M68K_INS_FTRAPNGL = 263 , M68K_INS_FTRAPNLE = 264 , M68K_INS_FTRAPNLT = 265 , M68K_INS_FTRAPNGE = 266 , M68K_INS_FTRAPNGT = 267 , M68K_INS_FTRAPSNE = 268 , M68K_INS_FTRAPST = 269 , M68K_INS_FTST = 270 , M68K_INS_FTWOTOX = 271 , M68K_INS_HALT = 272 , M68K_INS_ILLEGAL = 273 , M68K_INS_JMP = 274 , M68K_INS_JSR = 275 , M68K_INS_LEA = 276 , M68K_INS_LINK = 277 , M68K_INS_LPSTOP = 278 , M68K_INS_LSL = 279 , M68K_INS_LSR = 280 , M68K_INS_MOVE = 281 , M68K_INS_MOVEA = 282 , M68K_INS_MOVEC = 283 , M68K_INS_MOVEM = 284 , M68K_INS_MOVEP = 285 , M68K_INS_MOVEQ = 286 , M68K_INS_MOVES = 287 , M68K_INS_MOVE16 = 288 , M68K_INS_MULS = 289 , M68K_INS_MULU = 290 , M68K_INS_NBCD = 291 , M68K_INS_NEG = 292 , M68K_INS_NEGX = 293 , M68K_INS_NOP = 294 , M68K_INS_NOT = 295 , M68K_INS_OR = 296 , M68K_INS_ORI = 297 , M68K_INS_PACK = 298 , M68K_INS_PEA = 299 , M68K_INS_PFLUSH = 300 , M68K_INS_PFLUSHA = 301 , M68K_INS_PFLUSHAN = 302 , M68K_INS_PFLUSHN = 303 , M68K_INS_PLOADR = 304 , M68K_INS_PLOADW = 305 , M68K_INS_PLPAR = 306 , M68K_INS_PLPAW = 307 , M68K_INS_PMOVE = 308 , M68K_INS_PMOVEFD = 309 , M68K_INS_PTESTR = 310 , M68K_INS_PTESTW = 311 , M68K_INS_PULSE = 312 , M68K_INS_REMS = 313 , M68K_INS_REMU = 314 , M68K_INS_RESET = 315 , M68K_INS_ROL = 316 , M68K_INS_ROR = 317 , M68K_INS_ROXL = 318 , M68K_INS_ROXR = 319 , M68K_INS_RTD = 320 , M68K_INS_RTE = 321 , M68K_INS_RTM = 322 , M68K_INS_RTR = 323 , M68K_INS_RTS = 324 , M68K_INS_SBCD = 325 , M68K_INS_ST = 326 , M68K_INS_SF = 327 , M68K_INS_SHI = 328 , M68K_INS_SLS = 329 , M68K_INS_SCC = 330 , M68K_INS_SHS = 331 , M68K_INS_SCS = 332 , M68K_INS_SLO = 333 , M68K_INS_SNE = 334 , M68K_INS_SEQ = 335 , M68K_INS_SVC = 336 , M68K_INS_SVS = 337 , M68K_INS_SPL = 338 , M68K_INS_SMI = 339 , M68K_INS_SGE = 340 , M68K_INS_SLT = 341 , M68K_INS_SGT = 342 , M68K_INS_SLE = 343 , M68K_INS_STOP = 344 , M68K_INS_SUB = 345 , M68K_INS_SUBA = 346 , M68K_INS_SUBI = 347 , M68K_INS_SUBQ = 348 , M68K_INS_SUBX = 349 , M68K_INS_SWAP = 350 , M68K_INS_TAS = 351 , M68K_INS_TRAP = 352 , M68K_INS_TRAPV = 353 , M68K_INS_TRAPT = 354 , M68K_INS_TRAPF = 355 , M68K_INS_TRAPHI = 356 , M68K_INS_TRAPLS = 357 , M68K_INS_TRAPCC = 358 , M68K_INS_TRAPHS = 359 , M68K_INS_TRAPCS = 360 , M68K_INS_TRAPLO = 361 , M68K_INS_TRAPNE = 362 , M68K_INS_TRAPEQ = 363 , M68K_INS_TRAPVC = 364 , M68K_INS_TRAPVS = 365 , M68K_INS_TRAPPL = 366 , M68K_INS_TRAPMI = 367 , M68K_INS_TRAPGE = 368 , M68K_INS_TRAPLT = 369 , M68K_INS_TRAPGT = 370 , M68K_INS_TRAPLE = 371 , M68K_INS_TST = 372 , M68K_INS_UNLK = 373 , M68K_INS_UNPK = 374 , M68K_INS_ENDING = 375 , } # [repr (u32)] # [doc = " Group of M68K instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_group_type { # [doc = "< CS_GRUP_INVALID"] M68K_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M68K_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] M68K_GRP_RET = 3 , # [doc = "< = CS_GRP_IRET"] M68K_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M68K_GRP_BRANCH_RELATIVE = 7 , M68K_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MIPS_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MIPS_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MIPS_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MIPS_OP_MEM = 3 , } impl mips_reg { pub const MIPS_REG_ZERO : mips_reg = mips_reg :: MIPS_REG_0 ; } impl mips_reg { pub const MIPS_REG_AT : mips_reg = mips_reg :: MIPS_REG_1 ; } impl mips_reg { pub const MIPS_REG_V0 : mips_reg = mips_reg :: MIPS_REG_2 ; } impl mips_reg { pub const MIPS_REG_V1 : mips_reg = mips_reg :: MIPS_REG_3 ; } impl mips_reg { pub const MIPS_REG_A0 : mips_reg = mips_reg :: MIPS_REG_4 ; } impl mips_reg { pub const MIPS_REG_A1 : mips_reg = mips_reg :: MIPS_REG_5 ; } impl mips_reg { pub const MIPS_REG_A2 : mips_reg = mips_reg :: MIPS_REG_6 ; } impl mips_reg { pub const MIPS_REG_A3 : mips_reg = mips_reg :: MIPS_REG_7 ; } impl mips_reg { pub const MIPS_REG_T0 : mips_reg = mips_reg :: MIPS_REG_8 ; } impl mips_reg { pub const MIPS_REG_T1 : mips_reg = mips_reg :: MIPS_REG_9 ; } impl mips_reg { pub const MIPS_REG_T2 : mips_reg = mips_reg :: MIPS_REG_10 ; } impl mips_reg { pub const MIPS_REG_T3 : mips_reg = mips_reg :: MIPS_REG_11 ; } impl mips_reg { pub const MIPS_REG_T4 : mips_reg = mips_reg :: MIPS_REG_12 ; } impl mips_reg { pub const MIPS_REG_T5 : mips_reg = mips_reg :: MIPS_REG_13 ; } impl mips_reg { pub const MIPS_REG_T6 : mips_reg = mips_reg :: MIPS_REG_14 ; } impl mips_reg { pub const MIPS_REG_T7 : mips_reg = mips_reg :: MIPS_REG_15 ; } impl mips_reg { pub const MIPS_REG_S0 : mips_reg = mips_reg :: MIPS_REG_16 ; } impl mips_reg { pub const MIPS_REG_S1 : mips_reg = mips_reg :: MIPS_REG_17 ; } impl mips_reg { pub const MIPS_REG_S2 : mips_reg = mips_reg :: MIPS_REG_18 ; } impl mips_reg { pub const MIPS_REG_S3 : mips_reg = mips_reg :: MIPS_REG_19 ; } impl mips_reg { pub const MIPS_REG_S4 : mips_reg = mips_reg :: MIPS_REG_20 ; } impl mips_reg { pub const MIPS_REG_S5 : mips_reg = mips_reg :: MIPS_REG_21 ; } impl mips_reg { pub const MIPS_REG_S6 : mips_reg = mips_reg :: MIPS_REG_22 ; } impl mips_reg { pub const MIPS_REG_S7 : mips_reg = mips_reg :: MIPS_REG_23 ; } impl mips_reg { pub const MIPS_REG_T8 : mips_reg = mips_reg :: MIPS_REG_24 ; } impl mips_reg { pub const MIPS_REG_T9 : mips_reg = mips_reg :: MIPS_REG_25 ; } impl mips_reg { pub const MIPS_REG_K0 : mips_reg = mips_reg :: MIPS_REG_26 ; } impl mips_reg { pub const MIPS_REG_K1 : mips_reg = mips_reg :: MIPS_REG_27 ; } impl mips_reg { pub const MIPS_REG_GP : mips_reg = mips_reg :: MIPS_REG_28 ; } impl mips_reg { pub const MIPS_REG_SP : mips_reg = mips_reg :: MIPS_REG_29 ; } impl mips_reg { pub const MIPS_REG_FP : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_S8 : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_RA : mips_reg = mips_reg :: MIPS_REG_31 ; } impl mips_reg { pub const MIPS_REG_HI0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_HI1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_HI2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_HI3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } impl mips_reg { pub const MIPS_REG_LO0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_LO1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_LO2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_LO3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } # [repr (u32)] # [doc = " MIPS registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_reg { MIPS_REG_INVALID = 0 , MIPS_REG_PC = 1 , MIPS_REG_0 = 2 , MIPS_REG_1 = 3 , MIPS_REG_2 = 4 , MIPS_REG_3 = 5 , MIPS_REG_4 = 6 , MIPS_REG_5 = 7 , MIPS_REG_6 = 8 , MIPS_REG_7 = 9 , MIPS_REG_8 = 10 , MIPS_REG_9 = 11 , MIPS_REG_10 = 12 , MIPS_REG_11 = 13 , MIPS_REG_12 = 14 , MIPS_REG_13 = 15 , MIPS_REG_14 = 16 , MIPS_REG_15 = 17 , MIPS_REG_16 = 18 , MIPS_REG_17 = 19 , MIPS_REG_18 = 20 , MIPS_REG_19 = 21 , MIPS_REG_20 = 22 , MIPS_REG_21 = 23 , MIPS_REG_22 = 24 , MIPS_REG_23 = 25 , MIPS_REG_24 = 26 , MIPS_REG_25 = 27 , MIPS_REG_26 = 28 , MIPS_REG_27 = 29 , MIPS_REG_28 = 30 , MIPS_REG_29 = 31 , MIPS_REG_30 = 32 , MIPS_REG_31 = 33 , MIPS_REG_DSPCCOND = 34 , MIPS_REG_DSPCARRY = 35 , MIPS_REG_DSPEFI = 36 , MIPS_REG_DSPOUTFLAG = 37 , MIPS_REG_DSPOUTFLAG16_19 = 38 , MIPS_REG_DSPOUTFLAG20 = 39 , MIPS_REG_DSPOUTFLAG21 = 40 , MIPS_REG_DSPOUTFLAG22 = 41 , MIPS_REG_DSPOUTFLAG23 = 42 , MIPS_REG_DSPPOS = 43 , MIPS_REG_DSPSCOUNT = 44 , MIPS_REG_AC0 = 45 , MIPS_REG_AC1 = 46 , MIPS_REG_AC2 = 47 , MIPS_REG_AC3 = 48 , MIPS_REG_CC0 = 49 , MIPS_REG_CC1 = 50 , MIPS_REG_CC2 = 51 , MIPS_REG_CC3 = 52 , MIPS_REG_CC4 = 53 , MIPS_REG_CC5 = 54 , MIPS_REG_CC6 = 55 , MIPS_REG_CC7 = 56 , MIPS_REG_F0 = 57 , MIPS_REG_F1 = 58 , MIPS_REG_F2 = 59 , MIPS_REG_F3 = 60 , MIPS_REG_F4 = 61 , MIPS_REG_F5 = 62 , MIPS_REG_F6 = 63 , MIPS_REG_F7 = 64 , MIPS_REG_F8 = 65 , MIPS_REG_F9 = 66 , MIPS_REG_F10 = 67 , MIPS_REG_F11 = 68 , MIPS_REG_F12 = 69 , MIPS_REG_F13 = 70 , MIPS_REG_F14 = 71 , MIPS_REG_F15 = 72 , MIPS_REG_F16 = 73 , MIPS_REG_F17 = 74 , MIPS_REG_F18 = 75 , MIPS_REG_F19 = 76 , MIPS_REG_F20 = 77 , MIPS_REG_F21 = 78 , MIPS_REG_F22 = 79 , MIPS_REG_F23 = 80 , MIPS_REG_F24 = 81 , MIPS_REG_F25 = 82 , MIPS_REG_F26 = 83 , MIPS_REG_F27 = 84 , MIPS_REG_F28 = 85 , MIPS_REG_F29 = 86 , MIPS_REG_F30 = 87 , MIPS_REG_F31 = 88 , MIPS_REG_FCC0 = 89 , MIPS_REG_FCC1 = 90 , MIPS_REG_FCC2 = 91 , MIPS_REG_FCC3 = 92 , MIPS_REG_FCC4 = 93 , MIPS_REG_FCC5 = 94 , MIPS_REG_FCC6 = 95 , MIPS_REG_FCC7 = 96 , MIPS_REG_W0 = 97 , MIPS_REG_W1 = 98 , MIPS_REG_W2 = 99 , MIPS_REG_W3 = 100 , MIPS_REG_W4 = 101 , MIPS_REG_W5 = 102 , MIPS_REG_W6 = 103 , MIPS_REG_W7 = 104 , MIPS_REG_W8 = 105 , MIPS_REG_W9 = 106 , MIPS_REG_W10 = 107 , MIPS_REG_W11 = 108 , MIPS_REG_W12 = 109 , MIPS_REG_W13 = 110 , MIPS_REG_W14 = 111 , MIPS_REG_W15 = 112 , MIPS_REG_W16 = 113 , MIPS_REG_W17 = 114 , MIPS_REG_W18 = 115 , MIPS_REG_W19 = 116 , MIPS_REG_W20 = 117 , MIPS_REG_W21 = 118 , MIPS_REG_W22 = 119 , MIPS_REG_W23 = 120 , MIPS_REG_W24 = 121 , MIPS_REG_W25 = 122 , MIPS_REG_W26 = 123 , MIPS_REG_W27 = 124 , MIPS_REG_W28 = 125 , MIPS_REG_W29 = 126 , MIPS_REG_W30 = 127 , MIPS_REG_W31 = 128 , MIPS_REG_HI = 129 , MIPS_REG_LO = 130 , MIPS_REG_P0 = 131 , MIPS_REG_P1 = 132 , MIPS_REG_P2 = 133 , MIPS_REG_MPL0 = 134 , MIPS_REG_MPL1 = 135 , MIPS_REG_MPL2 = 136 , MIPS_REG_ENDING = 137 , } # [doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct mips_op_mem { # [doc = "< base register"] pub base : mips_reg , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of mips_op_mem"] [:: std :: mem :: size_of :: < mips_op_mem > () - 16usize] ; ["Alignment of mips_op_mem"] [:: std :: mem :: align_of :: < mips_op_mem > () - 8usize] ; ["Offset of field: mips_op_mem::base"] [:: std :: mem :: offset_of ! (mips_op_mem , base) - 0usize] ; ["Offset of field: mips_op_mem::disp"] [:: std :: mem :: offset_of ! (mips_op_mem , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips_op { # [doc = "< operand type"] pub type_ : mips_op_type , pub __bindgen_anon_1 : cs_mips_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mips_op__bindgen_ty_1 { # [doc = "< register id for REG operand"] pub reg : mips_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : mips_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mips_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mips_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op"] [:: std :: mem :: size_of :: < cs_mips_op > () - 24usize] ; ["Alignment of cs_mips_op"] [:: std :: mem :: align_of :: < cs_mips_op > () - 8usize] ; ["Offset of field: cs_mips_op::type_"] [:: std :: mem :: offset_of ! (cs_mips_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mips_op ; 10usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips"] [:: std :: mem :: size_of :: < cs_mips > () - 248usize] ; ["Alignment of cs_mips"] [:: std :: mem :: align_of :: < cs_mips > () - 8usize] ; ["Offset of field: cs_mips::op_count"] [:: std :: mem :: offset_of ! (cs_mips , op_count) - 0usize] ; ["Offset of field: cs_mips::operands"] [:: std :: mem :: offset_of ! (cs_mips , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mips { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " MIPS instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn { MIPS_INS_INVALID = 0 , MIPS_INS_ABSQ_S = 1 , MIPS_INS_ADD = 2 , MIPS_INS_ADDIUPC = 3 , MIPS_INS_ADDIUR1SP = 4 , MIPS_INS_ADDIUR2 = 5 , MIPS_INS_ADDIUS5 = 6 , MIPS_INS_ADDIUSP = 7 , MIPS_INS_ADDQH = 8 , MIPS_INS_ADDQH_R = 9 , MIPS_INS_ADDQ = 10 , MIPS_INS_ADDQ_S = 11 , MIPS_INS_ADDSC = 12 , MIPS_INS_ADDS_A = 13 , MIPS_INS_ADDS_S = 14 , MIPS_INS_ADDS_U = 15 , MIPS_INS_ADDU16 = 16 , MIPS_INS_ADDUH = 17 , MIPS_INS_ADDUH_R = 18 , MIPS_INS_ADDU = 19 , MIPS_INS_ADDU_S = 20 , MIPS_INS_ADDVI = 21 , MIPS_INS_ADDV = 22 , MIPS_INS_ADDWC = 23 , MIPS_INS_ADD_A = 24 , MIPS_INS_ADDI = 25 , MIPS_INS_ADDIU = 26 , MIPS_INS_ALIGN = 27 , MIPS_INS_ALUIPC = 28 , MIPS_INS_AND = 29 , MIPS_INS_AND16 = 30 , MIPS_INS_ANDI16 = 31 , MIPS_INS_ANDI = 32 , MIPS_INS_APPEND = 33 , MIPS_INS_ASUB_S = 34 , MIPS_INS_ASUB_U = 35 , MIPS_INS_AUI = 36 , MIPS_INS_AUIPC = 37 , MIPS_INS_AVER_S = 38 , MIPS_INS_AVER_U = 39 , MIPS_INS_AVE_S = 40 , MIPS_INS_AVE_U = 41 , MIPS_INS_B16 = 42 , MIPS_INS_BADDU = 43 , MIPS_INS_BAL = 44 , MIPS_INS_BALC = 45 , MIPS_INS_BALIGN = 46 , MIPS_INS_BBIT0 = 47 , MIPS_INS_BBIT032 = 48 , MIPS_INS_BBIT1 = 49 , MIPS_INS_BBIT132 = 50 , MIPS_INS_BC = 51 , MIPS_INS_BC0F = 52 , MIPS_INS_BC0FL = 53 , MIPS_INS_BC0T = 54 , MIPS_INS_BC0TL = 55 , MIPS_INS_BC1EQZ = 56 , MIPS_INS_BC1F = 57 , MIPS_INS_BC1FL = 58 , MIPS_INS_BC1NEZ = 59 , MIPS_INS_BC1T = 60 , MIPS_INS_BC1TL = 61 , MIPS_INS_BC2EQZ = 62 , MIPS_INS_BC2F = 63 , MIPS_INS_BC2FL = 64 , MIPS_INS_BC2NEZ = 65 , MIPS_INS_BC2T = 66 , MIPS_INS_BC2TL = 67 , MIPS_INS_BC3F = 68 , MIPS_INS_BC3FL = 69 , MIPS_INS_BC3T = 70 , MIPS_INS_BC3TL = 71 , MIPS_INS_BCLRI = 72 , MIPS_INS_BCLR = 73 , MIPS_INS_BEQ = 74 , MIPS_INS_BEQC = 75 , MIPS_INS_BEQL = 76 , MIPS_INS_BEQZ16 = 77 , MIPS_INS_BEQZALC = 78 , MIPS_INS_BEQZC = 79 , MIPS_INS_BGEC = 80 , MIPS_INS_BGEUC = 81 , MIPS_INS_BGEZ = 82 , MIPS_INS_BGEZAL = 83 , MIPS_INS_BGEZALC = 84 , MIPS_INS_BGEZALL = 85 , MIPS_INS_BGEZALS = 86 , MIPS_INS_BGEZC = 87 , MIPS_INS_BGEZL = 88 , MIPS_INS_BGTZ = 89 , MIPS_INS_BGTZALC = 90 , MIPS_INS_BGTZC = 91 , MIPS_INS_BGTZL = 92 , MIPS_INS_BINSLI = 93 , MIPS_INS_BINSL = 94 , MIPS_INS_BINSRI = 95 , MIPS_INS_BINSR = 96 , MIPS_INS_BITREV = 97 , MIPS_INS_BITSWAP = 98 , MIPS_INS_BLEZ = 99 , MIPS_INS_BLEZALC = 100 , MIPS_INS_BLEZC = 101 , MIPS_INS_BLEZL = 102 , MIPS_INS_BLTC = 103 , MIPS_INS_BLTUC = 104 , MIPS_INS_BLTZ = 105 , MIPS_INS_BLTZAL = 106 , MIPS_INS_BLTZALC = 107 , MIPS_INS_BLTZALL = 108 , MIPS_INS_BLTZALS = 109 , MIPS_INS_BLTZC = 110 , MIPS_INS_BLTZL = 111 , MIPS_INS_BMNZI = 112 , MIPS_INS_BMNZ = 113 , MIPS_INS_BMZI = 114 , MIPS_INS_BMZ = 115 , MIPS_INS_BNE = 116 , MIPS_INS_BNEC = 117 , MIPS_INS_BNEGI = 118 , MIPS_INS_BNEG = 119 , MIPS_INS_BNEL = 120 , MIPS_INS_BNEZ16 = 121 , MIPS_INS_BNEZALC = 122 , MIPS_INS_BNEZC = 123 , MIPS_INS_BNVC = 124 , MIPS_INS_BNZ = 125 , MIPS_INS_BOVC = 126 , MIPS_INS_BPOSGE32 = 127 , MIPS_INS_BREAK = 128 , MIPS_INS_BREAK16 = 129 , MIPS_INS_BSELI = 130 , MIPS_INS_BSEL = 131 , MIPS_INS_BSETI = 132 , MIPS_INS_BSET = 133 , MIPS_INS_BZ = 134 , MIPS_INS_BEQZ = 135 , MIPS_INS_B = 136 , MIPS_INS_BNEZ = 137 , MIPS_INS_BTEQZ = 138 , MIPS_INS_BTNEZ = 139 , MIPS_INS_CACHE = 140 , MIPS_INS_CEIL = 141 , MIPS_INS_CEQI = 142 , MIPS_INS_CEQ = 143 , MIPS_INS_CFC1 = 144 , MIPS_INS_CFCMSA = 145 , MIPS_INS_CINS = 146 , MIPS_INS_CINS32 = 147 , MIPS_INS_CLASS = 148 , MIPS_INS_CLEI_S = 149 , MIPS_INS_CLEI_U = 150 , MIPS_INS_CLE_S = 151 , MIPS_INS_CLE_U = 152 , MIPS_INS_CLO = 153 , MIPS_INS_CLTI_S = 154 , MIPS_INS_CLTI_U = 155 , MIPS_INS_CLT_S = 156 , MIPS_INS_CLT_U = 157 , MIPS_INS_CLZ = 158 , MIPS_INS_CMPGDU = 159 , MIPS_INS_CMPGU = 160 , MIPS_INS_CMPU = 161 , MIPS_INS_CMP = 162 , MIPS_INS_COPY_S = 163 , MIPS_INS_COPY_U = 164 , MIPS_INS_CTC1 = 165 , MIPS_INS_CTCMSA = 166 , MIPS_INS_CVT = 167 , MIPS_INS_C = 168 , MIPS_INS_CMPI = 169 , MIPS_INS_DADD = 170 , MIPS_INS_DADDI = 171 , MIPS_INS_DADDIU = 172 , MIPS_INS_DADDU = 173 , MIPS_INS_DAHI = 174 , MIPS_INS_DALIGN = 175 , MIPS_INS_DATI = 176 , MIPS_INS_DAUI = 177 , MIPS_INS_DBITSWAP = 178 , MIPS_INS_DCLO = 179 , MIPS_INS_DCLZ = 180 , MIPS_INS_DDIV = 181 , MIPS_INS_DDIVU = 182 , MIPS_INS_DERET = 183 , MIPS_INS_DEXT = 184 , MIPS_INS_DEXTM = 185 , MIPS_INS_DEXTU = 186 , MIPS_INS_DI = 187 , MIPS_INS_DINS = 188 , MIPS_INS_DINSM = 189 , MIPS_INS_DINSU = 190 , MIPS_INS_DIV = 191 , MIPS_INS_DIVU = 192 , MIPS_INS_DIV_S = 193 , MIPS_INS_DIV_U = 194 , MIPS_INS_DLSA = 195 , MIPS_INS_DMFC0 = 196 , MIPS_INS_DMFC1 = 197 , MIPS_INS_DMFC2 = 198 , MIPS_INS_DMOD = 199 , MIPS_INS_DMODU = 200 , MIPS_INS_DMTC0 = 201 , MIPS_INS_DMTC1 = 202 , MIPS_INS_DMTC2 = 203 , MIPS_INS_DMUH = 204 , MIPS_INS_DMUHU = 205 , MIPS_INS_DMUL = 206 , MIPS_INS_DMULT = 207 , MIPS_INS_DMULTU = 208 , MIPS_INS_DMULU = 209 , MIPS_INS_DOTP_S = 210 , MIPS_INS_DOTP_U = 211 , MIPS_INS_DPADD_S = 212 , MIPS_INS_DPADD_U = 213 , MIPS_INS_DPAQX_SA = 214 , MIPS_INS_DPAQX_S = 215 , MIPS_INS_DPAQ_SA = 216 , MIPS_INS_DPAQ_S = 217 , MIPS_INS_DPAU = 218 , MIPS_INS_DPAX = 219 , MIPS_INS_DPA = 220 , MIPS_INS_DPOP = 221 , MIPS_INS_DPSQX_SA = 222 , MIPS_INS_DPSQX_S = 223 , MIPS_INS_DPSQ_SA = 224 , MIPS_INS_DPSQ_S = 225 , MIPS_INS_DPSUB_S = 226 , MIPS_INS_DPSUB_U = 227 , MIPS_INS_DPSU = 228 , MIPS_INS_DPSX = 229 , MIPS_INS_DPS = 230 , MIPS_INS_DROTR = 231 , MIPS_INS_DROTR32 = 232 , MIPS_INS_DROTRV = 233 , MIPS_INS_DSBH = 234 , MIPS_INS_DSHD = 235 , MIPS_INS_DSLL = 236 , MIPS_INS_DSLL32 = 237 , MIPS_INS_DSLLV = 238 , MIPS_INS_DSRA = 239 , MIPS_INS_DSRA32 = 240 , MIPS_INS_DSRAV = 241 , MIPS_INS_DSRL = 242 , MIPS_INS_DSRL32 = 243 , MIPS_INS_DSRLV = 244 , MIPS_INS_DSUB = 245 , MIPS_INS_DSUBU = 246 , MIPS_INS_EHB = 247 , MIPS_INS_EI = 248 , MIPS_INS_ERET = 249 , MIPS_INS_EXT = 250 , MIPS_INS_EXTP = 251 , MIPS_INS_EXTPDP = 252 , MIPS_INS_EXTPDPV = 253 , MIPS_INS_EXTPV = 254 , MIPS_INS_EXTRV_RS = 255 , MIPS_INS_EXTRV_R = 256 , MIPS_INS_EXTRV_S = 257 , MIPS_INS_EXTRV = 258 , MIPS_INS_EXTR_RS = 259 , MIPS_INS_EXTR_R = 260 , MIPS_INS_EXTR_S = 261 , MIPS_INS_EXTR = 262 , MIPS_INS_EXTS = 263 , MIPS_INS_EXTS32 = 264 , MIPS_INS_ABS = 265 , MIPS_INS_FADD = 266 , MIPS_INS_FCAF = 267 , MIPS_INS_FCEQ = 268 , MIPS_INS_FCLASS = 269 , MIPS_INS_FCLE = 270 , MIPS_INS_FCLT = 271 , MIPS_INS_FCNE = 272 , MIPS_INS_FCOR = 273 , MIPS_INS_FCUEQ = 274 , MIPS_INS_FCULE = 275 , MIPS_INS_FCULT = 276 , MIPS_INS_FCUNE = 277 , MIPS_INS_FCUN = 278 , MIPS_INS_FDIV = 279 , MIPS_INS_FEXDO = 280 , MIPS_INS_FEXP2 = 281 , MIPS_INS_FEXUPL = 282 , MIPS_INS_FEXUPR = 283 , MIPS_INS_FFINT_S = 284 , MIPS_INS_FFINT_U = 285 , MIPS_INS_FFQL = 286 , MIPS_INS_FFQR = 287 , MIPS_INS_FILL = 288 , MIPS_INS_FLOG2 = 289 , MIPS_INS_FLOOR = 290 , MIPS_INS_FMADD = 291 , MIPS_INS_FMAX_A = 292 , MIPS_INS_FMAX = 293 , MIPS_INS_FMIN_A = 294 , MIPS_INS_FMIN = 295 , MIPS_INS_MOV = 296 , MIPS_INS_FMSUB = 297 , MIPS_INS_FMUL = 298 , MIPS_INS_MUL = 299 , MIPS_INS_NEG = 300 , MIPS_INS_FRCP = 301 , MIPS_INS_FRINT = 302 , MIPS_INS_FRSQRT = 303 , MIPS_INS_FSAF = 304 , MIPS_INS_FSEQ = 305 , MIPS_INS_FSLE = 306 , MIPS_INS_FSLT = 307 , MIPS_INS_FSNE = 308 , MIPS_INS_FSOR = 309 , MIPS_INS_FSQRT = 310 , MIPS_INS_SQRT = 311 , MIPS_INS_FSUB = 312 , MIPS_INS_SUB = 313 , MIPS_INS_FSUEQ = 314 , MIPS_INS_FSULE = 315 , MIPS_INS_FSULT = 316 , MIPS_INS_FSUNE = 317 , MIPS_INS_FSUN = 318 , MIPS_INS_FTINT_S = 319 , MIPS_INS_FTINT_U = 320 , MIPS_INS_FTQ = 321 , MIPS_INS_FTRUNC_S = 322 , MIPS_INS_FTRUNC_U = 323 , MIPS_INS_HADD_S = 324 , MIPS_INS_HADD_U = 325 , MIPS_INS_HSUB_S = 326 , MIPS_INS_HSUB_U = 327 , MIPS_INS_ILVEV = 328 , MIPS_INS_ILVL = 329 , MIPS_INS_ILVOD = 330 , MIPS_INS_ILVR = 331 , MIPS_INS_INS = 332 , MIPS_INS_INSERT = 333 , MIPS_INS_INSV = 334 , MIPS_INS_INSVE = 335 , MIPS_INS_J = 336 , MIPS_INS_JAL = 337 , MIPS_INS_JALR = 338 , MIPS_INS_JALRS16 = 339 , MIPS_INS_JALRS = 340 , MIPS_INS_JALS = 341 , MIPS_INS_JALX = 342 , MIPS_INS_JIALC = 343 , MIPS_INS_JIC = 344 , MIPS_INS_JR = 345 , MIPS_INS_JR16 = 346 , MIPS_INS_JRADDIUSP = 347 , MIPS_INS_JRC = 348 , MIPS_INS_JALRC = 349 , MIPS_INS_LB = 350 , MIPS_INS_LBU16 = 351 , MIPS_INS_LBUX = 352 , MIPS_INS_LBU = 353 , MIPS_INS_LD = 354 , MIPS_INS_LDC1 = 355 , MIPS_INS_LDC2 = 356 , MIPS_INS_LDC3 = 357 , MIPS_INS_LDI = 358 , MIPS_INS_LDL = 359 , MIPS_INS_LDPC = 360 , MIPS_INS_LDR = 361 , MIPS_INS_LDXC1 = 362 , MIPS_INS_LH = 363 , MIPS_INS_LHU16 = 364 , MIPS_INS_LHX = 365 , MIPS_INS_LHU = 366 , MIPS_INS_LI16 = 367 , MIPS_INS_LL = 368 , MIPS_INS_LLD = 369 , MIPS_INS_LSA = 370 , MIPS_INS_LUXC1 = 371 , MIPS_INS_LUI = 372 , MIPS_INS_LW = 373 , MIPS_INS_LW16 = 374 , MIPS_INS_LWC1 = 375 , MIPS_INS_LWC2 = 376 , MIPS_INS_LWC3 = 377 , MIPS_INS_LWL = 378 , MIPS_INS_LWM16 = 379 , MIPS_INS_LWM32 = 380 , MIPS_INS_LWPC = 381 , MIPS_INS_LWP = 382 , MIPS_INS_LWR = 383 , MIPS_INS_LWUPC = 384 , MIPS_INS_LWU = 385 , MIPS_INS_LWX = 386 , MIPS_INS_LWXC1 = 387 , MIPS_INS_LWXS = 388 , MIPS_INS_LI = 389 , MIPS_INS_MADD = 390 , MIPS_INS_MADDF = 391 , MIPS_INS_MADDR_Q = 392 , MIPS_INS_MADDU = 393 , MIPS_INS_MADDV = 394 , MIPS_INS_MADD_Q = 395 , MIPS_INS_MAQ_SA = 396 , MIPS_INS_MAQ_S = 397 , MIPS_INS_MAXA = 398 , MIPS_INS_MAXI_S = 399 , MIPS_INS_MAXI_U = 400 , MIPS_INS_MAX_A = 401 , MIPS_INS_MAX = 402 , MIPS_INS_MAX_S = 403 , MIPS_INS_MAX_U = 404 , MIPS_INS_MFC0 = 405 , MIPS_INS_MFC1 = 406 , MIPS_INS_MFC2 = 407 , MIPS_INS_MFHC1 = 408 , MIPS_INS_MFHI = 409 , MIPS_INS_MFLO = 410 , MIPS_INS_MINA = 411 , MIPS_INS_MINI_S = 412 , MIPS_INS_MINI_U = 413 , MIPS_INS_MIN_A = 414 , MIPS_INS_MIN = 415 , MIPS_INS_MIN_S = 416 , MIPS_INS_MIN_U = 417 , MIPS_INS_MOD = 418 , MIPS_INS_MODSUB = 419 , MIPS_INS_MODU = 420 , MIPS_INS_MOD_S = 421 , MIPS_INS_MOD_U = 422 , MIPS_INS_MOVE = 423 , MIPS_INS_MOVEP = 424 , MIPS_INS_MOVF = 425 , MIPS_INS_MOVN = 426 , MIPS_INS_MOVT = 427 , MIPS_INS_MOVZ = 428 , MIPS_INS_MSUB = 429 , MIPS_INS_MSUBF = 430 , MIPS_INS_MSUBR_Q = 431 , MIPS_INS_MSUBU = 432 , MIPS_INS_MSUBV = 433 , MIPS_INS_MSUB_Q = 434 , MIPS_INS_MTC0 = 435 , MIPS_INS_MTC1 = 436 , MIPS_INS_MTC2 = 437 , MIPS_INS_MTHC1 = 438 , MIPS_INS_MTHI = 439 , MIPS_INS_MTHLIP = 440 , MIPS_INS_MTLO = 441 , MIPS_INS_MTM0 = 442 , MIPS_INS_MTM1 = 443 , MIPS_INS_MTM2 = 444 , MIPS_INS_MTP0 = 445 , MIPS_INS_MTP1 = 446 , MIPS_INS_MTP2 = 447 , MIPS_INS_MUH = 448 , MIPS_INS_MUHU = 449 , MIPS_INS_MULEQ_S = 450 , MIPS_INS_MULEU_S = 451 , MIPS_INS_MULQ_RS = 452 , MIPS_INS_MULQ_S = 453 , MIPS_INS_MULR_Q = 454 , MIPS_INS_MULSAQ_S = 455 , MIPS_INS_MULSA = 456 , MIPS_INS_MULT = 457 , MIPS_INS_MULTU = 458 , MIPS_INS_MULU = 459 , MIPS_INS_MULV = 460 , MIPS_INS_MUL_Q = 461 , MIPS_INS_MUL_S = 462 , MIPS_INS_NLOC = 463 , MIPS_INS_NLZC = 464 , MIPS_INS_NMADD = 465 , MIPS_INS_NMSUB = 466 , MIPS_INS_NOR = 467 , MIPS_INS_NORI = 468 , MIPS_INS_NOT16 = 469 , MIPS_INS_NOT = 470 , MIPS_INS_OR = 471 , MIPS_INS_OR16 = 472 , MIPS_INS_ORI = 473 , MIPS_INS_PACKRL = 474 , MIPS_INS_PAUSE = 475 , MIPS_INS_PCKEV = 476 , MIPS_INS_PCKOD = 477 , MIPS_INS_PCNT = 478 , MIPS_INS_PICK = 479 , MIPS_INS_POP = 480 , MIPS_INS_PRECEQU = 481 , MIPS_INS_PRECEQ = 482 , MIPS_INS_PRECEU = 483 , MIPS_INS_PRECRQU_S = 484 , MIPS_INS_PRECRQ = 485 , MIPS_INS_PRECRQ_RS = 486 , MIPS_INS_PRECR = 487 , MIPS_INS_PRECR_SRA = 488 , MIPS_INS_PRECR_SRA_R = 489 , MIPS_INS_PREF = 490 , MIPS_INS_PREPEND = 491 , MIPS_INS_RADDU = 492 , MIPS_INS_RDDSP = 493 , MIPS_INS_RDHWR = 494 , MIPS_INS_REPLV = 495 , MIPS_INS_REPL = 496 , MIPS_INS_RINT = 497 , MIPS_INS_ROTR = 498 , MIPS_INS_ROTRV = 499 , MIPS_INS_ROUND = 500 , MIPS_INS_SAT_S = 501 , MIPS_INS_SAT_U = 502 , MIPS_INS_SB = 503 , MIPS_INS_SB16 = 504 , MIPS_INS_SC = 505 , MIPS_INS_SCD = 506 , MIPS_INS_SD = 507 , MIPS_INS_SDBBP = 508 , MIPS_INS_SDBBP16 = 509 , MIPS_INS_SDC1 = 510 , MIPS_INS_SDC2 = 511 , MIPS_INS_SDC3 = 512 , MIPS_INS_SDL = 513 , MIPS_INS_SDR = 514 , MIPS_INS_SDXC1 = 515 , MIPS_INS_SEB = 516 , MIPS_INS_SEH = 517 , MIPS_INS_SELEQZ = 518 , MIPS_INS_SELNEZ = 519 , MIPS_INS_SEL = 520 , MIPS_INS_SEQ = 521 , MIPS_INS_SEQI = 522 , MIPS_INS_SH = 523 , MIPS_INS_SH16 = 524 , MIPS_INS_SHF = 525 , MIPS_INS_SHILO = 526 , MIPS_INS_SHILOV = 527 , MIPS_INS_SHLLV = 528 , MIPS_INS_SHLLV_S = 529 , MIPS_INS_SHLL = 530 , MIPS_INS_SHLL_S = 531 , MIPS_INS_SHRAV = 532 , MIPS_INS_SHRAV_R = 533 , MIPS_INS_SHRA = 534 , MIPS_INS_SHRA_R = 535 , MIPS_INS_SHRLV = 536 , MIPS_INS_SHRL = 537 , MIPS_INS_SLDI = 538 , MIPS_INS_SLD = 539 , MIPS_INS_SLL = 540 , MIPS_INS_SLL16 = 541 , MIPS_INS_SLLI = 542 , MIPS_INS_SLLV = 543 , MIPS_INS_SLT = 544 , MIPS_INS_SLTI = 545 , MIPS_INS_SLTIU = 546 , MIPS_INS_SLTU = 547 , MIPS_INS_SNE = 548 , MIPS_INS_SNEI = 549 , MIPS_INS_SPLATI = 550 , MIPS_INS_SPLAT = 551 , MIPS_INS_SRA = 552 , MIPS_INS_SRAI = 553 , MIPS_INS_SRARI = 554 , MIPS_INS_SRAR = 555 , MIPS_INS_SRAV = 556 , MIPS_INS_SRL = 557 , MIPS_INS_SRL16 = 558 , MIPS_INS_SRLI = 559 , MIPS_INS_SRLRI = 560 , MIPS_INS_SRLR = 561 , MIPS_INS_SRLV = 562 , MIPS_INS_SSNOP = 563 , MIPS_INS_ST = 564 , MIPS_INS_SUBQH = 565 , MIPS_INS_SUBQH_R = 566 , MIPS_INS_SUBQ = 567 , MIPS_INS_SUBQ_S = 568 , MIPS_INS_SUBSUS_U = 569 , MIPS_INS_SUBSUU_S = 570 , MIPS_INS_SUBS_S = 571 , MIPS_INS_SUBS_U = 572 , MIPS_INS_SUBU16 = 573 , MIPS_INS_SUBUH = 574 , MIPS_INS_SUBUH_R = 575 , MIPS_INS_SUBU = 576 , MIPS_INS_SUBU_S = 577 , MIPS_INS_SUBVI = 578 , MIPS_INS_SUBV = 579 , MIPS_INS_SUXC1 = 580 , MIPS_INS_SW = 581 , MIPS_INS_SW16 = 582 , MIPS_INS_SWC1 = 583 , MIPS_INS_SWC2 = 584 , MIPS_INS_SWC3 = 585 , MIPS_INS_SWL = 586 , MIPS_INS_SWM16 = 587 , MIPS_INS_SWM32 = 588 , MIPS_INS_SWP = 589 , MIPS_INS_SWR = 590 , MIPS_INS_SWXC1 = 591 , MIPS_INS_SYNC = 592 , MIPS_INS_SYNCI = 593 , MIPS_INS_SYSCALL = 594 , MIPS_INS_TEQ = 595 , MIPS_INS_TEQI = 596 , MIPS_INS_TGE = 597 , MIPS_INS_TGEI = 598 , MIPS_INS_TGEIU = 599 , MIPS_INS_TGEU = 600 , MIPS_INS_TLBP = 601 , MIPS_INS_TLBR = 602 , MIPS_INS_TLBWI = 603 , MIPS_INS_TLBWR = 604 , MIPS_INS_TLT = 605 , MIPS_INS_TLTI = 606 , MIPS_INS_TLTIU = 607 , MIPS_INS_TLTU = 608 , MIPS_INS_TNE = 609 , MIPS_INS_TNEI = 610 , MIPS_INS_TRUNC = 611 , MIPS_INS_V3MULU = 612 , MIPS_INS_VMM0 = 613 , MIPS_INS_VMULU = 614 , MIPS_INS_VSHF = 615 , MIPS_INS_WAIT = 616 , MIPS_INS_WRDSP = 617 , MIPS_INS_WSBH = 618 , MIPS_INS_XOR = 619 , MIPS_INS_XOR16 = 620 , MIPS_INS_XORI = 621 , MIPS_INS_NOP = 622 , MIPS_INS_NEGU = 623 , MIPS_INS_JALR_HB = 624 , MIPS_INS_JR_HB = 625 , MIPS_INS_ENDING = 626 , } # [repr (u32)] # [doc = " Group of MIPS instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn_group { # [doc = "< = CS_GRP_INVALID"] MIPS_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MIPS_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] MIPS_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MIPS_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MIPS_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MIPS_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] MIPS_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MIPS_GRP_BRANCH_RELATIVE = 7 , MIPS_GRP_BITCOUNT = 128 , MIPS_GRP_DSP = 129 , MIPS_GRP_DSPR2 = 130 , MIPS_GRP_FPIDX = 131 , MIPS_GRP_MSA = 132 , MIPS_GRP_MIPS32R2 = 133 , MIPS_GRP_MIPS64 = 134 , MIPS_GRP_MIPS64R2 = 135 , MIPS_GRP_SEINREG = 136 , MIPS_GRP_STDENC = 137 , MIPS_GRP_SWAP = 138 , MIPS_GRP_MICROMIPS = 139 , MIPS_GRP_MIPS16MODE = 140 , MIPS_GRP_FP64BIT = 141 , MIPS_GRP_NONANSFPMATH = 142 , MIPS_GRP_NOTFP64BIT = 143 , MIPS_GRP_NOTINMICROMIPS = 144 , MIPS_GRP_NOTNACL = 145 , MIPS_GRP_NOTMIPS32R6 = 146 , MIPS_GRP_NOTMIPS64R6 = 147 , MIPS_GRP_CNMIPS = 148 , MIPS_GRP_MIPS32 = 149 , MIPS_GRP_MIPS32R6 = 150 , MIPS_GRP_MIPS64R6 = 151 , MIPS_GRP_MIPS2 = 152 , MIPS_GRP_MIPS3 = 153 , MIPS_GRP_MIPS3_32 = 154 , MIPS_GRP_MIPS3_32R2 = 155 , MIPS_GRP_MIPS4_32 = 156 , MIPS_GRP_MIPS4_32R2 = 157 , MIPS_GRP_MIPS5_32R2 = 158 , MIPS_GRP_GP32BIT = 159 , MIPS_GRP_GP64BIT = 160 , MIPS_GRP_ENDING = 161 , } # [repr (u32)] # [doc = " PPC branch codes for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bc { PPC_BC_INVALID = 0 , PPC_BC_LT = 12 , PPC_BC_LE = 36 , PPC_BC_EQ = 76 , PPC_BC_GE = 4 , PPC_BC_GT = 44 , PPC_BC_NE = 68 , PPC_BC_UN = 108 , PPC_BC_NU = 100 , # [doc = "< summary overflow"] PPC_BC_SO = 140 , # [doc = "< not summary overflow"] PPC_BC_NS = 132 , } # [repr (u32)] # [doc = " PPC branch hint for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bh { # [doc = "< no hint"] PPC_BH_INVALID = 0 , # [doc = "< PLUS hint"] PPC_BH_PLUS = 1 , # [doc = "< MINUS hint"] PPC_BH_MINUS = 2 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] PPC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] PPC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] PPC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] PPC_OP_MEM = 3 , # [doc = "< Condition Register field"] PPC_OP_CRX = 64 , } # [repr (u32)] # [doc = " PPC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_reg { PPC_REG_INVALID = 0 , PPC_REG_CARRY = 2 , PPC_REG_CTR = 3 , PPC_REG_LR = 5 , PPC_REG_RM = 6 , PPC_REG_VRSAVE = 8 , PPC_REG_XER = 9 , PPC_REG_ZERO = 10 , PPC_REG_CR0 = 12 , PPC_REG_CR1 = 13 , PPC_REG_CR2 = 14 , PPC_REG_CR3 = 15 , PPC_REG_CR4 = 16 , PPC_REG_CR5 = 17 , PPC_REG_CR6 = 18 , PPC_REG_CR7 = 19 , PPC_REG_CTR8 = 20 , PPC_REG_F0 = 21 , PPC_REG_F1 = 22 , PPC_REG_F2 = 23 , PPC_REG_F3 = 24 , PPC_REG_F4 = 25 , PPC_REG_F5 = 26 , PPC_REG_F6 = 27 , PPC_REG_F7 = 28 , PPC_REG_F8 = 29 , PPC_REG_F9 = 30 , PPC_REG_F10 = 31 , PPC_REG_F11 = 32 , PPC_REG_F12 = 33 , PPC_REG_F13 = 34 , PPC_REG_F14 = 35 , PPC_REG_F15 = 36 , PPC_REG_F16 = 37 , PPC_REG_F17 = 38 , PPC_REG_F18 = 39 , PPC_REG_F19 = 40 , PPC_REG_F20 = 41 , PPC_REG_F21 = 42 , PPC_REG_F22 = 43 , PPC_REG_F23 = 44 , PPC_REG_F24 = 45 , PPC_REG_F25 = 46 , PPC_REG_F26 = 47 , PPC_REG_F27 = 48 , PPC_REG_F28 = 49 , PPC_REG_F29 = 50 , PPC_REG_F30 = 51 , PPC_REG_F31 = 52 , PPC_REG_LR8 = 54 , PPC_REG_Q0 = 55 , PPC_REG_Q1 = 56 , PPC_REG_Q2 = 57 , PPC_REG_Q3 = 58 , PPC_REG_Q4 = 59 , PPC_REG_Q5 = 60 , PPC_REG_Q6 = 61 , PPC_REG_Q7 = 62 , PPC_REG_Q8 = 63 , PPC_REG_Q9 = 64 , PPC_REG_Q10 = 65 , PPC_REG_Q11 = 66 , PPC_REG_Q12 = 67 , PPC_REG_Q13 = 68 , PPC_REG_Q14 = 69 , PPC_REG_Q15 = 70 , PPC_REG_Q16 = 71 , PPC_REG_Q17 = 72 , PPC_REG_Q18 = 73 , PPC_REG_Q19 = 74 , PPC_REG_Q20 = 75 , PPC_REG_Q21 = 76 , PPC_REG_Q22 = 77 , PPC_REG_Q23 = 78 , PPC_REG_Q24 = 79 , PPC_REG_Q25 = 80 , PPC_REG_Q26 = 81 , PPC_REG_Q27 = 82 , PPC_REG_Q28 = 83 , PPC_REG_Q29 = 84 , PPC_REG_Q30 = 85 , PPC_REG_Q31 = 86 , PPC_REG_R0 = 87 , PPC_REG_R1 = 88 , PPC_REG_R2 = 89 , PPC_REG_R3 = 90 , PPC_REG_R4 = 91 , PPC_REG_R5 = 92 , PPC_REG_R6 = 93 , PPC_REG_R7 = 94 , PPC_REG_R8 = 95 , PPC_REG_R9 = 96 , PPC_REG_R10 = 97 , PPC_REG_R11 = 98 , PPC_REG_R12 = 99 , PPC_REG_R13 = 100 , PPC_REG_R14 = 101 , PPC_REG_R15 = 102 , PPC_REG_R16 = 103 , PPC_REG_R17 = 104 , PPC_REG_R18 = 105 , PPC_REG_R19 = 106 , PPC_REG_R20 = 107 , PPC_REG_R21 = 108 , PPC_REG_R22 = 109 , PPC_REG_R23 = 110 , PPC_REG_R24 = 111 , PPC_REG_R25 = 112 , PPC_REG_R26 = 113 , PPC_REG_R27 = 114 , PPC_REG_R28 = 115 , PPC_REG_R29 = 116 , PPC_REG_R30 = 117 , PPC_REG_R31 = 118 , PPC_REG_V0 = 151 , PPC_REG_V1 = 152 , PPC_REG_V2 = 153 , PPC_REG_V3 = 154 , PPC_REG_V4 = 155 , PPC_REG_V5 = 156 , PPC_REG_V6 = 157 , PPC_REG_V7 = 158 , PPC_REG_V8 = 159 , PPC_REG_V9 = 160 , PPC_REG_V10 = 161 , PPC_REG_V11 = 162 , PPC_REG_V12 = 163 , PPC_REG_V13 = 164 , PPC_REG_V14 = 165 , PPC_REG_V15 = 166 , PPC_REG_V16 = 167 , PPC_REG_V17 = 168 , PPC_REG_V18 = 169 , PPC_REG_V19 = 170 , PPC_REG_V20 = 171 , PPC_REG_V21 = 172 , PPC_REG_V22 = 173 , PPC_REG_V23 = 174 , PPC_REG_V24 = 175 , PPC_REG_V25 = 176 , PPC_REG_V26 = 177 , PPC_REG_V27 = 178 , PPC_REG_V28 = 179 , PPC_REG_V29 = 180 , PPC_REG_V30 = 181 , PPC_REG_V31 = 182 , PPC_REG_VS0 = 215 , PPC_REG_VS1 = 216 , PPC_REG_VS2 = 217 , PPC_REG_VS3 = 218 , PPC_REG_VS4 = 219 , PPC_REG_VS5 = 220 , PPC_REG_VS6 = 221 , PPC_REG_VS7 = 222 , PPC_REG_VS8 = 223 , PPC_REG_VS9 = 224 , PPC_REG_VS10 = 225 , PPC_REG_VS11 = 226 , PPC_REG_VS12 = 227 , PPC_REG_VS13 = 228 , PPC_REG_VS14 = 229 , PPC_REG_VS15 = 230 , PPC_REG_VS16 = 231 , PPC_REG_VS17 = 232 , PPC_REG_VS18 = 233 , PPC_REG_VS19 = 234 , PPC_REG_VS20 = 235 , PPC_REG_VS21 = 236 , PPC_REG_VS22 = 237 , PPC_REG_VS23 = 238 , PPC_REG_VS24 = 239 , PPC_REG_VS25 = 240 , PPC_REG_VS26 = 241 , PPC_REG_VS27 = 242 , PPC_REG_VS28 = 243 , PPC_REG_VS29 = 244 , PPC_REG_VS30 = 245 , PPC_REG_VS31 = 246 , PPC_REG_VS32 = 247 , PPC_REG_VS33 = 248 , PPC_REG_VS34 = 249 , PPC_REG_VS35 = 250 , PPC_REG_VS36 = 251 , PPC_REG_VS37 = 252 , PPC_REG_VS38 = 253 , PPC_REG_VS39 = 254 , PPC_REG_VS40 = 255 , PPC_REG_VS41 = 256 , PPC_REG_VS42 = 257 , PPC_REG_VS43 = 258 , PPC_REG_VS44 = 259 , PPC_REG_VS45 = 260 , PPC_REG_VS46 = 261 , PPC_REG_VS47 = 262 , PPC_REG_VS48 = 263 , PPC_REG_VS49 = 264 , PPC_REG_VS50 = 265 , PPC_REG_VS51 = 266 , PPC_REG_VS52 = 267 , PPC_REG_VS53 = 268 , PPC_REG_VS54 = 269 , PPC_REG_VS55 = 270 , PPC_REG_VS56 = 271 , PPC_REG_VS57 = 272 , PPC_REG_VS58 = 273 , PPC_REG_VS59 = 274 , PPC_REG_VS60 = 275 , PPC_REG_VS61 = 276 , PPC_REG_VS62 = 277 , PPC_REG_VS63 = 278 , PPC_REG_CR0EQ = 312 , PPC_REG_CR1EQ = 313 , PPC_REG_CR2EQ = 314 , PPC_REG_CR3EQ = 315 , PPC_REG_CR4EQ = 316 , PPC_REG_CR5EQ = 317 , PPC_REG_CR6EQ = 318 , PPC_REG_CR7EQ = 319 , PPC_REG_CR0GT = 320 , PPC_REG_CR1GT = 321 , PPC_REG_CR2GT = 322 , PPC_REG_CR3GT = 323 , PPC_REG_CR4GT = 324 , PPC_REG_CR5GT = 325 , PPC_REG_CR6GT = 326 , PPC_REG_CR7GT = 327 , PPC_REG_CR0LT = 328 , PPC_REG_CR1LT = 329 , PPC_REG_CR2LT = 330 , PPC_REG_CR3LT = 331 , PPC_REG_CR4LT = 332 , PPC_REG_CR5LT = 333 , PPC_REG_CR6LT = 334 , PPC_REG_CR7LT = 335 , PPC_REG_CR0UN = 336 , PPC_REG_CR1UN = 337 , PPC_REG_CR2UN = 338 , PPC_REG_CR3UN = 339 , PPC_REG_CR4UN = 340 , PPC_REG_CR5UN = 341 , PPC_REG_CR6UN = 342 , PPC_REG_CR7UN = 343 , PPC_REG_ENDING = 344 , } # [doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_mem { # [doc = "< base register"] pub base : ppc_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_mem"] [:: std :: mem :: size_of :: < ppc_op_mem > () - 8usize] ; ["Alignment of ppc_op_mem"] [:: std :: mem :: align_of :: < ppc_op_mem > () - 4usize] ; ["Offset of field: ppc_op_mem::base"] [:: std :: mem :: offset_of ! (ppc_op_mem , base) - 0usize] ; ["Offset of field: ppc_op_mem::disp"] [:: std :: mem :: offset_of ! (ppc_op_mem , disp) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_crx { pub scale : :: std :: os :: raw :: c_uint , pub reg : ppc_reg , pub cond : ppc_bc , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_crx"] [:: std :: mem :: size_of :: < ppc_op_crx > () - 12usize] ; ["Alignment of ppc_op_crx"] [:: std :: mem :: align_of :: < ppc_op_crx > () - 4usize] ; ["Offset of field: ppc_op_crx::scale"] [:: std :: mem :: offset_of ! (ppc_op_crx , scale) - 0usize] ; ["Offset of field: ppc_op_crx::reg"] [:: std :: mem :: offset_of ! (ppc_op_crx , reg) - 4usize] ; ["Offset of field: ppc_op_crx::cond"] [:: std :: mem :: offset_of ! (ppc_op_crx , cond) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc_op { # [doc = "< operand type"] pub type_ : ppc_op_type , pub __bindgen_anon_1 : cs_ppc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_ppc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : ppc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : ppc_op_mem , # [doc = "< operand with condition register"] pub crx : ppc_op_crx , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_ppc_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_ppc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::crx"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , crx) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op"] [:: std :: mem :: size_of :: < cs_ppc_op > () - 24usize] ; ["Alignment of cs_ppc_op"] [:: std :: mem :: align_of :: < cs_ppc_op > () - 8usize] ; ["Offset of field: cs_ppc_op::type_"] [:: std :: mem :: offset_of ! (cs_ppc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc { # [doc = " branch code for branch instructions"] pub bc : ppc_bc , # [doc = " branch hint for branch instructions"] pub bh : ppc_bh , # [doc = " if update_cr0 = True, then this 'dot' insn updates CR0"] pub update_cr0 : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_ppc_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc"] [:: std :: mem :: size_of :: < cs_ppc > () - 208usize] ; ["Alignment of cs_ppc"] [:: std :: mem :: align_of :: < cs_ppc > () - 8usize] ; ["Offset of field: cs_ppc::bc"] [:: std :: mem :: offset_of ! (cs_ppc , bc) - 0usize] ; ["Offset of field: cs_ppc::bh"] [:: std :: mem :: offset_of ! (cs_ppc , bh) - 4usize] ; ["Offset of field: cs_ppc::update_cr0"] [:: std :: mem :: offset_of ! (cs_ppc , update_cr0) - 8usize] ; ["Offset of field: cs_ppc::op_count"] [:: std :: mem :: offset_of ! (cs_ppc , op_count) - 9usize] ; ["Offset of field: cs_ppc::operands"] [:: std :: mem :: offset_of ! (cs_ppc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}" , self . bc , self . bh , self . update_cr0 , self . op_count , self . operands) } } # [repr (u32)] # [doc = " PPC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn { PPC_INS_INVALID = 0 , PPC_INS_ADD = 1 , PPC_INS_ADDC = 2 , PPC_INS_ADDE = 3 , PPC_INS_ADDI = 4 , PPC_INS_ADDIC = 5 , PPC_INS_ADDIS = 6 , PPC_INS_ADDME = 7 , PPC_INS_ADDPCIS = 8 , PPC_INS_ADDZE = 9 , PPC_INS_AND = 10 , PPC_INS_ANDC = 11 , PPC_INS_ANDI = 12 , PPC_INS_ANDIS = 13 , PPC_INS_ATTN = 14 , PPC_INS_B = 15 , PPC_INS_BA = 16 , PPC_INS_BC = 17 , PPC_INS_BCA = 18 , PPC_INS_BCCTR = 19 , PPC_INS_BCCTRL = 20 , PPC_INS_BCDCFN = 21 , PPC_INS_BCDCFSQ = 22 , PPC_INS_BCDCFZ = 23 , PPC_INS_BCDCPSGN = 24 , PPC_INS_BCDCTN = 25 , PPC_INS_BCDCTSQ = 26 , PPC_INS_BCDCTZ = 27 , PPC_INS_BCDS = 28 , PPC_INS_BCDSETSGN = 29 , PPC_INS_BCDSR = 30 , PPC_INS_BCDTRUNC = 31 , PPC_INS_BCDUS = 32 , PPC_INS_BCDUTRUNC = 33 , PPC_INS_BCL = 34 , PPC_INS_BCLA = 35 , PPC_INS_BCLR = 36 , PPC_INS_BCLRL = 37 , PPC_INS_BCTR = 38 , PPC_INS_BCTRL = 39 , PPC_INS_BDNZ = 40 , PPC_INS_BDNZA = 41 , PPC_INS_BDNZF = 42 , PPC_INS_BDNZFA = 43 , PPC_INS_BDNZFL = 44 , PPC_INS_BDNZFLA = 45 , PPC_INS_BDNZFLR = 46 , PPC_INS_BDNZFLRL = 47 , PPC_INS_BDNZL = 48 , PPC_INS_BDNZLA = 49 , PPC_INS_BDNZLR = 50 , PPC_INS_BDNZLRL = 51 , PPC_INS_BDNZT = 52 , PPC_INS_BDNZTA = 53 , PPC_INS_BDNZTL = 54 , PPC_INS_BDNZTLA = 55 , PPC_INS_BDNZTLR = 56 , PPC_INS_BDNZTLRL = 57 , PPC_INS_BDZ = 58 , PPC_INS_BDZA = 59 , PPC_INS_BDZF = 60 , PPC_INS_BDZFA = 61 , PPC_INS_BDZFL = 62 , PPC_INS_BDZFLA = 63 , PPC_INS_BDZFLR = 64 , PPC_INS_BDZFLRL = 65 , PPC_INS_BDZL = 66 , PPC_INS_BDZLA = 67 , PPC_INS_BDZLR = 68 , PPC_INS_BDZLRL = 69 , PPC_INS_BDZT = 70 , PPC_INS_BDZTA = 71 , PPC_INS_BDZTL = 72 , PPC_INS_BDZTLA = 73 , PPC_INS_BDZTLR = 74 , PPC_INS_BDZTLRL = 75 , PPC_INS_BEQ = 76 , PPC_INS_BEQA = 77 , PPC_INS_BEQCTR = 78 , PPC_INS_BEQCTRL = 79 , PPC_INS_BEQL = 80 , PPC_INS_BEQLA = 81 , PPC_INS_BEQLR = 82 , PPC_INS_BEQLRL = 83 , PPC_INS_BF = 84 , PPC_INS_BFA = 85 , PPC_INS_BFCTR = 86 , PPC_INS_BFCTRL = 87 , PPC_INS_BFL = 88 , PPC_INS_BFLA = 89 , PPC_INS_BFLR = 90 , PPC_INS_BFLRL = 91 , PPC_INS_BGE = 92 , PPC_INS_BGEA = 93 , PPC_INS_BGECTR = 94 , PPC_INS_BGECTRL = 95 , PPC_INS_BGEL = 96 , PPC_INS_BGELA = 97 , PPC_INS_BGELR = 98 , PPC_INS_BGELRL = 99 , PPC_INS_BGT = 100 , PPC_INS_BGTA = 101 , PPC_INS_BGTCTR = 102 , PPC_INS_BGTCTRL = 103 , PPC_INS_BGTL = 104 , PPC_INS_BGTLA = 105 , PPC_INS_BGTLR = 106 , PPC_INS_BGTLRL = 107 , PPC_INS_BL = 108 , PPC_INS_BLA = 109 , PPC_INS_BLE = 110 , PPC_INS_BLEA = 111 , PPC_INS_BLECTR = 112 , PPC_INS_BLECTRL = 113 , PPC_INS_BLEL = 114 , PPC_INS_BLELA = 115 , PPC_INS_BLELR = 116 , PPC_INS_BLELRL = 117 , PPC_INS_BLR = 118 , PPC_INS_BLRL = 119 , PPC_INS_BLT = 120 , PPC_INS_BLTA = 121 , PPC_INS_BLTCTR = 122 , PPC_INS_BLTCTRL = 123 , PPC_INS_BLTL = 124 , PPC_INS_BLTLA = 125 , PPC_INS_BLTLR = 126 , PPC_INS_BLTLRL = 127 , PPC_INS_BNE = 128 , PPC_INS_BNEA = 129 , PPC_INS_BNECTR = 130 , PPC_INS_BNECTRL = 131 , PPC_INS_BNEL = 132 , PPC_INS_BNELA = 133 , PPC_INS_BNELR = 134 , PPC_INS_BNELRL = 135 , PPC_INS_BNG = 136 , PPC_INS_BNGA = 137 , PPC_INS_BNGCTR = 138 , PPC_INS_BNGCTRL = 139 , PPC_INS_BNGL = 140 , PPC_INS_BNGLA = 141 , PPC_INS_BNGLR = 142 , PPC_INS_BNGLRL = 143 , PPC_INS_BNL = 144 , PPC_INS_BNLA = 145 , PPC_INS_BNLCTR = 146 , PPC_INS_BNLCTRL = 147 , PPC_INS_BNLL = 148 , PPC_INS_BNLLA = 149 , PPC_INS_BNLLR = 150 , PPC_INS_BNLLRL = 151 , PPC_INS_BNS = 152 , PPC_INS_BNSA = 153 , PPC_INS_BNSCTR = 154 , PPC_INS_BNSCTRL = 155 , PPC_INS_BNSL = 156 , PPC_INS_BNSLA = 157 , PPC_INS_BNSLR = 158 , PPC_INS_BNSLRL = 159 , PPC_INS_BNU = 160 , PPC_INS_BNUA = 161 , PPC_INS_BNUCTR = 162 , PPC_INS_BNUCTRL = 163 , PPC_INS_BNUL = 164 , PPC_INS_BNULA = 165 , PPC_INS_BNULR = 166 , PPC_INS_BNULRL = 167 , PPC_INS_BPERMD = 168 , PPC_INS_BRINC = 169 , PPC_INS_BSO = 170 , PPC_INS_BSOA = 171 , PPC_INS_BSOCTR = 172 , PPC_INS_BSOCTRL = 173 , PPC_INS_BSOL = 174 , PPC_INS_BSOLA = 175 , PPC_INS_BSOLR = 176 , PPC_INS_BSOLRL = 177 , PPC_INS_BT = 178 , PPC_INS_BTA = 179 , PPC_INS_BTCTR = 180 , PPC_INS_BTCTRL = 181 , PPC_INS_BTL = 182 , PPC_INS_BTLA = 183 , PPC_INS_BTLR = 184 , PPC_INS_BTLRL = 185 , PPC_INS_BUN = 186 , PPC_INS_BUNA = 187 , PPC_INS_BUNCTR = 188 , PPC_INS_BUNCTRL = 189 , PPC_INS_BUNL = 190 , PPC_INS_BUNLA = 191 , PPC_INS_BUNLR = 192 , PPC_INS_BUNLRL = 193 , PPC_INS_CLRBHRB = 194 , PPC_INS_CLRLDI = 195 , PPC_INS_CLRLSLDI = 196 , PPC_INS_CLRLSLWI = 197 , PPC_INS_CLRLWI = 198 , PPC_INS_CLRRDI = 199 , PPC_INS_CLRRWI = 200 , PPC_INS_CMP = 201 , PPC_INS_CMPB = 202 , PPC_INS_CMPD = 203 , PPC_INS_CMPDI = 204 , PPC_INS_CMPEQB = 205 , PPC_INS_CMPI = 206 , PPC_INS_CMPL = 207 , PPC_INS_CMPLD = 208 , PPC_INS_CMPLDI = 209 , PPC_INS_CMPLI = 210 , PPC_INS_CMPLW = 211 , PPC_INS_CMPLWI = 212 , PPC_INS_CMPRB = 213 , PPC_INS_CMPW = 214 , PPC_INS_CMPWI = 215 , PPC_INS_CNTLZD = 216 , PPC_INS_CNTLZW = 217 , PPC_INS_CNTTZD = 218 , PPC_INS_CNTTZW = 219 , PPC_INS_COPY = 220 , PPC_INS_COPY_FIRST = 221 , PPC_INS_CP_ABORT = 222 , PPC_INS_CRAND = 223 , PPC_INS_CRANDC = 224 , PPC_INS_CRCLR = 225 , PPC_INS_CREQV = 226 , PPC_INS_CRMOVE = 227 , PPC_INS_CRNAND = 228 , PPC_INS_CRNOR = 229 , PPC_INS_CRNOT = 230 , PPC_INS_CROR = 231 , PPC_INS_CRORC = 232 , PPC_INS_CRSET = 233 , PPC_INS_CRXOR = 234 , PPC_INS_DARN = 235 , PPC_INS_DCBA = 236 , PPC_INS_DCBF = 237 , PPC_INS_DCBFEP = 238 , PPC_INS_DCBFL = 239 , PPC_INS_DCBFLP = 240 , PPC_INS_DCBI = 241 , PPC_INS_DCBST = 242 , PPC_INS_DCBSTEP = 243 , PPC_INS_DCBT = 244 , PPC_INS_DCBTCT = 245 , PPC_INS_DCBTDS = 246 , PPC_INS_DCBTEP = 247 , PPC_INS_DCBTST = 248 , PPC_INS_DCBTSTCT = 249 , PPC_INS_DCBTSTDS = 250 , PPC_INS_DCBTSTEP = 251 , PPC_INS_DCBTSTT = 252 , PPC_INS_DCBTT = 253 , PPC_INS_DCBZ = 254 , PPC_INS_DCBZEP = 255 , PPC_INS_DCBZL = 256 , PPC_INS_DCBZLEP = 257 , PPC_INS_DCCCI = 258 , PPC_INS_DCI = 259 , PPC_INS_DIVD = 260 , PPC_INS_DIVDE = 261 , PPC_INS_DIVDEU = 262 , PPC_INS_DIVDU = 263 , PPC_INS_DIVW = 264 , PPC_INS_DIVWE = 265 , PPC_INS_DIVWEU = 266 , PPC_INS_DIVWU = 267 , PPC_INS_DSS = 268 , PPC_INS_DSSALL = 269 , PPC_INS_DST = 270 , PPC_INS_DSTST = 271 , PPC_INS_DSTSTT = 272 , PPC_INS_DSTT = 273 , PPC_INS_EFDABS = 274 , PPC_INS_EFDADD = 275 , PPC_INS_EFDCFS = 276 , PPC_INS_EFDCFSF = 277 , PPC_INS_EFDCFSI = 278 , PPC_INS_EFDCFSID = 279 , PPC_INS_EFDCFUF = 280 , PPC_INS_EFDCFUI = 281 , PPC_INS_EFDCFUID = 282 , PPC_INS_EFDCMPEQ = 283 , PPC_INS_EFDCMPGT = 284 , PPC_INS_EFDCMPLT = 285 , PPC_INS_EFDCTSF = 286 , PPC_INS_EFDCTSI = 287 , PPC_INS_EFDCTSIDZ = 288 , PPC_INS_EFDCTSIZ = 289 , PPC_INS_EFDCTUF = 290 , PPC_INS_EFDCTUI = 291 , PPC_INS_EFDCTUIDZ = 292 , PPC_INS_EFDCTUIZ = 293 , PPC_INS_EFDDIV = 294 , PPC_INS_EFDMUL = 295 , PPC_INS_EFDNABS = 296 , PPC_INS_EFDNEG = 297 , PPC_INS_EFDSUB = 298 , PPC_INS_EFDTSTEQ = 299 , PPC_INS_EFDTSTGT = 300 , PPC_INS_EFDTSTLT = 301 , PPC_INS_EFSABS = 302 , PPC_INS_EFSADD = 303 , PPC_INS_EFSCFD = 304 , PPC_INS_EFSCFSF = 305 , PPC_INS_EFSCFSI = 306 , PPC_INS_EFSCFUF = 307 , PPC_INS_EFSCFUI = 308 , PPC_INS_EFSCMPEQ = 309 , PPC_INS_EFSCMPGT = 310 , PPC_INS_EFSCMPLT = 311 , PPC_INS_EFSCTSF = 312 , PPC_INS_EFSCTSI = 313 , PPC_INS_EFSCTSIZ = 314 , PPC_INS_EFSCTUF = 315 , PPC_INS_EFSCTUI = 316 , PPC_INS_EFSCTUIZ = 317 , PPC_INS_EFSDIV = 318 , PPC_INS_EFSMUL = 319 , PPC_INS_EFSNABS = 320 , PPC_INS_EFSNEG = 321 , PPC_INS_EFSSUB = 322 , PPC_INS_EFSTSTEQ = 323 , PPC_INS_EFSTSTGT = 324 , PPC_INS_EFSTSTLT = 325 , PPC_INS_EIEIO = 326 , PPC_INS_EQV = 327 , PPC_INS_EVABS = 328 , PPC_INS_EVADDIW = 329 , PPC_INS_EVADDSMIAAW = 330 , PPC_INS_EVADDSSIAAW = 331 , PPC_INS_EVADDUMIAAW = 332 , PPC_INS_EVADDUSIAAW = 333 , PPC_INS_EVADDW = 334 , PPC_INS_EVAND = 335 , PPC_INS_EVANDC = 336 , PPC_INS_EVCMPEQ = 337 , PPC_INS_EVCMPGTS = 338 , PPC_INS_EVCMPGTU = 339 , PPC_INS_EVCMPLTS = 340 , PPC_INS_EVCMPLTU = 341 , PPC_INS_EVCNTLSW = 342 , PPC_INS_EVCNTLZW = 343 , PPC_INS_EVDIVWS = 344 , PPC_INS_EVDIVWU = 345 , PPC_INS_EVEQV = 346 , PPC_INS_EVEXTSB = 347 , PPC_INS_EVEXTSH = 348 , PPC_INS_EVFSABS = 349 , PPC_INS_EVFSADD = 350 , PPC_INS_EVFSCFSF = 351 , PPC_INS_EVFSCFSI = 352 , PPC_INS_EVFSCFUF = 353 , PPC_INS_EVFSCFUI = 354 , PPC_INS_EVFSCMPEQ = 355 , PPC_INS_EVFSCMPGT = 356 , PPC_INS_EVFSCMPLT = 357 , PPC_INS_EVFSCTSF = 358 , PPC_INS_EVFSCTSI = 359 , PPC_INS_EVFSCTSIZ = 360 , PPC_INS_EVFSCTUI = 361 , PPC_INS_EVFSDIV = 362 , PPC_INS_EVFSMUL = 363 , PPC_INS_EVFSNABS = 364 , PPC_INS_EVFSNEG = 365 , PPC_INS_EVFSSUB = 366 , PPC_INS_EVFSTSTEQ = 367 , PPC_INS_EVFSTSTGT = 368 , PPC_INS_EVFSTSTLT = 369 , PPC_INS_EVLDD = 370 , PPC_INS_EVLDDX = 371 , PPC_INS_EVLDH = 372 , PPC_INS_EVLDHX = 373 , PPC_INS_EVLDW = 374 , PPC_INS_EVLDWX = 375 , PPC_INS_EVLHHESPLAT = 376 , PPC_INS_EVLHHESPLATX = 377 , PPC_INS_EVLHHOSSPLAT = 378 , PPC_INS_EVLHHOSSPLATX = 379 , PPC_INS_EVLHHOUSPLAT = 380 , PPC_INS_EVLHHOUSPLATX = 381 , PPC_INS_EVLWHE = 382 , PPC_INS_EVLWHEX = 383 , PPC_INS_EVLWHOS = 384 , PPC_INS_EVLWHOSX = 385 , PPC_INS_EVLWHOU = 386 , PPC_INS_EVLWHOUX = 387 , PPC_INS_EVLWHSPLAT = 388 , PPC_INS_EVLWHSPLATX = 389 , PPC_INS_EVLWWSPLAT = 390 , PPC_INS_EVLWWSPLATX = 391 , PPC_INS_EVMERGEHI = 392 , PPC_INS_EVMERGEHILO = 393 , PPC_INS_EVMERGELO = 394 , PPC_INS_EVMERGELOHI = 395 , PPC_INS_EVMHEGSMFAA = 396 , PPC_INS_EVMHEGSMFAN = 397 , PPC_INS_EVMHEGSMIAA = 398 , PPC_INS_EVMHEGSMIAN = 399 , PPC_INS_EVMHEGUMIAA = 400 , PPC_INS_EVMHEGUMIAN = 401 , PPC_INS_EVMHESMF = 402 , PPC_INS_EVMHESMFA = 403 , PPC_INS_EVMHESMFAAW = 404 , PPC_INS_EVMHESMFANW = 405 , PPC_INS_EVMHESMI = 406 , PPC_INS_EVMHESMIA = 407 , PPC_INS_EVMHESMIAAW = 408 , PPC_INS_EVMHESMIANW = 409 , PPC_INS_EVMHESSF = 410 , PPC_INS_EVMHESSFA = 411 , PPC_INS_EVMHESSFAAW = 412 , PPC_INS_EVMHESSFANW = 413 , PPC_INS_EVMHESSIAAW = 414 , PPC_INS_EVMHESSIANW = 415 , PPC_INS_EVMHEUMI = 416 , PPC_INS_EVMHEUMIA = 417 , PPC_INS_EVMHEUMIAAW = 418 , PPC_INS_EVMHEUMIANW = 419 , PPC_INS_EVMHEUSIAAW = 420 , PPC_INS_EVMHEUSIANW = 421 , PPC_INS_EVMHOGSMFAA = 422 , PPC_INS_EVMHOGSMFAN = 423 , PPC_INS_EVMHOGSMIAA = 424 , PPC_INS_EVMHOGSMIAN = 425 , PPC_INS_EVMHOGUMIAA = 426 , PPC_INS_EVMHOGUMIAN = 427 , PPC_INS_EVMHOSMF = 428 , PPC_INS_EVMHOSMFA = 429 , PPC_INS_EVMHOSMFAAW = 430 , PPC_INS_EVMHOSMFANW = 431 , PPC_INS_EVMHOSMI = 432 , PPC_INS_EVMHOSMIA = 433 , PPC_INS_EVMHOSMIAAW = 434 , PPC_INS_EVMHOSMIANW = 435 , PPC_INS_EVMHOSSF = 436 , PPC_INS_EVMHOSSFA = 437 , PPC_INS_EVMHOSSFAAW = 438 , PPC_INS_EVMHOSSFANW = 439 , PPC_INS_EVMHOSSIAAW = 440 , PPC_INS_EVMHOSSIANW = 441 , PPC_INS_EVMHOUMI = 442 , PPC_INS_EVMHOUMIA = 443 , PPC_INS_EVMHOUMIAAW = 444 , PPC_INS_EVMHOUMIANW = 445 , PPC_INS_EVMHOUSIAAW = 446 , PPC_INS_EVMHOUSIANW = 447 , PPC_INS_EVMRA = 448 , PPC_INS_EVMWHSMF = 449 , PPC_INS_EVMWHSMFA = 450 , PPC_INS_EVMWHSMI = 451 , PPC_INS_EVMWHSMIA = 452 , PPC_INS_EVMWHSSF = 453 , PPC_INS_EVMWHSSFA = 454 , PPC_INS_EVMWHUMI = 455 , PPC_INS_EVMWHUMIA = 456 , PPC_INS_EVMWLSMIAAW = 457 , PPC_INS_EVMWLSMIANW = 458 , PPC_INS_EVMWLSSIAAW = 459 , PPC_INS_EVMWLSSIANW = 460 , PPC_INS_EVMWLUMI = 461 , PPC_INS_EVMWLUMIA = 462 , PPC_INS_EVMWLUMIAAW = 463 , PPC_INS_EVMWLUMIANW = 464 , PPC_INS_EVMWLUSIAAW = 465 , PPC_INS_EVMWLUSIANW = 466 , PPC_INS_EVMWSMF = 467 , PPC_INS_EVMWSMFA = 468 , PPC_INS_EVMWSMFAA = 469 , PPC_INS_EVMWSMFAN = 470 , PPC_INS_EVMWSMI = 471 , PPC_INS_EVMWSMIA = 472 , PPC_INS_EVMWSMIAA = 473 , PPC_INS_EVMWSMIAN = 474 , PPC_INS_EVMWSSF = 475 , PPC_INS_EVMWSSFA = 476 , PPC_INS_EVMWSSFAA = 477 , PPC_INS_EVMWSSFAN = 478 , PPC_INS_EVMWUMI = 479 , PPC_INS_EVMWUMIA = 480 , PPC_INS_EVMWUMIAA = 481 , PPC_INS_EVMWUMIAN = 482 , PPC_INS_EVNAND = 483 , PPC_INS_EVNEG = 484 , PPC_INS_EVNOR = 485 , PPC_INS_EVOR = 486 , PPC_INS_EVORC = 487 , PPC_INS_EVRLW = 488 , PPC_INS_EVRLWI = 489 , PPC_INS_EVRNDW = 490 , PPC_INS_EVSEL = 491 , PPC_INS_EVSLW = 492 , PPC_INS_EVSLWI = 493 , PPC_INS_EVSPLATFI = 494 , PPC_INS_EVSPLATI = 495 , PPC_INS_EVSRWIS = 496 , PPC_INS_EVSRWIU = 497 , PPC_INS_EVSRWS = 498 , PPC_INS_EVSRWU = 499 , PPC_INS_EVSTDD = 500 , PPC_INS_EVSTDDX = 501 , PPC_INS_EVSTDH = 502 , PPC_INS_EVSTDHX = 503 , PPC_INS_EVSTDW = 504 , PPC_INS_EVSTDWX = 505 , PPC_INS_EVSTWHE = 506 , PPC_INS_EVSTWHEX = 507 , PPC_INS_EVSTWHO = 508 , PPC_INS_EVSTWHOX = 509 , PPC_INS_EVSTWWE = 510 , PPC_INS_EVSTWWEX = 511 , PPC_INS_EVSTWWO = 512 , PPC_INS_EVSTWWOX = 513 , PPC_INS_EVSUBFSMIAAW = 514 , PPC_INS_EVSUBFSSIAAW = 515 , PPC_INS_EVSUBFUMIAAW = 516 , PPC_INS_EVSUBFUSIAAW = 517 , PPC_INS_EVSUBFW = 518 , PPC_INS_EVSUBIFW = 519 , PPC_INS_EVXOR = 520 , PPC_INS_EXTLDI = 521 , PPC_INS_EXTLWI = 522 , PPC_INS_EXTRDI = 523 , PPC_INS_EXTRWI = 524 , PPC_INS_EXTSB = 525 , PPC_INS_EXTSH = 526 , PPC_INS_EXTSW = 527 , PPC_INS_EXTSWSLI = 528 , PPC_INS_FABS = 529 , PPC_INS_FADD = 530 , PPC_INS_FADDS = 531 , PPC_INS_FCFID = 532 , PPC_INS_FCFIDS = 533 , PPC_INS_FCFIDU = 534 , PPC_INS_FCFIDUS = 535 , PPC_INS_FCMPU = 536 , PPC_INS_FCPSGN = 537 , PPC_INS_FCTID = 538 , PPC_INS_FCTIDU = 539 , PPC_INS_FCTIDUZ = 540 , PPC_INS_FCTIDZ = 541 , PPC_INS_FCTIW = 542 , PPC_INS_FCTIWU = 543 , PPC_INS_FCTIWUZ = 544 , PPC_INS_FCTIWZ = 545 , PPC_INS_FDIV = 546 , PPC_INS_FDIVS = 547 , PPC_INS_FMADD = 548 , PPC_INS_FMADDS = 549 , PPC_INS_FMR = 550 , PPC_INS_FMSUB = 551 , PPC_INS_FMSUBS = 552 , PPC_INS_FMUL = 553 , PPC_INS_FMULS = 554 , PPC_INS_FNABS = 555 , PPC_INS_FNEG = 556 , PPC_INS_FNMADD = 557 , PPC_INS_FNMADDS = 558 , PPC_INS_FNMSUB = 559 , PPC_INS_FNMSUBS = 560 , PPC_INS_FRE = 561 , PPC_INS_FRES = 562 , PPC_INS_FRIM = 563 , PPC_INS_FRIN = 564 , PPC_INS_FRIP = 565 , PPC_INS_FRIZ = 566 , PPC_INS_FRSP = 567 , PPC_INS_FRSQRTE = 568 , PPC_INS_FRSQRTES = 569 , PPC_INS_FSEL = 570 , PPC_INS_FSQRT = 571 , PPC_INS_FSQRTS = 572 , PPC_INS_FSUB = 573 , PPC_INS_FSUBS = 574 , PPC_INS_FTDIV = 575 , PPC_INS_FTSQRT = 576 , PPC_INS_HRFID = 577 , PPC_INS_ICBI = 578 , PPC_INS_ICBIEP = 579 , PPC_INS_ICBLC = 580 , PPC_INS_ICBLQ = 581 , PPC_INS_ICBT = 582 , PPC_INS_ICBTLS = 583 , PPC_INS_ICCCI = 584 , PPC_INS_ICI = 585 , PPC_INS_INSLWI = 586 , PPC_INS_INSRDI = 587 , PPC_INS_INSRWI = 588 , PPC_INS_ISEL = 589 , PPC_INS_ISYNC = 590 , PPC_INS_LA = 591 , PPC_INS_LBARX = 592 , PPC_INS_LBEPX = 593 , PPC_INS_LBZ = 594 , PPC_INS_LBZCIX = 595 , PPC_INS_LBZU = 596 , PPC_INS_LBZUX = 597 , PPC_INS_LBZX = 598 , PPC_INS_LD = 599 , PPC_INS_LDARX = 600 , PPC_INS_LDAT = 601 , PPC_INS_LDBRX = 602 , PPC_INS_LDCIX = 603 , PPC_INS_LDMX = 604 , PPC_INS_LDU = 605 , PPC_INS_LDUX = 606 , PPC_INS_LDX = 607 , PPC_INS_LFD = 608 , PPC_INS_LFDEPX = 609 , PPC_INS_LFDU = 610 , PPC_INS_LFDUX = 611 , PPC_INS_LFDX = 612 , PPC_INS_LFIWAX = 613 , PPC_INS_LFIWZX = 614 , PPC_INS_LFS = 615 , PPC_INS_LFSU = 616 , PPC_INS_LFSUX = 617 , PPC_INS_LFSX = 618 , PPC_INS_LHA = 619 , PPC_INS_LHARX = 620 , PPC_INS_LHAU = 621 , PPC_INS_LHAUX = 622 , PPC_INS_LHAX = 623 , PPC_INS_LHBRX = 624 , PPC_INS_LHEPX = 625 , PPC_INS_LHZ = 626 , PPC_INS_LHZCIX = 627 , PPC_INS_LHZU = 628 , PPC_INS_LHZUX = 629 , PPC_INS_LHZX = 630 , PPC_INS_LI = 631 , PPC_INS_LIS = 632 , PPC_INS_LMW = 633 , PPC_INS_LNIA = 634 , PPC_INS_LSWI = 635 , PPC_INS_LVEBX = 636 , PPC_INS_LVEHX = 637 , PPC_INS_LVEWX = 638 , PPC_INS_LVSL = 639 , PPC_INS_LVSR = 640 , PPC_INS_LVX = 641 , PPC_INS_LVXL = 642 , PPC_INS_LWA = 643 , PPC_INS_LWARX = 644 , PPC_INS_LWAT = 645 , PPC_INS_LWAUX = 646 , PPC_INS_LWAX = 647 , PPC_INS_LWBRX = 648 , PPC_INS_LWEPX = 649 , PPC_INS_LWSYNC = 650 , PPC_INS_LWZ = 651 , PPC_INS_LWZCIX = 652 , PPC_INS_LWZU = 653 , PPC_INS_LWZUX = 654 , PPC_INS_LWZX = 655 , PPC_INS_LXSD = 656 , PPC_INS_LXSDX = 657 , PPC_INS_LXSIBZX = 658 , PPC_INS_LXSIHZX = 659 , PPC_INS_LXSIWAX = 660 , PPC_INS_LXSIWZX = 661 , PPC_INS_LXSSP = 662 , PPC_INS_LXSSPX = 663 , PPC_INS_LXV = 664 , PPC_INS_LXVB16X = 665 , PPC_INS_LXVD2X = 666 , PPC_INS_LXVDSX = 667 , PPC_INS_LXVH8X = 668 , PPC_INS_LXVL = 669 , PPC_INS_LXVLL = 670 , PPC_INS_LXVW4X = 671 , PPC_INS_LXVWSX = 672 , PPC_INS_LXVX = 673 , PPC_INS_MADDHD = 674 , PPC_INS_MADDHDU = 675 , PPC_INS_MADDLD = 676 , PPC_INS_MBAR = 677 , PPC_INS_MCRF = 678 , PPC_INS_MCRFS = 679 , PPC_INS_MCRXRX = 680 , PPC_INS_MFAMR = 681 , PPC_INS_MFASR = 682 , PPC_INS_MFBHRBE = 683 , PPC_INS_MFBR0 = 684 , PPC_INS_MFBR1 = 685 , PPC_INS_MFBR2 = 686 , PPC_INS_MFBR3 = 687 , PPC_INS_MFBR4 = 688 , PPC_INS_MFBR5 = 689 , PPC_INS_MFBR6 = 690 , PPC_INS_MFBR7 = 691 , PPC_INS_MFCFAR = 692 , PPC_INS_MFCR = 693 , PPC_INS_MFCTR = 694 , PPC_INS_MFDAR = 695 , PPC_INS_MFDBATL = 696 , PPC_INS_MFDBATU = 697 , PPC_INS_MFDCCR = 698 , PPC_INS_MFDCR = 699 , PPC_INS_MFDEAR = 700 , PPC_INS_MFDEC = 701 , PPC_INS_MFDSCR = 702 , PPC_INS_MFDSISR = 703 , PPC_INS_MFESR = 704 , PPC_INS_MFFPRD = 705 , PPC_INS_MFFS = 706 , PPC_INS_MFFSCDRN = 707 , PPC_INS_MFFSCDRNI = 708 , PPC_INS_MFFSCE = 709 , PPC_INS_MFFSCRN = 710 , PPC_INS_MFFSCRNI = 711 , PPC_INS_MFFSL = 712 , PPC_INS_MFIBATL = 713 , PPC_INS_MFIBATU = 714 , PPC_INS_MFICCR = 715 , PPC_INS_MFLR = 716 , PPC_INS_MFMSR = 717 , PPC_INS_MFOCRF = 718 , PPC_INS_MFPID = 719 , PPC_INS_MFPMR = 720 , PPC_INS_MFPVR = 721 , PPC_INS_MFRTCL = 722 , PPC_INS_MFRTCU = 723 , PPC_INS_MFSDR1 = 724 , PPC_INS_MFSPEFSCR = 725 , PPC_INS_MFSPR = 726 , PPC_INS_MFSPRG = 727 , PPC_INS_MFSPRG0 = 728 , PPC_INS_MFSPRG1 = 729 , PPC_INS_MFSPRG2 = 730 , PPC_INS_MFSPRG3 = 731 , PPC_INS_MFSPRG4 = 732 , PPC_INS_MFSPRG5 = 733 , PPC_INS_MFSPRG6 = 734 , PPC_INS_MFSPRG7 = 735 , PPC_INS_MFSR = 736 , PPC_INS_MFSRIN = 737 , PPC_INS_MFSRR0 = 738 , PPC_INS_MFSRR1 = 739 , PPC_INS_MFSRR2 = 740 , PPC_INS_MFSRR3 = 741 , PPC_INS_MFTB = 742 , PPC_INS_MFTBHI = 743 , PPC_INS_MFTBL = 744 , PPC_INS_MFTBLO = 745 , PPC_INS_MFTBU = 746 , PPC_INS_MFTCR = 747 , PPC_INS_MFVRD = 748 , PPC_INS_MFVRSAVE = 749 , PPC_INS_MFVSCR = 750 , PPC_INS_MFVSRD = 751 , PPC_INS_MFVSRLD = 752 , PPC_INS_MFVSRWZ = 753 , PPC_INS_MFXER = 754 , PPC_INS_MODSD = 755 , PPC_INS_MODSW = 756 , PPC_INS_MODUD = 757 , PPC_INS_MODUW = 758 , PPC_INS_MR = 759 , PPC_INS_MSGSYNC = 760 , PPC_INS_MSYNC = 761 , PPC_INS_MTAMR = 762 , PPC_INS_MTASR = 763 , PPC_INS_MTBR0 = 764 , PPC_INS_MTBR1 = 765 , PPC_INS_MTBR2 = 766 , PPC_INS_MTBR3 = 767 , PPC_INS_MTBR4 = 768 , PPC_INS_MTBR5 = 769 , PPC_INS_MTBR6 = 770 , PPC_INS_MTBR7 = 771 , PPC_INS_MTCFAR = 772 , PPC_INS_MTCR = 773 , PPC_INS_MTCRF = 774 , PPC_INS_MTCTR = 775 , PPC_INS_MTDAR = 776 , PPC_INS_MTDBATL = 777 , PPC_INS_MTDBATU = 778 , PPC_INS_MTDCCR = 779 , PPC_INS_MTDCR = 780 , PPC_INS_MTDEAR = 781 , PPC_INS_MTDEC = 782 , PPC_INS_MTDSCR = 783 , PPC_INS_MTDSISR = 784 , PPC_INS_MTESR = 785 , PPC_INS_MTFSB0 = 786 , PPC_INS_MTFSB1 = 787 , PPC_INS_MTFSF = 788 , PPC_INS_MTFSFI = 789 , PPC_INS_MTIBATL = 790 , PPC_INS_MTIBATU = 791 , PPC_INS_MTICCR = 792 , PPC_INS_MTLR = 793 , PPC_INS_MTMSR = 794 , PPC_INS_MTMSRD = 795 , PPC_INS_MTOCRF = 796 , PPC_INS_MTPID = 797 , PPC_INS_MTPMR = 798 , PPC_INS_MTSDR1 = 799 , PPC_INS_MTSPEFSCR = 800 , PPC_INS_MTSPR = 801 , PPC_INS_MTSPRG = 802 , PPC_INS_MTSPRG0 = 803 , PPC_INS_MTSPRG1 = 804 , PPC_INS_MTSPRG2 = 805 , PPC_INS_MTSPRG3 = 806 , PPC_INS_MTSPRG4 = 807 , PPC_INS_MTSPRG5 = 808 , PPC_INS_MTSPRG6 = 809 , PPC_INS_MTSPRG7 = 810 , PPC_INS_MTSR = 811 , PPC_INS_MTSRIN = 812 , PPC_INS_MTSRR0 = 813 , PPC_INS_MTSRR1 = 814 , PPC_INS_MTSRR2 = 815 , PPC_INS_MTSRR3 = 816 , PPC_INS_MTTBHI = 817 , PPC_INS_MTTBL = 818 , PPC_INS_MTTBLO = 819 , PPC_INS_MTTBU = 820 , PPC_INS_MTTCR = 821 , PPC_INS_MTVRSAVE = 822 , PPC_INS_MTVSCR = 823 , PPC_INS_MTVSRD = 824 , PPC_INS_MTVSRDD = 825 , PPC_INS_MTVSRWA = 826 , PPC_INS_MTVSRWS = 827 , PPC_INS_MTVSRWZ = 828 , PPC_INS_MTXER = 829 , PPC_INS_MULHD = 830 , PPC_INS_MULHDU = 831 , PPC_INS_MULHW = 832 , PPC_INS_MULHWU = 833 , PPC_INS_MULLD = 834 , PPC_INS_MULLI = 835 , PPC_INS_MULLW = 836 , PPC_INS_NAND = 837 , PPC_INS_NAP = 838 , PPC_INS_NEG = 839 , PPC_INS_NOP = 840 , PPC_INS_NOR = 841 , PPC_INS_NOT = 842 , PPC_INS_OR = 843 , PPC_INS_ORC = 844 , PPC_INS_ORI = 845 , PPC_INS_ORIS = 846 , PPC_INS_PASTE = 847 , PPC_INS_PASTE_LAST = 848 , PPC_INS_POPCNTB = 849 , PPC_INS_POPCNTD = 850 , PPC_INS_POPCNTW = 851 , PPC_INS_PTESYNC = 852 , PPC_INS_QVALIGNI = 853 , PPC_INS_QVESPLATI = 854 , PPC_INS_QVFABS = 855 , PPC_INS_QVFADD = 856 , PPC_INS_QVFADDS = 857 , PPC_INS_QVFAND = 858 , PPC_INS_QVFANDC = 859 , PPC_INS_QVFCFID = 860 , PPC_INS_QVFCFIDS = 861 , PPC_INS_QVFCFIDU = 862 , PPC_INS_QVFCFIDUS = 863 , PPC_INS_QVFCLR = 864 , PPC_INS_QVFCMPEQ = 865 , PPC_INS_QVFCMPGT = 866 , PPC_INS_QVFCMPLT = 867 , PPC_INS_QVFCPSGN = 868 , PPC_INS_QVFCTFB = 869 , PPC_INS_QVFCTID = 870 , PPC_INS_QVFCTIDU = 871 , PPC_INS_QVFCTIDUZ = 872 , PPC_INS_QVFCTIDZ = 873 , PPC_INS_QVFCTIW = 874 , PPC_INS_QVFCTIWU = 875 , PPC_INS_QVFCTIWUZ = 876 , PPC_INS_QVFCTIWZ = 877 , PPC_INS_QVFEQU = 878 , PPC_INS_QVFLOGICAL = 879 , PPC_INS_QVFMADD = 880 , PPC_INS_QVFMADDS = 881 , PPC_INS_QVFMR = 882 , PPC_INS_QVFMSUB = 883 , PPC_INS_QVFMSUBS = 884 , PPC_INS_QVFMUL = 885 , PPC_INS_QVFMULS = 886 , PPC_INS_QVFNABS = 887 , PPC_INS_QVFNAND = 888 , PPC_INS_QVFNEG = 889 , PPC_INS_QVFNMADD = 890 , PPC_INS_QVFNMADDS = 891 , PPC_INS_QVFNMSUB = 892 , PPC_INS_QVFNMSUBS = 893 , PPC_INS_QVFNOR = 894 , PPC_INS_QVFNOT = 895 , PPC_INS_QVFOR = 896 , PPC_INS_QVFORC = 897 , PPC_INS_QVFPERM = 898 , PPC_INS_QVFRE = 899 , PPC_INS_QVFRES = 900 , PPC_INS_QVFRIM = 901 , PPC_INS_QVFRIN = 902 , PPC_INS_QVFRIP = 903 , PPC_INS_QVFRIZ = 904 , PPC_INS_QVFRSP = 905 , PPC_INS_QVFRSQRTE = 906 , PPC_INS_QVFRSQRTES = 907 , PPC_INS_QVFSEL = 908 , PPC_INS_QVFSET = 909 , PPC_INS_QVFSUB = 910 , PPC_INS_QVFSUBS = 911 , PPC_INS_QVFTSTNAN = 912 , PPC_INS_QVFXMADD = 913 , PPC_INS_QVFXMADDS = 914 , PPC_INS_QVFXMUL = 915 , PPC_INS_QVFXMULS = 916 , PPC_INS_QVFXOR = 917 , PPC_INS_QVFXXCPNMADD = 918 , PPC_INS_QVFXXCPNMADDS = 919 , PPC_INS_QVFXXMADD = 920 , PPC_INS_QVFXXMADDS = 921 , PPC_INS_QVFXXNPMADD = 922 , PPC_INS_QVFXXNPMADDS = 923 , PPC_INS_QVGPCI = 924 , PPC_INS_QVLFCDUX = 925 , PPC_INS_QVLFCDUXA = 926 , PPC_INS_QVLFCDX = 927 , PPC_INS_QVLFCDXA = 928 , PPC_INS_QVLFCSUX = 929 , PPC_INS_QVLFCSUXA = 930 , PPC_INS_QVLFCSX = 931 , PPC_INS_QVLFCSXA = 932 , PPC_INS_QVLFDUX = 933 , PPC_INS_QVLFDUXA = 934 , PPC_INS_QVLFDX = 935 , PPC_INS_QVLFDXA = 936 , PPC_INS_QVLFIWAX = 937 , PPC_INS_QVLFIWAXA = 938 , PPC_INS_QVLFIWZX = 939 , PPC_INS_QVLFIWZXA = 940 , PPC_INS_QVLFSUX = 941 , PPC_INS_QVLFSUXA = 942 , PPC_INS_QVLFSX = 943 , PPC_INS_QVLFSXA = 944 , PPC_INS_QVLPCLDX = 945 , PPC_INS_QVLPCLSX = 946 , PPC_INS_QVLPCRDX = 947 , PPC_INS_QVLPCRSX = 948 , PPC_INS_QVSTFCDUX = 949 , PPC_INS_QVSTFCDUXA = 950 , PPC_INS_QVSTFCDUXI = 951 , PPC_INS_QVSTFCDUXIA = 952 , PPC_INS_QVSTFCDX = 953 , PPC_INS_QVSTFCDXA = 954 , PPC_INS_QVSTFCDXI = 955 , PPC_INS_QVSTFCDXIA = 956 , PPC_INS_QVSTFCSUX = 957 , PPC_INS_QVSTFCSUXA = 958 , PPC_INS_QVSTFCSUXI = 959 , PPC_INS_QVSTFCSUXIA = 960 , PPC_INS_QVSTFCSX = 961 , PPC_INS_QVSTFCSXA = 962 , PPC_INS_QVSTFCSXI = 963 , PPC_INS_QVSTFCSXIA = 964 , PPC_INS_QVSTFDUX = 965 , PPC_INS_QVSTFDUXA = 966 , PPC_INS_QVSTFDUXI = 967 , PPC_INS_QVSTFDUXIA = 968 , PPC_INS_QVSTFDX = 969 , PPC_INS_QVSTFDXA = 970 , PPC_INS_QVSTFDXI = 971 , PPC_INS_QVSTFDXIA = 972 , PPC_INS_QVSTFIWX = 973 , PPC_INS_QVSTFIWXA = 974 , PPC_INS_QVSTFSUX = 975 , PPC_INS_QVSTFSUXA = 976 , PPC_INS_QVSTFSUXI = 977 , PPC_INS_QVSTFSUXIA = 978 , PPC_INS_QVSTFSX = 979 , PPC_INS_QVSTFSXA = 980 , PPC_INS_QVSTFSXI = 981 , PPC_INS_QVSTFSXIA = 982 , PPC_INS_RFCI = 983 , PPC_INS_RFDI = 984 , PPC_INS_RFEBB = 985 , PPC_INS_RFI = 986 , PPC_INS_RFID = 987 , PPC_INS_RFMCI = 988 , PPC_INS_RLDCL = 989 , PPC_INS_RLDCR = 990 , PPC_INS_RLDIC = 991 , PPC_INS_RLDICL = 992 , PPC_INS_RLDICR = 993 , PPC_INS_RLDIMI = 994 , PPC_INS_RLWIMI = 995 , PPC_INS_RLWINM = 996 , PPC_INS_RLWNM = 997 , PPC_INS_ROTLD = 998 , PPC_INS_ROTLDI = 999 , PPC_INS_ROTLW = 1000 , PPC_INS_ROTLWI = 1001 , PPC_INS_ROTRDI = 1002 , PPC_INS_ROTRWI = 1003 , PPC_INS_SC = 1004 , PPC_INS_SETB = 1005 , PPC_INS_SLBIA = 1006 , PPC_INS_SLBIE = 1007 , PPC_INS_SLBIEG = 1008 , PPC_INS_SLBMFEE = 1009 , PPC_INS_SLBMFEV = 1010 , PPC_INS_SLBMTE = 1011 , PPC_INS_SLBSYNC = 1012 , PPC_INS_SLD = 1013 , PPC_INS_SLDI = 1014 , PPC_INS_SLW = 1015 , PPC_INS_SLWI = 1016 , PPC_INS_SRAD = 1017 , PPC_INS_SRADI = 1018 , PPC_INS_SRAW = 1019 , PPC_INS_SRAWI = 1020 , PPC_INS_SRD = 1021 , PPC_INS_SRDI = 1022 , PPC_INS_SRW = 1023 , PPC_INS_SRWI = 1024 , PPC_INS_STB = 1025 , PPC_INS_STBCIX = 1026 , PPC_INS_STBCX = 1027 , PPC_INS_STBEPX = 1028 , PPC_INS_STBU = 1029 , PPC_INS_STBUX = 1030 , PPC_INS_STBX = 1031 , PPC_INS_STD = 1032 , PPC_INS_STDAT = 1033 , PPC_INS_STDBRX = 1034 , PPC_INS_STDCIX = 1035 , PPC_INS_STDCX = 1036 , PPC_INS_STDU = 1037 , PPC_INS_STDUX = 1038 , PPC_INS_STDX = 1039 , PPC_INS_STFD = 1040 , PPC_INS_STFDEPX = 1041 , PPC_INS_STFDU = 1042 , PPC_INS_STFDUX = 1043 , PPC_INS_STFDX = 1044 , PPC_INS_STFIWX = 1045 , PPC_INS_STFS = 1046 , PPC_INS_STFSU = 1047 , PPC_INS_STFSUX = 1048 , PPC_INS_STFSX = 1049 , PPC_INS_STH = 1050 , PPC_INS_STHBRX = 1051 , PPC_INS_STHCIX = 1052 , PPC_INS_STHCX = 1053 , PPC_INS_STHEPX = 1054 , PPC_INS_STHU = 1055 , PPC_INS_STHUX = 1056 , PPC_INS_STHX = 1057 , PPC_INS_STMW = 1058 , PPC_INS_STOP = 1059 , PPC_INS_STSWI = 1060 , PPC_INS_STVEBX = 1061 , PPC_INS_STVEHX = 1062 , PPC_INS_STVEWX = 1063 , PPC_INS_STVX = 1064 , PPC_INS_STVXL = 1065 , PPC_INS_STW = 1066 , PPC_INS_STWAT = 1067 , PPC_INS_STWBRX = 1068 , PPC_INS_STWCIX = 1069 , PPC_INS_STWCX = 1070 , PPC_INS_STWEPX = 1071 , PPC_INS_STWU = 1072 , PPC_INS_STWUX = 1073 , PPC_INS_STWX = 1074 , PPC_INS_STXSD = 1075 , PPC_INS_STXSDX = 1076 , PPC_INS_STXSIBX = 1077 , PPC_INS_STXSIHX = 1078 , PPC_INS_STXSIWX = 1079 , PPC_INS_STXSSP = 1080 , PPC_INS_STXSSPX = 1081 , PPC_INS_STXV = 1082 , PPC_INS_STXVB16X = 1083 , PPC_INS_STXVD2X = 1084 , PPC_INS_STXVH8X = 1085 , PPC_INS_STXVL = 1086 , PPC_INS_STXVLL = 1087 , PPC_INS_STXVW4X = 1088 , PPC_INS_STXVX = 1089 , PPC_INS_SUB = 1090 , PPC_INS_SUBC = 1091 , PPC_INS_SUBF = 1092 , PPC_INS_SUBFC = 1093 , PPC_INS_SUBFE = 1094 , PPC_INS_SUBFIC = 1095 , PPC_INS_SUBFME = 1096 , PPC_INS_SUBFZE = 1097 , PPC_INS_SUBI = 1098 , PPC_INS_SUBIC = 1099 , PPC_INS_SUBIS = 1100 , PPC_INS_SUBPCIS = 1101 , PPC_INS_SYNC = 1102 , PPC_INS_TABORT = 1103 , PPC_INS_TABORTDC = 1104 , PPC_INS_TABORTDCI = 1105 , PPC_INS_TABORTWC = 1106 , PPC_INS_TABORTWCI = 1107 , PPC_INS_TBEGIN = 1108 , PPC_INS_TCHECK = 1109 , PPC_INS_TD = 1110 , PPC_INS_TDEQ = 1111 , PPC_INS_TDEQI = 1112 , PPC_INS_TDGE = 1113 , PPC_INS_TDGEI = 1114 , PPC_INS_TDGT = 1115 , PPC_INS_TDGTI = 1116 , PPC_INS_TDI = 1117 , PPC_INS_TDLE = 1118 , PPC_INS_TDLEI = 1119 , PPC_INS_TDLGE = 1120 , PPC_INS_TDLGEI = 1121 , PPC_INS_TDLGT = 1122 , PPC_INS_TDLGTI = 1123 , PPC_INS_TDLLE = 1124 , PPC_INS_TDLLEI = 1125 , PPC_INS_TDLLT = 1126 , PPC_INS_TDLLTI = 1127 , PPC_INS_TDLNG = 1128 , PPC_INS_TDLNGI = 1129 , PPC_INS_TDLNL = 1130 , PPC_INS_TDLNLI = 1131 , PPC_INS_TDLT = 1132 , PPC_INS_TDLTI = 1133 , PPC_INS_TDNE = 1134 , PPC_INS_TDNEI = 1135 , PPC_INS_TDNG = 1136 , PPC_INS_TDNGI = 1137 , PPC_INS_TDNL = 1138 , PPC_INS_TDNLI = 1139 , PPC_INS_TDU = 1140 , PPC_INS_TDUI = 1141 , PPC_INS_TEND = 1142 , PPC_INS_TLBIA = 1143 , PPC_INS_TLBIE = 1144 , PPC_INS_TLBIEL = 1145 , PPC_INS_TLBIVAX = 1146 , PPC_INS_TLBLD = 1147 , PPC_INS_TLBLI = 1148 , PPC_INS_TLBRE = 1149 , PPC_INS_TLBREHI = 1150 , PPC_INS_TLBRELO = 1151 , PPC_INS_TLBSX = 1152 , PPC_INS_TLBSYNC = 1153 , PPC_INS_TLBWE = 1154 , PPC_INS_TLBWEHI = 1155 , PPC_INS_TLBWELO = 1156 , PPC_INS_TRAP = 1157 , PPC_INS_TRECHKPT = 1158 , PPC_INS_TRECLAIM = 1159 , PPC_INS_TSR = 1160 , PPC_INS_TW = 1161 , PPC_INS_TWEQ = 1162 , PPC_INS_TWEQI = 1163 , PPC_INS_TWGE = 1164 , PPC_INS_TWGEI = 1165 , PPC_INS_TWGT = 1166 , PPC_INS_TWGTI = 1167 , PPC_INS_TWI = 1168 , PPC_INS_TWLE = 1169 , PPC_INS_TWLEI = 1170 , PPC_INS_TWLGE = 1171 , PPC_INS_TWLGEI = 1172 , PPC_INS_TWLGT = 1173 , PPC_INS_TWLGTI = 1174 , PPC_INS_TWLLE = 1175 , PPC_INS_TWLLEI = 1176 , PPC_INS_TWLLT = 1177 , PPC_INS_TWLLTI = 1178 , PPC_INS_TWLNG = 1179 , PPC_INS_TWLNGI = 1180 , PPC_INS_TWLNL = 1181 , PPC_INS_TWLNLI = 1182 , PPC_INS_TWLT = 1183 , PPC_INS_TWLTI = 1184 , PPC_INS_TWNE = 1185 , PPC_INS_TWNEI = 1186 , PPC_INS_TWNG = 1187 , PPC_INS_TWNGI = 1188 , PPC_INS_TWNL = 1189 , PPC_INS_TWNLI = 1190 , PPC_INS_TWU = 1191 , PPC_INS_TWUI = 1192 , PPC_INS_VABSDUB = 1193 , PPC_INS_VABSDUH = 1194 , PPC_INS_VABSDUW = 1195 , PPC_INS_VADDCUQ = 1196 , PPC_INS_VADDCUW = 1197 , PPC_INS_VADDECUQ = 1198 , PPC_INS_VADDEUQM = 1199 , PPC_INS_VADDFP = 1200 , PPC_INS_VADDSBS = 1201 , PPC_INS_VADDSHS = 1202 , PPC_INS_VADDSWS = 1203 , PPC_INS_VADDUBM = 1204 , PPC_INS_VADDUBS = 1205 , PPC_INS_VADDUDM = 1206 , PPC_INS_VADDUHM = 1207 , PPC_INS_VADDUHS = 1208 , PPC_INS_VADDUQM = 1209 , PPC_INS_VADDUWM = 1210 , PPC_INS_VADDUWS = 1211 , PPC_INS_VAND = 1212 , PPC_INS_VANDC = 1213 , PPC_INS_VAVGSB = 1214 , PPC_INS_VAVGSH = 1215 , PPC_INS_VAVGSW = 1216 , PPC_INS_VAVGUB = 1217 , PPC_INS_VAVGUH = 1218 , PPC_INS_VAVGUW = 1219 , PPC_INS_VBPERMD = 1220 , PPC_INS_VBPERMQ = 1221 , PPC_INS_VCFSX = 1222 , PPC_INS_VCFUX = 1223 , PPC_INS_VCIPHER = 1224 , PPC_INS_VCIPHERLAST = 1225 , PPC_INS_VCLZB = 1226 , PPC_INS_VCLZD = 1227 , PPC_INS_VCLZH = 1228 , PPC_INS_VCLZLSBB = 1229 , PPC_INS_VCLZW = 1230 , PPC_INS_VCMPBFP = 1231 , PPC_INS_VCMPEQFP = 1232 , PPC_INS_VCMPEQUB = 1233 , PPC_INS_VCMPEQUD = 1234 , PPC_INS_VCMPEQUH = 1235 , PPC_INS_VCMPEQUW = 1236 , PPC_INS_VCMPGEFP = 1237 , PPC_INS_VCMPGTFP = 1238 , PPC_INS_VCMPGTSB = 1239 , PPC_INS_VCMPGTSD = 1240 , PPC_INS_VCMPGTSH = 1241 , PPC_INS_VCMPGTSW = 1242 , PPC_INS_VCMPGTUB = 1243 , PPC_INS_VCMPGTUD = 1244 , PPC_INS_VCMPGTUH = 1245 , PPC_INS_VCMPGTUW = 1246 , PPC_INS_VCMPNEB = 1247 , PPC_INS_VCMPNEH = 1248 , PPC_INS_VCMPNEW = 1249 , PPC_INS_VCMPNEZB = 1250 , PPC_INS_VCMPNEZH = 1251 , PPC_INS_VCMPNEZW = 1252 , PPC_INS_VCTSXS = 1253 , PPC_INS_VCTUXS = 1254 , PPC_INS_VCTZB = 1255 , PPC_INS_VCTZD = 1256 , PPC_INS_VCTZH = 1257 , PPC_INS_VCTZLSBB = 1258 , PPC_INS_VCTZW = 1259 , PPC_INS_VEQV = 1260 , PPC_INS_VEXPTEFP = 1261 , PPC_INS_VEXTRACTD = 1262 , PPC_INS_VEXTRACTUB = 1263 , PPC_INS_VEXTRACTUH = 1264 , PPC_INS_VEXTRACTUW = 1265 , PPC_INS_VEXTSB2D = 1266 , PPC_INS_VEXTSB2W = 1267 , PPC_INS_VEXTSH2D = 1268 , PPC_INS_VEXTSH2W = 1269 , PPC_INS_VEXTSW2D = 1270 , PPC_INS_VEXTUBLX = 1271 , PPC_INS_VEXTUBRX = 1272 , PPC_INS_VEXTUHLX = 1273 , PPC_INS_VEXTUHRX = 1274 , PPC_INS_VEXTUWLX = 1275 , PPC_INS_VEXTUWRX = 1276 , PPC_INS_VGBBD = 1277 , PPC_INS_VINSERTB = 1278 , PPC_INS_VINSERTD = 1279 , PPC_INS_VINSERTH = 1280 , PPC_INS_VINSERTW = 1281 , PPC_INS_VLOGEFP = 1282 , PPC_INS_VMADDFP = 1283 , PPC_INS_VMAXFP = 1284 , PPC_INS_VMAXSB = 1285 , PPC_INS_VMAXSD = 1286 , PPC_INS_VMAXSH = 1287 , PPC_INS_VMAXSW = 1288 , PPC_INS_VMAXUB = 1289 , PPC_INS_VMAXUD = 1290 , PPC_INS_VMAXUH = 1291 , PPC_INS_VMAXUW = 1292 , PPC_INS_VMHADDSHS = 1293 , PPC_INS_VMHRADDSHS = 1294 , PPC_INS_VMINFP = 1295 , PPC_INS_VMINSB = 1296 , PPC_INS_VMINSD = 1297 , PPC_INS_VMINSH = 1298 , PPC_INS_VMINSW = 1299 , PPC_INS_VMINUB = 1300 , PPC_INS_VMINUD = 1301 , PPC_INS_VMINUH = 1302 , PPC_INS_VMINUW = 1303 , PPC_INS_VMLADDUHM = 1304 , PPC_INS_VMR = 1305 , PPC_INS_VMRGEW = 1306 , PPC_INS_VMRGHB = 1307 , PPC_INS_VMRGHH = 1308 , PPC_INS_VMRGHW = 1309 , PPC_INS_VMRGLB = 1310 , PPC_INS_VMRGLH = 1311 , PPC_INS_VMRGLW = 1312 , PPC_INS_VMRGOW = 1313 , PPC_INS_VMSUMMBM = 1314 , PPC_INS_VMSUMSHM = 1315 , PPC_INS_VMSUMSHS = 1316 , PPC_INS_VMSUMUBM = 1317 , PPC_INS_VMSUMUHM = 1318 , PPC_INS_VMSUMUHS = 1319 , PPC_INS_VMUL10CUQ = 1320 , PPC_INS_VMUL10ECUQ = 1321 , PPC_INS_VMUL10EUQ = 1322 , PPC_INS_VMUL10UQ = 1323 , PPC_INS_VMULESB = 1324 , PPC_INS_VMULESH = 1325 , PPC_INS_VMULESW = 1326 , PPC_INS_VMULEUB = 1327 , PPC_INS_VMULEUH = 1328 , PPC_INS_VMULEUW = 1329 , PPC_INS_VMULOSB = 1330 , PPC_INS_VMULOSH = 1331 , PPC_INS_VMULOSW = 1332 , PPC_INS_VMULOUB = 1333 , PPC_INS_VMULOUH = 1334 , PPC_INS_VMULOUW = 1335 , PPC_INS_VMULUWM = 1336 , PPC_INS_VNAND = 1337 , PPC_INS_VNCIPHER = 1338 , PPC_INS_VNCIPHERLAST = 1339 , PPC_INS_VNEGD = 1340 , PPC_INS_VNEGW = 1341 , PPC_INS_VNMSUBFP = 1342 , PPC_INS_VNOR = 1343 , PPC_INS_VNOT = 1344 , PPC_INS_VOR = 1345 , PPC_INS_VORC = 1346 , PPC_INS_VPERM = 1347 , PPC_INS_VPERMR = 1348 , PPC_INS_VPERMXOR = 1349 , PPC_INS_VPKPX = 1350 , PPC_INS_VPKSDSS = 1351 , PPC_INS_VPKSDUS = 1352 , PPC_INS_VPKSHSS = 1353 , PPC_INS_VPKSHUS = 1354 , PPC_INS_VPKSWSS = 1355 , PPC_INS_VPKSWUS = 1356 , PPC_INS_VPKUDUM = 1357 , PPC_INS_VPKUDUS = 1358 , PPC_INS_VPKUHUM = 1359 , PPC_INS_VPKUHUS = 1360 , PPC_INS_VPKUWUM = 1361 , PPC_INS_VPKUWUS = 1362 , PPC_INS_VPMSUMB = 1363 , PPC_INS_VPMSUMD = 1364 , PPC_INS_VPMSUMH = 1365 , PPC_INS_VPMSUMW = 1366 , PPC_INS_VPOPCNTB = 1367 , PPC_INS_VPOPCNTD = 1368 , PPC_INS_VPOPCNTH = 1369 , PPC_INS_VPOPCNTW = 1370 , PPC_INS_VPRTYBD = 1371 , PPC_INS_VPRTYBQ = 1372 , PPC_INS_VPRTYBW = 1373 , PPC_INS_VREFP = 1374 , PPC_INS_VRFIM = 1375 , PPC_INS_VRFIN = 1376 , PPC_INS_VRFIP = 1377 , PPC_INS_VRFIZ = 1378 , PPC_INS_VRLB = 1379 , PPC_INS_VRLD = 1380 , PPC_INS_VRLDMI = 1381 , PPC_INS_VRLDNM = 1382 , PPC_INS_VRLH = 1383 , PPC_INS_VRLW = 1384 , PPC_INS_VRLWMI = 1385 , PPC_INS_VRLWNM = 1386 , PPC_INS_VRSQRTEFP = 1387 , PPC_INS_VSBOX = 1388 , PPC_INS_VSEL = 1389 , PPC_INS_VSHASIGMAD = 1390 , PPC_INS_VSHASIGMAW = 1391 , PPC_INS_VSL = 1392 , PPC_INS_VSLB = 1393 , PPC_INS_VSLD = 1394 , PPC_INS_VSLDOI = 1395 , PPC_INS_VSLH = 1396 , PPC_INS_VSLO = 1397 , PPC_INS_VSLV = 1398 , PPC_INS_VSLW = 1399 , PPC_INS_VSPLTB = 1400 , PPC_INS_VSPLTH = 1401 , PPC_INS_VSPLTISB = 1402 , PPC_INS_VSPLTISH = 1403 , PPC_INS_VSPLTISW = 1404 , PPC_INS_VSPLTW = 1405 , PPC_INS_VSR = 1406 , PPC_INS_VSRAB = 1407 , PPC_INS_VSRAD = 1408 , PPC_INS_VSRAH = 1409 , PPC_INS_VSRAW = 1410 , PPC_INS_VSRB = 1411 , PPC_INS_VSRD = 1412 , PPC_INS_VSRH = 1413 , PPC_INS_VSRO = 1414 , PPC_INS_VSRV = 1415 , PPC_INS_VSRW = 1416 , PPC_INS_VSUBCUQ = 1417 , PPC_INS_VSUBCUW = 1418 , PPC_INS_VSUBECUQ = 1419 , PPC_INS_VSUBEUQM = 1420 , PPC_INS_VSUBFP = 1421 , PPC_INS_VSUBSBS = 1422 , PPC_INS_VSUBSHS = 1423 , PPC_INS_VSUBSWS = 1424 , PPC_INS_VSUBUBM = 1425 , PPC_INS_VSUBUBS = 1426 , PPC_INS_VSUBUDM = 1427 , PPC_INS_VSUBUHM = 1428 , PPC_INS_VSUBUHS = 1429 , PPC_INS_VSUBUQM = 1430 , PPC_INS_VSUBUWM = 1431 , PPC_INS_VSUBUWS = 1432 , PPC_INS_VSUM2SWS = 1433 , PPC_INS_VSUM4SBS = 1434 , PPC_INS_VSUM4SHS = 1435 , PPC_INS_VSUM4UBS = 1436 , PPC_INS_VSUMSWS = 1437 , PPC_INS_VUPKHPX = 1438 , PPC_INS_VUPKHSB = 1439 , PPC_INS_VUPKHSH = 1440 , PPC_INS_VUPKHSW = 1441 , PPC_INS_VUPKLPX = 1442 , PPC_INS_VUPKLSB = 1443 , PPC_INS_VUPKLSH = 1444 , PPC_INS_VUPKLSW = 1445 , PPC_INS_VXOR = 1446 , PPC_INS_WAIT = 1447 , PPC_INS_WAITIMPL = 1448 , PPC_INS_WAITRSV = 1449 , PPC_INS_WRTEE = 1450 , PPC_INS_WRTEEI = 1451 , PPC_INS_XNOP = 1452 , PPC_INS_XOR = 1453 , PPC_INS_XORI = 1454 , PPC_INS_XORIS = 1455 , PPC_INS_XSABSDP = 1456 , PPC_INS_XSABSQP = 1457 , PPC_INS_XSADDDP = 1458 , PPC_INS_XSADDQP = 1459 , PPC_INS_XSADDQPO = 1460 , PPC_INS_XSADDSP = 1461 , PPC_INS_XSCMPEQDP = 1462 , PPC_INS_XSCMPEXPDP = 1463 , PPC_INS_XSCMPEXPQP = 1464 , PPC_INS_XSCMPGEDP = 1465 , PPC_INS_XSCMPGTDP = 1466 , PPC_INS_XSCMPODP = 1467 , PPC_INS_XSCMPOQP = 1468 , PPC_INS_XSCMPUDP = 1469 , PPC_INS_XSCMPUQP = 1470 , PPC_INS_XSCPSGNDP = 1471 , PPC_INS_XSCPSGNQP = 1472 , PPC_INS_XSCVDPHP = 1473 , PPC_INS_XSCVDPQP = 1474 , PPC_INS_XSCVDPSP = 1475 , PPC_INS_XSCVDPSPN = 1476 , PPC_INS_XSCVDPSXDS = 1477 , PPC_INS_XSCVDPSXWS = 1478 , PPC_INS_XSCVDPUXDS = 1479 , PPC_INS_XSCVDPUXWS = 1480 , PPC_INS_XSCVHPDP = 1481 , PPC_INS_XSCVQPDP = 1482 , PPC_INS_XSCVQPDPO = 1483 , PPC_INS_XSCVQPSDZ = 1484 , PPC_INS_XSCVQPSWZ = 1485 , PPC_INS_XSCVQPUDZ = 1486 , PPC_INS_XSCVQPUWZ = 1487 , PPC_INS_XSCVSDQP = 1488 , PPC_INS_XSCVSPDP = 1489 , PPC_INS_XSCVSPDPN = 1490 , PPC_INS_XSCVSXDDP = 1491 , PPC_INS_XSCVSXDSP = 1492 , PPC_INS_XSCVUDQP = 1493 , PPC_INS_XSCVUXDDP = 1494 , PPC_INS_XSCVUXDSP = 1495 , PPC_INS_XSDIVDP = 1496 , PPC_INS_XSDIVQP = 1497 , PPC_INS_XSDIVQPO = 1498 , PPC_INS_XSDIVSP = 1499 , PPC_INS_XSIEXPDP = 1500 , PPC_INS_XSIEXPQP = 1501 , PPC_INS_XSMADDADP = 1502 , PPC_INS_XSMADDASP = 1503 , PPC_INS_XSMADDMDP = 1504 , PPC_INS_XSMADDMSP = 1505 , PPC_INS_XSMADDQP = 1506 , PPC_INS_XSMADDQPO = 1507 , PPC_INS_XSMAXCDP = 1508 , PPC_INS_XSMAXDP = 1509 , PPC_INS_XSMAXJDP = 1510 , PPC_INS_XSMINCDP = 1511 , PPC_INS_XSMINDP = 1512 , PPC_INS_XSMINJDP = 1513 , PPC_INS_XSMSUBADP = 1514 , PPC_INS_XSMSUBASP = 1515 , PPC_INS_XSMSUBMDP = 1516 , PPC_INS_XSMSUBMSP = 1517 , PPC_INS_XSMSUBQP = 1518 , PPC_INS_XSMSUBQPO = 1519 , PPC_INS_XSMULDP = 1520 , PPC_INS_XSMULQP = 1521 , PPC_INS_XSMULQPO = 1522 , PPC_INS_XSMULSP = 1523 , PPC_INS_XSNABSDP = 1524 , PPC_INS_XSNABSQP = 1525 , PPC_INS_XSNEGDP = 1526 , PPC_INS_XSNEGQP = 1527 , PPC_INS_XSNMADDADP = 1528 , PPC_INS_XSNMADDASP = 1529 , PPC_INS_XSNMADDMDP = 1530 , PPC_INS_XSNMADDMSP = 1531 , PPC_INS_XSNMADDQP = 1532 , PPC_INS_XSNMADDQPO = 1533 , PPC_INS_XSNMSUBADP = 1534 , PPC_INS_XSNMSUBASP = 1535 , PPC_INS_XSNMSUBMDP = 1536 , PPC_INS_XSNMSUBMSP = 1537 , PPC_INS_XSNMSUBQP = 1538 , PPC_INS_XSNMSUBQPO = 1539 , PPC_INS_XSRDPI = 1540 , PPC_INS_XSRDPIC = 1541 , PPC_INS_XSRDPIM = 1542 , PPC_INS_XSRDPIP = 1543 , PPC_INS_XSRDPIZ = 1544 , PPC_INS_XSREDP = 1545 , PPC_INS_XSRESP = 1546 , PPC_INS_XSRQPI = 1547 , PPC_INS_XSRQPIX = 1548 , PPC_INS_XSRQPXP = 1549 , PPC_INS_XSRSP = 1550 , PPC_INS_XSRSQRTEDP = 1551 , PPC_INS_XSRSQRTESP = 1552 , PPC_INS_XSSQRTDP = 1553 , PPC_INS_XSSQRTQP = 1554 , PPC_INS_XSSQRTQPO = 1555 , PPC_INS_XSSQRTSP = 1556 , PPC_INS_XSSUBDP = 1557 , PPC_INS_XSSUBQP = 1558 , PPC_INS_XSSUBQPO = 1559 , PPC_INS_XSSUBSP = 1560 , PPC_INS_XSTDIVDP = 1561 , PPC_INS_XSTSQRTDP = 1562 , PPC_INS_XSTSTDCDP = 1563 , PPC_INS_XSTSTDCQP = 1564 , PPC_INS_XSTSTDCSP = 1565 , PPC_INS_XSXEXPDP = 1566 , PPC_INS_XSXEXPQP = 1567 , PPC_INS_XSXSIGDP = 1568 , PPC_INS_XSXSIGQP = 1569 , PPC_INS_XVABSDP = 1570 , PPC_INS_XVABSSP = 1571 , PPC_INS_XVADDDP = 1572 , PPC_INS_XVADDSP = 1573 , PPC_INS_XVCMPEQDP = 1574 , PPC_INS_XVCMPEQSP = 1575 , PPC_INS_XVCMPGEDP = 1576 , PPC_INS_XVCMPGESP = 1577 , PPC_INS_XVCMPGTDP = 1578 , PPC_INS_XVCMPGTSP = 1579 , PPC_INS_XVCPSGNDP = 1580 , PPC_INS_XVCPSGNSP = 1581 , PPC_INS_XVCVDPSP = 1582 , PPC_INS_XVCVDPSXDS = 1583 , PPC_INS_XVCVDPSXWS = 1584 , PPC_INS_XVCVDPUXDS = 1585 , PPC_INS_XVCVDPUXWS = 1586 , PPC_INS_XVCVHPSP = 1587 , PPC_INS_XVCVSPDP = 1588 , PPC_INS_XVCVSPHP = 1589 , PPC_INS_XVCVSPSXDS = 1590 , PPC_INS_XVCVSPSXWS = 1591 , PPC_INS_XVCVSPUXDS = 1592 , PPC_INS_XVCVSPUXWS = 1593 , PPC_INS_XVCVSXDDP = 1594 , PPC_INS_XVCVSXDSP = 1595 , PPC_INS_XVCVSXWDP = 1596 , PPC_INS_XVCVSXWSP = 1597 , PPC_INS_XVCVUXDDP = 1598 , PPC_INS_XVCVUXDSP = 1599 , PPC_INS_XVCVUXWDP = 1600 , PPC_INS_XVCVUXWSP = 1601 , PPC_INS_XVDIVDP = 1602 , PPC_INS_XVDIVSP = 1603 , PPC_INS_XVIEXPDP = 1604 , PPC_INS_XVIEXPSP = 1605 , PPC_INS_XVMADDADP = 1606 , PPC_INS_XVMADDASP = 1607 , PPC_INS_XVMADDMDP = 1608 , PPC_INS_XVMADDMSP = 1609 , PPC_INS_XVMAXDP = 1610 , PPC_INS_XVMAXSP = 1611 , PPC_INS_XVMINDP = 1612 , PPC_INS_XVMINSP = 1613 , PPC_INS_XVMOVDP = 1614 , PPC_INS_XVMOVSP = 1615 , PPC_INS_XVMSUBADP = 1616 , PPC_INS_XVMSUBASP = 1617 , PPC_INS_XVMSUBMDP = 1618 , PPC_INS_XVMSUBMSP = 1619 , PPC_INS_XVMULDP = 1620 , PPC_INS_XVMULSP = 1621 , PPC_INS_XVNABSDP = 1622 , PPC_INS_XVNABSSP = 1623 , PPC_INS_XVNEGDP = 1624 , PPC_INS_XVNEGSP = 1625 , PPC_INS_XVNMADDADP = 1626 , PPC_INS_XVNMADDASP = 1627 , PPC_INS_XVNMADDMDP = 1628 , PPC_INS_XVNMADDMSP = 1629 , PPC_INS_XVNMSUBADP = 1630 , PPC_INS_XVNMSUBASP = 1631 , PPC_INS_XVNMSUBMDP = 1632 , PPC_INS_XVNMSUBMSP = 1633 , PPC_INS_XVRDPI = 1634 , PPC_INS_XVRDPIC = 1635 , PPC_INS_XVRDPIM = 1636 , PPC_INS_XVRDPIP = 1637 , PPC_INS_XVRDPIZ = 1638 , PPC_INS_XVREDP = 1639 , PPC_INS_XVRESP = 1640 , PPC_INS_XVRSPI = 1641 , PPC_INS_XVRSPIC = 1642 , PPC_INS_XVRSPIM = 1643 , PPC_INS_XVRSPIP = 1644 , PPC_INS_XVRSPIZ = 1645 , PPC_INS_XVRSQRTEDP = 1646 , PPC_INS_XVRSQRTESP = 1647 , PPC_INS_XVSQRTDP = 1648 , PPC_INS_XVSQRTSP = 1649 , PPC_INS_XVSUBDP = 1650 , PPC_INS_XVSUBSP = 1651 , PPC_INS_XVTDIVDP = 1652 , PPC_INS_XVTDIVSP = 1653 , PPC_INS_XVTSQRTDP = 1654 , PPC_INS_XVTSQRTSP = 1655 , PPC_INS_XVTSTDCDP = 1656 , PPC_INS_XVTSTDCSP = 1657 , PPC_INS_XVXEXPDP = 1658 , PPC_INS_XVXEXPSP = 1659 , PPC_INS_XVXSIGDP = 1660 , PPC_INS_XVXSIGSP = 1661 , PPC_INS_XXBRD = 1662 , PPC_INS_XXBRH = 1663 , PPC_INS_XXBRQ = 1664 , PPC_INS_XXBRW = 1665 , PPC_INS_XXEXTRACTUW = 1666 , PPC_INS_XXINSERTW = 1667 , PPC_INS_XXLAND = 1668 , PPC_INS_XXLANDC = 1669 , PPC_INS_XXLEQV = 1670 , PPC_INS_XXLNAND = 1671 , PPC_INS_XXLNOR = 1672 , PPC_INS_XXLOR = 1673 , PPC_INS_XXLORC = 1674 , PPC_INS_XXLXOR = 1675 , PPC_INS_XXMRGHD = 1676 , PPC_INS_XXMRGHW = 1677 , PPC_INS_XXMRGLD = 1678 , PPC_INS_XXMRGLW = 1679 , PPC_INS_XXPERM = 1680 , PPC_INS_XXPERMDI = 1681 , PPC_INS_XXPERMR = 1682 , PPC_INS_XXSEL = 1683 , PPC_INS_XXSLDWI = 1684 , PPC_INS_XXSPLTD = 1685 , PPC_INS_XXSPLTIB = 1686 , PPC_INS_XXSPLTW = 1687 , PPC_INS_XXSWAPD = 1688 , PPC_INS_DCBZ_L = 1689 , PPC_INS_PSQ_L = 1690 , PPC_INS_PSQ_LU = 1691 , PPC_INS_PSQ_LUX = 1692 , PPC_INS_PSQ_LX = 1693 , PPC_INS_PSQ_ST = 1694 , PPC_INS_PSQ_STU = 1695 , PPC_INS_PSQ_STUX = 1696 , PPC_INS_PSQ_STX = 1697 , PPC_INS_PS_ABS = 1698 , PPC_INS_PS_ADD = 1699 , PPC_INS_PS_CMPO0 = 1700 , PPC_INS_PS_CMPO1 = 1701 , PPC_INS_PS_CMPU0 = 1702 , PPC_INS_PS_CMPU1 = 1703 , PPC_INS_PS_DIV = 1704 , PPC_INS_PS_MADD = 1705 , PPC_INS_PS_MADDS0 = 1706 , PPC_INS_PS_MADDS1 = 1707 , PPC_INS_PS_MERGE00 = 1708 , PPC_INS_PS_MERGE01 = 1709 , PPC_INS_PS_MERGE10 = 1710 , PPC_INS_PS_MERGE11 = 1711 , PPC_INS_PS_MR = 1712 , PPC_INS_PS_MSUB = 1713 , PPC_INS_PS_MUL = 1714 , PPC_INS_PS_MULS0 = 1715 , PPC_INS_PS_MULS1 = 1716 , PPC_INS_PS_NABS = 1717 , PPC_INS_PS_NEG = 1718 , PPC_INS_PS_NMADD = 1719 , PPC_INS_PS_NMSUB = 1720 , PPC_INS_PS_RES = 1721 , PPC_INS_PS_RSQRTE = 1722 , PPC_INS_PS_SEL = 1723 , PPC_INS_PS_SUB = 1724 , PPC_INS_PS_SUM0 = 1725 , PPC_INS_PS_SUM1 = 1726 , PPC_INS_ENDING = 1727 , } # [repr (u32)] # [doc = " Group of PPC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn_group { # [doc = "< = CS_GRP_INVALID"] PPC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] PPC_GRP_JUMP = 1 , PPC_GRP_ALTIVEC = 128 , PPC_GRP_MODE32 = 129 , PPC_GRP_MODE64 = 130 , PPC_GRP_BOOKE = 131 , PPC_GRP_NOTBOOKE = 132 , PPC_GRP_SPE = 133 , PPC_GRP_VSX = 134 , PPC_GRP_E500 = 135 , PPC_GRP_PPC4XX = 136 , PPC_GRP_PPC6XX = 137 , PPC_GRP_ICBT = 138 , PPC_GRP_P8ALTIVEC = 139 , PPC_GRP_P8VECTOR = 140 , PPC_GRP_QPX = 141 , PPC_GRP_PS = 142 , PPC_GRP_ENDING = 143 , } # [repr (u32)] # [doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_cc { # [doc = "< invalid CC (default)"] SPARC_CC_INVALID = 0 , # [doc = "< Always"] SPARC_CC_ICC_A = 264 , # [doc = "< Never"] SPARC_CC_ICC_N = 256 , # [doc = "< Not Equal"] SPARC_CC_ICC_NE = 265 , # [doc = "< Equal"] SPARC_CC_ICC_E = 257 , # [doc = "< Greater"] SPARC_CC_ICC_G = 266 , # [doc = "< Less or Equal"] SPARC_CC_ICC_LE = 258 , # [doc = "< Greater or Equal"] SPARC_CC_ICC_GE = 267 , # [doc = "< Less"] SPARC_CC_ICC_L = 259 , # [doc = "< Greater Unsigned"] SPARC_CC_ICC_GU = 268 , # [doc = "< Less or Equal Unsigned"] SPARC_CC_ICC_LEU = 260 , # [doc = "< Carry Clear/Great or Equal Unsigned"] SPARC_CC_ICC_CC = 269 , # [doc = "< Carry Set/Less Unsigned"] SPARC_CC_ICC_CS = 261 , # [doc = "< Positive"] SPARC_CC_ICC_POS = 270 , # [doc = "< Negative"] SPARC_CC_ICC_NEG = 262 , # [doc = "< Overflow Clear"] SPARC_CC_ICC_VC = 271 , # [doc = "< Overflow Set"] SPARC_CC_ICC_VS = 263 , # [doc = "< Always"] SPARC_CC_FCC_A = 280 , # [doc = "< Never"] SPARC_CC_FCC_N = 272 , # [doc = "< Unordered"] SPARC_CC_FCC_U = 279 , # [doc = "< Greater"] SPARC_CC_FCC_G = 278 , # [doc = "< Unordered or Greater"] SPARC_CC_FCC_UG = 277 , # [doc = "< Less"] SPARC_CC_FCC_L = 276 , # [doc = "< Unordered or Less"] SPARC_CC_FCC_UL = 275 , # [doc = "< Less or Greater"] SPARC_CC_FCC_LG = 274 , # [doc = "< Not Equal"] SPARC_CC_FCC_NE = 273 , # [doc = "< Equal"] SPARC_CC_FCC_E = 281 , # [doc = "< Unordered or Equal"] SPARC_CC_FCC_UE = 282 , # [doc = "< Greater or Equal"] SPARC_CC_FCC_GE = 283 , # [doc = "< Unordered or Greater or Equal"] SPARC_CC_FCC_UGE = 284 , # [doc = "< Less or Equal"] SPARC_CC_FCC_LE = 285 , # [doc = "< Unordered or Less or Equal"] SPARC_CC_FCC_ULE = 286 , # [doc = "< Ordered"] SPARC_CC_FCC_O = 287 , } # [repr (u32)] # [doc = " Branch hint"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_hint { # [doc = "< no hint"] SPARC_HINT_INVALID = 0 , # [doc = "< annul delay slot instruction"] SPARC_HINT_A = 1 , # [doc = "< branch taken"] SPARC_HINT_PT = 2 , # [doc = "< branch NOT taken"] SPARC_HINT_PN = 4 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SPARC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SPARC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SPARC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SPARC_OP_MEM = 3 , } impl sparc_reg { pub const SPARC_REG_O6 : sparc_reg = sparc_reg :: SPARC_REG_SP ; } impl sparc_reg { pub const SPARC_REG_I6 : sparc_reg = sparc_reg :: SPARC_REG_FP ; } # [repr (u32)] # [doc = " SPARC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_reg { SPARC_REG_INVALID = 0 , SPARC_REG_F0 = 1 , SPARC_REG_F1 = 2 , SPARC_REG_F2 = 3 , SPARC_REG_F3 = 4 , SPARC_REG_F4 = 5 , SPARC_REG_F5 = 6 , SPARC_REG_F6 = 7 , SPARC_REG_F7 = 8 , SPARC_REG_F8 = 9 , SPARC_REG_F9 = 10 , SPARC_REG_F10 = 11 , SPARC_REG_F11 = 12 , SPARC_REG_F12 = 13 , SPARC_REG_F13 = 14 , SPARC_REG_F14 = 15 , SPARC_REG_F15 = 16 , SPARC_REG_F16 = 17 , SPARC_REG_F17 = 18 , SPARC_REG_F18 = 19 , SPARC_REG_F19 = 20 , SPARC_REG_F20 = 21 , SPARC_REG_F21 = 22 , SPARC_REG_F22 = 23 , SPARC_REG_F23 = 24 , SPARC_REG_F24 = 25 , SPARC_REG_F25 = 26 , SPARC_REG_F26 = 27 , SPARC_REG_F27 = 28 , SPARC_REG_F28 = 29 , SPARC_REG_F29 = 30 , SPARC_REG_F30 = 31 , SPARC_REG_F31 = 32 , SPARC_REG_F32 = 33 , SPARC_REG_F34 = 34 , SPARC_REG_F36 = 35 , SPARC_REG_F38 = 36 , SPARC_REG_F40 = 37 , SPARC_REG_F42 = 38 , SPARC_REG_F44 = 39 , SPARC_REG_F46 = 40 , SPARC_REG_F48 = 41 , SPARC_REG_F50 = 42 , SPARC_REG_F52 = 43 , SPARC_REG_F54 = 44 , SPARC_REG_F56 = 45 , SPARC_REG_F58 = 46 , SPARC_REG_F60 = 47 , SPARC_REG_F62 = 48 , SPARC_REG_FCC0 = 49 , SPARC_REG_FCC1 = 50 , SPARC_REG_FCC2 = 51 , SPARC_REG_FCC3 = 52 , SPARC_REG_FP = 53 , SPARC_REG_G0 = 54 , SPARC_REG_G1 = 55 , SPARC_REG_G2 = 56 , SPARC_REG_G3 = 57 , SPARC_REG_G4 = 58 , SPARC_REG_G5 = 59 , SPARC_REG_G6 = 60 , SPARC_REG_G7 = 61 , SPARC_REG_I0 = 62 , SPARC_REG_I1 = 63 , SPARC_REG_I2 = 64 , SPARC_REG_I3 = 65 , SPARC_REG_I4 = 66 , SPARC_REG_I5 = 67 , SPARC_REG_I7 = 68 , SPARC_REG_ICC = 69 , SPARC_REG_L0 = 70 , SPARC_REG_L1 = 71 , SPARC_REG_L2 = 72 , SPARC_REG_L3 = 73 , SPARC_REG_L4 = 74 , SPARC_REG_L5 = 75 , SPARC_REG_L6 = 76 , SPARC_REG_L7 = 77 , SPARC_REG_O0 = 78 , SPARC_REG_O1 = 79 , SPARC_REG_O2 = 80 , SPARC_REG_O3 = 81 , SPARC_REG_O4 = 82 , SPARC_REG_O5 = 83 , SPARC_REG_O7 = 84 , SPARC_REG_SP = 85 , SPARC_REG_Y = 86 , SPARC_REG_XCC = 87 , SPARC_REG_ENDING = 88 , } # [doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sparc_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sparc_op_mem"] [:: std :: mem :: size_of :: < sparc_op_mem > () - 8usize] ; ["Alignment of sparc_op_mem"] [:: std :: mem :: align_of :: < sparc_op_mem > () - 4usize] ; ["Offset of field: sparc_op_mem::base"] [:: std :: mem :: offset_of ! (sparc_op_mem , base) - 0usize] ; ["Offset of field: sparc_op_mem::index"] [:: std :: mem :: offset_of ! (sparc_op_mem , index) - 1usize] ; ["Offset of field: sparc_op_mem::disp"] [:: std :: mem :: offset_of ! (sparc_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc_op { # [doc = "< operand type"] pub type_ : sparc_op_type , pub __bindgen_anon_1 : cs_sparc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sparc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sparc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sparc_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op"] [:: std :: mem :: size_of :: < cs_sparc_op > () - 16usize] ; ["Alignment of cs_sparc_op"] [:: std :: mem :: align_of :: < cs_sparc_op > () - 8usize] ; ["Offset of field: cs_sparc_op::type_"] [:: std :: mem :: offset_of ! (cs_sparc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc { # [doc = "< code condition for this insn"] pub cc : sparc_cc , # [doc = "< branch hint: encoding as bitwise OR of sparc_hint."] pub hint : sparc_hint , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sparc_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc"] [:: std :: mem :: size_of :: < cs_sparc > () - 80usize] ; ["Alignment of cs_sparc"] [:: std :: mem :: align_of :: < cs_sparc > () - 8usize] ; ["Offset of field: cs_sparc::cc"] [:: std :: mem :: offset_of ! (cs_sparc , cc) - 0usize] ; ["Offset of field: cs_sparc::hint"] [:: std :: mem :: offset_of ! (cs_sparc , hint) - 4usize] ; ["Offset of field: cs_sparc::op_count"] [:: std :: mem :: offset_of ! (cs_sparc , op_count) - 8usize] ; ["Offset of field: cs_sparc::operands"] [:: std :: mem :: offset_of ! (cs_sparc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . hint , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SPARC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn { SPARC_INS_INVALID = 0 , SPARC_INS_ADDCC = 1 , SPARC_INS_ADDX = 2 , SPARC_INS_ADDXCC = 3 , SPARC_INS_ADDXC = 4 , SPARC_INS_ADDXCCC = 5 , SPARC_INS_ADD = 6 , SPARC_INS_ALIGNADDR = 7 , SPARC_INS_ALIGNADDRL = 8 , SPARC_INS_ANDCC = 9 , SPARC_INS_ANDNCC = 10 , SPARC_INS_ANDN = 11 , SPARC_INS_AND = 12 , SPARC_INS_ARRAY16 = 13 , SPARC_INS_ARRAY32 = 14 , SPARC_INS_ARRAY8 = 15 , SPARC_INS_B = 16 , SPARC_INS_JMP = 17 , SPARC_INS_BMASK = 18 , SPARC_INS_FB = 19 , SPARC_INS_BRGEZ = 20 , SPARC_INS_BRGZ = 21 , SPARC_INS_BRLEZ = 22 , SPARC_INS_BRLZ = 23 , SPARC_INS_BRNZ = 24 , SPARC_INS_BRZ = 25 , SPARC_INS_BSHUFFLE = 26 , SPARC_INS_CALL = 27 , SPARC_INS_CASX = 28 , SPARC_INS_CAS = 29 , SPARC_INS_CMASK16 = 30 , SPARC_INS_CMASK32 = 31 , SPARC_INS_CMASK8 = 32 , SPARC_INS_CMP = 33 , SPARC_INS_EDGE16 = 34 , SPARC_INS_EDGE16L = 35 , SPARC_INS_EDGE16LN = 36 , SPARC_INS_EDGE16N = 37 , SPARC_INS_EDGE32 = 38 , SPARC_INS_EDGE32L = 39 , SPARC_INS_EDGE32LN = 40 , SPARC_INS_EDGE32N = 41 , SPARC_INS_EDGE8 = 42 , SPARC_INS_EDGE8L = 43 , SPARC_INS_EDGE8LN = 44 , SPARC_INS_EDGE8N = 45 , SPARC_INS_FABSD = 46 , SPARC_INS_FABSQ = 47 , SPARC_INS_FABSS = 48 , SPARC_INS_FADDD = 49 , SPARC_INS_FADDQ = 50 , SPARC_INS_FADDS = 51 , SPARC_INS_FALIGNDATA = 52 , SPARC_INS_FAND = 53 , SPARC_INS_FANDNOT1 = 54 , SPARC_INS_FANDNOT1S = 55 , SPARC_INS_FANDNOT2 = 56 , SPARC_INS_FANDNOT2S = 57 , SPARC_INS_FANDS = 58 , SPARC_INS_FCHKSM16 = 59 , SPARC_INS_FCMPD = 60 , SPARC_INS_FCMPEQ16 = 61 , SPARC_INS_FCMPEQ32 = 62 , SPARC_INS_FCMPGT16 = 63 , SPARC_INS_FCMPGT32 = 64 , SPARC_INS_FCMPLE16 = 65 , SPARC_INS_FCMPLE32 = 66 , SPARC_INS_FCMPNE16 = 67 , SPARC_INS_FCMPNE32 = 68 , SPARC_INS_FCMPQ = 69 , SPARC_INS_FCMPS = 70 , SPARC_INS_FDIVD = 71 , SPARC_INS_FDIVQ = 72 , SPARC_INS_FDIVS = 73 , SPARC_INS_FDMULQ = 74 , SPARC_INS_FDTOI = 75 , SPARC_INS_FDTOQ = 76 , SPARC_INS_FDTOS = 77 , SPARC_INS_FDTOX = 78 , SPARC_INS_FEXPAND = 79 , SPARC_INS_FHADDD = 80 , SPARC_INS_FHADDS = 81 , SPARC_INS_FHSUBD = 82 , SPARC_INS_FHSUBS = 83 , SPARC_INS_FITOD = 84 , SPARC_INS_FITOQ = 85 , SPARC_INS_FITOS = 86 , SPARC_INS_FLCMPD = 87 , SPARC_INS_FLCMPS = 88 , SPARC_INS_FLUSHW = 89 , SPARC_INS_FMEAN16 = 90 , SPARC_INS_FMOVD = 91 , SPARC_INS_FMOVQ = 92 , SPARC_INS_FMOVRDGEZ = 93 , SPARC_INS_FMOVRQGEZ = 94 , SPARC_INS_FMOVRSGEZ = 95 , SPARC_INS_FMOVRDGZ = 96 , SPARC_INS_FMOVRQGZ = 97 , SPARC_INS_FMOVRSGZ = 98 , SPARC_INS_FMOVRDLEZ = 99 , SPARC_INS_FMOVRQLEZ = 100 , SPARC_INS_FMOVRSLEZ = 101 , SPARC_INS_FMOVRDLZ = 102 , SPARC_INS_FMOVRQLZ = 103 , SPARC_INS_FMOVRSLZ = 104 , SPARC_INS_FMOVRDNZ = 105 , SPARC_INS_FMOVRQNZ = 106 , SPARC_INS_FMOVRSNZ = 107 , SPARC_INS_FMOVRDZ = 108 , SPARC_INS_FMOVRQZ = 109 , SPARC_INS_FMOVRSZ = 110 , SPARC_INS_FMOVS = 111 , SPARC_INS_FMUL8SUX16 = 112 , SPARC_INS_FMUL8ULX16 = 113 , SPARC_INS_FMUL8X16 = 114 , SPARC_INS_FMUL8X16AL = 115 , SPARC_INS_FMUL8X16AU = 116 , SPARC_INS_FMULD = 117 , SPARC_INS_FMULD8SUX16 = 118 , SPARC_INS_FMULD8ULX16 = 119 , SPARC_INS_FMULQ = 120 , SPARC_INS_FMULS = 121 , SPARC_INS_FNADDD = 122 , SPARC_INS_FNADDS = 123 , SPARC_INS_FNAND = 124 , SPARC_INS_FNANDS = 125 , SPARC_INS_FNEGD = 126 , SPARC_INS_FNEGQ = 127 , SPARC_INS_FNEGS = 128 , SPARC_INS_FNHADDD = 129 , SPARC_INS_FNHADDS = 130 , SPARC_INS_FNOR = 131 , SPARC_INS_FNORS = 132 , SPARC_INS_FNOT1 = 133 , SPARC_INS_FNOT1S = 134 , SPARC_INS_FNOT2 = 135 , SPARC_INS_FNOT2S = 136 , SPARC_INS_FONE = 137 , SPARC_INS_FONES = 138 , SPARC_INS_FOR = 139 , SPARC_INS_FORNOT1 = 140 , SPARC_INS_FORNOT1S = 141 , SPARC_INS_FORNOT2 = 142 , SPARC_INS_FORNOT2S = 143 , SPARC_INS_FORS = 144 , SPARC_INS_FPACK16 = 145 , SPARC_INS_FPACK32 = 146 , SPARC_INS_FPACKFIX = 147 , SPARC_INS_FPADD16 = 148 , SPARC_INS_FPADD16S = 149 , SPARC_INS_FPADD32 = 150 , SPARC_INS_FPADD32S = 151 , SPARC_INS_FPADD64 = 152 , SPARC_INS_FPMERGE = 153 , SPARC_INS_FPSUB16 = 154 , SPARC_INS_FPSUB16S = 155 , SPARC_INS_FPSUB32 = 156 , SPARC_INS_FPSUB32S = 157 , SPARC_INS_FQTOD = 158 , SPARC_INS_FQTOI = 159 , SPARC_INS_FQTOS = 160 , SPARC_INS_FQTOX = 161 , SPARC_INS_FSLAS16 = 162 , SPARC_INS_FSLAS32 = 163 , SPARC_INS_FSLL16 = 164 , SPARC_INS_FSLL32 = 165 , SPARC_INS_FSMULD = 166 , SPARC_INS_FSQRTD = 167 , SPARC_INS_FSQRTQ = 168 , SPARC_INS_FSQRTS = 169 , SPARC_INS_FSRA16 = 170 , SPARC_INS_FSRA32 = 171 , SPARC_INS_FSRC1 = 172 , SPARC_INS_FSRC1S = 173 , SPARC_INS_FSRC2 = 174 , SPARC_INS_FSRC2S = 175 , SPARC_INS_FSRL16 = 176 , SPARC_INS_FSRL32 = 177 , SPARC_INS_FSTOD = 178 , SPARC_INS_FSTOI = 179 , SPARC_INS_FSTOQ = 180 , SPARC_INS_FSTOX = 181 , SPARC_INS_FSUBD = 182 , SPARC_INS_FSUBQ = 183 , SPARC_INS_FSUBS = 184 , SPARC_INS_FXNOR = 185 , SPARC_INS_FXNORS = 186 , SPARC_INS_FXOR = 187 , SPARC_INS_FXORS = 188 , SPARC_INS_FXTOD = 189 , SPARC_INS_FXTOQ = 190 , SPARC_INS_FXTOS = 191 , SPARC_INS_FZERO = 192 , SPARC_INS_FZEROS = 193 , SPARC_INS_JMPL = 194 , SPARC_INS_LDD = 195 , SPARC_INS_LD = 196 , SPARC_INS_LDQ = 197 , SPARC_INS_LDSB = 198 , SPARC_INS_LDSH = 199 , SPARC_INS_LDSW = 200 , SPARC_INS_LDUB = 201 , SPARC_INS_LDUH = 202 , SPARC_INS_LDX = 203 , SPARC_INS_LZCNT = 204 , SPARC_INS_MEMBAR = 205 , SPARC_INS_MOVDTOX = 206 , SPARC_INS_MOV = 207 , SPARC_INS_MOVRGEZ = 208 , SPARC_INS_MOVRGZ = 209 , SPARC_INS_MOVRLEZ = 210 , SPARC_INS_MOVRLZ = 211 , SPARC_INS_MOVRNZ = 212 , SPARC_INS_MOVRZ = 213 , SPARC_INS_MOVSTOSW = 214 , SPARC_INS_MOVSTOUW = 215 , SPARC_INS_MULX = 216 , SPARC_INS_NOP = 217 , SPARC_INS_ORCC = 218 , SPARC_INS_ORNCC = 219 , SPARC_INS_ORN = 220 , SPARC_INS_OR = 221 , SPARC_INS_PDIST = 222 , SPARC_INS_PDISTN = 223 , SPARC_INS_POPC = 224 , SPARC_INS_RD = 225 , SPARC_INS_RESTORE = 226 , SPARC_INS_RETT = 227 , SPARC_INS_SAVE = 228 , SPARC_INS_SDIVCC = 229 , SPARC_INS_SDIVX = 230 , SPARC_INS_SDIV = 231 , SPARC_INS_SETHI = 232 , SPARC_INS_SHUTDOWN = 233 , SPARC_INS_SIAM = 234 , SPARC_INS_SLLX = 235 , SPARC_INS_SLL = 236 , SPARC_INS_SMULCC = 237 , SPARC_INS_SMUL = 238 , SPARC_INS_SRAX = 239 , SPARC_INS_SRA = 240 , SPARC_INS_SRLX = 241 , SPARC_INS_SRL = 242 , SPARC_INS_STBAR = 243 , SPARC_INS_STB = 244 , SPARC_INS_STD = 245 , SPARC_INS_ST = 246 , SPARC_INS_STH = 247 , SPARC_INS_STQ = 248 , SPARC_INS_STX = 249 , SPARC_INS_SUBCC = 250 , SPARC_INS_SUBX = 251 , SPARC_INS_SUBXCC = 252 , SPARC_INS_SUB = 253 , SPARC_INS_SWAP = 254 , SPARC_INS_TADDCCTV = 255 , SPARC_INS_TADDCC = 256 , SPARC_INS_T = 257 , SPARC_INS_TSUBCCTV = 258 , SPARC_INS_TSUBCC = 259 , SPARC_INS_UDIVCC = 260 , SPARC_INS_UDIVX = 261 , SPARC_INS_UDIV = 262 , SPARC_INS_UMULCC = 263 , SPARC_INS_UMULXHI = 264 , SPARC_INS_UMUL = 265 , SPARC_INS_UNIMP = 266 , SPARC_INS_FCMPED = 267 , SPARC_INS_FCMPEQ = 268 , SPARC_INS_FCMPES = 269 , SPARC_INS_WR = 270 , SPARC_INS_XMULX = 271 , SPARC_INS_XMULXHI = 272 , SPARC_INS_XNORCC = 273 , SPARC_INS_XNOR = 274 , SPARC_INS_XORCC = 275 , SPARC_INS_XOR = 276 , SPARC_INS_RET = 277 , SPARC_INS_RETL = 278 , SPARC_INS_ENDING = 279 , } # [repr (u32)] # [doc = " Group of SPARC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn_group { # [doc = "< = CS_GRP_INVALID"] SPARC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SPARC_GRP_JUMP = 1 , SPARC_GRP_HARDQUAD = 128 , SPARC_GRP_V9 = 129 , SPARC_GRP_VIS = 130 , SPARC_GRP_VIS2 = 131 , SPARC_GRP_VIS3 = 132 , SPARC_GRP_32BIT = 133 , SPARC_GRP_64BIT = 134 , SPARC_GRP_ENDING = 135 , } # [repr (u32)] # [doc = " Enums corresponding to SystemZ condition codes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_cc { # [doc = "< invalid CC (default)"] SYSZ_CC_INVALID = 0 , SYSZ_CC_O = 1 , SYSZ_CC_H = 2 , SYSZ_CC_NLE = 3 , SYSZ_CC_L = 4 , SYSZ_CC_NHE = 5 , SYSZ_CC_LH = 6 , SYSZ_CC_NE = 7 , SYSZ_CC_E = 8 , SYSZ_CC_NLH = 9 , SYSZ_CC_HE = 10 , SYSZ_CC_NL = 11 , SYSZ_CC_LE = 12 , SYSZ_CC_NH = 13 , SYSZ_CC_NO = 14 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SYSZ_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SYSZ_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SYSZ_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SYSZ_OP_MEM = 3 , # [doc = "< Access register operand."] SYSZ_OP_ACREG = 64 , } # [repr (u32)] # [doc = " SystemZ registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_reg { SYSZ_REG_INVALID = 0 , SYSZ_REG_0 = 1 , SYSZ_REG_1 = 2 , SYSZ_REG_2 = 3 , SYSZ_REG_3 = 4 , SYSZ_REG_4 = 5 , SYSZ_REG_5 = 6 , SYSZ_REG_6 = 7 , SYSZ_REG_7 = 8 , SYSZ_REG_8 = 9 , SYSZ_REG_9 = 10 , SYSZ_REG_10 = 11 , SYSZ_REG_11 = 12 , SYSZ_REG_12 = 13 , SYSZ_REG_13 = 14 , SYSZ_REG_14 = 15 , SYSZ_REG_15 = 16 , SYSZ_REG_CC = 17 , SYSZ_REG_F0 = 18 , SYSZ_REG_F1 = 19 , SYSZ_REG_F2 = 20 , SYSZ_REG_F3 = 21 , SYSZ_REG_F4 = 22 , SYSZ_REG_F5 = 23 , SYSZ_REG_F6 = 24 , SYSZ_REG_F7 = 25 , SYSZ_REG_F8 = 26 , SYSZ_REG_F9 = 27 , SYSZ_REG_F10 = 28 , SYSZ_REG_F11 = 29 , SYSZ_REG_F12 = 30 , SYSZ_REG_F13 = 31 , SYSZ_REG_F14 = 32 , SYSZ_REG_F15 = 33 , SYSZ_REG_R0L = 34 , SYSZ_REG_A0 = 35 , SYSZ_REG_A1 = 36 , SYSZ_REG_A2 = 37 , SYSZ_REG_A3 = 38 , SYSZ_REG_A4 = 39 , SYSZ_REG_A5 = 40 , SYSZ_REG_A6 = 41 , SYSZ_REG_A7 = 42 , SYSZ_REG_A8 = 43 , SYSZ_REG_A9 = 44 , SYSZ_REG_A10 = 45 , SYSZ_REG_A11 = 46 , SYSZ_REG_A12 = 47 , SYSZ_REG_A13 = 48 , SYSZ_REG_A14 = 49 , SYSZ_REG_A15 = 50 , SYSZ_REG_C0 = 51 , SYSZ_REG_C1 = 52 , SYSZ_REG_C2 = 53 , SYSZ_REG_C3 = 54 , SYSZ_REG_C4 = 55 , SYSZ_REG_C5 = 56 , SYSZ_REG_C6 = 57 , SYSZ_REG_C7 = 58 , SYSZ_REG_C8 = 59 , SYSZ_REG_C9 = 60 , SYSZ_REG_C10 = 61 , SYSZ_REG_C11 = 62 , SYSZ_REG_C12 = 63 , SYSZ_REG_C13 = 64 , SYSZ_REG_C14 = 65 , SYSZ_REG_C15 = 66 , SYSZ_REG_V0 = 67 , SYSZ_REG_V1 = 68 , SYSZ_REG_V2 = 69 , SYSZ_REG_V3 = 70 , SYSZ_REG_V4 = 71 , SYSZ_REG_V5 = 72 , SYSZ_REG_V6 = 73 , SYSZ_REG_V7 = 74 , SYSZ_REG_V8 = 75 , SYSZ_REG_V9 = 76 , SYSZ_REG_V10 = 77 , SYSZ_REG_V11 = 78 , SYSZ_REG_V12 = 79 , SYSZ_REG_V13 = 80 , SYSZ_REG_V14 = 81 , SYSZ_REG_V15 = 82 , SYSZ_REG_V16 = 83 , SYSZ_REG_V17 = 84 , SYSZ_REG_V18 = 85 , SYSZ_REG_V19 = 86 , SYSZ_REG_V20 = 87 , SYSZ_REG_V21 = 88 , SYSZ_REG_V22 = 89 , SYSZ_REG_V23 = 90 , SYSZ_REG_V24 = 91 , SYSZ_REG_V25 = 92 , SYSZ_REG_V26 = 93 , SYSZ_REG_V27 = 94 , SYSZ_REG_V28 = 95 , SYSZ_REG_V29 = 96 , SYSZ_REG_V30 = 97 , SYSZ_REG_V31 = 98 , SYSZ_REG_F16 = 99 , SYSZ_REG_F17 = 100 , SYSZ_REG_F18 = 101 , SYSZ_REG_F19 = 102 , SYSZ_REG_F20 = 103 , SYSZ_REG_F21 = 104 , SYSZ_REG_F22 = 105 , SYSZ_REG_F23 = 106 , SYSZ_REG_F24 = 107 , SYSZ_REG_F25 = 108 , SYSZ_REG_F26 = 109 , SYSZ_REG_F27 = 110 , SYSZ_REG_F28 = 111 , SYSZ_REG_F29 = 112 , SYSZ_REG_F30 = 113 , SYSZ_REG_F31 = 114 , SYSZ_REG_F0Q = 115 , SYSZ_REG_F4Q = 116 , SYSZ_REG_ENDING = 117 , } # [doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sysz_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< BDLAddr operand"] pub length : u64 , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sysz_op_mem"] [:: std :: mem :: size_of :: < sysz_op_mem > () - 24usize] ; ["Alignment of sysz_op_mem"] [:: std :: mem :: align_of :: < sysz_op_mem > () - 8usize] ; ["Offset of field: sysz_op_mem::base"] [:: std :: mem :: offset_of ! (sysz_op_mem , base) - 0usize] ; ["Offset of field: sysz_op_mem::index"] [:: std :: mem :: offset_of ! (sysz_op_mem , index) - 1usize] ; ["Offset of field: sysz_op_mem::length"] [:: std :: mem :: offset_of ! (sysz_op_mem , length) - 8usize] ; ["Offset of field: sysz_op_mem::disp"] [:: std :: mem :: offset_of ! (sysz_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz_op { # [doc = "< operand type"] pub type_ : sysz_op_type , pub __bindgen_anon_1 : cs_sysz_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sysz_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sysz_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sysz_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sysz_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sysz_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op"] [:: std :: mem :: size_of :: < cs_sysz_op > () - 32usize] ; ["Alignment of cs_sysz_op"] [:: std :: mem :: align_of :: < cs_sysz_op > () - 8usize] ; ["Offset of field: cs_sysz_op::type_"] [:: std :: mem :: offset_of ! (cs_sysz_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz { # [doc = "< Code condition"] pub cc : sysz_cc , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sysz_op ; 6usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz"] [:: std :: mem :: size_of :: < cs_sysz > () - 200usize] ; ["Alignment of cs_sysz"] [:: std :: mem :: align_of :: < cs_sysz > () - 8usize] ; ["Offset of field: cs_sysz::cc"] [:: std :: mem :: offset_of ! (cs_sysz , cc) - 0usize] ; ["Offset of field: cs_sysz::op_count"] [:: std :: mem :: offset_of ! (cs_sysz , op_count) - 4usize] ; ["Offset of field: cs_sysz::operands"] [:: std :: mem :: offset_of ! (cs_sysz , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SystemZ instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn { SYSZ_INS_INVALID = 0 , SYSZ_INS_A = 1 , SYSZ_INS_ADB = 2 , SYSZ_INS_ADBR = 3 , SYSZ_INS_AEB = 4 , SYSZ_INS_AEBR = 5 , SYSZ_INS_AFI = 6 , SYSZ_INS_AG = 7 , SYSZ_INS_AGF = 8 , SYSZ_INS_AGFI = 9 , SYSZ_INS_AGFR = 10 , SYSZ_INS_AGHI = 11 , SYSZ_INS_AGHIK = 12 , SYSZ_INS_AGR = 13 , SYSZ_INS_AGRK = 14 , SYSZ_INS_AGSI = 15 , SYSZ_INS_AH = 16 , SYSZ_INS_AHI = 17 , SYSZ_INS_AHIK = 18 , SYSZ_INS_AHY = 19 , SYSZ_INS_AIH = 20 , SYSZ_INS_AL = 21 , SYSZ_INS_ALC = 22 , SYSZ_INS_ALCG = 23 , SYSZ_INS_ALCGR = 24 , SYSZ_INS_ALCR = 25 , SYSZ_INS_ALFI = 26 , SYSZ_INS_ALG = 27 , SYSZ_INS_ALGF = 28 , SYSZ_INS_ALGFI = 29 , SYSZ_INS_ALGFR = 30 , SYSZ_INS_ALGHSIK = 31 , SYSZ_INS_ALGR = 32 , SYSZ_INS_ALGRK = 33 , SYSZ_INS_ALHSIK = 34 , SYSZ_INS_ALR = 35 , SYSZ_INS_ALRK = 36 , SYSZ_INS_ALY = 37 , SYSZ_INS_AR = 38 , SYSZ_INS_ARK = 39 , SYSZ_INS_ASI = 40 , SYSZ_INS_AXBR = 41 , SYSZ_INS_AY = 42 , SYSZ_INS_BCR = 43 , SYSZ_INS_BRC = 44 , SYSZ_INS_BRCL = 45 , SYSZ_INS_CGIJ = 46 , SYSZ_INS_CGRJ = 47 , SYSZ_INS_CIJ = 48 , SYSZ_INS_CLGIJ = 49 , SYSZ_INS_CLGRJ = 50 , SYSZ_INS_CLIJ = 51 , SYSZ_INS_CLRJ = 52 , SYSZ_INS_CRJ = 53 , SYSZ_INS_BER = 54 , SYSZ_INS_JE = 55 , SYSZ_INS_JGE = 56 , SYSZ_INS_LOCE = 57 , SYSZ_INS_LOCGE = 58 , SYSZ_INS_LOCGRE = 59 , SYSZ_INS_LOCRE = 60 , SYSZ_INS_STOCE = 61 , SYSZ_INS_STOCGE = 62 , SYSZ_INS_BHR = 63 , SYSZ_INS_BHER = 64 , SYSZ_INS_JHE = 65 , SYSZ_INS_JGHE = 66 , SYSZ_INS_LOCHE = 67 , SYSZ_INS_LOCGHE = 68 , SYSZ_INS_LOCGRHE = 69 , SYSZ_INS_LOCRHE = 70 , SYSZ_INS_STOCHE = 71 , SYSZ_INS_STOCGHE = 72 , SYSZ_INS_JH = 73 , SYSZ_INS_JGH = 74 , SYSZ_INS_LOCH = 75 , SYSZ_INS_LOCGH = 76 , SYSZ_INS_LOCGRH = 77 , SYSZ_INS_LOCRH = 78 , SYSZ_INS_STOCH = 79 , SYSZ_INS_STOCGH = 80 , SYSZ_INS_CGIJNLH = 81 , SYSZ_INS_CGRJNLH = 82 , SYSZ_INS_CIJNLH = 83 , SYSZ_INS_CLGIJNLH = 84 , SYSZ_INS_CLGRJNLH = 85 , SYSZ_INS_CLIJNLH = 86 , SYSZ_INS_CLRJNLH = 87 , SYSZ_INS_CRJNLH = 88 , SYSZ_INS_CGIJE = 89 , SYSZ_INS_CGRJE = 90 , SYSZ_INS_CIJE = 91 , SYSZ_INS_CLGIJE = 92 , SYSZ_INS_CLGRJE = 93 , SYSZ_INS_CLIJE = 94 , SYSZ_INS_CLRJE = 95 , SYSZ_INS_CRJE = 96 , SYSZ_INS_CGIJNLE = 97 , SYSZ_INS_CGRJNLE = 98 , SYSZ_INS_CIJNLE = 99 , SYSZ_INS_CLGIJNLE = 100 , SYSZ_INS_CLGRJNLE = 101 , SYSZ_INS_CLIJNLE = 102 , SYSZ_INS_CLRJNLE = 103 , SYSZ_INS_CRJNLE = 104 , SYSZ_INS_CGIJH = 105 , SYSZ_INS_CGRJH = 106 , SYSZ_INS_CIJH = 107 , SYSZ_INS_CLGIJH = 108 , SYSZ_INS_CLGRJH = 109 , SYSZ_INS_CLIJH = 110 , SYSZ_INS_CLRJH = 111 , SYSZ_INS_CRJH = 112 , SYSZ_INS_CGIJNL = 113 , SYSZ_INS_CGRJNL = 114 , SYSZ_INS_CIJNL = 115 , SYSZ_INS_CLGIJNL = 116 , SYSZ_INS_CLGRJNL = 117 , SYSZ_INS_CLIJNL = 118 , SYSZ_INS_CLRJNL = 119 , SYSZ_INS_CRJNL = 120 , SYSZ_INS_CGIJHE = 121 , SYSZ_INS_CGRJHE = 122 , SYSZ_INS_CIJHE = 123 , SYSZ_INS_CLGIJHE = 124 , SYSZ_INS_CLGRJHE = 125 , SYSZ_INS_CLIJHE = 126 , SYSZ_INS_CLRJHE = 127 , SYSZ_INS_CRJHE = 128 , SYSZ_INS_CGIJNHE = 129 , SYSZ_INS_CGRJNHE = 130 , SYSZ_INS_CIJNHE = 131 , SYSZ_INS_CLGIJNHE = 132 , SYSZ_INS_CLGRJNHE = 133 , SYSZ_INS_CLIJNHE = 134 , SYSZ_INS_CLRJNHE = 135 , SYSZ_INS_CRJNHE = 136 , SYSZ_INS_CGIJL = 137 , SYSZ_INS_CGRJL = 138 , SYSZ_INS_CIJL = 139 , SYSZ_INS_CLGIJL = 140 , SYSZ_INS_CLGRJL = 141 , SYSZ_INS_CLIJL = 142 , SYSZ_INS_CLRJL = 143 , SYSZ_INS_CRJL = 144 , SYSZ_INS_CGIJNH = 145 , SYSZ_INS_CGRJNH = 146 , SYSZ_INS_CIJNH = 147 , SYSZ_INS_CLGIJNH = 148 , SYSZ_INS_CLGRJNH = 149 , SYSZ_INS_CLIJNH = 150 , SYSZ_INS_CLRJNH = 151 , SYSZ_INS_CRJNH = 152 , SYSZ_INS_CGIJLE = 153 , SYSZ_INS_CGRJLE = 154 , SYSZ_INS_CIJLE = 155 , SYSZ_INS_CLGIJLE = 156 , SYSZ_INS_CLGRJLE = 157 , SYSZ_INS_CLIJLE = 158 , SYSZ_INS_CLRJLE = 159 , SYSZ_INS_CRJLE = 160 , SYSZ_INS_CGIJNE = 161 , SYSZ_INS_CGRJNE = 162 , SYSZ_INS_CIJNE = 163 , SYSZ_INS_CLGIJNE = 164 , SYSZ_INS_CLGRJNE = 165 , SYSZ_INS_CLIJNE = 166 , SYSZ_INS_CLRJNE = 167 , SYSZ_INS_CRJNE = 168 , SYSZ_INS_CGIJLH = 169 , SYSZ_INS_CGRJLH = 170 , SYSZ_INS_CIJLH = 171 , SYSZ_INS_CLGIJLH = 172 , SYSZ_INS_CLGRJLH = 173 , SYSZ_INS_CLIJLH = 174 , SYSZ_INS_CLRJLH = 175 , SYSZ_INS_CRJLH = 176 , SYSZ_INS_BLR = 177 , SYSZ_INS_BLER = 178 , SYSZ_INS_JLE = 179 , SYSZ_INS_JGLE = 180 , SYSZ_INS_LOCLE = 181 , SYSZ_INS_LOCGLE = 182 , SYSZ_INS_LOCGRLE = 183 , SYSZ_INS_LOCRLE = 184 , SYSZ_INS_STOCLE = 185 , SYSZ_INS_STOCGLE = 186 , SYSZ_INS_BLHR = 187 , SYSZ_INS_JLH = 188 , SYSZ_INS_JGLH = 189 , SYSZ_INS_LOCLH = 190 , SYSZ_INS_LOCGLH = 191 , SYSZ_INS_LOCGRLH = 192 , SYSZ_INS_LOCRLH = 193 , SYSZ_INS_STOCLH = 194 , SYSZ_INS_STOCGLH = 195 , SYSZ_INS_JL = 196 , SYSZ_INS_JGL = 197 , SYSZ_INS_LOCL = 198 , SYSZ_INS_LOCGL = 199 , SYSZ_INS_LOCGRL = 200 , SYSZ_INS_LOCRL = 201 , SYSZ_INS_LOC = 202 , SYSZ_INS_LOCG = 203 , SYSZ_INS_LOCGR = 204 , SYSZ_INS_LOCR = 205 , SYSZ_INS_STOCL = 206 , SYSZ_INS_STOCGL = 207 , SYSZ_INS_BNER = 208 , SYSZ_INS_JNE = 209 , SYSZ_INS_JGNE = 210 , SYSZ_INS_LOCNE = 211 , SYSZ_INS_LOCGNE = 212 , SYSZ_INS_LOCGRNE = 213 , SYSZ_INS_LOCRNE = 214 , SYSZ_INS_STOCNE = 215 , SYSZ_INS_STOCGNE = 216 , SYSZ_INS_BNHR = 217 , SYSZ_INS_BNHER = 218 , SYSZ_INS_JNHE = 219 , SYSZ_INS_JGNHE = 220 , SYSZ_INS_LOCNHE = 221 , SYSZ_INS_LOCGNHE = 222 , SYSZ_INS_LOCGRNHE = 223 , SYSZ_INS_LOCRNHE = 224 , SYSZ_INS_STOCNHE = 225 , SYSZ_INS_STOCGNHE = 226 , SYSZ_INS_JNH = 227 , SYSZ_INS_JGNH = 228 , SYSZ_INS_LOCNH = 229 , SYSZ_INS_LOCGNH = 230 , SYSZ_INS_LOCGRNH = 231 , SYSZ_INS_LOCRNH = 232 , SYSZ_INS_STOCNH = 233 , SYSZ_INS_STOCGNH = 234 , SYSZ_INS_BNLR = 235 , SYSZ_INS_BNLER = 236 , SYSZ_INS_JNLE = 237 , SYSZ_INS_JGNLE = 238 , SYSZ_INS_LOCNLE = 239 , SYSZ_INS_LOCGNLE = 240 , SYSZ_INS_LOCGRNLE = 241 , SYSZ_INS_LOCRNLE = 242 , SYSZ_INS_STOCNLE = 243 , SYSZ_INS_STOCGNLE = 244 , SYSZ_INS_BNLHR = 245 , SYSZ_INS_JNLH = 246 , SYSZ_INS_JGNLH = 247 , SYSZ_INS_LOCNLH = 248 , SYSZ_INS_LOCGNLH = 249 , SYSZ_INS_LOCGRNLH = 250 , SYSZ_INS_LOCRNLH = 251 , SYSZ_INS_STOCNLH = 252 , SYSZ_INS_STOCGNLH = 253 , SYSZ_INS_JNL = 254 , SYSZ_INS_JGNL = 255 , SYSZ_INS_LOCNL = 256 , SYSZ_INS_LOCGNL = 257 , SYSZ_INS_LOCGRNL = 258 , SYSZ_INS_LOCRNL = 259 , SYSZ_INS_STOCNL = 260 , SYSZ_INS_STOCGNL = 261 , SYSZ_INS_BNOR = 262 , SYSZ_INS_JNO = 263 , SYSZ_INS_JGNO = 264 , SYSZ_INS_LOCNO = 265 , SYSZ_INS_LOCGNO = 266 , SYSZ_INS_LOCGRNO = 267 , SYSZ_INS_LOCRNO = 268 , SYSZ_INS_STOCNO = 269 , SYSZ_INS_STOCGNO = 270 , SYSZ_INS_BOR = 271 , SYSZ_INS_JO = 272 , SYSZ_INS_JGO = 273 , SYSZ_INS_LOCO = 274 , SYSZ_INS_LOCGO = 275 , SYSZ_INS_LOCGRO = 276 , SYSZ_INS_LOCRO = 277 , SYSZ_INS_STOCO = 278 , SYSZ_INS_STOCGO = 279 , SYSZ_INS_STOC = 280 , SYSZ_INS_STOCG = 281 , SYSZ_INS_BASR = 282 , SYSZ_INS_BR = 283 , SYSZ_INS_BRAS = 284 , SYSZ_INS_BRASL = 285 , SYSZ_INS_J = 286 , SYSZ_INS_JG = 287 , SYSZ_INS_BRCT = 288 , SYSZ_INS_BRCTG = 289 , SYSZ_INS_C = 290 , SYSZ_INS_CDB = 291 , SYSZ_INS_CDBR = 292 , SYSZ_INS_CDFBR = 293 , SYSZ_INS_CDGBR = 294 , SYSZ_INS_CDLFBR = 295 , SYSZ_INS_CDLGBR = 296 , SYSZ_INS_CEB = 297 , SYSZ_INS_CEBR = 298 , SYSZ_INS_CEFBR = 299 , SYSZ_INS_CEGBR = 300 , SYSZ_INS_CELFBR = 301 , SYSZ_INS_CELGBR = 302 , SYSZ_INS_CFDBR = 303 , SYSZ_INS_CFEBR = 304 , SYSZ_INS_CFI = 305 , SYSZ_INS_CFXBR = 306 , SYSZ_INS_CG = 307 , SYSZ_INS_CGDBR = 308 , SYSZ_INS_CGEBR = 309 , SYSZ_INS_CGF = 310 , SYSZ_INS_CGFI = 311 , SYSZ_INS_CGFR = 312 , SYSZ_INS_CGFRL = 313 , SYSZ_INS_CGH = 314 , SYSZ_INS_CGHI = 315 , SYSZ_INS_CGHRL = 316 , SYSZ_INS_CGHSI = 317 , SYSZ_INS_CGR = 318 , SYSZ_INS_CGRL = 319 , SYSZ_INS_CGXBR = 320 , SYSZ_INS_CH = 321 , SYSZ_INS_CHF = 322 , SYSZ_INS_CHHSI = 323 , SYSZ_INS_CHI = 324 , SYSZ_INS_CHRL = 325 , SYSZ_INS_CHSI = 326 , SYSZ_INS_CHY = 327 , SYSZ_INS_CIH = 328 , SYSZ_INS_CL = 329 , SYSZ_INS_CLC = 330 , SYSZ_INS_CLFDBR = 331 , SYSZ_INS_CLFEBR = 332 , SYSZ_INS_CLFHSI = 333 , SYSZ_INS_CLFI = 334 , SYSZ_INS_CLFXBR = 335 , SYSZ_INS_CLG = 336 , SYSZ_INS_CLGDBR = 337 , SYSZ_INS_CLGEBR = 338 , SYSZ_INS_CLGF = 339 , SYSZ_INS_CLGFI = 340 , SYSZ_INS_CLGFR = 341 , SYSZ_INS_CLGFRL = 342 , SYSZ_INS_CLGHRL = 343 , SYSZ_INS_CLGHSI = 344 , SYSZ_INS_CLGR = 345 , SYSZ_INS_CLGRL = 346 , SYSZ_INS_CLGXBR = 347 , SYSZ_INS_CLHF = 348 , SYSZ_INS_CLHHSI = 349 , SYSZ_INS_CLHRL = 350 , SYSZ_INS_CLI = 351 , SYSZ_INS_CLIH = 352 , SYSZ_INS_CLIY = 353 , SYSZ_INS_CLR = 354 , SYSZ_INS_CLRL = 355 , SYSZ_INS_CLST = 356 , SYSZ_INS_CLY = 357 , SYSZ_INS_CPSDR = 358 , SYSZ_INS_CR = 359 , SYSZ_INS_CRL = 360 , SYSZ_INS_CS = 361 , SYSZ_INS_CSG = 362 , SYSZ_INS_CSY = 363 , SYSZ_INS_CXBR = 364 , SYSZ_INS_CXFBR = 365 , SYSZ_INS_CXGBR = 366 , SYSZ_INS_CXLFBR = 367 , SYSZ_INS_CXLGBR = 368 , SYSZ_INS_CY = 369 , SYSZ_INS_DDB = 370 , SYSZ_INS_DDBR = 371 , SYSZ_INS_DEB = 372 , SYSZ_INS_DEBR = 373 , SYSZ_INS_DL = 374 , SYSZ_INS_DLG = 375 , SYSZ_INS_DLGR = 376 , SYSZ_INS_DLR = 377 , SYSZ_INS_DSG = 378 , SYSZ_INS_DSGF = 379 , SYSZ_INS_DSGFR = 380 , SYSZ_INS_DSGR = 381 , SYSZ_INS_DXBR = 382 , SYSZ_INS_EAR = 383 , SYSZ_INS_FIDBR = 384 , SYSZ_INS_FIDBRA = 385 , SYSZ_INS_FIEBR = 386 , SYSZ_INS_FIEBRA = 387 , SYSZ_INS_FIXBR = 388 , SYSZ_INS_FIXBRA = 389 , SYSZ_INS_FLOGR = 390 , SYSZ_INS_IC = 391 , SYSZ_INS_ICY = 392 , SYSZ_INS_IIHF = 393 , SYSZ_INS_IIHH = 394 , SYSZ_INS_IIHL = 395 , SYSZ_INS_IILF = 396 , SYSZ_INS_IILH = 397 , SYSZ_INS_IILL = 398 , SYSZ_INS_IPM = 399 , SYSZ_INS_L = 400 , SYSZ_INS_LA = 401 , SYSZ_INS_LAA = 402 , SYSZ_INS_LAAG = 403 , SYSZ_INS_LAAL = 404 , SYSZ_INS_LAALG = 405 , SYSZ_INS_LAN = 406 , SYSZ_INS_LANG = 407 , SYSZ_INS_LAO = 408 , SYSZ_INS_LAOG = 409 , SYSZ_INS_LARL = 410 , SYSZ_INS_LAX = 411 , SYSZ_INS_LAXG = 412 , SYSZ_INS_LAY = 413 , SYSZ_INS_LB = 414 , SYSZ_INS_LBH = 415 , SYSZ_INS_LBR = 416 , SYSZ_INS_LCDBR = 417 , SYSZ_INS_LCEBR = 418 , SYSZ_INS_LCGFR = 419 , SYSZ_INS_LCGR = 420 , SYSZ_INS_LCR = 421 , SYSZ_INS_LCXBR = 422 , SYSZ_INS_LD = 423 , SYSZ_INS_LDEB = 424 , SYSZ_INS_LDEBR = 425 , SYSZ_INS_LDGR = 426 , SYSZ_INS_LDR = 427 , SYSZ_INS_LDXBR = 428 , SYSZ_INS_LDXBRA = 429 , SYSZ_INS_LDY = 430 , SYSZ_INS_LE = 431 , SYSZ_INS_LEDBR = 432 , SYSZ_INS_LEDBRA = 433 , SYSZ_INS_LER = 434 , SYSZ_INS_LEXBR = 435 , SYSZ_INS_LEXBRA = 436 , SYSZ_INS_LEY = 437 , SYSZ_INS_LFH = 438 , SYSZ_INS_LG = 439 , SYSZ_INS_LGB = 440 , SYSZ_INS_LGBR = 441 , SYSZ_INS_LGDR = 442 , SYSZ_INS_LGF = 443 , SYSZ_INS_LGFI = 444 , SYSZ_INS_LGFR = 445 , SYSZ_INS_LGFRL = 446 , SYSZ_INS_LGH = 447 , SYSZ_INS_LGHI = 448 , SYSZ_INS_LGHR = 449 , SYSZ_INS_LGHRL = 450 , SYSZ_INS_LGR = 451 , SYSZ_INS_LGRL = 452 , SYSZ_INS_LH = 453 , SYSZ_INS_LHH = 454 , SYSZ_INS_LHI = 455 , SYSZ_INS_LHR = 456 , SYSZ_INS_LHRL = 457 , SYSZ_INS_LHY = 458 , SYSZ_INS_LLC = 459 , SYSZ_INS_LLCH = 460 , SYSZ_INS_LLCR = 461 , SYSZ_INS_LLGC = 462 , SYSZ_INS_LLGCR = 463 , SYSZ_INS_LLGF = 464 , SYSZ_INS_LLGFR = 465 , SYSZ_INS_LLGFRL = 466 , SYSZ_INS_LLGH = 467 , SYSZ_INS_LLGHR = 468 , SYSZ_INS_LLGHRL = 469 , SYSZ_INS_LLH = 470 , SYSZ_INS_LLHH = 471 , SYSZ_INS_LLHR = 472 , SYSZ_INS_LLHRL = 473 , SYSZ_INS_LLIHF = 474 , SYSZ_INS_LLIHH = 475 , SYSZ_INS_LLIHL = 476 , SYSZ_INS_LLILF = 477 , SYSZ_INS_LLILH = 478 , SYSZ_INS_LLILL = 479 , SYSZ_INS_LMG = 480 , SYSZ_INS_LNDBR = 481 , SYSZ_INS_LNEBR = 482 , SYSZ_INS_LNGFR = 483 , SYSZ_INS_LNGR = 484 , SYSZ_INS_LNR = 485 , SYSZ_INS_LNXBR = 486 , SYSZ_INS_LPDBR = 487 , SYSZ_INS_LPEBR = 488 , SYSZ_INS_LPGFR = 489 , SYSZ_INS_LPGR = 490 , SYSZ_INS_LPR = 491 , SYSZ_INS_LPXBR = 492 , SYSZ_INS_LR = 493 , SYSZ_INS_LRL = 494 , SYSZ_INS_LRV = 495 , SYSZ_INS_LRVG = 496 , SYSZ_INS_LRVGR = 497 , SYSZ_INS_LRVR = 498 , SYSZ_INS_LT = 499 , SYSZ_INS_LTDBR = 500 , SYSZ_INS_LTEBR = 501 , SYSZ_INS_LTG = 502 , SYSZ_INS_LTGF = 503 , SYSZ_INS_LTGFR = 504 , SYSZ_INS_LTGR = 505 , SYSZ_INS_LTR = 506 , SYSZ_INS_LTXBR = 507 , SYSZ_INS_LXDB = 508 , SYSZ_INS_LXDBR = 509 , SYSZ_INS_LXEB = 510 , SYSZ_INS_LXEBR = 511 , SYSZ_INS_LXR = 512 , SYSZ_INS_LY = 513 , SYSZ_INS_LZDR = 514 , SYSZ_INS_LZER = 515 , SYSZ_INS_LZXR = 516 , SYSZ_INS_MADB = 517 , SYSZ_INS_MADBR = 518 , SYSZ_INS_MAEB = 519 , SYSZ_INS_MAEBR = 520 , SYSZ_INS_MDB = 521 , SYSZ_INS_MDBR = 522 , SYSZ_INS_MDEB = 523 , SYSZ_INS_MDEBR = 524 , SYSZ_INS_MEEB = 525 , SYSZ_INS_MEEBR = 526 , SYSZ_INS_MGHI = 527 , SYSZ_INS_MH = 528 , SYSZ_INS_MHI = 529 , SYSZ_INS_MHY = 530 , SYSZ_INS_MLG = 531 , SYSZ_INS_MLGR = 532 , SYSZ_INS_MS = 533 , SYSZ_INS_MSDB = 534 , SYSZ_INS_MSDBR = 535 , SYSZ_INS_MSEB = 536 , SYSZ_INS_MSEBR = 537 , SYSZ_INS_MSFI = 538 , SYSZ_INS_MSG = 539 , SYSZ_INS_MSGF = 540 , SYSZ_INS_MSGFI = 541 , SYSZ_INS_MSGFR = 542 , SYSZ_INS_MSGR = 543 , SYSZ_INS_MSR = 544 , SYSZ_INS_MSY = 545 , SYSZ_INS_MVC = 546 , SYSZ_INS_MVGHI = 547 , SYSZ_INS_MVHHI = 548 , SYSZ_INS_MVHI = 549 , SYSZ_INS_MVI = 550 , SYSZ_INS_MVIY = 551 , SYSZ_INS_MVST = 552 , SYSZ_INS_MXBR = 553 , SYSZ_INS_MXDB = 554 , SYSZ_INS_MXDBR = 555 , SYSZ_INS_N = 556 , SYSZ_INS_NC = 557 , SYSZ_INS_NG = 558 , SYSZ_INS_NGR = 559 , SYSZ_INS_NGRK = 560 , SYSZ_INS_NI = 561 , SYSZ_INS_NIHF = 562 , SYSZ_INS_NIHH = 563 , SYSZ_INS_NIHL = 564 , SYSZ_INS_NILF = 565 , SYSZ_INS_NILH = 566 , SYSZ_INS_NILL = 567 , SYSZ_INS_NIY = 568 , SYSZ_INS_NR = 569 , SYSZ_INS_NRK = 570 , SYSZ_INS_NY = 571 , SYSZ_INS_O = 572 , SYSZ_INS_OC = 573 , SYSZ_INS_OG = 574 , SYSZ_INS_OGR = 575 , SYSZ_INS_OGRK = 576 , SYSZ_INS_OI = 577 , SYSZ_INS_OIHF = 578 , SYSZ_INS_OIHH = 579 , SYSZ_INS_OIHL = 580 , SYSZ_INS_OILF = 581 , SYSZ_INS_OILH = 582 , SYSZ_INS_OILL = 583 , SYSZ_INS_OIY = 584 , SYSZ_INS_OR = 585 , SYSZ_INS_ORK = 586 , SYSZ_INS_OY = 587 , SYSZ_INS_PFD = 588 , SYSZ_INS_PFDRL = 589 , SYSZ_INS_RISBG = 590 , SYSZ_INS_RISBHG = 591 , SYSZ_INS_RISBLG = 592 , SYSZ_INS_RLL = 593 , SYSZ_INS_RLLG = 594 , SYSZ_INS_RNSBG = 595 , SYSZ_INS_ROSBG = 596 , SYSZ_INS_RXSBG = 597 , SYSZ_INS_S = 598 , SYSZ_INS_SDB = 599 , SYSZ_INS_SDBR = 600 , SYSZ_INS_SEB = 601 , SYSZ_INS_SEBR = 602 , SYSZ_INS_SG = 603 , SYSZ_INS_SGF = 604 , SYSZ_INS_SGFR = 605 , SYSZ_INS_SGR = 606 , SYSZ_INS_SGRK = 607 , SYSZ_INS_SH = 608 , SYSZ_INS_SHY = 609 , SYSZ_INS_SL = 610 , SYSZ_INS_SLB = 611 , SYSZ_INS_SLBG = 612 , SYSZ_INS_SLBR = 613 , SYSZ_INS_SLFI = 614 , SYSZ_INS_SLG = 615 , SYSZ_INS_SLBGR = 616 , SYSZ_INS_SLGF = 617 , SYSZ_INS_SLGFI = 618 , SYSZ_INS_SLGFR = 619 , SYSZ_INS_SLGR = 620 , SYSZ_INS_SLGRK = 621 , SYSZ_INS_SLL = 622 , SYSZ_INS_SLLG = 623 , SYSZ_INS_SLLK = 624 , SYSZ_INS_SLR = 625 , SYSZ_INS_SLRK = 626 , SYSZ_INS_SLY = 627 , SYSZ_INS_SQDB = 628 , SYSZ_INS_SQDBR = 629 , SYSZ_INS_SQEB = 630 , SYSZ_INS_SQEBR = 631 , SYSZ_INS_SQXBR = 632 , SYSZ_INS_SR = 633 , SYSZ_INS_SRA = 634 , SYSZ_INS_SRAG = 635 , SYSZ_INS_SRAK = 636 , SYSZ_INS_SRK = 637 , SYSZ_INS_SRL = 638 , SYSZ_INS_SRLG = 639 , SYSZ_INS_SRLK = 640 , SYSZ_INS_SRST = 641 , SYSZ_INS_ST = 642 , SYSZ_INS_STC = 643 , SYSZ_INS_STCH = 644 , SYSZ_INS_STCY = 645 , SYSZ_INS_STD = 646 , SYSZ_INS_STDY = 647 , SYSZ_INS_STE = 648 , SYSZ_INS_STEY = 649 , SYSZ_INS_STFH = 650 , SYSZ_INS_STG = 651 , SYSZ_INS_STGRL = 652 , SYSZ_INS_STH = 653 , SYSZ_INS_STHH = 654 , SYSZ_INS_STHRL = 655 , SYSZ_INS_STHY = 656 , SYSZ_INS_STMG = 657 , SYSZ_INS_STRL = 658 , SYSZ_INS_STRV = 659 , SYSZ_INS_STRVG = 660 , SYSZ_INS_STY = 661 , SYSZ_INS_SXBR = 662 , SYSZ_INS_SY = 663 , SYSZ_INS_TM = 664 , SYSZ_INS_TMHH = 665 , SYSZ_INS_TMHL = 666 , SYSZ_INS_TMLH = 667 , SYSZ_INS_TMLL = 668 , SYSZ_INS_TMY = 669 , SYSZ_INS_X = 670 , SYSZ_INS_XC = 671 , SYSZ_INS_XG = 672 , SYSZ_INS_XGR = 673 , SYSZ_INS_XGRK = 674 , SYSZ_INS_XI = 675 , SYSZ_INS_XIHF = 676 , SYSZ_INS_XILF = 677 , SYSZ_INS_XIY = 678 , SYSZ_INS_XR = 679 , SYSZ_INS_XRK = 680 , SYSZ_INS_XY = 681 , SYSZ_INS_AD = 682 , SYSZ_INS_ADR = 683 , SYSZ_INS_ADTR = 684 , SYSZ_INS_ADTRA = 685 , SYSZ_INS_AE = 686 , SYSZ_INS_AER = 687 , SYSZ_INS_AGH = 688 , SYSZ_INS_AHHHR = 689 , SYSZ_INS_AHHLR = 690 , SYSZ_INS_ALGSI = 691 , SYSZ_INS_ALHHHR = 692 , SYSZ_INS_ALHHLR = 693 , SYSZ_INS_ALSI = 694 , SYSZ_INS_ALSIH = 695 , SYSZ_INS_ALSIHN = 696 , SYSZ_INS_AP = 697 , SYSZ_INS_AU = 698 , SYSZ_INS_AUR = 699 , SYSZ_INS_AW = 700 , SYSZ_INS_AWR = 701 , SYSZ_INS_AXR = 702 , SYSZ_INS_AXTR = 703 , SYSZ_INS_AXTRA = 704 , SYSZ_INS_B = 705 , SYSZ_INS_BAKR = 706 , SYSZ_INS_BAL = 707 , SYSZ_INS_BALR = 708 , SYSZ_INS_BAS = 709 , SYSZ_INS_BASSM = 710 , SYSZ_INS_BC = 711 , SYSZ_INS_BCT = 712 , SYSZ_INS_BCTG = 713 , SYSZ_INS_BCTGR = 714 , SYSZ_INS_BCTR = 715 , SYSZ_INS_BE = 716 , SYSZ_INS_BH = 717 , SYSZ_INS_BHE = 718 , SYSZ_INS_BI = 719 , SYSZ_INS_BIC = 720 , SYSZ_INS_BIE = 721 , SYSZ_INS_BIH = 722 , SYSZ_INS_BIHE = 723 , SYSZ_INS_BIL = 724 , SYSZ_INS_BILE = 725 , SYSZ_INS_BILH = 726 , SYSZ_INS_BIM = 727 , SYSZ_INS_BINE = 728 , SYSZ_INS_BINH = 729 , SYSZ_INS_BINHE = 730 , SYSZ_INS_BINL = 731 , SYSZ_INS_BINLE = 732 , SYSZ_INS_BINLH = 733 , SYSZ_INS_BINM = 734 , SYSZ_INS_BINO = 735 , SYSZ_INS_BINP = 736 , SYSZ_INS_BINZ = 737 , SYSZ_INS_BIO = 738 , SYSZ_INS_BIP = 739 , SYSZ_INS_BIZ = 740 , SYSZ_INS_BL = 741 , SYSZ_INS_BLE = 742 , SYSZ_INS_BLH = 743 , SYSZ_INS_BM = 744 , SYSZ_INS_BMR = 745 , SYSZ_INS_BNE = 746 , SYSZ_INS_BNH = 747 , SYSZ_INS_BNHE = 748 , SYSZ_INS_BNL = 749 , SYSZ_INS_BNLE = 750 , SYSZ_INS_BNLH = 751 , SYSZ_INS_BNM = 752 , SYSZ_INS_BNMR = 753 , SYSZ_INS_BNO = 754 , SYSZ_INS_BNP = 755 , SYSZ_INS_BNPR = 756 , SYSZ_INS_BNZ = 757 , SYSZ_INS_BNZR = 758 , SYSZ_INS_BO = 759 , SYSZ_INS_BP = 760 , SYSZ_INS_BPP = 761 , SYSZ_INS_BPR = 762 , SYSZ_INS_BPRP = 763 , SYSZ_INS_BRCTH = 764 , SYSZ_INS_BRXH = 765 , SYSZ_INS_BRXHG = 766 , SYSZ_INS_BRXLE = 767 , SYSZ_INS_BRXLG = 768 , SYSZ_INS_BSA = 769 , SYSZ_INS_BSG = 770 , SYSZ_INS_BSM = 771 , SYSZ_INS_BXH = 772 , SYSZ_INS_BXHG = 773 , SYSZ_INS_BXLE = 774 , SYSZ_INS_BXLEG = 775 , SYSZ_INS_BZ = 776 , SYSZ_INS_BZR = 777 , SYSZ_INS_CD = 778 , SYSZ_INS_CDFBRA = 779 , SYSZ_INS_CDFR = 780 , SYSZ_INS_CDFTR = 781 , SYSZ_INS_CDGBRA = 782 , SYSZ_INS_CDGR = 783 , SYSZ_INS_CDGTR = 784 , SYSZ_INS_CDGTRA = 785 , SYSZ_INS_CDLFTR = 786 , SYSZ_INS_CDLGTR = 787 , SYSZ_INS_CDPT = 788 , SYSZ_INS_CDR = 789 , SYSZ_INS_CDS = 790 , SYSZ_INS_CDSG = 791 , SYSZ_INS_CDSTR = 792 , SYSZ_INS_CDSY = 793 , SYSZ_INS_CDTR = 794 , SYSZ_INS_CDUTR = 795 , SYSZ_INS_CDZT = 796 , SYSZ_INS_CE = 797 , SYSZ_INS_CEDTR = 798 , SYSZ_INS_CEFBRA = 799 , SYSZ_INS_CEFR = 800 , SYSZ_INS_CEGBRA = 801 , SYSZ_INS_CEGR = 802 , SYSZ_INS_CER = 803 , SYSZ_INS_CEXTR = 804 , SYSZ_INS_CFC = 805 , SYSZ_INS_CFDBRA = 806 , SYSZ_INS_CFDR = 807 , SYSZ_INS_CFDTR = 808 , SYSZ_INS_CFEBRA = 809 , SYSZ_INS_CFER = 810 , SYSZ_INS_CFXBRA = 811 , SYSZ_INS_CFXR = 812 , SYSZ_INS_CFXTR = 813 , SYSZ_INS_CGDBRA = 814 , SYSZ_INS_CGDR = 815 , SYSZ_INS_CGDTR = 816 , SYSZ_INS_CGDTRA = 817 , SYSZ_INS_CGEBRA = 818 , SYSZ_INS_CGER = 819 , SYSZ_INS_CGIB = 820 , SYSZ_INS_CGIBE = 821 , SYSZ_INS_CGIBH = 822 , SYSZ_INS_CGIBHE = 823 , SYSZ_INS_CGIBL = 824 , SYSZ_INS_CGIBLE = 825 , SYSZ_INS_CGIBLH = 826 , SYSZ_INS_CGIBNE = 827 , SYSZ_INS_CGIBNH = 828 , SYSZ_INS_CGIBNHE = 829 , SYSZ_INS_CGIBNL = 830 , SYSZ_INS_CGIBNLE = 831 , SYSZ_INS_CGIBNLH = 832 , SYSZ_INS_CGIT = 833 , SYSZ_INS_CGITE = 834 , SYSZ_INS_CGITH = 835 , SYSZ_INS_CGITHE = 836 , SYSZ_INS_CGITL = 837 , SYSZ_INS_CGITLE = 838 , SYSZ_INS_CGITLH = 839 , SYSZ_INS_CGITNE = 840 , SYSZ_INS_CGITNH = 841 , SYSZ_INS_CGITNHE = 842 , SYSZ_INS_CGITNL = 843 , SYSZ_INS_CGITNLE = 844 , SYSZ_INS_CGITNLH = 845 , SYSZ_INS_CGRB = 846 , SYSZ_INS_CGRBE = 847 , SYSZ_INS_CGRBH = 848 , SYSZ_INS_CGRBHE = 849 , SYSZ_INS_CGRBL = 850 , SYSZ_INS_CGRBLE = 851 , SYSZ_INS_CGRBLH = 852 , SYSZ_INS_CGRBNE = 853 , SYSZ_INS_CGRBNH = 854 , SYSZ_INS_CGRBNHE = 855 , SYSZ_INS_CGRBNL = 856 , SYSZ_INS_CGRBNLE = 857 , SYSZ_INS_CGRBNLH = 858 , SYSZ_INS_CGRT = 859 , SYSZ_INS_CGRTE = 860 , SYSZ_INS_CGRTH = 861 , SYSZ_INS_CGRTHE = 862 , SYSZ_INS_CGRTL = 863 , SYSZ_INS_CGRTLE = 864 , SYSZ_INS_CGRTLH = 865 , SYSZ_INS_CGRTNE = 866 , SYSZ_INS_CGRTNH = 867 , SYSZ_INS_CGRTNHE = 868 , SYSZ_INS_CGRTNL = 869 , SYSZ_INS_CGRTNLE = 870 , SYSZ_INS_CGRTNLH = 871 , SYSZ_INS_CGXBRA = 872 , SYSZ_INS_CGXR = 873 , SYSZ_INS_CGXTR = 874 , SYSZ_INS_CGXTRA = 875 , SYSZ_INS_CHHR = 876 , SYSZ_INS_CHLR = 877 , SYSZ_INS_CIB = 878 , SYSZ_INS_CIBE = 879 , SYSZ_INS_CIBH = 880 , SYSZ_INS_CIBHE = 881 , SYSZ_INS_CIBL = 882 , SYSZ_INS_CIBLE = 883 , SYSZ_INS_CIBLH = 884 , SYSZ_INS_CIBNE = 885 , SYSZ_INS_CIBNH = 886 , SYSZ_INS_CIBNHE = 887 , SYSZ_INS_CIBNL = 888 , SYSZ_INS_CIBNLE = 889 , SYSZ_INS_CIBNLH = 890 , SYSZ_INS_CIT = 891 , SYSZ_INS_CITE = 892 , SYSZ_INS_CITH = 893 , SYSZ_INS_CITHE = 894 , SYSZ_INS_CITL = 895 , SYSZ_INS_CITLE = 896 , SYSZ_INS_CITLH = 897 , SYSZ_INS_CITNE = 898 , SYSZ_INS_CITNH = 899 , SYSZ_INS_CITNHE = 900 , SYSZ_INS_CITNL = 901 , SYSZ_INS_CITNLE = 902 , SYSZ_INS_CITNLH = 903 , SYSZ_INS_CKSM = 904 , SYSZ_INS_CLCL = 905 , SYSZ_INS_CLCLE = 906 , SYSZ_INS_CLCLU = 907 , SYSZ_INS_CLFDTR = 908 , SYSZ_INS_CLFIT = 909 , SYSZ_INS_CLFITE = 910 , SYSZ_INS_CLFITH = 911 , SYSZ_INS_CLFITHE = 912 , SYSZ_INS_CLFITL = 913 , SYSZ_INS_CLFITLE = 914 , SYSZ_INS_CLFITLH = 915 , SYSZ_INS_CLFITNE = 916 , SYSZ_INS_CLFITNH = 917 , SYSZ_INS_CLFITNHE = 918 , SYSZ_INS_CLFITNL = 919 , SYSZ_INS_CLFITNLE = 920 , SYSZ_INS_CLFITNLH = 921 , SYSZ_INS_CLFXTR = 922 , SYSZ_INS_CLGDTR = 923 , SYSZ_INS_CLGIB = 924 , SYSZ_INS_CLGIBE = 925 , SYSZ_INS_CLGIBH = 926 , SYSZ_INS_CLGIBHE = 927 , SYSZ_INS_CLGIBL = 928 , SYSZ_INS_CLGIBLE = 929 , SYSZ_INS_CLGIBLH = 930 , SYSZ_INS_CLGIBNE = 931 , SYSZ_INS_CLGIBNH = 932 , SYSZ_INS_CLGIBNHE = 933 , SYSZ_INS_CLGIBNL = 934 , SYSZ_INS_CLGIBNLE = 935 , SYSZ_INS_CLGIBNLH = 936 , SYSZ_INS_CLGIT = 937 , SYSZ_INS_CLGITE = 938 , SYSZ_INS_CLGITH = 939 , SYSZ_INS_CLGITHE = 940 , SYSZ_INS_CLGITL = 941 , SYSZ_INS_CLGITLE = 942 , SYSZ_INS_CLGITLH = 943 , SYSZ_INS_CLGITNE = 944 , SYSZ_INS_CLGITNH = 945 , SYSZ_INS_CLGITNHE = 946 , SYSZ_INS_CLGITNL = 947 , SYSZ_INS_CLGITNLE = 948 , SYSZ_INS_CLGITNLH = 949 , SYSZ_INS_CLGRB = 950 , SYSZ_INS_CLGRBE = 951 , SYSZ_INS_CLGRBH = 952 , SYSZ_INS_CLGRBHE = 953 , SYSZ_INS_CLGRBL = 954 , SYSZ_INS_CLGRBLE = 955 , SYSZ_INS_CLGRBLH = 956 , SYSZ_INS_CLGRBNE = 957 , SYSZ_INS_CLGRBNH = 958 , SYSZ_INS_CLGRBNHE = 959 , SYSZ_INS_CLGRBNL = 960 , SYSZ_INS_CLGRBNLE = 961 , SYSZ_INS_CLGRBNLH = 962 , SYSZ_INS_CLGRT = 963 , SYSZ_INS_CLGRTE = 964 , SYSZ_INS_CLGRTH = 965 , SYSZ_INS_CLGRTHE = 966 , SYSZ_INS_CLGRTL = 967 , SYSZ_INS_CLGRTLE = 968 , SYSZ_INS_CLGRTLH = 969 , SYSZ_INS_CLGRTNE = 970 , SYSZ_INS_CLGRTNH = 971 , SYSZ_INS_CLGRTNHE = 972 , SYSZ_INS_CLGRTNL = 973 , SYSZ_INS_CLGRTNLE = 974 , SYSZ_INS_CLGRTNLH = 975 , SYSZ_INS_CLGT = 976 , SYSZ_INS_CLGTE = 977 , SYSZ_INS_CLGTH = 978 , SYSZ_INS_CLGTHE = 979 , SYSZ_INS_CLGTL = 980 , SYSZ_INS_CLGTLE = 981 , SYSZ_INS_CLGTLH = 982 , SYSZ_INS_CLGTNE = 983 , SYSZ_INS_CLGTNH = 984 , SYSZ_INS_CLGTNHE = 985 , SYSZ_INS_CLGTNL = 986 , SYSZ_INS_CLGTNLE = 987 , SYSZ_INS_CLGTNLH = 988 , SYSZ_INS_CLGXTR = 989 , SYSZ_INS_CLHHR = 990 , SYSZ_INS_CLHLR = 991 , SYSZ_INS_CLIB = 992 , SYSZ_INS_CLIBE = 993 , SYSZ_INS_CLIBH = 994 , SYSZ_INS_CLIBHE = 995 , SYSZ_INS_CLIBL = 996 , SYSZ_INS_CLIBLE = 997 , SYSZ_INS_CLIBLH = 998 , SYSZ_INS_CLIBNE = 999 , SYSZ_INS_CLIBNH = 1000 , SYSZ_INS_CLIBNHE = 1001 , SYSZ_INS_CLIBNL = 1002 , SYSZ_INS_CLIBNLE = 1003 , SYSZ_INS_CLIBNLH = 1004 , SYSZ_INS_CLM = 1005 , SYSZ_INS_CLMH = 1006 , SYSZ_INS_CLMY = 1007 , SYSZ_INS_CLRB = 1008 , SYSZ_INS_CLRBE = 1009 , SYSZ_INS_CLRBH = 1010 , SYSZ_INS_CLRBHE = 1011 , SYSZ_INS_CLRBL = 1012 , SYSZ_INS_CLRBLE = 1013 , SYSZ_INS_CLRBLH = 1014 , SYSZ_INS_CLRBNE = 1015 , SYSZ_INS_CLRBNH = 1016 , SYSZ_INS_CLRBNHE = 1017 , SYSZ_INS_CLRBNL = 1018 , SYSZ_INS_CLRBNLE = 1019 , SYSZ_INS_CLRBNLH = 1020 , SYSZ_INS_CLRT = 1021 , SYSZ_INS_CLRTE = 1022 , SYSZ_INS_CLRTH = 1023 , SYSZ_INS_CLRTHE = 1024 , SYSZ_INS_CLRTL = 1025 , SYSZ_INS_CLRTLE = 1026 , SYSZ_INS_CLRTLH = 1027 , SYSZ_INS_CLRTNE = 1028 , SYSZ_INS_CLRTNH = 1029 , SYSZ_INS_CLRTNHE = 1030 , SYSZ_INS_CLRTNL = 1031 , SYSZ_INS_CLRTNLE = 1032 , SYSZ_INS_CLRTNLH = 1033 , SYSZ_INS_CLT = 1034 , SYSZ_INS_CLTE = 1035 , SYSZ_INS_CLTH = 1036 , SYSZ_INS_CLTHE = 1037 , SYSZ_INS_CLTL = 1038 , SYSZ_INS_CLTLE = 1039 , SYSZ_INS_CLTLH = 1040 , SYSZ_INS_CLTNE = 1041 , SYSZ_INS_CLTNH = 1042 , SYSZ_INS_CLTNHE = 1043 , SYSZ_INS_CLTNL = 1044 , SYSZ_INS_CLTNLE = 1045 , SYSZ_INS_CLTNLH = 1046 , SYSZ_INS_CMPSC = 1047 , SYSZ_INS_CP = 1048 , SYSZ_INS_CPDT = 1049 , SYSZ_INS_CPXT = 1050 , SYSZ_INS_CPYA = 1051 , SYSZ_INS_CRB = 1052 , SYSZ_INS_CRBE = 1053 , SYSZ_INS_CRBH = 1054 , SYSZ_INS_CRBHE = 1055 , SYSZ_INS_CRBL = 1056 , SYSZ_INS_CRBLE = 1057 , SYSZ_INS_CRBLH = 1058 , SYSZ_INS_CRBNE = 1059 , SYSZ_INS_CRBNH = 1060 , SYSZ_INS_CRBNHE = 1061 , SYSZ_INS_CRBNL = 1062 , SYSZ_INS_CRBNLE = 1063 , SYSZ_INS_CRBNLH = 1064 , SYSZ_INS_CRDTE = 1065 , SYSZ_INS_CRT = 1066 , SYSZ_INS_CRTE = 1067 , SYSZ_INS_CRTH = 1068 , SYSZ_INS_CRTHE = 1069 , SYSZ_INS_CRTL = 1070 , SYSZ_INS_CRTLE = 1071 , SYSZ_INS_CRTLH = 1072 , SYSZ_INS_CRTNE = 1073 , SYSZ_INS_CRTNH = 1074 , SYSZ_INS_CRTNHE = 1075 , SYSZ_INS_CRTNL = 1076 , SYSZ_INS_CRTNLE = 1077 , SYSZ_INS_CRTNLH = 1078 , SYSZ_INS_CSCH = 1079 , SYSZ_INS_CSDTR = 1080 , SYSZ_INS_CSP = 1081 , SYSZ_INS_CSPG = 1082 , SYSZ_INS_CSST = 1083 , SYSZ_INS_CSXTR = 1084 , SYSZ_INS_CU12 = 1085 , SYSZ_INS_CU14 = 1086 , SYSZ_INS_CU21 = 1087 , SYSZ_INS_CU24 = 1088 , SYSZ_INS_CU41 = 1089 , SYSZ_INS_CU42 = 1090 , SYSZ_INS_CUDTR = 1091 , SYSZ_INS_CUSE = 1092 , SYSZ_INS_CUTFU = 1093 , SYSZ_INS_CUUTF = 1094 , SYSZ_INS_CUXTR = 1095 , SYSZ_INS_CVB = 1096 , SYSZ_INS_CVBG = 1097 , SYSZ_INS_CVBY = 1098 , SYSZ_INS_CVD = 1099 , SYSZ_INS_CVDG = 1100 , SYSZ_INS_CVDY = 1101 , SYSZ_INS_CXFBRA = 1102 , SYSZ_INS_CXFR = 1103 , SYSZ_INS_CXFTR = 1104 , SYSZ_INS_CXGBRA = 1105 , SYSZ_INS_CXGR = 1106 , SYSZ_INS_CXGTR = 1107 , SYSZ_INS_CXGTRA = 1108 , SYSZ_INS_CXLFTR = 1109 , SYSZ_INS_CXLGTR = 1110 , SYSZ_INS_CXPT = 1111 , SYSZ_INS_CXR = 1112 , SYSZ_INS_CXSTR = 1113 , SYSZ_INS_CXTR = 1114 , SYSZ_INS_CXUTR = 1115 , SYSZ_INS_CXZT = 1116 , SYSZ_INS_CZDT = 1117 , SYSZ_INS_CZXT = 1118 , SYSZ_INS_D = 1119 , SYSZ_INS_DD = 1120 , SYSZ_INS_DDR = 1121 , SYSZ_INS_DDTR = 1122 , SYSZ_INS_DDTRA = 1123 , SYSZ_INS_DE = 1124 , SYSZ_INS_DER = 1125 , SYSZ_INS_DIAG = 1126 , SYSZ_INS_DIDBR = 1127 , SYSZ_INS_DIEBR = 1128 , SYSZ_INS_DP = 1129 , SYSZ_INS_DR = 1130 , SYSZ_INS_DXR = 1131 , SYSZ_INS_DXTR = 1132 , SYSZ_INS_DXTRA = 1133 , SYSZ_INS_ECAG = 1134 , SYSZ_INS_ECCTR = 1135 , SYSZ_INS_ECPGA = 1136 , SYSZ_INS_ECTG = 1137 , SYSZ_INS_ED = 1138 , SYSZ_INS_EDMK = 1139 , SYSZ_INS_EEDTR = 1140 , SYSZ_INS_EEXTR = 1141 , SYSZ_INS_EFPC = 1142 , SYSZ_INS_EPAIR = 1143 , SYSZ_INS_EPAR = 1144 , SYSZ_INS_EPCTR = 1145 , SYSZ_INS_EPSW = 1146 , SYSZ_INS_EREG = 1147 , SYSZ_INS_EREGG = 1148 , SYSZ_INS_ESAIR = 1149 , SYSZ_INS_ESAR = 1150 , SYSZ_INS_ESDTR = 1151 , SYSZ_INS_ESEA = 1152 , SYSZ_INS_ESTA = 1153 , SYSZ_INS_ESXTR = 1154 , SYSZ_INS_ETND = 1155 , SYSZ_INS_EX = 1156 , SYSZ_INS_EXRL = 1157 , SYSZ_INS_FIDR = 1158 , SYSZ_INS_FIDTR = 1159 , SYSZ_INS_FIER = 1160 , SYSZ_INS_FIXR = 1161 , SYSZ_INS_FIXTR = 1162 , SYSZ_INS_HDR = 1163 , SYSZ_INS_HER = 1164 , SYSZ_INS_HSCH = 1165 , SYSZ_INS_IAC = 1166 , SYSZ_INS_ICM = 1167 , SYSZ_INS_ICMH = 1168 , SYSZ_INS_ICMY = 1169 , SYSZ_INS_IDTE = 1170 , SYSZ_INS_IEDTR = 1171 , SYSZ_INS_IEXTR = 1172 , SYSZ_INS_IPK = 1173 , SYSZ_INS_IPTE = 1174 , SYSZ_INS_IRBM = 1175 , SYSZ_INS_ISKE = 1176 , SYSZ_INS_IVSK = 1177 , SYSZ_INS_JGM = 1178 , SYSZ_INS_JGNM = 1179 , SYSZ_INS_JGNP = 1180 , SYSZ_INS_JGNZ = 1181 , SYSZ_INS_JGP = 1182 , SYSZ_INS_JGZ = 1183 , SYSZ_INS_JM = 1184 , SYSZ_INS_JNM = 1185 , SYSZ_INS_JNP = 1186 , SYSZ_INS_JNZ = 1187 , SYSZ_INS_JP = 1188 , SYSZ_INS_JZ = 1189 , SYSZ_INS_KDB = 1190 , SYSZ_INS_KDBR = 1191 , SYSZ_INS_KDTR = 1192 , SYSZ_INS_KEB = 1193 , SYSZ_INS_KEBR = 1194 , SYSZ_INS_KIMD = 1195 , SYSZ_INS_KLMD = 1196 , SYSZ_INS_KM = 1197 , SYSZ_INS_KMA = 1198 , SYSZ_INS_KMAC = 1199 , SYSZ_INS_KMC = 1200 , SYSZ_INS_KMCTR = 1201 , SYSZ_INS_KMF = 1202 , SYSZ_INS_KMO = 1203 , SYSZ_INS_KXBR = 1204 , SYSZ_INS_KXTR = 1205 , SYSZ_INS_LAE = 1206 , SYSZ_INS_LAEY = 1207 , SYSZ_INS_LAM = 1208 , SYSZ_INS_LAMY = 1209 , SYSZ_INS_LASP = 1210 , SYSZ_INS_LAT = 1211 , SYSZ_INS_LCBB = 1212 , SYSZ_INS_LCCTL = 1213 , SYSZ_INS_LCDFR = 1214 , SYSZ_INS_LCDR = 1215 , SYSZ_INS_LCER = 1216 , SYSZ_INS_LCTL = 1217 , SYSZ_INS_LCTLG = 1218 , SYSZ_INS_LCXR = 1219 , SYSZ_INS_LDE = 1220 , SYSZ_INS_LDER = 1221 , SYSZ_INS_LDETR = 1222 , SYSZ_INS_LDXR = 1223 , SYSZ_INS_LDXTR = 1224 , SYSZ_INS_LEDR = 1225 , SYSZ_INS_LEDTR = 1226 , SYSZ_INS_LEXR = 1227 , SYSZ_INS_LFAS = 1228 , SYSZ_INS_LFHAT = 1229 , SYSZ_INS_LFPC = 1230 , SYSZ_INS_LGAT = 1231 , SYSZ_INS_LGG = 1232 , SYSZ_INS_LGSC = 1233 , SYSZ_INS_LLGFAT = 1234 , SYSZ_INS_LLGFSG = 1235 , SYSZ_INS_LLGT = 1236 , SYSZ_INS_LLGTAT = 1237 , SYSZ_INS_LLGTR = 1238 , SYSZ_INS_LLZRGF = 1239 , SYSZ_INS_LM = 1240 , SYSZ_INS_LMD = 1241 , SYSZ_INS_LMH = 1242 , SYSZ_INS_LMY = 1243 , SYSZ_INS_LNDFR = 1244 , SYSZ_INS_LNDR = 1245 , SYSZ_INS_LNER = 1246 , SYSZ_INS_LNXR = 1247 , SYSZ_INS_LOCFH = 1248 , SYSZ_INS_LOCFHE = 1249 , SYSZ_INS_LOCFHH = 1250 , SYSZ_INS_LOCFHHE = 1251 , SYSZ_INS_LOCFHL = 1252 , SYSZ_INS_LOCFHLE = 1253 , SYSZ_INS_LOCFHLH = 1254 , SYSZ_INS_LOCFHM = 1255 , SYSZ_INS_LOCFHNE = 1256 , SYSZ_INS_LOCFHNH = 1257 , SYSZ_INS_LOCFHNHE = 1258 , SYSZ_INS_LOCFHNL = 1259 , SYSZ_INS_LOCFHNLE = 1260 , SYSZ_INS_LOCFHNLH = 1261 , SYSZ_INS_LOCFHNM = 1262 , SYSZ_INS_LOCFHNO = 1263 , SYSZ_INS_LOCFHNP = 1264 , SYSZ_INS_LOCFHNZ = 1265 , SYSZ_INS_LOCFHO = 1266 , SYSZ_INS_LOCFHP = 1267 , SYSZ_INS_LOCFHR = 1268 , SYSZ_INS_LOCFHRE = 1269 , SYSZ_INS_LOCFHRH = 1270 , SYSZ_INS_LOCFHRHE = 1271 , SYSZ_INS_LOCFHRL = 1272 , SYSZ_INS_LOCFHRLE = 1273 , SYSZ_INS_LOCFHRLH = 1274 , SYSZ_INS_LOCFHRM = 1275 , SYSZ_INS_LOCFHRNE = 1276 , SYSZ_INS_LOCFHRNH = 1277 , SYSZ_INS_LOCFHRNHE = 1278 , SYSZ_INS_LOCFHRNL = 1279 , SYSZ_INS_LOCFHRNLE = 1280 , SYSZ_INS_LOCFHRNLH = 1281 , SYSZ_INS_LOCFHRNM = 1282 , SYSZ_INS_LOCFHRNO = 1283 , SYSZ_INS_LOCFHRNP = 1284 , SYSZ_INS_LOCFHRNZ = 1285 , SYSZ_INS_LOCFHRO = 1286 , SYSZ_INS_LOCFHRP = 1287 , SYSZ_INS_LOCFHRZ = 1288 , SYSZ_INS_LOCFHZ = 1289 , SYSZ_INS_LOCGHI = 1290 , SYSZ_INS_LOCGHIE = 1291 , SYSZ_INS_LOCGHIH = 1292 , SYSZ_INS_LOCGHIHE = 1293 , SYSZ_INS_LOCGHIL = 1294 , SYSZ_INS_LOCGHILE = 1295 , SYSZ_INS_LOCGHILH = 1296 , SYSZ_INS_LOCGHIM = 1297 , SYSZ_INS_LOCGHINE = 1298 , SYSZ_INS_LOCGHINH = 1299 , SYSZ_INS_LOCGHINHE = 1300 , SYSZ_INS_LOCGHINL = 1301 , SYSZ_INS_LOCGHINLE = 1302 , SYSZ_INS_LOCGHINLH = 1303 , SYSZ_INS_LOCGHINM = 1304 , SYSZ_INS_LOCGHINO = 1305 , SYSZ_INS_LOCGHINP = 1306 , SYSZ_INS_LOCGHINZ = 1307 , SYSZ_INS_LOCGHIO = 1308 , SYSZ_INS_LOCGHIP = 1309 , SYSZ_INS_LOCGHIZ = 1310 , SYSZ_INS_LOCGM = 1311 , SYSZ_INS_LOCGNM = 1312 , SYSZ_INS_LOCGNP = 1313 , SYSZ_INS_LOCGNZ = 1314 , SYSZ_INS_LOCGP = 1315 , SYSZ_INS_LOCGRM = 1316 , SYSZ_INS_LOCGRNM = 1317 , SYSZ_INS_LOCGRNP = 1318 , SYSZ_INS_LOCGRNZ = 1319 , SYSZ_INS_LOCGRP = 1320 , SYSZ_INS_LOCGRZ = 1321 , SYSZ_INS_LOCGZ = 1322 , SYSZ_INS_LOCHHI = 1323 , SYSZ_INS_LOCHHIE = 1324 , SYSZ_INS_LOCHHIH = 1325 , SYSZ_INS_LOCHHIHE = 1326 , SYSZ_INS_LOCHHIL = 1327 , SYSZ_INS_LOCHHILE = 1328 , SYSZ_INS_LOCHHILH = 1329 , SYSZ_INS_LOCHHIM = 1330 , SYSZ_INS_LOCHHINE = 1331 , SYSZ_INS_LOCHHINH = 1332 , SYSZ_INS_LOCHHINHE = 1333 , SYSZ_INS_LOCHHINL = 1334 , SYSZ_INS_LOCHHINLE = 1335 , SYSZ_INS_LOCHHINLH = 1336 , SYSZ_INS_LOCHHINM = 1337 , SYSZ_INS_LOCHHINO = 1338 , SYSZ_INS_LOCHHINP = 1339 , SYSZ_INS_LOCHHINZ = 1340 , SYSZ_INS_LOCHHIO = 1341 , SYSZ_INS_LOCHHIP = 1342 , SYSZ_INS_LOCHHIZ = 1343 , SYSZ_INS_LOCHI = 1344 , SYSZ_INS_LOCHIE = 1345 , SYSZ_INS_LOCHIH = 1346 , SYSZ_INS_LOCHIHE = 1347 , SYSZ_INS_LOCHIL = 1348 , SYSZ_INS_LOCHILE = 1349 , SYSZ_INS_LOCHILH = 1350 , SYSZ_INS_LOCHIM = 1351 , SYSZ_INS_LOCHINE = 1352 , SYSZ_INS_LOCHINH = 1353 , SYSZ_INS_LOCHINHE = 1354 , SYSZ_INS_LOCHINL = 1355 , SYSZ_INS_LOCHINLE = 1356 , SYSZ_INS_LOCHINLH = 1357 , SYSZ_INS_LOCHINM = 1358 , SYSZ_INS_LOCHINO = 1359 , SYSZ_INS_LOCHINP = 1360 , SYSZ_INS_LOCHINZ = 1361 , SYSZ_INS_LOCHIO = 1362 , SYSZ_INS_LOCHIP = 1363 , SYSZ_INS_LOCHIZ = 1364 , SYSZ_INS_LOCM = 1365 , SYSZ_INS_LOCNM = 1366 , SYSZ_INS_LOCNP = 1367 , SYSZ_INS_LOCNZ = 1368 , SYSZ_INS_LOCP = 1369 , SYSZ_INS_LOCRM = 1370 , SYSZ_INS_LOCRNM = 1371 , SYSZ_INS_LOCRNP = 1372 , SYSZ_INS_LOCRNZ = 1373 , SYSZ_INS_LOCRP = 1374 , SYSZ_INS_LOCRZ = 1375 , SYSZ_INS_LOCZ = 1376 , SYSZ_INS_LPCTL = 1377 , SYSZ_INS_LPD = 1378 , SYSZ_INS_LPDFR = 1379 , SYSZ_INS_LPDG = 1380 , SYSZ_INS_LPDR = 1381 , SYSZ_INS_LPER = 1382 , SYSZ_INS_LPP = 1383 , SYSZ_INS_LPQ = 1384 , SYSZ_INS_LPSW = 1385 , SYSZ_INS_LPSWE = 1386 , SYSZ_INS_LPTEA = 1387 , SYSZ_INS_LPXR = 1388 , SYSZ_INS_LRA = 1389 , SYSZ_INS_LRAG = 1390 , SYSZ_INS_LRAY = 1391 , SYSZ_INS_LRDR = 1392 , SYSZ_INS_LRER = 1393 , SYSZ_INS_LRVH = 1394 , SYSZ_INS_LSCTL = 1395 , SYSZ_INS_LTDR = 1396 , SYSZ_INS_LTDTR = 1397 , SYSZ_INS_LTER = 1398 , SYSZ_INS_LTXR = 1399 , SYSZ_INS_LTXTR = 1400 , SYSZ_INS_LURA = 1401 , SYSZ_INS_LURAG = 1402 , SYSZ_INS_LXD = 1403 , SYSZ_INS_LXDR = 1404 , SYSZ_INS_LXDTR = 1405 , SYSZ_INS_LXE = 1406 , SYSZ_INS_LXER = 1407 , SYSZ_INS_LZRF = 1408 , SYSZ_INS_LZRG = 1409 , SYSZ_INS_M = 1410 , SYSZ_INS_MAD = 1411 , SYSZ_INS_MADR = 1412 , SYSZ_INS_MAE = 1413 , SYSZ_INS_MAER = 1414 , SYSZ_INS_MAY = 1415 , SYSZ_INS_MAYH = 1416 , SYSZ_INS_MAYHR = 1417 , SYSZ_INS_MAYL = 1418 , SYSZ_INS_MAYLR = 1419 , SYSZ_INS_MAYR = 1420 , SYSZ_INS_MC = 1421 , SYSZ_INS_MD = 1422 , SYSZ_INS_MDE = 1423 , SYSZ_INS_MDER = 1424 , SYSZ_INS_MDR = 1425 , SYSZ_INS_MDTR = 1426 , SYSZ_INS_MDTRA = 1427 , SYSZ_INS_ME = 1428 , SYSZ_INS_MEE = 1429 , SYSZ_INS_MEER = 1430 , SYSZ_INS_MER = 1431 , SYSZ_INS_MFY = 1432 , SYSZ_INS_MG = 1433 , SYSZ_INS_MGH = 1434 , SYSZ_INS_MGRK = 1435 , SYSZ_INS_ML = 1436 , SYSZ_INS_MLR = 1437 , SYSZ_INS_MP = 1438 , SYSZ_INS_MR = 1439 , SYSZ_INS_MSC = 1440 , SYSZ_INS_MSCH = 1441 , SYSZ_INS_MSD = 1442 , SYSZ_INS_MSDR = 1443 , SYSZ_INS_MSE = 1444 , SYSZ_INS_MSER = 1445 , SYSZ_INS_MSGC = 1446 , SYSZ_INS_MSGRKC = 1447 , SYSZ_INS_MSRKC = 1448 , SYSZ_INS_MSTA = 1449 , SYSZ_INS_MVCDK = 1450 , SYSZ_INS_MVCIN = 1451 , SYSZ_INS_MVCK = 1452 , SYSZ_INS_MVCL = 1453 , SYSZ_INS_MVCLE = 1454 , SYSZ_INS_MVCLU = 1455 , SYSZ_INS_MVCOS = 1456 , SYSZ_INS_MVCP = 1457 , SYSZ_INS_MVCS = 1458 , SYSZ_INS_MVCSK = 1459 , SYSZ_INS_MVN = 1460 , SYSZ_INS_MVO = 1461 , SYSZ_INS_MVPG = 1462 , SYSZ_INS_MVZ = 1463 , SYSZ_INS_MXD = 1464 , SYSZ_INS_MXDR = 1465 , SYSZ_INS_MXR = 1466 , SYSZ_INS_MXTR = 1467 , SYSZ_INS_MXTRA = 1468 , SYSZ_INS_MY = 1469 , SYSZ_INS_MYH = 1470 , SYSZ_INS_MYHR = 1471 , SYSZ_INS_MYL = 1472 , SYSZ_INS_MYLR = 1473 , SYSZ_INS_MYR = 1474 , SYSZ_INS_NIAI = 1475 , SYSZ_INS_NTSTG = 1476 , SYSZ_INS_PACK = 1477 , SYSZ_INS_PALB = 1478 , SYSZ_INS_PC = 1479 , SYSZ_INS_PCC = 1480 , SYSZ_INS_PCKMO = 1481 , SYSZ_INS_PFMF = 1482 , SYSZ_INS_PFPO = 1483 , SYSZ_INS_PGIN = 1484 , SYSZ_INS_PGOUT = 1485 , SYSZ_INS_PKA = 1486 , SYSZ_INS_PKU = 1487 , SYSZ_INS_PLO = 1488 , SYSZ_INS_POPCNT = 1489 , SYSZ_INS_PPA = 1490 , SYSZ_INS_PPNO = 1491 , SYSZ_INS_PR = 1492 , SYSZ_INS_PRNO = 1493 , SYSZ_INS_PT = 1494 , SYSZ_INS_PTF = 1495 , SYSZ_INS_PTFF = 1496 , SYSZ_INS_PTI = 1497 , SYSZ_INS_PTLB = 1498 , SYSZ_INS_QADTR = 1499 , SYSZ_INS_QAXTR = 1500 , SYSZ_INS_QCTRI = 1501 , SYSZ_INS_QSI = 1502 , SYSZ_INS_RCHP = 1503 , SYSZ_INS_RISBGN = 1504 , SYSZ_INS_RP = 1505 , SYSZ_INS_RRBE = 1506 , SYSZ_INS_RRBM = 1507 , SYSZ_INS_RRDTR = 1508 , SYSZ_INS_RRXTR = 1509 , SYSZ_INS_RSCH = 1510 , SYSZ_INS_SAC = 1511 , SYSZ_INS_SACF = 1512 , SYSZ_INS_SAL = 1513 , SYSZ_INS_SAM24 = 1514 , SYSZ_INS_SAM31 = 1515 , SYSZ_INS_SAM64 = 1516 , SYSZ_INS_SAR = 1517 , SYSZ_INS_SCCTR = 1518 , SYSZ_INS_SCHM = 1519 , SYSZ_INS_SCK = 1520 , SYSZ_INS_SCKC = 1521 , SYSZ_INS_SCKPF = 1522 , SYSZ_INS_SD = 1523 , SYSZ_INS_SDR = 1524 , SYSZ_INS_SDTR = 1525 , SYSZ_INS_SDTRA = 1526 , SYSZ_INS_SE = 1527 , SYSZ_INS_SER = 1528 , SYSZ_INS_SFASR = 1529 , SYSZ_INS_SFPC = 1530 , SYSZ_INS_SGH = 1531 , SYSZ_INS_SHHHR = 1532 , SYSZ_INS_SHHLR = 1533 , SYSZ_INS_SIE = 1534 , SYSZ_INS_SIGA = 1535 , SYSZ_INS_SIGP = 1536 , SYSZ_INS_SLA = 1537 , SYSZ_INS_SLAG = 1538 , SYSZ_INS_SLAK = 1539 , SYSZ_INS_SLDA = 1540 , SYSZ_INS_SLDL = 1541 , SYSZ_INS_SLDT = 1542 , SYSZ_INS_SLHHHR = 1543 , SYSZ_INS_SLHHLR = 1544 , SYSZ_INS_SLXT = 1545 , SYSZ_INS_SP = 1546 , SYSZ_INS_SPCTR = 1547 , SYSZ_INS_SPKA = 1548 , SYSZ_INS_SPM = 1549 , SYSZ_INS_SPT = 1550 , SYSZ_INS_SPX = 1551 , SYSZ_INS_SQD = 1552 , SYSZ_INS_SQDR = 1553 , SYSZ_INS_SQE = 1554 , SYSZ_INS_SQER = 1555 , SYSZ_INS_SQXR = 1556 , SYSZ_INS_SRDA = 1557 , SYSZ_INS_SRDL = 1558 , SYSZ_INS_SRDT = 1559 , SYSZ_INS_SRNM = 1560 , SYSZ_INS_SRNMB = 1561 , SYSZ_INS_SRNMT = 1562 , SYSZ_INS_SRP = 1563 , SYSZ_INS_SRSTU = 1564 , SYSZ_INS_SRXT = 1565 , SYSZ_INS_SSAIR = 1566 , SYSZ_INS_SSAR = 1567 , SYSZ_INS_SSCH = 1568 , SYSZ_INS_SSKE = 1569 , SYSZ_INS_SSM = 1570 , SYSZ_INS_STAM = 1571 , SYSZ_INS_STAMY = 1572 , SYSZ_INS_STAP = 1573 , SYSZ_INS_STCK = 1574 , SYSZ_INS_STCKC = 1575 , SYSZ_INS_STCKE = 1576 , SYSZ_INS_STCKF = 1577 , SYSZ_INS_STCM = 1578 , SYSZ_INS_STCMH = 1579 , SYSZ_INS_STCMY = 1580 , SYSZ_INS_STCPS = 1581 , SYSZ_INS_STCRW = 1582 , SYSZ_INS_STCTG = 1583 , SYSZ_INS_STCTL = 1584 , SYSZ_INS_STFL = 1585 , SYSZ_INS_STFLE = 1586 , SYSZ_INS_STFPC = 1587 , SYSZ_INS_STGSC = 1588 , SYSZ_INS_STIDP = 1589 , SYSZ_INS_STM = 1590 , SYSZ_INS_STMH = 1591 , SYSZ_INS_STMY = 1592 , SYSZ_INS_STNSM = 1593 , SYSZ_INS_STOCFH = 1594 , SYSZ_INS_STOCFHE = 1595 , SYSZ_INS_STOCFHH = 1596 , SYSZ_INS_STOCFHHE = 1597 , SYSZ_INS_STOCFHL = 1598 , SYSZ_INS_STOCFHLE = 1599 , SYSZ_INS_STOCFHLH = 1600 , SYSZ_INS_STOCFHM = 1601 , SYSZ_INS_STOCFHNE = 1602 , SYSZ_INS_STOCFHNH = 1603 , SYSZ_INS_STOCFHNHE = 1604 , SYSZ_INS_STOCFHNL = 1605 , SYSZ_INS_STOCFHNLE = 1606 , SYSZ_INS_STOCFHNLH = 1607 , SYSZ_INS_STOCFHNM = 1608 , SYSZ_INS_STOCFHNO = 1609 , SYSZ_INS_STOCFHNP = 1610 , SYSZ_INS_STOCFHNZ = 1611 , SYSZ_INS_STOCFHO = 1612 , SYSZ_INS_STOCFHP = 1613 , SYSZ_INS_STOCFHZ = 1614 , SYSZ_INS_STOCGM = 1615 , SYSZ_INS_STOCGNM = 1616 , SYSZ_INS_STOCGNP = 1617 , SYSZ_INS_STOCGNZ = 1618 , SYSZ_INS_STOCGP = 1619 , SYSZ_INS_STOCGZ = 1620 , SYSZ_INS_STOCM = 1621 , SYSZ_INS_STOCNM = 1622 , SYSZ_INS_STOCNP = 1623 , SYSZ_INS_STOCNZ = 1624 , SYSZ_INS_STOCP = 1625 , SYSZ_INS_STOCZ = 1626 , SYSZ_INS_STOSM = 1627 , SYSZ_INS_STPQ = 1628 , SYSZ_INS_STPT = 1629 , SYSZ_INS_STPX = 1630 , SYSZ_INS_STRAG = 1631 , SYSZ_INS_STRVH = 1632 , SYSZ_INS_STSCH = 1633 , SYSZ_INS_STSI = 1634 , SYSZ_INS_STURA = 1635 , SYSZ_INS_STURG = 1636 , SYSZ_INS_SU = 1637 , SYSZ_INS_SUR = 1638 , SYSZ_INS_SVC = 1639 , SYSZ_INS_SW = 1640 , SYSZ_INS_SWR = 1641 , SYSZ_INS_SXR = 1642 , SYSZ_INS_SXTR = 1643 , SYSZ_INS_SXTRA = 1644 , SYSZ_INS_TABORT = 1645 , SYSZ_INS_TAM = 1646 , SYSZ_INS_TAR = 1647 , SYSZ_INS_TB = 1648 , SYSZ_INS_TBDR = 1649 , SYSZ_INS_TBEDR = 1650 , SYSZ_INS_TBEGIN = 1651 , SYSZ_INS_TBEGINC = 1652 , SYSZ_INS_TCDB = 1653 , SYSZ_INS_TCEB = 1654 , SYSZ_INS_TCXB = 1655 , SYSZ_INS_TDCDT = 1656 , SYSZ_INS_TDCET = 1657 , SYSZ_INS_TDCXT = 1658 , SYSZ_INS_TDGDT = 1659 , SYSZ_INS_TDGET = 1660 , SYSZ_INS_TDGXT = 1661 , SYSZ_INS_TEND = 1662 , SYSZ_INS_THDER = 1663 , SYSZ_INS_THDR = 1664 , SYSZ_INS_TP = 1665 , SYSZ_INS_TPI = 1666 , SYSZ_INS_TPROT = 1667 , SYSZ_INS_TR = 1668 , SYSZ_INS_TRACE = 1669 , SYSZ_INS_TRACG = 1670 , SYSZ_INS_TRAP2 = 1671 , SYSZ_INS_TRAP4 = 1672 , SYSZ_INS_TRE = 1673 , SYSZ_INS_TROO = 1674 , SYSZ_INS_TROT = 1675 , SYSZ_INS_TRT = 1676 , SYSZ_INS_TRTE = 1677 , SYSZ_INS_TRTO = 1678 , SYSZ_INS_TRTR = 1679 , SYSZ_INS_TRTRE = 1680 , SYSZ_INS_TRTT = 1681 , SYSZ_INS_TS = 1682 , SYSZ_INS_TSCH = 1683 , SYSZ_INS_UNPK = 1684 , SYSZ_INS_UNPKA = 1685 , SYSZ_INS_UNPKU = 1686 , SYSZ_INS_UPT = 1687 , SYSZ_INS_VA = 1688 , SYSZ_INS_VAB = 1689 , SYSZ_INS_VAC = 1690 , SYSZ_INS_VACC = 1691 , SYSZ_INS_VACCB = 1692 , SYSZ_INS_VACCC = 1693 , SYSZ_INS_VACCCQ = 1694 , SYSZ_INS_VACCF = 1695 , SYSZ_INS_VACCG = 1696 , SYSZ_INS_VACCH = 1697 , SYSZ_INS_VACCQ = 1698 , SYSZ_INS_VACQ = 1699 , SYSZ_INS_VAF = 1700 , SYSZ_INS_VAG = 1701 , SYSZ_INS_VAH = 1702 , SYSZ_INS_VAP = 1703 , SYSZ_INS_VAQ = 1704 , SYSZ_INS_VAVG = 1705 , SYSZ_INS_VAVGB = 1706 , SYSZ_INS_VAVGF = 1707 , SYSZ_INS_VAVGG = 1708 , SYSZ_INS_VAVGH = 1709 , SYSZ_INS_VAVGL = 1710 , SYSZ_INS_VAVGLB = 1711 , SYSZ_INS_VAVGLF = 1712 , SYSZ_INS_VAVGLG = 1713 , SYSZ_INS_VAVGLH = 1714 , SYSZ_INS_VBPERM = 1715 , SYSZ_INS_VCDG = 1716 , SYSZ_INS_VCDGB = 1717 , SYSZ_INS_VCDLG = 1718 , SYSZ_INS_VCDLGB = 1719 , SYSZ_INS_VCEQ = 1720 , SYSZ_INS_VCEQB = 1721 , SYSZ_INS_VCEQBS = 1722 , SYSZ_INS_VCEQF = 1723 , SYSZ_INS_VCEQFS = 1724 , SYSZ_INS_VCEQG = 1725 , SYSZ_INS_VCEQGS = 1726 , SYSZ_INS_VCEQH = 1727 , SYSZ_INS_VCEQHS = 1728 , SYSZ_INS_VCGD = 1729 , SYSZ_INS_VCGDB = 1730 , SYSZ_INS_VCH = 1731 , SYSZ_INS_VCHB = 1732 , SYSZ_INS_VCHBS = 1733 , SYSZ_INS_VCHF = 1734 , SYSZ_INS_VCHFS = 1735 , SYSZ_INS_VCHG = 1736 , SYSZ_INS_VCHGS = 1737 , SYSZ_INS_VCHH = 1738 , SYSZ_INS_VCHHS = 1739 , SYSZ_INS_VCHL = 1740 , SYSZ_INS_VCHLB = 1741 , SYSZ_INS_VCHLBS = 1742 , SYSZ_INS_VCHLF = 1743 , SYSZ_INS_VCHLFS = 1744 , SYSZ_INS_VCHLG = 1745 , SYSZ_INS_VCHLGS = 1746 , SYSZ_INS_VCHLH = 1747 , SYSZ_INS_VCHLHS = 1748 , SYSZ_INS_VCKSM = 1749 , SYSZ_INS_VCLGD = 1750 , SYSZ_INS_VCLGDB = 1751 , SYSZ_INS_VCLZ = 1752 , SYSZ_INS_VCLZB = 1753 , SYSZ_INS_VCLZF = 1754 , SYSZ_INS_VCLZG = 1755 , SYSZ_INS_VCLZH = 1756 , SYSZ_INS_VCP = 1757 , SYSZ_INS_VCTZ = 1758 , SYSZ_INS_VCTZB = 1759 , SYSZ_INS_VCTZF = 1760 , SYSZ_INS_VCTZG = 1761 , SYSZ_INS_VCTZH = 1762 , SYSZ_INS_VCVB = 1763 , SYSZ_INS_VCVBG = 1764 , SYSZ_INS_VCVD = 1765 , SYSZ_INS_VCVDG = 1766 , SYSZ_INS_VDP = 1767 , SYSZ_INS_VEC = 1768 , SYSZ_INS_VECB = 1769 , SYSZ_INS_VECF = 1770 , SYSZ_INS_VECG = 1771 , SYSZ_INS_VECH = 1772 , SYSZ_INS_VECL = 1773 , SYSZ_INS_VECLB = 1774 , SYSZ_INS_VECLF = 1775 , SYSZ_INS_VECLG = 1776 , SYSZ_INS_VECLH = 1777 , SYSZ_INS_VERIM = 1778 , SYSZ_INS_VERIMB = 1779 , SYSZ_INS_VERIMF = 1780 , SYSZ_INS_VERIMG = 1781 , SYSZ_INS_VERIMH = 1782 , SYSZ_INS_VERLL = 1783 , SYSZ_INS_VERLLB = 1784 , SYSZ_INS_VERLLF = 1785 , SYSZ_INS_VERLLG = 1786 , SYSZ_INS_VERLLH = 1787 , SYSZ_INS_VERLLV = 1788 , SYSZ_INS_VERLLVB = 1789 , SYSZ_INS_VERLLVF = 1790 , SYSZ_INS_VERLLVG = 1791 , SYSZ_INS_VERLLVH = 1792 , SYSZ_INS_VESL = 1793 , SYSZ_INS_VESLB = 1794 , SYSZ_INS_VESLF = 1795 , SYSZ_INS_VESLG = 1796 , SYSZ_INS_VESLH = 1797 , SYSZ_INS_VESLV = 1798 , SYSZ_INS_VESLVB = 1799 , SYSZ_INS_VESLVF = 1800 , SYSZ_INS_VESLVG = 1801 , SYSZ_INS_VESLVH = 1802 , SYSZ_INS_VESRA = 1803 , SYSZ_INS_VESRAB = 1804 , SYSZ_INS_VESRAF = 1805 , SYSZ_INS_VESRAG = 1806 , SYSZ_INS_VESRAH = 1807 , SYSZ_INS_VESRAV = 1808 , SYSZ_INS_VESRAVB = 1809 , SYSZ_INS_VESRAVF = 1810 , SYSZ_INS_VESRAVG = 1811 , SYSZ_INS_VESRAVH = 1812 , SYSZ_INS_VESRL = 1813 , SYSZ_INS_VESRLB = 1814 , SYSZ_INS_VESRLF = 1815 , SYSZ_INS_VESRLG = 1816 , SYSZ_INS_VESRLH = 1817 , SYSZ_INS_VESRLV = 1818 , SYSZ_INS_VESRLVB = 1819 , SYSZ_INS_VESRLVF = 1820 , SYSZ_INS_VESRLVG = 1821 , SYSZ_INS_VESRLVH = 1822 , SYSZ_INS_VFA = 1823 , SYSZ_INS_VFADB = 1824 , SYSZ_INS_VFAE = 1825 , SYSZ_INS_VFAEB = 1826 , SYSZ_INS_VFAEBS = 1827 , SYSZ_INS_VFAEF = 1828 , SYSZ_INS_VFAEFS = 1829 , SYSZ_INS_VFAEH = 1830 , SYSZ_INS_VFAEHS = 1831 , SYSZ_INS_VFAEZB = 1832 , SYSZ_INS_VFAEZBS = 1833 , SYSZ_INS_VFAEZF = 1834 , SYSZ_INS_VFAEZFS = 1835 , SYSZ_INS_VFAEZH = 1836 , SYSZ_INS_VFAEZHS = 1837 , SYSZ_INS_VFASB = 1838 , SYSZ_INS_VFCE = 1839 , SYSZ_INS_VFCEDB = 1840 , SYSZ_INS_VFCEDBS = 1841 , SYSZ_INS_VFCESB = 1842 , SYSZ_INS_VFCESBS = 1843 , SYSZ_INS_VFCH = 1844 , SYSZ_INS_VFCHDB = 1845 , SYSZ_INS_VFCHDBS = 1846 , SYSZ_INS_VFCHE = 1847 , SYSZ_INS_VFCHEDB = 1848 , SYSZ_INS_VFCHEDBS = 1849 , SYSZ_INS_VFCHESB = 1850 , SYSZ_INS_VFCHESBS = 1851 , SYSZ_INS_VFCHSB = 1852 , SYSZ_INS_VFCHSBS = 1853 , SYSZ_INS_VFD = 1854 , SYSZ_INS_VFDDB = 1855 , SYSZ_INS_VFDSB = 1856 , SYSZ_INS_VFEE = 1857 , SYSZ_INS_VFEEB = 1858 , SYSZ_INS_VFEEBS = 1859 , SYSZ_INS_VFEEF = 1860 , SYSZ_INS_VFEEFS = 1861 , SYSZ_INS_VFEEH = 1862 , SYSZ_INS_VFEEHS = 1863 , SYSZ_INS_VFEEZB = 1864 , SYSZ_INS_VFEEZBS = 1865 , SYSZ_INS_VFEEZF = 1866 , SYSZ_INS_VFEEZFS = 1867 , SYSZ_INS_VFEEZH = 1868 , SYSZ_INS_VFEEZHS = 1869 , SYSZ_INS_VFENE = 1870 , SYSZ_INS_VFENEB = 1871 , SYSZ_INS_VFENEBS = 1872 , SYSZ_INS_VFENEF = 1873 , SYSZ_INS_VFENEFS = 1874 , SYSZ_INS_VFENEH = 1875 , SYSZ_INS_VFENEHS = 1876 , SYSZ_INS_VFENEZB = 1877 , SYSZ_INS_VFENEZBS = 1878 , SYSZ_INS_VFENEZF = 1879 , SYSZ_INS_VFENEZFS = 1880 , SYSZ_INS_VFENEZH = 1881 , SYSZ_INS_VFENEZHS = 1882 , SYSZ_INS_VFI = 1883 , SYSZ_INS_VFIDB = 1884 , SYSZ_INS_VFISB = 1885 , SYSZ_INS_VFKEDB = 1886 , SYSZ_INS_VFKEDBS = 1887 , SYSZ_INS_VFKESB = 1888 , SYSZ_INS_VFKESBS = 1889 , SYSZ_INS_VFKHDB = 1890 , SYSZ_INS_VFKHDBS = 1891 , SYSZ_INS_VFKHEDB = 1892 , SYSZ_INS_VFKHEDBS = 1893 , SYSZ_INS_VFKHESB = 1894 , SYSZ_INS_VFKHESBS = 1895 , SYSZ_INS_VFKHSB = 1896 , SYSZ_INS_VFKHSBS = 1897 , SYSZ_INS_VFLCDB = 1898 , SYSZ_INS_VFLCSB = 1899 , SYSZ_INS_VFLL = 1900 , SYSZ_INS_VFLLS = 1901 , SYSZ_INS_VFLNDB = 1902 , SYSZ_INS_VFLNSB = 1903 , SYSZ_INS_VFLPDB = 1904 , SYSZ_INS_VFLPSB = 1905 , SYSZ_INS_VFLR = 1906 , SYSZ_INS_VFLRD = 1907 , SYSZ_INS_VFM = 1908 , SYSZ_INS_VFMA = 1909 , SYSZ_INS_VFMADB = 1910 , SYSZ_INS_VFMASB = 1911 , SYSZ_INS_VFMAX = 1912 , SYSZ_INS_VFMAXDB = 1913 , SYSZ_INS_VFMAXSB = 1914 , SYSZ_INS_VFMDB = 1915 , SYSZ_INS_VFMIN = 1916 , SYSZ_INS_VFMINDB = 1917 , SYSZ_INS_VFMINSB = 1918 , SYSZ_INS_VFMS = 1919 , SYSZ_INS_VFMSB = 1920 , SYSZ_INS_VFMSDB = 1921 , SYSZ_INS_VFMSSB = 1922 , SYSZ_INS_VFNMA = 1923 , SYSZ_INS_VFNMADB = 1924 , SYSZ_INS_VFNMASB = 1925 , SYSZ_INS_VFNMS = 1926 , SYSZ_INS_VFNMSDB = 1927 , SYSZ_INS_VFNMSSB = 1928 , SYSZ_INS_VFPSO = 1929 , SYSZ_INS_VFPSODB = 1930 , SYSZ_INS_VFPSOSB = 1931 , SYSZ_INS_VFS = 1932 , SYSZ_INS_VFSDB = 1933 , SYSZ_INS_VFSQ = 1934 , SYSZ_INS_VFSQDB = 1935 , SYSZ_INS_VFSQSB = 1936 , SYSZ_INS_VFSSB = 1937 , SYSZ_INS_VFTCI = 1938 , SYSZ_INS_VFTCIDB = 1939 , SYSZ_INS_VFTCISB = 1940 , SYSZ_INS_VGBM = 1941 , SYSZ_INS_VGEF = 1942 , SYSZ_INS_VGEG = 1943 , SYSZ_INS_VGFM = 1944 , SYSZ_INS_VGFMA = 1945 , SYSZ_INS_VGFMAB = 1946 , SYSZ_INS_VGFMAF = 1947 , SYSZ_INS_VGFMAG = 1948 , SYSZ_INS_VGFMAH = 1949 , SYSZ_INS_VGFMB = 1950 , SYSZ_INS_VGFMF = 1951 , SYSZ_INS_VGFMG = 1952 , SYSZ_INS_VGFMH = 1953 , SYSZ_INS_VGM = 1954 , SYSZ_INS_VGMB = 1955 , SYSZ_INS_VGMF = 1956 , SYSZ_INS_VGMG = 1957 , SYSZ_INS_VGMH = 1958 , SYSZ_INS_VISTR = 1959 , SYSZ_INS_VISTRB = 1960 , SYSZ_INS_VISTRBS = 1961 , SYSZ_INS_VISTRF = 1962 , SYSZ_INS_VISTRFS = 1963 , SYSZ_INS_VISTRH = 1964 , SYSZ_INS_VISTRHS = 1965 , SYSZ_INS_VL = 1966 , SYSZ_INS_VLBB = 1967 , SYSZ_INS_VLC = 1968 , SYSZ_INS_VLCB = 1969 , SYSZ_INS_VLCF = 1970 , SYSZ_INS_VLCG = 1971 , SYSZ_INS_VLCH = 1972 , SYSZ_INS_VLDE = 1973 , SYSZ_INS_VLDEB = 1974 , SYSZ_INS_VLEB = 1975 , SYSZ_INS_VLED = 1976 , SYSZ_INS_VLEDB = 1977 , SYSZ_INS_VLEF = 1978 , SYSZ_INS_VLEG = 1979 , SYSZ_INS_VLEH = 1980 , SYSZ_INS_VLEIB = 1981 , SYSZ_INS_VLEIF = 1982 , SYSZ_INS_VLEIG = 1983 , SYSZ_INS_VLEIH = 1984 , SYSZ_INS_VLGV = 1985 , SYSZ_INS_VLGVB = 1986 , SYSZ_INS_VLGVF = 1987 , SYSZ_INS_VLGVG = 1988 , SYSZ_INS_VLGVH = 1989 , SYSZ_INS_VLIP = 1990 , SYSZ_INS_VLL = 1991 , SYSZ_INS_VLLEZ = 1992 , SYSZ_INS_VLLEZB = 1993 , SYSZ_INS_VLLEZF = 1994 , SYSZ_INS_VLLEZG = 1995 , SYSZ_INS_VLLEZH = 1996 , SYSZ_INS_VLLEZLF = 1997 , SYSZ_INS_VLM = 1998 , SYSZ_INS_VLP = 1999 , SYSZ_INS_VLPB = 2000 , SYSZ_INS_VLPF = 2001 , SYSZ_INS_VLPG = 2002 , SYSZ_INS_VLPH = 2003 , SYSZ_INS_VLR = 2004 , SYSZ_INS_VLREP = 2005 , SYSZ_INS_VLREPB = 2006 , SYSZ_INS_VLREPF = 2007 , SYSZ_INS_VLREPG = 2008 , SYSZ_INS_VLREPH = 2009 , SYSZ_INS_VLRL = 2010 , SYSZ_INS_VLRLR = 2011 , SYSZ_INS_VLVG = 2012 , SYSZ_INS_VLVGB = 2013 , SYSZ_INS_VLVGF = 2014 , SYSZ_INS_VLVGG = 2015 , SYSZ_INS_VLVGH = 2016 , SYSZ_INS_VLVGP = 2017 , SYSZ_INS_VMAE = 2018 , SYSZ_INS_VMAEB = 2019 , SYSZ_INS_VMAEF = 2020 , SYSZ_INS_VMAEH = 2021 , SYSZ_INS_VMAH = 2022 , SYSZ_INS_VMAHB = 2023 , SYSZ_INS_VMAHF = 2024 , SYSZ_INS_VMAHH = 2025 , SYSZ_INS_VMAL = 2026 , SYSZ_INS_VMALB = 2027 , SYSZ_INS_VMALE = 2028 , SYSZ_INS_VMALEB = 2029 , SYSZ_INS_VMALEF = 2030 , SYSZ_INS_VMALEH = 2031 , SYSZ_INS_VMALF = 2032 , SYSZ_INS_VMALH = 2033 , SYSZ_INS_VMALHB = 2034 , SYSZ_INS_VMALHF = 2035 , SYSZ_INS_VMALHH = 2036 , SYSZ_INS_VMALHW = 2037 , SYSZ_INS_VMALO = 2038 , SYSZ_INS_VMALOB = 2039 , SYSZ_INS_VMALOF = 2040 , SYSZ_INS_VMALOH = 2041 , SYSZ_INS_VMAO = 2042 , SYSZ_INS_VMAOB = 2043 , SYSZ_INS_VMAOF = 2044 , SYSZ_INS_VMAOH = 2045 , SYSZ_INS_VME = 2046 , SYSZ_INS_VMEB = 2047 , SYSZ_INS_VMEF = 2048 , SYSZ_INS_VMEH = 2049 , SYSZ_INS_VMH = 2050 , SYSZ_INS_VMHB = 2051 , SYSZ_INS_VMHF = 2052 , SYSZ_INS_VMHH = 2053 , SYSZ_INS_VML = 2054 , SYSZ_INS_VMLB = 2055 , SYSZ_INS_VMLE = 2056 , SYSZ_INS_VMLEB = 2057 , SYSZ_INS_VMLEF = 2058 , SYSZ_INS_VMLEH = 2059 , SYSZ_INS_VMLF = 2060 , SYSZ_INS_VMLH = 2061 , SYSZ_INS_VMLHB = 2062 , SYSZ_INS_VMLHF = 2063 , SYSZ_INS_VMLHH = 2064 , SYSZ_INS_VMLHW = 2065 , SYSZ_INS_VMLO = 2066 , SYSZ_INS_VMLOB = 2067 , SYSZ_INS_VMLOF = 2068 , SYSZ_INS_VMLOH = 2069 , SYSZ_INS_VMN = 2070 , SYSZ_INS_VMNB = 2071 , SYSZ_INS_VMNF = 2072 , SYSZ_INS_VMNG = 2073 , SYSZ_INS_VMNH = 2074 , SYSZ_INS_VMNL = 2075 , SYSZ_INS_VMNLB = 2076 , SYSZ_INS_VMNLF = 2077 , SYSZ_INS_VMNLG = 2078 , SYSZ_INS_VMNLH = 2079 , SYSZ_INS_VMO = 2080 , SYSZ_INS_VMOB = 2081 , SYSZ_INS_VMOF = 2082 , SYSZ_INS_VMOH = 2083 , SYSZ_INS_VMP = 2084 , SYSZ_INS_VMRH = 2085 , SYSZ_INS_VMRHB = 2086 , SYSZ_INS_VMRHF = 2087 , SYSZ_INS_VMRHG = 2088 , SYSZ_INS_VMRHH = 2089 , SYSZ_INS_VMRL = 2090 , SYSZ_INS_VMRLB = 2091 , SYSZ_INS_VMRLF = 2092 , SYSZ_INS_VMRLG = 2093 , SYSZ_INS_VMRLH = 2094 , SYSZ_INS_VMSL = 2095 , SYSZ_INS_VMSLG = 2096 , SYSZ_INS_VMSP = 2097 , SYSZ_INS_VMX = 2098 , SYSZ_INS_VMXB = 2099 , SYSZ_INS_VMXF = 2100 , SYSZ_INS_VMXG = 2101 , SYSZ_INS_VMXH = 2102 , SYSZ_INS_VMXL = 2103 , SYSZ_INS_VMXLB = 2104 , SYSZ_INS_VMXLF = 2105 , SYSZ_INS_VMXLG = 2106 , SYSZ_INS_VMXLH = 2107 , SYSZ_INS_VN = 2108 , SYSZ_INS_VNC = 2109 , SYSZ_INS_VNN = 2110 , SYSZ_INS_VNO = 2111 , SYSZ_INS_VNX = 2112 , SYSZ_INS_VO = 2113 , SYSZ_INS_VOC = 2114 , SYSZ_INS_VONE = 2115 , SYSZ_INS_VPDI = 2116 , SYSZ_INS_VPERM = 2117 , SYSZ_INS_VPK = 2118 , SYSZ_INS_VPKF = 2119 , SYSZ_INS_VPKG = 2120 , SYSZ_INS_VPKH = 2121 , SYSZ_INS_VPKLS = 2122 , SYSZ_INS_VPKLSF = 2123 , SYSZ_INS_VPKLSFS = 2124 , SYSZ_INS_VPKLSG = 2125 , SYSZ_INS_VPKLSGS = 2126 , SYSZ_INS_VPKLSH = 2127 , SYSZ_INS_VPKLSHS = 2128 , SYSZ_INS_VPKS = 2129 , SYSZ_INS_VPKSF = 2130 , SYSZ_INS_VPKSFS = 2131 , SYSZ_INS_VPKSG = 2132 , SYSZ_INS_VPKSGS = 2133 , SYSZ_INS_VPKSH = 2134 , SYSZ_INS_VPKSHS = 2135 , SYSZ_INS_VPKZ = 2136 , SYSZ_INS_VPOPCT = 2137 , SYSZ_INS_VPOPCTB = 2138 , SYSZ_INS_VPOPCTF = 2139 , SYSZ_INS_VPOPCTG = 2140 , SYSZ_INS_VPOPCTH = 2141 , SYSZ_INS_VPSOP = 2142 , SYSZ_INS_VREP = 2143 , SYSZ_INS_VREPB = 2144 , SYSZ_INS_VREPF = 2145 , SYSZ_INS_VREPG = 2146 , SYSZ_INS_VREPH = 2147 , SYSZ_INS_VREPI = 2148 , SYSZ_INS_VREPIB = 2149 , SYSZ_INS_VREPIF = 2150 , SYSZ_INS_VREPIG = 2151 , SYSZ_INS_VREPIH = 2152 , SYSZ_INS_VRP = 2153 , SYSZ_INS_VS = 2154 , SYSZ_INS_VSB = 2155 , SYSZ_INS_VSBCBI = 2156 , SYSZ_INS_VSBCBIQ = 2157 , SYSZ_INS_VSBI = 2158 , SYSZ_INS_VSBIQ = 2159 , SYSZ_INS_VSCBI = 2160 , SYSZ_INS_VSCBIB = 2161 , SYSZ_INS_VSCBIF = 2162 , SYSZ_INS_VSCBIG = 2163 , SYSZ_INS_VSCBIH = 2164 , SYSZ_INS_VSCBIQ = 2165 , SYSZ_INS_VSCEF = 2166 , SYSZ_INS_VSCEG = 2167 , SYSZ_INS_VSDP = 2168 , SYSZ_INS_VSEG = 2169 , SYSZ_INS_VSEGB = 2170 , SYSZ_INS_VSEGF = 2171 , SYSZ_INS_VSEGH = 2172 , SYSZ_INS_VSEL = 2173 , SYSZ_INS_VSF = 2174 , SYSZ_INS_VSG = 2175 , SYSZ_INS_VSH = 2176 , SYSZ_INS_VSL = 2177 , SYSZ_INS_VSLB = 2178 , SYSZ_INS_VSLDB = 2179 , SYSZ_INS_VSP = 2180 , SYSZ_INS_VSQ = 2181 , SYSZ_INS_VSRA = 2182 , SYSZ_INS_VSRAB = 2183 , SYSZ_INS_VSRL = 2184 , SYSZ_INS_VSRLB = 2185 , SYSZ_INS_VSRP = 2186 , SYSZ_INS_VST = 2187 , SYSZ_INS_VSTEB = 2188 , SYSZ_INS_VSTEF = 2189 , SYSZ_INS_VSTEG = 2190 , SYSZ_INS_VSTEH = 2191 , SYSZ_INS_VSTL = 2192 , SYSZ_INS_VSTM = 2193 , SYSZ_INS_VSTRC = 2194 , SYSZ_INS_VSTRCB = 2195 , SYSZ_INS_VSTRCBS = 2196 , SYSZ_INS_VSTRCF = 2197 , SYSZ_INS_VSTRCFS = 2198 , SYSZ_INS_VSTRCH = 2199 , SYSZ_INS_VSTRCHS = 2200 , SYSZ_INS_VSTRCZB = 2201 , SYSZ_INS_VSTRCZBS = 2202 , SYSZ_INS_VSTRCZF = 2203 , SYSZ_INS_VSTRCZFS = 2204 , SYSZ_INS_VSTRCZH = 2205 , SYSZ_INS_VSTRCZHS = 2206 , SYSZ_INS_VSTRL = 2207 , SYSZ_INS_VSTRLR = 2208 , SYSZ_INS_VSUM = 2209 , SYSZ_INS_VSUMB = 2210 , SYSZ_INS_VSUMG = 2211 , SYSZ_INS_VSUMGF = 2212 , SYSZ_INS_VSUMGH = 2213 , SYSZ_INS_VSUMH = 2214 , SYSZ_INS_VSUMQ = 2215 , SYSZ_INS_VSUMQF = 2216 , SYSZ_INS_VSUMQG = 2217 , SYSZ_INS_VTM = 2218 , SYSZ_INS_VTP = 2219 , SYSZ_INS_VUPH = 2220 , SYSZ_INS_VUPHB = 2221 , SYSZ_INS_VUPHF = 2222 , SYSZ_INS_VUPHH = 2223 , SYSZ_INS_VUPKZ = 2224 , SYSZ_INS_VUPL = 2225 , SYSZ_INS_VUPLB = 2226 , SYSZ_INS_VUPLF = 2227 , SYSZ_INS_VUPLH = 2228 , SYSZ_INS_VUPLHB = 2229 , SYSZ_INS_VUPLHF = 2230 , SYSZ_INS_VUPLHH = 2231 , SYSZ_INS_VUPLHW = 2232 , SYSZ_INS_VUPLL = 2233 , SYSZ_INS_VUPLLB = 2234 , SYSZ_INS_VUPLLF = 2235 , SYSZ_INS_VUPLLH = 2236 , SYSZ_INS_VX = 2237 , SYSZ_INS_VZERO = 2238 , SYSZ_INS_WCDGB = 2239 , SYSZ_INS_WCDLGB = 2240 , SYSZ_INS_WCGDB = 2241 , SYSZ_INS_WCLGDB = 2242 , SYSZ_INS_WFADB = 2243 , SYSZ_INS_WFASB = 2244 , SYSZ_INS_WFAXB = 2245 , SYSZ_INS_WFC = 2246 , SYSZ_INS_WFCDB = 2247 , SYSZ_INS_WFCEDB = 2248 , SYSZ_INS_WFCEDBS = 2249 , SYSZ_INS_WFCESB = 2250 , SYSZ_INS_WFCESBS = 2251 , SYSZ_INS_WFCEXB = 2252 , SYSZ_INS_WFCEXBS = 2253 , SYSZ_INS_WFCHDB = 2254 , SYSZ_INS_WFCHDBS = 2255 , SYSZ_INS_WFCHEDB = 2256 , SYSZ_INS_WFCHEDBS = 2257 , SYSZ_INS_WFCHESB = 2258 , SYSZ_INS_WFCHESBS = 2259 , SYSZ_INS_WFCHEXB = 2260 , SYSZ_INS_WFCHEXBS = 2261 , SYSZ_INS_WFCHSB = 2262 , SYSZ_INS_WFCHSBS = 2263 , SYSZ_INS_WFCHXB = 2264 , SYSZ_INS_WFCHXBS = 2265 , SYSZ_INS_WFCSB = 2266 , SYSZ_INS_WFCXB = 2267 , SYSZ_INS_WFDDB = 2268 , SYSZ_INS_WFDSB = 2269 , SYSZ_INS_WFDXB = 2270 , SYSZ_INS_WFIDB = 2271 , SYSZ_INS_WFISB = 2272 , SYSZ_INS_WFIXB = 2273 , SYSZ_INS_WFK = 2274 , SYSZ_INS_WFKDB = 2275 , SYSZ_INS_WFKEDB = 2276 , SYSZ_INS_WFKEDBS = 2277 , SYSZ_INS_WFKESB = 2278 , SYSZ_INS_WFKESBS = 2279 , SYSZ_INS_WFKEXB = 2280 , SYSZ_INS_WFKEXBS = 2281 , SYSZ_INS_WFKHDB = 2282 , SYSZ_INS_WFKHDBS = 2283 , SYSZ_INS_WFKHEDB = 2284 , SYSZ_INS_WFKHEDBS = 2285 , SYSZ_INS_WFKHESB = 2286 , SYSZ_INS_WFKHESBS = 2287 , SYSZ_INS_WFKHEXB = 2288 , SYSZ_INS_WFKHEXBS = 2289 , SYSZ_INS_WFKHSB = 2290 , SYSZ_INS_WFKHSBS = 2291 , SYSZ_INS_WFKHXB = 2292 , SYSZ_INS_WFKHXBS = 2293 , SYSZ_INS_WFKSB = 2294 , SYSZ_INS_WFKXB = 2295 , SYSZ_INS_WFLCDB = 2296 , SYSZ_INS_WFLCSB = 2297 , SYSZ_INS_WFLCXB = 2298 , SYSZ_INS_WFLLD = 2299 , SYSZ_INS_WFLLS = 2300 , SYSZ_INS_WFLNDB = 2301 , SYSZ_INS_WFLNSB = 2302 , SYSZ_INS_WFLNXB = 2303 , SYSZ_INS_WFLPDB = 2304 , SYSZ_INS_WFLPSB = 2305 , SYSZ_INS_WFLPXB = 2306 , SYSZ_INS_WFLRD = 2307 , SYSZ_INS_WFLRX = 2308 , SYSZ_INS_WFMADB = 2309 , SYSZ_INS_WFMASB = 2310 , SYSZ_INS_WFMAXB = 2311 , SYSZ_INS_WFMAXDB = 2312 , SYSZ_INS_WFMAXSB = 2313 , SYSZ_INS_WFMAXXB = 2314 , SYSZ_INS_WFMDB = 2315 , SYSZ_INS_WFMINDB = 2316 , SYSZ_INS_WFMINSB = 2317 , SYSZ_INS_WFMINXB = 2318 , SYSZ_INS_WFMSB = 2319 , SYSZ_INS_WFMSDB = 2320 , SYSZ_INS_WFMSSB = 2321 , SYSZ_INS_WFMSXB = 2322 , SYSZ_INS_WFMXB = 2323 , SYSZ_INS_WFNMADB = 2324 , SYSZ_INS_WFNMASB = 2325 , SYSZ_INS_WFNMAXB = 2326 , SYSZ_INS_WFNMSDB = 2327 , SYSZ_INS_WFNMSSB = 2328 , SYSZ_INS_WFNMSXB = 2329 , SYSZ_INS_WFPSODB = 2330 , SYSZ_INS_WFPSOSB = 2331 , SYSZ_INS_WFPSOXB = 2332 , SYSZ_INS_WFSDB = 2333 , SYSZ_INS_WFSQDB = 2334 , SYSZ_INS_WFSQSB = 2335 , SYSZ_INS_WFSQXB = 2336 , SYSZ_INS_WFSSB = 2337 , SYSZ_INS_WFSXB = 2338 , SYSZ_INS_WFTCIDB = 2339 , SYSZ_INS_WFTCISB = 2340 , SYSZ_INS_WFTCIXB = 2341 , SYSZ_INS_WLDEB = 2342 , SYSZ_INS_WLEDB = 2343 , SYSZ_INS_XSCH = 2344 , SYSZ_INS_ZAP = 2345 , SYSZ_INS_ENDING = 2346 , } # [repr (u32)] # [doc = " Group of SystemZ instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn_group { # [doc = "< = CS_GRP_INVALID"] SYSZ_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SYSZ_GRP_JUMP = 1 , SYSZ_GRP_DISTINCTOPS = 128 , SYSZ_GRP_FPEXTENSION = 129 , SYSZ_GRP_HIGHWORD = 130 , SYSZ_GRP_INTERLOCKEDACCESS1 = 131 , SYSZ_GRP_LOADSTOREONCOND = 132 , SYSZ_GRP_DFPPACKEDCONVERSION = 133 , SYSZ_GRP_DFPZONEDCONVERSION = 134 , SYSZ_GRP_ENHANCEDDAT2 = 135 , SYSZ_GRP_EXECUTIONHINT = 136 , SYSZ_GRP_GUARDEDSTORAGE = 137 , SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 , SYSZ_GRP_LOADANDTRAP = 139 , SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 , SYSZ_GRP_LOADSTOREONCOND2 = 141 , SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 , SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 , SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 , SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 , SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 , SYSZ_GRP_NOVECTOR = 149 , SYSZ_GRP_POPULATIONCOUNT = 150 , SYSZ_GRP_PROCESSORASSIST = 151 , SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 , SYSZ_GRP_TRANSACTIONALEXECUTION = 153 , SYSZ_GRP_VECTOR = 154 , SYSZ_GRP_VECTORENHANCEMENTS1 = 155 , SYSZ_GRP_VECTORPACKEDDECIMAL = 156 , SYSZ_GRP_ENDING = 157 , } # [repr (u32)] # [doc = " X86 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_reg { X86_REG_INVALID = 0 , X86_REG_AH = 1 , X86_REG_AL = 2 , X86_REG_AX = 3 , X86_REG_BH = 4 , X86_REG_BL = 5 , X86_REG_BP = 6 , X86_REG_BPL = 7 , X86_REG_BX = 8 , X86_REG_CH = 9 , X86_REG_CL = 10 , X86_REG_CS = 11 , X86_REG_CX = 12 , X86_REG_DH = 13 , X86_REG_DI = 14 , X86_REG_DIL = 15 , X86_REG_DL = 16 , X86_REG_DS = 17 , X86_REG_DX = 18 , X86_REG_EAX = 19 , X86_REG_EBP = 20 , X86_REG_EBX = 21 , X86_REG_ECX = 22 , X86_REG_EDI = 23 , X86_REG_EDX = 24 , X86_REG_EFLAGS = 25 , X86_REG_EIP = 26 , X86_REG_EIZ = 27 , X86_REG_ES = 28 , X86_REG_ESI = 29 , X86_REG_ESP = 30 , X86_REG_FPSW = 31 , X86_REG_FS = 32 , X86_REG_GS = 33 , X86_REG_IP = 34 , X86_REG_RAX = 35 , X86_REG_RBP = 36 , X86_REG_RBX = 37 , X86_REG_RCX = 38 , X86_REG_RDI = 39 , X86_REG_RDX = 40 , X86_REG_RIP = 41 , X86_REG_RIZ = 42 , X86_REG_RSI = 43 , X86_REG_RSP = 44 , X86_REG_SI = 45 , X86_REG_SIL = 46 , X86_REG_SP = 47 , X86_REG_SPL = 48 , X86_REG_SS = 49 , X86_REG_CR0 = 50 , X86_REG_CR1 = 51 , X86_REG_CR2 = 52 , X86_REG_CR3 = 53 , X86_REG_CR4 = 54 , X86_REG_CR5 = 55 , X86_REG_CR6 = 56 , X86_REG_CR7 = 57 , X86_REG_CR8 = 58 , X86_REG_CR9 = 59 , X86_REG_CR10 = 60 , X86_REG_CR11 = 61 , X86_REG_CR12 = 62 , X86_REG_CR13 = 63 , X86_REG_CR14 = 64 , X86_REG_CR15 = 65 , X86_REG_DR0 = 66 , X86_REG_DR1 = 67 , X86_REG_DR2 = 68 , X86_REG_DR3 = 69 , X86_REG_DR4 = 70 , X86_REG_DR5 = 71 , X86_REG_DR6 = 72 , X86_REG_DR7 = 73 , X86_REG_DR8 = 74 , X86_REG_DR9 = 75 , X86_REG_DR10 = 76 , X86_REG_DR11 = 77 , X86_REG_DR12 = 78 , X86_REG_DR13 = 79 , X86_REG_DR14 = 80 , X86_REG_DR15 = 81 , X86_REG_FP0 = 82 , X86_REG_FP1 = 83 , X86_REG_FP2 = 84 , X86_REG_FP3 = 85 , X86_REG_FP4 = 86 , X86_REG_FP5 = 87 , X86_REG_FP6 = 88 , X86_REG_FP7 = 89 , X86_REG_K0 = 90 , X86_REG_K1 = 91 , X86_REG_K2 = 92 , X86_REG_K3 = 93 , X86_REG_K4 = 94 , X86_REG_K5 = 95 , X86_REG_K6 = 96 , X86_REG_K7 = 97 , X86_REG_MM0 = 98 , X86_REG_MM1 = 99 , X86_REG_MM2 = 100 , X86_REG_MM3 = 101 , X86_REG_MM4 = 102 , X86_REG_MM5 = 103 , X86_REG_MM6 = 104 , X86_REG_MM7 = 105 , X86_REG_R8 = 106 , X86_REG_R9 = 107 , X86_REG_R10 = 108 , X86_REG_R11 = 109 , X86_REG_R12 = 110 , X86_REG_R13 = 111 , X86_REG_R14 = 112 , X86_REG_R15 = 113 , X86_REG_ST0 = 114 , X86_REG_ST1 = 115 , X86_REG_ST2 = 116 , X86_REG_ST3 = 117 , X86_REG_ST4 = 118 , X86_REG_ST5 = 119 , X86_REG_ST6 = 120 , X86_REG_ST7 = 121 , X86_REG_XMM0 = 122 , X86_REG_XMM1 = 123 , X86_REG_XMM2 = 124 , X86_REG_XMM3 = 125 , X86_REG_XMM4 = 126 , X86_REG_XMM5 = 127 , X86_REG_XMM6 = 128 , X86_REG_XMM7 = 129 , X86_REG_XMM8 = 130 , X86_REG_XMM9 = 131 , X86_REG_XMM10 = 132 , X86_REG_XMM11 = 133 , X86_REG_XMM12 = 134 , X86_REG_XMM13 = 135 , X86_REG_XMM14 = 136 , X86_REG_XMM15 = 137 , X86_REG_XMM16 = 138 , X86_REG_XMM17 = 139 , X86_REG_XMM18 = 140 , X86_REG_XMM19 = 141 , X86_REG_XMM20 = 142 , X86_REG_XMM21 = 143 , X86_REG_XMM22 = 144 , X86_REG_XMM23 = 145 , X86_REG_XMM24 = 146 , X86_REG_XMM25 = 147 , X86_REG_XMM26 = 148 , X86_REG_XMM27 = 149 , X86_REG_XMM28 = 150 , X86_REG_XMM29 = 151 , X86_REG_XMM30 = 152 , X86_REG_XMM31 = 153 , X86_REG_YMM0 = 154 , X86_REG_YMM1 = 155 , X86_REG_YMM2 = 156 , X86_REG_YMM3 = 157 , X86_REG_YMM4 = 158 , X86_REG_YMM5 = 159 , X86_REG_YMM6 = 160 , X86_REG_YMM7 = 161 , X86_REG_YMM8 = 162 , X86_REG_YMM9 = 163 , X86_REG_YMM10 = 164 , X86_REG_YMM11 = 165 , X86_REG_YMM12 = 166 , X86_REG_YMM13 = 167 , X86_REG_YMM14 = 168 , X86_REG_YMM15 = 169 , X86_REG_YMM16 = 170 , X86_REG_YMM17 = 171 , X86_REG_YMM18 = 172 , X86_REG_YMM19 = 173 , X86_REG_YMM20 = 174 , X86_REG_YMM21 = 175 , X86_REG_YMM22 = 176 , X86_REG_YMM23 = 177 , X86_REG_YMM24 = 178 , X86_REG_YMM25 = 179 , X86_REG_YMM26 = 180 , X86_REG_YMM27 = 181 , X86_REG_YMM28 = 182 , X86_REG_YMM29 = 183 , X86_REG_YMM30 = 184 , X86_REG_YMM31 = 185 , X86_REG_ZMM0 = 186 , X86_REG_ZMM1 = 187 , X86_REG_ZMM2 = 188 , X86_REG_ZMM3 = 189 , X86_REG_ZMM4 = 190 , X86_REG_ZMM5 = 191 , X86_REG_ZMM6 = 192 , X86_REG_ZMM7 = 193 , X86_REG_ZMM8 = 194 , X86_REG_ZMM9 = 195 , X86_REG_ZMM10 = 196 , X86_REG_ZMM11 = 197 , X86_REG_ZMM12 = 198 , X86_REG_ZMM13 = 199 , X86_REG_ZMM14 = 200 , X86_REG_ZMM15 = 201 , X86_REG_ZMM16 = 202 , X86_REG_ZMM17 = 203 , X86_REG_ZMM18 = 204 , X86_REG_ZMM19 = 205 , X86_REG_ZMM20 = 206 , X86_REG_ZMM21 = 207 , X86_REG_ZMM22 = 208 , X86_REG_ZMM23 = 209 , X86_REG_ZMM24 = 210 , X86_REG_ZMM25 = 211 , X86_REG_ZMM26 = 212 , X86_REG_ZMM27 = 213 , X86_REG_ZMM28 = 214 , X86_REG_ZMM29 = 215 , X86_REG_ZMM30 = 216 , X86_REG_ZMM31 = 217 , X86_REG_R8B = 218 , X86_REG_R9B = 219 , X86_REG_R10B = 220 , X86_REG_R11B = 221 , X86_REG_R12B = 222 , X86_REG_R13B = 223 , X86_REG_R14B = 224 , X86_REG_R15B = 225 , X86_REG_R8D = 226 , X86_REG_R9D = 227 , X86_REG_R10D = 228 , X86_REG_R11D = 229 , X86_REG_R12D = 230 , X86_REG_R13D = 231 , X86_REG_R14D = 232 , X86_REG_R15D = 233 , X86_REG_R8W = 234 , X86_REG_R9W = 235 , X86_REG_R10W = 236 , X86_REG_R11W = 237 , X86_REG_R12W = 238 , X86_REG_R13W = 239 , X86_REG_R14W = 240 , X86_REG_R15W = 241 , X86_REG_BND0 = 242 , X86_REG_BND1 = 243 , X86_REG_BND2 = 244 , X86_REG_BND3 = 245 , X86_REG_ENDING = 246 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] X86_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] X86_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] X86_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] X86_OP_MEM = 3 , } # [repr (u32)] # [doc = " XOP Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_xop_cc { # [doc = "< Uninitialized."] X86_XOP_CC_INVALID = 0 , X86_XOP_CC_LT = 1 , X86_XOP_CC_LE = 2 , X86_XOP_CC_GT = 3 , X86_XOP_CC_GE = 4 , X86_XOP_CC_EQ = 5 , X86_XOP_CC_NEQ = 6 , X86_XOP_CC_FALSE = 7 , X86_XOP_CC_TRUE = 8 , } # [repr (u32)] # [doc = " AVX broadcast type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_bcast { # [doc = "< Uninitialized."] X86_AVX_BCAST_INVALID = 0 , # [doc = "< AVX512 broadcast type {1to2}"] X86_AVX_BCAST_2 = 1 , # [doc = "< AVX512 broadcast type {1to4}"] X86_AVX_BCAST_4 = 2 , # [doc = "< AVX512 broadcast type {1to8}"] X86_AVX_BCAST_8 = 3 , # [doc = "< AVX512 broadcast type {1to16}"] X86_AVX_BCAST_16 = 4 , } # [repr (u32)] # [doc = " SSE Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_sse_cc { # [doc = "< Uninitialized."] X86_SSE_CC_INVALID = 0 , X86_SSE_CC_EQ = 1 , X86_SSE_CC_LT = 2 , X86_SSE_CC_LE = 3 , X86_SSE_CC_UNORD = 4 , X86_SSE_CC_NEQ = 5 , X86_SSE_CC_NLT = 6 , X86_SSE_CC_NLE = 7 , X86_SSE_CC_ORD = 8 , } # [repr (u32)] # [doc = " AVX Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_cc { # [doc = "< Uninitialized."] X86_AVX_CC_INVALID = 0 , X86_AVX_CC_EQ = 1 , X86_AVX_CC_LT = 2 , X86_AVX_CC_LE = 3 , X86_AVX_CC_UNORD = 4 , X86_AVX_CC_NEQ = 5 , X86_AVX_CC_NLT = 6 , X86_AVX_CC_NLE = 7 , X86_AVX_CC_ORD = 8 , X86_AVX_CC_EQ_UQ = 9 , X86_AVX_CC_NGE = 10 , X86_AVX_CC_NGT = 11 , X86_AVX_CC_FALSE = 12 , X86_AVX_CC_NEQ_OQ = 13 , X86_AVX_CC_GE = 14 , X86_AVX_CC_GT = 15 , X86_AVX_CC_TRUE = 16 , X86_AVX_CC_EQ_OS = 17 , X86_AVX_CC_LT_OQ = 18 , X86_AVX_CC_LE_OQ = 19 , X86_AVX_CC_UNORD_S = 20 , X86_AVX_CC_NEQ_US = 21 , X86_AVX_CC_NLT_UQ = 22 , X86_AVX_CC_NLE_UQ = 23 , X86_AVX_CC_ORD_S = 24 , X86_AVX_CC_EQ_US = 25 , X86_AVX_CC_NGE_UQ = 26 , X86_AVX_CC_NGT_UQ = 27 , X86_AVX_CC_FALSE_OS = 28 , X86_AVX_CC_NEQ_OS = 29 , X86_AVX_CC_GE_OQ = 30 , X86_AVX_CC_GT_OQ = 31 , X86_AVX_CC_TRUE_US = 32 , } # [repr (u32)] # [doc = " AVX static rounding mode type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_rm { # [doc = "< Uninitialized."] X86_AVX_RM_INVALID = 0 , # [doc = "< Round to nearest"] X86_AVX_RM_RN = 1 , # [doc = "< Round down"] X86_AVX_RM_RD = 2 , # [doc = "< Round up"] X86_AVX_RM_RU = 3 , # [doc = "< Round toward zero"] X86_AVX_RM_RZ = 4 , } impl x86_prefix { pub const X86_PREFIX_REPE : x86_prefix = x86_prefix :: X86_PREFIX_REP ; } # [repr (u32)] # [doc = " Instruction prefixes - to be used in cs_x86.prefix[]"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_prefix { # [doc = "< lock (cs_x86.prefix[0]"] X86_PREFIX_LOCK = 240 , # [doc = "< rep (cs_x86.prefix[0]"] X86_PREFIX_REP = 243 , # [doc = "< repne/repnz (cs_x86.prefix[0]"] X86_PREFIX_REPNE = 242 , # [doc = "< segment override CS (cs_x86.prefix[1]"] X86_PREFIX_CS = 46 , # [doc = "< segment override SS (cs_x86.prefix[1]"] X86_PREFIX_SS = 54 , # [doc = "< segment override DS (cs_x86.prefix[1]"] X86_PREFIX_DS = 62 , # [doc = "< segment override ES (cs_x86.prefix[1]"] X86_PREFIX_ES = 38 , # [doc = "< segment override FS (cs_x86.prefix[1]"] X86_PREFIX_FS = 100 , # [doc = "< segment override GS (cs_x86.prefix[1]"] X86_PREFIX_GS = 101 , # [doc = "< operand-size override (cs_x86.prefix[2]"] X86_PREFIX_OPSIZE = 102 , # [doc = "< address-size override (cs_x86.prefix[3]"] X86_PREFIX_ADDRSIZE = 103 , } # [doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct x86_op_mem { # [doc = "< segment register (or X86_REG_INVALID if irrelevant)"] pub segment : x86_reg , # [doc = "< base register (or X86_REG_INVALID if irrelevant)"] pub base : x86_reg , # [doc = "< index register (or X86_REG_INVALID if irrelevant)"] pub index : x86_reg , # [doc = "< scale for index register"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of x86_op_mem"] [:: std :: mem :: size_of :: < x86_op_mem > () - 24usize] ; ["Alignment of x86_op_mem"] [:: std :: mem :: align_of :: < x86_op_mem > () - 8usize] ; ["Offset of field: x86_op_mem::segment"] [:: std :: mem :: offset_of ! (x86_op_mem , segment) - 0usize] ; ["Offset of field: x86_op_mem::base"] [:: std :: mem :: offset_of ! (x86_op_mem , base) - 4usize] ; ["Offset of field: x86_op_mem::index"] [:: std :: mem :: offset_of ! (x86_op_mem , index) - 8usize] ; ["Offset of field: x86_op_mem::scale"] [:: std :: mem :: offset_of ! (x86_op_mem , scale) - 12usize] ; ["Offset of field: x86_op_mem::disp"] [:: std :: mem :: offset_of ! (x86_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86_op { # [doc = "< operand type"] pub type_ : x86_op_type , pub __bindgen_anon_1 : cs_x86_op__bindgen_ty_1 , # [doc = " size of this operand (in bytes)."] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " AVX broadcast type, or 0 if irrelevant"] pub avx_bcast : x86_avx_bcast , # [doc = " AVX zero opmask {z}"] pub avx_zero_opmask : bool , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : x86_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : x86_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op"] [:: std :: mem :: size_of :: < cs_x86_op > () - 48usize] ; ["Alignment of cs_x86_op"] [:: std :: mem :: align_of :: < cs_x86_op > () - 8usize] ; ["Offset of field: cs_x86_op::type_"] [:: std :: mem :: offset_of ! (cs_x86_op , type_) - 0usize] ; ["Offset of field: cs_x86_op::size"] [:: std :: mem :: offset_of ! (cs_x86_op , size) - 32usize] ; ["Offset of field: cs_x86_op::access"] [:: std :: mem :: offset_of ! (cs_x86_op , access) - 33usize] ; ["Offset of field: cs_x86_op::avx_bcast"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_bcast) - 36usize] ; ["Offset of field: cs_x86_op::avx_zero_opmask"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_zero_opmask) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask) } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_x86_encoding { # [doc = " ModR/M offset, or 0 when irrelevant"] pub modrm_offset : u8 , # [doc = " Displacement offset, or 0 when irrelevant."] pub disp_offset : u8 , pub disp_size : u8 , # [doc = " Immediate offset, or 0 when irrelevant."] pub imm_offset : u8 , pub imm_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_encoding"] [:: std :: mem :: size_of :: < cs_x86_encoding > () - 5usize] ; ["Alignment of cs_x86_encoding"] [:: std :: mem :: align_of :: < cs_x86_encoding > () - 1usize] ; ["Offset of field: cs_x86_encoding::modrm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , modrm_offset) - 0usize] ; ["Offset of field: cs_x86_encoding::disp_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_offset) - 1usize] ; ["Offset of field: cs_x86_encoding::disp_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_size) - 2usize] ; ["Offset of field: cs_x86_encoding::imm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_offset) - 3usize] ; ["Offset of field: cs_x86_encoding::imm_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_size) - 4usize] ; } ; # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86 { # [doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"] pub prefix : [u8 ; 4usize] , # [doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."] pub opcode : [u8 ; 4usize] , # [doc = " REX prefix: only a non-zero value is relevant for x86_64"] pub rex : u8 , # [doc = " Address size, which can be overridden with above prefix[5]."] pub addr_size : u8 , # [doc = " ModR/M byte"] pub modrm : u8 , # [doc = " SIB value, or 0 when irrelevant."] pub sib : u8 , # [doc = " Displacement value, valid if encoding.disp_offset != 0"] pub disp : i64 , # [doc = " SIB index register, or X86_REG_INVALID when irrelevant."] pub sib_index : x86_reg , # [doc = " SIB scale, only applicable if sib_index is valid."] pub sib_scale : i8 , # [doc = " SIB base register, or X86_REG_INVALID when irrelevant."] pub sib_base : x86_reg , # [doc = " XOP Code Condition"] pub xop_cc : x86_xop_cc , # [doc = " SSE Code Condition"] pub sse_cc : x86_sse_cc , # [doc = " AVX Code Condition"] pub avx_cc : x86_avx_cc , # [doc = " AVX Suppress all Exception"] pub avx_sae : bool , # [doc = " AVX static rounding mode"] pub avx_rm : x86_avx_rm , pub __bindgen_anon_1 : cs_x86__bindgen_ty_1 , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_x86_op ; 8usize] , # [doc = "< encoding information"] pub encoding : cs_x86_encoding , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86__bindgen_ty_1 { # [doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"] pub eflags : u64 , # [doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"] pub fpu_flags : u64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_x86__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86__bindgen_ty_1::eflags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , eflags) - 0usize] ; ["Offset of field: cs_x86__bindgen_ty_1::fpu_flags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , fpu_flags) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86"] [:: std :: mem :: size_of :: < cs_x86 > () - 464usize] ; ["Alignment of cs_x86"] [:: std :: mem :: align_of :: < cs_x86 > () - 8usize] ; ["Offset of field: cs_x86::prefix"] [:: std :: mem :: offset_of ! (cs_x86 , prefix) - 0usize] ; ["Offset of field: cs_x86::opcode"] [:: std :: mem :: offset_of ! (cs_x86 , opcode) - 4usize] ; ["Offset of field: cs_x86::rex"] [:: std :: mem :: offset_of ! (cs_x86 , rex) - 8usize] ; ["Offset of field: cs_x86::addr_size"] [:: std :: mem :: offset_of ! (cs_x86 , addr_size) - 9usize] ; ["Offset of field: cs_x86::modrm"] [:: std :: mem :: offset_of ! (cs_x86 , modrm) - 10usize] ; ["Offset of field: cs_x86::sib"] [:: std :: mem :: offset_of ! (cs_x86 , sib) - 11usize] ; ["Offset of field: cs_x86::disp"] [:: std :: mem :: offset_of ! (cs_x86 , disp) - 16usize] ; ["Offset of field: cs_x86::sib_index"] [:: std :: mem :: offset_of ! (cs_x86 , sib_index) - 24usize] ; ["Offset of field: cs_x86::sib_scale"] [:: std :: mem :: offset_of ! (cs_x86 , sib_scale) - 28usize] ; ["Offset of field: cs_x86::sib_base"] [:: std :: mem :: offset_of ! (cs_x86 , sib_base) - 32usize] ; ["Offset of field: cs_x86::xop_cc"] [:: std :: mem :: offset_of ! (cs_x86 , xop_cc) - 36usize] ; ["Offset of field: cs_x86::sse_cc"] [:: std :: mem :: offset_of ! (cs_x86 , sse_cc) - 40usize] ; ["Offset of field: cs_x86::avx_cc"] [:: std :: mem :: offset_of ! (cs_x86 , avx_cc) - 44usize] ; ["Offset of field: cs_x86::avx_sae"] [:: std :: mem :: offset_of ! (cs_x86 , avx_sae) - 48usize] ; ["Offset of field: cs_x86::avx_rm"] [:: std :: mem :: offset_of ! (cs_x86 , avx_rm) - 52usize] ; ["Offset of field: cs_x86::op_count"] [:: std :: mem :: offset_of ! (cs_x86 , op_count) - 64usize] ; ["Offset of field: cs_x86::operands"] [:: std :: mem :: offset_of ! (cs_x86 , operands) - 72usize] ; ["Offset of field: cs_x86::encoding"] [:: std :: mem :: offset_of ! (cs_x86 , encoding) - 456usize] ; } ; impl :: std :: fmt :: Debug for cs_x86 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding) } } # [repr (u32)] # [doc = " X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn { X86_INS_INVALID = 0 , X86_INS_AAA = 1 , X86_INS_AAD = 2 , X86_INS_AAM = 3 , X86_INS_AAS = 4 , X86_INS_FABS = 5 , X86_INS_ADC = 6 , X86_INS_ADCX = 7 , X86_INS_ADD = 8 , X86_INS_ADDPD = 9 , X86_INS_ADDPS = 10 , X86_INS_ADDSD = 11 , X86_INS_ADDSS = 12 , X86_INS_ADDSUBPD = 13 , X86_INS_ADDSUBPS = 14 , X86_INS_FADD = 15 , X86_INS_FIADD = 16 , X86_INS_ADOX = 17 , X86_INS_AESDECLAST = 18 , X86_INS_AESDEC = 19 , X86_INS_AESENCLAST = 20 , X86_INS_AESENC = 21 , X86_INS_AESIMC = 22 , X86_INS_AESKEYGENASSIST = 23 , X86_INS_AND = 24 , X86_INS_ANDN = 25 , X86_INS_ANDNPD = 26 , X86_INS_ANDNPS = 27 , X86_INS_ANDPD = 28 , X86_INS_ANDPS = 29 , X86_INS_ARPL = 30 , X86_INS_BEXTR = 31 , X86_INS_BLCFILL = 32 , X86_INS_BLCI = 33 , X86_INS_BLCIC = 34 , X86_INS_BLCMSK = 35 , X86_INS_BLCS = 36 , X86_INS_BLENDPD = 37 , X86_INS_BLENDPS = 38 , X86_INS_BLENDVPD = 39 , X86_INS_BLENDVPS = 40 , X86_INS_BLSFILL = 41 , X86_INS_BLSI = 42 , X86_INS_BLSIC = 43 , X86_INS_BLSMSK = 44 , X86_INS_BLSR = 45 , X86_INS_BNDCL = 46 , X86_INS_BNDCN = 47 , X86_INS_BNDCU = 48 , X86_INS_BNDLDX = 49 , X86_INS_BNDMK = 50 , X86_INS_BNDMOV = 51 , X86_INS_BNDSTX = 52 , X86_INS_BOUND = 53 , X86_INS_BSF = 54 , X86_INS_BSR = 55 , X86_INS_BSWAP = 56 , X86_INS_BT = 57 , X86_INS_BTC = 58 , X86_INS_BTR = 59 , X86_INS_BTS = 60 , X86_INS_BZHI = 61 , X86_INS_CALL = 62 , X86_INS_CBW = 63 , X86_INS_CDQ = 64 , X86_INS_CDQE = 65 , X86_INS_FCHS = 66 , X86_INS_CLAC = 67 , X86_INS_CLC = 68 , X86_INS_CLD = 69 , X86_INS_CLDEMOTE = 70 , X86_INS_CLFLUSH = 71 , X86_INS_CLFLUSHOPT = 72 , X86_INS_CLGI = 73 , X86_INS_CLI = 74 , X86_INS_CLRSSBSY = 75 , X86_INS_CLTS = 76 , X86_INS_CLWB = 77 , X86_INS_CLZERO = 78 , X86_INS_CMC = 79 , X86_INS_CMOVA = 80 , X86_INS_CMOVAE = 81 , X86_INS_CMOVB = 82 , X86_INS_CMOVBE = 83 , X86_INS_FCMOVBE = 84 , X86_INS_FCMOVB = 85 , X86_INS_CMOVE = 86 , X86_INS_FCMOVE = 87 , X86_INS_CMOVG = 88 , X86_INS_CMOVGE = 89 , X86_INS_CMOVL = 90 , X86_INS_CMOVLE = 91 , X86_INS_FCMOVNBE = 92 , X86_INS_FCMOVNB = 93 , X86_INS_CMOVNE = 94 , X86_INS_FCMOVNE = 95 , X86_INS_CMOVNO = 96 , X86_INS_CMOVNP = 97 , X86_INS_FCMOVNU = 98 , X86_INS_FCMOVNP = 99 , X86_INS_CMOVNS = 100 , X86_INS_CMOVO = 101 , X86_INS_CMOVP = 102 , X86_INS_FCMOVU = 103 , X86_INS_CMOVS = 104 , X86_INS_CMP = 105 , X86_INS_CMPPD = 106 , X86_INS_CMPPS = 107 , X86_INS_CMPSB = 108 , X86_INS_CMPSD = 109 , X86_INS_CMPSQ = 110 , X86_INS_CMPSS = 111 , X86_INS_CMPSW = 112 , X86_INS_CMPXCHG16B = 113 , X86_INS_CMPXCHG = 114 , X86_INS_CMPXCHG8B = 115 , X86_INS_COMISD = 116 , X86_INS_COMISS = 117 , X86_INS_FCOMP = 118 , X86_INS_FCOMPI = 119 , X86_INS_FCOMI = 120 , X86_INS_FCOM = 121 , X86_INS_FCOS = 122 , X86_INS_CPUID = 123 , X86_INS_CQO = 124 , X86_INS_CRC32 = 125 , X86_INS_CVTDQ2PD = 126 , X86_INS_CVTDQ2PS = 127 , X86_INS_CVTPD2DQ = 128 , X86_INS_CVTPD2PS = 129 , X86_INS_CVTPS2DQ = 130 , X86_INS_CVTPS2PD = 131 , X86_INS_CVTSD2SI = 132 , X86_INS_CVTSD2SS = 133 , X86_INS_CVTSI2SD = 134 , X86_INS_CVTSI2SS = 135 , X86_INS_CVTSS2SD = 136 , X86_INS_CVTSS2SI = 137 , X86_INS_CVTTPD2DQ = 138 , X86_INS_CVTTPS2DQ = 139 , X86_INS_CVTTSD2SI = 140 , X86_INS_CVTTSS2SI = 141 , X86_INS_CWD = 142 , X86_INS_CWDE = 143 , X86_INS_DAA = 144 , X86_INS_DAS = 145 , X86_INS_DATA16 = 146 , X86_INS_DEC = 147 , X86_INS_DIV = 148 , X86_INS_DIVPD = 149 , X86_INS_DIVPS = 150 , X86_INS_FDIVR = 151 , X86_INS_FIDIVR = 152 , X86_INS_FDIVRP = 153 , X86_INS_DIVSD = 154 , X86_INS_DIVSS = 155 , X86_INS_FDIV = 156 , X86_INS_FIDIV = 157 , X86_INS_FDIVP = 158 , X86_INS_DPPD = 159 , X86_INS_DPPS = 160 , X86_INS_ENCLS = 161 , X86_INS_ENCLU = 162 , X86_INS_ENCLV = 163 , X86_INS_ENDBR32 = 164 , X86_INS_ENDBR64 = 165 , X86_INS_ENTER = 166 , X86_INS_EXTRACTPS = 167 , X86_INS_EXTRQ = 168 , X86_INS_F2XM1 = 169 , X86_INS_LCALL = 170 , X86_INS_LJMP = 171 , X86_INS_JMP = 172 , X86_INS_FBLD = 173 , X86_INS_FBSTP = 174 , X86_INS_FCOMPP = 175 , X86_INS_FDECSTP = 176 , X86_INS_FDISI8087_NOP = 177 , X86_INS_FEMMS = 178 , X86_INS_FENI8087_NOP = 179 , X86_INS_FFREE = 180 , X86_INS_FFREEP = 181 , X86_INS_FICOM = 182 , X86_INS_FICOMP = 183 , X86_INS_FINCSTP = 184 , X86_INS_FLDCW = 185 , X86_INS_FLDENV = 186 , X86_INS_FLDL2E = 187 , X86_INS_FLDL2T = 188 , X86_INS_FLDLG2 = 189 , X86_INS_FLDLN2 = 190 , X86_INS_FLDPI = 191 , X86_INS_FNCLEX = 192 , X86_INS_FNINIT = 193 , X86_INS_FNOP = 194 , X86_INS_FNSTCW = 195 , X86_INS_FNSTSW = 196 , X86_INS_FPATAN = 197 , X86_INS_FSTPNCE = 198 , X86_INS_FPREM = 199 , X86_INS_FPREM1 = 200 , X86_INS_FPTAN = 201 , X86_INS_FRNDINT = 202 , X86_INS_FRSTOR = 203 , X86_INS_FNSAVE = 204 , X86_INS_FSCALE = 205 , X86_INS_FSETPM = 206 , X86_INS_FSINCOS = 207 , X86_INS_FNSTENV = 208 , X86_INS_FXAM = 209 , X86_INS_FXRSTOR = 210 , X86_INS_FXRSTOR64 = 211 , X86_INS_FXSAVE = 212 , X86_INS_FXSAVE64 = 213 , X86_INS_FXTRACT = 214 , X86_INS_FYL2X = 215 , X86_INS_FYL2XP1 = 216 , X86_INS_GETSEC = 217 , X86_INS_GF2P8AFFINEINVQB = 218 , X86_INS_GF2P8AFFINEQB = 219 , X86_INS_GF2P8MULB = 220 , X86_INS_HADDPD = 221 , X86_INS_HADDPS = 222 , X86_INS_HLT = 223 , X86_INS_HSUBPD = 224 , X86_INS_HSUBPS = 225 , X86_INS_IDIV = 226 , X86_INS_FILD = 227 , X86_INS_IMUL = 228 , X86_INS_IN = 229 , X86_INS_INC = 230 , X86_INS_INCSSPD = 231 , X86_INS_INCSSPQ = 232 , X86_INS_INSB = 233 , X86_INS_INSERTPS = 234 , X86_INS_INSERTQ = 235 , X86_INS_INSD = 236 , X86_INS_INSW = 237 , X86_INS_INT = 238 , X86_INS_INT1 = 239 , X86_INS_INT3 = 240 , X86_INS_INTO = 241 , X86_INS_INVD = 242 , X86_INS_INVEPT = 243 , X86_INS_INVLPG = 244 , X86_INS_INVLPGA = 245 , X86_INS_INVPCID = 246 , X86_INS_INVVPID = 247 , X86_INS_IRET = 248 , X86_INS_IRETD = 249 , X86_INS_IRETQ = 250 , X86_INS_FISTTP = 251 , X86_INS_FIST = 252 , X86_INS_FISTP = 253 , X86_INS_JAE = 254 , X86_INS_JA = 255 , X86_INS_JBE = 256 , X86_INS_JB = 257 , X86_INS_JCXZ = 258 , X86_INS_JECXZ = 259 , X86_INS_JE = 260 , X86_INS_JGE = 261 , X86_INS_JG = 262 , X86_INS_JLE = 263 , X86_INS_JL = 264 , X86_INS_JNE = 265 , X86_INS_JNO = 266 , X86_INS_JNP = 267 , X86_INS_JNS = 268 , X86_INS_JO = 269 , X86_INS_JP = 270 , X86_INS_JRCXZ = 271 , X86_INS_JS = 272 , X86_INS_KADDB = 273 , X86_INS_KADDD = 274 , X86_INS_KADDQ = 275 , X86_INS_KADDW = 276 , X86_INS_KANDB = 277 , X86_INS_KANDD = 278 , X86_INS_KANDNB = 279 , X86_INS_KANDND = 280 , X86_INS_KANDNQ = 281 , X86_INS_KANDNW = 282 , X86_INS_KANDQ = 283 , X86_INS_KANDW = 284 , X86_INS_KMOVB = 285 , X86_INS_KMOVD = 286 , X86_INS_KMOVQ = 287 , X86_INS_KMOVW = 288 , X86_INS_KNOTB = 289 , X86_INS_KNOTD = 290 , X86_INS_KNOTQ = 291 , X86_INS_KNOTW = 292 , X86_INS_KORB = 293 , X86_INS_KORD = 294 , X86_INS_KORQ = 295 , X86_INS_KORTESTB = 296 , X86_INS_KORTESTD = 297 , X86_INS_KORTESTQ = 298 , X86_INS_KORTESTW = 299 , X86_INS_KORW = 300 , X86_INS_KSHIFTLB = 301 , X86_INS_KSHIFTLD = 302 , X86_INS_KSHIFTLQ = 303 , X86_INS_KSHIFTLW = 304 , X86_INS_KSHIFTRB = 305 , X86_INS_KSHIFTRD = 306 , X86_INS_KSHIFTRQ = 307 , X86_INS_KSHIFTRW = 308 , X86_INS_KTESTB = 309 , X86_INS_KTESTD = 310 , X86_INS_KTESTQ = 311 , X86_INS_KTESTW = 312 , X86_INS_KUNPCKBW = 313 , X86_INS_KUNPCKDQ = 314 , X86_INS_KUNPCKWD = 315 , X86_INS_KXNORB = 316 , X86_INS_KXNORD = 317 , X86_INS_KXNORQ = 318 , X86_INS_KXNORW = 319 , X86_INS_KXORB = 320 , X86_INS_KXORD = 321 , X86_INS_KXORQ = 322 , X86_INS_KXORW = 323 , X86_INS_LAHF = 324 , X86_INS_LAR = 325 , X86_INS_LDDQU = 326 , X86_INS_LDMXCSR = 327 , X86_INS_LDS = 328 , X86_INS_FLDZ = 329 , X86_INS_FLD1 = 330 , X86_INS_FLD = 331 , X86_INS_LEA = 332 , X86_INS_LEAVE = 333 , X86_INS_LES = 334 , X86_INS_LFENCE = 335 , X86_INS_LFS = 336 , X86_INS_LGDT = 337 , X86_INS_LGS = 338 , X86_INS_LIDT = 339 , X86_INS_LLDT = 340 , X86_INS_LLWPCB = 341 , X86_INS_LMSW = 342 , X86_INS_LOCK = 343 , X86_INS_LODSB = 344 , X86_INS_LODSD = 345 , X86_INS_LODSQ = 346 , X86_INS_LODSW = 347 , X86_INS_LOOP = 348 , X86_INS_LOOPE = 349 , X86_INS_LOOPNE = 350 , X86_INS_RETF = 351 , X86_INS_RETFQ = 352 , X86_INS_LSL = 353 , X86_INS_LSS = 354 , X86_INS_LTR = 355 , X86_INS_LWPINS = 356 , X86_INS_LWPVAL = 357 , X86_INS_LZCNT = 358 , X86_INS_MASKMOVDQU = 359 , X86_INS_MAXPD = 360 , X86_INS_MAXPS = 361 , X86_INS_MAXSD = 362 , X86_INS_MAXSS = 363 , X86_INS_MFENCE = 364 , X86_INS_MINPD = 365 , X86_INS_MINPS = 366 , X86_INS_MINSD = 367 , X86_INS_MINSS = 368 , X86_INS_CVTPD2PI = 369 , X86_INS_CVTPI2PD = 370 , X86_INS_CVTPI2PS = 371 , X86_INS_CVTPS2PI = 372 , X86_INS_CVTTPD2PI = 373 , X86_INS_CVTTPS2PI = 374 , X86_INS_EMMS = 375 , X86_INS_MASKMOVQ = 376 , X86_INS_MOVD = 377 , X86_INS_MOVQ = 378 , X86_INS_MOVDQ2Q = 379 , X86_INS_MOVNTQ = 380 , X86_INS_MOVQ2DQ = 381 , X86_INS_PABSB = 382 , X86_INS_PABSD = 383 , X86_INS_PABSW = 384 , X86_INS_PACKSSDW = 385 , X86_INS_PACKSSWB = 386 , X86_INS_PACKUSWB = 387 , X86_INS_PADDB = 388 , X86_INS_PADDD = 389 , X86_INS_PADDQ = 390 , X86_INS_PADDSB = 391 , X86_INS_PADDSW = 392 , X86_INS_PADDUSB = 393 , X86_INS_PADDUSW = 394 , X86_INS_PADDW = 395 , X86_INS_PALIGNR = 396 , X86_INS_PANDN = 397 , X86_INS_PAND = 398 , X86_INS_PAVGB = 399 , X86_INS_PAVGW = 400 , X86_INS_PCMPEQB = 401 , X86_INS_PCMPEQD = 402 , X86_INS_PCMPEQW = 403 , X86_INS_PCMPGTB = 404 , X86_INS_PCMPGTD = 405 , X86_INS_PCMPGTW = 406 , X86_INS_PEXTRW = 407 , X86_INS_PHADDD = 408 , X86_INS_PHADDSW = 409 , X86_INS_PHADDW = 410 , X86_INS_PHSUBD = 411 , X86_INS_PHSUBSW = 412 , X86_INS_PHSUBW = 413 , X86_INS_PINSRW = 414 , X86_INS_PMADDUBSW = 415 , X86_INS_PMADDWD = 416 , X86_INS_PMAXSW = 417 , X86_INS_PMAXUB = 418 , X86_INS_PMINSW = 419 , X86_INS_PMINUB = 420 , X86_INS_PMOVMSKB = 421 , X86_INS_PMULHRSW = 422 , X86_INS_PMULHUW = 423 , X86_INS_PMULHW = 424 , X86_INS_PMULLW = 425 , X86_INS_PMULUDQ = 426 , X86_INS_POR = 427 , X86_INS_PSADBW = 428 , X86_INS_PSHUFB = 429 , X86_INS_PSHUFW = 430 , X86_INS_PSIGNB = 431 , X86_INS_PSIGND = 432 , X86_INS_PSIGNW = 433 , X86_INS_PSLLD = 434 , X86_INS_PSLLQ = 435 , X86_INS_PSLLW = 436 , X86_INS_PSRAD = 437 , X86_INS_PSRAW = 438 , X86_INS_PSRLD = 439 , X86_INS_PSRLQ = 440 , X86_INS_PSRLW = 441 , X86_INS_PSUBB = 442 , X86_INS_PSUBD = 443 , X86_INS_PSUBQ = 444 , X86_INS_PSUBSB = 445 , X86_INS_PSUBSW = 446 , X86_INS_PSUBUSB = 447 , X86_INS_PSUBUSW = 448 , X86_INS_PSUBW = 449 , X86_INS_PUNPCKHBW = 450 , X86_INS_PUNPCKHDQ = 451 , X86_INS_PUNPCKHWD = 452 , X86_INS_PUNPCKLBW = 453 , X86_INS_PUNPCKLDQ = 454 , X86_INS_PUNPCKLWD = 455 , X86_INS_PXOR = 456 , X86_INS_MONITORX = 457 , X86_INS_MONITOR = 458 , X86_INS_MONTMUL = 459 , X86_INS_MOV = 460 , X86_INS_MOVABS = 461 , X86_INS_MOVAPD = 462 , X86_INS_MOVAPS = 463 , X86_INS_MOVBE = 464 , X86_INS_MOVDDUP = 465 , X86_INS_MOVDIR64B = 466 , X86_INS_MOVDIRI = 467 , X86_INS_MOVDQA = 468 , X86_INS_MOVDQU = 469 , X86_INS_MOVHLPS = 470 , X86_INS_MOVHPD = 471 , X86_INS_MOVHPS = 472 , X86_INS_MOVLHPS = 473 , X86_INS_MOVLPD = 474 , X86_INS_MOVLPS = 475 , X86_INS_MOVMSKPD = 476 , X86_INS_MOVMSKPS = 477 , X86_INS_MOVNTDQA = 478 , X86_INS_MOVNTDQ = 479 , X86_INS_MOVNTI = 480 , X86_INS_MOVNTPD = 481 , X86_INS_MOVNTPS = 482 , X86_INS_MOVNTSD = 483 , X86_INS_MOVNTSS = 484 , X86_INS_MOVSB = 485 , X86_INS_MOVSD = 486 , X86_INS_MOVSHDUP = 487 , X86_INS_MOVSLDUP = 488 , X86_INS_MOVSQ = 489 , X86_INS_MOVSS = 490 , X86_INS_MOVSW = 491 , X86_INS_MOVSX = 492 , X86_INS_MOVSXD = 493 , X86_INS_MOVUPD = 494 , X86_INS_MOVUPS = 495 , X86_INS_MOVZX = 496 , X86_INS_MPSADBW = 497 , X86_INS_MUL = 498 , X86_INS_MULPD = 499 , X86_INS_MULPS = 500 , X86_INS_MULSD = 501 , X86_INS_MULSS = 502 , X86_INS_MULX = 503 , X86_INS_FMUL = 504 , X86_INS_FIMUL = 505 , X86_INS_FMULP = 506 , X86_INS_MWAITX = 507 , X86_INS_MWAIT = 508 , X86_INS_NEG = 509 , X86_INS_NOP = 510 , X86_INS_NOT = 511 , X86_INS_OR = 512 , X86_INS_ORPD = 513 , X86_INS_ORPS = 514 , X86_INS_OUT = 515 , X86_INS_OUTSB = 516 , X86_INS_OUTSD = 517 , X86_INS_OUTSW = 518 , X86_INS_PACKUSDW = 519 , X86_INS_PAUSE = 520 , X86_INS_PAVGUSB = 521 , X86_INS_PBLENDVB = 522 , X86_INS_PBLENDW = 523 , X86_INS_PCLMULQDQ = 524 , X86_INS_PCMPEQQ = 525 , X86_INS_PCMPESTRI = 526 , X86_INS_PCMPESTRM = 527 , X86_INS_PCMPGTQ = 528 , X86_INS_PCMPISTRI = 529 , X86_INS_PCMPISTRM = 530 , X86_INS_PCONFIG = 531 , X86_INS_PDEP = 532 , X86_INS_PEXT = 533 , X86_INS_PEXTRB = 534 , X86_INS_PEXTRD = 535 , X86_INS_PEXTRQ = 536 , X86_INS_PF2ID = 537 , X86_INS_PF2IW = 538 , X86_INS_PFACC = 539 , X86_INS_PFADD = 540 , X86_INS_PFCMPEQ = 541 , X86_INS_PFCMPGE = 542 , X86_INS_PFCMPGT = 543 , X86_INS_PFMAX = 544 , X86_INS_PFMIN = 545 , X86_INS_PFMUL = 546 , X86_INS_PFNACC = 547 , X86_INS_PFPNACC = 548 , X86_INS_PFRCPIT1 = 549 , X86_INS_PFRCPIT2 = 550 , X86_INS_PFRCP = 551 , X86_INS_PFRSQIT1 = 552 , X86_INS_PFRSQRT = 553 , X86_INS_PFSUBR = 554 , X86_INS_PFSUB = 555 , X86_INS_PHMINPOSUW = 556 , X86_INS_PI2FD = 557 , X86_INS_PI2FW = 558 , X86_INS_PINSRB = 559 , X86_INS_PINSRD = 560 , X86_INS_PINSRQ = 561 , X86_INS_PMAXSB = 562 , X86_INS_PMAXSD = 563 , X86_INS_PMAXUD = 564 , X86_INS_PMAXUW = 565 , X86_INS_PMINSB = 566 , X86_INS_PMINSD = 567 , X86_INS_PMINUD = 568 , X86_INS_PMINUW = 569 , X86_INS_PMOVSXBD = 570 , X86_INS_PMOVSXBQ = 571 , X86_INS_PMOVSXBW = 572 , X86_INS_PMOVSXDQ = 573 , X86_INS_PMOVSXWD = 574 , X86_INS_PMOVSXWQ = 575 , X86_INS_PMOVZXBD = 576 , X86_INS_PMOVZXBQ = 577 , X86_INS_PMOVZXBW = 578 , X86_INS_PMOVZXDQ = 579 , X86_INS_PMOVZXWD = 580 , X86_INS_PMOVZXWQ = 581 , X86_INS_PMULDQ = 582 , X86_INS_PMULHRW = 583 , X86_INS_PMULLD = 584 , X86_INS_POP = 585 , X86_INS_POPAW = 586 , X86_INS_POPAL = 587 , X86_INS_POPCNT = 588 , X86_INS_POPF = 589 , X86_INS_POPFD = 590 , X86_INS_POPFQ = 591 , X86_INS_PREFETCH = 592 , X86_INS_PREFETCHNTA = 593 , X86_INS_PREFETCHT0 = 594 , X86_INS_PREFETCHT1 = 595 , X86_INS_PREFETCHT2 = 596 , X86_INS_PREFETCHW = 597 , X86_INS_PREFETCHWT1 = 598 , X86_INS_PSHUFD = 599 , X86_INS_PSHUFHW = 600 , X86_INS_PSHUFLW = 601 , X86_INS_PSLLDQ = 602 , X86_INS_PSRLDQ = 603 , X86_INS_PSWAPD = 604 , X86_INS_PTEST = 605 , X86_INS_PTWRITE = 606 , X86_INS_PUNPCKHQDQ = 607 , X86_INS_PUNPCKLQDQ = 608 , X86_INS_PUSH = 609 , X86_INS_PUSHAW = 610 , X86_INS_PUSHAL = 611 , X86_INS_PUSHF = 612 , X86_INS_PUSHFD = 613 , X86_INS_PUSHFQ = 614 , X86_INS_RCL = 615 , X86_INS_RCPPS = 616 , X86_INS_RCPSS = 617 , X86_INS_RCR = 618 , X86_INS_RDFSBASE = 619 , X86_INS_RDGSBASE = 620 , X86_INS_RDMSR = 621 , X86_INS_RDPID = 622 , X86_INS_RDPKRU = 623 , X86_INS_RDPMC = 624 , X86_INS_RDRAND = 625 , X86_INS_RDSEED = 626 , X86_INS_RDSSPD = 627 , X86_INS_RDSSPQ = 628 , X86_INS_RDTSC = 629 , X86_INS_RDTSCP = 630 , X86_INS_REPNE = 631 , X86_INS_REP = 632 , X86_INS_RET = 633 , X86_INS_REX64 = 634 , X86_INS_ROL = 635 , X86_INS_ROR = 636 , X86_INS_RORX = 637 , X86_INS_ROUNDPD = 638 , X86_INS_ROUNDPS = 639 , X86_INS_ROUNDSD = 640 , X86_INS_ROUNDSS = 641 , X86_INS_RSM = 642 , X86_INS_RSQRTPS = 643 , X86_INS_RSQRTSS = 644 , X86_INS_RSTORSSP = 645 , X86_INS_SAHF = 646 , X86_INS_SAL = 647 , X86_INS_SALC = 648 , X86_INS_SAR = 649 , X86_INS_SARX = 650 , X86_INS_SAVEPREVSSP = 651 , X86_INS_SBB = 652 , X86_INS_SCASB = 653 , X86_INS_SCASD = 654 , X86_INS_SCASQ = 655 , X86_INS_SCASW = 656 , X86_INS_SETAE = 657 , X86_INS_SETA = 658 , X86_INS_SETBE = 659 , X86_INS_SETB = 660 , X86_INS_SETE = 661 , X86_INS_SETGE = 662 , X86_INS_SETG = 663 , X86_INS_SETLE = 664 , X86_INS_SETL = 665 , X86_INS_SETNE = 666 , X86_INS_SETNO = 667 , X86_INS_SETNP = 668 , X86_INS_SETNS = 669 , X86_INS_SETO = 670 , X86_INS_SETP = 671 , X86_INS_SETSSBSY = 672 , X86_INS_SETS = 673 , X86_INS_SFENCE = 674 , X86_INS_SGDT = 675 , X86_INS_SHA1MSG1 = 676 , X86_INS_SHA1MSG2 = 677 , X86_INS_SHA1NEXTE = 678 , X86_INS_SHA1RNDS4 = 679 , X86_INS_SHA256MSG1 = 680 , X86_INS_SHA256MSG2 = 681 , X86_INS_SHA256RNDS2 = 682 , X86_INS_SHL = 683 , X86_INS_SHLD = 684 , X86_INS_SHLX = 685 , X86_INS_SHR = 686 , X86_INS_SHRD = 687 , X86_INS_SHRX = 688 , X86_INS_SHUFPD = 689 , X86_INS_SHUFPS = 690 , X86_INS_SIDT = 691 , X86_INS_FSIN = 692 , X86_INS_SKINIT = 693 , X86_INS_SLDT = 694 , X86_INS_SLWPCB = 695 , X86_INS_SMSW = 696 , X86_INS_SQRTPD = 697 , X86_INS_SQRTPS = 698 , X86_INS_SQRTSD = 699 , X86_INS_SQRTSS = 700 , X86_INS_FSQRT = 701 , X86_INS_STAC = 702 , X86_INS_STC = 703 , X86_INS_STD = 704 , X86_INS_STGI = 705 , X86_INS_STI = 706 , X86_INS_STMXCSR = 707 , X86_INS_STOSB = 708 , X86_INS_STOSD = 709 , X86_INS_STOSQ = 710 , X86_INS_STOSW = 711 , X86_INS_STR = 712 , X86_INS_FST = 713 , X86_INS_FSTP = 714 , X86_INS_SUB = 715 , X86_INS_SUBPD = 716 , X86_INS_SUBPS = 717 , X86_INS_FSUBR = 718 , X86_INS_FISUBR = 719 , X86_INS_FSUBRP = 720 , X86_INS_SUBSD = 721 , X86_INS_SUBSS = 722 , X86_INS_FSUB = 723 , X86_INS_FISUB = 724 , X86_INS_FSUBP = 725 , X86_INS_SWAPGS = 726 , X86_INS_SYSCALL = 727 , X86_INS_SYSENTER = 728 , X86_INS_SYSEXIT = 729 , X86_INS_SYSEXITQ = 730 , X86_INS_SYSRET = 731 , X86_INS_SYSRETQ = 732 , X86_INS_T1MSKC = 733 , X86_INS_TEST = 734 , X86_INS_TPAUSE = 735 , X86_INS_FTST = 736 , X86_INS_TZCNT = 737 , X86_INS_TZMSK = 738 , X86_INS_UCOMISD = 739 , X86_INS_UCOMISS = 740 , X86_INS_FUCOMPI = 741 , X86_INS_FUCOMI = 742 , X86_INS_FUCOMPP = 743 , X86_INS_FUCOMP = 744 , X86_INS_FUCOM = 745 , X86_INS_UD0 = 746 , X86_INS_UD1 = 747 , X86_INS_UD2 = 748 , X86_INS_UMONITOR = 749 , X86_INS_UMWAIT = 750 , X86_INS_UNPCKHPD = 751 , X86_INS_UNPCKHPS = 752 , X86_INS_UNPCKLPD = 753 , X86_INS_UNPCKLPS = 754 , X86_INS_V4FMADDPS = 755 , X86_INS_V4FMADDSS = 756 , X86_INS_V4FNMADDPS = 757 , X86_INS_V4FNMADDSS = 758 , X86_INS_VADDPD = 759 , X86_INS_VADDPS = 760 , X86_INS_VADDSD = 761 , X86_INS_VADDSS = 762 , X86_INS_VADDSUBPD = 763 , X86_INS_VADDSUBPS = 764 , X86_INS_VAESDECLAST = 765 , X86_INS_VAESDEC = 766 , X86_INS_VAESENCLAST = 767 , X86_INS_VAESENC = 768 , X86_INS_VAESIMC = 769 , X86_INS_VAESKEYGENASSIST = 770 , X86_INS_VALIGND = 771 , X86_INS_VALIGNQ = 772 , X86_INS_VANDNPD = 773 , X86_INS_VANDNPS = 774 , X86_INS_VANDPD = 775 , X86_INS_VANDPS = 776 , X86_INS_VBLENDMPD = 777 , X86_INS_VBLENDMPS = 778 , X86_INS_VBLENDPD = 779 , X86_INS_VBLENDPS = 780 , X86_INS_VBLENDVPD = 781 , X86_INS_VBLENDVPS = 782 , X86_INS_VBROADCASTF128 = 783 , X86_INS_VBROADCASTF32X2 = 784 , X86_INS_VBROADCASTF32X4 = 785 , X86_INS_VBROADCASTF32X8 = 786 , X86_INS_VBROADCASTF64X2 = 787 , X86_INS_VBROADCASTF64X4 = 788 , X86_INS_VBROADCASTI128 = 789 , X86_INS_VBROADCASTI32X2 = 790 , X86_INS_VBROADCASTI32X4 = 791 , X86_INS_VBROADCASTI32X8 = 792 , X86_INS_VBROADCASTI64X2 = 793 , X86_INS_VBROADCASTI64X4 = 794 , X86_INS_VBROADCASTSD = 795 , X86_INS_VBROADCASTSS = 796 , X86_INS_VCMP = 797 , X86_INS_VCMPPD = 798 , X86_INS_VCMPPS = 799 , X86_INS_VCMPSD = 800 , X86_INS_VCMPSS = 801 , X86_INS_VCOMISD = 802 , X86_INS_VCOMISS = 803 , X86_INS_VCOMPRESSPD = 804 , X86_INS_VCOMPRESSPS = 805 , X86_INS_VCVTDQ2PD = 806 , X86_INS_VCVTDQ2PS = 807 , X86_INS_VCVTPD2DQ = 808 , X86_INS_VCVTPD2PS = 809 , X86_INS_VCVTPD2QQ = 810 , X86_INS_VCVTPD2UDQ = 811 , X86_INS_VCVTPD2UQQ = 812 , X86_INS_VCVTPH2PS = 813 , X86_INS_VCVTPS2DQ = 814 , X86_INS_VCVTPS2PD = 815 , X86_INS_VCVTPS2PH = 816 , X86_INS_VCVTPS2QQ = 817 , X86_INS_VCVTPS2UDQ = 818 , X86_INS_VCVTPS2UQQ = 819 , X86_INS_VCVTQQ2PD = 820 , X86_INS_VCVTQQ2PS = 821 , X86_INS_VCVTSD2SI = 822 , X86_INS_VCVTSD2SS = 823 , X86_INS_VCVTSD2USI = 824 , X86_INS_VCVTSI2SD = 825 , X86_INS_VCVTSI2SS = 826 , X86_INS_VCVTSS2SD = 827 , X86_INS_VCVTSS2SI = 828 , X86_INS_VCVTSS2USI = 829 , X86_INS_VCVTTPD2DQ = 830 , X86_INS_VCVTTPD2QQ = 831 , X86_INS_VCVTTPD2UDQ = 832 , X86_INS_VCVTTPD2UQQ = 833 , X86_INS_VCVTTPS2DQ = 834 , X86_INS_VCVTTPS2QQ = 835 , X86_INS_VCVTTPS2UDQ = 836 , X86_INS_VCVTTPS2UQQ = 837 , X86_INS_VCVTTSD2SI = 838 , X86_INS_VCVTTSD2USI = 839 , X86_INS_VCVTTSS2SI = 840 , X86_INS_VCVTTSS2USI = 841 , X86_INS_VCVTUDQ2PD = 842 , X86_INS_VCVTUDQ2PS = 843 , X86_INS_VCVTUQQ2PD = 844 , X86_INS_VCVTUQQ2PS = 845 , X86_INS_VCVTUSI2SD = 846 , X86_INS_VCVTUSI2SS = 847 , X86_INS_VDBPSADBW = 848 , X86_INS_VDIVPD = 849 , X86_INS_VDIVPS = 850 , X86_INS_VDIVSD = 851 , X86_INS_VDIVSS = 852 , X86_INS_VDPPD = 853 , X86_INS_VDPPS = 854 , X86_INS_VERR = 855 , X86_INS_VERW = 856 , X86_INS_VEXP2PD = 857 , X86_INS_VEXP2PS = 858 , X86_INS_VEXPANDPD = 859 , X86_INS_VEXPANDPS = 860 , X86_INS_VEXTRACTF128 = 861 , X86_INS_VEXTRACTF32X4 = 862 , X86_INS_VEXTRACTF32X8 = 863 , X86_INS_VEXTRACTF64X2 = 864 , X86_INS_VEXTRACTF64X4 = 865 , X86_INS_VEXTRACTI128 = 866 , X86_INS_VEXTRACTI32X4 = 867 , X86_INS_VEXTRACTI32X8 = 868 , X86_INS_VEXTRACTI64X2 = 869 , X86_INS_VEXTRACTI64X4 = 870 , X86_INS_VEXTRACTPS = 871 , X86_INS_VFIXUPIMMPD = 872 , X86_INS_VFIXUPIMMPS = 873 , X86_INS_VFIXUPIMMSD = 874 , X86_INS_VFIXUPIMMSS = 875 , X86_INS_VFMADD132PD = 876 , X86_INS_VFMADD132PS = 877 , X86_INS_VFMADD132SD = 878 , X86_INS_VFMADD132SS = 879 , X86_INS_VFMADD213PD = 880 , X86_INS_VFMADD213PS = 881 , X86_INS_VFMADD213SD = 882 , X86_INS_VFMADD213SS = 883 , X86_INS_VFMADD231PD = 884 , X86_INS_VFMADD231PS = 885 , X86_INS_VFMADD231SD = 886 , X86_INS_VFMADD231SS = 887 , X86_INS_VFMADDPD = 888 , X86_INS_VFMADDPS = 889 , X86_INS_VFMADDSD = 890 , X86_INS_VFMADDSS = 891 , X86_INS_VFMADDSUB132PD = 892 , X86_INS_VFMADDSUB132PS = 893 , X86_INS_VFMADDSUB213PD = 894 , X86_INS_VFMADDSUB213PS = 895 , X86_INS_VFMADDSUB231PD = 896 , X86_INS_VFMADDSUB231PS = 897 , X86_INS_VFMADDSUBPD = 898 , X86_INS_VFMADDSUBPS = 899 , X86_INS_VFMSUB132PD = 900 , X86_INS_VFMSUB132PS = 901 , X86_INS_VFMSUB132SD = 902 , X86_INS_VFMSUB132SS = 903 , X86_INS_VFMSUB213PD = 904 , X86_INS_VFMSUB213PS = 905 , X86_INS_VFMSUB213SD = 906 , X86_INS_VFMSUB213SS = 907 , X86_INS_VFMSUB231PD = 908 , X86_INS_VFMSUB231PS = 909 , X86_INS_VFMSUB231SD = 910 , X86_INS_VFMSUB231SS = 911 , X86_INS_VFMSUBADD132PD = 912 , X86_INS_VFMSUBADD132PS = 913 , X86_INS_VFMSUBADD213PD = 914 , X86_INS_VFMSUBADD213PS = 915 , X86_INS_VFMSUBADD231PD = 916 , X86_INS_VFMSUBADD231PS = 917 , X86_INS_VFMSUBADDPD = 918 , X86_INS_VFMSUBADDPS = 919 , X86_INS_VFMSUBPD = 920 , X86_INS_VFMSUBPS = 921 , X86_INS_VFMSUBSD = 922 , X86_INS_VFMSUBSS = 923 , X86_INS_VFNMADD132PD = 924 , X86_INS_VFNMADD132PS = 925 , X86_INS_VFNMADD132SD = 926 , X86_INS_VFNMADD132SS = 927 , X86_INS_VFNMADD213PD = 928 , X86_INS_VFNMADD213PS = 929 , X86_INS_VFNMADD213SD = 930 , X86_INS_VFNMADD213SS = 931 , X86_INS_VFNMADD231PD = 932 , X86_INS_VFNMADD231PS = 933 , X86_INS_VFNMADD231SD = 934 , X86_INS_VFNMADD231SS = 935 , X86_INS_VFNMADDPD = 936 , X86_INS_VFNMADDPS = 937 , X86_INS_VFNMADDSD = 938 , X86_INS_VFNMADDSS = 939 , X86_INS_VFNMSUB132PD = 940 , X86_INS_VFNMSUB132PS = 941 , X86_INS_VFNMSUB132SD = 942 , X86_INS_VFNMSUB132SS = 943 , X86_INS_VFNMSUB213PD = 944 , X86_INS_VFNMSUB213PS = 945 , X86_INS_VFNMSUB213SD = 946 , X86_INS_VFNMSUB213SS = 947 , X86_INS_VFNMSUB231PD = 948 , X86_INS_VFNMSUB231PS = 949 , X86_INS_VFNMSUB231SD = 950 , X86_INS_VFNMSUB231SS = 951 , X86_INS_VFNMSUBPD = 952 , X86_INS_VFNMSUBPS = 953 , X86_INS_VFNMSUBSD = 954 , X86_INS_VFNMSUBSS = 955 , X86_INS_VFPCLASSPD = 956 , X86_INS_VFPCLASSPS = 957 , X86_INS_VFPCLASSSD = 958 , X86_INS_VFPCLASSSS = 959 , X86_INS_VFRCZPD = 960 , X86_INS_VFRCZPS = 961 , X86_INS_VFRCZSD = 962 , X86_INS_VFRCZSS = 963 , X86_INS_VGATHERDPD = 964 , X86_INS_VGATHERDPS = 965 , X86_INS_VGATHERPF0DPD = 966 , X86_INS_VGATHERPF0DPS = 967 , X86_INS_VGATHERPF0QPD = 968 , X86_INS_VGATHERPF0QPS = 969 , X86_INS_VGATHERPF1DPD = 970 , X86_INS_VGATHERPF1DPS = 971 , X86_INS_VGATHERPF1QPD = 972 , X86_INS_VGATHERPF1QPS = 973 , X86_INS_VGATHERQPD = 974 , X86_INS_VGATHERQPS = 975 , X86_INS_VGETEXPPD = 976 , X86_INS_VGETEXPPS = 977 , X86_INS_VGETEXPSD = 978 , X86_INS_VGETEXPSS = 979 , X86_INS_VGETMANTPD = 980 , X86_INS_VGETMANTPS = 981 , X86_INS_VGETMANTSD = 982 , X86_INS_VGETMANTSS = 983 , X86_INS_VGF2P8AFFINEINVQB = 984 , X86_INS_VGF2P8AFFINEQB = 985 , X86_INS_VGF2P8MULB = 986 , X86_INS_VHADDPD = 987 , X86_INS_VHADDPS = 988 , X86_INS_VHSUBPD = 989 , X86_INS_VHSUBPS = 990 , X86_INS_VINSERTF128 = 991 , X86_INS_VINSERTF32X4 = 992 , X86_INS_VINSERTF32X8 = 993 , X86_INS_VINSERTF64X2 = 994 , X86_INS_VINSERTF64X4 = 995 , X86_INS_VINSERTI128 = 996 , X86_INS_VINSERTI32X4 = 997 , X86_INS_VINSERTI32X8 = 998 , X86_INS_VINSERTI64X2 = 999 , X86_INS_VINSERTI64X4 = 1000 , X86_INS_VINSERTPS = 1001 , X86_INS_VLDDQU = 1002 , X86_INS_VLDMXCSR = 1003 , X86_INS_VMASKMOVDQU = 1004 , X86_INS_VMASKMOVPD = 1005 , X86_INS_VMASKMOVPS = 1006 , X86_INS_VMAXPD = 1007 , X86_INS_VMAXPS = 1008 , X86_INS_VMAXSD = 1009 , X86_INS_VMAXSS = 1010 , X86_INS_VMCALL = 1011 , X86_INS_VMCLEAR = 1012 , X86_INS_VMFUNC = 1013 , X86_INS_VMINPD = 1014 , X86_INS_VMINPS = 1015 , X86_INS_VMINSD = 1016 , X86_INS_VMINSS = 1017 , X86_INS_VMLAUNCH = 1018 , X86_INS_VMLOAD = 1019 , X86_INS_VMMCALL = 1020 , X86_INS_VMOVQ = 1021 , X86_INS_VMOVAPD = 1022 , X86_INS_VMOVAPS = 1023 , X86_INS_VMOVDDUP = 1024 , X86_INS_VMOVD = 1025 , X86_INS_VMOVDQA32 = 1026 , X86_INS_VMOVDQA64 = 1027 , X86_INS_VMOVDQA = 1028 , X86_INS_VMOVDQU16 = 1029 , X86_INS_VMOVDQU32 = 1030 , X86_INS_VMOVDQU64 = 1031 , X86_INS_VMOVDQU8 = 1032 , X86_INS_VMOVDQU = 1033 , X86_INS_VMOVHLPS = 1034 , X86_INS_VMOVHPD = 1035 , X86_INS_VMOVHPS = 1036 , X86_INS_VMOVLHPS = 1037 , X86_INS_VMOVLPD = 1038 , X86_INS_VMOVLPS = 1039 , X86_INS_VMOVMSKPD = 1040 , X86_INS_VMOVMSKPS = 1041 , X86_INS_VMOVNTDQA = 1042 , X86_INS_VMOVNTDQ = 1043 , X86_INS_VMOVNTPD = 1044 , X86_INS_VMOVNTPS = 1045 , X86_INS_VMOVSD = 1046 , X86_INS_VMOVSHDUP = 1047 , X86_INS_VMOVSLDUP = 1048 , X86_INS_VMOVSS = 1049 , X86_INS_VMOVUPD = 1050 , X86_INS_VMOVUPS = 1051 , X86_INS_VMPSADBW = 1052 , X86_INS_VMPTRLD = 1053 , X86_INS_VMPTRST = 1054 , X86_INS_VMREAD = 1055 , X86_INS_VMRESUME = 1056 , X86_INS_VMRUN = 1057 , X86_INS_VMSAVE = 1058 , X86_INS_VMULPD = 1059 , X86_INS_VMULPS = 1060 , X86_INS_VMULSD = 1061 , X86_INS_VMULSS = 1062 , X86_INS_VMWRITE = 1063 , X86_INS_VMXOFF = 1064 , X86_INS_VMXON = 1065 , X86_INS_VORPD = 1066 , X86_INS_VORPS = 1067 , X86_INS_VP4DPWSSDS = 1068 , X86_INS_VP4DPWSSD = 1069 , X86_INS_VPABSB = 1070 , X86_INS_VPABSD = 1071 , X86_INS_VPABSQ = 1072 , X86_INS_VPABSW = 1073 , X86_INS_VPACKSSDW = 1074 , X86_INS_VPACKSSWB = 1075 , X86_INS_VPACKUSDW = 1076 , X86_INS_VPACKUSWB = 1077 , X86_INS_VPADDB = 1078 , X86_INS_VPADDD = 1079 , X86_INS_VPADDQ = 1080 , X86_INS_VPADDSB = 1081 , X86_INS_VPADDSW = 1082 , X86_INS_VPADDUSB = 1083 , X86_INS_VPADDUSW = 1084 , X86_INS_VPADDW = 1085 , X86_INS_VPALIGNR = 1086 , X86_INS_VPANDD = 1087 , X86_INS_VPANDND = 1088 , X86_INS_VPANDNQ = 1089 , X86_INS_VPANDN = 1090 , X86_INS_VPANDQ = 1091 , X86_INS_VPAND = 1092 , X86_INS_VPAVGB = 1093 , X86_INS_VPAVGW = 1094 , X86_INS_VPBLENDD = 1095 , X86_INS_VPBLENDMB = 1096 , X86_INS_VPBLENDMD = 1097 , X86_INS_VPBLENDMQ = 1098 , X86_INS_VPBLENDMW = 1099 , X86_INS_VPBLENDVB = 1100 , X86_INS_VPBLENDW = 1101 , X86_INS_VPBROADCASTB = 1102 , X86_INS_VPBROADCASTD = 1103 , X86_INS_VPBROADCASTMB2Q = 1104 , X86_INS_VPBROADCASTMW2D = 1105 , X86_INS_VPBROADCASTQ = 1106 , X86_INS_VPBROADCASTW = 1107 , X86_INS_VPCLMULQDQ = 1108 , X86_INS_VPCMOV = 1109 , X86_INS_VPCMP = 1110 , X86_INS_VPCMPB = 1111 , X86_INS_VPCMPD = 1112 , X86_INS_VPCMPEQB = 1113 , X86_INS_VPCMPEQD = 1114 , X86_INS_VPCMPEQQ = 1115 , X86_INS_VPCMPEQW = 1116 , X86_INS_VPCMPESTRI = 1117 , X86_INS_VPCMPESTRM = 1118 , X86_INS_VPCMPGTB = 1119 , X86_INS_VPCMPGTD = 1120 , X86_INS_VPCMPGTQ = 1121 , X86_INS_VPCMPGTW = 1122 , X86_INS_VPCMPISTRI = 1123 , X86_INS_VPCMPISTRM = 1124 , X86_INS_VPCMPQ = 1125 , X86_INS_VPCMPUB = 1126 , X86_INS_VPCMPUD = 1127 , X86_INS_VPCMPUQ = 1128 , X86_INS_VPCMPUW = 1129 , X86_INS_VPCMPW = 1130 , X86_INS_VPCOM = 1131 , X86_INS_VPCOMB = 1132 , X86_INS_VPCOMD = 1133 , X86_INS_VPCOMPRESSB = 1134 , X86_INS_VPCOMPRESSD = 1135 , X86_INS_VPCOMPRESSQ = 1136 , X86_INS_VPCOMPRESSW = 1137 , X86_INS_VPCOMQ = 1138 , X86_INS_VPCOMUB = 1139 , X86_INS_VPCOMUD = 1140 , X86_INS_VPCOMUQ = 1141 , X86_INS_VPCOMUW = 1142 , X86_INS_VPCOMW = 1143 , X86_INS_VPCONFLICTD = 1144 , X86_INS_VPCONFLICTQ = 1145 , X86_INS_VPDPBUSDS = 1146 , X86_INS_VPDPBUSD = 1147 , X86_INS_VPDPWSSDS = 1148 , X86_INS_VPDPWSSD = 1149 , X86_INS_VPERM2F128 = 1150 , X86_INS_VPERM2I128 = 1151 , X86_INS_VPERMB = 1152 , X86_INS_VPERMD = 1153 , X86_INS_VPERMI2B = 1154 , X86_INS_VPERMI2D = 1155 , X86_INS_VPERMI2PD = 1156 , X86_INS_VPERMI2PS = 1157 , X86_INS_VPERMI2Q = 1158 , X86_INS_VPERMI2W = 1159 , X86_INS_VPERMIL2PD = 1160 , X86_INS_VPERMILPD = 1161 , X86_INS_VPERMIL2PS = 1162 , X86_INS_VPERMILPS = 1163 , X86_INS_VPERMPD = 1164 , X86_INS_VPERMPS = 1165 , X86_INS_VPERMQ = 1166 , X86_INS_VPERMT2B = 1167 , X86_INS_VPERMT2D = 1168 , X86_INS_VPERMT2PD = 1169 , X86_INS_VPERMT2PS = 1170 , X86_INS_VPERMT2Q = 1171 , X86_INS_VPERMT2W = 1172 , X86_INS_VPERMW = 1173 , X86_INS_VPEXPANDB = 1174 , X86_INS_VPEXPANDD = 1175 , X86_INS_VPEXPANDQ = 1176 , X86_INS_VPEXPANDW = 1177 , X86_INS_VPEXTRB = 1178 , X86_INS_VPEXTRD = 1179 , X86_INS_VPEXTRQ = 1180 , X86_INS_VPEXTRW = 1181 , X86_INS_VPGATHERDD = 1182 , X86_INS_VPGATHERDQ = 1183 , X86_INS_VPGATHERQD = 1184 , X86_INS_VPGATHERQQ = 1185 , X86_INS_VPHADDBD = 1186 , X86_INS_VPHADDBQ = 1187 , X86_INS_VPHADDBW = 1188 , X86_INS_VPHADDDQ = 1189 , X86_INS_VPHADDD = 1190 , X86_INS_VPHADDSW = 1191 , X86_INS_VPHADDUBD = 1192 , X86_INS_VPHADDUBQ = 1193 , X86_INS_VPHADDUBW = 1194 , X86_INS_VPHADDUDQ = 1195 , X86_INS_VPHADDUWD = 1196 , X86_INS_VPHADDUWQ = 1197 , X86_INS_VPHADDWD = 1198 , X86_INS_VPHADDWQ = 1199 , X86_INS_VPHADDW = 1200 , X86_INS_VPHMINPOSUW = 1201 , X86_INS_VPHSUBBW = 1202 , X86_INS_VPHSUBDQ = 1203 , X86_INS_VPHSUBD = 1204 , X86_INS_VPHSUBSW = 1205 , X86_INS_VPHSUBWD = 1206 , X86_INS_VPHSUBW = 1207 , X86_INS_VPINSRB = 1208 , X86_INS_VPINSRD = 1209 , X86_INS_VPINSRQ = 1210 , X86_INS_VPINSRW = 1211 , X86_INS_VPLZCNTD = 1212 , X86_INS_VPLZCNTQ = 1213 , X86_INS_VPMACSDD = 1214 , X86_INS_VPMACSDQH = 1215 , X86_INS_VPMACSDQL = 1216 , X86_INS_VPMACSSDD = 1217 , X86_INS_VPMACSSDQH = 1218 , X86_INS_VPMACSSDQL = 1219 , X86_INS_VPMACSSWD = 1220 , X86_INS_VPMACSSWW = 1221 , X86_INS_VPMACSWD = 1222 , X86_INS_VPMACSWW = 1223 , X86_INS_VPMADCSSWD = 1224 , X86_INS_VPMADCSWD = 1225 , X86_INS_VPMADD52HUQ = 1226 , X86_INS_VPMADD52LUQ = 1227 , X86_INS_VPMADDUBSW = 1228 , X86_INS_VPMADDWD = 1229 , X86_INS_VPMASKMOVD = 1230 , X86_INS_VPMASKMOVQ = 1231 , X86_INS_VPMAXSB = 1232 , X86_INS_VPMAXSD = 1233 , X86_INS_VPMAXSQ = 1234 , X86_INS_VPMAXSW = 1235 , X86_INS_VPMAXUB = 1236 , X86_INS_VPMAXUD = 1237 , X86_INS_VPMAXUQ = 1238 , X86_INS_VPMAXUW = 1239 , X86_INS_VPMINSB = 1240 , X86_INS_VPMINSD = 1241 , X86_INS_VPMINSQ = 1242 , X86_INS_VPMINSW = 1243 , X86_INS_VPMINUB = 1244 , X86_INS_VPMINUD = 1245 , X86_INS_VPMINUQ = 1246 , X86_INS_VPMINUW = 1247 , X86_INS_VPMOVB2M = 1248 , X86_INS_VPMOVD2M = 1249 , X86_INS_VPMOVDB = 1250 , X86_INS_VPMOVDW = 1251 , X86_INS_VPMOVM2B = 1252 , X86_INS_VPMOVM2D = 1253 , X86_INS_VPMOVM2Q = 1254 , X86_INS_VPMOVM2W = 1255 , X86_INS_VPMOVMSKB = 1256 , X86_INS_VPMOVQ2M = 1257 , X86_INS_VPMOVQB = 1258 , X86_INS_VPMOVQD = 1259 , X86_INS_VPMOVQW = 1260 , X86_INS_VPMOVSDB = 1261 , X86_INS_VPMOVSDW = 1262 , X86_INS_VPMOVSQB = 1263 , X86_INS_VPMOVSQD = 1264 , X86_INS_VPMOVSQW = 1265 , X86_INS_VPMOVSWB = 1266 , X86_INS_VPMOVSXBD = 1267 , X86_INS_VPMOVSXBQ = 1268 , X86_INS_VPMOVSXBW = 1269 , X86_INS_VPMOVSXDQ = 1270 , X86_INS_VPMOVSXWD = 1271 , X86_INS_VPMOVSXWQ = 1272 , X86_INS_VPMOVUSDB = 1273 , X86_INS_VPMOVUSDW = 1274 , X86_INS_VPMOVUSQB = 1275 , X86_INS_VPMOVUSQD = 1276 , X86_INS_VPMOVUSQW = 1277 , X86_INS_VPMOVUSWB = 1278 , X86_INS_VPMOVW2M = 1279 , X86_INS_VPMOVWB = 1280 , X86_INS_VPMOVZXBD = 1281 , X86_INS_VPMOVZXBQ = 1282 , X86_INS_VPMOVZXBW = 1283 , X86_INS_VPMOVZXDQ = 1284 , X86_INS_VPMOVZXWD = 1285 , X86_INS_VPMOVZXWQ = 1286 , X86_INS_VPMULDQ = 1287 , X86_INS_VPMULHRSW = 1288 , X86_INS_VPMULHUW = 1289 , X86_INS_VPMULHW = 1290 , X86_INS_VPMULLD = 1291 , X86_INS_VPMULLQ = 1292 , X86_INS_VPMULLW = 1293 , X86_INS_VPMULTISHIFTQB = 1294 , X86_INS_VPMULUDQ = 1295 , X86_INS_VPOPCNTB = 1296 , X86_INS_VPOPCNTD = 1297 , X86_INS_VPOPCNTQ = 1298 , X86_INS_VPOPCNTW = 1299 , X86_INS_VPORD = 1300 , X86_INS_VPORQ = 1301 , X86_INS_VPOR = 1302 , X86_INS_VPPERM = 1303 , X86_INS_VPROLD = 1304 , X86_INS_VPROLQ = 1305 , X86_INS_VPROLVD = 1306 , X86_INS_VPROLVQ = 1307 , X86_INS_VPRORD = 1308 , X86_INS_VPRORQ = 1309 , X86_INS_VPRORVD = 1310 , X86_INS_VPRORVQ = 1311 , X86_INS_VPROTB = 1312 , X86_INS_VPROTD = 1313 , X86_INS_VPROTQ = 1314 , X86_INS_VPROTW = 1315 , X86_INS_VPSADBW = 1316 , X86_INS_VPSCATTERDD = 1317 , X86_INS_VPSCATTERDQ = 1318 , X86_INS_VPSCATTERQD = 1319 , X86_INS_VPSCATTERQQ = 1320 , X86_INS_VPSHAB = 1321 , X86_INS_VPSHAD = 1322 , X86_INS_VPSHAQ = 1323 , X86_INS_VPSHAW = 1324 , X86_INS_VPSHLB = 1325 , X86_INS_VPSHLDD = 1326 , X86_INS_VPSHLDQ = 1327 , X86_INS_VPSHLDVD = 1328 , X86_INS_VPSHLDVQ = 1329 , X86_INS_VPSHLDVW = 1330 , X86_INS_VPSHLDW = 1331 , X86_INS_VPSHLD = 1332 , X86_INS_VPSHLQ = 1333 , X86_INS_VPSHLW = 1334 , X86_INS_VPSHRDD = 1335 , X86_INS_VPSHRDQ = 1336 , X86_INS_VPSHRDVD = 1337 , X86_INS_VPSHRDVQ = 1338 , X86_INS_VPSHRDVW = 1339 , X86_INS_VPSHRDW = 1340 , X86_INS_VPSHUFBITQMB = 1341 , X86_INS_VPSHUFB = 1342 , X86_INS_VPSHUFD = 1343 , X86_INS_VPSHUFHW = 1344 , X86_INS_VPSHUFLW = 1345 , X86_INS_VPSIGNB = 1346 , X86_INS_VPSIGND = 1347 , X86_INS_VPSIGNW = 1348 , X86_INS_VPSLLDQ = 1349 , X86_INS_VPSLLD = 1350 , X86_INS_VPSLLQ = 1351 , X86_INS_VPSLLVD = 1352 , X86_INS_VPSLLVQ = 1353 , X86_INS_VPSLLVW = 1354 , X86_INS_VPSLLW = 1355 , X86_INS_VPSRAD = 1356 , X86_INS_VPSRAQ = 1357 , X86_INS_VPSRAVD = 1358 , X86_INS_VPSRAVQ = 1359 , X86_INS_VPSRAVW = 1360 , X86_INS_VPSRAW = 1361 , X86_INS_VPSRLDQ = 1362 , X86_INS_VPSRLD = 1363 , X86_INS_VPSRLQ = 1364 , X86_INS_VPSRLVD = 1365 , X86_INS_VPSRLVQ = 1366 , X86_INS_VPSRLVW = 1367 , X86_INS_VPSRLW = 1368 , X86_INS_VPSUBB = 1369 , X86_INS_VPSUBD = 1370 , X86_INS_VPSUBQ = 1371 , X86_INS_VPSUBSB = 1372 , X86_INS_VPSUBSW = 1373 , X86_INS_VPSUBUSB = 1374 , X86_INS_VPSUBUSW = 1375 , X86_INS_VPSUBW = 1376 , X86_INS_VPTERNLOGD = 1377 , X86_INS_VPTERNLOGQ = 1378 , X86_INS_VPTESTMB = 1379 , X86_INS_VPTESTMD = 1380 , X86_INS_VPTESTMQ = 1381 , X86_INS_VPTESTMW = 1382 , X86_INS_VPTESTNMB = 1383 , X86_INS_VPTESTNMD = 1384 , X86_INS_VPTESTNMQ = 1385 , X86_INS_VPTESTNMW = 1386 , X86_INS_VPTEST = 1387 , X86_INS_VPUNPCKHBW = 1388 , X86_INS_VPUNPCKHDQ = 1389 , X86_INS_VPUNPCKHQDQ = 1390 , X86_INS_VPUNPCKHWD = 1391 , X86_INS_VPUNPCKLBW = 1392 , X86_INS_VPUNPCKLDQ = 1393 , X86_INS_VPUNPCKLQDQ = 1394 , X86_INS_VPUNPCKLWD = 1395 , X86_INS_VPXORD = 1396 , X86_INS_VPXORQ = 1397 , X86_INS_VPXOR = 1398 , X86_INS_VRANGEPD = 1399 , X86_INS_VRANGEPS = 1400 , X86_INS_VRANGESD = 1401 , X86_INS_VRANGESS = 1402 , X86_INS_VRCP14PD = 1403 , X86_INS_VRCP14PS = 1404 , X86_INS_VRCP14SD = 1405 , X86_INS_VRCP14SS = 1406 , X86_INS_VRCP28PD = 1407 , X86_INS_VRCP28PS = 1408 , X86_INS_VRCP28SD = 1409 , X86_INS_VRCP28SS = 1410 , X86_INS_VRCPPS = 1411 , X86_INS_VRCPSS = 1412 , X86_INS_VREDUCEPD = 1413 , X86_INS_VREDUCEPS = 1414 , X86_INS_VREDUCESD = 1415 , X86_INS_VREDUCESS = 1416 , X86_INS_VRNDSCALEPD = 1417 , X86_INS_VRNDSCALEPS = 1418 , X86_INS_VRNDSCALESD = 1419 , X86_INS_VRNDSCALESS = 1420 , X86_INS_VROUNDPD = 1421 , X86_INS_VROUNDPS = 1422 , X86_INS_VROUNDSD = 1423 , X86_INS_VROUNDSS = 1424 , X86_INS_VRSQRT14PD = 1425 , X86_INS_VRSQRT14PS = 1426 , X86_INS_VRSQRT14SD = 1427 , X86_INS_VRSQRT14SS = 1428 , X86_INS_VRSQRT28PD = 1429 , X86_INS_VRSQRT28PS = 1430 , X86_INS_VRSQRT28SD = 1431 , X86_INS_VRSQRT28SS = 1432 , X86_INS_VRSQRTPS = 1433 , X86_INS_VRSQRTSS = 1434 , X86_INS_VSCALEFPD = 1435 , X86_INS_VSCALEFPS = 1436 , X86_INS_VSCALEFSD = 1437 , X86_INS_VSCALEFSS = 1438 , X86_INS_VSCATTERDPD = 1439 , X86_INS_VSCATTERDPS = 1440 , X86_INS_VSCATTERPF0DPD = 1441 , X86_INS_VSCATTERPF0DPS = 1442 , X86_INS_VSCATTERPF0QPD = 1443 , X86_INS_VSCATTERPF0QPS = 1444 , X86_INS_VSCATTERPF1DPD = 1445 , X86_INS_VSCATTERPF1DPS = 1446 , X86_INS_VSCATTERPF1QPD = 1447 , X86_INS_VSCATTERPF1QPS = 1448 , X86_INS_VSCATTERQPD = 1449 , X86_INS_VSCATTERQPS = 1450 , X86_INS_VSHUFF32X4 = 1451 , X86_INS_VSHUFF64X2 = 1452 , X86_INS_VSHUFI32X4 = 1453 , X86_INS_VSHUFI64X2 = 1454 , X86_INS_VSHUFPD = 1455 , X86_INS_VSHUFPS = 1456 , X86_INS_VSQRTPD = 1457 , X86_INS_VSQRTPS = 1458 , X86_INS_VSQRTSD = 1459 , X86_INS_VSQRTSS = 1460 , X86_INS_VSTMXCSR = 1461 , X86_INS_VSUBPD = 1462 , X86_INS_VSUBPS = 1463 , X86_INS_VSUBSD = 1464 , X86_INS_VSUBSS = 1465 , X86_INS_VTESTPD = 1466 , X86_INS_VTESTPS = 1467 , X86_INS_VUCOMISD = 1468 , X86_INS_VUCOMISS = 1469 , X86_INS_VUNPCKHPD = 1470 , X86_INS_VUNPCKHPS = 1471 , X86_INS_VUNPCKLPD = 1472 , X86_INS_VUNPCKLPS = 1473 , X86_INS_VXORPD = 1474 , X86_INS_VXORPS = 1475 , X86_INS_VZEROALL = 1476 , X86_INS_VZEROUPPER = 1477 , X86_INS_WAIT = 1478 , X86_INS_WBINVD = 1479 , X86_INS_WBNOINVD = 1480 , X86_INS_WRFSBASE = 1481 , X86_INS_WRGSBASE = 1482 , X86_INS_WRMSR = 1483 , X86_INS_WRPKRU = 1484 , X86_INS_WRSSD = 1485 , X86_INS_WRSSQ = 1486 , X86_INS_WRUSSD = 1487 , X86_INS_WRUSSQ = 1488 , X86_INS_XABORT = 1489 , X86_INS_XACQUIRE = 1490 , X86_INS_XADD = 1491 , X86_INS_XBEGIN = 1492 , X86_INS_XCHG = 1493 , X86_INS_FXCH = 1494 , X86_INS_XCRYPTCBC = 1495 , X86_INS_XCRYPTCFB = 1496 , X86_INS_XCRYPTCTR = 1497 , X86_INS_XCRYPTECB = 1498 , X86_INS_XCRYPTOFB = 1499 , X86_INS_XEND = 1500 , X86_INS_XGETBV = 1501 , X86_INS_XLATB = 1502 , X86_INS_XOR = 1503 , X86_INS_XORPD = 1504 , X86_INS_XORPS = 1505 , X86_INS_XRELEASE = 1506 , X86_INS_XRSTOR = 1507 , X86_INS_XRSTOR64 = 1508 , X86_INS_XRSTORS = 1509 , X86_INS_XRSTORS64 = 1510 , X86_INS_XSAVE = 1511 , X86_INS_XSAVE64 = 1512 , X86_INS_XSAVEC = 1513 , X86_INS_XSAVEC64 = 1514 , X86_INS_XSAVEOPT = 1515 , X86_INS_XSAVEOPT64 = 1516 , X86_INS_XSAVES = 1517 , X86_INS_XSAVES64 = 1518 , X86_INS_XSETBV = 1519 , X86_INS_XSHA1 = 1520 , X86_INS_XSHA256 = 1521 , X86_INS_XSTORE = 1522 , X86_INS_XTEST = 1523 , X86_INS_ENDING = 1524 , } # [repr (u32)] # [doc = " Group of X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn_group { # [doc = "< = CS_GRP_INVALID"] X86_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] X86_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] X86_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] X86_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] X86_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] X86_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] X86_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] X86_GRP_BRANCH_RELATIVE = 7 , # [doc = "< all virtualization instructions (VT-x + AMD-V)"] X86_GRP_VM = 128 , X86_GRP_3DNOW = 129 , X86_GRP_AES = 130 , X86_GRP_ADX = 131 , X86_GRP_AVX = 132 , X86_GRP_AVX2 = 133 , X86_GRP_AVX512 = 134 , X86_GRP_BMI = 135 , X86_GRP_BMI2 = 136 , X86_GRP_CMOV = 137 , X86_GRP_F16C = 138 , X86_GRP_FMA = 139 , X86_GRP_FMA4 = 140 , X86_GRP_FSGSBASE = 141 , X86_GRP_HLE = 142 , X86_GRP_MMX = 143 , X86_GRP_MODE32 = 144 , X86_GRP_MODE64 = 145 , X86_GRP_RTM = 146 , X86_GRP_SHA = 147 , X86_GRP_SSE1 = 148 , X86_GRP_SSE2 = 149 , X86_GRP_SSE3 = 150 , X86_GRP_SSE41 = 151 , X86_GRP_SSE42 = 152 , X86_GRP_SSE4A = 153 , X86_GRP_SSSE3 = 154 , X86_GRP_PCLMUL = 155 , X86_GRP_XOP = 156 , X86_GRP_CDI = 157 , X86_GRP_ERI = 158 , X86_GRP_TBM = 159 , X86_GRP_16BITMODE = 160 , X86_GRP_NOT64BITMODE = 161 , X86_GRP_SGX = 162 , X86_GRP_DQI = 163 , X86_GRP_BWI = 164 , X86_GRP_PFI = 165 , X86_GRP_VLX = 166 , X86_GRP_SMAP = 167 , X86_GRP_NOVLX = 168 , X86_GRP_FPU = 169 , X86_GRP_ENDING = 170 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] XCORE_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] XCORE_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] XCORE_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] XCORE_OP_MEM = 3 , } # [repr (u32)] # [doc = " XCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_reg { XCORE_REG_INVALID = 0 , XCORE_REG_CP = 1 , XCORE_REG_DP = 2 , XCORE_REG_LR = 3 , XCORE_REG_SP = 4 , XCORE_REG_R0 = 5 , XCORE_REG_R1 = 6 , XCORE_REG_R2 = 7 , XCORE_REG_R3 = 8 , XCORE_REG_R4 = 9 , XCORE_REG_R5 = 10 , XCORE_REG_R6 = 11 , XCORE_REG_R7 = 12 , XCORE_REG_R8 = 13 , XCORE_REG_R9 = 14 , XCORE_REG_R10 = 15 , XCORE_REG_R11 = 16 , # [doc = "< pc"] XCORE_REG_PC = 17 , # [doc = "< save pc"] XCORE_REG_SCP = 18 , XCORE_REG_SSR = 19 , XCORE_REG_ET = 20 , XCORE_REG_ED = 21 , XCORE_REG_SED = 22 , XCORE_REG_KEP = 23 , XCORE_REG_KSP = 24 , XCORE_REG_ID = 25 , XCORE_REG_ENDING = 26 , } # [doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct xcore_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , # [doc = "< +1: forward, -1: backward"] pub direct : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of xcore_op_mem"] [:: std :: mem :: size_of :: < xcore_op_mem > () - 12usize] ; ["Alignment of xcore_op_mem"] [:: std :: mem :: align_of :: < xcore_op_mem > () - 4usize] ; ["Offset of field: xcore_op_mem::base"] [:: std :: mem :: offset_of ! (xcore_op_mem , base) - 0usize] ; ["Offset of field: xcore_op_mem::index"] [:: std :: mem :: offset_of ! (xcore_op_mem , index) - 1usize] ; ["Offset of field: xcore_op_mem::disp"] [:: std :: mem :: offset_of ! (xcore_op_mem , disp) - 4usize] ; ["Offset of field: xcore_op_mem::direct"] [:: std :: mem :: offset_of ! (xcore_op_mem , direct) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore_op { # [doc = "< operand type"] pub type_ : xcore_op_type , pub __bindgen_anon_1 : cs_xcore_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_xcore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : xcore_reg , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : xcore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_xcore_op__bindgen_ty_1 > () - 12usize] ; ["Alignment of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_xcore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op"] [:: std :: mem :: size_of :: < cs_xcore_op > () - 16usize] ; ["Alignment of cs_xcore_op"] [:: std :: mem :: align_of :: < cs_xcore_op > () - 4usize] ; ["Offset of field: cs_xcore_op::type_"] [:: std :: mem :: offset_of ! (cs_xcore_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_xcore_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore"] [:: std :: mem :: size_of :: < cs_xcore > () - 132usize] ; ["Alignment of cs_xcore"] [:: std :: mem :: align_of :: < cs_xcore > () - 4usize] ; ["Offset of field: cs_xcore::op_count"] [:: std :: mem :: offset_of ! (cs_xcore , op_count) - 0usize] ; ["Offset of field: cs_xcore::operands"] [:: std :: mem :: offset_of ! (cs_xcore , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " XCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn { XCORE_INS_INVALID = 0 , XCORE_INS_ADD = 1 , XCORE_INS_ANDNOT = 2 , XCORE_INS_AND = 3 , XCORE_INS_ASHR = 4 , XCORE_INS_BAU = 5 , XCORE_INS_BITREV = 6 , XCORE_INS_BLA = 7 , XCORE_INS_BLAT = 8 , XCORE_INS_BL = 9 , XCORE_INS_BF = 10 , XCORE_INS_BT = 11 , XCORE_INS_BU = 12 , XCORE_INS_BRU = 13 , XCORE_INS_BYTEREV = 14 , XCORE_INS_CHKCT = 15 , XCORE_INS_CLRE = 16 , XCORE_INS_CLRPT = 17 , XCORE_INS_CLRSR = 18 , XCORE_INS_CLZ = 19 , XCORE_INS_CRC8 = 20 , XCORE_INS_CRC32 = 21 , XCORE_INS_DCALL = 22 , XCORE_INS_DENTSP = 23 , XCORE_INS_DGETREG = 24 , XCORE_INS_DIVS = 25 , XCORE_INS_DIVU = 26 , XCORE_INS_DRESTSP = 27 , XCORE_INS_DRET = 28 , XCORE_INS_ECALLF = 29 , XCORE_INS_ECALLT = 30 , XCORE_INS_EDU = 31 , XCORE_INS_EEF = 32 , XCORE_INS_EET = 33 , XCORE_INS_EEU = 34 , XCORE_INS_ENDIN = 35 , XCORE_INS_ENTSP = 36 , XCORE_INS_EQ = 37 , XCORE_INS_EXTDP = 38 , XCORE_INS_EXTSP = 39 , XCORE_INS_FREER = 40 , XCORE_INS_FREET = 41 , XCORE_INS_GETD = 42 , XCORE_INS_GET = 43 , XCORE_INS_GETN = 44 , XCORE_INS_GETR = 45 , XCORE_INS_GETSR = 46 , XCORE_INS_GETST = 47 , XCORE_INS_GETTS = 48 , XCORE_INS_INCT = 49 , XCORE_INS_INIT = 50 , XCORE_INS_INPW = 51 , XCORE_INS_INSHR = 52 , XCORE_INS_INT = 53 , XCORE_INS_IN = 54 , XCORE_INS_KCALL = 55 , XCORE_INS_KENTSP = 56 , XCORE_INS_KRESTSP = 57 , XCORE_INS_KRET = 58 , XCORE_INS_LADD = 59 , XCORE_INS_LD16S = 60 , XCORE_INS_LD8U = 61 , XCORE_INS_LDA16 = 62 , XCORE_INS_LDAP = 63 , XCORE_INS_LDAW = 64 , XCORE_INS_LDC = 65 , XCORE_INS_LDW = 66 , XCORE_INS_LDIVU = 67 , XCORE_INS_LMUL = 68 , XCORE_INS_LSS = 69 , XCORE_INS_LSUB = 70 , XCORE_INS_LSU = 71 , XCORE_INS_MACCS = 72 , XCORE_INS_MACCU = 73 , XCORE_INS_MJOIN = 74 , XCORE_INS_MKMSK = 75 , XCORE_INS_MSYNC = 76 , XCORE_INS_MUL = 77 , XCORE_INS_NEG = 78 , XCORE_INS_NOT = 79 , XCORE_INS_OR = 80 , XCORE_INS_OUTCT = 81 , XCORE_INS_OUTPW = 82 , XCORE_INS_OUTSHR = 83 , XCORE_INS_OUTT = 84 , XCORE_INS_OUT = 85 , XCORE_INS_PEEK = 86 , XCORE_INS_REMS = 87 , XCORE_INS_REMU = 88 , XCORE_INS_RETSP = 89 , XCORE_INS_SETCLK = 90 , XCORE_INS_SET = 91 , XCORE_INS_SETC = 92 , XCORE_INS_SETD = 93 , XCORE_INS_SETEV = 94 , XCORE_INS_SETN = 95 , XCORE_INS_SETPSC = 96 , XCORE_INS_SETPT = 97 , XCORE_INS_SETRDY = 98 , XCORE_INS_SETSR = 99 , XCORE_INS_SETTW = 100 , XCORE_INS_SETV = 101 , XCORE_INS_SEXT = 102 , XCORE_INS_SHL = 103 , XCORE_INS_SHR = 104 , XCORE_INS_SSYNC = 105 , XCORE_INS_ST16 = 106 , XCORE_INS_ST8 = 107 , XCORE_INS_STW = 108 , XCORE_INS_SUB = 109 , XCORE_INS_SYNCR = 110 , XCORE_INS_TESTCT = 111 , XCORE_INS_TESTLCL = 112 , XCORE_INS_TESTWCT = 113 , XCORE_INS_TSETMR = 114 , XCORE_INS_START = 115 , XCORE_INS_WAITEF = 116 , XCORE_INS_WAITET = 117 , XCORE_INS_WAITEU = 118 , XCORE_INS_XOR = 119 , XCORE_INS_ZEXT = 120 , XCORE_INS_ENDING = 121 , } # [repr (u32)] # [doc = " Group of XCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn_group { # [doc = "< = CS_GRP_INVALID"] XCORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] XCORE_GRP_JUMP = 1 , XCORE_GRP_ENDING = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] TMS320C64X_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] TMS320C64X_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] TMS320C64X_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] TMS320C64X_OP_MEM = 3 , # [doc = "< Register pair for double word ops"] TMS320C64X_OP_REGPAIR = 64 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0 , TMS320C64X_MEM_DISP_CONSTANT = 1 , TMS320C64X_MEM_DISP_REGISTER = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0 , TMS320C64X_MEM_DIR_FW = 1 , TMS320C64X_MEM_DIR_BW = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0 , TMS320C64X_MEM_MOD_NO = 1 , TMS320C64X_MEM_MOD_PRE = 2 , TMS320C64X_MEM_MOD_POST = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tms320c64x_op_mem { # [doc = "< base register"] pub base : :: std :: os :: raw :: c_uint , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_uint , # [doc = "< unit of base and offset register"] pub unit : :: std :: os :: raw :: c_uint , # [doc = "< offset scaled"] pub scaled : :: std :: os :: raw :: c_uint , # [doc = "< displacement type"] pub disptype : :: std :: os :: raw :: c_uint , # [doc = "< direction"] pub direction : :: std :: os :: raw :: c_uint , # [doc = "< modification"] pub modify : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tms320c64x_op_mem"] [:: std :: mem :: size_of :: < tms320c64x_op_mem > () - 28usize] ; ["Alignment of tms320c64x_op_mem"] [:: std :: mem :: align_of :: < tms320c64x_op_mem > () - 4usize] ; ["Offset of field: tms320c64x_op_mem::base"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , base) - 0usize] ; ["Offset of field: tms320c64x_op_mem::disp"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disp) - 4usize] ; ["Offset of field: tms320c64x_op_mem::unit"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , unit) - 8usize] ; ["Offset of field: tms320c64x_op_mem::scaled"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , scaled) - 12usize] ; ["Offset of field: tms320c64x_op_mem::disptype"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disptype) - 16usize] ; ["Offset of field: tms320c64x_op_mem::direction"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , direction) - 20usize] ; ["Offset of field: tms320c64x_op_mem::modify"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , modify) - 24usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x_op { # [doc = "< operand type"] pub type_ : tms320c64x_op_type , pub __bindgen_anon_1 : cs_tms320c64x_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tms320c64x_op__bindgen_ty_1 { # [doc = "< register value for REG operand or first register for REGPAIR operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tms320c64x_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 28usize] ; ["Alignment of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op"] [:: std :: mem :: size_of :: < cs_tms320c64x_op > () - 32usize] ; ["Alignment of cs_tms320c64x_op"] [:: std :: mem :: align_of :: < cs_tms320c64x_op > () - 4usize] ; ["Offset of field: cs_tms320c64x_op::type_"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x { pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tms320c64x_op ; 8usize] , pub condition : cs_tms320c64x__bindgen_ty_1 , pub funit : cs_tms320c64x__bindgen_ty_2 , pub parallel : :: std :: os :: raw :: c_uint , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub zero : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::zero"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , zero) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_2 { pub unit : :: std :: os :: raw :: c_uint , pub side : :: std :: os :: raw :: c_uint , pub crosspath : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_2 > () - 12usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_2 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::unit"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , unit) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::side"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , side) - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::crosspath"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , crosspath) - 8usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x"] [:: std :: mem :: size_of :: < cs_tms320c64x > () - 284usize] ; ["Alignment of cs_tms320c64x"] [:: std :: mem :: align_of :: < cs_tms320c64x > () - 4usize] ; ["Offset of field: cs_tms320c64x::op_count"] [:: std :: mem :: offset_of ! (cs_tms320c64x , op_count) - 0usize] ; ["Offset of field: cs_tms320c64x::operands"] [:: std :: mem :: offset_of ! (cs_tms320c64x , operands) - 4usize] ; ["Offset of field: cs_tms320c64x::condition"] [:: std :: mem :: offset_of ! (cs_tms320c64x , condition) - 260usize] ; ["Offset of field: cs_tms320c64x::funit"] [:: std :: mem :: offset_of ! (cs_tms320c64x , funit) - 268usize] ; ["Offset of field: cs_tms320c64x::parallel"] [:: std :: mem :: offset_of ! (cs_tms320c64x , parallel) - 280usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel) } } impl tms320c64x_reg { pub const TMS320C64X_REG_EFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ECR ; } impl tms320c64x_reg { pub const TMS320C64X_REG_IFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ISR ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0 , TMS320C64X_REG_AMR = 1 , TMS320C64X_REG_CSR = 2 , TMS320C64X_REG_DIER = 3 , TMS320C64X_REG_DNUM = 4 , TMS320C64X_REG_ECR = 5 , TMS320C64X_REG_GFPGFR = 6 , TMS320C64X_REG_GPLYA = 7 , TMS320C64X_REG_GPLYB = 8 , TMS320C64X_REG_ICR = 9 , TMS320C64X_REG_IER = 10 , TMS320C64X_REG_IERR = 11 , TMS320C64X_REG_ILC = 12 , TMS320C64X_REG_IRP = 13 , TMS320C64X_REG_ISR = 14 , TMS320C64X_REG_ISTP = 15 , TMS320C64X_REG_ITSR = 16 , TMS320C64X_REG_NRP = 17 , TMS320C64X_REG_NTSR = 18 , TMS320C64X_REG_REP = 19 , TMS320C64X_REG_RILC = 20 , TMS320C64X_REG_SSR = 21 , TMS320C64X_REG_TSCH = 22 , TMS320C64X_REG_TSCL = 23 , TMS320C64X_REG_TSR = 24 , TMS320C64X_REG_A0 = 25 , TMS320C64X_REG_A1 = 26 , TMS320C64X_REG_A2 = 27 , TMS320C64X_REG_A3 = 28 , TMS320C64X_REG_A4 = 29 , TMS320C64X_REG_A5 = 30 , TMS320C64X_REG_A6 = 31 , TMS320C64X_REG_A7 = 32 , TMS320C64X_REG_A8 = 33 , TMS320C64X_REG_A9 = 34 , TMS320C64X_REG_A10 = 35 , TMS320C64X_REG_A11 = 36 , TMS320C64X_REG_A12 = 37 , TMS320C64X_REG_A13 = 38 , TMS320C64X_REG_A14 = 39 , TMS320C64X_REG_A15 = 40 , TMS320C64X_REG_A16 = 41 , TMS320C64X_REG_A17 = 42 , TMS320C64X_REG_A18 = 43 , TMS320C64X_REG_A19 = 44 , TMS320C64X_REG_A20 = 45 , TMS320C64X_REG_A21 = 46 , TMS320C64X_REG_A22 = 47 , TMS320C64X_REG_A23 = 48 , TMS320C64X_REG_A24 = 49 , TMS320C64X_REG_A25 = 50 , TMS320C64X_REG_A26 = 51 , TMS320C64X_REG_A27 = 52 , TMS320C64X_REG_A28 = 53 , TMS320C64X_REG_A29 = 54 , TMS320C64X_REG_A30 = 55 , TMS320C64X_REG_A31 = 56 , TMS320C64X_REG_B0 = 57 , TMS320C64X_REG_B1 = 58 , TMS320C64X_REG_B2 = 59 , TMS320C64X_REG_B3 = 60 , TMS320C64X_REG_B4 = 61 , TMS320C64X_REG_B5 = 62 , TMS320C64X_REG_B6 = 63 , TMS320C64X_REG_B7 = 64 , TMS320C64X_REG_B8 = 65 , TMS320C64X_REG_B9 = 66 , TMS320C64X_REG_B10 = 67 , TMS320C64X_REG_B11 = 68 , TMS320C64X_REG_B12 = 69 , TMS320C64X_REG_B13 = 70 , TMS320C64X_REG_B14 = 71 , TMS320C64X_REG_B15 = 72 , TMS320C64X_REG_B16 = 73 , TMS320C64X_REG_B17 = 74 , TMS320C64X_REG_B18 = 75 , TMS320C64X_REG_B19 = 76 , TMS320C64X_REG_B20 = 77 , TMS320C64X_REG_B21 = 78 , TMS320C64X_REG_B22 = 79 , TMS320C64X_REG_B23 = 80 , TMS320C64X_REG_B24 = 81 , TMS320C64X_REG_B25 = 82 , TMS320C64X_REG_B26 = 83 , TMS320C64X_REG_B27 = 84 , TMS320C64X_REG_B28 = 85 , TMS320C64X_REG_B29 = 86 , TMS320C64X_REG_B30 = 87 , TMS320C64X_REG_B31 = 88 , TMS320C64X_REG_PCE1 = 89 , TMS320C64X_REG_ENDING = 90 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0 , TMS320C64X_INS_ABS = 1 , TMS320C64X_INS_ABS2 = 2 , TMS320C64X_INS_ADD = 3 , TMS320C64X_INS_ADD2 = 4 , TMS320C64X_INS_ADD4 = 5 , TMS320C64X_INS_ADDAB = 6 , TMS320C64X_INS_ADDAD = 7 , TMS320C64X_INS_ADDAH = 8 , TMS320C64X_INS_ADDAW = 9 , TMS320C64X_INS_ADDK = 10 , TMS320C64X_INS_ADDKPC = 11 , TMS320C64X_INS_ADDU = 12 , TMS320C64X_INS_AND = 13 , TMS320C64X_INS_ANDN = 14 , TMS320C64X_INS_AVG2 = 15 , TMS320C64X_INS_AVGU4 = 16 , TMS320C64X_INS_B = 17 , TMS320C64X_INS_BDEC = 18 , TMS320C64X_INS_BITC4 = 19 , TMS320C64X_INS_BNOP = 20 , TMS320C64X_INS_BPOS = 21 , TMS320C64X_INS_CLR = 22 , TMS320C64X_INS_CMPEQ = 23 , TMS320C64X_INS_CMPEQ2 = 24 , TMS320C64X_INS_CMPEQ4 = 25 , TMS320C64X_INS_CMPGT = 26 , TMS320C64X_INS_CMPGT2 = 27 , TMS320C64X_INS_CMPGTU4 = 28 , TMS320C64X_INS_CMPLT = 29 , TMS320C64X_INS_CMPLTU = 30 , TMS320C64X_INS_DEAL = 31 , TMS320C64X_INS_DOTP2 = 32 , TMS320C64X_INS_DOTPN2 = 33 , TMS320C64X_INS_DOTPNRSU2 = 34 , TMS320C64X_INS_DOTPRSU2 = 35 , TMS320C64X_INS_DOTPSU4 = 36 , TMS320C64X_INS_DOTPU4 = 37 , TMS320C64X_INS_EXT = 38 , TMS320C64X_INS_EXTU = 39 , TMS320C64X_INS_GMPGTU = 40 , TMS320C64X_INS_GMPY4 = 41 , TMS320C64X_INS_LDB = 42 , TMS320C64X_INS_LDBU = 43 , TMS320C64X_INS_LDDW = 44 , TMS320C64X_INS_LDH = 45 , TMS320C64X_INS_LDHU = 46 , TMS320C64X_INS_LDNDW = 47 , TMS320C64X_INS_LDNW = 48 , TMS320C64X_INS_LDW = 49 , TMS320C64X_INS_LMBD = 50 , TMS320C64X_INS_MAX2 = 51 , TMS320C64X_INS_MAXU4 = 52 , TMS320C64X_INS_MIN2 = 53 , TMS320C64X_INS_MINU4 = 54 , TMS320C64X_INS_MPY = 55 , TMS320C64X_INS_MPY2 = 56 , TMS320C64X_INS_MPYH = 57 , TMS320C64X_INS_MPYHI = 58 , TMS320C64X_INS_MPYHIR = 59 , TMS320C64X_INS_MPYHL = 60 , TMS320C64X_INS_MPYHLU = 61 , TMS320C64X_INS_MPYHSLU = 62 , TMS320C64X_INS_MPYHSU = 63 , TMS320C64X_INS_MPYHU = 64 , TMS320C64X_INS_MPYHULS = 65 , TMS320C64X_INS_MPYHUS = 66 , TMS320C64X_INS_MPYLH = 67 , TMS320C64X_INS_MPYLHU = 68 , TMS320C64X_INS_MPYLI = 69 , TMS320C64X_INS_MPYLIR = 70 , TMS320C64X_INS_MPYLSHU = 71 , TMS320C64X_INS_MPYLUHS = 72 , TMS320C64X_INS_MPYSU = 73 , TMS320C64X_INS_MPYSU4 = 74 , TMS320C64X_INS_MPYU = 75 , TMS320C64X_INS_MPYU4 = 76 , TMS320C64X_INS_MPYUS = 77 , TMS320C64X_INS_MVC = 78 , TMS320C64X_INS_MVD = 79 , TMS320C64X_INS_MVK = 80 , TMS320C64X_INS_MVKL = 81 , TMS320C64X_INS_MVKLH = 82 , TMS320C64X_INS_NOP = 83 , TMS320C64X_INS_NORM = 84 , TMS320C64X_INS_OR = 85 , TMS320C64X_INS_PACK2 = 86 , TMS320C64X_INS_PACKH2 = 87 , TMS320C64X_INS_PACKH4 = 88 , TMS320C64X_INS_PACKHL2 = 89 , TMS320C64X_INS_PACKL4 = 90 , TMS320C64X_INS_PACKLH2 = 91 , TMS320C64X_INS_ROTL = 92 , TMS320C64X_INS_SADD = 93 , TMS320C64X_INS_SADD2 = 94 , TMS320C64X_INS_SADDU4 = 95 , TMS320C64X_INS_SADDUS2 = 96 , TMS320C64X_INS_SAT = 97 , TMS320C64X_INS_SET = 98 , TMS320C64X_INS_SHFL = 99 , TMS320C64X_INS_SHL = 100 , TMS320C64X_INS_SHLMB = 101 , TMS320C64X_INS_SHR = 102 , TMS320C64X_INS_SHR2 = 103 , TMS320C64X_INS_SHRMB = 104 , TMS320C64X_INS_SHRU = 105 , TMS320C64X_INS_SHRU2 = 106 , TMS320C64X_INS_SMPY = 107 , TMS320C64X_INS_SMPY2 = 108 , TMS320C64X_INS_SMPYH = 109 , TMS320C64X_INS_SMPYHL = 110 , TMS320C64X_INS_SMPYLH = 111 , TMS320C64X_INS_SPACK2 = 112 , TMS320C64X_INS_SPACKU4 = 113 , TMS320C64X_INS_SSHL = 114 , TMS320C64X_INS_SSHVL = 115 , TMS320C64X_INS_SSHVR = 116 , TMS320C64X_INS_SSUB = 117 , TMS320C64X_INS_STB = 118 , TMS320C64X_INS_STDW = 119 , TMS320C64X_INS_STH = 120 , TMS320C64X_INS_STNDW = 121 , TMS320C64X_INS_STNW = 122 , TMS320C64X_INS_STW = 123 , TMS320C64X_INS_SUB = 124 , TMS320C64X_INS_SUB2 = 125 , TMS320C64X_INS_SUB4 = 126 , TMS320C64X_INS_SUBAB = 127 , TMS320C64X_INS_SUBABS4 = 128 , TMS320C64X_INS_SUBAH = 129 , TMS320C64X_INS_SUBAW = 130 , TMS320C64X_INS_SUBC = 131 , TMS320C64X_INS_SUBU = 132 , TMS320C64X_INS_SWAP4 = 133 , TMS320C64X_INS_UNPKHU4 = 134 , TMS320C64X_INS_UNPKLU4 = 135 , TMS320C64X_INS_XOR = 136 , TMS320C64X_INS_XPND2 = 137 , TMS320C64X_INS_XPND4 = 138 , TMS320C64X_INS_IDLE = 139 , TMS320C64X_INS_MV = 140 , TMS320C64X_INS_NEG = 141 , TMS320C64X_INS_NOT = 142 , TMS320C64X_INS_SWAP2 = 143 , TMS320C64X_INS_ZERO = 144 , TMS320C64X_INS_ENDING = 145 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn_group { # [doc = "< = CS_GRP_INVALID"] TMS320C64X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] TMS320C64X_GRP_JUMP = 1 , TMS320C64X_GRP_FUNIT_D = 128 , TMS320C64X_GRP_FUNIT_L = 129 , TMS320C64X_GRP_FUNIT_M = 130 , TMS320C64X_GRP_FUNIT_S = 131 , TMS320C64X_GRP_FUNIT_NO = 132 , TMS320C64X_GRP_ENDING = 133 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0 , TMS320C64X_FUNIT_D = 1 , TMS320C64X_FUNIT_L = 2 , TMS320C64X_FUNIT_M = 3 , TMS320C64X_FUNIT_S = 4 , TMS320C64X_FUNIT_NO = 5 , } # [repr (u32)] # [doc = " M680X registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_reg { M680X_REG_INVALID = 0 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_A = 1 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_B = 2 , # [doc = "< HD6309"] M680X_REG_E = 3 , # [doc = "< HD6309"] M680X_REG_F = 4 , # [doc = "< HD6309"] M680X_REG_0 = 5 , # [doc = "< M6801/3/9, HD6301/9"] M680X_REG_D = 6 , # [doc = "< HD6309"] M680X_REG_W = 7 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_CC = 8 , # [doc = "< M6809/M6309"] M680X_REG_DP = 9 , # [doc = "< M6309"] M680X_REG_MD = 10 , # [doc = "< M6808"] M680X_REG_HX = 11 , # [doc = "< M6808"] M680X_REG_H = 12 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_X = 13 , # [doc = "< M6809/M6309"] M680X_REG_Y = 14 , # [doc = "< M6809/M6309"] M680X_REG_S = 15 , # [doc = "< M6809/M6309"] M680X_REG_U = 16 , # [doc = "< M6309"] M680X_REG_V = 17 , # [doc = "< M6309"] M680X_REG_Q = 18 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_PC = 19 , # [doc = "< CPU12"] M680X_REG_TMP2 = 20 , # [doc = "< CPU12"] M680X_REG_TMP3 = 21 , # [doc = "< <-- mark the end of the list of registers"] M680X_REG_ENDING = 22 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M680X_OP_INVALID = 0 , # [doc = "< = Register operand."] M680X_OP_REGISTER = 1 , # [doc = "< = Immediate operand."] M680X_OP_IMMEDIATE = 2 , # [doc = "< = Indexed addressing operand."] M680X_OP_INDEXED = 3 , # [doc = "< = Extended addressing operand."] M680X_OP_EXTENDED = 4 , # [doc = "< = Direct addressing operand."] M680X_OP_DIRECT = 5 , # [doc = "< = Relative addressing operand."] M680X_OP_RELATIVE = 6 , # [doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."] M680X_OP_CONSTANT = 7 , } # [doc = " Instruction's operand referring to indexed addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_idx { # [doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"] pub base_reg : m680x_reg , # [doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"] pub offset_reg : m680x_reg , # [doc = "< 5-,8- or 16-bit offset. See also offset_bits."] pub offset : i16 , # [doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"] pub offset_addr : u16 , # [doc = "< offset width in bits for indexed addressing"] pub offset_bits : u8 , # [doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"] pub inc_dec : i8 , # [doc = "< 8-bit flags (see above)"] pub flags : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_idx"] [:: std :: mem :: size_of :: < m680x_op_idx > () - 16usize] ; ["Alignment of m680x_op_idx"] [:: std :: mem :: align_of :: < m680x_op_idx > () - 4usize] ; ["Offset of field: m680x_op_idx::base_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , base_reg) - 0usize] ; ["Offset of field: m680x_op_idx::offset_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_reg) - 4usize] ; ["Offset of field: m680x_op_idx::offset"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset) - 8usize] ; ["Offset of field: m680x_op_idx::offset_addr"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_addr) - 10usize] ; ["Offset of field: m680x_op_idx::offset_bits"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_bits) - 12usize] ; ["Offset of field: m680x_op_idx::inc_dec"] [:: std :: mem :: offset_of ! (m680x_op_idx , inc_dec) - 13usize] ; ["Offset of field: m680x_op_idx::flags"] [:: std :: mem :: offset_of ! (m680x_op_idx , flags) - 14usize] ; } ; # [doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_rel { # [doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."] pub address : u16 , # [doc = "< the offset/displacement value"] pub offset : i16 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_rel"] [:: std :: mem :: size_of :: < m680x_op_rel > () - 4usize] ; ["Alignment of m680x_op_rel"] [:: std :: mem :: align_of :: < m680x_op_rel > () - 2usize] ; ["Offset of field: m680x_op_rel::address"] [:: std :: mem :: offset_of ! (m680x_op_rel , address) - 0usize] ; ["Offset of field: m680x_op_rel::offset"] [:: std :: mem :: offset_of ! (m680x_op_rel , offset) - 2usize] ; } ; # [doc = " Instruction's operand referring to extended addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_ext { # [doc = "< The absolute address"] pub address : u16 , # [doc = "< true if extended indirect addressing"] pub indirect : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_ext"] [:: std :: mem :: size_of :: < m680x_op_ext > () - 4usize] ; ["Alignment of m680x_op_ext"] [:: std :: mem :: align_of :: < m680x_op_ext > () - 2usize] ; ["Offset of field: m680x_op_ext::address"] [:: std :: mem :: offset_of ! (m680x_op_ext , address) - 0usize] ; ["Offset of field: m680x_op_ext::indirect"] [:: std :: mem :: offset_of ! (m680x_op_ext , indirect) - 2usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x_op { pub type_ : m680x_op_type , pub __bindgen_anon_1 : cs_m680x_op__bindgen_ty_1 , # [doc = "< size of this operand (in bytes)"] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m680x_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< register value for REG operand"] pub reg : m680x_reg , # [doc = "< Indexed addressing operand"] pub idx : m680x_op_idx , # [doc = "< Relative address. operand (Bcc/LBcc)"] pub rel : m680x_op_rel , # [doc = "< Extended address"] pub ext : m680x_op_ext , # [doc = "<</ Direct address (lower 8-bit)"] pub direct_addr : u8 , # [doc = "< constant value (bit index, page nr.)"] pub const_val : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m680x_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m680x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::idx"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , idx) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::rel"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , rel) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , ext) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::direct_addr"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , direct_addr) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::const_val"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , const_val) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op"] [:: std :: mem :: size_of :: < cs_m680x_op > () - 24usize] ; ["Alignment of cs_m680x_op"] [:: std :: mem :: align_of :: < cs_m680x_op > () - 4usize] ; ["Offset of field: cs_m680x_op::type_"] [:: std :: mem :: offset_of ! (cs_m680x_op , type_) - 0usize] ; ["Offset of field: cs_m680x_op::size"] [:: std :: mem :: offset_of ! (cs_m680x_op , size) - 20usize] ; ["Offset of field: cs_m680x_op::access"] [:: std :: mem :: offset_of ! (cs_m680x_op , access) - 21usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access) } } # [repr (u32)] # [doc = " Group of M680X instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_group_type { M680X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M680X_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] M680X_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] M680X_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] M680X_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] M680X_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEDGE; not used"] M680X_GRP_PRIV = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M680X_GRP_BRAREL = 7 , M680X_GRP_ENDING = 8 , } # [doc = " The M680X instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x { # [doc = "< See: M680X instruction flags"] pub flags : u8 , # [doc = "< number of operands for the instruction or 0"] pub op_count : u8 , # [doc = "< operands for this insn."] pub operands : [cs_m680x_op ; 9usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x"] [:: std :: mem :: size_of :: < cs_m680x > () - 220usize] ; ["Alignment of cs_m680x"] [:: std :: mem :: align_of :: < cs_m680x > () - 4usize] ; ["Offset of field: cs_m680x::flags"] [:: std :: mem :: offset_of ! (cs_m680x , flags) - 0usize] ; ["Offset of field: cs_m680x::op_count"] [:: std :: mem :: offset_of ! (cs_m680x , op_count) - 1usize] ; ["Offset of field: cs_m680x::operands"] [:: std :: mem :: offset_of ! (cs_m680x , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " M680X instruction IDs"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_insn { M680X_INS_INVLD = 0 , # [doc = "< M6800/1/2/3"] M680X_INS_ABA = 1 , M680X_INS_ABX = 2 , M680X_INS_ABY = 3 , M680X_INS_ADC = 4 , M680X_INS_ADCA = 5 , M680X_INS_ADCB = 6 , M680X_INS_ADCD = 7 , M680X_INS_ADCR = 8 , M680X_INS_ADD = 9 , M680X_INS_ADDA = 10 , M680X_INS_ADDB = 11 , M680X_INS_ADDD = 12 , M680X_INS_ADDE = 13 , M680X_INS_ADDF = 14 , M680X_INS_ADDR = 15 , M680X_INS_ADDW = 16 , M680X_INS_AIM = 17 , M680X_INS_AIS = 18 , M680X_INS_AIX = 19 , M680X_INS_AND = 20 , M680X_INS_ANDA = 21 , M680X_INS_ANDB = 22 , M680X_INS_ANDCC = 23 , M680X_INS_ANDD = 24 , M680X_INS_ANDR = 25 , M680X_INS_ASL = 26 , M680X_INS_ASLA = 27 , M680X_INS_ASLB = 28 , # [doc = "< or LSLD"] M680X_INS_ASLD = 29 , M680X_INS_ASR = 30 , M680X_INS_ASRA = 31 , M680X_INS_ASRB = 32 , M680X_INS_ASRD = 33 , M680X_INS_ASRX = 34 , M680X_INS_BAND = 35 , # [doc = "< or BHS"] M680X_INS_BCC = 36 , M680X_INS_BCLR = 37 , # [doc = "< or BLO"] M680X_INS_BCS = 38 , M680X_INS_BEOR = 39 , M680X_INS_BEQ = 40 , M680X_INS_BGE = 41 , M680X_INS_BGND = 42 , M680X_INS_BGT = 43 , M680X_INS_BHCC = 44 , M680X_INS_BHCS = 45 , M680X_INS_BHI = 46 , M680X_INS_BIAND = 47 , M680X_INS_BIEOR = 48 , M680X_INS_BIH = 49 , M680X_INS_BIL = 50 , M680X_INS_BIOR = 51 , M680X_INS_BIT = 52 , M680X_INS_BITA = 53 , M680X_INS_BITB = 54 , M680X_INS_BITD = 55 , M680X_INS_BITMD = 56 , M680X_INS_BLE = 57 , M680X_INS_BLS = 58 , M680X_INS_BLT = 59 , M680X_INS_BMC = 60 , M680X_INS_BMI = 61 , M680X_INS_BMS = 62 , M680X_INS_BNE = 63 , M680X_INS_BOR = 64 , M680X_INS_BPL = 65 , M680X_INS_BRCLR = 66 , M680X_INS_BRSET = 67 , M680X_INS_BRA = 68 , M680X_INS_BRN = 69 , M680X_INS_BSET = 70 , M680X_INS_BSR = 71 , M680X_INS_BVC = 72 , M680X_INS_BVS = 73 , M680X_INS_CALL = 74 , # [doc = "< M6800/1/2/3"] M680X_INS_CBA = 75 , M680X_INS_CBEQ = 76 , M680X_INS_CBEQA = 77 , M680X_INS_CBEQX = 78 , # [doc = "< M6800/1/2/3"] M680X_INS_CLC = 79 , # [doc = "< M6800/1/2/3"] M680X_INS_CLI = 80 , M680X_INS_CLR = 81 , M680X_INS_CLRA = 82 , M680X_INS_CLRB = 83 , M680X_INS_CLRD = 84 , M680X_INS_CLRE = 85 , M680X_INS_CLRF = 86 , M680X_INS_CLRH = 87 , M680X_INS_CLRW = 88 , M680X_INS_CLRX = 89 , # [doc = "< M6800/1/2/3"] M680X_INS_CLV = 90 , M680X_INS_CMP = 91 , M680X_INS_CMPA = 92 , M680X_INS_CMPB = 93 , M680X_INS_CMPD = 94 , M680X_INS_CMPE = 95 , M680X_INS_CMPF = 96 , M680X_INS_CMPR = 97 , M680X_INS_CMPS = 98 , M680X_INS_CMPU = 99 , M680X_INS_CMPW = 100 , M680X_INS_CMPX = 101 , M680X_INS_CMPY = 102 , M680X_INS_COM = 103 , M680X_INS_COMA = 104 , M680X_INS_COMB = 105 , M680X_INS_COMD = 106 , M680X_INS_COME = 107 , M680X_INS_COMF = 108 , M680X_INS_COMW = 109 , M680X_INS_COMX = 110 , M680X_INS_CPD = 111 , M680X_INS_CPHX = 112 , M680X_INS_CPS = 113 , # [doc = "< M6800/1/2/3"] M680X_INS_CPX = 114 , M680X_INS_CPY = 115 , M680X_INS_CWAI = 116 , M680X_INS_DAA = 117 , M680X_INS_DBEQ = 118 , M680X_INS_DBNE = 119 , M680X_INS_DBNZ = 120 , M680X_INS_DBNZA = 121 , M680X_INS_DBNZX = 122 , M680X_INS_DEC = 123 , M680X_INS_DECA = 124 , M680X_INS_DECB = 125 , M680X_INS_DECD = 126 , M680X_INS_DECE = 127 , M680X_INS_DECF = 128 , M680X_INS_DECW = 129 , M680X_INS_DECX = 130 , # [doc = "< M6800/1/2/3"] M680X_INS_DES = 131 , # [doc = "< M6800/1/2/3"] M680X_INS_DEX = 132 , M680X_INS_DEY = 133 , M680X_INS_DIV = 134 , M680X_INS_DIVD = 135 , M680X_INS_DIVQ = 136 , M680X_INS_EDIV = 137 , M680X_INS_EDIVS = 138 , M680X_INS_EIM = 139 , M680X_INS_EMACS = 140 , M680X_INS_EMAXD = 141 , M680X_INS_EMAXM = 142 , M680X_INS_EMIND = 143 , M680X_INS_EMINM = 144 , M680X_INS_EMUL = 145 , M680X_INS_EMULS = 146 , M680X_INS_EOR = 147 , M680X_INS_EORA = 148 , M680X_INS_EORB = 149 , M680X_INS_EORD = 150 , M680X_INS_EORR = 151 , M680X_INS_ETBL = 152 , M680X_INS_EXG = 153 , M680X_INS_FDIV = 154 , M680X_INS_IBEQ = 155 , M680X_INS_IBNE = 156 , M680X_INS_IDIV = 157 , M680X_INS_IDIVS = 158 , M680X_INS_ILLGL = 159 , M680X_INS_INC = 160 , M680X_INS_INCA = 161 , M680X_INS_INCB = 162 , M680X_INS_INCD = 163 , M680X_INS_INCE = 164 , M680X_INS_INCF = 165 , M680X_INS_INCW = 166 , M680X_INS_INCX = 167 , # [doc = "< M6800/1/2/3"] M680X_INS_INS = 168 , # [doc = "< M6800/1/2/3"] M680X_INS_INX = 169 , M680X_INS_INY = 170 , M680X_INS_JMP = 171 , M680X_INS_JSR = 172 , # [doc = "< or LBHS"] M680X_INS_LBCC = 173 , # [doc = "< or LBLO"] M680X_INS_LBCS = 174 , M680X_INS_LBEQ = 175 , M680X_INS_LBGE = 176 , M680X_INS_LBGT = 177 , M680X_INS_LBHI = 178 , M680X_INS_LBLE = 179 , M680X_INS_LBLS = 180 , M680X_INS_LBLT = 181 , M680X_INS_LBMI = 182 , M680X_INS_LBNE = 183 , M680X_INS_LBPL = 184 , M680X_INS_LBRA = 185 , M680X_INS_LBRN = 186 , M680X_INS_LBSR = 187 , M680X_INS_LBVC = 188 , M680X_INS_LBVS = 189 , M680X_INS_LDA = 190 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAA = 191 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAB = 192 , M680X_INS_LDB = 193 , M680X_INS_LDBT = 194 , M680X_INS_LDD = 195 , M680X_INS_LDE = 196 , M680X_INS_LDF = 197 , M680X_INS_LDHX = 198 , M680X_INS_LDMD = 199 , M680X_INS_LDQ = 200 , M680X_INS_LDS = 201 , M680X_INS_LDU = 202 , M680X_INS_LDW = 203 , M680X_INS_LDX = 204 , M680X_INS_LDY = 205 , M680X_INS_LEAS = 206 , M680X_INS_LEAU = 207 , M680X_INS_LEAX = 208 , M680X_INS_LEAY = 209 , M680X_INS_LSL = 210 , M680X_INS_LSLA = 211 , M680X_INS_LSLB = 212 , M680X_INS_LSLD = 213 , M680X_INS_LSLX = 214 , M680X_INS_LSR = 215 , M680X_INS_LSRA = 216 , M680X_INS_LSRB = 217 , # [doc = "< or ASRD"] M680X_INS_LSRD = 218 , M680X_INS_LSRW = 219 , M680X_INS_LSRX = 220 , M680X_INS_MAXA = 221 , M680X_INS_MAXM = 222 , M680X_INS_MEM = 223 , M680X_INS_MINA = 224 , M680X_INS_MINM = 225 , M680X_INS_MOV = 226 , M680X_INS_MOVB = 227 , M680X_INS_MOVW = 228 , M680X_INS_MUL = 229 , M680X_INS_MULD = 230 , M680X_INS_NEG = 231 , M680X_INS_NEGA = 232 , M680X_INS_NEGB = 233 , M680X_INS_NEGD = 234 , M680X_INS_NEGX = 235 , M680X_INS_NOP = 236 , M680X_INS_NSA = 237 , M680X_INS_OIM = 238 , M680X_INS_ORA = 239 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAA = 240 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAB = 241 , M680X_INS_ORB = 242 , M680X_INS_ORCC = 243 , M680X_INS_ORD = 244 , M680X_INS_ORR = 245 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHA = 246 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHB = 247 , M680X_INS_PSHC = 248 , M680X_INS_PSHD = 249 , M680X_INS_PSHH = 250 , M680X_INS_PSHS = 251 , M680X_INS_PSHSW = 252 , M680X_INS_PSHU = 253 , M680X_INS_PSHUW = 254 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHX = 255 , M680X_INS_PSHY = 256 , # [doc = "< M6800/1/2/3"] M680X_INS_PULA = 257 , # [doc = "< M6800/1/2/3"] M680X_INS_PULB = 258 , M680X_INS_PULC = 259 , M680X_INS_PULD = 260 , M680X_INS_PULH = 261 , M680X_INS_PULS = 262 , M680X_INS_PULSW = 263 , M680X_INS_PULU = 264 , M680X_INS_PULUW = 265 , # [doc = "< M6800/1/2/3"] M680X_INS_PULX = 266 , M680X_INS_PULY = 267 , M680X_INS_REV = 268 , M680X_INS_REVW = 269 , M680X_INS_ROL = 270 , M680X_INS_ROLA = 271 , M680X_INS_ROLB = 272 , M680X_INS_ROLD = 273 , M680X_INS_ROLW = 274 , M680X_INS_ROLX = 275 , M680X_INS_ROR = 276 , M680X_INS_RORA = 277 , M680X_INS_RORB = 278 , M680X_INS_RORD = 279 , M680X_INS_RORW = 280 , M680X_INS_RORX = 281 , M680X_INS_RSP = 282 , M680X_INS_RTC = 283 , M680X_INS_RTI = 284 , M680X_INS_RTS = 285 , # [doc = "< M6800/1/2/3"] M680X_INS_SBA = 286 , M680X_INS_SBC = 287 , M680X_INS_SBCA = 288 , M680X_INS_SBCB = 289 , M680X_INS_SBCD = 290 , M680X_INS_SBCR = 291 , M680X_INS_SEC = 292 , M680X_INS_SEI = 293 , M680X_INS_SEV = 294 , M680X_INS_SEX = 295 , M680X_INS_SEXW = 296 , M680X_INS_SLP = 297 , M680X_INS_STA = 298 , # [doc = "< M6800/1/2/3"] M680X_INS_STAA = 299 , # [doc = "< M6800/1/2/3"] M680X_INS_STAB = 300 , M680X_INS_STB = 301 , M680X_INS_STBT = 302 , M680X_INS_STD = 303 , M680X_INS_STE = 304 , M680X_INS_STF = 305 , M680X_INS_STOP = 306 , M680X_INS_STHX = 307 , M680X_INS_STQ = 308 , M680X_INS_STS = 309 , M680X_INS_STU = 310 , M680X_INS_STW = 311 , M680X_INS_STX = 312 , M680X_INS_STY = 313 , M680X_INS_SUB = 314 , M680X_INS_SUBA = 315 , M680X_INS_SUBB = 316 , M680X_INS_SUBD = 317 , M680X_INS_SUBE = 318 , M680X_INS_SUBF = 319 , M680X_INS_SUBR = 320 , M680X_INS_SUBW = 321 , M680X_INS_SWI = 322 , M680X_INS_SWI2 = 323 , M680X_INS_SWI3 = 324 , M680X_INS_SYNC = 325 , # [doc = "< M6800/1/2/3"] M680X_INS_TAB = 326 , # [doc = "< M6800/1/2/3"] M680X_INS_TAP = 327 , M680X_INS_TAX = 328 , # [doc = "< M6800/1/2/3"] M680X_INS_TBA = 329 , M680X_INS_TBEQ = 330 , M680X_INS_TBL = 331 , M680X_INS_TBNE = 332 , M680X_INS_TEST = 333 , M680X_INS_TFM = 334 , M680X_INS_TFR = 335 , M680X_INS_TIM = 336 , # [doc = "< M6800/1/2/3"] M680X_INS_TPA = 337 , M680X_INS_TST = 338 , M680X_INS_TSTA = 339 , M680X_INS_TSTB = 340 , M680X_INS_TSTD = 341 , M680X_INS_TSTE = 342 , M680X_INS_TSTF = 343 , M680X_INS_TSTW = 344 , M680X_INS_TSTX = 345 , # [doc = "< M6800/1/2/3"] M680X_INS_TSX = 346 , M680X_INS_TSY = 347 , M680X_INS_TXA = 348 , # [doc = "< M6800/1/2/3"] M680X_INS_TXS = 349 , M680X_INS_TYS = 350 , # [doc = "< M6800/1/2/3"] M680X_INS_WAI = 351 , M680X_INS_WAIT = 352 , M680X_INS_WAV = 353 , M680X_INS_WAVR = 354 , # [doc = "< HD6301"] M680X_INS_XGDX = 355 , M680X_INS_XGDY = 356 , M680X_INS_ENDING = 357 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_evm { # [doc = "< number of items popped from the stack"] pub pop : :: std :: os :: raw :: c_uchar , # [doc = "< number of items pushed into the stack"] pub push : :: std :: os :: raw :: c_uchar , # [doc = "< gas fee for the instruction"] pub fee : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_evm"] [:: std :: mem :: size_of :: < cs_evm > () - 8usize] ; ["Alignment of cs_evm"] [:: std :: mem :: align_of :: < cs_evm > () - 4usize] ; ["Offset of field: cs_evm::pop"] [:: std :: mem :: offset_of ! (cs_evm , pop) - 0usize] ; ["Offset of field: cs_evm::push"] [:: std :: mem :: offset_of ! (cs_evm , push) - 1usize] ; ["Offset of field: cs_evm::fee"] [:: std :: mem :: offset_of ! (cs_evm , fee) - 4usize] ; } ; # [repr (u32)] # [doc = " EVM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn { EVM_INS_STOP = 0 , EVM_INS_ADD = 1 , EVM_INS_MUL = 2 , EVM_INS_SUB = 3 , EVM_INS_DIV = 4 , EVM_INS_SDIV = 5 , EVM_INS_MOD = 6 , EVM_INS_SMOD = 7 , EVM_INS_ADDMOD = 8 , EVM_INS_MULMOD = 9 , EVM_INS_EXP = 10 , EVM_INS_SIGNEXTEND = 11 , EVM_INS_LT = 16 , EVM_INS_GT = 17 , EVM_INS_SLT = 18 , EVM_INS_SGT = 19 , EVM_INS_EQ = 20 , EVM_INS_ISZERO = 21 , EVM_INS_AND = 22 , EVM_INS_OR = 23 , EVM_INS_XOR = 24 , EVM_INS_NOT = 25 , EVM_INS_BYTE = 26 , EVM_INS_SHA3 = 32 , EVM_INS_ADDRESS = 48 , EVM_INS_BALANCE = 49 , EVM_INS_ORIGIN = 50 , EVM_INS_CALLER = 51 , EVM_INS_CALLVALUE = 52 , EVM_INS_CALLDATALOAD = 53 , EVM_INS_CALLDATASIZE = 54 , EVM_INS_CALLDATACOPY = 55 , EVM_INS_CODESIZE = 56 , EVM_INS_CODECOPY = 57 , EVM_INS_GASPRICE = 58 , EVM_INS_EXTCODESIZE = 59 , EVM_INS_EXTCODECOPY = 60 , EVM_INS_RETURNDATASIZE = 61 , EVM_INS_RETURNDATACOPY = 62 , EVM_INS_BLOCKHASH = 64 , EVM_INS_COINBASE = 65 , EVM_INS_TIMESTAMP = 66 , EVM_INS_NUMBER = 67 , EVM_INS_DIFFICULTY = 68 , EVM_INS_GASLIMIT = 69 , EVM_INS_POP = 80 , EVM_INS_MLOAD = 81 , EVM_INS_MSTORE = 82 , EVM_INS_MSTORE8 = 83 , EVM_INS_SLOAD = 84 , EVM_INS_SSTORE = 85 , EVM_INS_JUMP = 86 , EVM_INS_JUMPI = 87 , EVM_INS_PC = 88 , EVM_INS_MSIZE = 89 , EVM_INS_GAS = 90 , EVM_INS_JUMPDEST = 91 , EVM_INS_PUSH1 = 96 , EVM_INS_PUSH2 = 97 , EVM_INS_PUSH3 = 98 , EVM_INS_PUSH4 = 99 , EVM_INS_PUSH5 = 100 , EVM_INS_PUSH6 = 101 , EVM_INS_PUSH7 = 102 , EVM_INS_PUSH8 = 103 , EVM_INS_PUSH9 = 104 , EVM_INS_PUSH10 = 105 , EVM_INS_PUSH11 = 106 , EVM_INS_PUSH12 = 107 , EVM_INS_PUSH13 = 108 , EVM_INS_PUSH14 = 109 , EVM_INS_PUSH15 = 110 , EVM_INS_PUSH16 = 111 , EVM_INS_PUSH17 = 112 , EVM_INS_PUSH18 = 113 , EVM_INS_PUSH19 = 114 , EVM_INS_PUSH20 = 115 , EVM_INS_PUSH21 = 116 , EVM_INS_PUSH22 = 117 , EVM_INS_PUSH23 = 118 , EVM_INS_PUSH24 = 119 , EVM_INS_PUSH25 = 120 , EVM_INS_PUSH26 = 121 , EVM_INS_PUSH27 = 122 , EVM_INS_PUSH28 = 123 , EVM_INS_PUSH29 = 124 , EVM_INS_PUSH30 = 125 , EVM_INS_PUSH31 = 126 , EVM_INS_PUSH32 = 127 , EVM_INS_DUP1 = 128 , EVM_INS_DUP2 = 129 , EVM_INS_DUP3 = 130 , EVM_INS_DUP4 = 131 , EVM_INS_DUP5 = 132 , EVM_INS_DUP6 = 133 , EVM_INS_DUP7 = 134 , EVM_INS_DUP8 = 135 , EVM_INS_DUP9 = 136 , EVM_INS_DUP10 = 137 , EVM_INS_DUP11 = 138 , EVM_INS_DUP12 = 139 , EVM_INS_DUP13 = 140 , EVM_INS_DUP14 = 141 , EVM_INS_DUP15 = 142 , EVM_INS_DUP16 = 143 , EVM_INS_SWAP1 = 144 , EVM_INS_SWAP2 = 145 , EVM_INS_SWAP3 = 146 , EVM_INS_SWAP4 = 147 , EVM_INS_SWAP5 = 148 , EVM_INS_SWAP6 = 149 , EVM_INS_SWAP7 = 150 , EVM_INS_SWAP8 = 151 , EVM_INS_SWAP9 = 152 , EVM_INS_SWAP10 = 153 , EVM_INS_SWAP11 = 154 , EVM_INS_SWAP12 = 155 , EVM_INS_SWAP13 = 156 , EVM_INS_SWAP14 = 157 , EVM_INS_SWAP15 = 158 , EVM_INS_SWAP16 = 159 , EVM_INS_LOG0 = 160 , EVM_INS_LOG1 = 161 , EVM_INS_LOG2 = 162 , EVM_INS_LOG3 = 163 , EVM_INS_LOG4 = 164 , EVM_INS_CREATE = 240 , EVM_INS_CALL = 241 , EVM_INS_CALLCODE = 242 , EVM_INS_RETURN = 243 , EVM_INS_DELEGATECALL = 244 , EVM_INS_CALLBLACKBOX = 245 , EVM_INS_STATICCALL = 250 , EVM_INS_REVERT = 253 , EVM_INS_SUICIDE = 255 , EVM_INS_INVALID = 512 , EVM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of EVM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn_group { # [doc = "< = CS_GRP_INVALID"] EVM_GRP_INVALID = 0 , # [doc = "< all jump instructions"] EVM_GRP_JUMP = 1 , # [doc = "< math instructions"] EVM_GRP_MATH = 8 , # [doc = "< instructions write to stack"] EVM_GRP_STACK_WRITE = 9 , # [doc = "< instructions read from stack"] EVM_GRP_STACK_READ = 10 , # [doc = "< instructions write to memory"] EVM_GRP_MEM_WRITE = 11 , # [doc = "< instructions read from memory"] EVM_GRP_MEM_READ = 12 , # [doc = "< instructions write to storage"] EVM_GRP_STORE_WRITE = 13 , # [doc = "< instructions read from storage"] EVM_GRP_STORE_READ = 14 , # [doc = "< instructions halt execution"] EVM_GRP_HALT = 15 , # [doc = "< <-- mark the end of the list of groups"] EVM_GRP_ENDING = 16 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_op_type { RISCV_OP_INVALID = 0 , RISCV_OP_REG = 1 , RISCV_OP_IMM = 2 , RISCV_OP_MEM = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct riscv_op_mem { pub base : :: std :: os :: raw :: c_uint , pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of riscv_op_mem"] [:: std :: mem :: size_of :: < riscv_op_mem > () - 16usize] ; ["Alignment of riscv_op_mem"] [:: std :: mem :: align_of :: < riscv_op_mem > () - 8usize] ; ["Offset of field: riscv_op_mem::base"] [:: std :: mem :: offset_of ! (riscv_op_mem , base) - 0usize] ; ["Offset of field: riscv_op_mem::disp"] [:: std :: mem :: offset_of ! (riscv_op_mem , disp) - 8usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv_op { pub type_ : riscv_op_type , pub __bindgen_anon_1 : cs_riscv_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_riscv_op__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub imm : i64 , pub mem : riscv_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_riscv_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_riscv_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op"] [:: std :: mem :: size_of :: < cs_riscv_op > () - 24usize] ; ["Alignment of cs_riscv_op"] [:: std :: mem :: align_of :: < cs_riscv_op > () - 8usize] ; ["Offset of field: cs_riscv_op::type_"] [:: std :: mem :: offset_of ! (cs_riscv_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv { pub need_effective_addr : bool , pub op_count : u8 , pub operands : [cs_riscv_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv"] [:: std :: mem :: size_of :: < cs_riscv > () - 200usize] ; ["Alignment of cs_riscv"] [:: std :: mem :: align_of :: < cs_riscv > () - 8usize] ; ["Offset of field: cs_riscv::need_effective_addr"] [:: std :: mem :: offset_of ! (cs_riscv , need_effective_addr) - 0usize] ; ["Offset of field: cs_riscv::op_count"] [:: std :: mem :: offset_of ! (cs_riscv , op_count) - 1usize] ; ["Offset of field: cs_riscv::operands"] [:: std :: mem :: offset_of ! (cs_riscv , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}" , self . need_effective_addr , self . op_count , self . operands) } } impl riscv_reg { pub const RISCV_REG_ZERO : riscv_reg = riscv_reg :: RISCV_REG_X0 ; } impl riscv_reg { pub const RISCV_REG_RA : riscv_reg = riscv_reg :: RISCV_REG_X1 ; } impl riscv_reg { pub const RISCV_REG_SP : riscv_reg = riscv_reg :: RISCV_REG_X2 ; } impl riscv_reg { pub const RISCV_REG_GP : riscv_reg = riscv_reg :: RISCV_REG_X3 ; } impl riscv_reg { pub const RISCV_REG_TP : riscv_reg = riscv_reg :: RISCV_REG_X4 ; } impl riscv_reg { pub const RISCV_REG_T0 : riscv_reg = riscv_reg :: RISCV_REG_X5 ; } impl riscv_reg { pub const RISCV_REG_T1 : riscv_reg = riscv_reg :: RISCV_REG_X6 ; } impl riscv_reg { pub const RISCV_REG_T2 : riscv_reg = riscv_reg :: RISCV_REG_X7 ; } impl riscv_reg { pub const RISCV_REG_S0 : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_FP : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_S1 : riscv_reg = riscv_reg :: RISCV_REG_X9 ; } impl riscv_reg { pub const RISCV_REG_A0 : riscv_reg = riscv_reg :: RISCV_REG_X10 ; } impl riscv_reg { pub const RISCV_REG_A1 : riscv_reg = riscv_reg :: RISCV_REG_X11 ; } impl riscv_reg { pub const RISCV_REG_A2 : riscv_reg = riscv_reg :: RISCV_REG_X12 ; } impl riscv_reg { pub const RISCV_REG_A3 : riscv_reg = riscv_reg :: RISCV_REG_X13 ; } impl riscv_reg { pub const RISCV_REG_A4 : riscv_reg = riscv_reg :: RISCV_REG_X14 ; } impl riscv_reg { pub const RISCV_REG_A5 : riscv_reg = riscv_reg :: RISCV_REG_X15 ; } impl riscv_reg { pub const RISCV_REG_A6 : riscv_reg = riscv_reg :: RISCV_REG_X16 ; } impl riscv_reg { pub const RISCV_REG_A7 : riscv_reg = riscv_reg :: RISCV_REG_X17 ; } impl riscv_reg { pub const RISCV_REG_S2 : riscv_reg = riscv_reg :: RISCV_REG_X18 ; } impl riscv_reg { pub const RISCV_REG_S3 : riscv_reg = riscv_reg :: RISCV_REG_X19 ; } impl riscv_reg { pub const RISCV_REG_S4 : riscv_reg = riscv_reg :: RISCV_REG_X20 ; } impl riscv_reg { pub const RISCV_REG_S5 : riscv_reg = riscv_reg :: RISCV_REG_X21 ; } impl riscv_reg { pub const RISCV_REG_S6 : riscv_reg = riscv_reg :: RISCV_REG_X22 ; } impl riscv_reg { pub const RISCV_REG_S7 : riscv_reg = riscv_reg :: RISCV_REG_X23 ; } impl riscv_reg { pub const RISCV_REG_S8 : riscv_reg = riscv_reg :: RISCV_REG_X24 ; } impl riscv_reg { pub const RISCV_REG_S9 : riscv_reg = riscv_reg :: RISCV_REG_X25 ; } impl riscv_reg { pub const RISCV_REG_S10 : riscv_reg = riscv_reg :: RISCV_REG_X26 ; } impl riscv_reg { pub const RISCV_REG_S11 : riscv_reg = riscv_reg :: RISCV_REG_X27 ; } impl riscv_reg { pub const RISCV_REG_T3 : riscv_reg = riscv_reg :: RISCV_REG_X28 ; } impl riscv_reg { pub const RISCV_REG_T4 : riscv_reg = riscv_reg :: RISCV_REG_X29 ; } impl riscv_reg { pub const RISCV_REG_T5 : riscv_reg = riscv_reg :: RISCV_REG_X30 ; } impl riscv_reg { pub const RISCV_REG_T6 : riscv_reg = riscv_reg :: RISCV_REG_X31 ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_reg { RISCV_REG_INVALID = 0 , RISCV_REG_X0 = 1 , RISCV_REG_X1 = 2 , RISCV_REG_X2 = 3 , RISCV_REG_X3 = 4 , RISCV_REG_X4 = 5 , RISCV_REG_X5 = 6 , RISCV_REG_X6 = 7 , RISCV_REG_X7 = 8 , RISCV_REG_X8 = 9 , RISCV_REG_X9 = 10 , RISCV_REG_X10 = 11 , RISCV_REG_X11 = 12 , RISCV_REG_X12 = 13 , RISCV_REG_X13 = 14 , RISCV_REG_X14 = 15 , RISCV_REG_X15 = 16 , RISCV_REG_X16 = 17 , RISCV_REG_X17 = 18 , RISCV_REG_X18 = 19 , RISCV_REG_X19 = 20 , RISCV_REG_X20 = 21 , RISCV_REG_X21 = 22 , RISCV_REG_X22 = 23 , RISCV_REG_X23 = 24 , RISCV_REG_X24 = 25 , RISCV_REG_X25 = 26 , RISCV_REG_X26 = 27 , RISCV_REG_X27 = 28 , RISCV_REG_X28 = 29 , RISCV_REG_X29 = 30 , RISCV_REG_X30 = 31 , RISCV_REG_X31 = 32 , RISCV_REG_F0_32 = 33 , RISCV_REG_F0_64 = 34 , RISCV_REG_F1_32 = 35 , RISCV_REG_F1_64 = 36 , RISCV_REG_F2_32 = 37 , RISCV_REG_F2_64 = 38 , RISCV_REG_F3_32 = 39 , RISCV_REG_F3_64 = 40 , RISCV_REG_F4_32 = 41 , RISCV_REG_F4_64 = 42 , RISCV_REG_F5_32 = 43 , RISCV_REG_F5_64 = 44 , RISCV_REG_F6_32 = 45 , RISCV_REG_F6_64 = 46 , RISCV_REG_F7_32 = 47 , RISCV_REG_F7_64 = 48 , RISCV_REG_F8_32 = 49 , RISCV_REG_F8_64 = 50 , RISCV_REG_F9_32 = 51 , RISCV_REG_F9_64 = 52 , RISCV_REG_F10_32 = 53 , RISCV_REG_F10_64 = 54 , RISCV_REG_F11_32 = 55 , RISCV_REG_F11_64 = 56 , RISCV_REG_F12_32 = 57 , RISCV_REG_F12_64 = 58 , RISCV_REG_F13_32 = 59 , RISCV_REG_F13_64 = 60 , RISCV_REG_F14_32 = 61 , RISCV_REG_F14_64 = 62 , RISCV_REG_F15_32 = 63 , RISCV_REG_F15_64 = 64 , RISCV_REG_F16_32 = 65 , RISCV_REG_F16_64 = 66 , RISCV_REG_F17_32 = 67 , RISCV_REG_F17_64 = 68 , RISCV_REG_F18_32 = 69 , RISCV_REG_F18_64 = 70 , RISCV_REG_F19_32 = 71 , RISCV_REG_F19_64 = 72 , RISCV_REG_F20_32 = 73 , RISCV_REG_F20_64 = 74 , RISCV_REG_F21_32 = 75 , RISCV_REG_F21_64 = 76 , RISCV_REG_F22_32 = 77 , RISCV_REG_F22_64 = 78 , RISCV_REG_F23_32 = 79 , RISCV_REG_F23_64 = 80 , RISCV_REG_F24_32 = 81 , RISCV_REG_F24_64 = 82 , RISCV_REG_F25_32 = 83 , RISCV_REG_F25_64 = 84 , RISCV_REG_F26_32 = 85 , RISCV_REG_F26_64 = 86 , RISCV_REG_F27_32 = 87 , RISCV_REG_F27_64 = 88 , RISCV_REG_F28_32 = 89 , RISCV_REG_F28_64 = 90 , RISCV_REG_F29_32 = 91 , RISCV_REG_F29_64 = 92 , RISCV_REG_F30_32 = 93 , RISCV_REG_F30_64 = 94 , RISCV_REG_F31_32 = 95 , RISCV_REG_F31_64 = 96 , RISCV_REG_ENDING = 97 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn { RISCV_INS_INVALID = 0 , RISCV_INS_ADD = 1 , RISCV_INS_ADDI = 2 , RISCV_INS_ADDIW = 3 , RISCV_INS_ADDW = 4 , RISCV_INS_AMOADD_D = 5 , RISCV_INS_AMOADD_D_AQ = 6 , RISCV_INS_AMOADD_D_AQ_RL = 7 , RISCV_INS_AMOADD_D_RL = 8 , RISCV_INS_AMOADD_W = 9 , RISCV_INS_AMOADD_W_AQ = 10 , RISCV_INS_AMOADD_W_AQ_RL = 11 , RISCV_INS_AMOADD_W_RL = 12 , RISCV_INS_AMOAND_D = 13 , RISCV_INS_AMOAND_D_AQ = 14 , RISCV_INS_AMOAND_D_AQ_RL = 15 , RISCV_INS_AMOAND_D_RL = 16 , RISCV_INS_AMOAND_W = 17 , RISCV_INS_AMOAND_W_AQ = 18 , RISCV_INS_AMOAND_W_AQ_RL = 19 , RISCV_INS_AMOAND_W_RL = 20 , RISCV_INS_AMOMAXU_D = 21 , RISCV_INS_AMOMAXU_D_AQ = 22 , RISCV_INS_AMOMAXU_D_AQ_RL = 23 , RISCV_INS_AMOMAXU_D_RL = 24 , RISCV_INS_AMOMAXU_W = 25 , RISCV_INS_AMOMAXU_W_AQ = 26 , RISCV_INS_AMOMAXU_W_AQ_RL = 27 , RISCV_INS_AMOMAXU_W_RL = 28 , RISCV_INS_AMOMAX_D = 29 , RISCV_INS_AMOMAX_D_AQ = 30 , RISCV_INS_AMOMAX_D_AQ_RL = 31 , RISCV_INS_AMOMAX_D_RL = 32 , RISCV_INS_AMOMAX_W = 33 , RISCV_INS_AMOMAX_W_AQ = 34 , RISCV_INS_AMOMAX_W_AQ_RL = 35 , RISCV_INS_AMOMAX_W_RL = 36 , RISCV_INS_AMOMINU_D = 37 , RISCV_INS_AMOMINU_D_AQ = 38 , RISCV_INS_AMOMINU_D_AQ_RL = 39 , RISCV_INS_AMOMINU_D_RL = 40 , RISCV_INS_AMOMINU_W = 41 , RISCV_INS_AMOMINU_W_AQ = 42 , RISCV_INS_AMOMINU_W_AQ_RL = 43 , RISCV_INS_AMOMINU_W_RL = 44 , RISCV_INS_AMOMIN_D = 45 , RISCV_INS_AMOMIN_D_AQ = 46 , RISCV_INS_AMOMIN_D_AQ_RL = 47 , RISCV_INS_AMOMIN_D_RL = 48 , RISCV_INS_AMOMIN_W = 49 , RISCV_INS_AMOMIN_W_AQ = 50 , RISCV_INS_AMOMIN_W_AQ_RL = 51 , RISCV_INS_AMOMIN_W_RL = 52 , RISCV_INS_AMOOR_D = 53 , RISCV_INS_AMOOR_D_AQ = 54 , RISCV_INS_AMOOR_D_AQ_RL = 55 , RISCV_INS_AMOOR_D_RL = 56 , RISCV_INS_AMOOR_W = 57 , RISCV_INS_AMOOR_W_AQ = 58 , RISCV_INS_AMOOR_W_AQ_RL = 59 , RISCV_INS_AMOOR_W_RL = 60 , RISCV_INS_AMOSWAP_D = 61 , RISCV_INS_AMOSWAP_D_AQ = 62 , RISCV_INS_AMOSWAP_D_AQ_RL = 63 , RISCV_INS_AMOSWAP_D_RL = 64 , RISCV_INS_AMOSWAP_W = 65 , RISCV_INS_AMOSWAP_W_AQ = 66 , RISCV_INS_AMOSWAP_W_AQ_RL = 67 , RISCV_INS_AMOSWAP_W_RL = 68 , RISCV_INS_AMOXOR_D = 69 , RISCV_INS_AMOXOR_D_AQ = 70 , RISCV_INS_AMOXOR_D_AQ_RL = 71 , RISCV_INS_AMOXOR_D_RL = 72 , RISCV_INS_AMOXOR_W = 73 , RISCV_INS_AMOXOR_W_AQ = 74 , RISCV_INS_AMOXOR_W_AQ_RL = 75 , RISCV_INS_AMOXOR_W_RL = 76 , RISCV_INS_AND = 77 , RISCV_INS_ANDI = 78 , RISCV_INS_AUIPC = 79 , RISCV_INS_BEQ = 80 , RISCV_INS_BGE = 81 , RISCV_INS_BGEU = 82 , RISCV_INS_BLT = 83 , RISCV_INS_BLTU = 84 , RISCV_INS_BNE = 85 , RISCV_INS_CSRRC = 86 , RISCV_INS_CSRRCI = 87 , RISCV_INS_CSRRS = 88 , RISCV_INS_CSRRSI = 89 , RISCV_INS_CSRRW = 90 , RISCV_INS_CSRRWI = 91 , RISCV_INS_C_ADD = 92 , RISCV_INS_C_ADDI = 93 , RISCV_INS_C_ADDI16SP = 94 , RISCV_INS_C_ADDI4SPN = 95 , RISCV_INS_C_ADDIW = 96 , RISCV_INS_C_ADDW = 97 , RISCV_INS_C_AND = 98 , RISCV_INS_C_ANDI = 99 , RISCV_INS_C_BEQZ = 100 , RISCV_INS_C_BNEZ = 101 , RISCV_INS_C_EBREAK = 102 , RISCV_INS_C_FLD = 103 , RISCV_INS_C_FLDSP = 104 , RISCV_INS_C_FLW = 105 , RISCV_INS_C_FLWSP = 106 , RISCV_INS_C_FSD = 107 , RISCV_INS_C_FSDSP = 108 , RISCV_INS_C_FSW = 109 , RISCV_INS_C_FSWSP = 110 , RISCV_INS_C_J = 111 , RISCV_INS_C_JAL = 112 , RISCV_INS_C_JALR = 113 , RISCV_INS_C_JR = 114 , RISCV_INS_C_LD = 115 , RISCV_INS_C_LDSP = 116 , RISCV_INS_C_LI = 117 , RISCV_INS_C_LUI = 118 , RISCV_INS_C_LW = 119 , RISCV_INS_C_LWSP = 120 , RISCV_INS_C_MV = 121 , RISCV_INS_C_NOP = 122 , RISCV_INS_C_OR = 123 , RISCV_INS_C_SD = 124 , RISCV_INS_C_SDSP = 125 , RISCV_INS_C_SLLI = 126 , RISCV_INS_C_SRAI = 127 , RISCV_INS_C_SRLI = 128 , RISCV_INS_C_SUB = 129 , RISCV_INS_C_SUBW = 130 , RISCV_INS_C_SW = 131 , RISCV_INS_C_SWSP = 132 , RISCV_INS_C_UNIMP = 133 , RISCV_INS_C_XOR = 134 , RISCV_INS_DIV = 135 , RISCV_INS_DIVU = 136 , RISCV_INS_DIVUW = 137 , RISCV_INS_DIVW = 138 , RISCV_INS_EBREAK = 139 , RISCV_INS_ECALL = 140 , RISCV_INS_FADD_D = 141 , RISCV_INS_FADD_S = 142 , RISCV_INS_FCLASS_D = 143 , RISCV_INS_FCLASS_S = 144 , RISCV_INS_FCVT_D_L = 145 , RISCV_INS_FCVT_D_LU = 146 , RISCV_INS_FCVT_D_S = 147 , RISCV_INS_FCVT_D_W = 148 , RISCV_INS_FCVT_D_WU = 149 , RISCV_INS_FCVT_LU_D = 150 , RISCV_INS_FCVT_LU_S = 151 , RISCV_INS_FCVT_L_D = 152 , RISCV_INS_FCVT_L_S = 153 , RISCV_INS_FCVT_S_D = 154 , RISCV_INS_FCVT_S_L = 155 , RISCV_INS_FCVT_S_LU = 156 , RISCV_INS_FCVT_S_W = 157 , RISCV_INS_FCVT_S_WU = 158 , RISCV_INS_FCVT_WU_D = 159 , RISCV_INS_FCVT_WU_S = 160 , RISCV_INS_FCVT_W_D = 161 , RISCV_INS_FCVT_W_S = 162 , RISCV_INS_FDIV_D = 163 , RISCV_INS_FDIV_S = 164 , RISCV_INS_FENCE = 165 , RISCV_INS_FENCE_I = 166 , RISCV_INS_FENCE_TSO = 167 , RISCV_INS_FEQ_D = 168 , RISCV_INS_FEQ_S = 169 , RISCV_INS_FLD = 170 , RISCV_INS_FLE_D = 171 , RISCV_INS_FLE_S = 172 , RISCV_INS_FLT_D = 173 , RISCV_INS_FLT_S = 174 , RISCV_INS_FLW = 175 , RISCV_INS_FMADD_D = 176 , RISCV_INS_FMADD_S = 177 , RISCV_INS_FMAX_D = 178 , RISCV_INS_FMAX_S = 179 , RISCV_INS_FMIN_D = 180 , RISCV_INS_FMIN_S = 181 , RISCV_INS_FMSUB_D = 182 , RISCV_INS_FMSUB_S = 183 , RISCV_INS_FMUL_D = 184 , RISCV_INS_FMUL_S = 185 , RISCV_INS_FMV_D_X = 186 , RISCV_INS_FMV_W_X = 187 , RISCV_INS_FMV_X_D = 188 , RISCV_INS_FMV_X_W = 189 , RISCV_INS_FNMADD_D = 190 , RISCV_INS_FNMADD_S = 191 , RISCV_INS_FNMSUB_D = 192 , RISCV_INS_FNMSUB_S = 193 , RISCV_INS_FSD = 194 , RISCV_INS_FSGNJN_D = 195 , RISCV_INS_FSGNJN_S = 196 , RISCV_INS_FSGNJX_D = 197 , RISCV_INS_FSGNJX_S = 198 , RISCV_INS_FSGNJ_D = 199 , RISCV_INS_FSGNJ_S = 200 , RISCV_INS_FSQRT_D = 201 , RISCV_INS_FSQRT_S = 202 , RISCV_INS_FSUB_D = 203 , RISCV_INS_FSUB_S = 204 , RISCV_INS_FSW = 205 , RISCV_INS_JAL = 206 , RISCV_INS_JALR = 207 , RISCV_INS_LB = 208 , RISCV_INS_LBU = 209 , RISCV_INS_LD = 210 , RISCV_INS_LH = 211 , RISCV_INS_LHU = 212 , RISCV_INS_LR_D = 213 , RISCV_INS_LR_D_AQ = 214 , RISCV_INS_LR_D_AQ_RL = 215 , RISCV_INS_LR_D_RL = 216 , RISCV_INS_LR_W = 217 , RISCV_INS_LR_W_AQ = 218 , RISCV_INS_LR_W_AQ_RL = 219 , RISCV_INS_LR_W_RL = 220 , RISCV_INS_LUI = 221 , RISCV_INS_LW = 222 , RISCV_INS_LWU = 223 , RISCV_INS_MRET = 224 , RISCV_INS_MUL = 225 , RISCV_INS_MULH = 226 , RISCV_INS_MULHSU = 227 , RISCV_INS_MULHU = 228 , RISCV_INS_MULW = 229 , RISCV_INS_OR = 230 , RISCV_INS_ORI = 231 , RISCV_INS_REM = 232 , RISCV_INS_REMU = 233 , RISCV_INS_REMUW = 234 , RISCV_INS_REMW = 235 , RISCV_INS_SB = 236 , RISCV_INS_SC_D = 237 , RISCV_INS_SC_D_AQ = 238 , RISCV_INS_SC_D_AQ_RL = 239 , RISCV_INS_SC_D_RL = 240 , RISCV_INS_SC_W = 241 , RISCV_INS_SC_W_AQ = 242 , RISCV_INS_SC_W_AQ_RL = 243 , RISCV_INS_SC_W_RL = 244 , RISCV_INS_SD = 245 , RISCV_INS_SFENCE_VMA = 246 , RISCV_INS_SH = 247 , RISCV_INS_SLL = 248 , RISCV_INS_SLLI = 249 , RISCV_INS_SLLIW = 250 , RISCV_INS_SLLW = 251 , RISCV_INS_SLT = 252 , RISCV_INS_SLTI = 253 , RISCV_INS_SLTIU = 254 , RISCV_INS_SLTU = 255 , RISCV_INS_SRA = 256 , RISCV_INS_SRAI = 257 , RISCV_INS_SRAIW = 258 , RISCV_INS_SRAW = 259 , RISCV_INS_SRET = 260 , RISCV_INS_SRL = 261 , RISCV_INS_SRLI = 262 , RISCV_INS_SRLIW = 263 , RISCV_INS_SRLW = 264 , RISCV_INS_SUB = 265 , RISCV_INS_SUBW = 266 , RISCV_INS_SW = 267 , RISCV_INS_UNIMP = 268 , RISCV_INS_URET = 269 , RISCV_INS_WFI = 270 , RISCV_INS_XOR = 271 , RISCV_INS_XORI = 272 , RISCV_INS_ENDING = 273 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn_group { # [doc = "< = CS_GRP_INVALID"] RISCV_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] RISCV_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] RISCV_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] RISCV_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] RISCV_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] RISCV_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] RISCV_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] RISCV_GRP_BRANCH_RELATIVE = 7 , RISCV_GRP_ISRV32 = 128 , RISCV_GRP_ISRV64 = 129 , RISCV_GRP_HASSTDEXTA = 130 , RISCV_GRP_HASSTDEXTC = 131 , RISCV_GRP_HASSTDEXTD = 132 , RISCV_GRP_HASSTDEXTF = 133 , RISCV_GRP_HASSTDEXTM = 134 , RISCV_GRP_ENDING = 135 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_op_type { WASM_OP_INVALID = 0 , WASM_OP_NONE = 1 , WASM_OP_INT7 = 2 , WASM_OP_VARUINT32 = 3 , WASM_OP_VARUINT64 = 4 , WASM_OP_UINT32 = 5 , WASM_OP_UINT64 = 6 , WASM_OP_IMM = 7 , WASM_OP_BRTABLE = 8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_wasm_brtable { pub length : u32 , pub address : u64 , pub default_target : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_brtable"] [:: std :: mem :: size_of :: < cs_wasm_brtable > () - 24usize] ; ["Alignment of cs_wasm_brtable"] [:: std :: mem :: align_of :: < cs_wasm_brtable > () - 8usize] ; ["Offset of field: cs_wasm_brtable::length"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , length) - 0usize] ; ["Offset of field: cs_wasm_brtable::address"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , address) - 8usize] ; ["Offset of field: cs_wasm_brtable::default_target"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , default_target) - 16usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm_op { pub type_ : wasm_op_type , pub size : u32 , pub __bindgen_anon_1 : cs_wasm_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_wasm_op__bindgen_ty_1 { pub int7 : i8 , pub varuint32 : u32 , pub varuint64 : u64 , pub uint32 : u32 , pub uint64 : u64 , pub immediate : [u32 ; 2usize] , pub brtable : cs_wasm_brtable , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_wasm_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_wasm_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::int7"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , int7) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::immediate"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , immediate) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::brtable"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , brtable) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op"] [:: std :: mem :: size_of :: < cs_wasm_op > () - 32usize] ; ["Alignment of cs_wasm_op"] [:: std :: mem :: align_of :: < cs_wasm_op > () - 8usize] ; ["Offset of field: cs_wasm_op::type_"] [:: std :: mem :: offset_of ! (cs_wasm_op , type_) - 0usize] ; ["Offset of field: cs_wasm_op::size"] [:: std :: mem :: offset_of ! (cs_wasm_op , size) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . size , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm { pub op_count : u8 , pub operands : [cs_wasm_op ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm"] [:: std :: mem :: size_of :: < cs_wasm > () - 72usize] ; ["Alignment of cs_wasm"] [:: std :: mem :: align_of :: < cs_wasm > () - 8usize] ; ["Offset of field: cs_wasm::op_count"] [:: std :: mem :: offset_of ! (cs_wasm , op_count) - 0usize] ; ["Offset of field: cs_wasm::operands"] [:: std :: mem :: offset_of ! (cs_wasm , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " WASM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn { WASM_INS_UNREACHABLE = 0 , WASM_INS_NOP = 1 , WASM_INS_BLOCK = 2 , WASM_INS_LOOP = 3 , WASM_INS_IF = 4 , WASM_INS_ELSE = 5 , WASM_INS_END = 11 , WASM_INS_BR = 12 , WASM_INS_BR_IF = 13 , WASM_INS_BR_TABLE = 14 , WASM_INS_RETURN = 15 , WASM_INS_CALL = 16 , WASM_INS_CALL_INDIRECT = 17 , WASM_INS_DROP = 26 , WASM_INS_SELECT = 27 , WASM_INS_GET_LOCAL = 32 , WASM_INS_SET_LOCAL = 33 , WASM_INS_TEE_LOCAL = 34 , WASM_INS_GET_GLOBAL = 35 , WASM_INS_SET_GLOBAL = 36 , WASM_INS_I32_LOAD = 40 , WASM_INS_I64_LOAD = 41 , WASM_INS_F32_LOAD = 42 , WASM_INS_F64_LOAD = 43 , WASM_INS_I32_LOAD8_S = 44 , WASM_INS_I32_LOAD8_U = 45 , WASM_INS_I32_LOAD16_S = 46 , WASM_INS_I32_LOAD16_U = 47 , WASM_INS_I64_LOAD8_S = 48 , WASM_INS_I64_LOAD8_U = 49 , WASM_INS_I64_LOAD16_S = 50 , WASM_INS_I64_LOAD16_U = 51 , WASM_INS_I64_LOAD32_S = 52 , WASM_INS_I64_LOAD32_U = 53 , WASM_INS_I32_STORE = 54 , WASM_INS_I64_STORE = 55 , WASM_INS_F32_STORE = 56 , WASM_INS_F64_STORE = 57 , WASM_INS_I32_STORE8 = 58 , WASM_INS_I32_STORE16 = 59 , WASM_INS_I64_STORE8 = 60 , WASM_INS_I64_STORE16 = 61 , WASM_INS_I64_STORE32 = 62 , WASM_INS_CURRENT_MEMORY = 63 , WASM_INS_GROW_MEMORY = 64 , WASM_INS_I32_CONST = 65 , WASM_INS_I64_CONST = 66 , WASM_INS_F32_CONST = 67 , WASM_INS_F64_CONST = 68 , WASM_INS_I32_EQZ = 69 , WASM_INS_I32_EQ = 70 , WASM_INS_I32_NE = 71 , WASM_INS_I32_LT_S = 72 , WASM_INS_I32_LT_U = 73 , WASM_INS_I32_GT_S = 74 , WASM_INS_I32_GT_U = 75 , WASM_INS_I32_LE_S = 76 , WASM_INS_I32_LE_U = 77 , WASM_INS_I32_GE_S = 78 , WASM_INS_I32_GE_U = 79 , WASM_INS_I64_EQZ = 80 , WASM_INS_I64_EQ = 81 , WASM_INS_I64_NE = 82 , WASM_INS_I64_LT_S = 83 , WASM_INS_I64_LT_U = 84 , WASN_INS_I64_GT_S = 85 , WASM_INS_I64_GT_U = 86 , WASM_INS_I64_LE_S = 87 , WASM_INS_I64_LE_U = 88 , WASM_INS_I64_GE_S = 89 , WASM_INS_I64_GE_U = 90 , WASM_INS_F32_EQ = 91 , WASM_INS_F32_NE = 92 , WASM_INS_F32_LT = 93 , WASM_INS_F32_GT = 94 , WASM_INS_F32_LE = 95 , WASM_INS_F32_GE = 96 , WASM_INS_F64_EQ = 97 , WASM_INS_F64_NE = 98 , WASM_INS_F64_LT = 99 , WASM_INS_F64_GT = 100 , WASM_INS_F64_LE = 101 , WASM_INS_F64_GE = 102 , WASM_INS_I32_CLZ = 103 , WASM_INS_I32_CTZ = 104 , WASM_INS_I32_POPCNT = 105 , WASM_INS_I32_ADD = 106 , WASM_INS_I32_SUB = 107 , WASM_INS_I32_MUL = 108 , WASM_INS_I32_DIV_S = 109 , WASM_INS_I32_DIV_U = 110 , WASM_INS_I32_REM_S = 111 , WASM_INS_I32_REM_U = 112 , WASM_INS_I32_AND = 113 , WASM_INS_I32_OR = 114 , WASM_INS_I32_XOR = 115 , WASM_INS_I32_SHL = 116 , WASM_INS_I32_SHR_S = 117 , WASM_INS_I32_SHR_U = 118 , WASM_INS_I32_ROTL = 119 , WASM_INS_I32_ROTR = 120 , WASM_INS_I64_CLZ = 121 , WASM_INS_I64_CTZ = 122 , WASM_INS_I64_POPCNT = 123 , WASM_INS_I64_ADD = 124 , WASM_INS_I64_SUB = 125 , WASM_INS_I64_MUL = 126 , WASM_INS_I64_DIV_S = 127 , WASM_INS_I64_DIV_U = 128 , WASM_INS_I64_REM_S = 129 , WASM_INS_I64_REM_U = 130 , WASM_INS_I64_AND = 131 , WASM_INS_I64_OR = 132 , WASM_INS_I64_XOR = 133 , WASM_INS_I64_SHL = 134 , WASM_INS_I64_SHR_S = 135 , WASM_INS_I64_SHR_U = 136 , WASM_INS_I64_ROTL = 137 , WASM_INS_I64_ROTR = 138 , WASM_INS_F32_ABS = 139 , WASM_INS_F32_NEG = 140 , WASM_INS_F32_CEIL = 141 , WASM_INS_F32_FLOOR = 142 , WASM_INS_F32_TRUNC = 143 , WASM_INS_F32_NEAREST = 144 , WASM_INS_F32_SQRT = 145 , WASM_INS_F32_ADD = 146 , WASM_INS_F32_SUB = 147 , WASM_INS_F32_MUL = 148 , WASM_INS_F32_DIV = 149 , WASM_INS_F32_MIN = 150 , WASM_INS_F32_MAX = 151 , WASM_INS_F32_COPYSIGN = 152 , WASM_INS_F64_ABS = 153 , WASM_INS_F64_NEG = 154 , WASM_INS_F64_CEIL = 155 , WASM_INS_F64_FLOOR = 156 , WASM_INS_F64_TRUNC = 157 , WASM_INS_F64_NEAREST = 158 , WASM_INS_F64_SQRT = 159 , WASM_INS_F64_ADD = 160 , WASM_INS_F64_SUB = 161 , WASM_INS_F64_MUL = 162 , WASM_INS_F64_DIV = 163 , WASM_INS_F64_MIN = 164 , WASM_INS_F64_MAX = 165 , WASM_INS_F64_COPYSIGN = 166 , WASM_INS_I32_WARP_I64 = 167 , WASP_INS_I32_TRUNC_S_F32 = 168 , WASM_INS_I32_TRUNC_U_F32 = 169 , WASM_INS_I32_TRUNC_S_F64 = 170 , WASM_INS_I32_TRUNC_U_F64 = 171 , WASM_INS_I64_EXTEND_S_I32 = 172 , WASM_INS_I64_EXTEND_U_I32 = 173 , WASM_INS_I64_TRUNC_S_F32 = 174 , WASM_INS_I64_TRUNC_U_F32 = 175 , WASM_INS_I64_TRUNC_S_F64 = 176 , WASM_INS_I64_TRUNC_U_F64 = 177 , WASM_INS_F32_CONVERT_S_I32 = 178 , WASM_INS_F32_CONVERT_U_I32 = 179 , WASM_INS_F32_CONVERT_S_I64 = 180 , WASM_INS_F32_CONVERT_U_I64 = 181 , WASM_INS_F32_DEMOTE_F64 = 182 , WASM_INS_F64_CONVERT_S_I32 = 183 , WASM_INS_F64_CONVERT_U_I32 = 184 , WASM_INS_F64_CONVERT_S_I64 = 185 , WASM_INS_F64_CONVERT_U_I64 = 186 , WASM_INS_F64_PROMOTE_F32 = 187 , WASM_INS_I32_REINTERPRET_F32 = 188 , WASM_INS_I64_REINTERPRET_F64 = 189 , WASM_INS_F32_REINTERPRET_I32 = 190 , WASM_INS_F64_REINTERPRET_I64 = 191 , WASM_INS_INVALID = 512 , WASM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of WASM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn_group { # [doc = "< = CS_GRP_INVALID"] WASM_GRP_INVALID = 0 , WASM_GRP_NUMBERIC = 8 , WASM_GRP_PARAMETRIC = 9 , WASM_GRP_VARIABLE = 10 , WASM_GRP_MEMORY = 11 , WASM_GRP_CONTROL = 12 , # [doc = "< <-- mark the end of the list of groups"] WASM_GRP_ENDING = 13 , } # [repr (u32)] # [doc = " MOS65XX registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_reg { MOS65XX_REG_INVALID = 0 , # [doc = "< accumulator"] MOS65XX_REG_ACC = 1 , # [doc = "< X index register"] MOS65XX_REG_X = 2 , # [doc = "< Y index register"] MOS65XX_REG_Y = 3 , # [doc = "< status register"] MOS65XX_REG_P = 4 , # [doc = "< stack pointer register"] MOS65XX_REG_SP = 5 , # [doc = "< direct page register"] MOS65XX_REG_DP = 6 , # [doc = "< data bank register"] MOS65XX_REG_B = 7 , # [doc = "< program bank register"] MOS65XX_REG_K = 8 , MOS65XX_REG_ENDING = 9 , } # [repr (u32)] # [doc = " MOS65XX Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_address_mode { # [doc = "< No address mode."] MOS65XX_AM_NONE = 0 , # [doc = "< implied addressing (no addressing mode)"] MOS65XX_AM_IMP = 1 , # [doc = "< accumulator addressing"] MOS65XX_AM_ACC = 2 , # [doc = "< 8/16 Bit immediate value"] MOS65XX_AM_IMM = 3 , # [doc = "< relative addressing used by branches"] MOS65XX_AM_REL = 4 , # [doc = "< interrupt addressing"] MOS65XX_AM_INT = 5 , # [doc = "< memory block addressing"] MOS65XX_AM_BLOCK = 6 , # [doc = "< zeropage addressing"] MOS65XX_AM_ZP = 7 , # [doc = "< indexed zeropage addressing by the X index register"] MOS65XX_AM_ZP_X = 8 , # [doc = "< indexed zeropage addressing by the Y index register"] MOS65XX_AM_ZP_Y = 9 , # [doc = "< zero page address, branch relative address"] MOS65XX_AM_ZP_REL = 10 , # [doc = "< indirect zeropage addressing"] MOS65XX_AM_ZP_IND = 11 , # [doc = "< indexed zeropage indirect addressing by the X index register"] MOS65XX_AM_ZP_X_IND = 12 , # [doc = "< indirect zeropage indexed addressing by the Y index register"] MOS65XX_AM_ZP_IND_Y = 13 , # [doc = "< zeropage indirect long addressing"] MOS65XX_AM_ZP_IND_LONG = 14 , # [doc = "< zeropage indirect long addressing indexed by Y register"] MOS65XX_AM_ZP_IND_LONG_Y = 15 , # [doc = "< absolute addressing"] MOS65XX_AM_ABS = 16 , # [doc = "< indexed absolute addressing by the X index register"] MOS65XX_AM_ABS_X = 17 , # [doc = "< indexed absolute addressing by the Y index register"] MOS65XX_AM_ABS_Y = 18 , # [doc = "< absolute indirect addressing"] MOS65XX_AM_ABS_IND = 19 , # [doc = "< indexed absolute indirect addressing by the X index register"] MOS65XX_AM_ABS_X_IND = 20 , # [doc = "< absolute indirect long addressing"] MOS65XX_AM_ABS_IND_LONG = 21 , # [doc = "< absolute long address mode"] MOS65XX_AM_ABS_LONG = 22 , # [doc = "< absolute long address mode, indexed by X register"] MOS65XX_AM_ABS_LONG_X = 23 , # [doc = "< stack relative addressing"] MOS65XX_AM_SR = 24 , # [doc = "< indirect stack relative addressing indexed by the Y index register"] MOS65XX_AM_SR_IND_Y = 25 , } # [repr (u32)] # [doc = " MOS65XX instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_insn { MOS65XX_INS_INVALID = 0 , MOS65XX_INS_ADC = 1 , MOS65XX_INS_AND = 2 , MOS65XX_INS_ASL = 3 , MOS65XX_INS_BBR = 4 , MOS65XX_INS_BBS = 5 , MOS65XX_INS_BCC = 6 , MOS65XX_INS_BCS = 7 , MOS65XX_INS_BEQ = 8 , MOS65XX_INS_BIT = 9 , MOS65XX_INS_BMI = 10 , MOS65XX_INS_BNE = 11 , MOS65XX_INS_BPL = 12 , MOS65XX_INS_BRA = 13 , MOS65XX_INS_BRK = 14 , MOS65XX_INS_BRL = 15 , MOS65XX_INS_BVC = 16 , MOS65XX_INS_BVS = 17 , MOS65XX_INS_CLC = 18 , MOS65XX_INS_CLD = 19 , MOS65XX_INS_CLI = 20 , MOS65XX_INS_CLV = 21 , MOS65XX_INS_CMP = 22 , MOS65XX_INS_COP = 23 , MOS65XX_INS_CPX = 24 , MOS65XX_INS_CPY = 25 , MOS65XX_INS_DEC = 26 , MOS65XX_INS_DEX = 27 , MOS65XX_INS_DEY = 28 , MOS65XX_INS_EOR = 29 , MOS65XX_INS_INC = 30 , MOS65XX_INS_INX = 31 , MOS65XX_INS_INY = 32 , MOS65XX_INS_JML = 33 , MOS65XX_INS_JMP = 34 , MOS65XX_INS_JSL = 35 , MOS65XX_INS_JSR = 36 , MOS65XX_INS_LDA = 37 , MOS65XX_INS_LDX = 38 , MOS65XX_INS_LDY = 39 , MOS65XX_INS_LSR = 40 , MOS65XX_INS_MVN = 41 , MOS65XX_INS_MVP = 42 , MOS65XX_INS_NOP = 43 , MOS65XX_INS_ORA = 44 , MOS65XX_INS_PEA = 45 , MOS65XX_INS_PEI = 46 , MOS65XX_INS_PER = 47 , MOS65XX_INS_PHA = 48 , MOS65XX_INS_PHB = 49 , MOS65XX_INS_PHD = 50 , MOS65XX_INS_PHK = 51 , MOS65XX_INS_PHP = 52 , MOS65XX_INS_PHX = 53 , MOS65XX_INS_PHY = 54 , MOS65XX_INS_PLA = 55 , MOS65XX_INS_PLB = 56 , MOS65XX_INS_PLD = 57 , MOS65XX_INS_PLP = 58 , MOS65XX_INS_PLX = 59 , MOS65XX_INS_PLY = 60 , MOS65XX_INS_REP = 61 , MOS65XX_INS_RMB = 62 , MOS65XX_INS_ROL = 63 , MOS65XX_INS_ROR = 64 , MOS65XX_INS_RTI = 65 , MOS65XX_INS_RTL = 66 , MOS65XX_INS_RTS = 67 , MOS65XX_INS_SBC = 68 , MOS65XX_INS_SEC = 69 , MOS65XX_INS_SED = 70 , MOS65XX_INS_SEI = 71 , MOS65XX_INS_SEP = 72 , MOS65XX_INS_SMB = 73 , MOS65XX_INS_STA = 74 , MOS65XX_INS_STP = 75 , MOS65XX_INS_STX = 76 , MOS65XX_INS_STY = 77 , MOS65XX_INS_STZ = 78 , MOS65XX_INS_TAX = 79 , MOS65XX_INS_TAY = 80 , MOS65XX_INS_TCD = 81 , MOS65XX_INS_TCS = 82 , MOS65XX_INS_TDC = 83 , MOS65XX_INS_TRB = 84 , MOS65XX_INS_TSB = 85 , MOS65XX_INS_TSC = 86 , MOS65XX_INS_TSX = 87 , MOS65XX_INS_TXA = 88 , MOS65XX_INS_TXS = 89 , MOS65XX_INS_TXY = 90 , MOS65XX_INS_TYA = 91 , MOS65XX_INS_TYX = 92 , MOS65XX_INS_WAI = 93 , MOS65XX_INS_WDM = 94 , MOS65XX_INS_XBA = 95 , MOS65XX_INS_XCE = 96 , MOS65XX_INS_ENDING = 97 , } # [repr (u32)] # [doc = " Group of MOS65XX instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_group_type { # [doc = "< CS_GRP_INVALID"] MOS65XX_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MOS65XX_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MOS65XX_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MOS65XX_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MOS65XX_GRP_BRANCH_RELATIVE = 6 , MOS65XX_GRP_ENDING = 7 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MOS65XX_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MOS65XX_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MOS65XX_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MOS65XX_OP_MEM = 3 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx_op { # [doc = "< operand type"] pub type_ : mos65xx_op_type , pub __bindgen_anon_1 : cs_mos65xx_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mos65xx_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : mos65xx_reg , # [doc = "< immediate value for IMM operand"] pub imm : u16 , # [doc = "< address for MEM operand"] pub mem : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Alignment of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op"] [:: std :: mem :: size_of :: < cs_mos65xx_op > () - 8usize] ; ["Alignment of cs_mos65xx_op"] [:: std :: mem :: align_of :: < cs_mos65xx_op > () - 4usize] ; ["Offset of field: cs_mos65xx_op::type_"] [:: std :: mem :: offset_of ! (cs_mos65xx_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The MOS65XX address mode and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx { pub am : mos65xx_address_mode , pub modifies_flags : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mos65xx_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx"] [:: std :: mem :: size_of :: < cs_mos65xx > () - 32usize] ; ["Alignment of cs_mos65xx"] [:: std :: mem :: align_of :: < cs_mos65xx > () - 4usize] ; ["Offset of field: cs_mos65xx::am"] [:: std :: mem :: offset_of ! (cs_mos65xx , am) - 0usize] ; ["Offset of field: cs_mos65xx::modifies_flags"] [:: std :: mem :: offset_of ! (cs_mos65xx , modifies_flags) - 4usize] ; ["Offset of field: cs_mos65xx::op_count"] [:: std :: mem :: offset_of ! (cs_mos65xx , op_count) - 5usize] ; ["Offset of field: cs_mos65xx::operands"] [:: std :: mem :: offset_of ! (cs_mos65xx , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . am , self . modifies_flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_op_type { BPF_OP_INVALID = 0 , BPF_OP_REG = 1 , BPF_OP_IMM = 2 , BPF_OP_OFF = 3 , BPF_OP_MEM = 4 , # [doc = "< M[k] in cBPF"] BPF_OP_MMEM = 5 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] BPF_OP_MSH = 6 , # [doc = "< cBPF's extension (not eBPF)"] BPF_OP_EXT = 7 , } # [repr (u32)] # [doc = " BPF registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_reg { BPF_REG_INVALID = 0 , BPF_REG_A = 1 , BPF_REG_X = 2 , BPF_REG_R0 = 3 , BPF_REG_R1 = 4 , BPF_REG_R2 = 5 , BPF_REG_R3 = 6 , BPF_REG_R4 = 7 , BPF_REG_R5 = 8 , BPF_REG_R6 = 9 , BPF_REG_R7 = 10 , BPF_REG_R8 = 11 , BPF_REG_R9 = 12 , BPF_REG_R10 = 13 , BPF_REG_ENDING = 14 , } # [doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct bpf_op_mem { # [doc = "< base register"] pub base : bpf_reg , # [doc = "< offset value"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of bpf_op_mem"] [:: std :: mem :: size_of :: < bpf_op_mem > () - 8usize] ; ["Alignment of bpf_op_mem"] [:: std :: mem :: align_of :: < bpf_op_mem > () - 4usize] ; ["Offset of field: bpf_op_mem::base"] [:: std :: mem :: offset_of ! (bpf_op_mem , base) - 0usize] ; ["Offset of field: bpf_op_mem::disp"] [:: std :: mem :: offset_of ! (bpf_op_mem , disp) - 4usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_ext_type { BPF_EXT_INVALID = 0 , BPF_EXT_LEN = 1 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf_op { pub type_ : bpf_op_type , pub __bindgen_anon_1 : cs_bpf_op__bindgen_ty_1 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_bpf_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : u8 , # [doc = "< immediate value IMM operand"] pub imm : u64 , # [doc = "< offset value, used in jump & call"] pub off : u32 , # [doc = "< base/disp value for MEM operand"] pub mem : bpf_op_mem , # [doc = "< M[k] in cBPF"] pub mmem : u32 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] pub msh : u32 , # [doc = "< cBPF's extension (not eBPF)"] pub ext : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::off"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , off) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mmem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mmem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::msh"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , msh) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , ext) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op"] [:: std :: mem :: size_of :: < cs_bpf_op > () - 24usize] ; ["Alignment of cs_bpf_op"] [:: std :: mem :: align_of :: < cs_bpf_op > () - 8usize] ; ["Offset of field: cs_bpf_op::type_"] [:: std :: mem :: offset_of ! (cs_bpf_op , type_) - 0usize] ; ["Offset of field: cs_bpf_op::access"] [:: std :: mem :: offset_of ! (cs_bpf_op , access) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf { pub op_count : u8 , pub operands : [cs_bpf_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf"] [:: std :: mem :: size_of :: < cs_bpf > () - 104usize] ; ["Alignment of cs_bpf"] [:: std :: mem :: align_of :: < cs_bpf > () - 8usize] ; ["Offset of field: cs_bpf::op_count"] [:: std :: mem :: offset_of ! (cs_bpf , op_count) - 0usize] ; ["Offset of field: cs_bpf::operands"] [:: std :: mem :: offset_of ! (cs_bpf , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } impl bpf_insn { pub const BPF_INS_LD : bpf_insn = bpf_insn :: BPF_INS_LDW ; } impl bpf_insn { pub const BPF_INS_LDX : bpf_insn = bpf_insn :: BPF_INS_LDXW ; } impl bpf_insn { pub const BPF_INS_ST : bpf_insn = bpf_insn :: BPF_INS_STW ; } impl bpf_insn { pub const BPF_INS_STX : bpf_insn = bpf_insn :: BPF_INS_STXW ; } # [repr (u32)] # [doc = " BPF instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn { BPF_INS_INVALID = 0 , BPF_INS_ADD = 1 , BPF_INS_SUB = 2 , BPF_INS_MUL = 3 , BPF_INS_DIV = 4 , BPF_INS_OR = 5 , BPF_INS_AND = 6 , BPF_INS_LSH = 7 , BPF_INS_RSH = 8 , BPF_INS_NEG = 9 , BPF_INS_MOD = 10 , BPF_INS_XOR = 11 , # [doc = "< eBPF only"] BPF_INS_MOV = 12 , # [doc = "< eBPF only"] BPF_INS_ARSH = 13 , BPF_INS_ADD64 = 14 , BPF_INS_SUB64 = 15 , BPF_INS_MUL64 = 16 , BPF_INS_DIV64 = 17 , BPF_INS_OR64 = 18 , BPF_INS_AND64 = 19 , BPF_INS_LSH64 = 20 , BPF_INS_RSH64 = 21 , BPF_INS_NEG64 = 22 , BPF_INS_MOD64 = 23 , BPF_INS_XOR64 = 24 , BPF_INS_MOV64 = 25 , BPF_INS_ARSH64 = 26 , BPF_INS_LE16 = 27 , BPF_INS_LE32 = 28 , BPF_INS_LE64 = 29 , BPF_INS_BE16 = 30 , BPF_INS_BE32 = 31 , BPF_INS_BE64 = 32 , # [doc = "< eBPF only"] BPF_INS_LDW = 33 , BPF_INS_LDH = 34 , BPF_INS_LDB = 35 , # [doc = "< eBPF only: load 64-bit imm"] BPF_INS_LDDW = 36 , # [doc = "< eBPF only"] BPF_INS_LDXW = 37 , # [doc = "< eBPF only"] BPF_INS_LDXH = 38 , # [doc = "< eBPF only"] BPF_INS_LDXB = 39 , # [doc = "< eBPF only"] BPF_INS_LDXDW = 40 , # [doc = "< eBPF only"] BPF_INS_STW = 41 , # [doc = "< eBPF only"] BPF_INS_STH = 42 , # [doc = "< eBPF only"] BPF_INS_STB = 43 , # [doc = "< eBPF only"] BPF_INS_STDW = 44 , # [doc = "< eBPF only"] BPF_INS_STXW = 45 , # [doc = "< eBPF only"] BPF_INS_STXH = 46 , # [doc = "< eBPF only"] BPF_INS_STXB = 47 , # [doc = "< eBPF only"] BPF_INS_STXDW = 48 , # [doc = "< eBPF only"] BPF_INS_XADDW = 49 , # [doc = "< eBPF only"] BPF_INS_XADDDW = 50 , BPF_INS_JMP = 51 , BPF_INS_JEQ = 52 , BPF_INS_JGT = 53 , BPF_INS_JGE = 54 , BPF_INS_JSET = 55 , # [doc = "< eBPF only"] BPF_INS_JNE = 56 , # [doc = "< eBPF only"] BPF_INS_JSGT = 57 , # [doc = "< eBPF only"] BPF_INS_JSGE = 58 , # [doc = "< eBPF only"] BPF_INS_CALL = 59 , # [doc = "< eBPF only"] BPF_INS_CALLX = 60 , # [doc = "< eBPF only"] BPF_INS_EXIT = 61 , # [doc = "< eBPF only"] BPF_INS_JLT = 62 , # [doc = "< eBPF only"] BPF_INS_JLE = 63 , # [doc = "< eBPF only"] BPF_INS_JSLT = 64 , # [doc = "< eBPF only"] BPF_INS_JSLE = 65 , BPF_INS_RET = 66 , BPF_INS_TAX = 67 , BPF_INS_TXA = 68 , BPF_INS_ENDING = 69 , } # [repr (u32)] # [doc = " Group of BPF instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn_group { # [doc = "< = CS_GRP_INVALID"] BPF_GRP_INVALID = 0 , BPF_GRP_LOAD = 1 , BPF_GRP_STORE = 2 , BPF_GRP_ALU = 3 , BPF_GRP_JUMP = 4 , # [doc = "< eBPF only"] BPF_GRP_CALL = 5 , BPF_GRP_RETURN = 6 , # [doc = "< cBPF only"] BPF_GRP_MISC = 7 , BPF_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " SH registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_reg { SH_REG_INVALID = 0 , SH_REG_R0 = 1 , SH_REG_R1 = 2 , SH_REG_R2 = 3 , SH_REG_R3 = 4 , SH_REG_R4 = 5 , SH_REG_R5 = 6 , SH_REG_R6 = 7 , SH_REG_R7 = 8 , SH_REG_R8 = 9 , SH_REG_R9 = 10 , SH_REG_R10 = 11 , SH_REG_R11 = 12 , SH_REG_R12 = 13 , SH_REG_R13 = 14 , SH_REG_R14 = 15 , SH_REG_R15 = 16 , SH_REG_R0_BANK = 17 , SH_REG_R1_BANK = 18 , SH_REG_R2_BANK = 19 , SH_REG_R3_BANK = 20 , SH_REG_R4_BANK = 21 , SH_REG_R5_BANK = 22 , SH_REG_R6_BANK = 23 , SH_REG_R7_BANK = 24 , SH_REG_FR0 = 25 , SH_REG_FR1 = 26 , SH_REG_FR2 = 27 , SH_REG_FR3 = 28 , SH_REG_FR4 = 29 , SH_REG_FR5 = 30 , SH_REG_FR6 = 31 , SH_REG_FR7 = 32 , SH_REG_FR8 = 33 , SH_REG_FR9 = 34 , SH_REG_FR10 = 35 , SH_REG_FR11 = 36 , SH_REG_FR12 = 37 , SH_REG_FR13 = 38 , SH_REG_FR14 = 39 , SH_REG_FR15 = 40 , SH_REG_DR0 = 41 , SH_REG_DR2 = 42 , SH_REG_DR4 = 43 , SH_REG_DR6 = 44 , SH_REG_DR8 = 45 , SH_REG_DR10 = 46 , SH_REG_DR12 = 47 , SH_REG_DR14 = 48 , SH_REG_XD0 = 49 , SH_REG_XD2 = 50 , SH_REG_XD4 = 51 , SH_REG_XD6 = 52 , SH_REG_XD8 = 53 , SH_REG_XD10 = 54 , SH_REG_XD12 = 55 , SH_REG_XD14 = 56 , SH_REG_XF0 = 57 , SH_REG_XF1 = 58 , SH_REG_XF2 = 59 , SH_REG_XF3 = 60 , SH_REG_XF4 = 61 , SH_REG_XF5 = 62 , SH_REG_XF6 = 63 , SH_REG_XF7 = 64 , SH_REG_XF8 = 65 , SH_REG_XF9 = 66 , SH_REG_XF10 = 67 , SH_REG_XF11 = 68 , SH_REG_XF12 = 69 , SH_REG_XF13 = 70 , SH_REG_XF14 = 71 , SH_REG_XF15 = 72 , SH_REG_FV0 = 73 , SH_REG_FV4 = 74 , SH_REG_FV8 = 75 , SH_REG_FV12 = 76 , SH_REG_XMATRX = 77 , SH_REG_PC = 78 , SH_REG_PR = 79 , SH_REG_MACH = 80 , SH_REG_MACL = 81 , SH_REG_SR = 82 , SH_REG_GBR = 83 , SH_REG_SSR = 84 , SH_REG_SPC = 85 , SH_REG_SGR = 86 , SH_REG_DBR = 87 , SH_REG_VBR = 88 , SH_REG_TBR = 89 , SH_REG_RS = 90 , SH_REG_RE = 91 , SH_REG_MOD = 92 , SH_REG_FPUL = 93 , SH_REG_FPSCR = 94 , SH_REG_DSP_X0 = 95 , SH_REG_DSP_X1 = 96 , SH_REG_DSP_Y0 = 97 , SH_REG_DSP_Y1 = 98 , SH_REG_DSP_A0 = 99 , SH_REG_DSP_A1 = 100 , SH_REG_DSP_A0G = 101 , SH_REG_DSP_A1G = 102 , SH_REG_DSP_M0 = 103 , SH_REG_DSP_M1 = 104 , SH_REG_DSP_DSR = 105 , SH_REG_DSP_RSV0 = 106 , SH_REG_DSP_RSV1 = 107 , SH_REG_DSP_RSV2 = 108 , SH_REG_DSP_RSV3 = 109 , SH_REG_DSP_RSV4 = 110 , SH_REG_DSP_RSV5 = 111 , SH_REG_DSP_RSV6 = 112 , SH_REG_DSP_RSV7 = 113 , SH_REG_DSP_RSV8 = 114 , SH_REG_DSP_RSV9 = 115 , SH_REG_DSP_RSVA = 116 , SH_REG_DSP_RSVB = 117 , SH_REG_DSP_RSVC = 118 , SH_REG_DSP_RSVD = 119 , SH_REG_DSP_RSVE = 120 , SH_REG_DSP_RSVF = 121 , SH_REG_ENDING = 122 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SH_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SH_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SH_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SH_OP_MEM = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_mem_type { SH_OP_MEM_INVALID = 0 , # [doc = " <= Invalid"] SH_OP_MEM_REG_IND = 1 , # [doc = " <= Register indirect"] SH_OP_MEM_REG_POST = 2 , # [doc = " <= Register post increment"] SH_OP_MEM_REG_PRE = 3 , # [doc = " <= Register pre decrement"] SH_OP_MEM_REG_DISP = 4 , # [doc = " <= displacement"] SH_OP_MEM_REG_R0 = 5 , # [doc = " <= R0 indexed"] SH_OP_MEM_GBR_DISP = 6 , # [doc = " <= GBR based displacement"] SH_OP_MEM_GBR_R0 = 7 , # [doc = " <= GBR based R0 indexed"] SH_OP_MEM_PCR = 8 , # [doc = " <= PC relative"] SH_OP_MEM_TBR_DISP = 9 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_mem { pub address : sh_op_mem_type , # [doc = " <= memory address"] pub reg : sh_reg , # [doc = " <= base register"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_mem"] [:: std :: mem :: size_of :: < sh_op_mem > () - 12usize] ; ["Alignment of sh_op_mem"] [:: std :: mem :: align_of :: < sh_op_mem > () - 4usize] ; ["Offset of field: sh_op_mem::address"] [:: std :: mem :: offset_of ! (sh_op_mem , address) - 0usize] ; ["Offset of field: sh_op_mem::reg"] [:: std :: mem :: offset_of ! (sh_op_mem , reg) - 4usize] ; ["Offset of field: sh_op_mem::disp"] [:: std :: mem :: offset_of ! (sh_op_mem , disp) - 8usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn_type { SH_INS_DSP_INVALID = 0 , SH_INS_DSP_DOUBLE = 1 , SH_INS_DSP_SINGLE = 2 , SH_INS_DSP_PARALLEL = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn { SH_INS_DSP_NOP = 1 , SH_INS_DSP_MOV = 2 , SH_INS_DSP_PSHL = 3 , SH_INS_DSP_PSHA = 4 , SH_INS_DSP_PMULS = 5 , SH_INS_DSP_PCLR_PMULS = 6 , SH_INS_DSP_PSUB_PMULS = 7 , SH_INS_DSP_PADD_PMULS = 8 , SH_INS_DSP_PSUBC = 9 , SH_INS_DSP_PADDC = 10 , SH_INS_DSP_PCMP = 11 , SH_INS_DSP_PABS = 12 , SH_INS_DSP_PRND = 13 , SH_INS_DSP_PSUB = 14 , SH_INS_DSP_PSUBr = 15 , SH_INS_DSP_PADD = 16 , SH_INS_DSP_PAND = 17 , SH_INS_DSP_PXOR = 18 , SH_INS_DSP_POR = 19 , SH_INS_DSP_PDEC = 20 , SH_INS_DSP_PINC = 21 , SH_INS_DSP_PCLR = 22 , SH_INS_DSP_PDMSB = 23 , SH_INS_DSP_PNEG = 24 , SH_INS_DSP_PCOPY = 25 , SH_INS_DSP_PSTS = 26 , SH_INS_DSP_PLDS = 27 , SH_INS_DSP_PSWAP = 28 , SH_INS_DSP_PWAD = 29 , SH_INS_DSP_PWSB = 30 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_operand { SH_OP_DSP_INVALID = 0 , SH_OP_DSP_REG_PRE = 1 , SH_OP_DSP_REG_IND = 2 , SH_OP_DSP_REG_POST = 3 , SH_OP_DSP_REG_INDEX = 4 , SH_OP_DSP_REG = 5 , SH_OP_DSP_IMM = 6 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_cc { SH_DSP_CC_INVALID = 0 , SH_DSP_CC_NONE = 1 , SH_DSP_CC_DCT = 2 , SH_DSP_CC_DCF = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_dsp { pub insn : sh_dsp_insn , pub operand : [sh_dsp_operand ; 2usize] , pub r : [sh_reg ; 6usize] , pub cc : sh_dsp_cc , pub imm : u8 , pub size : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_dsp"] [:: std :: mem :: size_of :: < sh_op_dsp > () - 48usize] ; ["Alignment of sh_op_dsp"] [:: std :: mem :: align_of :: < sh_op_dsp > () - 4usize] ; ["Offset of field: sh_op_dsp::insn"] [:: std :: mem :: offset_of ! (sh_op_dsp , insn) - 0usize] ; ["Offset of field: sh_op_dsp::operand"] [:: std :: mem :: offset_of ! (sh_op_dsp , operand) - 4usize] ; ["Offset of field: sh_op_dsp::r"] [:: std :: mem :: offset_of ! (sh_op_dsp , r) - 12usize] ; ["Offset of field: sh_op_dsp::cc"] [:: std :: mem :: offset_of ! (sh_op_dsp , cc) - 36usize] ; ["Offset of field: sh_op_dsp::imm"] [:: std :: mem :: offset_of ! (sh_op_dsp , imm) - 40usize] ; ["Offset of field: sh_op_dsp::size"] [:: std :: mem :: offset_of ! (sh_op_dsp , size) - 44usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh_op { pub type_ : sh_op_type , pub __bindgen_anon_1 : cs_sh_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sh_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< register value for REG operand"] pub reg : sh_reg , # [doc = "< data when operand is targeting memory"] pub mem : sh_op_mem , # [doc = "< dsp instruction"] pub dsp : sh_op_dsp , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sh_op__bindgen_ty_1 > () - 48usize] ; ["Alignment of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sh_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::dsp"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , dsp) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op"] [:: std :: mem :: size_of :: < cs_sh_op > () - 56usize] ; ["Alignment of cs_sh_op"] [:: std :: mem :: align_of :: < cs_sh_op > () - 8usize] ; ["Offset of field: cs_sh_op::type_"] [:: std :: mem :: offset_of ! (cs_sh_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (u32)] # [doc = " SH instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn { SH_INS_INVALID = 0 , SH_INS_ADD_r = 1 , SH_INS_ADD = 2 , SH_INS_ADDC = 3 , SH_INS_ADDV = 4 , SH_INS_AND = 5 , SH_INS_BAND = 6 , SH_INS_BANDNOT = 7 , SH_INS_BCLR = 8 , SH_INS_BF = 9 , SH_INS_BF_S = 10 , SH_INS_BLD = 11 , SH_INS_BLDNOT = 12 , SH_INS_BOR = 13 , SH_INS_BORNOT = 14 , SH_INS_BRA = 15 , SH_INS_BRAF = 16 , SH_INS_BSET = 17 , SH_INS_BSR = 18 , SH_INS_BSRF = 19 , SH_INS_BST = 20 , SH_INS_BT = 21 , SH_INS_BT_S = 22 , SH_INS_BXOR = 23 , SH_INS_CLIPS = 24 , SH_INS_CLIPU = 25 , SH_INS_CLRDMXY = 26 , SH_INS_CLRMAC = 27 , SH_INS_CLRS = 28 , SH_INS_CLRT = 29 , SH_INS_CMP_EQ = 30 , SH_INS_CMP_GE = 31 , SH_INS_CMP_GT = 32 , SH_INS_CMP_HI = 33 , SH_INS_CMP_HS = 34 , SH_INS_CMP_PL = 35 , SH_INS_CMP_PZ = 36 , SH_INS_CMP_STR = 37 , SH_INS_DIV0S = 38 , SH_INS_DIV0U = 39 , SH_INS_DIV1 = 40 , SH_INS_DIVS = 41 , SH_INS_DIVU = 42 , SH_INS_DMULS_L = 43 , SH_INS_DMULU_L = 44 , SH_INS_DT = 45 , SH_INS_EXTS_B = 46 , SH_INS_EXTS_W = 47 , SH_INS_EXTU_B = 48 , SH_INS_EXTU_W = 49 , SH_INS_FABS = 50 , SH_INS_FADD = 51 , SH_INS_FCMP_EQ = 52 , SH_INS_FCMP_GT = 53 , SH_INS_FCNVDS = 54 , SH_INS_FCNVSD = 55 , SH_INS_FDIV = 56 , SH_INS_FIPR = 57 , SH_INS_FLDI0 = 58 , SH_INS_FLDI1 = 59 , SH_INS_FLDS = 60 , SH_INS_FLOAT = 61 , SH_INS_FMAC = 62 , SH_INS_FMOV = 63 , SH_INS_FMUL = 64 , SH_INS_FNEG = 65 , SH_INS_FPCHG = 66 , SH_INS_FRCHG = 67 , SH_INS_FSCA = 68 , SH_INS_FSCHG = 69 , SH_INS_FSQRT = 70 , SH_INS_FSRRA = 71 , SH_INS_FSTS = 72 , SH_INS_FSUB = 73 , SH_INS_FTRC = 74 , SH_INS_FTRV = 75 , SH_INS_ICBI = 76 , SH_INS_JMP = 77 , SH_INS_JSR = 78 , SH_INS_JSR_N = 79 , SH_INS_LDBANK = 80 , SH_INS_LDC = 81 , SH_INS_LDRC = 82 , SH_INS_LDRE = 83 , SH_INS_LDRS = 84 , SH_INS_LDS = 85 , SH_INS_LDTLB = 86 , SH_INS_MAC_L = 87 , SH_INS_MAC_W = 88 , SH_INS_MOV = 89 , SH_INS_MOVA = 90 , SH_INS_MOVCA = 91 , SH_INS_MOVCO = 92 , SH_INS_MOVI20 = 93 , SH_INS_MOVI20S = 94 , SH_INS_MOVLI = 95 , SH_INS_MOVML = 96 , SH_INS_MOVMU = 97 , SH_INS_MOVRT = 98 , SH_INS_MOVT = 99 , SH_INS_MOVU = 100 , SH_INS_MOVUA = 101 , SH_INS_MUL_L = 102 , SH_INS_MULR = 103 , SH_INS_MULS_W = 104 , SH_INS_MULU_W = 105 , SH_INS_NEG = 106 , SH_INS_NEGC = 107 , SH_INS_NOP = 108 , SH_INS_NOT = 109 , SH_INS_NOTT = 110 , SH_INS_OCBI = 111 , SH_INS_OCBP = 112 , SH_INS_OCBWB = 113 , SH_INS_OR = 114 , SH_INS_PREF = 115 , SH_INS_PREFI = 116 , SH_INS_RESBANK = 117 , SH_INS_ROTCL = 118 , SH_INS_ROTCR = 119 , SH_INS_ROTL = 120 , SH_INS_ROTR = 121 , SH_INS_RTE = 122 , SH_INS_RTS = 123 , SH_INS_RTS_N = 124 , SH_INS_RTV_N = 125 , SH_INS_SETDMX = 126 , SH_INS_SETDMY = 127 , SH_INS_SETRC = 128 , SH_INS_SETS = 129 , SH_INS_SETT = 130 , SH_INS_SHAD = 131 , SH_INS_SHAL = 132 , SH_INS_SHAR = 133 , SH_INS_SHLD = 134 , SH_INS_SHLL = 135 , SH_INS_SHLL16 = 136 , SH_INS_SHLL2 = 137 , SH_INS_SHLL8 = 138 , SH_INS_SHLR = 139 , SH_INS_SHLR16 = 140 , SH_INS_SHLR2 = 141 , SH_INS_SHLR8 = 142 , SH_INS_SLEEP = 143 , SH_INS_STBANK = 144 , SH_INS_STC = 145 , SH_INS_STS = 146 , SH_INS_SUB = 147 , SH_INS_SUBC = 148 , SH_INS_SUBV = 149 , SH_INS_SWAP_B = 150 , SH_INS_SWAP_W = 151 , SH_INS_SYNCO = 152 , SH_INS_TAS = 153 , SH_INS_TRAPA = 154 , SH_INS_TST = 155 , SH_INS_XOR = 156 , SH_INS_XTRCT = 157 , SH_INS_DSP = 158 , SH_INS_ENDING = 159 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh { pub insn : sh_insn , pub size : u8 , pub op_count : u8 , pub operands : [cs_sh_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh"] [:: std :: mem :: size_of :: < cs_sh > () - 176usize] ; ["Alignment of cs_sh"] [:: std :: mem :: align_of :: < cs_sh > () - 8usize] ; ["Offset of field: cs_sh::insn"] [:: std :: mem :: offset_of ! (cs_sh , insn) - 0usize] ; ["Offset of field: cs_sh::size"] [:: std :: mem :: offset_of ! (cs_sh , size) - 4usize] ; ["Offset of field: cs_sh::op_count"] [:: std :: mem :: offset_of ! (cs_sh , op_count) - 5usize] ; ["Offset of field: cs_sh::operands"] [:: std :: mem :: offset_of ! (cs_sh , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sh { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh {{ insn: {:?}, size: {:?}, op_count: {:?}, operands: {:?} }}" , self . insn , self . size , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Group of SH instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn_group { # [doc = "< CS_GRUP_INVALID"] SH_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SH_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] SH_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] SH_GRP_INT = 3 , # [doc = "< = CS_GRP_RET"] SH_GRP_RET = 4 , # [doc = "< = CS_GRP_IRET"] SH_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] SH_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] SH_GRP_BRANCH_RELATIVE = 7 , SH_GRP_SH1 = 8 , SH_GRP_SH2 = 9 , SH_GRP_SH2E = 10 , SH_GRP_SH2DSP = 11 , SH_GRP_SH2A = 12 , SH_GRP_SH2AFPU = 13 , SH_GRP_SH3 = 14 , SH_GRP_SH3DSP = 15 , SH_GRP_SH4 = 16 , SH_GRP_SH4A = 17 , SH_GRP_ENDING = 18 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_op_type { # [doc = "< CS_OP_INVALID (Uninitialized)."] TRICORE_OP_INVALID = 0 , # [doc = "< CS_OP_REG (Register operand)."] TRICORE_OP_REG = 1 , # [doc = "< CS_OP_IMM (Immediate operand)."] TRICORE_OP_IMM = 2 , # [doc = "< CS_OP_MEM (Memory operand)."] TRICORE_OP_MEM = 3 , } # [doc = " Instruction's operand referring to memory\n This is associated with TRICORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tricore_op_mem { # [doc = "< base register"] pub base : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tricore_op_mem"] [:: std :: mem :: size_of :: < tricore_op_mem > () - 8usize] ; ["Alignment of tricore_op_mem"] [:: std :: mem :: align_of :: < tricore_op_mem > () - 4usize] ; ["Offset of field: tricore_op_mem::base"] [:: std :: mem :: offset_of ! (tricore_op_mem , base) - 0usize] ; ["Offset of field: tricore_op_mem::disp"] [:: std :: mem :: offset_of ! (tricore_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore_op { # [doc = "< operand type"] pub type_ : tricore_op_type , pub __bindgen_anon_1 : cs_tricore_op__bindgen_ty_1 , # [doc = "< How is this operand accessed? (READ, WRITE or READ|WRITE)"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tricore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tricore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tricore_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tricore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op"] [:: std :: mem :: size_of :: < cs_tricore_op > () - 16usize] ; ["Alignment of cs_tricore_op"] [:: std :: mem :: align_of :: < cs_tricore_op > () - 4usize] ; ["Offset of field: cs_tricore_op::type_"] [:: std :: mem :: offset_of ! (cs_tricore_op , type_) - 0usize] ; ["Offset of field: cs_tricore_op::access"] [:: std :: mem :: offset_of ! (cs_tricore_op , access) - 12usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore { # [doc = "< number of operands of this instruction."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tricore_op ; 8usize] , # [doc = "< whether the flags register is updated."] pub update_flags : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore"] [:: std :: mem :: size_of :: < cs_tricore > () - 136usize] ; ["Alignment of cs_tricore"] [:: std :: mem :: align_of :: < cs_tricore > () - 4usize] ; ["Offset of field: cs_tricore::op_count"] [:: std :: mem :: offset_of ! (cs_tricore , op_count) - 0usize] ; ["Offset of field: cs_tricore::operands"] [:: std :: mem :: offset_of ! (cs_tricore , operands) - 4usize] ; ["Offset of field: cs_tricore::update_flags"] [:: std :: mem :: offset_of ! (cs_tricore , update_flags) - 132usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore {{ op_count: {:?}, operands: {:?}, update_flags: {:?} }}" , self . op_count , self . operands , self . update_flags) } } # [repr (u32)] # [doc = " TriCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_reg { TRICORE_REG_INVALID = 0 , TRICORE_REG_FCX = 1 , TRICORE_REG_PC = 2 , TRICORE_REG_PCXI = 3 , TRICORE_REG_PSW = 4 , TRICORE_REG_A0 = 5 , TRICORE_REG_A1 = 6 , TRICORE_REG_A2 = 7 , TRICORE_REG_A3 = 8 , TRICORE_REG_A4 = 9 , TRICORE_REG_A5 = 10 , TRICORE_REG_A6 = 11 , TRICORE_REG_A7 = 12 , TRICORE_REG_A8 = 13 , TRICORE_REG_A9 = 14 , TRICORE_REG_A10 = 15 , TRICORE_REG_A11 = 16 , TRICORE_REG_A12 = 17 , TRICORE_REG_A13 = 18 , TRICORE_REG_A14 = 19 , TRICORE_REG_A15 = 20 , TRICORE_REG_D0 = 21 , TRICORE_REG_D1 = 22 , TRICORE_REG_D2 = 23 , TRICORE_REG_D3 = 24 , TRICORE_REG_D4 = 25 , TRICORE_REG_D5 = 26 , TRICORE_REG_D6 = 27 , TRICORE_REG_D7 = 28 , TRICORE_REG_D8 = 29 , TRICORE_REG_D9 = 30 , TRICORE_REG_D10 = 31 , TRICORE_REG_D11 = 32 , TRICORE_REG_D12 = 33 , TRICORE_REG_D13 = 34 , TRICORE_REG_D14 = 35 , TRICORE_REG_D15 = 36 , TRICORE_REG_E0 = 37 , TRICORE_REG_E2 = 38 , TRICORE_REG_E4 = 39 , TRICORE_REG_E6 = 40 , TRICORE_REG_E8 = 41 , TRICORE_REG_E10 = 42 , TRICORE_REG_E12 = 43 , TRICORE_REG_E14 = 44 , TRICORE_REG_P0 = 45 , TRICORE_REG_P2 = 46 , TRICORE_REG_P4 = 47 , TRICORE_REG_P6 = 48 , TRICORE_REG_P8 = 49 , TRICORE_REG_P10 = 50 , TRICORE_REG_P12 = 51 , TRICORE_REG_P14 = 52 , TRICORE_REG_A0_A1 = 53 , TRICORE_REG_A2_A3 = 54 , TRICORE_REG_A4_A5 = 55 , TRICORE_REG_A6_A7 = 56 , TRICORE_REG_A8_A9 = 57 , TRICORE_REG_A10_A11 = 58 , TRICORE_REG_A12_A13 = 59 , TRICORE_REG_A14_A15 = 60 , TRICORE_REG_ENDING = 61 , } # [repr (u32)] # [doc = " TriCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn { TRICORE_INS_INVALID = 0 , TRICORE_INS_XOR_T = 1 , TRICORE_INS_ABSDIFS_B = 2 , TRICORE_INS_ABSDIFS_H = 3 , TRICORE_INS_ABSDIFS = 4 , TRICORE_INS_ABSDIF_B = 5 , TRICORE_INS_ABSDIF_H = 6 , TRICORE_INS_ABSDIF = 7 , TRICORE_INS_ABSS_B = 8 , TRICORE_INS_ABSS_H = 9 , TRICORE_INS_ABSS = 10 , TRICORE_INS_ABS_B = 11 , TRICORE_INS_ABS_H = 12 , TRICORE_INS_ABS = 13 , TRICORE_INS_ADDC = 14 , TRICORE_INS_ADDIH_A = 15 , TRICORE_INS_ADDIH = 16 , TRICORE_INS_ADDI = 17 , TRICORE_INS_ADDSC_AT = 18 , TRICORE_INS_ADDSC_A = 19 , TRICORE_INS_ADDS_BU = 20 , TRICORE_INS_ADDS_B = 21 , TRICORE_INS_ADDS_H = 22 , TRICORE_INS_ADDS_HU = 23 , TRICORE_INS_ADDS_U = 24 , TRICORE_INS_ADDS = 25 , TRICORE_INS_ADDX = 26 , TRICORE_INS_ADD_A = 27 , TRICORE_INS_ADD_B = 28 , TRICORE_INS_ADD_F = 29 , TRICORE_INS_ADD_H = 30 , TRICORE_INS_ADD = 31 , TRICORE_INS_ANDN_T = 32 , TRICORE_INS_ANDN = 33 , TRICORE_INS_AND_ANDN_T = 34 , TRICORE_INS_AND_AND_T = 35 , TRICORE_INS_AND_EQ = 36 , TRICORE_INS_AND_GE_U = 37 , TRICORE_INS_AND_GE = 38 , TRICORE_INS_AND_LT_U = 39 , TRICORE_INS_AND_LT = 40 , TRICORE_INS_AND_NE = 41 , TRICORE_INS_AND_NOR_T = 42 , TRICORE_INS_AND_OR_T = 43 , TRICORE_INS_AND_T = 44 , TRICORE_INS_AND = 45 , TRICORE_INS_BISR = 46 , TRICORE_INS_BMERGE = 47 , TRICORE_INS_BSPLIT = 48 , TRICORE_INS_CACHEA_I = 49 , TRICORE_INS_CACHEA_WI = 50 , TRICORE_INS_CACHEA_W = 51 , TRICORE_INS_CACHEI_I = 52 , TRICORE_INS_CACHEI_WI = 53 , TRICORE_INS_CACHEI_W = 54 , TRICORE_INS_CADDN_A = 55 , TRICORE_INS_CADDN = 56 , TRICORE_INS_CADD_A = 57 , TRICORE_INS_CADD = 58 , TRICORE_INS_CALLA = 59 , TRICORE_INS_CALLI = 60 , TRICORE_INS_CALL = 61 , TRICORE_INS_CLO_B = 62 , TRICORE_INS_CLO_H = 63 , TRICORE_INS_CLO = 64 , TRICORE_INS_CLS_B = 65 , TRICORE_INS_CLS_H = 66 , TRICORE_INS_CLS = 67 , TRICORE_INS_CLZ_B = 68 , TRICORE_INS_CLZ_H = 69 , TRICORE_INS_CLZ = 70 , TRICORE_INS_CMOVN = 71 , TRICORE_INS_CMOV = 72 , TRICORE_INS_CMPSWAP_W = 73 , TRICORE_INS_CMP_F = 74 , TRICORE_INS_CRC32B_W = 75 , TRICORE_INS_CRC32L_W = 76 , TRICORE_INS_CRC32_B = 77 , TRICORE_INS_CRCN = 78 , TRICORE_INS_CSUBN_A = 79 , TRICORE_INS_CSUBN = 80 , TRICORE_INS_CSUB_A = 81 , TRICORE_INS_CSUB = 82 , TRICORE_INS_DEBUG = 83 , TRICORE_INS_DEXTR = 84 , TRICORE_INS_DIFSC_A = 85 , TRICORE_INS_DISABLE = 86 , TRICORE_INS_DIV_F = 87 , TRICORE_INS_DIV_U = 88 , TRICORE_INS_DIV = 89 , TRICORE_INS_DSYNC = 90 , TRICORE_INS_DVADJ = 91 , TRICORE_INS_DVINIT_BU = 92 , TRICORE_INS_DVINIT_B = 93 , TRICORE_INS_DVINIT_HU = 94 , TRICORE_INS_DVINIT_H = 95 , TRICORE_INS_DVINIT_U = 96 , TRICORE_INS_DVINIT = 97 , TRICORE_INS_DVSTEP_U = 98 , TRICORE_INS_DVSTEP = 99 , TRICORE_INS_ENABLE = 100 , TRICORE_INS_EQANY_B = 101 , TRICORE_INS_EQANY_H = 102 , TRICORE_INS_EQZ_A = 103 , TRICORE_INS_EQ_A = 104 , TRICORE_INS_EQ_B = 105 , TRICORE_INS_EQ_H = 106 , TRICORE_INS_EQ_W = 107 , TRICORE_INS_EQ = 108 , TRICORE_INS_EXTR_U = 109 , TRICORE_INS_EXTR = 110 , TRICORE_INS_FCALLA = 111 , TRICORE_INS_FCALLI = 112 , TRICORE_INS_FCALL = 113 , TRICORE_INS_FRET = 114 , TRICORE_INS_FTOHP = 115 , TRICORE_INS_FTOIZ = 116 , TRICORE_INS_FTOI = 117 , TRICORE_INS_FTOQ31Z = 118 , TRICORE_INS_FTOQ31 = 119 , TRICORE_INS_FTOUZ = 120 , TRICORE_INS_FTOU = 121 , TRICORE_INS_GE_A = 122 , TRICORE_INS_GE_U = 123 , TRICORE_INS_GE = 124 , TRICORE_INS_HPTOF = 125 , TRICORE_INS_IMASK = 126 , TRICORE_INS_INSERT = 127 , TRICORE_INS_INSN_T = 128 , TRICORE_INS_INS_T = 129 , TRICORE_INS_ISYNC = 130 , TRICORE_INS_ITOF = 131 , TRICORE_INS_IXMAX_U = 132 , TRICORE_INS_IXMAX = 133 , TRICORE_INS_IXMIN_U = 134 , TRICORE_INS_IXMIN = 135 , TRICORE_INS_JA = 136 , TRICORE_INS_JEQ_A = 137 , TRICORE_INS_JEQ = 138 , TRICORE_INS_JGEZ = 139 , TRICORE_INS_JGE_U = 140 , TRICORE_INS_JGE = 141 , TRICORE_INS_JGTZ = 142 , TRICORE_INS_JI = 143 , TRICORE_INS_JLA = 144 , TRICORE_INS_JLEZ = 145 , TRICORE_INS_JLI = 146 , TRICORE_INS_JLTZ = 147 , TRICORE_INS_JLT_U = 148 , TRICORE_INS_JLT = 149 , TRICORE_INS_JL = 150 , TRICORE_INS_JNED = 151 , TRICORE_INS_JNEI = 152 , TRICORE_INS_JNE_A = 153 , TRICORE_INS_JNE = 154 , TRICORE_INS_JNZ_A = 155 , TRICORE_INS_JNZ_T = 156 , TRICORE_INS_JNZ = 157 , TRICORE_INS_JZ_A = 158 , TRICORE_INS_JZ_T = 159 , TRICORE_INS_JZ = 160 , TRICORE_INS_J = 161 , TRICORE_INS_LDLCX = 162 , TRICORE_INS_LDMST = 163 , TRICORE_INS_LDUCX = 164 , TRICORE_INS_LD_A = 165 , TRICORE_INS_LD_BU = 166 , TRICORE_INS_LD_B = 167 , TRICORE_INS_LD_DA = 168 , TRICORE_INS_LD_D = 169 , TRICORE_INS_LD_HU = 170 , TRICORE_INS_LD_H = 171 , TRICORE_INS_LD_Q = 172 , TRICORE_INS_LD_W = 173 , TRICORE_INS_LEA = 174 , TRICORE_INS_LHA = 175 , TRICORE_INS_LOOPU = 176 , TRICORE_INS_LOOP = 177 , TRICORE_INS_LT_A = 178 , TRICORE_INS_LT_B = 179 , TRICORE_INS_LT_BU = 180 , TRICORE_INS_LT_H = 181 , TRICORE_INS_LT_HU = 182 , TRICORE_INS_LT_U = 183 , TRICORE_INS_LT_W = 184 , TRICORE_INS_LT_WU = 185 , TRICORE_INS_LT = 186 , TRICORE_INS_MADDMS_H = 187 , TRICORE_INS_MADDMS_U = 188 , TRICORE_INS_MADDMS = 189 , TRICORE_INS_MADDM_H = 190 , TRICORE_INS_MADDM_Q = 191 , TRICORE_INS_MADDM_U = 192 , TRICORE_INS_MADDM = 193 , TRICORE_INS_MADDRS_H = 194 , TRICORE_INS_MADDRS_Q = 195 , TRICORE_INS_MADDR_H = 196 , TRICORE_INS_MADDR_Q = 197 , TRICORE_INS_MADDSUMS_H = 198 , TRICORE_INS_MADDSUM_H = 199 , TRICORE_INS_MADDSURS_H = 200 , TRICORE_INS_MADDSUR_H = 201 , TRICORE_INS_MADDSUS_H = 202 , TRICORE_INS_MADDSU_H = 203 , TRICORE_INS_MADDS_H = 204 , TRICORE_INS_MADDS_Q = 205 , TRICORE_INS_MADDS_U = 206 , TRICORE_INS_MADDS = 207 , TRICORE_INS_MADD_F = 208 , TRICORE_INS_MADD_H = 209 , TRICORE_INS_MADD_Q = 210 , TRICORE_INS_MADD_U = 211 , TRICORE_INS_MADD = 212 , TRICORE_INS_MAX_B = 213 , TRICORE_INS_MAX_BU = 214 , TRICORE_INS_MAX_H = 215 , TRICORE_INS_MAX_HU = 216 , TRICORE_INS_MAX_U = 217 , TRICORE_INS_MAX = 218 , TRICORE_INS_MFCR = 219 , TRICORE_INS_MIN_B = 220 , TRICORE_INS_MIN_BU = 221 , TRICORE_INS_MIN_H = 222 , TRICORE_INS_MIN_HU = 223 , TRICORE_INS_MIN_U = 224 , TRICORE_INS_MIN = 225 , TRICORE_INS_MOVH_A = 226 , TRICORE_INS_MOVH = 227 , TRICORE_INS_MOVZ_A = 228 , TRICORE_INS_MOV_AA = 229 , TRICORE_INS_MOV_A = 230 , TRICORE_INS_MOV_D = 231 , TRICORE_INS_MOV_U = 232 , TRICORE_INS_MOV = 233 , TRICORE_INS_MSUBADMS_H = 234 , TRICORE_INS_MSUBADM_H = 235 , TRICORE_INS_MSUBADRS_H = 236 , TRICORE_INS_MSUBADR_H = 237 , TRICORE_INS_MSUBADS_H = 238 , TRICORE_INS_MSUBAD_H = 239 , TRICORE_INS_MSUBMS_H = 240 , TRICORE_INS_MSUBMS_U = 241 , TRICORE_INS_MSUBMS = 242 , TRICORE_INS_MSUBM_H = 243 , TRICORE_INS_MSUBM_Q = 244 , TRICORE_INS_MSUBM_U = 245 , TRICORE_INS_MSUBM = 246 , TRICORE_INS_MSUBRS_H = 247 , TRICORE_INS_MSUBRS_Q = 248 , TRICORE_INS_MSUBR_H = 249 , TRICORE_INS_MSUBR_Q = 250 , TRICORE_INS_MSUBS_H = 251 , TRICORE_INS_MSUBS_Q = 252 , TRICORE_INS_MSUBS_U = 253 , TRICORE_INS_MSUBS = 254 , TRICORE_INS_MSUB_F = 255 , TRICORE_INS_MSUB_H = 256 , TRICORE_INS_MSUB_Q = 257 , TRICORE_INS_MSUB_U = 258 , TRICORE_INS_MSUB = 259 , TRICORE_INS_MTCR = 260 , TRICORE_INS_MULMS_H = 261 , TRICORE_INS_MULM_H = 262 , TRICORE_INS_MULM_U = 263 , TRICORE_INS_MULM = 264 , TRICORE_INS_MULR_H = 265 , TRICORE_INS_MULR_Q = 266 , TRICORE_INS_MULS_U = 267 , TRICORE_INS_MULS = 268 , TRICORE_INS_MUL_F = 269 , TRICORE_INS_MUL_H = 270 , TRICORE_INS_MUL_Q = 271 , TRICORE_INS_MUL_U = 272 , TRICORE_INS_MUL = 273 , TRICORE_INS_NAND_T = 274 , TRICORE_INS_NAND = 275 , TRICORE_INS_NEZ_A = 276 , TRICORE_INS_NE_A = 277 , TRICORE_INS_NE = 278 , TRICORE_INS_NOP = 279 , TRICORE_INS_NOR_T = 280 , TRICORE_INS_NOR = 281 , TRICORE_INS_NOT = 282 , TRICORE_INS_ORN_T = 283 , TRICORE_INS_ORN = 284 , TRICORE_INS_OR_ANDN_T = 285 , TRICORE_INS_OR_AND_T = 286 , TRICORE_INS_OR_EQ = 287 , TRICORE_INS_OR_GE_U = 288 , TRICORE_INS_OR_GE = 289 , TRICORE_INS_OR_LT_U = 290 , TRICORE_INS_OR_LT = 291 , TRICORE_INS_OR_NE = 292 , TRICORE_INS_OR_NOR_T = 293 , TRICORE_INS_OR_OR_T = 294 , TRICORE_INS_OR_T = 295 , TRICORE_INS_OR = 296 , TRICORE_INS_PACK = 297 , TRICORE_INS_PARITY = 298 , TRICORE_INS_POPCNT_W = 299 , TRICORE_INS_Q31TOF = 300 , TRICORE_INS_QSEED_F = 301 , TRICORE_INS_RESTORE = 302 , TRICORE_INS_RET = 303 , TRICORE_INS_RFE = 304 , TRICORE_INS_RFM = 305 , TRICORE_INS_RSLCX = 306 , TRICORE_INS_RSTV = 307 , TRICORE_INS_RSUBS_U = 308 , TRICORE_INS_RSUBS = 309 , TRICORE_INS_RSUB = 310 , TRICORE_INS_SAT_BU = 311 , TRICORE_INS_SAT_B = 312 , TRICORE_INS_SAT_HU = 313 , TRICORE_INS_SAT_H = 314 , TRICORE_INS_SELN_A = 315 , TRICORE_INS_SELN = 316 , TRICORE_INS_SEL_A = 317 , TRICORE_INS_SEL = 318 , TRICORE_INS_SHAS = 319 , TRICORE_INS_SHA_B = 320 , TRICORE_INS_SHA_H = 321 , TRICORE_INS_SHA = 322 , TRICORE_INS_SHUFFLE = 323 , TRICORE_INS_SH_ANDN_T = 324 , TRICORE_INS_SH_AND_T = 325 , TRICORE_INS_SH_B = 326 , TRICORE_INS_SH_EQ = 327 , TRICORE_INS_SH_GE_U = 328 , TRICORE_INS_SH_GE = 329 , TRICORE_INS_SH_H = 330 , TRICORE_INS_SH_LT_U = 331 , TRICORE_INS_SH_LT = 332 , TRICORE_INS_SH_NAND_T = 333 , TRICORE_INS_SH_NE = 334 , TRICORE_INS_SH_NOR_T = 335 , TRICORE_INS_SH_ORN_T = 336 , TRICORE_INS_SH_OR_T = 337 , TRICORE_INS_SH_XNOR_T = 338 , TRICORE_INS_SH_XOR_T = 339 , TRICORE_INS_SH = 340 , TRICORE_INS_STLCX = 341 , TRICORE_INS_STUCX = 342 , TRICORE_INS_ST_A = 343 , TRICORE_INS_ST_B = 344 , TRICORE_INS_ST_DA = 345 , TRICORE_INS_ST_D = 346 , TRICORE_INS_ST_H = 347 , TRICORE_INS_ST_Q = 348 , TRICORE_INS_ST_T = 349 , TRICORE_INS_ST_W = 350 , TRICORE_INS_SUBC = 351 , TRICORE_INS_SUBSC_A = 352 , TRICORE_INS_SUBS_BU = 353 , TRICORE_INS_SUBS_B = 354 , TRICORE_INS_SUBS_HU = 355 , TRICORE_INS_SUBS_H = 356 , TRICORE_INS_SUBS_U = 357 , TRICORE_INS_SUBS = 358 , TRICORE_INS_SUBX = 359 , TRICORE_INS_SUB_A = 360 , TRICORE_INS_SUB_B = 361 , TRICORE_INS_SUB_F = 362 , TRICORE_INS_SUB_H = 363 , TRICORE_INS_SUB = 364 , TRICORE_INS_SVLCX = 365 , TRICORE_INS_SWAPMSK_W = 366 , TRICORE_INS_SWAP_A = 367 , TRICORE_INS_SWAP_W = 368 , TRICORE_INS_SYSCALL = 369 , TRICORE_INS_TLBDEMAP = 370 , TRICORE_INS_TLBFLUSH_A = 371 , TRICORE_INS_TLBFLUSH_B = 372 , TRICORE_INS_TLBMAP = 373 , TRICORE_INS_TLBPROBE_A = 374 , TRICORE_INS_TLBPROBE_I = 375 , TRICORE_INS_TRAPSV = 376 , TRICORE_INS_TRAPV = 377 , TRICORE_INS_UNPACK = 378 , TRICORE_INS_UPDFL = 379 , TRICORE_INS_UTOF = 380 , TRICORE_INS_WAIT = 381 , TRICORE_INS_XNOR_T = 382 , TRICORE_INS_XNOR = 383 , TRICORE_INS_XOR_EQ = 384 , TRICORE_INS_XOR_GE_U = 385 , TRICORE_INS_XOR_GE = 386 , TRICORE_INS_XOR_LT_U = 387 , TRICORE_INS_XOR_LT = 388 , TRICORE_INS_XOR_NE = 389 , TRICORE_INS_XOR = 390 , TRICORE_INS_ENDING = 391 , } # [repr (u32)] # [doc = " Group of TriCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn_group { # [doc = "< = CS_GRP_INVALID"] TRICORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_CALL"] TRICORE_GRP_CALL = 1 , # [doc = "< = CS_GRP_JUMP"] TRICORE_GRP_JUMP = 2 , # [doc = "< mark the end of the list of groups"] TRICORE_GRP_ENDING = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_feature_t { TRICORE_FEATURE_INVALID = 0 , TRICORE_FEATURE_HasV110 = 128 , TRICORE_FEATURE_HasV120_UP = 129 , TRICORE_FEATURE_HasV130_UP = 130 , TRICORE_FEATURE_HasV161 = 131 , TRICORE_FEATURE_HasV160_UP = 132 , TRICORE_FEATURE_HasV131_UP = 133 , TRICORE_FEATURE_HasV161_UP = 134 , TRICORE_FEATURE_HasV162 = 135 , TRICORE_FEATURE_HasV162_UP = 136 , # [doc = "< mark the end of the list of features"] TRICORE_FEATURE_ENDING = 137 , } pub use self :: tricore_feature_t as tricore_feature ; # [doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_detail { pub regs_read : [u16 ; 20usize] , # [doc = "< number of implicit registers read by this insn"] pub regs_read_count : u8 , pub regs_write : [u16 ; 20usize] , # [doc = "< number of implicit registers modified by this insn"] pub regs_write_count : u8 , # [doc = "< list of group this instruction belong to"] pub groups : [u8 ; 8usize] , # [doc = "< number of groups this insn belongs to"] pub groups_count : u8 , # [doc = "< Instruction has writeback operands."] pub writeback : bool , pub __bindgen_anon_1 : cs_detail__bindgen_ty_1 , } # [doc = " Architecture-specific instruction info"] # [repr (C)] # [derive (Copy , Clone)] pub union cs_detail__bindgen_ty_1 { # [doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"] pub x86 : cs_x86 , # [doc = "< ARM64 architecture (aka AArch64)"] pub arm64 : cs_arm64 , # [doc = "< ARM architecture (including Thumb/Thumb2)"] pub arm : cs_arm , # [doc = "< M68K architecture"] pub m68k : cs_m68k , # [doc = "< MIPS architecture"] pub mips : cs_mips , # [doc = "< PowerPC architecture"] pub ppc : cs_ppc , # [doc = "< Sparc architecture"] pub sparc : cs_sparc , # [doc = "< SystemZ architecture"] pub sysz : cs_sysz , # [doc = "< XCore architecture"] pub xcore : cs_xcore , # [doc = "< TMS320C64x architecture"] pub tms320c64x : cs_tms320c64x , # [doc = "< M680X architecture"] pub m680x : cs_m680x , # [doc = "< Ethereum architecture"] pub evm : cs_evm , # [doc = "< MOS65XX architecture (including MOS6502)"] pub mos65xx : cs_mos65xx , # [doc = "< Web Assembly architecture"] pub wasm : cs_wasm , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] pub bpf : cs_bpf , # [doc = "< RISCV architecture"] pub riscv : cs_riscv , # [doc = "< SH architecture"] pub sh : cs_sh , # [doc = "< TriCore architecture"] pub tricore : cs_tricore , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_detail__bindgen_ty_1 > () - 1768usize] ; ["Alignment of cs_detail__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_detail__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_detail__bindgen_ty_1::x86"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , x86) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm64"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm64) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m68k"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m68k) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mips"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mips) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::ppc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , ppc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sparc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sparc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sysz"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sysz) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::xcore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , xcore) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tms320c64x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tms320c64x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m680x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m680x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::evm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , evm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mos65xx"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mos65xx) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::wasm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , wasm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::bpf"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , bpf) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::riscv"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , riscv) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sh"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sh) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tricore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tricore) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_detail__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail"] [:: std :: mem :: size_of :: < cs_detail > () - 1864usize] ; ["Alignment of cs_detail"] [:: std :: mem :: align_of :: < cs_detail > () - 8usize] ; ["Offset of field: cs_detail::regs_read"] [:: std :: mem :: offset_of ! (cs_detail , regs_read) - 0usize] ; ["Offset of field: cs_detail::regs_read_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_read_count) - 40usize] ; ["Offset of field: cs_detail::regs_write"] [:: std :: mem :: offset_of ! (cs_detail , regs_write) - 42usize] ; ["Offset of field: cs_detail::regs_write_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_write_count) - 82usize] ; ["Offset of field: cs_detail::groups"] [:: std :: mem :: offset_of ! (cs_detail , groups) - 83usize] ; ["Offset of field: cs_detail::groups_count"] [:: std :: mem :: offset_of ! (cs_detail , groups_count) - 91usize] ; ["Offset of field: cs_detail::writeback"] [:: std :: mem :: offset_of ! (cs_detail , writeback) - 92usize] ; } ; impl :: std :: fmt :: Debug for cs_detail { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, writeback: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . writeback , self . __bindgen_anon_1) } } # [doc = " Detail information of disassembled instruction"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_insn { # [doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub address : u64 , # [doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub size : u16 , # [doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub bytes : [u8 ; 24usize] , # [doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub mnemonic : [:: std :: os :: raw :: c_char ; 32usize] , # [doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub op_str : [:: std :: os :: raw :: c_char ; 160usize] , # [doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."] pub detail : * mut cs_detail , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_insn"] [:: std :: mem :: size_of :: < cs_insn > () - 248usize] ; ["Alignment of cs_insn"] [:: std :: mem :: align_of :: < cs_insn > () - 8usize] ; ["Offset of field: cs_insn::id"] [:: std :: mem :: offset_of ! (cs_insn , id) - 0usize] ; ["Offset of field: cs_insn::address"] [:: std :: mem :: offset_of ! (cs_insn , address) - 8usize] ; ["Offset of field: cs_insn::size"] [:: std :: mem :: offset_of ! (cs_insn , size) - 16usize] ; ["Offset of field: cs_insn::bytes"] [:: std :: mem :: offset_of ! (cs_insn , bytes) - 18usize] ; ["Offset of field: cs_insn::mnemonic"] [:: std :: mem :: offset_of ! (cs_insn , mnemonic) - 42usize] ; ["Offset of field: cs_insn::op_str"] [:: std :: mem :: offset_of ! (cs_insn , op_str) - 74usize] ; ["Offset of field: cs_insn::detail"] [:: std :: mem :: offset_of ! (cs_insn , detail) - 240usize] ; } ; # [repr (u32)] # [doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_err { # [doc = "< No error: everything was fine"] CS_ERR_OK = 0 , # [doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"] CS_ERR_MEM = 1 , # [doc = "< Unsupported architecture: cs_open()"] CS_ERR_ARCH = 2 , # [doc = "< Invalid handle: cs_op_count(), cs_op_index()"] CS_ERR_HANDLE = 3 , # [doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"] CS_ERR_CSH = 4 , # [doc = "< Invalid/unsupported mode: cs_open()"] CS_ERR_MODE = 5 , # [doc = "< Invalid/unsupported option: cs_option()"] CS_ERR_OPTION = 6 , # [doc = "< Information is unavailable because detail option is OFF"] CS_ERR_DETAIL = 7 , # [doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"] CS_ERR_MEMSETUP = 8 , # [doc = "< Unsupported version (bindings)"] CS_ERR_VERSION = 9 , # [doc = "< Access irrelevant data in \"diet\" engine"] CS_ERR_DIET = 10 , # [doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"] CS_ERR_SKIPDATA = 11 , # [doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_ATT = 12 , # [doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_INTEL = 13 , # [doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_MASM = 14 , } unsafe extern "C" { # [doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."] pub fn cs_version (major : * mut :: std :: os :: raw :: c_int , minor : * mut :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_uint ; } unsafe extern "C" { # [doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."] pub fn cs_support (query : :: std :: os :: raw :: c_int) -> bool ; } unsafe extern "C" { # [doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_open (arch : cs_arch , mode : cs_mode , handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_close (handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"] pub fn cs_option (handle : csh , type_ : cs_opt_type , value : usize) -> cs_err ; } unsafe extern "C" { # [doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"] pub fn cs_errno (handle : csh) -> cs_err ; } unsafe extern "C" { # [doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"] pub fn cs_strerror (code : cs_err) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm (handle : csh , code : * const u8 , code_size : usize , address : u64 , count : usize , insn : * mut * mut cs_insn) -> usize ; } unsafe extern "C" { # [doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."] pub fn cs_free (insn : * mut cs_insn , count : usize) ; } unsafe extern "C" { # [doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"] pub fn cs_malloc (handle : csh) -> * mut cs_insn ; } unsafe extern "C" { # [doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm_iter (handle : csh , code : * mut * const u8 , size : * mut usize , address : * mut u64 , insn : * mut cs_insn) -> bool ; } unsafe extern "C" { # [doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."] pub fn cs_reg_name (handle : csh , reg_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."] pub fn cs_insn_name (handle : csh , insn_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."] pub fn cs_group_name (handle : csh , group_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."] pub fn cs_insn_group (handle : csh , insn : * const cs_insn , group_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."] pub fn cs_reg_read (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."] pub fn cs_reg_write (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."] pub fn cs_op_count (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."] pub fn cs_op_index (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint , position : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } # [doc = " Type of array to keep the list of registers"] pub type cs_regs = [u16 ; 64usize] ; unsafe extern "C" { # [doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_regs_access (handle : csh , insn : * const cs_insn , regs_read : * mut u16 , regs_read_count : * mut u8 , regs_write : * mut u16 , regs_write_count : * mut u8) -> cs_err ; } pub type __builtin_va_list = [__va_list_tag ; 1usize] ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __va_list_tag { pub gp_offset : :: std :: os :: raw :: c_uint , pub fp_offset : :: std :: os :: raw :: c_uint , pub overflow_arg_area : * mut :: std :: os :: raw :: c_void , pub reg_save_area : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __va_list_tag"] [:: std :: mem :: size_of :: < __va_list_tag > () - 24usize] ; ["Alignment of __va_list_tag"] [:: std :: mem :: align_of :: < __va_list_tag > () - 8usize] ; ["Offset of field: __va_list_tag::gp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , gp_offset) - 0usize] ; ["Offset of field: __va_list_tag::fp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , fp_offset) - 4usize] ; ["Offset of field: __va_list_tag::overflow_arg_area"] [:: std :: mem :: offset_of ! (__va_list_tag , overflow_arg_area) - 8usize] ; ["Offset of field: __va_list_tag::reg_save_area"] [:: std :: mem :: offset_of ! (__va_list_tag , reg_save_area) - 16usize] ; } ;
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[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: unnecessary transmute
[INFO] [stdout]  --> /opt/rustwide/target/debug/build/falcon_capstone/f982cdb455ed4cf6/out/bindings.rs:3:80816
[INFO] [stdout]   |
[INFO] [stdout] 3 | ...: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > ::...
[INFO] [stdout]   |                                                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout] help: replace this with
[INFO] [stdout]   |
[INFO] [stdout] 3 - # [repr (C)] # [derive (Copy , Clone , Debug , Default , Eq , Hash , Ord , PartialEq , PartialOrd)] pub struct __BindgenBitfieldUnit < Storage > { storage : Storage , } impl < Storage > __BindgenBitfieldUnit < Storage > { # [inline] pub const fn new (storage : Storage) -> Self { Self { storage } } } impl < Storage > __BindgenBitfieldUnit < Storage > where Storage : AsRef < [u8] > + AsMut < [u8] >, { # [inline] fn extract_bit (byte : u8 , index : usize) -> bool { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; byte & mask == mask } # [inline] pub fn get_bit (& self , index : usize) -> bool { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = self . storage . as_ref () [byte_index] ; Self :: extract_bit (byte , index) } # [inline] pub unsafe fn raw_get_bit (this : * const Self , index : usize) -> bool { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { * (core :: ptr :: addr_of ! ((* this) . storage) as * const u8) . offset (byte_index as isize) } ; Self :: extract_bit (byte , index) } # [inline] fn change_bit (byte : u8 , index : usize , val : bool) -> u8 { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; if val { byte | mask } else { byte & ! mask } } # [inline] pub fn set_bit (& mut self , index : usize , val : bool) { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = & mut self . storage . as_mut () [byte_index] ; * byte = Self :: change_bit (* byte , index , val) ; } # [inline] pub unsafe fn raw_set_bit (this : * mut Self , index : usize , val : bool) { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { (core :: ptr :: addr_of_mut ! ((* this) . storage) as * mut u8) . offset (byte_index as isize) } ; unsafe { * byte = Self :: change_bit (* byte , index , val) } ; } # [inline] pub fn get (& self , bit_offset : usize , bit_width : u8) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if self . get_bit (i + bit_offset) { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub unsafe fn raw_get (this : * const Self , bit_offset : usize , bit_width : u8 ,) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if unsafe { Self :: raw_get_bit (this , i + bit_offset) } { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub fn set (& mut self , bit_offset : usize , bit_width : u8 , val : u64) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; self . set_bit (index + bit_offset , val_bit_is_set) ; } } # [inline] pub unsafe fn raw_set (this : * mut Self , bit_offset : usize , bit_width : u8 , val : u64 ,) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; unsafe { Self :: raw_set_bit (this , index + bit_offset , val_bit_is_set) } ; } } } # [derive (PartialEq , Copy , Clone , Hash , Debug , Default)] # [repr (C)] pub struct __BindgenComplex < T > { pub re : T , pub im : T } pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __GLIBC_USE_ISOC2Y : u32 = 0 ; pub const __GLIBC_USE_ISOC23 : u32 = 0 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 202405 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_XOPEN2K24 : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const __TIMESIZE : u32 = 64 ; pub const __USE_TIME_BITS64 : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_GETS : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_SCANF : u32 = 0 ; pub const __GLIBC_USE_C23_STRTOL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_60559_BFP__ : u32 = 201404 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_IEC_60559_COMPLEX__ : u32 = 201404 ; pub const __STDC_ISO_10646__ : u32 = 201706 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 43 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __glibc_c99_flexarr_available : u32 = 1 ; pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI : u32 = 0 ; pub const __HAVE_GENERIC_SELECTION : u32 = 1 ; pub const __GLIBC_USE_LIB_EXT2 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_TYPES_EXT : u32 = 0 ; pub const _STDLIB_H : u32 = 1 ; pub const WNOHANG : u32 = 1 ; pub const WUNTRACED : u32 = 2 ; pub const WSTOPPED : u32 = 2 ; pub const WEXITED : u32 = 4 ; pub const WCONTINUED : u32 = 8 ; pub const WNOWAIT : u32 = 16777216 ; pub const __WNOTHREAD : u32 = 536870912 ; pub const __WALL : u32 = 1073741824 ; pub const __WCLONE : u32 = 2147483648 ; pub const __W_CONTINUED : u32 = 65535 ; pub const __WCOREFLAG : u32 = 128 ; pub const __HAVE_FLOAT128 : u32 = 1 ; pub const __HAVE_DISTINCT_FLOAT128 : u32 = 1 ; pub const __HAVE_FLOAT64X : u32 = 1 ; pub const __HAVE_FLOAT64X_LONG_DOUBLE : u32 = 1 ; pub const __HAVE_FLOAT16 : u32 = 0 ; pub const __HAVE_FLOAT32 : u32 = 1 ; pub const __HAVE_FLOAT64 : u32 = 1 ; pub const __HAVE_FLOAT32X : u32 = 1 ; pub const __HAVE_FLOAT128X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT16 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT128X : u32 = 0 ; pub const __HAVE_FLOATN_NOT_TYPEDEF : u32 = 0 ; pub const __ldiv_t_defined : u32 = 1 ; pub const __lldiv_t_defined : u32 = 1 ; pub const RAND_MAX : u32 = 2147483647 ; pub const EXIT_FAILURE : u32 = 1 ; pub const EXIT_SUCCESS : u32 = 0 ; pub const _SYS_TYPES_H : u32 = 1 ; pub const _BITS_TYPES_H : u32 = 1 ; pub const _BITS_TYPESIZES_H : u32 = 1 ; pub const __OFF_T_MATCHES_OFF64_T : u32 = 1 ; pub const __INO_T_MATCHES_INO64_T : u32 = 1 ; pub const __RLIM_T_MATCHES_RLIM64_T : u32 = 1 ; pub const __STATFS_MATCHES_STATFS64 : u32 = 1 ; pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 : u32 = 1 ; pub const __FD_SETSIZE : u32 = 1024 ; pub const _BITS_TIME64_H : u32 = 1 ; pub const __clock_t_defined : u32 = 1 ; pub const __clockid_t_defined : u32 = 1 ; pub const __time_t_defined : u32 = 1 ; pub const __timer_t_defined : u32 = 1 ; pub const _BITS_STDINT_INTN_H : u32 = 1 ; pub const __BIT_TYPES_DEFINED__ : u32 = 1 ; pub const _ENDIAN_H : u32 = 1 ; pub const _BITS_ENDIAN_H : u32 = 1 ; pub const __LITTLE_ENDIAN : u32 = 1234 ; pub const __BIG_ENDIAN : u32 = 4321 ; pub const __PDP_ENDIAN : u32 = 3412 ; pub const _BITS_ENDIANNESS_H : u32 = 1 ; pub const __BYTE_ORDER : u32 = 1234 ; pub const __FLOAT_WORD_ORDER : u32 = 1234 ; pub const LITTLE_ENDIAN : u32 = 1234 ; pub const BIG_ENDIAN : u32 = 4321 ; pub const PDP_ENDIAN : u32 = 3412 ; pub const BYTE_ORDER : u32 = 1234 ; pub const _BITS_BYTESWAP_H : u32 = 1 ; pub const _BITS_UINTN_IDENTITY_H : u32 = 1 ; pub const _SYS_SELECT_H : u32 = 1 ; pub const __sigset_t_defined : u32 = 1 ; pub const __timeval_defined : u32 = 1 ; pub const _STRUCT_TIMESPEC : u32 = 1 ; pub const FD_SETSIZE : u32 = 1024 ; pub const _BITS_PTHREADTYPES_COMMON_H : u32 = 1 ; pub const _THREAD_SHARED_TYPES_H : u32 = 1 ; pub const _BITS_PTHREADTYPES_ARCH_H : u32 = 1 ; pub const __SIZEOF_PTHREAD_MUTEX_T : u32 = 40 ; pub const __SIZEOF_PTHREAD_ATTR_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_RWLOCK_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_BARRIER_T : u32 = 32 ; pub const __SIZEOF_PTHREAD_MUTEXATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_COND_T : u32 = 48 ; pub const __SIZEOF_PTHREAD_CONDATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_RWLOCKATTR_T : u32 = 8 ; pub const __SIZEOF_PTHREAD_BARRIERATTR_T : u32 = 4 ; pub const _THREAD_MUTEX_INTERNAL_H : u32 = 1 ; pub const __PTHREAD_MUTEX_HAVE_PREV : u32 = 1 ; pub const __have_pthread_attr_t : u32 = 1 ; pub const _ALLOCA_H : u32 = 1 ; pub const _STDIO_H : u32 = 1 ; pub const _____fpos_t_defined : u32 = 1 ; pub const ____mbstate_t_defined : u32 = 1 ; pub const _____fpos64_t_defined : u32 = 1 ; pub const ____FILE_defined : u32 = 1 ; pub const __FILE_defined : u32 = 1 ; pub const __struct_FILE_defined : u32 = 1 ; pub const _IO_EOF_SEEN : u32 = 16 ; pub const _IO_ERR_SEEN : u32 = 32 ; pub const _IO_USER_LOCK : u32 = 32768 ; pub const __cookie_io_functions_t_defined : u32 = 1 ; pub const _IOFBF : u32 = 0 ; pub const _IOLBF : u32 = 1 ; pub const _IONBF : u32 = 2 ; pub const BUFSIZ : u32 = 8192 ; pub const EOF : i32 = - 1 ; pub const SEEK_SET : u32 = 0 ; pub const SEEK_CUR : u32 = 1 ; pub const SEEK_END : u32 = 2 ; pub const P_tmpdir : & [u8 ; 5] = b"/tmp\0" ; pub const L_tmpnam : u32 = 20 ; pub const TMP_MAX : u32 = 238328 ; pub const _BITS_STDIO_LIM_H : u32 = 1 ; pub const FILENAME_MAX : u32 = 4096 ; pub const L_ctermid : u32 = 9 ; pub const FOPEN_MAX : u32 = 16 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const _INTTYPES_H : u32 = 1 ; pub const _STDINT_H : u32 = 1 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const _BITS_STDINT_UINTN_H : u32 = 1 ; pub const _BITS_STDINT_LEAST_H : u32 = 1 ; pub const INT8_MIN : i32 = - 128 ; pub const INT16_MIN : i32 = - 32768 ; pub const INT32_MIN : i32 = - 2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = - 128 ; pub const INT_LEAST16_MIN : i32 = - 32768 ; pub const INT_LEAST32_MIN : i32 = - 2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = - 128 ; pub const INT_FAST16_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST32_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = - 1 ; pub const UINT_FAST32_MAX : i32 = - 1 ; pub const INTPTR_MIN : i64 = - 9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = - 1 ; pub const PTRDIFF_MIN : i64 = - 9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = - 2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = - 1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const ____gwchar_t_defined : u32 = 1 ; pub const __PRI64_PREFIX : & [u8 ; 2] = b"l\0" ; pub const __PRIPTR_PREFIX : & [u8 ; 2] = b"l\0" ; pub const PRId8 : & [u8 ; 4] = b"hhd\0" ; pub const PRId16 : & [u8 ; 3] = b"hd\0" ; pub const PRId32 : & [u8 ; 2] = b"d\0" ; pub const PRId64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const PRIdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const PRIdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIi8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIi16 : & [u8 ; 3] = b"hi\0" ; pub const PRIi32 : & [u8 ; 2] = b"i\0" ; pub const PRIi64 : & [u8 ; 3] = b"li\0" ; pub const PRIiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const PRIiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const PRIiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiFAST16 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST32 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIo8 : & [u8 ; 4] = b"hho\0" ; pub const PRIo16 : & [u8 ; 3] = b"ho\0" ; pub const PRIo32 : & [u8 ; 2] = b"o\0" ; pub const PRIo64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const PRIoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const PRIoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIu8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIu16 : & [u8 ; 3] = b"hu\0" ; pub const PRIu32 : & [u8 ; 2] = b"u\0" ; pub const PRIu64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const PRIuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const PRIuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIx8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIx16 : & [u8 ; 3] = b"hx\0" ; pub const PRIx32 : & [u8 ; 2] = b"x\0" ; pub const PRIx64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const PRIxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const PRIxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIX8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIX16 : & [u8 ; 3] = b"hX\0" ; pub const PRIX32 : & [u8 ; 2] = b"X\0" ; pub const PRIX64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXLEAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXLEAST16 : & [u8 ; 3] = b"hX\0" ; pub const PRIXLEAST32 : & [u8 ; 2] = b"X\0" ; pub const PRIXLEAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXFAST16 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST32 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIdMAX : & [u8 ; 3] = b"ld\0" ; pub const PRIiMAX : & [u8 ; 3] = b"li\0" ; pub const PRIoMAX : & [u8 ; 3] = b"lo\0" ; pub const PRIuMAX : & [u8 ; 3] = b"lu\0" ; pub const PRIxMAX : & [u8 ; 3] = b"lx\0" ; pub const PRIXMAX : & [u8 ; 3] = b"lX\0" ; pub const PRIdPTR : & [u8 ; 3] = b"ld\0" ; pub const PRIiPTR : & [u8 ; 3] = b"li\0" ; pub const PRIoPTR : & [u8 ; 3] = b"lo\0" ; pub const PRIuPTR : & [u8 ; 3] = b"lu\0" ; pub const PRIxPTR : & [u8 ; 3] = b"lx\0" ; pub const PRIXPTR : & [u8 ; 3] = b"lX\0" ; pub const SCNd8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNd16 : & [u8 ; 3] = b"hd\0" ; pub const SCNd32 : & [u8 ; 2] = b"d\0" ; pub const SCNd64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const SCNdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const SCNdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNi8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNi16 : & [u8 ; 3] = b"hi\0" ; pub const SCNi32 : & [u8 ; 2] = b"i\0" ; pub const SCNi64 : & [u8 ; 3] = b"li\0" ; pub const SCNiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const SCNiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const SCNiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiFAST16 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST32 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNu8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNu16 : & [u8 ; 3] = b"hu\0" ; pub const SCNu32 : & [u8 ; 2] = b"u\0" ; pub const SCNu64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const SCNuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const SCNuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNo8 : & [u8 ; 4] = b"hho\0" ; pub const SCNo16 : & [u8 ; 3] = b"ho\0" ; pub const SCNo32 : & [u8 ; 2] = b"o\0" ; pub const SCNo64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const SCNoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const SCNoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNx8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNx16 : & [u8 ; 3] = b"hx\0" ; pub const SCNx32 : & [u8 ; 2] = b"x\0" ; pub const SCNx64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const SCNxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const SCNxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNdMAX : & [u8 ; 3] = b"ld\0" ; pub const SCNiMAX : & [u8 ; 3] = b"li\0" ; pub const SCNoMAX : & [u8 ; 3] = b"lo\0" ; pub const SCNuMAX : & [u8 ; 3] = b"lu\0" ; pub const SCNxMAX : & [u8 ; 3] = b"lx\0" ; pub const SCNdPTR : & [u8 ; 3] = b"ld\0" ; pub const SCNiPTR : & [u8 ; 3] = b"li\0" ; pub const SCNoPTR : & [u8 ; 3] = b"lo\0" ; pub const SCNuPTR : & [u8 ; 3] = b"lu\0" ; pub const SCNxPTR : & [u8 ; 3] = b"lx\0" ; pub const CS_API_MAJOR : u32 = 5 ; pub const CS_API_MINOR : u32 = 0 ; pub const CS_NEXT_VERSION : u32 = 5 ; pub const CS_VERSION_MAJOR : u32 = 5 ; pub const CS_VERSION_MINOR : u32 = 0 ; pub const CS_VERSION_EXTRA : u32 = 7 ; pub const CS_MNEMONIC_SIZE : u32 = 32 ; pub const M68K_OPERAND_COUNT : u32 = 4 ; pub const X86_EFLAGS_MODIFY_AF : u32 = 1 ; pub const X86_EFLAGS_MODIFY_CF : u32 = 2 ; pub const X86_EFLAGS_MODIFY_SF : u32 = 4 ; pub const X86_EFLAGS_MODIFY_ZF : u32 = 8 ; pub const X86_EFLAGS_MODIFY_PF : u32 = 16 ; pub const X86_EFLAGS_MODIFY_OF : u32 = 32 ; pub const X86_EFLAGS_MODIFY_TF : u32 = 64 ; pub const X86_EFLAGS_MODIFY_IF : u32 = 128 ; pub const X86_EFLAGS_MODIFY_DF : u32 = 256 ; pub const X86_EFLAGS_MODIFY_NT : u32 = 512 ; pub const X86_EFLAGS_MODIFY_RF : u32 = 1024 ; pub const X86_EFLAGS_PRIOR_OF : u32 = 2048 ; pub const X86_EFLAGS_PRIOR_SF : u32 = 4096 ; pub const X86_EFLAGS_PRIOR_ZF : u32 = 8192 ; pub const X86_EFLAGS_PRIOR_AF : u32 = 16384 ; pub const X86_EFLAGS_PRIOR_PF : u32 = 32768 ; pub const X86_EFLAGS_PRIOR_CF : u32 = 65536 ; pub const X86_EFLAGS_PRIOR_TF : u32 = 131072 ; pub const X86_EFLAGS_PRIOR_IF : u32 = 262144 ; pub const X86_EFLAGS_PRIOR_DF : u32 = 524288 ; pub const X86_EFLAGS_PRIOR_NT : u32 = 1048576 ; pub const X86_EFLAGS_RESET_OF : u32 = 2097152 ; pub const X86_EFLAGS_RESET_CF : u32 = 4194304 ; pub const X86_EFLAGS_RESET_DF : u32 = 8388608 ; pub const X86_EFLAGS_RESET_IF : u32 = 16777216 ; pub const X86_EFLAGS_RESET_SF : u32 = 33554432 ; pub const X86_EFLAGS_RESET_AF : u32 = 67108864 ; pub const X86_EFLAGS_RESET_TF : u32 = 134217728 ; pub const X86_EFLAGS_RESET_NT : u32 = 268435456 ; pub const X86_EFLAGS_RESET_PF : u32 = 536870912 ; pub const X86_EFLAGS_SET_CF : u32 = 1073741824 ; pub const X86_EFLAGS_SET_DF : u32 = 2147483648 ; pub const X86_EFLAGS_SET_IF : u64 = 4294967296 ; pub const X86_EFLAGS_TEST_OF : u64 = 8589934592 ; pub const X86_EFLAGS_TEST_SF : u64 = 17179869184 ; pub const X86_EFLAGS_TEST_ZF : u64 = 34359738368 ; pub const X86_EFLAGS_TEST_PF : u64 = 68719476736 ; pub const X86_EFLAGS_TEST_CF : u64 = 137438953472 ; pub const X86_EFLAGS_TEST_NT : u64 = 274877906944 ; pub const X86_EFLAGS_TEST_DF : u64 = 549755813888 ; pub const X86_EFLAGS_UNDEFINED_OF : u64 = 1099511627776 ; pub const X86_EFLAGS_UNDEFINED_SF : u64 = 2199023255552 ; pub const X86_EFLAGS_UNDEFINED_ZF : u64 = 4398046511104 ; pub const X86_EFLAGS_UNDEFINED_PF : u64 = 8796093022208 ; pub const X86_EFLAGS_UNDEFINED_AF : u64 = 17592186044416 ; pub const X86_EFLAGS_UNDEFINED_CF : u64 = 35184372088832 ; pub const X86_EFLAGS_RESET_RF : u64 = 70368744177664 ; pub const X86_EFLAGS_TEST_RF : u64 = 140737488355328 ; pub const X86_EFLAGS_TEST_IF : u64 = 281474976710656 ; pub const X86_EFLAGS_TEST_TF : u64 = 562949953421312 ; pub const X86_EFLAGS_TEST_AF : u64 = 1125899906842624 ; pub const X86_EFLAGS_RESET_ZF : u64 = 2251799813685248 ; pub const X86_EFLAGS_SET_OF : u64 = 4503599627370496 ; pub const X86_EFLAGS_SET_SF : u64 = 9007199254740992 ; pub const X86_EFLAGS_SET_ZF : u64 = 18014398509481984 ; pub const X86_EFLAGS_SET_AF : u64 = 36028797018963968 ; pub const X86_EFLAGS_SET_PF : u64 = 72057594037927936 ; pub const X86_EFLAGS_RESET_0F : u64 = 144115188075855872 ; pub const X86_EFLAGS_RESET_AC : u64 = 288230376151711744 ; pub const X86_FPU_FLAGS_MODIFY_C0 : u32 = 1 ; pub const X86_FPU_FLAGS_MODIFY_C1 : u32 = 2 ; pub const X86_FPU_FLAGS_MODIFY_C2 : u32 = 4 ; pub const X86_FPU_FLAGS_MODIFY_C3 : u32 = 8 ; pub const X86_FPU_FLAGS_RESET_C0 : u32 = 16 ; pub const X86_FPU_FLAGS_RESET_C1 : u32 = 32 ; pub const X86_FPU_FLAGS_RESET_C2 : u32 = 64 ; pub const X86_FPU_FLAGS_RESET_C3 : u32 = 128 ; pub const X86_FPU_FLAGS_SET_C0 : u32 = 256 ; pub const X86_FPU_FLAGS_SET_C1 : u32 = 512 ; pub const X86_FPU_FLAGS_SET_C2 : u32 = 1024 ; pub const X86_FPU_FLAGS_SET_C3 : u32 = 2048 ; pub const X86_FPU_FLAGS_UNDEFINED_C0 : u32 = 4096 ; pub const X86_FPU_FLAGS_UNDEFINED_C1 : u32 = 8192 ; pub const X86_FPU_FLAGS_UNDEFINED_C2 : u32 = 16384 ; pub const X86_FPU_FLAGS_UNDEFINED_C3 : u32 = 32768 ; pub const X86_FPU_FLAGS_TEST_C0 : u32 = 65536 ; pub const X86_FPU_FLAGS_TEST_C1 : u32 = 131072 ; pub const X86_FPU_FLAGS_TEST_C2 : u32 = 262144 ; pub const X86_FPU_FLAGS_TEST_C3 : u32 = 524288 ; pub const M680X_OPERAND_COUNT : u32 = 9 ; pub const M680X_OFFSET_NONE : u32 = 0 ; pub const M680X_OFFSET_BITS_5 : u32 = 5 ; pub const M680X_OFFSET_BITS_8 : u32 = 8 ; pub const M680X_OFFSET_BITS_9 : u32 = 9 ; pub const M680X_OFFSET_BITS_16 : u32 = 16 ; pub const M680X_IDX_INDIRECT : u32 = 1 ; pub const M680X_IDX_NO_COMMA : u32 = 2 ; pub const M680X_IDX_POST_INC_DEC : u32 = 4 ; pub const M680X_FIRST_OP_IN_MNEM : u32 = 1 ; pub const M680X_SECOND_OP_IN_MNEM : u32 = 2 ; pub const TRICORE_OP_COUNT : u32 = 8 ; pub const MAX_IMPL_W_REGS : u32 = 20 ; pub const MAX_IMPL_R_REGS : u32 = 20 ; pub const MAX_NUM_GROUPS : u32 = 8 ; pub type __gnuc_va_list = __builtin_va_list ; pub type va_list = __builtin_va_list ; pub type wchar_t = :: std :: os :: raw :: c_int ; pub type __cfloat128 = __BindgenComplex < u128 > ; pub type _Float128 = u128 ; pub type _Float32 = f32 ; pub type _Float64 = f64 ; pub type _Float32x = f64 ; pub type _Float64x = u128 ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct div_t { pub quot : :: std :: os :: raw :: c_int , pub rem : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of div_t"] [:: std :: mem :: size_of :: < div_t > () - 8usize] ; ["Alignment of div_t"] [:: std :: mem :: align_of :: < div_t > () - 4usize] ; ["Offset of field: div_t::quot"] [:: std :: mem :: offset_of ! (div_t , quot) - 0usize] ; ["Offset of field: div_t::rem"] [:: std :: mem :: offset_of ! (div_t , rem) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ldiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ldiv_t"] [:: std :: mem :: size_of :: < ldiv_t > () - 16usize] ; ["Alignment of ldiv_t"] [:: std :: mem :: align_of :: < ldiv_t > () - 8usize] ; ["Offset of field: ldiv_t::quot"] [:: std :: mem :: offset_of ! (ldiv_t , quot) - 0usize] ; ["Offset of field: ldiv_t::rem"] [:: std :: mem :: offset_of ! (ldiv_t , rem) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct lldiv_t { pub quot : :: std :: os :: raw :: c_longlong , pub rem : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of lldiv_t"] [:: std :: mem :: size_of :: < lldiv_t > () - 16usize] ; ["Alignment of lldiv_t"] [:: std :: mem :: align_of :: < lldiv_t > () - 8usize] ; ["Offset of field: lldiv_t::quot"] [:: std :: mem :: offset_of ! (lldiv_t , quot) - 0usize] ; ["Offset of field: lldiv_t::rem"] [:: std :: mem :: offset_of ! (lldiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn __ctype_get_mb_cur_max () -> usize ; } unsafe extern "C" { pub fn atof (__nptr : * const :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn atoi (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn atol (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn atoll (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtod (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn strtof (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f32 ; } unsafe extern "C" { pub fn strtold (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> u128 ; } unsafe extern "C" { pub fn strtol (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn strtoul (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn strtoq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtouq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn strtoll (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtoull (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn l64a (__n : :: std :: os :: raw :: c_long) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn a64l (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } pub type __u_char = :: std :: os :: raw :: c_uchar ; pub type __u_short = :: std :: os :: raw :: c_ushort ; pub type __u_int = :: std :: os :: raw :: c_uint ; pub type __u_long = :: std :: os :: raw :: c_ulong ; pub type __int8_t = :: std :: os :: raw :: c_schar ; pub type __uint8_t = :: std :: os :: raw :: c_uchar ; pub type __int16_t = :: std :: os :: raw :: c_short ; pub type __uint16_t = :: std :: os :: raw :: c_ushort ; pub type __int32_t = :: std :: os :: raw :: c_int ; pub type __uint32_t = :: std :: os :: raw :: c_uint ; pub type __int64_t = :: std :: os :: raw :: c_long ; pub type __uint64_t = :: std :: os :: raw :: c_ulong ; pub type __int_least8_t = __int8_t ; pub type __uint_least8_t = __uint8_t ; pub type __int_least16_t = __int16_t ; pub type __uint_least16_t = __uint16_t ; pub type __int_least32_t = __int32_t ; pub type __uint_least32_t = __uint32_t ; pub type __int_least64_t = __int64_t ; pub type __uint_least64_t = __uint64_t ; pub type __quad_t = :: std :: os :: raw :: c_long ; pub type __u_quad_t = :: std :: os :: raw :: c_ulong ; pub type __intmax_t = :: std :: os :: raw :: c_long ; pub type __uintmax_t = :: std :: os :: raw :: c_ulong ; pub type __dev_t = :: std :: os :: raw :: c_ulong ; pub type __uid_t = :: std :: os :: raw :: c_uint ; pub type __gid_t = :: std :: os :: raw :: c_uint ; pub type __ino_t = :: std :: os :: raw :: c_ulong ; pub type __ino64_t = :: std :: os :: raw :: c_ulong ; pub type __mode_t = :: std :: os :: raw :: c_uint ; pub type __nlink_t = :: std :: os :: raw :: c_ulong ; pub type __off_t = :: std :: os :: raw :: c_long ; pub type __off64_t = :: std :: os :: raw :: c_long ; pub type __pid_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __fsid_t { pub __val : [:: std :: os :: raw :: c_int ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __fsid_t"] [:: std :: mem :: size_of :: < __fsid_t > () - 8usize] ; ["Alignment of __fsid_t"] [:: std :: mem :: align_of :: < __fsid_t > () - 4usize] ; ["Offset of field: __fsid_t::__val"] [:: std :: mem :: offset_of ! (__fsid_t , __val) - 0usize] ; } ; pub type __clock_t = :: std :: os :: raw :: c_long ; pub type __rlim_t = :: std :: os :: raw :: c_ulong ; pub type __rlim64_t = :: std :: os :: raw :: c_ulong ; pub type __id_t = :: std :: os :: raw :: c_uint ; pub type __time_t = :: std :: os :: raw :: c_long ; pub type __useconds_t = :: std :: os :: raw :: c_uint ; pub type __suseconds_t = :: std :: os :: raw :: c_long ; pub type __suseconds64_t = :: std :: os :: raw :: c_long ; pub type __daddr_t = :: std :: os :: raw :: c_int ; pub type __key_t = :: std :: os :: raw :: c_int ; pub type __clockid_t = :: std :: os :: raw :: c_int ; pub type __timer_t = * mut :: std :: os :: raw :: c_void ; pub type __blksize_t = :: std :: os :: raw :: c_long ; pub type __blkcnt_t = :: std :: os :: raw :: c_long ; pub type __blkcnt64_t = :: std :: os :: raw :: c_long ; pub type __fsblkcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsblkcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsword_t = :: std :: os :: raw :: c_long ; pub type __ssize_t = :: std :: os :: raw :: c_long ; pub type __syscall_slong_t = :: std :: os :: raw :: c_long ; pub type __syscall_ulong_t = :: std :: os :: raw :: c_ulong ; pub type __loff_t = __off64_t ; pub type __caddr_t = * mut :: std :: os :: raw :: c_char ; pub type __intptr_t = :: std :: os :: raw :: c_long ; pub type __socklen_t = :: std :: os :: raw :: c_uint ; pub type __sig_atomic_t = :: std :: os :: raw :: c_int ; pub type u_char = __u_char ; pub type u_short = __u_short ; pub type u_int = __u_int ; pub type u_long = __u_long ; pub type quad_t = __quad_t ; pub type u_quad_t = __u_quad_t ; pub type fsid_t = __fsid_t ; pub type loff_t = __loff_t ; pub type ino_t = __ino_t ; pub type dev_t = __dev_t ; pub type gid_t = __gid_t ; pub type mode_t = __mode_t ; pub type nlink_t = __nlink_t ; pub type uid_t = __uid_t ; pub type off_t = __off_t ; pub type pid_t = __pid_t ; pub type id_t = __id_t ; pub type daddr_t = __daddr_t ; pub type caddr_t = __caddr_t ; pub type key_t = __key_t ; pub type clock_t = __clock_t ; pub type clockid_t = __clockid_t ; pub type time_t = __time_t ; pub type timer_t = __timer_t ; pub type ulong = :: std :: os :: raw :: c_ulong ; pub type ushort = :: std :: os :: raw :: c_ushort ; pub type uint = :: std :: os :: raw :: c_uint ; pub type u_int8_t = __uint8_t ; pub type u_int16_t = __uint16_t ; pub type u_int32_t = __uint32_t ; pub type u_int64_t = __uint64_t ; pub type register_t = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __sigset_t { pub __val : [:: std :: os :: raw :: c_ulong ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __sigset_t"] [:: std :: mem :: size_of :: < __sigset_t > () - 128usize] ; ["Alignment of __sigset_t"] [:: std :: mem :: align_of :: < __sigset_t > () - 8usize] ; ["Offset of field: __sigset_t::__val"] [:: std :: mem :: offset_of ! (__sigset_t , __val) - 0usize] ; } ; pub type sigset_t = __sigset_t ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timeval { pub tv_sec : __time_t , pub tv_usec : __suseconds_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timeval"] [:: std :: mem :: size_of :: < timeval > () - 16usize] ; ["Alignment of timeval"] [:: std :: mem :: align_of :: < timeval > () - 8usize] ; ["Offset of field: timeval::tv_sec"] [:: std :: mem :: offset_of ! (timeval , tv_sec) - 0usize] ; ["Offset of field: timeval::tv_usec"] [:: std :: mem :: offset_of ! (timeval , tv_usec) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timespec { pub tv_sec : __time_t , pub tv_nsec : __syscall_slong_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timespec"] [:: std :: mem :: size_of :: < timespec > () - 16usize] ; ["Alignment of timespec"] [:: std :: mem :: align_of :: < timespec > () - 8usize] ; ["Offset of field: timespec::tv_sec"] [:: std :: mem :: offset_of ! (timespec , tv_sec) - 0usize] ; ["Offset of field: timespec::tv_nsec"] [:: std :: mem :: offset_of ! (timespec , tv_nsec) - 8usize] ; } ; pub type suseconds_t = __suseconds_t ; pub type __fd_mask = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct fd_set { pub __fds_bits : [__fd_mask ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of fd_set"] [:: std :: mem :: size_of :: < fd_set > () - 128usize] ; ["Alignment of fd_set"] [:: std :: mem :: align_of :: < fd_set > () - 8usize] ; ["Offset of field: fd_set::__fds_bits"] [:: std :: mem :: offset_of ! (fd_set , __fds_bits) - 0usize] ; } ; pub type fd_mask = __fd_mask ; unsafe extern "C" { pub fn select (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * mut timeval) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pselect (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * const timespec , __sigmask : * const __sigset_t) -> :: std :: os :: raw :: c_int ; } pub type blksize_t = __blksize_t ; pub type blkcnt_t = __blkcnt_t ; pub type fsblkcnt_t = __fsblkcnt_t ; pub type fsfilcnt_t = __fsfilcnt_t ; # [repr (C)] # [derive (Copy , Clone)] pub union __atomic_wide_counter { pub __value64 : :: std :: os :: raw :: c_ulonglong , pub __value32 : __atomic_wide_counter__bindgen_ty_1 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __atomic_wide_counter__bindgen_ty_1 { pub __low : :: std :: os :: raw :: c_uint , pub __high : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: size_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 8usize] ; ["Alignment of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: align_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__low"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __low) - 0usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__high"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __high) - 4usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter"] [:: std :: mem :: size_of :: < __atomic_wide_counter > () - 8usize] ; ["Alignment of __atomic_wide_counter"] [:: std :: mem :: align_of :: < __atomic_wide_counter > () - 8usize] ; ["Offset of field: __atomic_wide_counter::__value64"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value64) - 0usize] ; ["Offset of field: __atomic_wide_counter::__value32"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value32) - 0usize] ; } ; impl :: std :: fmt :: Debug for __atomic_wide_counter { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__atomic_wide_counter {{ union }}") } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_list { pub __prev : * mut __pthread_internal_list , pub __next : * mut __pthread_internal_list , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_list"] [:: std :: mem :: size_of :: < __pthread_internal_list > () - 16usize] ; ["Alignment of __pthread_internal_list"] [:: std :: mem :: align_of :: < __pthread_internal_list > () - 8usize] ; ["Offset of field: __pthread_internal_list::__prev"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __prev) - 0usize] ; ["Offset of field: __pthread_internal_list::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __next) - 8usize] ; } ; pub type __pthread_list_t = __pthread_internal_list ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_slist { pub __next : * mut __pthread_internal_slist , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_slist"] [:: std :: mem :: size_of :: < __pthread_internal_slist > () - 8usize] ; ["Alignment of __pthread_internal_slist"] [:: std :: mem :: align_of :: < __pthread_internal_slist > () - 8usize] ; ["Offset of field: __pthread_internal_slist::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_slist , __next) - 0usize] ; } ; pub type __pthread_slist_t = __pthread_internal_slist ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_mutex_s { pub __lock : :: std :: os :: raw :: c_int , pub __count : :: std :: os :: raw :: c_uint , pub __owner : :: std :: os :: raw :: c_int , pub __nusers : :: std :: os :: raw :: c_uint , pub __kind : :: std :: os :: raw :: c_int , pub __spins : :: std :: os :: raw :: c_short , pub __unused : :: std :: os :: raw :: c_short , pub __list : __pthread_list_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_mutex_s"] [:: std :: mem :: size_of :: < __pthread_mutex_s > () - 40usize] ; ["Alignment of __pthread_mutex_s"] [:: std :: mem :: align_of :: < __pthread_mutex_s > () - 8usize] ; ["Offset of field: __pthread_mutex_s::__lock"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __lock) - 0usize] ; ["Offset of field: __pthread_mutex_s::__count"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __count) - 4usize] ; ["Offset of field: __pthread_mutex_s::__owner"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __owner) - 8usize] ; ["Offset of field: __pthread_mutex_s::__nusers"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __nusers) - 12usize] ; ["Offset of field: __pthread_mutex_s::__kind"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __kind) - 16usize] ; ["Offset of field: __pthread_mutex_s::__spins"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __spins) - 20usize] ; ["Offset of field: __pthread_mutex_s::__unused"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __unused) - 22usize] ; ["Offset of field: __pthread_mutex_s::__list"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __list) - 24usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_rwlock_arch_t { pub __readers : :: std :: os :: raw :: c_uint , pub __writers : :: std :: os :: raw :: c_uint , pub __wrphase_futex : :: std :: os :: raw :: c_uint , pub __writers_futex : :: std :: os :: raw :: c_uint , pub __pad3 : :: std :: os :: raw :: c_uint , pub __pad4 : :: std :: os :: raw :: c_uint , pub __cur_writer : :: std :: os :: raw :: c_int , pub __shared : :: std :: os :: raw :: c_int , pub __pad1 : :: std :: os :: raw :: c_ulong , pub __pad2 : :: std :: os :: raw :: c_ulong , pub __flags : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_rwlock_arch_t"] [:: std :: mem :: size_of :: < __pthread_rwlock_arch_t > () - 56usize] ; ["Alignment of __pthread_rwlock_arch_t"] [:: std :: mem :: align_of :: < __pthread_rwlock_arch_t > () - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__readers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __readers) - 0usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers) - 4usize] ; ["Offset of field: __pthread_rwlock_arch_t::__wrphase_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __wrphase_futex) - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers_futex) - 12usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad3"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad3) - 16usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad4"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad4) - 20usize] ; ["Offset of field: __pthread_rwlock_arch_t::__cur_writer"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __cur_writer) - 24usize] ; ["Offset of field: __pthread_rwlock_arch_t::__shared"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __shared) - 28usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad1"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad1) - 32usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad2"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad2) - 40usize] ; ["Offset of field: __pthread_rwlock_arch_t::__flags"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __flags) - 48usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct __pthread_cond_s { pub __wseq : __atomic_wide_counter , pub __g1_start : __atomic_wide_counter , pub __g_size : [:: std :: os :: raw :: c_uint ; 2usize] , pub __g1_orig_size : :: std :: os :: raw :: c_uint , pub __wrefs : :: std :: os :: raw :: c_uint , pub __g_signals : [:: std :: os :: raw :: c_uint ; 2usize] , pub __unused_initialized_1 : :: std :: os :: raw :: c_uint , pub __unused_initialized_2 : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_cond_s"] [:: std :: mem :: size_of :: < __pthread_cond_s > () - 48usize] ; ["Alignment of __pthread_cond_s"] [:: std :: mem :: align_of :: < __pthread_cond_s > () - 8usize] ; ["Offset of field: __pthread_cond_s::__wseq"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wseq) - 0usize] ; ["Offset of field: __pthread_cond_s::__g1_start"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_start) - 8usize] ; ["Offset of field: __pthread_cond_s::__g_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_size) - 16usize] ; ["Offset of field: __pthread_cond_s::__g1_orig_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_orig_size) - 24usize] ; ["Offset of field: __pthread_cond_s::__wrefs"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wrefs) - 28usize] ; ["Offset of field: __pthread_cond_s::__g_signals"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_signals) - 32usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_1"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_1) - 40usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_2"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_2) - 44usize] ; } ; impl :: std :: fmt :: Debug for __pthread_cond_s { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__pthread_cond_s {{ __wseq: {:?}, __g1_start: {:?}, __g_size: {:?}, __g1_orig_size: {:?}, __wrefs: {:?}, __g_signals: {:?}, __unused_initialized_1: {:?}, __unused_initialized_2: {:?} }}" , self . __wseq , self . __g1_start , self . __g_size , self . __g1_orig_size , self . __wrefs , self . __g_signals , self . __unused_initialized_1 , self . __unused_initialized_2) } } pub type __tss_t = :: std :: os :: raw :: c_uint ; pub type __thrd_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __once_flag { pub __data : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __once_flag"] [:: std :: mem :: size_of :: < __once_flag > () - 4usize] ; ["Alignment of __once_flag"] [:: std :: mem :: align_of :: < __once_flag > () - 4usize] ; ["Offset of field: __once_flag::__data"] [:: std :: mem :: offset_of ! (__once_flag , __data) - 0usize] ; } ; pub type pthread_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutexattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutexattr_t"] [:: std :: mem :: size_of :: < pthread_mutexattr_t > () - 4usize] ; ["Alignment of pthread_mutexattr_t"] [:: std :: mem :: align_of :: < pthread_mutexattr_t > () - 4usize] ; ["Offset of field: pthread_mutexattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __size) - 0usize] ; ["Offset of field: pthread_mutexattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutexattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutexattr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_condattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_condattr_t"] [:: std :: mem :: size_of :: < pthread_condattr_t > () - 4usize] ; ["Alignment of pthread_condattr_t"] [:: std :: mem :: align_of :: < pthread_condattr_t > () - 4usize] ; ["Offset of field: pthread_condattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __size) - 0usize] ; ["Offset of field: pthread_condattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_condattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_condattr_t {{ union }}") } } pub type pthread_key_t = :: std :: os :: raw :: c_uint ; pub type pthread_once_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_attr_t { pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_attr_t"] [:: std :: mem :: size_of :: < pthread_attr_t > () - 56usize] ; ["Alignment of pthread_attr_t"] [:: std :: mem :: align_of :: < pthread_attr_t > () - 8usize] ; ["Offset of field: pthread_attr_t::__size"] [:: std :: mem :: offset_of ! (pthread_attr_t , __size) - 0usize] ; ["Offset of field: pthread_attr_t::__align"] [:: std :: mem :: offset_of ! (pthread_attr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_attr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_attr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutex_t { pub __data : __pthread_mutex_s , pub __size : [:: std :: os :: raw :: c_char ; 40usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutex_t"] [:: std :: mem :: size_of :: < pthread_mutex_t > () - 40usize] ; ["Alignment of pthread_mutex_t"] [:: std :: mem :: align_of :: < pthread_mutex_t > () - 8usize] ; ["Offset of field: pthread_mutex_t::__data"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __data) - 0usize] ; ["Offset of field: pthread_mutex_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __size) - 0usize] ; ["Offset of field: pthread_mutex_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutex_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutex_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_cond_t { pub __data : __pthread_cond_s , pub __size : [:: std :: os :: raw :: c_char ; 48usize] , pub __align : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_cond_t"] [:: std :: mem :: size_of :: < pthread_cond_t > () - 48usize] ; ["Alignment of pthread_cond_t"] [:: std :: mem :: align_of :: < pthread_cond_t > () - 8usize] ; ["Offset of field: pthread_cond_t::__data"] [:: std :: mem :: offset_of ! (pthread_cond_t , __data) - 0usize] ; ["Offset of field: pthread_cond_t::__size"] [:: std :: mem :: offset_of ! (pthread_cond_t , __size) - 0usize] ; ["Offset of field: pthread_cond_t::__align"] [:: std :: mem :: offset_of ! (pthread_cond_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_cond_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_cond_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlock_t { pub __data : __pthread_rwlock_arch_t , pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlock_t"] [:: std :: mem :: size_of :: < pthread_rwlock_t > () - 56usize] ; ["Alignment of pthread_rwlock_t"] [:: std :: mem :: align_of :: < pthread_rwlock_t > () - 8usize] ; ["Offset of field: pthread_rwlock_t::__data"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __data) - 0usize] ; ["Offset of field: pthread_rwlock_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __size) - 0usize] ; ["Offset of field: pthread_rwlock_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlock_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlock_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlockattr_t { pub __size : [:: std :: os :: raw :: c_char ; 8usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlockattr_t"] [:: std :: mem :: size_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Alignment of pthread_rwlockattr_t"] [:: std :: mem :: align_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Offset of field: pthread_rwlockattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __size) - 0usize] ; ["Offset of field: pthread_rwlockattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlockattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlockattr_t {{ union }}") } } pub type pthread_spinlock_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrier_t { pub __size : [:: std :: os :: raw :: c_char ; 32usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrier_t"] [:: std :: mem :: size_of :: < pthread_barrier_t > () - 32usize] ; ["Alignment of pthread_barrier_t"] [:: std :: mem :: align_of :: < pthread_barrier_t > () - 8usize] ; ["Offset of field: pthread_barrier_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __size) - 0usize] ; ["Offset of field: pthread_barrier_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrier_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrier_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrierattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrierattr_t"] [:: std :: mem :: size_of :: < pthread_barrierattr_t > () - 4usize] ; ["Alignment of pthread_barrierattr_t"] [:: std :: mem :: align_of :: < pthread_barrierattr_t > () - 4usize] ; ["Offset of field: pthread_barrierattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __size) - 0usize] ; ["Offset of field: pthread_barrierattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrierattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrierattr_t {{ union }}") } } unsafe extern "C" { pub fn random () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srandom (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn initstate (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn setstate (__statebuf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct random_data { pub fptr : * mut i32 , pub rptr : * mut i32 , pub state : * mut i32 , pub rand_type : :: std :: os :: raw :: c_int , pub rand_deg : :: std :: os :: raw :: c_int , pub rand_sep : :: std :: os :: raw :: c_int , pub end_ptr : * mut i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of random_data"] [:: std :: mem :: size_of :: < random_data > () - 48usize] ; ["Alignment of random_data"] [:: std :: mem :: align_of :: < random_data > () - 8usize] ; ["Offset of field: random_data::fptr"] [:: std :: mem :: offset_of ! (random_data , fptr) - 0usize] ; ["Offset of field: random_data::rptr"] [:: std :: mem :: offset_of ! (random_data , rptr) - 8usize] ; ["Offset of field: random_data::state"] [:: std :: mem :: offset_of ! (random_data , state) - 16usize] ; ["Offset of field: random_data::rand_type"] [:: std :: mem :: offset_of ! (random_data , rand_type) - 24usize] ; ["Offset of field: random_data::rand_deg"] [:: std :: mem :: offset_of ! (random_data , rand_deg) - 28usize] ; ["Offset of field: random_data::rand_sep"] [:: std :: mem :: offset_of ! (random_data , rand_sep) - 32usize] ; ["Offset of field: random_data::end_ptr"] [:: std :: mem :: offset_of ! (random_data , end_ptr) - 40usize] ; } ; unsafe extern "C" { pub fn random_r (__buf : * mut random_data , __result : * mut i32) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srandom_r (__seed : :: std :: os :: raw :: c_uint , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn initstate_r (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setstate_r (__statebuf : * mut :: std :: os :: raw :: c_char , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rand () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn rand_r (__seed : * mut :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn drand48 () -> f64 ; } unsafe extern "C" { pub fn erand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> f64 ; } unsafe extern "C" { pub fn lrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn nrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn mrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn jrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srand48 (__seedval : :: std :: os :: raw :: c_long) ; } unsafe extern "C" { pub fn seed48 (__seed16v : * mut :: std :: os :: raw :: c_ushort) -> * mut :: std :: os :: raw :: c_ushort ; } unsafe extern "C" { pub fn lcong48 (__param : * mut :: std :: os :: raw :: c_ushort) ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct drand48_data { pub __x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __old_x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __c : :: std :: os :: raw :: c_ushort , pub __init : :: std :: os :: raw :: c_ushort , pub __a : :: std :: os :: raw :: c_ulonglong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of drand48_data"] [:: std :: mem :: size_of :: < drand48_data > () - 24usize] ; ["Alignment of drand48_data"] [:: std :: mem :: align_of :: < drand48_data > () - 8usize] ; ["Offset of field: drand48_data::__x"] [:: std :: mem :: offset_of ! (drand48_data , __x) - 0usize] ; ["Offset of field: drand48_data::__old_x"] [:: std :: mem :: offset_of ! (drand48_data , __old_x) - 6usize] ; ["Offset of field: drand48_data::__c"] [:: std :: mem :: offset_of ! (drand48_data , __c) - 12usize] ; ["Offset of field: drand48_data::__init"] [:: std :: mem :: offset_of ! (drand48_data , __init) - 14usize] ; ["Offset of field: drand48_data::__a"] [:: std :: mem :: offset_of ! (drand48_data , __a) - 16usize] ; } ; unsafe extern "C" { pub fn drand48_r (__buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn erand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn nrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn jrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand48_r (__seedval : :: std :: os :: raw :: c_long , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn seed48_r (__seed16v : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lcong48_r (__param : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn arc4random () -> __uint32_t ; } unsafe extern "C" { pub fn arc4random_buf (__buf : * mut :: std :: os :: raw :: c_void , __size : usize) ; } unsafe extern "C" { pub fn arc4random_uniform (__upper_bound : __uint32_t) -> __uint32_t ; } unsafe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn calloc (__nmemb : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn free (__ptr : * mut :: std :: os :: raw :: c_void) ; } unsafe extern "C" { pub fn reallocarray (__ptr : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn alloca (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn valloc (__size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn posix_memalign (__memptr : * mut * mut :: std :: os :: raw :: c_void , __alignment : usize , __size : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn aligned_alloc (__alignment : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn abort () -> ! ; } unsafe extern "C" { pub fn atexit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn at_quick_exit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn on_exit (__func : :: std :: option :: Option < unsafe extern "C" fn (__status : :: std :: os :: raw :: c_int , __arg : * mut :: std :: os :: raw :: c_void) > , __arg : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn quick_exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn _Exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn getenv (__name : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn putenv (__string : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setenv (__name : * const :: std :: os :: raw :: c_char , __value : * const :: std :: os :: raw :: c_char , __replace : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn unsetenv (__name : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearenv () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mktemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn mkstemp (__template : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkstemps (__template : * mut :: std :: os :: raw :: c_char , __suffixlen : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkdtemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn system (__command : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn realpath (__name : * const :: std :: os :: raw :: c_char , __resolved : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } pub type __compar_fn_t = :: std :: option :: Option < unsafe extern "C" fn (arg1 : * const :: std :: os :: raw :: c_void , arg2 : * const :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; unsafe extern "C" { pub fn bsearch (__key : * const :: std :: os :: raw :: c_void , __base : * const :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn qsort (__base : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) ; } unsafe extern "C" { pub fn abs (__x : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn labs (__x : :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn llabs (__x : :: std :: os :: raw :: c_longlong) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn div (__numer : :: std :: os :: raw :: c_int , __denom : :: std :: os :: raw :: c_int) -> div_t ; } unsafe extern "C" { pub fn ldiv (__numer : :: std :: os :: raw :: c_long , __denom : :: std :: os :: raw :: c_long) -> ldiv_t ; } unsafe extern "C" { pub fn lldiv (__numer : :: std :: os :: raw :: c_longlong , __denom : :: std :: os :: raw :: c_longlong) -> lldiv_t ; } unsafe extern "C" { pub fn ecvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn gcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qecvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qfcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qgcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn ecvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fcvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qecvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qfcvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mblen (__s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbtowc (__pwc : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn wctomb (__s : * mut :: std :: os :: raw :: c_char , __wchar : wchar_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbstowcs (__pwcs : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> usize ; } unsafe extern "C" { pub fn wcstombs (__s : * mut :: std :: os :: raw :: c_char , __pwcs : * const wchar_t , __n : usize) -> usize ; } unsafe extern "C" { pub fn rpmatch (__response : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getsubopt (__optionp : * mut * mut :: std :: os :: raw :: c_char , __tokens : * const * mut :: std :: os :: raw :: c_char , __valuep : * mut * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getloadavg (__loadavg : * mut f64 , __nelem : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } # [repr (C)] # [derive (Copy , Clone)] pub struct __mbstate_t { pub __count : :: std :: os :: raw :: c_int , pub __value : __mbstate_t__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union __mbstate_t__bindgen_ty_1 { pub __wch : :: std :: os :: raw :: c_uint , pub __wchb : [:: std :: os :: raw :: c_char ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: size_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Alignment of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: align_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wch"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wch) - 0usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wchb"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wchb) - 0usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t"] [:: std :: mem :: size_of :: < __mbstate_t > () - 8usize] ; ["Alignment of __mbstate_t"] [:: std :: mem :: align_of :: < __mbstate_t > () - 4usize] ; ["Offset of field: __mbstate_t::__count"] [:: std :: mem :: offset_of ! (__mbstate_t , __count) - 0usize] ; ["Offset of field: __mbstate_t::__value"] [:: std :: mem :: offset_of ! (__mbstate_t , __value) - 4usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t {{ __count: {:?}, __value: {:?} }}" , self . __count , self . __value) } } # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos_t { pub __pos : __off_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos_t"] [:: std :: mem :: size_of :: < _G_fpos_t > () - 16usize] ; ["Alignment of _G_fpos_t"] [:: std :: mem :: align_of :: < _G_fpos_t > () - 8usize] ; ["Offset of field: _G_fpos_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos_t , __pos) - 0usize] ; ["Offset of field: _G_fpos_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos_t = _G_fpos_t ; # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos64_t { pub __pos : __off64_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos64_t"] [:: std :: mem :: size_of :: < _G_fpos64_t > () - 16usize] ; ["Alignment of _G_fpos64_t"] [:: std :: mem :: align_of :: < _G_fpos64_t > () - 8usize] ; ["Offset of field: _G_fpos64_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __pos) - 0usize] ; ["Offset of field: _G_fpos64_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos64_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos64_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos64_t = _G_fpos64_t ; pub type __FILE = _IO_FILE ; pub type FILE = _IO_FILE ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_marker { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_codecvt { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_wide_data { _unused : [u8 ; 0] , } pub type _IO_lock_t = :: std :: os :: raw :: c_void ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_FILE { pub _flags : :: std :: os :: raw :: c_int , pub _IO_read_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_read_end : * mut :: std :: os :: raw :: c_char , pub _IO_read_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_write_end : * mut :: std :: os :: raw :: c_char , pub _IO_buf_base : * mut :: std :: os :: raw :: c_char , pub _IO_buf_end : * mut :: std :: os :: raw :: c_char , pub _IO_save_base : * mut :: std :: os :: raw :: c_char , pub _IO_backup_base : * mut :: std :: os :: raw :: c_char , pub _IO_save_end : * mut :: std :: os :: raw :: c_char , pub _markers : * mut _IO_marker , pub _chain : * mut _IO_FILE , pub _fileno : :: std :: os :: raw :: c_int , pub _bitfield_align_1 : [u32 ; 0] , pub _bitfield_1 : __BindgenBitfieldUnit < [u8 ; 3usize] > , pub _short_backupbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _old_offset : __off_t , pub _cur_column : :: std :: os :: raw :: c_ushort , pub _vtable_offset : :: std :: os :: raw :: c_schar , pub _shortbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _lock : * mut _IO_lock_t , pub _offset : __off64_t , pub _codecvt : * mut _IO_codecvt , pub _wide_data : * mut _IO_wide_data , pub _freeres_list : * mut _IO_FILE , pub _freeres_buf : * mut :: std :: os :: raw :: c_void , pub _prevchain : * mut * mut _IO_FILE , pub _mode : :: std :: os :: raw :: c_int , pub _unused3 : :: std :: os :: raw :: c_int , pub _total_written : __uint64_t , pub _unused2 : [:: std :: os :: raw :: c_char ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_FILE"] [:: std :: mem :: size_of :: < _IO_FILE > () - 216usize] ; ["Alignment of _IO_FILE"] [:: std :: mem :: align_of :: < _IO_FILE > () - 8usize] ; ["Offset of field: _IO_FILE::_flags"] [:: std :: mem :: offset_of ! (_IO_FILE , _flags) - 0usize] ; ["Offset of field: _IO_FILE::_IO_read_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_ptr) - 8usize] ; ["Offset of field: _IO_FILE::_IO_read_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_end) - 16usize] ; ["Offset of field: _IO_FILE::_IO_read_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_base) - 24usize] ; ["Offset of field: _IO_FILE::_IO_write_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_base) - 32usize] ; ["Offset of field: _IO_FILE::_IO_write_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_ptr) - 40usize] ; ["Offset of field: _IO_FILE::_IO_write_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_end) - 48usize] ; ["Offset of field: _IO_FILE::_IO_buf_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_base) - 56usize] ; ["Offset of field: _IO_FILE::_IO_buf_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_end) - 64usize] ; ["Offset of field: _IO_FILE::_IO_save_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_base) - 72usize] ; ["Offset of field: _IO_FILE::_IO_backup_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_backup_base) - 80usize] ; ["Offset of field: _IO_FILE::_IO_save_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_end) - 88usize] ; ["Offset of field: _IO_FILE::_markers"] [:: std :: mem :: offset_of ! (_IO_FILE , _markers) - 96usize] ; ["Offset of field: _IO_FILE::_chain"] [:: std :: mem :: offset_of ! (_IO_FILE , _chain) - 104usize] ; ["Offset of field: _IO_FILE::_fileno"] [:: std :: mem :: offset_of ! (_IO_FILE , _fileno) - 112usize] ; ["Offset of field: _IO_FILE::_short_backupbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _short_backupbuf) - 119usize] ; ["Offset of field: _IO_FILE::_old_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _old_offset) - 120usize] ; ["Offset of field: _IO_FILE::_cur_column"] [:: std :: mem :: offset_of ! (_IO_FILE , _cur_column) - 128usize] ; ["Offset of field: _IO_FILE::_vtable_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _vtable_offset) - 130usize] ; ["Offset of field: _IO_FILE::_shortbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _shortbuf) - 131usize] ; ["Offset of field: _IO_FILE::_lock"] [:: std :: mem :: offset_of ! (_IO_FILE , _lock) - 136usize] ; ["Offset of field: _IO_FILE::_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _offset) - 144usize] ; ["Offset of field: _IO_FILE::_codecvt"] [:: std :: mem :: offset_of ! (_IO_FILE , _codecvt) - 152usize] ; ["Offset of field: _IO_FILE::_wide_data"] [:: std :: mem :: offset_of ! (_IO_FILE , _wide_data) - 160usize] ; ["Offset of field: _IO_FILE::_freeres_list"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_list) - 168usize] ; ["Offset of field: _IO_FILE::_freeres_buf"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_buf) - 176usize] ; ["Offset of field: _IO_FILE::_prevchain"] [:: std :: mem :: offset_of ! (_IO_FILE , _prevchain) - 184usize] ; ["Offset of field: _IO_FILE::_mode"] [:: std :: mem :: offset_of ! (_IO_FILE , _mode) - 192usize] ; ["Offset of field: _IO_FILE::_unused3"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused3) - 196usize] ; ["Offset of field: _IO_FILE::_total_written"] [:: std :: mem :: offset_of ! (_IO_FILE , _total_written) - 200usize] ; ["Offset of field: _IO_FILE::_unused2"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused2) - 208usize] ; } ; impl _IO_FILE { # [inline] pub fn _flags2 (& self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set__flags2 (& mut self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; self . _bitfield_1 . set (0usize , 24u8 , val as u64) } } # [inline] pub unsafe fn _flags2_raw (this : * const Self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } } # [inline] pub unsafe fn set__flags2_raw (this : * mut Self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_set (:: std :: ptr :: addr_of_mut ! ((* this) . _bitfield_1) , 0usize , 24u8 , val as u64 ,) } } # [inline] pub fn new_bitfield_1 (_flags2 : :: std :: os :: raw :: c_int) -> __BindgenBitfieldUnit < [u8 ; 3usize] > { let mut __bindgen_bitfield_unit : __BindgenBitfieldUnit < [u8 ; 3usize] > = Default :: default () ; __bindgen_bitfield_unit . set (0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_unit } } pub type cookie_read_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * mut :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_write_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * const :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_seek_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __pos : * mut __off64_t , __w : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int > ; pub type cookie_close_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_cookie_io_functions_t { pub read : cookie_read_function_t , pub write : cookie_write_function_t , pub seek : cookie_seek_function_t , pub close : cookie_close_function_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_cookie_io_functions_t"] [:: std :: mem :: size_of :: < _IO_cookie_io_functions_t > () - 32usize] ; ["Alignment of _IO_cookie_io_functions_t"] [:: std :: mem :: align_of :: < _IO_cookie_io_functions_t > () - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::read"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , read) - 0usize] ; ["Offset of field: _IO_cookie_io_functions_t::write"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , write) - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::seek"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , seek) - 16usize] ; ["Offset of field: _IO_cookie_io_functions_t::close"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , close) - 24usize] ; } ; pub type cookie_io_functions_t = _IO_cookie_io_functions_t ; pub type fpos_t = __fpos_t ; unsafe extern "C" { pub static mut stdin : * mut FILE ; } unsafe extern "C" { pub static mut stdout : * mut FILE ; } unsafe extern "C" { pub static mut stderr : * mut FILE ; } unsafe extern "C" { pub fn remove (__filename : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rename (__old : * const :: std :: os :: raw :: c_char , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn renameat (__oldfd : :: std :: os :: raw :: c_int , __old : * const :: std :: os :: raw :: c_char , __newfd : :: std :: os :: raw :: c_int , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn tmpfile () -> * mut FILE ; } unsafe extern "C" { pub fn tmpnam (arg1 : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tmpnam_r (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tempnam (__dir : * const :: std :: os :: raw :: c_char , __pfx : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fflush (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fflush_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn freopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> * mut FILE ; } unsafe extern "C" { pub fn fdopen (__fd : :: std :: os :: raw :: c_int , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn fopencookie (__magic_cookie : * mut :: std :: os :: raw :: c_void , __modes : * const :: std :: os :: raw :: c_char , __io_funcs : cookie_io_functions_t) -> * mut FILE ; } unsafe extern "C" { pub fn fmemopen (__s : * mut :: std :: os :: raw :: c_void , __len : usize , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn open_memstream (__bufloc : * mut * mut :: std :: os :: raw :: c_char , __sizeloc : * mut usize) -> * mut FILE ; } unsafe extern "C" { pub fn setbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn setvbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __modes : :: std :: os :: raw :: c_int , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setbuffer (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __size : usize) ; } unsafe extern "C" { pub fn setlinebuf (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fprintf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn printf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfprintf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vprintf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn snprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsnprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vasprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __f : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vdprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn dprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fscanf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn scanf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_fscanf"] pub fn fscanf1 (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_scanf"] pub fn scanf1 (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_sscanf"] pub fn sscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfscanf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vscanf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vfscanf"] pub fn vfscanf1 (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vscanf"] pub fn vscanf1 (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vsscanf"] pub fn vsscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar_unlocked () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar_unlocked (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getw (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putw (__w : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgets (__s : * mut :: std :: os :: raw :: c_char , __n : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn __getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getline (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn fputs (__s : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn puts (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ungetc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fread (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __stream : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fwrite (__ptr : * const :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __s : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fread_unlocked (__ptr : * mut :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fwrite_unlocked (__ptr : * const :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fseek (__stream : * mut FILE , __off : :: std :: os :: raw :: c_long , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftell (__stream : * mut FILE) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn rewind (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fseeko (__stream : * mut FILE , __off : __off_t , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftello (__stream : * mut FILE) -> __off_t ; } unsafe extern "C" { pub fn fgetpos (__stream : * mut FILE , __pos : * mut fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fsetpos (__stream : * mut FILE , __pos : * const fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr_unlocked (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn perror (__s : * const :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn fileno (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fileno_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn popen (__command : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn ctermid (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn flockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn ftrylockfile (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn funlockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn __uflow (arg1 : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __overflow (arg1 : * mut FILE , arg2 : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } pub type int_least8_t = __int_least8_t ; pub type int_least16_t = __int_least16_t ; pub type int_least32_t = __int_least32_t ; pub type int_least64_t = __int_least64_t ; pub type uint_least8_t = __uint_least8_t ; pub type uint_least16_t = __uint_least16_t ; pub type uint_least32_t = __uint_least32_t ; pub type uint_least64_t = __uint_least64_t ; pub type int_fast8_t = :: std :: os :: raw :: c_schar ; pub type int_fast16_t = :: std :: os :: raw :: c_long ; pub type int_fast32_t = :: std :: os :: raw :: c_long ; pub type int_fast64_t = :: std :: os :: raw :: c_long ; pub type uint_fast8_t = :: std :: os :: raw :: c_uchar ; pub type uint_fast16_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast32_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast64_t = :: std :: os :: raw :: c_ulong ; pub type intmax_t = __intmax_t ; pub type uintmax_t = __uintmax_t ; pub type __gwchar_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct imaxdiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of imaxdiv_t"] [:: std :: mem :: size_of :: < imaxdiv_t > () - 16usize] ; ["Alignment of imaxdiv_t"] [:: std :: mem :: align_of :: < imaxdiv_t > () - 8usize] ; ["Offset of field: imaxdiv_t::quot"] [:: std :: mem :: offset_of ! (imaxdiv_t , quot) - 0usize] ; ["Offset of field: imaxdiv_t::rem"] [:: std :: mem :: offset_of ! (imaxdiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn imaxabs (__n : intmax_t) -> intmax_t ; } unsafe extern "C" { pub fn imaxdiv (__numer : intmax_t , __denom : intmax_t) -> imaxdiv_t ; } unsafe extern "C" { pub fn strtoimax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn strtoumax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } unsafe extern "C" { pub fn wcstoimax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn wcstoumax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } pub type csh = usize ; # [repr (u32)] # [doc = " Architecture type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_arch { # [doc = "< ARM architecture (including Thumb, Thumb-2)"] CS_ARCH_ARM = 0 , # [doc = "< ARM-64, also called AArch64"] CS_ARCH_ARM64 = 1 , # [doc = "< Mips architecture"] CS_ARCH_MIPS = 2 , # [doc = "< X86 architecture (including x86 & x86-64)"] CS_ARCH_X86 = 3 , # [doc = "< PowerPC architecture"] CS_ARCH_PPC = 4 , # [doc = "< Sparc architecture"] CS_ARCH_SPARC = 5 , # [doc = "< SystemZ architecture"] CS_ARCH_SYSZ = 6 , # [doc = "< XCore architecture"] CS_ARCH_XCORE = 7 , # [doc = "< 68K architecture"] CS_ARCH_M68K = 8 , # [doc = "< TMS320C64x architecture"] CS_ARCH_TMS320C64X = 9 , # [doc = "< 680X architecture"] CS_ARCH_M680X = 10 , # [doc = "< Ethereum architecture"] CS_ARCH_EVM = 11 , # [doc = "< MOS65XX architecture (including MOS6502)"] CS_ARCH_MOS65XX = 12 , # [doc = "< WebAssembly architecture"] CS_ARCH_WASM = 13 , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] CS_ARCH_BPF = 14 , # [doc = "< RISCV architecture"] CS_ARCH_RISCV = 15 , # [doc = "< SH architecture"] CS_ARCH_SH = 16 , # [doc = "< TriCore architecture"] CS_ARCH_TRICORE = 17 , CS_ARCH_MAX = 18 , CS_ARCH_ALL = 65535 , } # [doc = "< little-endian mode (default mode)"] pub const cs_mode_CS_MODE_LITTLE_ENDIAN : cs_mode = 0 ; # [doc = "< 32-bit ARM"] pub const cs_mode_CS_MODE_ARM : cs_mode = 0 ; # [doc = "< 16-bit mode (X86)"] pub const cs_mode_CS_MODE_16 : cs_mode = 2 ; # [doc = "< 32-bit mode (X86)"] pub const cs_mode_CS_MODE_32 : cs_mode = 4 ; # [doc = "< 64-bit mode (X86, PPC)"] pub const cs_mode_CS_MODE_64 : cs_mode = 8 ; # [doc = "< ARM's Thumb mode, including Thumb-2"] pub const cs_mode_CS_MODE_THUMB : cs_mode = 16 ; # [doc = "< ARM's Cortex-M series"] pub const cs_mode_CS_MODE_MCLASS : cs_mode = 32 ; # [doc = "< ARMv8 A32 encodings for ARM"] pub const cs_mode_CS_MODE_V8 : cs_mode = 64 ; # [doc = "< MicroMips mode (MIPS)"] pub const cs_mode_CS_MODE_MICRO : cs_mode = 16 ; # [doc = "< Mips III ISA"] pub const cs_mode_CS_MODE_MIPS3 : cs_mode = 32 ; # [doc = "< Mips32r6 ISA"] pub const cs_mode_CS_MODE_MIPS32R6 : cs_mode = 64 ; # [doc = "< Mips II ISA"] pub const cs_mode_CS_MODE_MIPS2 : cs_mode = 128 ; # [doc = "< SparcV9 mode (Sparc)"] pub const cs_mode_CS_MODE_V9 : cs_mode = 16 ; # [doc = "< Quad Processing eXtensions mode (PPC)"] pub const cs_mode_CS_MODE_QPX : cs_mode = 16 ; # [doc = "< Signal Processing Engine mode (PPC)"] pub const cs_mode_CS_MODE_SPE : cs_mode = 32 ; # [doc = "< Book-E mode (PPC)"] pub const cs_mode_CS_MODE_BOOKE : cs_mode = 64 ; # [doc = "< Paired-singles mode (PPC)"] pub const cs_mode_CS_MODE_PS : cs_mode = 128 ; # [doc = "< M68K 68000 mode"] pub const cs_mode_CS_MODE_M68K_000 : cs_mode = 2 ; # [doc = "< M68K 68010 mode"] pub const cs_mode_CS_MODE_M68K_010 : cs_mode = 4 ; # [doc = "< M68K 68020 mode"] pub const cs_mode_CS_MODE_M68K_020 : cs_mode = 8 ; # [doc = "< M68K 68030 mode"] pub const cs_mode_CS_MODE_M68K_030 : cs_mode = 16 ; # [doc = "< M68K 68040 mode"] pub const cs_mode_CS_MODE_M68K_040 : cs_mode = 32 ; # [doc = "< M68K 68060 mode"] pub const cs_mode_CS_MODE_M68K_060 : cs_mode = 64 ; # [doc = "< big-endian mode"] pub const cs_mode_CS_MODE_BIG_ENDIAN : cs_mode = 2147483648 ; # [doc = "< Mips32 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS32 : cs_mode = 4 ; # [doc = "< Mips64 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS64 : cs_mode = 8 ; # [doc = "< M680X Hitachi 6301,6303 mode"] pub const cs_mode_CS_MODE_M680X_6301 : cs_mode = 2 ; # [doc = "< M680X Hitachi 6309 mode"] pub const cs_mode_CS_MODE_M680X_6309 : cs_mode = 4 ; # [doc = "< M680X Motorola 6800,6802 mode"] pub const cs_mode_CS_MODE_M680X_6800 : cs_mode = 8 ; # [doc = "< M680X Motorola 6801,6803 mode"] pub const cs_mode_CS_MODE_M680X_6801 : cs_mode = 16 ; # [doc = "< M680X Motorola/Freescale 6805 mode"] pub const cs_mode_CS_MODE_M680X_6805 : cs_mode = 32 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"] pub const cs_mode_CS_MODE_M680X_6808 : cs_mode = 64 ; # [doc = "< M680X Motorola 6809 mode"] pub const cs_mode_CS_MODE_M680X_6809 : cs_mode = 128 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"] pub const cs_mode_CS_MODE_M680X_6811 : cs_mode = 256 ; # [doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"] pub const cs_mode_CS_MODE_M680X_CPU12 : cs_mode = 512 ; # [doc = "< M680X Freescale/NXP HCS08 mode"] pub const cs_mode_CS_MODE_M680X_HCS08 : cs_mode = 1024 ; # [doc = "< Classic BPF mode (default)"] pub const cs_mode_CS_MODE_BPF_CLASSIC : cs_mode = 0 ; # [doc = "< Extended BPF mode"] pub const cs_mode_CS_MODE_BPF_EXTENDED : cs_mode = 1 ; # [doc = "< RISCV RV32G"] pub const cs_mode_CS_MODE_RISCV32 : cs_mode = 1 ; # [doc = "< RISCV RV64G"] pub const cs_mode_CS_MODE_RISCV64 : cs_mode = 2 ; # [doc = "< RISCV compressed instructure mode"] pub const cs_mode_CS_MODE_RISCVC : cs_mode = 4 ; # [doc = "< MOS65XXX MOS 6502"] pub const cs_mode_CS_MODE_MOS65XX_6502 : cs_mode = 2 ; # [doc = "< MOS65XXX WDC 65c02"] pub const cs_mode_CS_MODE_MOS65XX_65C02 : cs_mode = 4 ; # [doc = "< MOS65XXX WDC W65c02"] pub const cs_mode_CS_MODE_MOS65XX_W65C02 : cs_mode = 8 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m/x"] pub const cs_mode_CS_MODE_MOS65XX_65816 : cs_mode = 16 ; # [doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_M : cs_mode = 32 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_X : cs_mode = 64 ; pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_MX : cs_mode = 96 ; # [doc = "< SH2"] pub const cs_mode_CS_MODE_SH2 : cs_mode = 2 ; # [doc = "< SH2A"] pub const cs_mode_CS_MODE_SH2A : cs_mode = 4 ; # [doc = "< SH3"] pub const cs_mode_CS_MODE_SH3 : cs_mode = 8 ; # [doc = "< SH4"] pub const cs_mode_CS_MODE_SH4 : cs_mode = 16 ; # [doc = "< SH4A"] pub const cs_mode_CS_MODE_SH4A : cs_mode = 32 ; # [doc = "< w/ FPU"] pub const cs_mode_CS_MODE_SHFPU : cs_mode = 64 ; # [doc = "< w/ DSP"] pub const cs_mode_CS_MODE_SHDSP : cs_mode = 128 ; # [doc = "< Tricore 1.1"] pub const cs_mode_CS_MODE_TRICORE_110 : cs_mode = 2 ; # [doc = "< Tricore 1.2"] pub const cs_mode_CS_MODE_TRICORE_120 : cs_mode = 4 ; # [doc = "< Tricore 1.3"] pub const cs_mode_CS_MODE_TRICORE_130 : cs_mode = 8 ; # [doc = "< Tricore 1.3.1"] pub const cs_mode_CS_MODE_TRICORE_131 : cs_mode = 16 ; # [doc = "< Tricore 1.6"] pub const cs_mode_CS_MODE_TRICORE_160 : cs_mode = 32 ; # [doc = "< Tricore 1.6.1"] pub const cs_mode_CS_MODE_TRICORE_161 : cs_mode = 64 ; # [doc = "< Tricore 1.6.2"] pub const cs_mode_CS_MODE_TRICORE_162 : cs_mode = 128 ; # [doc = " Mode type"] pub type cs_mode = :: std :: os :: raw :: c_uint ; pub type cs_malloc_t = :: std :: option :: Option < unsafe extern "C" fn (size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_calloc_t = :: std :: option :: Option < unsafe extern "C" fn (nmemb : usize , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_realloc_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_free_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void) > ; pub type cs_vsnprintf_t = :: std :: option :: Option < unsafe extern "C" fn (str_ : * mut :: std :: os :: raw :: c_char , size : usize , format : * const :: std :: os :: raw :: c_char , ap : * mut __va_list_tag) -> :: std :: os :: raw :: c_int > ; # [doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mem { pub malloc : cs_malloc_t , pub calloc : cs_calloc_t , pub realloc : cs_realloc_t , pub free : cs_free_t , pub vsnprintf : cs_vsnprintf_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mem"] [:: std :: mem :: size_of :: < cs_opt_mem > () - 40usize] ; ["Alignment of cs_opt_mem"] [:: std :: mem :: align_of :: < cs_opt_mem > () - 8usize] ; ["Offset of field: cs_opt_mem::malloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , malloc) - 0usize] ; ["Offset of field: cs_opt_mem::calloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , calloc) - 8usize] ; ["Offset of field: cs_opt_mem::realloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , realloc) - 16usize] ; ["Offset of field: cs_opt_mem::free"] [:: std :: mem :: offset_of ! (cs_opt_mem , free) - 24usize] ; ["Offset of field: cs_opt_mem::vsnprintf"] [:: std :: mem :: offset_of ! (cs_opt_mem , vsnprintf) - 32usize] ; } ; # [doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mnem { # [doc = " ID of instruction to be customized."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Customized instruction mnemonic."] pub mnemonic : * const :: std :: os :: raw :: c_char , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mnem"] [:: std :: mem :: size_of :: < cs_opt_mnem > () - 16usize] ; ["Alignment of cs_opt_mnem"] [:: std :: mem :: align_of :: < cs_opt_mnem > () - 8usize] ; ["Offset of field: cs_opt_mnem::id"] [:: std :: mem :: offset_of ! (cs_opt_mnem , id) - 0usize] ; ["Offset of field: cs_opt_mnem::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_mnem , mnemonic) - 8usize] ; } ; # [repr (u32)] # [doc = " Runtime option for the disassembled engine"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_type { # [doc = "< No option specified"] CS_OPT_INVALID = 0 , # [doc = "< Assembly output syntax"] CS_OPT_SYNTAX = 1 , # [doc = "< Break down instruction structure into details"] CS_OPT_DETAIL = 2 , # [doc = "< Change engine's mode at run-time"] CS_OPT_MODE = 3 , # [doc = "< User-defined dynamic memory related functions"] CS_OPT_MEM = 4 , # [doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."] CS_OPT_SKIPDATA = 5 , # [doc = "< Setup user-defined function for SKIPDATA option"] CS_OPT_SKIPDATA_SETUP = 6 , # [doc = "< Customize instruction mnemonic"] CS_OPT_MNEMONIC = 7 , # [doc = "< print immediate operands in unsigned form"] CS_OPT_UNSIGNED = 8 , # [doc = "< ARM, prints branch immediates without offset."] CS_OPT_NO_BRANCH_OFFSET = 9 , } impl cs_opt_value { pub const CS_OPT_SYNTAX_DEFAULT : cs_opt_value = cs_opt_value :: CS_OPT_OFF ; } impl cs_opt_value { pub const CS_OPT_SYNTAX_NOREGNAME : cs_opt_value = cs_opt_value :: CS_OPT_ON ; } # [repr (u32)] # [doc = " Runtime option value (associated with option type above)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_value { # [doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."] CS_OPT_OFF = 0 , # [doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."] CS_OPT_ON = 3 , # [doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_INTEL = 1 , # [doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_ATT = 2 , # [doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_MASM = 4 , # [doc = "< MOS65XX use $ as hex prefix"] CS_OPT_SYNTAX_MOTOROLA = 5 , } # [repr (u32)] # [doc = " Common instruction operand types - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_op_type { # [doc = "< uninitialized/invalid operand."] CS_OP_INVALID = 0 , # [doc = "< Register operand."] CS_OP_REG = 1 , # [doc = "< Immediate operand."] CS_OP_IMM = 2 , # [doc = "< Memory operand. Can be ORed with another operand type."] CS_OP_MEM = 3 , # [doc = "< Floating-Point operand."] CS_OP_FP = 4 , } # [repr (u32)] # [doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_ac_type { # [doc = "< Uninitialized/invalid access type."] CS_AC_INVALID = 0 , # [doc = "< Operand read from memory or register."] CS_AC_READ = 1 , # [doc = "< Operand write to memory or register."] CS_AC_WRITE = 2 , } # [repr (u32)] # [doc = " Common instruction groups - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_group_type { # [doc = "< uninitialized/invalid group."] CS_GRP_INVALID = 0 , # [doc = "< all jump instructions (conditional+direct+indirect jumps)"] CS_GRP_JUMP = 1 , # [doc = "< all call instructions"] CS_GRP_CALL = 2 , # [doc = "< all return instructions"] CS_GRP_RET = 3 , # [doc = "< all interrupt instructions (int+syscall)"] CS_GRP_INT = 4 , # [doc = "< all interrupt return instructions"] CS_GRP_IRET = 5 , # [doc = "< all privileged instructions"] CS_GRP_PRIVILEGE = 6 , # [doc = "< all relative branching instructions"] CS_GRP_BRANCH_RELATIVE = 7 , } # [doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."] pub type cs_skipdata_cb_t = :: std :: option :: Option < unsafe extern "C" fn (code : * const u8 , code_size : usize , offset : usize , user_data : * mut :: std :: os :: raw :: c_void) -> usize > ; # [doc = " User-customized setup for SKIPDATA option"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_skipdata { # [doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."] pub mnemonic : * const :: std :: os :: raw :: c_char , # [doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes.\n TriCore: 2 bytes."] pub callback : cs_skipdata_cb_t , # [doc = " User-defined data to be passed to @callback function pointer."] pub user_data : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_skipdata"] [:: std :: mem :: size_of :: < cs_opt_skipdata > () - 24usize] ; ["Alignment of cs_opt_skipdata"] [:: std :: mem :: align_of :: < cs_opt_skipdata > () - 8usize] ; ["Offset of field: cs_opt_skipdata::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , mnemonic) - 0usize] ; ["Offset of field: cs_opt_skipdata::callback"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , callback) - 8usize] ; ["Offset of field: cs_opt_skipdata::user_data"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , user_data) - 16usize] ; } ; # [repr (u32)] # [doc = " ARM shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_shifter { ARM_SFT_INVALID = 0 , # [doc = "< shift with immediate const"] ARM_SFT_ASR = 1 , # [doc = "< shift with immediate const"] ARM_SFT_LSL = 2 , # [doc = "< shift with immediate const"] ARM_SFT_LSR = 3 , # [doc = "< shift with immediate const"] ARM_SFT_ROR = 4 , # [doc = "< shift with immediate const"] ARM_SFT_RRX = 5 , # [doc = "< shift with register"] ARM_SFT_ASR_REG = 6 , # [doc = "< shift with register"] ARM_SFT_LSL_REG = 7 , # [doc = "< shift with register"] ARM_SFT_LSR_REG = 8 , # [doc = "< shift with register"] ARM_SFT_ROR_REG = 9 , # [doc = "< shift with register"] ARM_SFT_RRX_REG = 10 , } # [repr (u32)] # [doc = " ARM condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cc { ARM_CC_INVALID = 0 , # [doc = "< Equal                      Equal"] ARM_CC_EQ = 1 , # [doc = "< Not equal                  Not equal, or unordered"] ARM_CC_NE = 2 , # [doc = "< Carry set                  >, ==, or unordered"] ARM_CC_HS = 3 , # [doc = "< Carry clear                Less than"] ARM_CC_LO = 4 , # [doc = "< Minus, negative            Less than"] ARM_CC_MI = 5 , # [doc = "< Plus, positive or zero     >, ==, or unordered"] ARM_CC_PL = 6 , # [doc = "< Overflow                   Unordered"] ARM_CC_VS = 7 , # [doc = "< No overflow                Not unordered"] ARM_CC_VC = 8 , # [doc = "< Unsigned higher            Greater than, or unordered"] ARM_CC_HI = 9 , # [doc = "< Unsigned lower or same     Less than or equal"] ARM_CC_LS = 10 , # [doc = "< Greater than or equal      Greater than or equal"] ARM_CC_GE = 11 , # [doc = "< Less than                  Less than, or unordered"] ARM_CC_LT = 12 , # [doc = "< Greater than               Greater than"] ARM_CC_GT = 13 , # [doc = "< Less than or equal         <, ==, or unordered"] ARM_CC_LE = 14 , # [doc = "< Always (unconditional)     Always (unconditional)"] ARM_CC_AL = 15 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_sysreg { # [doc = " Special registers for MSR"] ARM_SYSREG_INVALID = 0 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_C = 1 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_X = 2 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_S = 4 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_F = 8 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_C = 16 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_X = 32 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_S = 64 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_F = 128 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR = 256 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_G = 257 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQ = 258 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQG = 259 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR = 260 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_G = 261 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQG = 262 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQ = 263 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR = 264 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_G = 265 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQG = 266 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQ = 267 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR = 268 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_G = 269 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQG = 270 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQ = 271 , # [doc = " Special registers for MSR"] ARM_SYSREG_IPSR = 272 , # [doc = " Special registers for MSR"] ARM_SYSREG_EPSR = 273 , # [doc = " Special registers for MSR"] ARM_SYSREG_IEPSR = 274 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP = 275 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP = 276 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK = 277 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI = 278 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_MAX = 279 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK = 280 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL = 281 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM = 282 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM = 283 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP_NS = 284 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP_NS = 285 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM_NS = 286 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM_NS = 287 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK_NS = 288 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_NS = 289 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK_NS = 290 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL_NS = 291 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_NS = 292 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_USR = 293 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_USR = 294 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_USR = 295 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_USR = 296 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_USR = 297 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_USR = 298 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_USR = 299 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_FIQ = 300 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_FIQ = 301 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_FIQ = 302 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_FIQ = 303 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_FIQ = 304 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_FIQ = 305 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_FIQ = 306 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_IRQ = 307 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_IRQ = 308 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_SVC = 309 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_SVC = 310 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_ABT = 311 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_ABT = 312 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_UND = 313 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_UND = 314 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_MON = 315 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_MON = 316 , # [doc = " Special registers for MSR"] ARM_SYSREG_ELR_HYP = 317 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_HYP = 318 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_FIQ = 319 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_IRQ = 320 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_SVC = 321 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_ABT = 322 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_UND = 323 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_MON = 324 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_HYP = 325 , } # [repr (u32)] # [doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_mem_barrier { ARM_MB_INVALID = 0 , ARM_MB_RESERVED_0 = 1 , ARM_MB_OSHLD = 2 , ARM_MB_OSHST = 3 , ARM_MB_OSH = 4 , ARM_MB_RESERVED_4 = 5 , ARM_MB_NSHLD = 6 , ARM_MB_NSHST = 7 , ARM_MB_NSH = 8 , ARM_MB_RESERVED_8 = 9 , ARM_MB_ISHLD = 10 , ARM_MB_ISHST = 11 , ARM_MB_ISH = 12 , ARM_MB_RESERVED_12 = 13 , ARM_MB_LD = 14 , ARM_MB_ST = 15 , ARM_MB_SY = 16 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM_OP_FP = 4 , # [doc = "< C-Immediate (coprocessor registers)"] ARM_OP_CIMM = 64 , # [doc = "< P-Immediate (coprocessor registers)"] ARM_OP_PIMM = 65 , # [doc = "< operand for SETEND instruction"] ARM_OP_SETEND = 66 , # [doc = "< MSR/MRS special register operand"] ARM_OP_SYSREG = 67 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_setend_type { # [doc = "< Uninitialized."] ARM_SETEND_INVALID = 0 , # [doc = "< BE operand."] ARM_SETEND_BE = 1 , # [doc = "< LE operand"] ARM_SETEND_LE = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0 , ARM_CPSMODE_IE = 2 , ARM_CPSMODE_ID = 3 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0 , ARM_CPSFLAG_F = 1 , ARM_CPSFLAG_I = 2 , ARM_CPSFLAG_A = 4 , # [doc = "< no flag"] ARM_CPSFLAG_NONE = 16 , } # [repr (u32)] # [doc = " Data type for elements of vector instructions."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0 , ARM_VECTORDATA_I8 = 1 , ARM_VECTORDATA_I16 = 2 , ARM_VECTORDATA_I32 = 3 , ARM_VECTORDATA_I64 = 4 , ARM_VECTORDATA_S8 = 5 , ARM_VECTORDATA_S16 = 6 , ARM_VECTORDATA_S32 = 7 , ARM_VECTORDATA_S64 = 8 , ARM_VECTORDATA_U8 = 9 , ARM_VECTORDATA_U16 = 10 , ARM_VECTORDATA_U32 = 11 , ARM_VECTORDATA_U64 = 12 , ARM_VECTORDATA_P8 = 13 , ARM_VECTORDATA_F16 = 14 , ARM_VECTORDATA_F32 = 15 , ARM_VECTORDATA_F64 = 16 , ARM_VECTORDATA_F16F64 = 17 , ARM_VECTORDATA_F64F16 = 18 , ARM_VECTORDATA_F32F16 = 19 , ARM_VECTORDATA_F16F32 = 20 , ARM_VECTORDATA_F64F32 = 21 , ARM_VECTORDATA_F32F64 = 22 , ARM_VECTORDATA_S32F32 = 23 , ARM_VECTORDATA_U32F32 = 24 , ARM_VECTORDATA_F32S32 = 25 , ARM_VECTORDATA_F32U32 = 26 , ARM_VECTORDATA_F64S16 = 27 , ARM_VECTORDATA_F32S16 = 28 , ARM_VECTORDATA_F64S32 = 29 , ARM_VECTORDATA_S16F64 = 30 , ARM_VECTORDATA_S16F32 = 31 , ARM_VECTORDATA_S32F64 = 32 , ARM_VECTORDATA_U16F64 = 33 , ARM_VECTORDATA_U16F32 = 34 , ARM_VECTORDATA_U32F64 = 35 , ARM_VECTORDATA_F64U16 = 36 , ARM_VECTORDATA_F32U16 = 37 , ARM_VECTORDATA_F64U32 = 38 , ARM_VECTORDATA_F16U16 = 39 , ARM_VECTORDATA_U16F16 = 40 , ARM_VECTORDATA_F16U32 = 41 , ARM_VECTORDATA_U32F16 = 42 , } impl arm_reg { pub const ARM_REG_R13 : arm_reg = arm_reg :: ARM_REG_SP ; } impl arm_reg { pub const ARM_REG_R14 : arm_reg = arm_reg :: ARM_REG_LR ; } impl arm_reg { pub const ARM_REG_R15 : arm_reg = arm_reg :: ARM_REG_PC ; } impl arm_reg { pub const ARM_REG_SB : arm_reg = arm_reg :: ARM_REG_R9 ; } impl arm_reg { pub const ARM_REG_SL : arm_reg = arm_reg :: ARM_REG_R10 ; } impl arm_reg { pub const ARM_REG_FP : arm_reg = arm_reg :: ARM_REG_R11 ; } impl arm_reg { pub const ARM_REG_IP : arm_reg = arm_reg :: ARM_REG_R12 ; } # [repr (u32)] # [doc = " ARM registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_reg { ARM_REG_INVALID = 0 , ARM_REG_APSR = 1 , ARM_REG_APSR_NZCV = 2 , ARM_REG_CPSR = 3 , ARM_REG_FPEXC = 4 , ARM_REG_FPINST = 5 , ARM_REG_FPSCR = 6 , ARM_REG_FPSCR_NZCV = 7 , ARM_REG_FPSID = 8 , ARM_REG_ITSTATE = 9 , ARM_REG_LR = 10 , ARM_REG_PC = 11 , ARM_REG_SP = 12 , ARM_REG_SPSR = 13 , ARM_REG_D0 = 14 , ARM_REG_D1 = 15 , ARM_REG_D2 = 16 , ARM_REG_D3 = 17 , ARM_REG_D4 = 18 , ARM_REG_D5 = 19 , ARM_REG_D6 = 20 , ARM_REG_D7 = 21 , ARM_REG_D8 = 22 , ARM_REG_D9 = 23 , ARM_REG_D10 = 24 , ARM_REG_D11 = 25 , ARM_REG_D12 = 26 , ARM_REG_D13 = 27 , ARM_REG_D14 = 28 , ARM_REG_D15 = 29 , ARM_REG_D16 = 30 , ARM_REG_D17 = 31 , ARM_REG_D18 = 32 , ARM_REG_D19 = 33 , ARM_REG_D20 = 34 , ARM_REG_D21 = 35 , ARM_REG_D22 = 36 , ARM_REG_D23 = 37 , ARM_REG_D24 = 38 , ARM_REG_D25 = 39 , ARM_REG_D26 = 40 , ARM_REG_D27 = 41 , ARM_REG_D28 = 42 , ARM_REG_D29 = 43 , ARM_REG_D30 = 44 , ARM_REG_D31 = 45 , ARM_REG_FPINST2 = 46 , ARM_REG_MVFR0 = 47 , ARM_REG_MVFR1 = 48 , ARM_REG_MVFR2 = 49 , ARM_REG_Q0 = 50 , ARM_REG_Q1 = 51 , ARM_REG_Q2 = 52 , ARM_REG_Q3 = 53 , ARM_REG_Q4 = 54 , ARM_REG_Q5 = 55 , ARM_REG_Q6 = 56 , ARM_REG_Q7 = 57 , ARM_REG_Q8 = 58 , ARM_REG_Q9 = 59 , ARM_REG_Q10 = 60 , ARM_REG_Q11 = 61 , ARM_REG_Q12 = 62 , ARM_REG_Q13 = 63 , ARM_REG_Q14 = 64 , ARM_REG_Q15 = 65 , ARM_REG_R0 = 66 , ARM_REG_R1 = 67 , ARM_REG_R2 = 68 , ARM_REG_R3 = 69 , ARM_REG_R4 = 70 , ARM_REG_R5 = 71 , ARM_REG_R6 = 72 , ARM_REG_R7 = 73 , ARM_REG_R8 = 74 , ARM_REG_R9 = 75 , ARM_REG_R10 = 76 , ARM_REG_R11 = 77 , ARM_REG_R12 = 78 , ARM_REG_S0 = 79 , ARM_REG_S1 = 80 , ARM_REG_S2 = 81 , ARM_REG_S3 = 82 , ARM_REG_S4 = 83 , ARM_REG_S5 = 84 , ARM_REG_S6 = 85 , ARM_REG_S7 = 86 , ARM_REG_S8 = 87 , ARM_REG_S9 = 88 , ARM_REG_S10 = 89 , ARM_REG_S11 = 90 , ARM_REG_S12 = 91 , ARM_REG_S13 = 92 , ARM_REG_S14 = 93 , ARM_REG_S15 = 94 , ARM_REG_S16 = 95 , ARM_REG_S17 = 96 , ARM_REG_S18 = 97 , ARM_REG_S19 = 98 , ARM_REG_S20 = 99 , ARM_REG_S21 = 100 , ARM_REG_S22 = 101 , ARM_REG_S23 = 102 , ARM_REG_S24 = 103 , ARM_REG_S25 = 104 , ARM_REG_S26 = 105 , ARM_REG_S27 = 106 , ARM_REG_S28 = 107 , ARM_REG_S29 = 108 , ARM_REG_S30 = 109 , ARM_REG_S31 = 110 , ARM_REG_ENDING = 111 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm_op_mem { # [doc = "< base register"] pub base : arm_reg , # [doc = "< index register"] pub index : arm_reg , # [doc = "< scale for index register (can be 1, or -1)"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_int , # [doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"] pub lshift : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm_op_mem"] [:: std :: mem :: size_of :: < arm_op_mem > () - 20usize] ; ["Alignment of arm_op_mem"] [:: std :: mem :: align_of :: < arm_op_mem > () - 4usize] ; ["Offset of field: arm_op_mem::base"] [:: std :: mem :: offset_of ! (arm_op_mem , base) - 0usize] ; ["Offset of field: arm_op_mem::index"] [:: std :: mem :: offset_of ! (arm_op_mem , index) - 4usize] ; ["Offset of field: arm_op_mem::scale"] [:: std :: mem :: offset_of ! (arm_op_mem , scale) - 8usize] ; ["Offset of field: arm_op_mem::disp"] [:: std :: mem :: offset_of ! (arm_op_mem , disp) - 12usize] ; ["Offset of field: arm_op_mem::lshift"] [:: std :: mem :: offset_of ! (arm_op_mem , lshift) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm_op { # [doc = "< Vector Index for some vector operands (or -1 if irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , pub shift : cs_arm_op__bindgen_ty_1 , # [doc = "< operand type"] pub type_ : arm_op_type , pub __bindgen_anon_1 : cs_arm_op__bindgen_ty_2 , # [doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."] pub subtracted : bool , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"] pub neon_lane : i8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm_op__bindgen_ty_1 { pub type_ : arm_shifter , pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm_op__bindgen_ty_2 { # [doc = "< register value for REG/SYSREG operand"] pub reg : :: std :: os :: raw :: c_int , # [doc = "< immediate value for C-IMM, P-IMM or IMM operand"] pub imm : i32 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm_op_mem , # [doc = "< SETEND instruction's operand type"] pub setend : arm_setend_type , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_2 > () - 24usize] ; ["Alignment of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::setend"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , setend) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op"] [:: std :: mem :: size_of :: < cs_arm_op > () - 48usize] ; ["Alignment of cs_arm_op"] [:: std :: mem :: align_of :: < cs_arm_op > () - 8usize] ; ["Offset of field: cs_arm_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm_op , vector_index) - 0usize] ; ["Offset of field: cs_arm_op::shift"] [:: std :: mem :: offset_of ! (cs_arm_op , shift) - 4usize] ; ["Offset of field: cs_arm_op::type_"] [:: std :: mem :: offset_of ! (cs_arm_op , type_) - 12usize] ; ["Offset of field: cs_arm_op::subtracted"] [:: std :: mem :: offset_of ! (cs_arm_op , subtracted) - 40usize] ; ["Offset of field: cs_arm_op::access"] [:: std :: mem :: offset_of ! (cs_arm_op , access) - 41usize] ; ["Offset of field: cs_arm_op::neon_lane"] [:: std :: mem :: offset_of ! (cs_arm_op , neon_lane) - 42usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm { # [doc = "< User-mode registers to be loaded (for LDM/STM instructions)"] pub usermode : bool , # [doc = "< Scalar size for vector instructions"] pub vector_size : :: std :: os :: raw :: c_int , # [doc = "< Data type for elements of vector instructions"] pub vector_data : arm_vectordata_type , # [doc = "< CPS mode for CPS instruction"] pub cps_mode : arm_cpsmode_type , # [doc = "< CPS mode for CPS instruction"] pub cps_flag : arm_cpsflag_type , # [doc = "< conditional code for this insn"] pub cc : arm_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn write-back?"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = "< Option for some memory barrier instructions"] pub mem_barrier : arm_mem_barrier , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm_op ; 36usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm"] [:: std :: mem :: size_of :: < cs_arm > () - 1768usize] ; ["Alignment of cs_arm"] [:: std :: mem :: align_of :: < cs_arm > () - 8usize] ; ["Offset of field: cs_arm::usermode"] [:: std :: mem :: offset_of ! (cs_arm , usermode) - 0usize] ; ["Offset of field: cs_arm::vector_size"] [:: std :: mem :: offset_of ! (cs_arm , vector_size) - 4usize] ; ["Offset of field: cs_arm::vector_data"] [:: std :: mem :: offset_of ! (cs_arm , vector_data) - 8usize] ; ["Offset of field: cs_arm::cps_mode"] [:: std :: mem :: offset_of ! (cs_arm , cps_mode) - 12usize] ; ["Offset of field: cs_arm::cps_flag"] [:: std :: mem :: offset_of ! (cs_arm , cps_flag) - 16usize] ; ["Offset of field: cs_arm::cc"] [:: std :: mem :: offset_of ! (cs_arm , cc) - 20usize] ; ["Offset of field: cs_arm::update_flags"] [:: std :: mem :: offset_of ! (cs_arm , update_flags) - 24usize] ; ["Offset of field: cs_arm::writeback"] [:: std :: mem :: offset_of ! (cs_arm , writeback) - 25usize] ; ["Offset of field: cs_arm::post_index"] [:: std :: mem :: offset_of ! (cs_arm , post_index) - 26usize] ; ["Offset of field: cs_arm::mem_barrier"] [:: std :: mem :: offset_of ! (cs_arm , mem_barrier) - 28usize] ; ["Offset of field: cs_arm::op_count"] [:: std :: mem :: offset_of ! (cs_arm , op_count) - 32usize] ; ["Offset of field: cs_arm::operands"] [:: std :: mem :: offset_of ! (cs_arm , operands) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_arm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . post_index , self . mem_barrier , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn { ARM_INS_INVALID = 0 , ARM_INS_ADC = 1 , ARM_INS_ADD = 2 , ARM_INS_ADDW = 3 , ARM_INS_ADR = 4 , ARM_INS_AESD = 5 , ARM_INS_AESE = 6 , ARM_INS_AESIMC = 7 , ARM_INS_AESMC = 8 , ARM_INS_AND = 9 , ARM_INS_ASR = 10 , ARM_INS_B = 11 , ARM_INS_BFC = 12 , ARM_INS_BFI = 13 , ARM_INS_BIC = 14 , ARM_INS_BKPT = 15 , ARM_INS_BL = 16 , ARM_INS_BLX = 17 , ARM_INS_BLXNS = 18 , ARM_INS_BX = 19 , ARM_INS_BXJ = 20 , ARM_INS_BXNS = 21 , ARM_INS_CBNZ = 22 , ARM_INS_CBZ = 23 , ARM_INS_CDP = 24 , ARM_INS_CDP2 = 25 , ARM_INS_CLREX = 26 , ARM_INS_CLZ = 27 , ARM_INS_CMN = 28 , ARM_INS_CMP = 29 , ARM_INS_CPS = 30 , ARM_INS_CRC32B = 31 , ARM_INS_CRC32CB = 32 , ARM_INS_CRC32CH = 33 , ARM_INS_CRC32CW = 34 , ARM_INS_CRC32H = 35 , ARM_INS_CRC32W = 36 , ARM_INS_CSDB = 37 , ARM_INS_DBG = 38 , ARM_INS_DCPS1 = 39 , ARM_INS_DCPS2 = 40 , ARM_INS_DCPS3 = 41 , ARM_INS_DFB = 42 , ARM_INS_DMB = 43 , ARM_INS_DSB = 44 , ARM_INS_EOR = 45 , ARM_INS_ERET = 46 , ARM_INS_ESB = 47 , ARM_INS_FADDD = 48 , ARM_INS_FADDS = 49 , ARM_INS_FCMPZD = 50 , ARM_INS_FCMPZS = 51 , ARM_INS_FCONSTD = 52 , ARM_INS_FCONSTS = 53 , ARM_INS_FLDMDBX = 54 , ARM_INS_FLDMIAX = 55 , ARM_INS_FMDHR = 56 , ARM_INS_FMDLR = 57 , ARM_INS_FMSTAT = 58 , ARM_INS_FSTMDBX = 59 , ARM_INS_FSTMIAX = 60 , ARM_INS_FSUBD = 61 , ARM_INS_FSUBS = 62 , ARM_INS_HINT = 63 , ARM_INS_HLT = 64 , ARM_INS_HVC = 65 , ARM_INS_ISB = 66 , ARM_INS_IT = 67 , ARM_INS_LDA = 68 , ARM_INS_LDAB = 69 , ARM_INS_LDAEX = 70 , ARM_INS_LDAEXB = 71 , ARM_INS_LDAEXD = 72 , ARM_INS_LDAEXH = 73 , ARM_INS_LDAH = 74 , ARM_INS_LDC = 75 , ARM_INS_LDC2 = 76 , ARM_INS_LDC2L = 77 , ARM_INS_LDCL = 78 , ARM_INS_LDM = 79 , ARM_INS_LDMDA = 80 , ARM_INS_LDMDB = 81 , ARM_INS_LDMIB = 82 , ARM_INS_LDR = 83 , ARM_INS_LDRB = 84 , ARM_INS_LDRBT = 85 , ARM_INS_LDRD = 86 , ARM_INS_LDREX = 87 , ARM_INS_LDREXB = 88 , ARM_INS_LDREXD = 89 , ARM_INS_LDREXH = 90 , ARM_INS_LDRH = 91 , ARM_INS_LDRHT = 92 , ARM_INS_LDRSB = 93 , ARM_INS_LDRSBT = 94 , ARM_INS_LDRSH = 95 , ARM_INS_LDRSHT = 96 , ARM_INS_LDRT = 97 , ARM_INS_LSL = 98 , ARM_INS_LSR = 99 , ARM_INS_MCR = 100 , ARM_INS_MCR2 = 101 , ARM_INS_MCRR = 102 , ARM_INS_MCRR2 = 103 , ARM_INS_MLA = 104 , ARM_INS_MLS = 105 , ARM_INS_MOV = 106 , ARM_INS_MOVS = 107 , ARM_INS_MOVT = 108 , ARM_INS_MOVW = 109 , ARM_INS_MRC = 110 , ARM_INS_MRC2 = 111 , ARM_INS_MRRC = 112 , ARM_INS_MRRC2 = 113 , ARM_INS_MRS = 114 , ARM_INS_MSR = 115 , ARM_INS_MUL = 116 , ARM_INS_MVN = 117 , ARM_INS_NEG = 118 , ARM_INS_NOP = 119 , ARM_INS_ORN = 120 , ARM_INS_ORR = 121 , ARM_INS_PKHBT = 122 , ARM_INS_PKHTB = 123 , ARM_INS_PLD = 124 , ARM_INS_PLDW = 125 , ARM_INS_PLI = 126 , ARM_INS_POP = 127 , ARM_INS_PUSH = 128 , ARM_INS_QADD = 129 , ARM_INS_QADD16 = 130 , ARM_INS_QADD8 = 131 , ARM_INS_QASX = 132 , ARM_INS_QDADD = 133 , ARM_INS_QDSUB = 134 , ARM_INS_QSAX = 135 , ARM_INS_QSUB = 136 , ARM_INS_QSUB16 = 137 , ARM_INS_QSUB8 = 138 , ARM_INS_RBIT = 139 , ARM_INS_REV = 140 , ARM_INS_REV16 = 141 , ARM_INS_REVSH = 142 , ARM_INS_RFEDA = 143 , ARM_INS_RFEDB = 144 , ARM_INS_RFEIA = 145 , ARM_INS_RFEIB = 146 , ARM_INS_ROR = 147 , ARM_INS_RRX = 148 , ARM_INS_RSB = 149 , ARM_INS_RSC = 150 , ARM_INS_SADD16 = 151 , ARM_INS_SADD8 = 152 , ARM_INS_SASX = 153 , ARM_INS_SBC = 154 , ARM_INS_SBFX = 155 , ARM_INS_SDIV = 156 , ARM_INS_SEL = 157 , ARM_INS_SETEND = 158 , ARM_INS_SETPAN = 159 , ARM_INS_SEV = 160 , ARM_INS_SEVL = 161 , ARM_INS_SG = 162 , ARM_INS_SHA1C = 163 , ARM_INS_SHA1H = 164 , ARM_INS_SHA1M = 165 , ARM_INS_SHA1P = 166 , ARM_INS_SHA1SU0 = 167 , ARM_INS_SHA1SU1 = 168 , ARM_INS_SHA256H = 169 , ARM_INS_SHA256H2 = 170 , ARM_INS_SHA256SU0 = 171 , ARM_INS_SHA256SU1 = 172 , ARM_INS_SHADD16 = 173 , ARM_INS_SHADD8 = 174 , ARM_INS_SHASX = 175 , ARM_INS_SHSAX = 176 , ARM_INS_SHSUB16 = 177 , ARM_INS_SHSUB8 = 178 , ARM_INS_SMC = 179 , ARM_INS_SMLABB = 180 , ARM_INS_SMLABT = 181 , ARM_INS_SMLAD = 182 , ARM_INS_SMLADX = 183 , ARM_INS_SMLAL = 184 , ARM_INS_SMLALBB = 185 , ARM_INS_SMLALBT = 186 , ARM_INS_SMLALD = 187 , ARM_INS_SMLALDX = 188 , ARM_INS_SMLALTB = 189 , ARM_INS_SMLALTT = 190 , ARM_INS_SMLATB = 191 , ARM_INS_SMLATT = 192 , ARM_INS_SMLAWB = 193 , ARM_INS_SMLAWT = 194 , ARM_INS_SMLSD = 195 , ARM_INS_SMLSDX = 196 , ARM_INS_SMLSLD = 197 , ARM_INS_SMLSLDX = 198 , ARM_INS_SMMLA = 199 , ARM_INS_SMMLAR = 200 , ARM_INS_SMMLS = 201 , ARM_INS_SMMLSR = 202 , ARM_INS_SMMUL = 203 , ARM_INS_SMMULR = 204 , ARM_INS_SMUAD = 205 , ARM_INS_SMUADX = 206 , ARM_INS_SMULBB = 207 , ARM_INS_SMULBT = 208 , ARM_INS_SMULL = 209 , ARM_INS_SMULTB = 210 , ARM_INS_SMULTT = 211 , ARM_INS_SMULWB = 212 , ARM_INS_SMULWT = 213 , ARM_INS_SMUSD = 214 , ARM_INS_SMUSDX = 215 , ARM_INS_SRSDA = 216 , ARM_INS_SRSDB = 217 , ARM_INS_SRSIA = 218 , ARM_INS_SRSIB = 219 , ARM_INS_SSAT = 220 , ARM_INS_SSAT16 = 221 , ARM_INS_SSAX = 222 , ARM_INS_SSUB16 = 223 , ARM_INS_SSUB8 = 224 , ARM_INS_STC = 225 , ARM_INS_STC2 = 226 , ARM_INS_STC2L = 227 , ARM_INS_STCL = 228 , ARM_INS_STL = 229 , ARM_INS_STLB = 230 , ARM_INS_STLEX = 231 , ARM_INS_STLEXB = 232 , ARM_INS_STLEXD = 233 , ARM_INS_STLEXH = 234 , ARM_INS_STLH = 235 , ARM_INS_STM = 236 , ARM_INS_STMDA = 237 , ARM_INS_STMDB = 238 , ARM_INS_STMIB = 239 , ARM_INS_STR = 240 , ARM_INS_STRB = 241 , ARM_INS_STRBT = 242 , ARM_INS_STRD = 243 , ARM_INS_STREX = 244 , ARM_INS_STREXB = 245 , ARM_INS_STREXD = 246 , ARM_INS_STREXH = 247 , ARM_INS_STRH = 248 , ARM_INS_STRHT = 249 , ARM_INS_STRT = 250 , ARM_INS_SUB = 251 , ARM_INS_SUBS = 252 , ARM_INS_SUBW = 253 , ARM_INS_SVC = 254 , ARM_INS_SWP = 255 , ARM_INS_SWPB = 256 , ARM_INS_SXTAB = 257 , ARM_INS_SXTAB16 = 258 , ARM_INS_SXTAH = 259 , ARM_INS_SXTB = 260 , ARM_INS_SXTB16 = 261 , ARM_INS_SXTH = 262 , ARM_INS_TBB = 263 , ARM_INS_TBH = 264 , ARM_INS_TEQ = 265 , ARM_INS_TRAP = 266 , ARM_INS_TSB = 267 , ARM_INS_TST = 268 , ARM_INS_TT = 269 , ARM_INS_TTA = 270 , ARM_INS_TTAT = 271 , ARM_INS_TTT = 272 , ARM_INS_UADD16 = 273 , ARM_INS_UADD8 = 274 , ARM_INS_UASX = 275 , ARM_INS_UBFX = 276 , ARM_INS_UDF = 277 , ARM_INS_UDIV = 278 , ARM_INS_UHADD16 = 279 , ARM_INS_UHADD8 = 280 , ARM_INS_UHASX = 281 , ARM_INS_UHSAX = 282 , ARM_INS_UHSUB16 = 283 , ARM_INS_UHSUB8 = 284 , ARM_INS_UMAAL = 285 , ARM_INS_UMLAL = 286 , ARM_INS_UMULL = 287 , ARM_INS_UQADD16 = 288 , ARM_INS_UQADD8 = 289 , ARM_INS_UQASX = 290 , ARM_INS_UQSAX = 291 , ARM_INS_UQSUB16 = 292 , ARM_INS_UQSUB8 = 293 , ARM_INS_USAD8 = 294 , ARM_INS_USADA8 = 295 , ARM_INS_USAT = 296 , ARM_INS_USAT16 = 297 , ARM_INS_USAX = 298 , ARM_INS_USUB16 = 299 , ARM_INS_USUB8 = 300 , ARM_INS_UXTAB = 301 , ARM_INS_UXTAB16 = 302 , ARM_INS_UXTAH = 303 , ARM_INS_UXTB = 304 , ARM_INS_UXTB16 = 305 , ARM_INS_UXTH = 306 , ARM_INS_VABA = 307 , ARM_INS_VABAL = 308 , ARM_INS_VABD = 309 , ARM_INS_VABDL = 310 , ARM_INS_VABS = 311 , ARM_INS_VACGE = 312 , ARM_INS_VACGT = 313 , ARM_INS_VACLE = 314 , ARM_INS_VACLT = 315 , ARM_INS_VADD = 316 , ARM_INS_VADDHN = 317 , ARM_INS_VADDL = 318 , ARM_INS_VADDW = 319 , ARM_INS_VAND = 320 , ARM_INS_VBIC = 321 , ARM_INS_VBIF = 322 , ARM_INS_VBIT = 323 , ARM_INS_VBSL = 324 , ARM_INS_VCADD = 325 , ARM_INS_VCEQ = 326 , ARM_INS_VCGE = 327 , ARM_INS_VCGT = 328 , ARM_INS_VCLE = 329 , ARM_INS_VCLS = 330 , ARM_INS_VCLT = 331 , ARM_INS_VCLZ = 332 , ARM_INS_VCMLA = 333 , ARM_INS_VCMP = 334 , ARM_INS_VCMPE = 335 , ARM_INS_VCNT = 336 , ARM_INS_VCVT = 337 , ARM_INS_VCVTA = 338 , ARM_INS_VCVTB = 339 , ARM_INS_VCVTM = 340 , ARM_INS_VCVTN = 341 , ARM_INS_VCVTP = 342 , ARM_INS_VCVTR = 343 , ARM_INS_VCVTT = 344 , ARM_INS_VDIV = 345 , ARM_INS_VDUP = 346 , ARM_INS_VEOR = 347 , ARM_INS_VEXT = 348 , ARM_INS_VFMA = 349 , ARM_INS_VFMS = 350 , ARM_INS_VFNMA = 351 , ARM_INS_VFNMS = 352 , ARM_INS_VHADD = 353 , ARM_INS_VHSUB = 354 , ARM_INS_VINS = 355 , ARM_INS_VJCVT = 356 , ARM_INS_VLD1 = 357 , ARM_INS_VLD2 = 358 , ARM_INS_VLD3 = 359 , ARM_INS_VLD4 = 360 , ARM_INS_VLDMDB = 361 , ARM_INS_VLDMIA = 362 , ARM_INS_VLDR = 363 , ARM_INS_VLLDM = 364 , ARM_INS_VLSTM = 365 , ARM_INS_VMAX = 366 , ARM_INS_VMAXNM = 367 , ARM_INS_VMIN = 368 , ARM_INS_VMINNM = 369 , ARM_INS_VMLA = 370 , ARM_INS_VMLAL = 371 , ARM_INS_VMLS = 372 , ARM_INS_VMLSL = 373 , ARM_INS_VMOV = 374 , ARM_INS_VMOVL = 375 , ARM_INS_VMOVN = 376 , ARM_INS_VMOVX = 377 , ARM_INS_VMRS = 378 , ARM_INS_VMSR = 379 , ARM_INS_VMUL = 380 , ARM_INS_VMULL = 381 , ARM_INS_VMVN = 382 , ARM_INS_VNEG = 383 , ARM_INS_VNMLA = 384 , ARM_INS_VNMLS = 385 , ARM_INS_VNMUL = 386 , ARM_INS_VORN = 387 , ARM_INS_VORR = 388 , ARM_INS_VPADAL = 389 , ARM_INS_VPADD = 390 , ARM_INS_VPADDL = 391 , ARM_INS_VPMAX = 392 , ARM_INS_VPMIN = 393 , ARM_INS_VPOP = 394 , ARM_INS_VPUSH = 395 , ARM_INS_VQABS = 396 , ARM_INS_VQADD = 397 , ARM_INS_VQDMLAL = 398 , ARM_INS_VQDMLSL = 399 , ARM_INS_VQDMULH = 400 , ARM_INS_VQDMULL = 401 , ARM_INS_VQMOVN = 402 , ARM_INS_VQMOVUN = 403 , ARM_INS_VQNEG = 404 , ARM_INS_VQRDMLAH = 405 , ARM_INS_VQRDMLSH = 406 , ARM_INS_VQRDMULH = 407 , ARM_INS_VQRSHL = 408 , ARM_INS_VQRSHRN = 409 , ARM_INS_VQRSHRUN = 410 , ARM_INS_VQSHL = 411 , ARM_INS_VQSHLU = 412 , ARM_INS_VQSHRN = 413 , ARM_INS_VQSHRUN = 414 , ARM_INS_VQSUB = 415 , ARM_INS_VRADDHN = 416 , ARM_INS_VRECPE = 417 , ARM_INS_VRECPS = 418 , ARM_INS_VREV16 = 419 , ARM_INS_VREV32 = 420 , ARM_INS_VREV64 = 421 , ARM_INS_VRHADD = 422 , ARM_INS_VRINTA = 423 , ARM_INS_VRINTM = 424 , ARM_INS_VRINTN = 425 , ARM_INS_VRINTP = 426 , ARM_INS_VRINTR = 427 , ARM_INS_VRINTX = 428 , ARM_INS_VRINTZ = 429 , ARM_INS_VRSHL = 430 , ARM_INS_VRSHR = 431 , ARM_INS_VRSHRN = 432 , ARM_INS_VRSQRTE = 433 , ARM_INS_VRSQRTS = 434 , ARM_INS_VRSRA = 435 , ARM_INS_VRSUBHN = 436 , ARM_INS_VSDOT = 437 , ARM_INS_VSELEQ = 438 , ARM_INS_VSELGE = 439 , ARM_INS_VSELGT = 440 , ARM_INS_VSELVS = 441 , ARM_INS_VSHL = 442 , ARM_INS_VSHLL = 443 , ARM_INS_VSHR = 444 , ARM_INS_VSHRN = 445 , ARM_INS_VSLI = 446 , ARM_INS_VSQRT = 447 , ARM_INS_VSRA = 448 , ARM_INS_VSRI = 449 , ARM_INS_VST1 = 450 , ARM_INS_VST2 = 451 , ARM_INS_VST3 = 452 , ARM_INS_VST4 = 453 , ARM_INS_VSTMDB = 454 , ARM_INS_VSTMIA = 455 , ARM_INS_VSTR = 456 , ARM_INS_VSUB = 457 , ARM_INS_VSUBHN = 458 , ARM_INS_VSUBL = 459 , ARM_INS_VSUBW = 460 , ARM_INS_VSWP = 461 , ARM_INS_VTBL = 462 , ARM_INS_VTBX = 463 , ARM_INS_VTRN = 464 , ARM_INS_VTST = 465 , ARM_INS_VUDOT = 466 , ARM_INS_VUZP = 467 , ARM_INS_VZIP = 468 , ARM_INS_WFE = 469 , ARM_INS_WFI = 470 , ARM_INS_YIELD = 471 , ARM_INS_ENDING = 472 , } # [repr (u32)] # [doc = " Group of ARM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] ARM_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] ARM_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM_GRP_BRANCH_RELATIVE = 7 , ARM_GRP_CRYPTO = 128 , ARM_GRP_DATABARRIER = 129 , ARM_GRP_DIVIDE = 130 , ARM_GRP_FPARMV8 = 131 , ARM_GRP_MULTPRO = 132 , ARM_GRP_NEON = 133 , ARM_GRP_T2EXTRACTPACK = 134 , ARM_GRP_THUMB2DSP = 135 , ARM_GRP_TRUSTZONE = 136 , ARM_GRP_V4T = 137 , ARM_GRP_V5T = 138 , ARM_GRP_V5TE = 139 , ARM_GRP_V6 = 140 , ARM_GRP_V6T2 = 141 , ARM_GRP_V7 = 142 , ARM_GRP_V8 = 143 , ARM_GRP_VFP2 = 144 , ARM_GRP_VFP3 = 145 , ARM_GRP_VFP4 = 146 , ARM_GRP_ARM = 147 , ARM_GRP_MCLASS = 148 , ARM_GRP_NOTMCLASS = 149 , ARM_GRP_THUMB = 150 , ARM_GRP_THUMB1ONLY = 151 , ARM_GRP_THUMB2 = 152 , ARM_GRP_PREV8 = 153 , ARM_GRP_FPVMLX = 154 , ARM_GRP_MULOPS = 155 , ARM_GRP_CRC = 156 , ARM_GRP_DPVFP = 157 , ARM_GRP_V6M = 158 , ARM_GRP_VIRTUALIZATION = 159 , ARM_GRP_ENDING = 160 , } # [repr (u32)] # [doc = " ARM64 shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_shifter { ARM64_SFT_INVALID = 0 , ARM64_SFT_LSL = 1 , ARM64_SFT_MSL = 2 , ARM64_SFT_LSR = 3 , ARM64_SFT_ASR = 4 , ARM64_SFT_ROR = 5 , } # [repr (u32)] # [doc = " ARM64 extender type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_extender { ARM64_EXT_INVALID = 0 , ARM64_EXT_UXTB = 1 , ARM64_EXT_UXTH = 2 , ARM64_EXT_UXTW = 3 , ARM64_EXT_UXTX = 4 , ARM64_EXT_SXTB = 5 , ARM64_EXT_SXTH = 6 , ARM64_EXT_SXTW = 7 , ARM64_EXT_SXTX = 8 , } # [repr (u32)] # [doc = " ARM64 condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_cc { ARM64_CC_INVALID = 0 , # [doc = "< Equal"] ARM64_CC_EQ = 1 , # [doc = "< Not equal:                 Not equal, or unordered"] ARM64_CC_NE = 2 , # [doc = "< Unsigned higher or same:   >, ==, or unordered"] ARM64_CC_HS = 3 , # [doc = "< Unsigned lower or same:    Less than"] ARM64_CC_LO = 4 , # [doc = "< Minus, negative:           Less than"] ARM64_CC_MI = 5 , # [doc = "< Plus, positive or zero:    >, ==, or unordered"] ARM64_CC_PL = 6 , # [doc = "< Overflow:                  Unordered"] ARM64_CC_VS = 7 , # [doc = "< No overflow:               Ordered"] ARM64_CC_VC = 8 , # [doc = "< Unsigned higher:           Greater than, or unordered"] ARM64_CC_HI = 9 , # [doc = "< Unsigned lower or same:    Less than or equal"] ARM64_CC_LS = 10 , # [doc = "< Greater than or equal:     Greater than or equal"] ARM64_CC_GE = 11 , # [doc = "< Less than:                 Less than, or unordered"] ARM64_CC_LT = 12 , # [doc = "< Signed greater than:       Greater than"] ARM64_CC_GT = 13 , # [doc = "< Signed less than or equal: <, ==, or unordered"] ARM64_CC_LE = 14 , # [doc = "< Always (unconditional):    Always (unconditional)"] ARM64_CC_AL = 15 , # [doc = "< Always (unconditional):   Always (unconditional)"] ARM64_CC_NV = 16 , } impl arm64_sysreg { pub const ARM64_SYSREG_DBGDTRTX_EL0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_DBGDTRRX_EL0 ; } impl arm64_sysreg { pub const ARM64_SYSREG_TRCEXTINSELR0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TRCEXTINSELR ; } impl arm64_sysreg { pub const ARM64_SYSREG_VSCTLR_EL2 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TTBR0_EL2 ; } # [repr (u32)] # [doc = " System registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sysreg { ARM64_SYSREG_INVALID = 0 , ARM64_SYSREG_ACCDATA_EL1 = 50821 , ARM64_SYSREG_ACTLR_EL1 = 49281 , ARM64_SYSREG_ACTLR_EL2 = 57473 , ARM64_SYSREG_ACTLR_EL3 = 61569 , ARM64_SYSREG_AFSR0_EL1 = 49800 , ARM64_SYSREG_AFSR0_EL12 = 60040 , ARM64_SYSREG_AFSR0_EL2 = 57992 , ARM64_SYSREG_AFSR0_EL3 = 62088 , ARM64_SYSREG_AFSR1_EL1 = 49801 , ARM64_SYSREG_AFSR1_EL12 = 60041 , ARM64_SYSREG_AFSR1_EL2 = 57993 , ARM64_SYSREG_AFSR1_EL3 = 62089 , ARM64_SYSREG_AIDR_EL1 = 51207 , ARM64_SYSREG_AMAIR_EL1 = 50456 , ARM64_SYSREG_AMAIR_EL12 = 60696 , ARM64_SYSREG_AMAIR_EL2 = 58648 , ARM64_SYSREG_AMAIR_EL3 = 62744 , ARM64_SYSREG_AMCFGR_EL0 = 56977 , ARM64_SYSREG_AMCGCR_EL0 = 56978 , ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980 , ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984 , ARM64_SYSREG_AMCNTENSET0_EL0 = 56981 , ARM64_SYSREG_AMCNTENSET1_EL0 = 56985 , ARM64_SYSREG_AMCR_EL0 = 56976 , ARM64_SYSREG_AMEVCNTR00_EL0 = 56992 , ARM64_SYSREG_AMEVCNTR01_EL0 = 56993 , ARM64_SYSREG_AMEVCNTR02_EL0 = 56994 , ARM64_SYSREG_AMEVCNTR03_EL0 = 56995 , ARM64_SYSREG_AMEVCNTR10_EL0 = 57056 , ARM64_SYSREG_AMEVCNTR110_EL0 = 57066 , ARM64_SYSREG_AMEVCNTR111_EL0 = 57067 , ARM64_SYSREG_AMEVCNTR112_EL0 = 57068 , ARM64_SYSREG_AMEVCNTR113_EL0 = 57069 , ARM64_SYSREG_AMEVCNTR114_EL0 = 57070 , ARM64_SYSREG_AMEVCNTR115_EL0 = 57071 , ARM64_SYSREG_AMEVCNTR11_EL0 = 57057 , ARM64_SYSREG_AMEVCNTR12_EL0 = 57058 , ARM64_SYSREG_AMEVCNTR13_EL0 = 57059 , ARM64_SYSREG_AMEVCNTR14_EL0 = 57060 , ARM64_SYSREG_AMEVCNTR15_EL0 = 57061 , ARM64_SYSREG_AMEVCNTR16_EL0 = 57062 , ARM64_SYSREG_AMEVCNTR17_EL0 = 57063 , ARM64_SYSREG_AMEVCNTR18_EL0 = 57064 , ARM64_SYSREG_AMEVCNTR19_EL0 = 57065 , ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 59072 , ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 59082 , ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 59083 , ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 59084 , ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 59085 , ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 59086 , ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 59087 , ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 59073 , ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 59074 , ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 59075 , ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 59076 , ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 59077 , ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 59078 , ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 59079 , ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 59080 , ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 59081 , ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 59088 , ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 59098 , ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 59099 , ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 59100 , ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 59101 , ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 59102 , ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 59103 , ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 59089 , ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 59090 , ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 59091 , ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 59092 , ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 59093 , ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 59094 , ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 59095 , ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 59096 , ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 59097 , ARM64_SYSREG_AMEVTYPER00_EL0 = 57008 , ARM64_SYSREG_AMEVTYPER01_EL0 = 57009 , ARM64_SYSREG_AMEVTYPER02_EL0 = 57010 , ARM64_SYSREG_AMEVTYPER03_EL0 = 57011 , ARM64_SYSREG_AMEVTYPER10_EL0 = 57072 , ARM64_SYSREG_AMEVTYPER110_EL0 = 57082 , ARM64_SYSREG_AMEVTYPER111_EL0 = 57083 , ARM64_SYSREG_AMEVTYPER112_EL0 = 57084 , ARM64_SYSREG_AMEVTYPER113_EL0 = 57085 , ARM64_SYSREG_AMEVTYPER114_EL0 = 57086 , ARM64_SYSREG_AMEVTYPER115_EL0 = 57087 , ARM64_SYSREG_AMEVTYPER11_EL0 = 57073 , ARM64_SYSREG_AMEVTYPER12_EL0 = 57074 , ARM64_SYSREG_AMEVTYPER13_EL0 = 57075 , ARM64_SYSREG_AMEVTYPER14_EL0 = 57076 , ARM64_SYSREG_AMEVTYPER15_EL0 = 57077 , ARM64_SYSREG_AMEVTYPER16_EL0 = 57078 , ARM64_SYSREG_AMEVTYPER17_EL0 = 57079 , ARM64_SYSREG_AMEVTYPER18_EL0 = 57080 , ARM64_SYSREG_AMEVTYPER19_EL0 = 57081 , ARM64_SYSREG_AMUSERENR_EL0 = 56979 , ARM64_SYSREG_APDAKEYHI_EL1 = 49425 , ARM64_SYSREG_APDAKEYLO_EL1 = 49424 , ARM64_SYSREG_APDBKEYHI_EL1 = 49427 , ARM64_SYSREG_APDBKEYLO_EL1 = 49426 , ARM64_SYSREG_APGAKEYHI_EL1 = 49433 , ARM64_SYSREG_APGAKEYLO_EL1 = 49432 , ARM64_SYSREG_APIAKEYHI_EL1 = 49417 , ARM64_SYSREG_APIAKEYLO_EL1 = 49416 , ARM64_SYSREG_APIBKEYHI_EL1 = 49419 , ARM64_SYSREG_APIBKEYLO_EL1 = 49418 , ARM64_SYSREG_BRBCR_EL1 = 35968 , ARM64_SYSREG_BRBCR_EL12 = 44160 , ARM64_SYSREG_BRBCR_EL2 = 42112 , ARM64_SYSREG_BRBFCR_EL1 = 35969 , ARM64_SYSREG_BRBIDR0_EL1 = 35984 , ARM64_SYSREG_BRBINF0_EL1 = 35840 , ARM64_SYSREG_BRBINF10_EL1 = 35920 , ARM64_SYSREG_BRBINF11_EL1 = 35928 , ARM64_SYSREG_BRBINF12_EL1 = 35936 , ARM64_SYSREG_BRBINF13_EL1 = 35944 , ARM64_SYSREG_BRBINF14_EL1 = 35952 , ARM64_SYSREG_BRBINF15_EL1 = 35960 , ARM64_SYSREG_BRBINF16_EL1 = 35844 , ARM64_SYSREG_BRBINF17_EL1 = 35852 , ARM64_SYSREG_BRBINF18_EL1 = 35860 , ARM64_SYSREG_BRBINF19_EL1 = 35868 , ARM64_SYSREG_BRBINF1_EL1 = 35848 , ARM64_SYSREG_BRBINF20_EL1 = 35876 , ARM64_SYSREG_BRBINF21_EL1 = 35884 , ARM64_SYSREG_BRBINF22_EL1 = 35892 , ARM64_SYSREG_BRBINF23_EL1 = 35900 , ARM64_SYSREG_BRBINF24_EL1 = 35908 , ARM64_SYSREG_BRBINF25_EL1 = 35916 , ARM64_SYSREG_BRBINF26_EL1 = 35924 , ARM64_SYSREG_BRBINF27_EL1 = 35932 , ARM64_SYSREG_BRBINF28_EL1 = 35940 , ARM64_SYSREG_BRBINF29_EL1 = 35948 , ARM64_SYSREG_BRBINF2_EL1 = 35856 , ARM64_SYSREG_BRBINF30_EL1 = 35956 , ARM64_SYSREG_BRBINF31_EL1 = 35964 , ARM64_SYSREG_BRBINF3_EL1 = 35864 , ARM64_SYSREG_BRBINF4_EL1 = 35872 , ARM64_SYSREG_BRBINF5_EL1 = 35880 , ARM64_SYSREG_BRBINF6_EL1 = 35888 , ARM64_SYSREG_BRBINF7_EL1 = 35896 , ARM64_SYSREG_BRBINF8_EL1 = 35904 , ARM64_SYSREG_BRBINF9_EL1 = 35912 , ARM64_SYSREG_BRBINFINJ_EL1 = 35976 , ARM64_SYSREG_BRBSRC0_EL1 = 35841 , ARM64_SYSREG_BRBSRC10_EL1 = 35921 , ARM64_SYSREG_BRBSRC11_EL1 = 35929 , ARM64_SYSREG_BRBSRC12_EL1 = 35937 , ARM64_SYSREG_BRBSRC13_EL1 = 35945 , ARM64_SYSREG_BRBSRC14_EL1 = 35953 , ARM64_SYSREG_BRBSRC15_EL1 = 35961 , ARM64_SYSREG_BRBSRC16_EL1 = 35845 , ARM64_SYSREG_BRBSRC17_EL1 = 35853 , ARM64_SYSREG_BRBSRC18_EL1 = 35861 , ARM64_SYSREG_BRBSRC19_EL1 = 35869 , ARM64_SYSREG_BRBSRC1_EL1 = 35849 , ARM64_SYSREG_BRBSRC20_EL1 = 35877 , ARM64_SYSREG_BRBSRC21_EL1 = 35885 , ARM64_SYSREG_BRBSRC22_EL1 = 35893 , ARM64_SYSREG_BRBSRC23_EL1 = 35901 , ARM64_SYSREG_BRBSRC24_EL1 = 35909 , ARM64_SYSREG_BRBSRC25_EL1 = 35917 , ARM64_SYSREG_BRBSRC26_EL1 = 35925 , ARM64_SYSREG_BRBSRC27_EL1 = 35933 , ARM64_SYSREG_BRBSRC28_EL1 = 35941 , ARM64_SYSREG_BRBSRC29_EL1 = 35949 , ARM64_SYSREG_BRBSRC2_EL1 = 35857 , ARM64_SYSREG_BRBSRC30_EL1 = 35957 , ARM64_SYSREG_BRBSRC31_EL1 = 35965 , ARM64_SYSREG_BRBSRC3_EL1 = 35865 , ARM64_SYSREG_BRBSRC4_EL1 = 35873 , ARM64_SYSREG_BRBSRC5_EL1 = 35881 , ARM64_SYSREG_BRBSRC6_EL1 = 35889 , ARM64_SYSREG_BRBSRC7_EL1 = 35897 , ARM64_SYSREG_BRBSRC8_EL1 = 35905 , ARM64_SYSREG_BRBSRC9_EL1 = 35913 , ARM64_SYSREG_BRBSRCINJ_EL1 = 35977 , ARM64_SYSREG_BRBTGT0_EL1 = 35842 , ARM64_SYSREG_BRBTGT10_EL1 = 35922 , ARM64_SYSREG_BRBTGT11_EL1 = 35930 , ARM64_SYSREG_BRBTGT12_EL1 = 35938 , ARM64_SYSREG_BRBTGT13_EL1 = 35946 , ARM64_SYSREG_BRBTGT14_EL1 = 35954 , ARM64_SYSREG_BRBTGT15_EL1 = 35962 , ARM64_SYSREG_BRBTGT16_EL1 = 35846 , ARM64_SYSREG_BRBTGT17_EL1 = 35854 , ARM64_SYSREG_BRBTGT18_EL1 = 35862 , ARM64_SYSREG_BRBTGT19_EL1 = 35870 , ARM64_SYSREG_BRBTGT1_EL1 = 35850 , ARM64_SYSREG_BRBTGT20_EL1 = 35878 , ARM64_SYSREG_BRBTGT21_EL1 = 35886 , ARM64_SYSREG_BRBTGT22_EL1 = 35894 , ARM64_SYSREG_BRBTGT23_EL1 = 35902 , ARM64_SYSREG_BRBTGT24_EL1 = 35910 , ARM64_SYSREG_BRBTGT25_EL1 = 35918 , ARM64_SYSREG_BRBTGT26_EL1 = 35926 , ARM64_SYSREG_BRBTGT27_EL1 = 35934 , ARM64_SYSREG_BRBTGT28_EL1 = 35942 , ARM64_SYSREG_BRBTGT29_EL1 = 35950 , ARM64_SYSREG_BRBTGT2_EL1 = 35858 , ARM64_SYSREG_BRBTGT30_EL1 = 35958 , ARM64_SYSREG_BRBTGT31_EL1 = 35966 , ARM64_SYSREG_BRBTGT3_EL1 = 35866 , ARM64_SYSREG_BRBTGT4_EL1 = 35874 , ARM64_SYSREG_BRBTGT5_EL1 = 35882 , ARM64_SYSREG_BRBTGT6_EL1 = 35890 , ARM64_SYSREG_BRBTGT7_EL1 = 35898 , ARM64_SYSREG_BRBTGT8_EL1 = 35906 , ARM64_SYSREG_BRBTGT9_EL1 = 35914 , ARM64_SYSREG_BRBTGTINJ_EL1 = 35978 , ARM64_SYSREG_BRBTS_EL1 = 35970 , ARM64_SYSREG_CCSIDR2_EL1 = 51202 , ARM64_SYSREG_CCSIDR_EL1 = 51200 , ARM64_SYSREG_CLIDR_EL1 = 51201 , ARM64_SYSREG_CNTFRQ_EL0 = 57088 , ARM64_SYSREG_CNTHCTL_EL2 = 59144 , ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177 , ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178 , ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176 , ARM64_SYSREG_CNTHP_CTL_EL2 = 59153 , ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154 , ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152 , ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169 , ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170 , ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168 , ARM64_SYSREG_CNTHV_CTL_EL2 = 59161 , ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162 , ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160 , ARM64_SYSREG_CNTISCALE_EL2 = 59141 , ARM64_SYSREG_CNTKCTL_EL1 = 50952 , ARM64_SYSREG_CNTKCTL_EL12 = 61192 , ARM64_SYSREG_CNTPCTSS_EL0 = 57093 , ARM64_SYSREG_CNTPCT_EL0 = 57089 , ARM64_SYSREG_CNTPOFF_EL2 = 59142 , ARM64_SYSREG_CNTPS_CTL_EL1 = 65297 , ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298 , ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296 , ARM64_SYSREG_CNTP_CTL_EL0 = 57105 , ARM64_SYSREG_CNTP_CTL_EL02 = 61201 , ARM64_SYSREG_CNTP_CVAL_EL0 = 57106 , ARM64_SYSREG_CNTP_CVAL_EL02 = 61202 , ARM64_SYSREG_CNTP_TVAL_EL0 = 57104 , ARM64_SYSREG_CNTP_TVAL_EL02 = 61200 , ARM64_SYSREG_CNTSCALE_EL2 = 59140 , ARM64_SYSREG_CNTVCTSS_EL0 = 57094 , ARM64_SYSREG_CNTVCT_EL0 = 57090 , ARM64_SYSREG_CNTVFRQ_EL2 = 59143 , ARM64_SYSREG_CNTVOFF_EL2 = 59139 , ARM64_SYSREG_CNTV_CTL_EL0 = 57113 , ARM64_SYSREG_CNTV_CTL_EL02 = 61209 , ARM64_SYSREG_CNTV_CVAL_EL0 = 57114 , ARM64_SYSREG_CNTV_CVAL_EL02 = 61210 , ARM64_SYSREG_CNTV_TVAL_EL0 = 57112 , ARM64_SYSREG_CNTV_TVAL_EL02 = 61208 , ARM64_SYSREG_CONTEXTIDR_EL1 = 50817 , ARM64_SYSREG_CONTEXTIDR_EL12 = 61057 , ARM64_SYSREG_CONTEXTIDR_EL2 = 59009 , ARM64_SYSREG_CPACR_EL1 = 49282 , ARM64_SYSREG_CPACR_EL12 = 59522 , ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424 , ARM64_SYSREG_CPTR_EL2 = 57482 , ARM64_SYSREG_CPTR_EL3 = 61578 , ARM64_SYSREG_CSSELR_EL1 = 53248 , ARM64_SYSREG_CTR_EL0 = 55297 , ARM64_SYSREG_CURRENTEL = 49682 , ARM64_SYSREG_DACR32_EL2 = 57728 , ARM64_SYSREG_DAIF = 55825 , ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782 , ARM64_SYSREG_DBGBCR0_EL1 = 32773 , ARM64_SYSREG_DBGBCR10_EL1 = 32853 , ARM64_SYSREG_DBGBCR11_EL1 = 32861 , ARM64_SYSREG_DBGBCR12_EL1 = 32869 , ARM64_SYSREG_DBGBCR13_EL1 = 32877 , ARM64_SYSREG_DBGBCR14_EL1 = 32885 , ARM64_SYSREG_DBGBCR15_EL1 = 32893 , ARM64_SYSREG_DBGBCR1_EL1 = 32781 , ARM64_SYSREG_DBGBCR2_EL1 = 32789 , ARM64_SYSREG_DBGBCR3_EL1 = 32797 , ARM64_SYSREG_DBGBCR4_EL1 = 32805 , ARM64_SYSREG_DBGBCR5_EL1 = 32813 , ARM64_SYSREG_DBGBCR6_EL1 = 32821 , ARM64_SYSREG_DBGBCR7_EL1 = 32829 , ARM64_SYSREG_DBGBCR8_EL1 = 32837 , ARM64_SYSREG_DBGBCR9_EL1 = 32845 , ARM64_SYSREG_DBGBVR0_EL1 = 32772 , ARM64_SYSREG_DBGBVR10_EL1 = 32852 , ARM64_SYSREG_DBGBVR11_EL1 = 32860 , ARM64_SYSREG_DBGBVR12_EL1 = 32868 , ARM64_SYSREG_DBGBVR13_EL1 = 32876 , ARM64_SYSREG_DBGBVR14_EL1 = 32884 , ARM64_SYSREG_DBGBVR15_EL1 = 32892 , ARM64_SYSREG_DBGBVR1_EL1 = 32780 , ARM64_SYSREG_DBGBVR2_EL1 = 32788 , ARM64_SYSREG_DBGBVR3_EL1 = 32796 , ARM64_SYSREG_DBGBVR4_EL1 = 32804 , ARM64_SYSREG_DBGBVR5_EL1 = 32812 , ARM64_SYSREG_DBGBVR6_EL1 = 32820 , ARM64_SYSREG_DBGBVR7_EL1 = 32828 , ARM64_SYSREG_DBGBVR8_EL1 = 32836 , ARM64_SYSREG_DBGBVR9_EL1 = 32844 , ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742 , ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734 , ARM64_SYSREG_DBGDTRRX_EL0 = 38952 , ARM64_SYSREG_DBGDTR_EL0 = 38944 , ARM64_SYSREG_DBGPRCR_EL1 = 32932 , ARM64_SYSREG_DBGVCR32_EL2 = 41016 , ARM64_SYSREG_DBGWCR0_EL1 = 32775 , ARM64_SYSREG_DBGWCR10_EL1 = 32855 , ARM64_SYSREG_DBGWCR11_EL1 = 32863 , ARM64_SYSREG_DBGWCR12_EL1 = 32871 , ARM64_SYSREG_DBGWCR13_EL1 = 32879 , ARM64_SYSREG_DBGWCR14_EL1 = 32887 , ARM64_SYSREG_DBGWCR15_EL1 = 32895 , ARM64_SYSREG_DBGWCR1_EL1 = 32783 , ARM64_SYSREG_DBGWCR2_EL1 = 32791 , ARM64_SYSREG_DBGWCR3_EL1 = 32799 , ARM64_SYSREG_DBGWCR4_EL1 = 32807 , ARM64_SYSREG_DBGWCR5_EL1 = 32815 , ARM64_SYSREG_DBGWCR6_EL1 = 32823 , ARM64_SYSREG_DBGWCR7_EL1 = 32831 , ARM64_SYSREG_DBGWCR8_EL1 = 32839 , ARM64_SYSREG_DBGWCR9_EL1 = 32847 , ARM64_SYSREG_DBGWVR0_EL1 = 32774 , ARM64_SYSREG_DBGWVR10_EL1 = 32854 , ARM64_SYSREG_DBGWVR11_EL1 = 32862 , ARM64_SYSREG_DBGWVR12_EL1 = 32870 , ARM64_SYSREG_DBGWVR13_EL1 = 32878 , ARM64_SYSREG_DBGWVR14_EL1 = 32886 , ARM64_SYSREG_DBGWVR15_EL1 = 32894 , ARM64_SYSREG_DBGWVR1_EL1 = 32782 , ARM64_SYSREG_DBGWVR2_EL1 = 32790 , ARM64_SYSREG_DBGWVR3_EL1 = 32798 , ARM64_SYSREG_DBGWVR4_EL1 = 32806 , ARM64_SYSREG_DBGWVR5_EL1 = 32814 , ARM64_SYSREG_DBGWVR6_EL1 = 32822 , ARM64_SYSREG_DBGWVR7_EL1 = 32830 , ARM64_SYSREG_DBGWVR8_EL1 = 32838 , ARM64_SYSREG_DBGWVR9_EL1 = 32846 , ARM64_SYSREG_DCZID_EL0 = 55303 , ARM64_SYSREG_DISR_EL1 = 50697 , ARM64_SYSREG_DIT = 55829 , ARM64_SYSREG_DLR_EL0 = 55849 , ARM64_SYSREG_DSPSR_EL0 = 55848 , ARM64_SYSREG_ELR_EL1 = 49665 , ARM64_SYSREG_ELR_EL12 = 59905 , ARM64_SYSREG_ELR_EL2 = 57857 , ARM64_SYSREG_ELR_EL3 = 61953 , ARM64_SYSREG_ERRIDR_EL1 = 49816 , ARM64_SYSREG_ERRSELR_EL1 = 49817 , ARM64_SYSREG_ERXADDR_EL1 = 49827 , ARM64_SYSREG_ERXCTLR_EL1 = 49825 , ARM64_SYSREG_ERXFR_EL1 = 49824 , ARM64_SYSREG_ERXMISC0_EL1 = 49832 , ARM64_SYSREG_ERXMISC1_EL1 = 49833 , ARM64_SYSREG_ERXMISC2_EL1 = 49834 , ARM64_SYSREG_ERXMISC3_EL1 = 49835 , ARM64_SYSREG_ERXPFGCDN_EL1 = 49830 , ARM64_SYSREG_ERXPFGCTL_EL1 = 49829 , ARM64_SYSREG_ERXPFGF_EL1 = 49828 , ARM64_SYSREG_ERXSTATUS_EL1 = 49826 , ARM64_SYSREG_ESR_EL1 = 49808 , ARM64_SYSREG_ESR_EL12 = 60048 , ARM64_SYSREG_ESR_EL2 = 58000 , ARM64_SYSREG_ESR_EL3 = 62096 , ARM64_SYSREG_FAR_EL1 = 49920 , ARM64_SYSREG_FAR_EL12 = 60160 , ARM64_SYSREG_FAR_EL2 = 58112 , ARM64_SYSREG_FAR_EL3 = 62208 , ARM64_SYSREG_FPCR = 55840 , ARM64_SYSREG_FPEXC32_EL2 = 58008 , ARM64_SYSREG_FPSR = 55841 , ARM64_SYSREG_GCR_EL1 = 49286 , ARM64_SYSREG_GMID_EL1 = 51204 , ARM64_SYSREG_GPCCR_EL3 = 61710 , ARM64_SYSREG_GPTBR_EL3 = 61708 , ARM64_SYSREG_HACR_EL2 = 57487 , ARM64_SYSREG_HCRX_EL2 = 57490 , ARM64_SYSREG_HCR_EL2 = 57480 , ARM64_SYSREG_HDFGRTR_EL2 = 57740 , ARM64_SYSREG_HDFGWTR_EL2 = 57741 , ARM64_SYSREG_HFGITR_EL2 = 57486 , ARM64_SYSREG_HFGRTR_EL2 = 57484 , ARM64_SYSREG_HFGWTR_EL2 = 57485 , ARM64_SYSREG_HPFAR_EL2 = 58116 , ARM64_SYSREG_HSTR_EL2 = 57483 , ARM64_SYSREG_ICC_AP0R0_EL1 = 50756 , ARM64_SYSREG_ICC_AP0R1_EL1 = 50757 , ARM64_SYSREG_ICC_AP0R2_EL1 = 50758 , ARM64_SYSREG_ICC_AP0R3_EL1 = 50759 , ARM64_SYSREG_ICC_AP1R0_EL1 = 50760 , ARM64_SYSREG_ICC_AP1R1_EL1 = 50761 , ARM64_SYSREG_ICC_AP1R2_EL1 = 50762 , ARM64_SYSREG_ICC_AP1R3_EL1 = 50763 , ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782 , ARM64_SYSREG_ICC_BPR0_EL1 = 50755 , ARM64_SYSREG_ICC_BPR1_EL1 = 50787 , ARM64_SYSREG_ICC_CTLR_EL1 = 50788 , ARM64_SYSREG_ICC_CTLR_EL3 = 63076 , ARM64_SYSREG_ICC_DIR_EL1 = 50777 , ARM64_SYSREG_ICC_EOIR0_EL1 = 50753 , ARM64_SYSREG_ICC_EOIR1_EL1 = 50785 , ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754 , ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786 , ARM64_SYSREG_ICC_IAR0_EL1 = 50752 , ARM64_SYSREG_ICC_IAR1_EL1 = 50784 , ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790 , ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791 , ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079 , ARM64_SYSREG_ICC_PMR_EL1 = 49712 , ARM64_SYSREG_ICC_RPR_EL1 = 50779 , ARM64_SYSREG_ICC_SGI0R_EL1 = 50783 , ARM64_SYSREG_ICC_SGI1R_EL1 = 50781 , ARM64_SYSREG_ICC_SRE_EL1 = 50789 , ARM64_SYSREG_ICC_SRE_EL2 = 58957 , ARM64_SYSREG_ICC_SRE_EL3 = 63077 , ARM64_SYSREG_ICH_AP0R0_EL2 = 58944 , ARM64_SYSREG_ICH_AP0R1_EL2 = 58945 , ARM64_SYSREG_ICH_AP0R2_EL2 = 58946 , ARM64_SYSREG_ICH_AP0R3_EL2 = 58947 , ARM64_SYSREG_ICH_AP1R0_EL2 = 58952 , ARM64_SYSREG_ICH_AP1R1_EL2 = 58953 , ARM64_SYSREG_ICH_AP1R2_EL2 = 58954 , ARM64_SYSREG_ICH_AP1R3_EL2 = 58955 , ARM64_SYSREG_ICH_EISR_EL2 = 58971 , ARM64_SYSREG_ICH_ELRSR_EL2 = 58973 , ARM64_SYSREG_ICH_HCR_EL2 = 58968 , ARM64_SYSREG_ICH_LR0_EL2 = 58976 , ARM64_SYSREG_ICH_LR10_EL2 = 58986 , ARM64_SYSREG_ICH_LR11_EL2 = 58987 , ARM64_SYSREG_ICH_LR12_EL2 = 58988 , ARM64_SYSREG_ICH_LR13_EL2 = 58989 , ARM64_SYSREG_ICH_LR14_EL2 = 58990 , ARM64_SYSREG_ICH_LR15_EL2 = 58991 , ARM64_SYSREG_ICH_LR1_EL2 = 58977 , ARM64_SYSREG_ICH_LR2_EL2 = 58978 , ARM64_SYSREG_ICH_LR3_EL2 = 58979 , ARM64_SYSREG_ICH_LR4_EL2 = 58980 , ARM64_SYSREG_ICH_LR5_EL2 = 58981 , ARM64_SYSREG_ICH_LR6_EL2 = 58982 , ARM64_SYSREG_ICH_LR7_EL2 = 58983 , ARM64_SYSREG_ICH_LR8_EL2 = 58984 , ARM64_SYSREG_ICH_LR9_EL2 = 58985 , ARM64_SYSREG_ICH_MISR_EL2 = 58970 , ARM64_SYSREG_ICH_VMCR_EL2 = 58975 , ARM64_SYSREG_ICH_VTR_EL2 = 58969 , ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196 , ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197 , ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192 , ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193 , ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200 , ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201 , ARM64_SYSREG_ID_AA64ISAR2_EL1 = 49202 , ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208 , ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209 , ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210 , ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184 , ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185 , ARM64_SYSREG_ID_AA64SMFR0_EL1 = 49189 , ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188 , ARM64_SYSREG_ID_AFR0_EL1 = 49163 , ARM64_SYSREG_ID_DFR0_EL1 = 49162 , ARM64_SYSREG_ID_ISAR0_EL1 = 49168 , ARM64_SYSREG_ID_ISAR1_EL1 = 49169 , ARM64_SYSREG_ID_ISAR2_EL1 = 49170 , ARM64_SYSREG_ID_ISAR3_EL1 = 49171 , ARM64_SYSREG_ID_ISAR4_EL1 = 49172 , ARM64_SYSREG_ID_ISAR5_EL1 = 49173 , ARM64_SYSREG_ID_ISAR6_EL1 = 49175 , ARM64_SYSREG_ID_MMFR0_EL1 = 49164 , ARM64_SYSREG_ID_MMFR1_EL1 = 49165 , ARM64_SYSREG_ID_MMFR2_EL1 = 49166 , ARM64_SYSREG_ID_MMFR3_EL1 = 49167 , ARM64_SYSREG_ID_MMFR4_EL1 = 49174 , ARM64_SYSREG_ID_MMFR5_EL1 = 49182 , ARM64_SYSREG_ID_PFR0_EL1 = 49160 , ARM64_SYSREG_ID_PFR1_EL1 = 49161 , ARM64_SYSREG_ID_PFR2_EL1 = 49180 , ARM64_SYSREG_IFSR32_EL2 = 57985 , ARM64_SYSREG_ISR_EL1 = 50696 , ARM64_SYSREG_LORC_EL1 = 50467 , ARM64_SYSREG_LOREA_EL1 = 50465 , ARM64_SYSREG_LORID_EL1 = 50471 , ARM64_SYSREG_LORN_EL1 = 50466 , ARM64_SYSREG_LORSA_EL1 = 50464 , ARM64_SYSREG_MAIR_EL1 = 50448 , ARM64_SYSREG_MAIR_EL12 = 60688 , ARM64_SYSREG_MAIR_EL2 = 58640 , ARM64_SYSREG_MAIR_EL3 = 62736 , ARM64_SYSREG_MDCCINT_EL1 = 32784 , ARM64_SYSREG_MDCCSR_EL0 = 38920 , ARM64_SYSREG_MDCR_EL2 = 57481 , ARM64_SYSREG_MDCR_EL3 = 61593 , ARM64_SYSREG_MDRAR_EL1 = 32896 , ARM64_SYSREG_MDSCR_EL1 = 32786 , ARM64_SYSREG_MFAR_EL3 = 62213 , ARM64_SYSREG_MIDR_EL1 = 49152 , ARM64_SYSREG_MPAM0_EL1 = 50473 , ARM64_SYSREG_MPAM1_EL1 = 50472 , ARM64_SYSREG_MPAM1_EL12 = 60712 , ARM64_SYSREG_MPAM2_EL2 = 58664 , ARM64_SYSREG_MPAM3_EL3 = 62760 , ARM64_SYSREG_MPAMHCR_EL2 = 58656 , ARM64_SYSREG_MPAMIDR_EL1 = 50468 , ARM64_SYSREG_MPAMSM_EL1 = 50475 , ARM64_SYSREG_MPAMVPM0_EL2 = 58672 , ARM64_SYSREG_MPAMVPM1_EL2 = 58673 , ARM64_SYSREG_MPAMVPM2_EL2 = 58674 , ARM64_SYSREG_MPAMVPM3_EL2 = 58675 , ARM64_SYSREG_MPAMVPM4_EL2 = 58676 , ARM64_SYSREG_MPAMVPM5_EL2 = 58677 , ARM64_SYSREG_MPAMVPM6_EL2 = 58678 , ARM64_SYSREG_MPAMVPM7_EL2 = 58679 , ARM64_SYSREG_MPAMVPMV_EL2 = 58657 , ARM64_SYSREG_MPIDR_EL1 = 49157 , ARM64_SYSREG_MPUIR_EL1 = 49156 , ARM64_SYSREG_MPUIR_EL2 = 57348 , ARM64_SYSREG_MVFR0_EL1 = 49176 , ARM64_SYSREG_MVFR1_EL1 = 49177 , ARM64_SYSREG_MVFR2_EL1 = 49178 , ARM64_SYSREG_NZCV = 55824 , ARM64_SYSREG_OSDLR_EL1 = 32924 , ARM64_SYSREG_OSDTRRX_EL1 = 32770 , ARM64_SYSREG_OSDTRTX_EL1 = 32794 , ARM64_SYSREG_OSECCR_EL1 = 32818 , ARM64_SYSREG_OSLAR_EL1 = 32900 , ARM64_SYSREG_OSLSR_EL1 = 32908 , ARM64_SYSREG_PAN = 49683 , ARM64_SYSREG_PAR_EL1 = 50080 , ARM64_SYSREG_PMBIDR_EL1 = 50391 , ARM64_SYSREG_PMBLIMITR_EL1 = 50384 , ARM64_SYSREG_PMBPTR_EL1 = 50385 , ARM64_SYSREG_PMBSR_EL1 = 50387 , ARM64_SYSREG_PMCCFILTR_EL0 = 57215 , ARM64_SYSREG_PMCCNTR_EL0 = 56552 , ARM64_SYSREG_PMCEID0_EL0 = 56550 , ARM64_SYSREG_PMCEID1_EL0 = 56551 , ARM64_SYSREG_PMCNTENCLR_EL0 = 56546 , ARM64_SYSREG_PMCNTENSET_EL0 = 56545 , ARM64_SYSREG_PMCR_EL0 = 56544 , ARM64_SYSREG_PMEVCNTR0_EL0 = 57152 , ARM64_SYSREG_PMEVCNTR10_EL0 = 57162 , ARM64_SYSREG_PMEVCNTR11_EL0 = 57163 , ARM64_SYSREG_PMEVCNTR12_EL0 = 57164 , ARM64_SYSREG_PMEVCNTR13_EL0 = 57165 , ARM64_SYSREG_PMEVCNTR14_EL0 = 57166 , ARM64_SYSREG_PMEVCNTR15_EL0 = 57167 , ARM64_SYSREG_PMEVCNTR16_EL0 = 57168 , ARM64_SYSREG_PMEVCNTR17_EL0 = 57169 , ARM64_SYSREG_PMEVCNTR18_EL0 = 57170 , ARM64_SYSREG_PMEVCNTR19_EL0 = 57171 , ARM64_SYSREG_PMEVCNTR1_EL0 = 57153 , ARM64_SYSREG_PMEVCNTR20_EL0 = 57172 , ARM64_SYSREG_PMEVCNTR21_EL0 = 57173 , ARM64_SYSREG_PMEVCNTR22_EL0 = 57174 , ARM64_SYSREG_PMEVCNTR23_EL0 = 57175 , ARM64_SYSREG_PMEVCNTR24_EL0 = 57176 , ARM64_SYSREG_PMEVCNTR25_EL0 = 57177 , ARM64_SYSREG_PMEVCNTR26_EL0 = 57178 , ARM64_SYSREG_PMEVCNTR27_EL0 = 57179 , ARM64_SYSREG_PMEVCNTR28_EL0 = 57180 , ARM64_SYSREG_PMEVCNTR29_EL0 = 57181 , ARM64_SYSREG_PMEVCNTR2_EL0 = 57154 , ARM64_SYSREG_PMEVCNTR30_EL0 = 57182 , ARM64_SYSREG_PMEVCNTR3_EL0 = 57155 , ARM64_SYSREG_PMEVCNTR4_EL0 = 57156 , ARM64_SYSREG_PMEVCNTR5_EL0 = 57157 , ARM64_SYSREG_PMEVCNTR6_EL0 = 57158 , ARM64_SYSREG_PMEVCNTR7_EL0 = 57159 , ARM64_SYSREG_PMEVCNTR8_EL0 = 57160 , ARM64_SYSREG_PMEVCNTR9_EL0 = 57161 , ARM64_SYSREG_PMEVTYPER0_EL0 = 57184 , ARM64_SYSREG_PMEVTYPER10_EL0 = 57194 , ARM64_SYSREG_PMEVTYPER11_EL0 = 57195 , ARM64_SYSREG_PMEVTYPER12_EL0 = 57196 , ARM64_SYSREG_PMEVTYPER13_EL0 = 57197 , ARM64_SYSREG_PMEVTYPER14_EL0 = 57198 , ARM64_SYSREG_PMEVTYPER15_EL0 = 57199 , ARM64_SYSREG_PMEVTYPER16_EL0 = 57200 , ARM64_SYSREG_PMEVTYPER17_EL0 = 57201 , ARM64_SYSREG_PMEVTYPER18_EL0 = 57202 , ARM64_SYSREG_PMEVTYPER19_EL0 = 57203 , ARM64_SYSREG_PMEVTYPER1_EL0 = 57185 , ARM64_SYSREG_PMEVTYPER20_EL0 = 57204 , ARM64_SYSREG_PMEVTYPER21_EL0 = 57205 , ARM64_SYSREG_PMEVTYPER22_EL0 = 57206 , ARM64_SYSREG_PMEVTYPER23_EL0 = 57207 , ARM64_SYSREG_PMEVTYPER24_EL0 = 57208 , ARM64_SYSREG_PMEVTYPER25_EL0 = 57209 , ARM64_SYSREG_PMEVTYPER26_EL0 = 57210 , ARM64_SYSREG_PMEVTYPER27_EL0 = 57211 , ARM64_SYSREG_PMEVTYPER28_EL0 = 57212 , ARM64_SYSREG_PMEVTYPER29_EL0 = 57213 , ARM64_SYSREG_PMEVTYPER2_EL0 = 57186 , ARM64_SYSREG_PMEVTYPER30_EL0 = 57214 , ARM64_SYSREG_PMEVTYPER3_EL0 = 57187 , ARM64_SYSREG_PMEVTYPER4_EL0 = 57188 , ARM64_SYSREG_PMEVTYPER5_EL0 = 57189 , ARM64_SYSREG_PMEVTYPER6_EL0 = 57190 , ARM64_SYSREG_PMEVTYPER7_EL0 = 57191 , ARM64_SYSREG_PMEVTYPER8_EL0 = 57192 , ARM64_SYSREG_PMEVTYPER9_EL0 = 57193 , ARM64_SYSREG_PMINTENCLR_EL1 = 50418 , ARM64_SYSREG_PMINTENSET_EL1 = 50417 , ARM64_SYSREG_PMMIR_EL1 = 50422 , ARM64_SYSREG_PMOVSCLR_EL0 = 56547 , ARM64_SYSREG_PMOVSSET_EL0 = 56563 , ARM64_SYSREG_PMSCR_EL1 = 50376 , ARM64_SYSREG_PMSCR_EL12 = 60616 , ARM64_SYSREG_PMSCR_EL2 = 58568 , ARM64_SYSREG_PMSELR_EL0 = 56549 , ARM64_SYSREG_PMSEVFR_EL1 = 50381 , ARM64_SYSREG_PMSFCR_EL1 = 50380 , ARM64_SYSREG_PMSICR_EL1 = 50378 , ARM64_SYSREG_PMSIDR_EL1 = 50383 , ARM64_SYSREG_PMSIRR_EL1 = 50379 , ARM64_SYSREG_PMSLATFR_EL1 = 50382 , ARM64_SYSREG_PMSNEVFR_EL1 = 50377 , ARM64_SYSREG_PMSWINC_EL0 = 56548 , ARM64_SYSREG_PMUSERENR_EL0 = 56560 , ARM64_SYSREG_PMXEVCNTR_EL0 = 56554 , ARM64_SYSREG_PMXEVTYPER_EL0 = 56553 , ARM64_SYSREG_PRBAR10_EL1 = 50024 , ARM64_SYSREG_PRBAR10_EL2 = 58216 , ARM64_SYSREG_PRBAR11_EL1 = 50028 , ARM64_SYSREG_PRBAR11_EL2 = 58220 , ARM64_SYSREG_PRBAR12_EL1 = 50032 , ARM64_SYSREG_PRBAR12_EL2 = 58224 , ARM64_SYSREG_PRBAR13_EL1 = 50036 , ARM64_SYSREG_PRBAR13_EL2 = 58228 , ARM64_SYSREG_PRBAR14_EL1 = 50040 , ARM64_SYSREG_PRBAR14_EL2 = 58232 , ARM64_SYSREG_PRBAR15_EL1 = 50044 , ARM64_SYSREG_PRBAR15_EL2 = 58236 , ARM64_SYSREG_PRBAR1_EL1 = 49988 , ARM64_SYSREG_PRBAR1_EL2 = 58180 , ARM64_SYSREG_PRBAR2_EL1 = 49992 , ARM64_SYSREG_PRBAR2_EL2 = 58184 , ARM64_SYSREG_PRBAR3_EL1 = 49996 , ARM64_SYSREG_PRBAR3_EL2 = 58188 , ARM64_SYSREG_PRBAR4_EL1 = 50000 , ARM64_SYSREG_PRBAR4_EL2 = 58192 , ARM64_SYSREG_PRBAR5_EL1 = 50004 , ARM64_SYSREG_PRBAR5_EL2 = 58196 , ARM64_SYSREG_PRBAR6_EL1 = 50008 , ARM64_SYSREG_PRBAR6_EL2 = 58200 , ARM64_SYSREG_PRBAR7_EL1 = 50012 , ARM64_SYSREG_PRBAR7_EL2 = 58204 , ARM64_SYSREG_PRBAR8_EL1 = 50016 , ARM64_SYSREG_PRBAR8_EL2 = 58208 , ARM64_SYSREG_PRBAR9_EL1 = 50020 , ARM64_SYSREG_PRBAR9_EL2 = 58212 , ARM64_SYSREG_PRBAR_EL1 = 49984 , ARM64_SYSREG_PRBAR_EL2 = 58176 , ARM64_SYSREG_PRENR_EL1 = 49929 , ARM64_SYSREG_PRENR_EL2 = 58121 , ARM64_SYSREG_PRLAR10_EL1 = 50025 , ARM64_SYSREG_PRLAR10_EL2 = 58217 , ARM64_SYSREG_PRLAR11_EL1 = 50029 , ARM64_SYSREG_PRLAR11_EL2 = 58221 , ARM64_SYSREG_PRLAR12_EL1 = 50033 , ARM64_SYSREG_PRLAR12_EL2 = 58225 , ARM64_SYSREG_PRLAR13_EL1 = 50037 , ARM64_SYSREG_PRLAR13_EL2 = 58229 , ARM64_SYSREG_PRLAR14_EL1 = 50041 , ARM64_SYSREG_PRLAR14_EL2 = 58233 , ARM64_SYSREG_PRLAR15_EL1 = 50045 , ARM64_SYSREG_PRLAR15_EL2 = 58237 , ARM64_SYSREG_PRLAR1_EL1 = 49989 , ARM64_SYSREG_PRLAR1_EL2 = 58181 , ARM64_SYSREG_PRLAR2_EL1 = 49993 , ARM64_SYSREG_PRLAR2_EL2 = 58185 , ARM64_SYSREG_PRLAR3_EL1 = 49997 , ARM64_SYSREG_PRLAR3_EL2 = 58189 , ARM64_SYSREG_PRLAR4_EL1 = 50001 , ARM64_SYSREG_PRLAR4_EL2 = 58193 , ARM64_SYSREG_PRLAR5_EL1 = 50005 , ARM64_SYSREG_PRLAR5_EL2 = 58197 , ARM64_SYSREG_PRLAR6_EL1 = 50009 , ARM64_SYSREG_PRLAR6_EL2 = 58201 , ARM64_SYSREG_PRLAR7_EL1 = 50013 , ARM64_SYSREG_PRLAR7_EL2 = 58205 , ARM64_SYSREG_PRLAR8_EL1 = 50017 , ARM64_SYSREG_PRLAR8_EL2 = 58209 , ARM64_SYSREG_PRLAR9_EL1 = 50021 , ARM64_SYSREG_PRLAR9_EL2 = 58213 , ARM64_SYSREG_PRLAR_EL1 = 49985 , ARM64_SYSREG_PRLAR_EL2 = 58177 , ARM64_SYSREG_PRSELR_EL1 = 49937 , ARM64_SYSREG_PRSELR_EL2 = 58129 , ARM64_SYSREG_REVIDR_EL1 = 49158 , ARM64_SYSREG_RGSR_EL1 = 49285 , ARM64_SYSREG_RMR_EL1 = 50690 , ARM64_SYSREG_RMR_EL2 = 58882 , ARM64_SYSREG_RMR_EL3 = 62978 , ARM64_SYSREG_RNDR = 55584 , ARM64_SYSREG_RNDRRS = 55585 , ARM64_SYSREG_RVBAR_EL1 = 50689 , ARM64_SYSREG_RVBAR_EL2 = 58881 , ARM64_SYSREG_RVBAR_EL3 = 62977 , ARM64_SYSREG_SCR_EL3 = 61576 , ARM64_SYSREG_SCTLR_EL1 = 49280 , ARM64_SYSREG_SCTLR_EL12 = 59520 , ARM64_SYSREG_SCTLR_EL2 = 57472 , ARM64_SYSREG_SCTLR_EL3 = 61568 , ARM64_SYSREG_SCXTNUM_EL0 = 56967 , ARM64_SYSREG_SCXTNUM_EL1 = 50823 , ARM64_SYSREG_SCXTNUM_EL12 = 61063 , ARM64_SYSREG_SCXTNUM_EL2 = 59015 , ARM64_SYSREG_SCXTNUM_EL3 = 63111 , ARM64_SYSREG_SDER32_EL2 = 57497 , ARM64_SYSREG_SDER32_EL3 = 61577 , ARM64_SYSREG_SMCR_EL1 = 49302 , ARM64_SYSREG_SMCR_EL12 = 59542 , ARM64_SYSREG_SMCR_EL2 = 57494 , ARM64_SYSREG_SMCR_EL3 = 61590 , ARM64_SYSREG_SMIDR_EL1 = 51206 , ARM64_SYSREG_SMPRIMAP_EL2 = 57493 , ARM64_SYSREG_SMPRI_EL1 = 49300 , ARM64_SYSREG_SPSEL = 49680 , ARM64_SYSREG_SPSR_ABT = 57881 , ARM64_SYSREG_SPSR_EL1 = 49664 , ARM64_SYSREG_SPSR_EL12 = 59904 , ARM64_SYSREG_SPSR_EL2 = 57856 , ARM64_SYSREG_SPSR_EL3 = 61952 , ARM64_SYSREG_SPSR_FIQ = 57883 , ARM64_SYSREG_SPSR_IRQ = 57880 , ARM64_SYSREG_SPSR_UND = 57882 , ARM64_SYSREG_SP_EL0 = 49672 , ARM64_SYSREG_SP_EL1 = 57864 , ARM64_SYSREG_SP_EL2 = 61960 , ARM64_SYSREG_SSBS = 55830 , ARM64_SYSREG_SVCR = 55826 , ARM64_SYSREG_TCO = 55831 , ARM64_SYSREG_TCR_EL1 = 49410 , ARM64_SYSREG_TCR_EL12 = 59650 , ARM64_SYSREG_TCR_EL2 = 57602 , ARM64_SYSREG_TCR_EL3 = 61698 , ARM64_SYSREG_TEECR32_EL1 = 36864 , ARM64_SYSREG_TEEHBR32_EL1 = 36992 , ARM64_SYSREG_TFSRE0_EL1 = 49841 , ARM64_SYSREG_TFSR_EL1 = 49840 , ARM64_SYSREG_TFSR_EL12 = 60080 , ARM64_SYSREG_TFSR_EL2 = 58032 , ARM64_SYSREG_TFSR_EL3 = 62128 , ARM64_SYSREG_TPIDR2_EL0 = 56965 , ARM64_SYSREG_TPIDRRO_EL0 = 56963 , ARM64_SYSREG_TPIDR_EL0 = 56962 , ARM64_SYSREG_TPIDR_EL1 = 50820 , ARM64_SYSREG_TPIDR_EL2 = 59010 , ARM64_SYSREG_TPIDR_EL3 = 63106 , ARM64_SYSREG_TRBBASER_EL1 = 50394 , ARM64_SYSREG_TRBIDR_EL1 = 50399 , ARM64_SYSREG_TRBLIMITR_EL1 = 50392 , ARM64_SYSREG_TRBMAR_EL1 = 50396 , ARM64_SYSREG_TRBPTR_EL1 = 50393 , ARM64_SYSREG_TRBSR_EL1 = 50395 , ARM64_SYSREG_TRBTRG_EL1 = 50398 , ARM64_SYSREG_TRCACATR0 = 35074 , ARM64_SYSREG_TRCACATR1 = 35090 , ARM64_SYSREG_TRCACATR10 = 35107 , ARM64_SYSREG_TRCACATR11 = 35123 , ARM64_SYSREG_TRCACATR12 = 35139 , ARM64_SYSREG_TRCACATR13 = 35155 , ARM64_SYSREG_TRCACATR14 = 35171 , ARM64_SYSREG_TRCACATR15 = 35187 , ARM64_SYSREG_TRCACATR2 = 35106 , ARM64_SYSREG_TRCACATR3 = 35122 , ARM64_SYSREG_TRCACATR4 = 35138 , ARM64_SYSREG_TRCACATR5 = 35154 , ARM64_SYSREG_TRCACATR6 = 35170 , ARM64_SYSREG_TRCACATR7 = 35186 , ARM64_SYSREG_TRCACATR8 = 35075 , ARM64_SYSREG_TRCACATR9 = 35091 , ARM64_SYSREG_TRCACVR0 = 35072 , ARM64_SYSREG_TRCACVR1 = 35088 , ARM64_SYSREG_TRCACVR10 = 35105 , ARM64_SYSREG_TRCACVR11 = 35121 , ARM64_SYSREG_TRCACVR12 = 35137 , ARM64_SYSREG_TRCACVR13 = 35153 , ARM64_SYSREG_TRCACVR14 = 35169 , ARM64_SYSREG_TRCACVR15 = 35185 , ARM64_SYSREG_TRCACVR2 = 35104 , ARM64_SYSREG_TRCACVR3 = 35120 , ARM64_SYSREG_TRCACVR4 = 35136 , ARM64_SYSREG_TRCACVR5 = 35152 , ARM64_SYSREG_TRCACVR6 = 35168 , ARM64_SYSREG_TRCACVR7 = 35184 , ARM64_SYSREG_TRCACVR8 = 35073 , ARM64_SYSREG_TRCACVR9 = 35089 , ARM64_SYSREG_TRCAUTHSTATUS = 35830 , ARM64_SYSREG_TRCAUXCTLR = 34864 , ARM64_SYSREG_TRCBBCTLR = 34936 , ARM64_SYSREG_TRCCCCTLR = 34928 , ARM64_SYSREG_TRCCIDCCTLR0 = 35202 , ARM64_SYSREG_TRCCIDCCTLR1 = 35210 , ARM64_SYSREG_TRCCIDCVR0 = 35200 , ARM64_SYSREG_TRCCIDCVR1 = 35216 , ARM64_SYSREG_TRCCIDCVR2 = 35232 , ARM64_SYSREG_TRCCIDCVR3 = 35248 , ARM64_SYSREG_TRCCIDCVR4 = 35264 , ARM64_SYSREG_TRCCIDCVR5 = 35280 , ARM64_SYSREG_TRCCIDCVR6 = 35296 , ARM64_SYSREG_TRCCIDCVR7 = 35312 , ARM64_SYSREG_TRCCIDR0 = 35815 , ARM64_SYSREG_TRCCIDR1 = 35823 , ARM64_SYSREG_TRCCIDR2 = 35831 , ARM64_SYSREG_TRCCIDR3 = 35839 , ARM64_SYSREG_TRCCLAIMCLR = 35790 , ARM64_SYSREG_TRCCLAIMSET = 35782 , ARM64_SYSREG_TRCCNTCTLR0 = 34853 , ARM64_SYSREG_TRCCNTCTLR1 = 34861 , ARM64_SYSREG_TRCCNTCTLR2 = 34869 , ARM64_SYSREG_TRCCNTCTLR3 = 34877 , ARM64_SYSREG_TRCCNTRLDVR0 = 34821 , ARM64_SYSREG_TRCCNTRLDVR1 = 34829 , ARM64_SYSREG_TRCCNTRLDVR2 = 34837 , ARM64_SYSREG_TRCCNTRLDVR3 = 34845 , ARM64_SYSREG_TRCCNTVR0 = 34885 , ARM64_SYSREG_TRCCNTVR1 = 34893 , ARM64_SYSREG_TRCCNTVR2 = 34901 , ARM64_SYSREG_TRCCNTVR3 = 34909 , ARM64_SYSREG_TRCCONFIGR = 34848 , ARM64_SYSREG_TRCDEVAFF0 = 35798 , ARM64_SYSREG_TRCDEVAFF1 = 35806 , ARM64_SYSREG_TRCDEVARCH = 35838 , ARM64_SYSREG_TRCDEVID = 35735 , ARM64_SYSREG_TRCDEVTYPE = 35743 , ARM64_SYSREG_TRCDVCMR0 = 35078 , ARM64_SYSREG_TRCDVCMR1 = 35110 , ARM64_SYSREG_TRCDVCMR2 = 35142 , ARM64_SYSREG_TRCDVCMR3 = 35174 , ARM64_SYSREG_TRCDVCMR4 = 35079 , ARM64_SYSREG_TRCDVCMR5 = 35111 , ARM64_SYSREG_TRCDVCMR6 = 35143 , ARM64_SYSREG_TRCDVCMR7 = 35175 , ARM64_SYSREG_TRCDVCVR0 = 35076 , ARM64_SYSREG_TRCDVCVR1 = 35108 , ARM64_SYSREG_TRCDVCVR2 = 35140 , ARM64_SYSREG_TRCDVCVR3 = 35172 , ARM64_SYSREG_TRCDVCVR4 = 35077 , ARM64_SYSREG_TRCDVCVR5 = 35109 , ARM64_SYSREG_TRCDVCVR6 = 35141 , ARM64_SYSREG_TRCDVCVR7 = 35173 , ARM64_SYSREG_TRCEVENTCTL0R = 34880 , ARM64_SYSREG_TRCEVENTCTL1R = 34888 , ARM64_SYSREG_TRCEXTINSELR = 34884 , ARM64_SYSREG_TRCEXTINSELR1 = 34892 , ARM64_SYSREG_TRCEXTINSELR2 = 34900 , ARM64_SYSREG_TRCEXTINSELR3 = 34908 , ARM64_SYSREG_TRCIDR0 = 34887 , ARM64_SYSREG_TRCIDR1 = 34895 , ARM64_SYSREG_TRCIDR10 = 34838 , ARM64_SYSREG_TRCIDR11 = 34846 , ARM64_SYSREG_TRCIDR12 = 34854 , ARM64_SYSREG_TRCIDR13 = 34862 , ARM64_SYSREG_TRCIDR2 = 34903 , ARM64_SYSREG_TRCIDR3 = 34911 , ARM64_SYSREG_TRCIDR4 = 34919 , ARM64_SYSREG_TRCIDR5 = 34927 , ARM64_SYSREG_TRCIDR6 = 34935 , ARM64_SYSREG_TRCIDR7 = 34943 , ARM64_SYSREG_TRCIDR8 = 34822 , ARM64_SYSREG_TRCIDR9 = 34830 , ARM64_SYSREG_TRCIMSPEC0 = 34823 , ARM64_SYSREG_TRCIMSPEC1 = 34831 , ARM64_SYSREG_TRCIMSPEC2 = 34839 , ARM64_SYSREG_TRCIMSPEC3 = 34847 , ARM64_SYSREG_TRCIMSPEC4 = 34855 , ARM64_SYSREG_TRCIMSPEC5 = 34863 , ARM64_SYSREG_TRCIMSPEC6 = 34871 , ARM64_SYSREG_TRCIMSPEC7 = 34879 , ARM64_SYSREG_TRCITCTRL = 35716 , ARM64_SYSREG_TRCLAR = 35814 , ARM64_SYSREG_TRCLSR = 35822 , ARM64_SYSREG_TRCOSLAR = 34948 , ARM64_SYSREG_TRCOSLSR = 34956 , ARM64_SYSREG_TRCPDCR = 34980 , ARM64_SYSREG_TRCPDSR = 34988 , ARM64_SYSREG_TRCPIDR0 = 35783 , ARM64_SYSREG_TRCPIDR1 = 35791 , ARM64_SYSREG_TRCPIDR2 = 35799 , ARM64_SYSREG_TRCPIDR3 = 35807 , ARM64_SYSREG_TRCPIDR4 = 35751 , ARM64_SYSREG_TRCPIDR5 = 35759 , ARM64_SYSREG_TRCPIDR6 = 35767 , ARM64_SYSREG_TRCPIDR7 = 35775 , ARM64_SYSREG_TRCPRGCTLR = 34824 , ARM64_SYSREG_TRCPROCSELR = 34832 , ARM64_SYSREG_TRCQCTLR = 34825 , ARM64_SYSREG_TRCRSCTLR10 = 35024 , ARM64_SYSREG_TRCRSCTLR11 = 35032 , ARM64_SYSREG_TRCRSCTLR12 = 35040 , ARM64_SYSREG_TRCRSCTLR13 = 35048 , ARM64_SYSREG_TRCRSCTLR14 = 35056 , ARM64_SYSREG_TRCRSCTLR15 = 35064 , ARM64_SYSREG_TRCRSCTLR16 = 34945 , ARM64_SYSREG_TRCRSCTLR17 = 34953 , ARM64_SYSREG_TRCRSCTLR18 = 34961 , ARM64_SYSREG_TRCRSCTLR19 = 34969 , ARM64_SYSREG_TRCRSCTLR2 = 34960 , ARM64_SYSREG_TRCRSCTLR20 = 34977 , ARM64_SYSREG_TRCRSCTLR21 = 34985 , ARM64_SYSREG_TRCRSCTLR22 = 34993 , ARM64_SYSREG_TRCRSCTLR23 = 35001 , ARM64_SYSREG_TRCRSCTLR24 = 35009 , ARM64_SYSREG_TRCRSCTLR25 = 35017 , ARM64_SYSREG_TRCRSCTLR26 = 35025 , ARM64_SYSREG_TRCRSCTLR27 = 35033 , ARM64_SYSREG_TRCRSCTLR28 = 35041 , ARM64_SYSREG_TRCRSCTLR29 = 35049 , ARM64_SYSREG_TRCRSCTLR3 = 34968 , ARM64_SYSREG_TRCRSCTLR30 = 35057 , ARM64_SYSREG_TRCRSCTLR31 = 35065 , ARM64_SYSREG_TRCRSCTLR4 = 34976 , ARM64_SYSREG_TRCRSCTLR5 = 34984 , ARM64_SYSREG_TRCRSCTLR6 = 34992 , ARM64_SYSREG_TRCRSCTLR7 = 35000 , ARM64_SYSREG_TRCRSCTLR8 = 35008 , ARM64_SYSREG_TRCRSCTLR9 = 35016 , ARM64_SYSREG_TRCRSR = 34896 , ARM64_SYSREG_TRCSEQEVR0 = 34820 , ARM64_SYSREG_TRCSEQEVR1 = 34828 , ARM64_SYSREG_TRCSEQEVR2 = 34836 , ARM64_SYSREG_TRCSEQRSTEVR = 34868 , ARM64_SYSREG_TRCSEQSTR = 34876 , ARM64_SYSREG_TRCSSCCR0 = 34946 , ARM64_SYSREG_TRCSSCCR1 = 34954 , ARM64_SYSREG_TRCSSCCR2 = 34962 , ARM64_SYSREG_TRCSSCCR3 = 34970 , ARM64_SYSREG_TRCSSCCR4 = 34978 , ARM64_SYSREG_TRCSSCCR5 = 34986 , ARM64_SYSREG_TRCSSCCR6 = 34994 , ARM64_SYSREG_TRCSSCCR7 = 35002 , ARM64_SYSREG_TRCSSCSR0 = 35010 , ARM64_SYSREG_TRCSSCSR1 = 35018 , ARM64_SYSREG_TRCSSCSR2 = 35026 , ARM64_SYSREG_TRCSSCSR3 = 35034 , ARM64_SYSREG_TRCSSCSR4 = 35042 , ARM64_SYSREG_TRCSSCSR5 = 35050 , ARM64_SYSREG_TRCSSCSR6 = 35058 , ARM64_SYSREG_TRCSSCSR7 = 35066 , ARM64_SYSREG_TRCSSPCICR0 = 34947 , ARM64_SYSREG_TRCSSPCICR1 = 34955 , ARM64_SYSREG_TRCSSPCICR2 = 34963 , ARM64_SYSREG_TRCSSPCICR3 = 34971 , ARM64_SYSREG_TRCSSPCICR4 = 34979 , ARM64_SYSREG_TRCSSPCICR5 = 34987 , ARM64_SYSREG_TRCSSPCICR6 = 34995 , ARM64_SYSREG_TRCSSPCICR7 = 35003 , ARM64_SYSREG_TRCSTALLCTLR = 34904 , ARM64_SYSREG_TRCSTATR = 34840 , ARM64_SYSREG_TRCSYNCPR = 34920 , ARM64_SYSREG_TRCTRACEIDR = 34817 , ARM64_SYSREG_TRCTSCTLR = 34912 , ARM64_SYSREG_TRCVDARCCTLR = 34898 , ARM64_SYSREG_TRCVDCTLR = 34882 , ARM64_SYSREG_TRCVDSACCTLR = 34890 , ARM64_SYSREG_TRCVICTLR = 34818 , ARM64_SYSREG_TRCVIIECTLR = 34826 , ARM64_SYSREG_TRCVIPCSSCTLR = 34842 , ARM64_SYSREG_TRCVISSCTLR = 34834 , ARM64_SYSREG_TRCVMIDCCTLR0 = 35218 , ARM64_SYSREG_TRCVMIDCCTLR1 = 35226 , ARM64_SYSREG_TRCVMIDCVR0 = 35201 , ARM64_SYSREG_TRCVMIDCVR1 = 35217 , ARM64_SYSREG_TRCVMIDCVR2 = 35233 , ARM64_SYSREG_TRCVMIDCVR3 = 35249 , ARM64_SYSREG_TRCVMIDCVR4 = 35265 , ARM64_SYSREG_TRCVMIDCVR5 = 35281 , ARM64_SYSREG_TRCVMIDCVR6 = 35297 , ARM64_SYSREG_TRCVMIDCVR7 = 35313 , ARM64_SYSREG_TRFCR_EL1 = 49297 , ARM64_SYSREG_TRFCR_EL12 = 59537 , ARM64_SYSREG_TRFCR_EL2 = 57489 , ARM64_SYSREG_TTBR0_EL1 = 49408 , ARM64_SYSREG_TTBR0_EL12 = 59648 , ARM64_SYSREG_TTBR0_EL2 = 57600 , ARM64_SYSREG_TTBR0_EL3 = 61696 , ARM64_SYSREG_TTBR1_EL1 = 49409 , ARM64_SYSREG_TTBR1_EL12 = 59649 , ARM64_SYSREG_TTBR1_EL2 = 57601 , ARM64_SYSREG_UAO = 49684 , ARM64_SYSREG_VBAR_EL1 = 50688 , ARM64_SYSREG_VBAR_EL12 = 60928 , ARM64_SYSREG_VBAR_EL2 = 58880 , ARM64_SYSREG_VBAR_EL3 = 62976 , ARM64_SYSREG_VDISR_EL2 = 58889 , ARM64_SYSREG_VMPIDR_EL2 = 57349 , ARM64_SYSREG_VNCR_EL2 = 57616 , ARM64_SYSREG_VPIDR_EL2 = 57344 , ARM64_SYSREG_VSESR_EL2 = 58003 , ARM64_SYSREG_VSTCR_EL2 = 57650 , ARM64_SYSREG_VSTTBR_EL2 = 57648 , ARM64_SYSREG_VTCR_EL2 = 57610 , ARM64_SYSREG_VTTBR_EL2 = 57608 , ARM64_SYSREG_ZCR_EL1 = 49296 , ARM64_SYSREG_ZCR_EL12 = 59536 , ARM64_SYSREG_ZCR_EL2 = 57488 , ARM64_SYSREG_ZCR_EL3 = 61584 , } # [repr (u32)] # [doc = " System PState Field (MSR instruction)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_pstate { ARM64_PSTATE_INVALID = 0 , ARM64_PSTATE_SPSEL = 5 , ARM64_PSTATE_DAIFSET = 30 , ARM64_PSTATE_DAIFCLR = 31 , ARM64_PSTATE_PAN = 4 , ARM64_PSTATE_UAO = 3 , ARM64_PSTATE_DIT = 26 , } # [repr (u32)] # [doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_vas { ARM64_VAS_INVALID = 0 , ARM64_VAS_16B = 1 , ARM64_VAS_8B = 2 , ARM64_VAS_4B = 3 , ARM64_VAS_1B = 4 , ARM64_VAS_8H = 5 , ARM64_VAS_4H = 6 , ARM64_VAS_2H = 7 , ARM64_VAS_1H = 8 , ARM64_VAS_4S = 9 , ARM64_VAS_2S = 10 , ARM64_VAS_1S = 11 , ARM64_VAS_2D = 12 , ARM64_VAS_1D = 13 , ARM64_VAS_1Q = 14 , } # [repr (u32)] # [doc = " Memory barrier operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0 , ARM64_BARRIER_OSHLD = 1 , ARM64_BARRIER_OSHST = 2 , ARM64_BARRIER_OSH = 3 , ARM64_BARRIER_NSHLD = 5 , ARM64_BARRIER_NSHST = 6 , ARM64_BARRIER_NSH = 7 , ARM64_BARRIER_ISHLD = 9 , ARM64_BARRIER_ISHST = 10 , ARM64_BARRIER_ISH = 11 , ARM64_BARRIER_LD = 13 , ARM64_BARRIER_ST = 14 , ARM64_BARRIER_SY = 15 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM64_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM64_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM64_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM64_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM64_OP_FP = 4 , # [doc = "< C-Immediate"] ARM64_OP_CIMM = 64 , # [doc = "< MRS register operand."] ARM64_OP_REG_MRS = 65 , # [doc = "< MSR register operand."] ARM64_OP_REG_MSR = 66 , # [doc = "< PState operand."] ARM64_OP_PSTATE = 67 , # [doc = "< SYS operand for IC/DC/AT/TLBI instructions."] ARM64_OP_SYS = 68 , # [doc = "< SVCR operand for MSR SVCR instructions."] ARM64_OP_SVCR = 69 , # [doc = "< Prefetch operand (PRFM)."] ARM64_OP_PREFETCH = 70 , # [doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."] ARM64_OP_BARRIER = 71 , # [doc = "< SME instruction operand with with index."] ARM64_OP_SME_INDEX = 72 , } # [repr (u32)] # [doc = " SYS operands (IC/DC/AC/TLBI)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sys_op { ARM64_SYS_INVALID = 0 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1 = 1 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1IS = 2 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1ISNXS = 3 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1NXS = 4 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OS = 5 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OSNXS = 6 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2 = 7 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2IS = 8 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2ISNXS = 9 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2NXS = 10 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OS = 11 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OSNXS = 12 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3 = 13 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3IS = 14 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3ISNXS = 15 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3NXS = 16 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OS = 17 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OSNXS = 18 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1 = 19 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1IS = 20 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1ISNXS = 21 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1NXS = 22 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OS = 23 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OSNXS = 24 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1 = 25 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1IS = 26 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1ISNXS = 27 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1NXS = 28 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OS = 29 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OSNXS = 30 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1 = 31 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1IS = 32 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1ISNXS = 33 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1NXS = 34 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OS = 35 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OSNXS = 36 , # [doc = " TLBI operations"] ARM64_TLBI_PAALL = 37 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLNXS = 38 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOS = 39 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOSNXS = 40 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1 = 41 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1IS = 42 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1ISNXS = 43 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1NXS = 44 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OS = 45 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OSNXS = 46 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1 = 47 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1IS = 48 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1ISNXS = 49 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1NXS = 50 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OS = 51 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OSNXS = 52 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOS = 53 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOSNXS = 54 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOS = 55 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOSNXS = 56 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1 = 57 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1IS = 58 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1ISNXS = 59 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1NXS = 60 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OS = 61 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OSNXS = 62 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1 = 63 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1IS = 64 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1ISNXS = 65 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1NXS = 66 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OS = 67 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OSNXS = 68 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1 = 69 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1IS = 70 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1ISNXS = 71 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1NXS = 72 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OS = 73 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OSNXS = 74 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2 = 75 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2IS = 76 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2ISNXS = 77 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2NXS = 78 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OS = 79 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OSNXS = 80 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3 = 81 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3IS = 82 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3ISNXS = 83 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3NXS = 84 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OS = 85 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OSNXS = 86 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1 = 87 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1IS = 88 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1ISNXS = 89 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1NXS = 90 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OS = 91 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OSNXS = 92 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2 = 93 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2IS = 94 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2ISNXS = 95 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2NXS = 96 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OS = 97 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OSNXS = 98 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3 = 99 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3IS = 100 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3ISNXS = 101 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3NXS = 102 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OS = 103 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OSNXS = 104 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1 = 105 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1IS = 106 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1ISNXS = 107 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1NXS = 108 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OS = 109 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OSNXS = 110 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1 = 111 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1IS = 112 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1ISNXS = 113 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1NXS = 114 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OS = 115 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OSNXS = 116 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1 = 117 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1IS = 118 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1ISNXS = 119 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1NXS = 120 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OS = 121 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OSNXS = 122 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2 = 123 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2IS = 124 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2ISNXS = 125 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2NXS = 126 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OS = 127 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OSNXS = 128 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3 = 129 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3IS = 130 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3ISNXS = 131 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3NXS = 132 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OS = 133 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OSNXS = 134 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1 = 135 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1IS = 136 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1ISNXS = 137 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1NXS = 138 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OS = 139 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OSNXS = 140 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2 = 141 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2IS = 142 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2ISNXS = 143 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2NXS = 144 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OS = 145 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OSNXS = 146 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3 = 147 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3IS = 148 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3ISNXS = 149 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3NXS = 150 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OS = 151 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OSNXS = 152 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1 = 153 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1IS = 154 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1ISNXS = 155 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1NXS = 156 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OS = 157 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OSNXS = 158 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1 = 159 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1IS = 160 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1ISNXS = 161 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1NXS = 162 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OS = 163 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OSNXS = 164 , # [doc = " AT operations"] ARM64_AT_S1E1R = 165 , # [doc = " AT operations"] ARM64_AT_S1E2R = 166 , # [doc = " AT operations"] ARM64_AT_S1E3R = 167 , # [doc = " AT operations"] ARM64_AT_S1E1W = 168 , # [doc = " AT operations"] ARM64_AT_S1E2W = 169 , # [doc = " AT operations"] ARM64_AT_S1E3W = 170 , # [doc = " AT operations"] ARM64_AT_S1E0R = 171 , # [doc = " AT operations"] ARM64_AT_S1E0W = 172 , # [doc = " AT operations"] ARM64_AT_S12E1R = 173 , # [doc = " AT operations"] ARM64_AT_S12E1W = 174 , # [doc = " AT operations"] ARM64_AT_S12E0R = 175 , # [doc = " AT operations"] ARM64_AT_S12E0W = 176 , # [doc = " AT operations"] ARM64_AT_S1E1RP = 177 , # [doc = " AT operations"] ARM64_AT_S1E1WP = 178 , # [doc = " DC operations"] ARM64_DC_CGDSW = 179 , # [doc = " DC operations"] ARM64_DC_CGDVAC = 180 , # [doc = " DC operations"] ARM64_DC_CGDVADP = 181 , # [doc = " DC operations"] ARM64_DC_CGDVAP = 182 , # [doc = " DC operations"] ARM64_DC_CGSW = 183 , # [doc = " DC operations"] ARM64_DC_CGVAC = 184 , # [doc = " DC operations"] ARM64_DC_CGVADP = 185 , # [doc = " DC operations"] ARM64_DC_CGVAP = 186 , # [doc = " DC operations"] ARM64_DC_CIGDSW = 187 , # [doc = " DC operations"] ARM64_DC_CIGDVAC = 188 , # [doc = " DC operations"] ARM64_DC_CIGSW = 189 , # [doc = " DC operations"] ARM64_DC_CIGVAC = 190 , # [doc = " DC operations"] ARM64_DC_CISW = 191 , # [doc = " DC operations"] ARM64_DC_CIVAC = 192 , # [doc = " DC operations"] ARM64_DC_CSW = 193 , # [doc = " DC operations"] ARM64_DC_CVAC = 194 , # [doc = " DC operations"] ARM64_DC_CVADP = 195 , # [doc = " DC operations"] ARM64_DC_CVAP = 196 , # [doc = " DC operations"] ARM64_DC_CVAU = 197 , # [doc = " DC operations"] ARM64_DC_GVA = 198 , # [doc = " DC operations"] ARM64_DC_GZVA = 199 , # [doc = " DC operations"] ARM64_DC_IGDSW = 200 , # [doc = " DC operations"] ARM64_DC_IGDVAC = 201 , # [doc = " DC operations"] ARM64_DC_IGSW = 202 , # [doc = " DC operations"] ARM64_DC_IGVAC = 203 , # [doc = " DC operations"] ARM64_DC_ISW = 204 , # [doc = " DC operations"] ARM64_DC_IVAC = 205 , # [doc = " DC operations"] ARM64_DC_ZVA = 206 , # [doc = " IC operations"] ARM64_IC_IALLUIS = 207 , # [doc = " IC operations"] ARM64_IC_IALLU = 208 , # [doc = " IC operations"] ARM64_IC_IVAU = 209 , } # [repr (u32)] # [doc = " SVCR operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_svcr_op { ARM64_SVCR_INVALID = 0 , ARM64_SVCR_SVCRSM = 1 , ARM64_SVCR_SVCRSMZA = 3 , ARM64_SVCR_SVCRZA = 2 , } # [repr (u32)] # [doc = " Prefetch operations (PRFM)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0 , ARM64_PRFM_PLDL1KEEP = 1 , ARM64_PRFM_PLDL1STRM = 2 , ARM64_PRFM_PLDL2KEEP = 3 , ARM64_PRFM_PLDL2STRM = 4 , ARM64_PRFM_PLDL3KEEP = 5 , ARM64_PRFM_PLDL3STRM = 6 , ARM64_PRFM_PLIL1KEEP = 9 , ARM64_PRFM_PLIL1STRM = 10 , ARM64_PRFM_PLIL2KEEP = 11 , ARM64_PRFM_PLIL2STRM = 12 , ARM64_PRFM_PLIL3KEEP = 13 , ARM64_PRFM_PLIL3STRM = 14 , ARM64_PRFM_PSTL1KEEP = 17 , ARM64_PRFM_PSTL1STRM = 18 , ARM64_PRFM_PSTL2KEEP = 19 , ARM64_PRFM_PSTL2STRM = 20 , ARM64_PRFM_PSTL3KEEP = 21 , ARM64_PRFM_PSTL3STRM = 22 , } impl arm64_reg { pub const ARM64_REG_IP0 : arm64_reg = arm64_reg :: ARM64_REG_X16 ; } impl arm64_reg { pub const ARM64_REG_IP1 : arm64_reg = arm64_reg :: ARM64_REG_X17 ; } impl arm64_reg { pub const ARM64_REG_X29 : arm64_reg = arm64_reg :: ARM64_REG_FP ; } impl arm64_reg { pub const ARM64_REG_X30 : arm64_reg = arm64_reg :: ARM64_REG_LR ; } # [repr (u32)] # [doc = " ARM64 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_reg { ARM64_REG_INVALID = 0 , ARM64_REG_FFR = 1 , ARM64_REG_FP = 2 , ARM64_REG_LR = 3 , ARM64_REG_NZCV = 4 , ARM64_REG_SP = 5 , ARM64_REG_VG = 6 , ARM64_REG_WSP = 7 , ARM64_REG_WZR = 8 , ARM64_REG_XZR = 9 , ARM64_REG_ZA = 10 , ARM64_REG_B0 = 11 , ARM64_REG_B1 = 12 , ARM64_REG_B2 = 13 , ARM64_REG_B3 = 14 , ARM64_REG_B4 = 15 , ARM64_REG_B5 = 16 , ARM64_REG_B6 = 17 , ARM64_REG_B7 = 18 , ARM64_REG_B8 = 19 , ARM64_REG_B9 = 20 , ARM64_REG_B10 = 21 , ARM64_REG_B11 = 22 , ARM64_REG_B12 = 23 , ARM64_REG_B13 = 24 , ARM64_REG_B14 = 25 , ARM64_REG_B15 = 26 , ARM64_REG_B16 = 27 , ARM64_REG_B17 = 28 , ARM64_REG_B18 = 29 , ARM64_REG_B19 = 30 , ARM64_REG_B20 = 31 , ARM64_REG_B21 = 32 , ARM64_REG_B22 = 33 , ARM64_REG_B23 = 34 , ARM64_REG_B24 = 35 , ARM64_REG_B25 = 36 , ARM64_REG_B26 = 37 , ARM64_REG_B27 = 38 , ARM64_REG_B28 = 39 , ARM64_REG_B29 = 40 , ARM64_REG_B30 = 41 , ARM64_REG_B31 = 42 , ARM64_REG_D0 = 43 , ARM64_REG_D1 = 44 , ARM64_REG_D2 = 45 , ARM64_REG_D3 = 46 , ARM64_REG_D4 = 47 , ARM64_REG_D5 = 48 , ARM64_REG_D6 = 49 , ARM64_REG_D7 = 50 , ARM64_REG_D8 = 51 , ARM64_REG_D9 = 52 , ARM64_REG_D10 = 53 , ARM64_REG_D11 = 54 , ARM64_REG_D12 = 55 , ARM64_REG_D13 = 56 , ARM64_REG_D14 = 57 , ARM64_REG_D15 = 58 , ARM64_REG_D16 = 59 , ARM64_REG_D17 = 60 , ARM64_REG_D18 = 61 , ARM64_REG_D19 = 62 , ARM64_REG_D20 = 63 , ARM64_REG_D21 = 64 , ARM64_REG_D22 = 65 , ARM64_REG_D23 = 66 , ARM64_REG_D24 = 67 , ARM64_REG_D25 = 68 , ARM64_REG_D26 = 69 , ARM64_REG_D27 = 70 , ARM64_REG_D28 = 71 , ARM64_REG_D29 = 72 , ARM64_REG_D30 = 73 , ARM64_REG_D31 = 74 , ARM64_REG_H0 = 75 , ARM64_REG_H1 = 76 , ARM64_REG_H2 = 77 , ARM64_REG_H3 = 78 , ARM64_REG_H4 = 79 , ARM64_REG_H5 = 80 , ARM64_REG_H6 = 81 , ARM64_REG_H7 = 82 , ARM64_REG_H8 = 83 , ARM64_REG_H9 = 84 , ARM64_REG_H10 = 85 , ARM64_REG_H11 = 86 , ARM64_REG_H12 = 87 , ARM64_REG_H13 = 88 , ARM64_REG_H14 = 89 , ARM64_REG_H15 = 90 , ARM64_REG_H16 = 91 , ARM64_REG_H17 = 92 , ARM64_REG_H18 = 93 , ARM64_REG_H19 = 94 , ARM64_REG_H20 = 95 , ARM64_REG_H21 = 96 , ARM64_REG_H22 = 97 , ARM64_REG_H23 = 98 , ARM64_REG_H24 = 99 , ARM64_REG_H25 = 100 , ARM64_REG_H26 = 101 , ARM64_REG_H27 = 102 , ARM64_REG_H28 = 103 , ARM64_REG_H29 = 104 , ARM64_REG_H30 = 105 , ARM64_REG_H31 = 106 , ARM64_REG_P0 = 107 , ARM64_REG_P1 = 108 , ARM64_REG_P2 = 109 , ARM64_REG_P3 = 110 , ARM64_REG_P4 = 111 , ARM64_REG_P5 = 112 , ARM64_REG_P6 = 113 , ARM64_REG_P7 = 114 , ARM64_REG_P8 = 115 , ARM64_REG_P9 = 116 , ARM64_REG_P10 = 117 , ARM64_REG_P11 = 118 , ARM64_REG_P12 = 119 , ARM64_REG_P13 = 120 , ARM64_REG_P14 = 121 , ARM64_REG_P15 = 122 , ARM64_REG_Q0 = 123 , ARM64_REG_Q1 = 124 , ARM64_REG_Q2 = 125 , ARM64_REG_Q3 = 126 , ARM64_REG_Q4 = 127 , ARM64_REG_Q5 = 128 , ARM64_REG_Q6 = 129 , ARM64_REG_Q7 = 130 , ARM64_REG_Q8 = 131 , ARM64_REG_Q9 = 132 , ARM64_REG_Q10 = 133 , ARM64_REG_Q11 = 134 , ARM64_REG_Q12 = 135 , ARM64_REG_Q13 = 136 , ARM64_REG_Q14 = 137 , ARM64_REG_Q15 = 138 , ARM64_REG_Q16 = 139 , ARM64_REG_Q17 = 140 , ARM64_REG_Q18 = 141 , ARM64_REG_Q19 = 142 , ARM64_REG_Q20 = 143 , ARM64_REG_Q21 = 144 , ARM64_REG_Q22 = 145 , ARM64_REG_Q23 = 146 , ARM64_REG_Q24 = 147 , ARM64_REG_Q25 = 148 , ARM64_REG_Q26 = 149 , ARM64_REG_Q27 = 150 , ARM64_REG_Q28 = 151 , ARM64_REG_Q29 = 152 , ARM64_REG_Q30 = 153 , ARM64_REG_Q31 = 154 , ARM64_REG_S0 = 155 , ARM64_REG_S1 = 156 , ARM64_REG_S2 = 157 , ARM64_REG_S3 = 158 , ARM64_REG_S4 = 159 , ARM64_REG_S5 = 160 , ARM64_REG_S6 = 161 , ARM64_REG_S7 = 162 , ARM64_REG_S8 = 163 , ARM64_REG_S9 = 164 , ARM64_REG_S10 = 165 , ARM64_REG_S11 = 166 , ARM64_REG_S12 = 167 , ARM64_REG_S13 = 168 , ARM64_REG_S14 = 169 , ARM64_REG_S15 = 170 , ARM64_REG_S16 = 171 , ARM64_REG_S17 = 172 , ARM64_REG_S18 = 173 , ARM64_REG_S19 = 174 , ARM64_REG_S20 = 175 , ARM64_REG_S21 = 176 , ARM64_REG_S22 = 177 , ARM64_REG_S23 = 178 , ARM64_REG_S24 = 179 , ARM64_REG_S25 = 180 , ARM64_REG_S26 = 181 , ARM64_REG_S27 = 182 , ARM64_REG_S28 = 183 , ARM64_REG_S29 = 184 , ARM64_REG_S30 = 185 , ARM64_REG_S31 = 186 , ARM64_REG_W0 = 187 , ARM64_REG_W1 = 188 , ARM64_REG_W2 = 189 , ARM64_REG_W3 = 190 , ARM64_REG_W4 = 191 , ARM64_REG_W5 = 192 , ARM64_REG_W6 = 193 , ARM64_REG_W7 = 194 , ARM64_REG_W8 = 195 , ARM64_REG_W9 = 196 , ARM64_REG_W10 = 197 , ARM64_REG_W11 = 198 , ARM64_REG_W12 = 199 , ARM64_REG_W13 = 200 , ARM64_REG_W14 = 201 , ARM64_REG_W15 = 202 , ARM64_REG_W16 = 203 , ARM64_REG_W17 = 204 , ARM64_REG_W18 = 205 , ARM64_REG_W19 = 206 , ARM64_REG_W20 = 207 , ARM64_REG_W21 = 208 , ARM64_REG_W22 = 209 , ARM64_REG_W23 = 210 , ARM64_REG_W24 = 211 , ARM64_REG_W25 = 212 , ARM64_REG_W26 = 213 , ARM64_REG_W27 = 214 , ARM64_REG_W28 = 215 , ARM64_REG_W29 = 216 , ARM64_REG_W30 = 217 , ARM64_REG_X0 = 218 , ARM64_REG_X1 = 219 , ARM64_REG_X2 = 220 , ARM64_REG_X3 = 221 , ARM64_REG_X4 = 222 , ARM64_REG_X5 = 223 , ARM64_REG_X6 = 224 , ARM64_REG_X7 = 225 , ARM64_REG_X8 = 226 , ARM64_REG_X9 = 227 , ARM64_REG_X10 = 228 , ARM64_REG_X11 = 229 , ARM64_REG_X12 = 230 , ARM64_REG_X13 = 231 , ARM64_REG_X14 = 232 , ARM64_REG_X15 = 233 , ARM64_REG_X16 = 234 , ARM64_REG_X17 = 235 , ARM64_REG_X18 = 236 , ARM64_REG_X19 = 237 , ARM64_REG_X20 = 238 , ARM64_REG_X21 = 239 , ARM64_REG_X22 = 240 , ARM64_REG_X23 = 241 , ARM64_REG_X24 = 242 , ARM64_REG_X25 = 243 , ARM64_REG_X26 = 244 , ARM64_REG_X27 = 245 , ARM64_REG_X28 = 246 , ARM64_REG_Z0 = 247 , ARM64_REG_Z1 = 248 , ARM64_REG_Z2 = 249 , ARM64_REG_Z3 = 250 , ARM64_REG_Z4 = 251 , ARM64_REG_Z5 = 252 , ARM64_REG_Z6 = 253 , ARM64_REG_Z7 = 254 , ARM64_REG_Z8 = 255 , ARM64_REG_Z9 = 256 , ARM64_REG_Z10 = 257 , ARM64_REG_Z11 = 258 , ARM64_REG_Z12 = 259 , ARM64_REG_Z13 = 260 , ARM64_REG_Z14 = 261 , ARM64_REG_Z15 = 262 , ARM64_REG_Z16 = 263 , ARM64_REG_Z17 = 264 , ARM64_REG_Z18 = 265 , ARM64_REG_Z19 = 266 , ARM64_REG_Z20 = 267 , ARM64_REG_Z21 = 268 , ARM64_REG_Z22 = 269 , ARM64_REG_Z23 = 270 , ARM64_REG_Z24 = 271 , ARM64_REG_Z25 = 272 , ARM64_REG_Z26 = 273 , ARM64_REG_Z27 = 274 , ARM64_REG_Z28 = 275 , ARM64_REG_Z29 = 276 , ARM64_REG_Z30 = 277 , ARM64_REG_Z31 = 278 , ARM64_REG_ZAB0 = 279 , ARM64_REG_ZAD0 = 280 , ARM64_REG_ZAD1 = 281 , ARM64_REG_ZAD2 = 282 , ARM64_REG_ZAD3 = 283 , ARM64_REG_ZAD4 = 284 , ARM64_REG_ZAD5 = 285 , ARM64_REG_ZAD6 = 286 , ARM64_REG_ZAD7 = 287 , ARM64_REG_ZAH0 = 288 , ARM64_REG_ZAH1 = 289 , ARM64_REG_ZAQ0 = 290 , ARM64_REG_ZAQ1 = 291 , ARM64_REG_ZAQ2 = 292 , ARM64_REG_ZAQ3 = 293 , ARM64_REG_ZAQ4 = 294 , ARM64_REG_ZAQ5 = 295 , ARM64_REG_ZAQ6 = 296 , ARM64_REG_ZAQ7 = 297 , ARM64_REG_ZAQ8 = 298 , ARM64_REG_ZAQ9 = 299 , ARM64_REG_ZAQ10 = 300 , ARM64_REG_ZAQ11 = 301 , ARM64_REG_ZAQ12 = 302 , ARM64_REG_ZAQ13 = 303 , ARM64_REG_ZAQ14 = 304 , ARM64_REG_ZAQ15 = 305 , ARM64_REG_ZAS0 = 306 , ARM64_REG_ZAS1 = 307 , ARM64_REG_ZAS2 = 308 , ARM64_REG_ZAS3 = 309 , ARM64_REG_V0 = 310 , ARM64_REG_V1 = 311 , ARM64_REG_V2 = 312 , ARM64_REG_V3 = 313 , ARM64_REG_V4 = 314 , ARM64_REG_V5 = 315 , ARM64_REG_V6 = 316 , ARM64_REG_V7 = 317 , ARM64_REG_V8 = 318 , ARM64_REG_V9 = 319 , ARM64_REG_V10 = 320 , ARM64_REG_V11 = 321 , ARM64_REG_V12 = 322 , ARM64_REG_V13 = 323 , ARM64_REG_V14 = 324 , ARM64_REG_V15 = 325 , ARM64_REG_V16 = 326 , ARM64_REG_V17 = 327 , ARM64_REG_V18 = 328 , ARM64_REG_V19 = 329 , ARM64_REG_V20 = 330 , ARM64_REG_V21 = 331 , ARM64_REG_V22 = 332 , ARM64_REG_V23 = 333 , ARM64_REG_V24 = 334 , ARM64_REG_V25 = 335 , ARM64_REG_V26 = 336 , ARM64_REG_V27 = 337 , ARM64_REG_V28 = 338 , ARM64_REG_V29 = 339 , ARM64_REG_V30 = 340 , ARM64_REG_V31 = 341 , ARM64_REG_ENDING = 342 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_mem { # [doc = "< base register"] pub base : arm64_reg , # [doc = "< index register"] pub index : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_mem"] [:: std :: mem :: size_of :: < arm64_op_mem > () - 12usize] ; ["Alignment of arm64_op_mem"] [:: std :: mem :: align_of :: < arm64_op_mem > () - 4usize] ; ["Offset of field: arm64_op_mem::base"] [:: std :: mem :: offset_of ! (arm64_op_mem , base) - 0usize] ; ["Offset of field: arm64_op_mem::index"] [:: std :: mem :: offset_of ! (arm64_op_mem , index) - 4usize] ; ["Offset of field: arm64_op_mem::disp"] [:: std :: mem :: offset_of ! (arm64_op_mem , disp) - 8usize] ; } ; # [doc = " SME Instruction's operand has index\n This is associated with ARM64_OP_SME_INDEX operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_sme_index { # [doc = "< register being indexed"] pub reg : arm64_reg , # [doc = "< base register"] pub base : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_sme_index"] [:: std :: mem :: size_of :: < arm64_op_sme_index > () - 12usize] ; ["Alignment of arm64_op_sme_index"] [:: std :: mem :: align_of :: < arm64_op_sme_index > () - 4usize] ; ["Offset of field: arm64_op_sme_index::reg"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , reg) - 0usize] ; ["Offset of field: arm64_op_sme_index::base"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , base) - 4usize] ; ["Offset of field: arm64_op_sme_index::disp"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64_op { # [doc = "< Vector Index for some vector operands (or -1 if\n< irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , # [doc = "< Vector Arrangement Specifier"] pub vas : arm64_vas , pub shift : cs_arm64_op__bindgen_ty_1 , # [doc = "< extender type of this operand"] pub ext : arm64_extender , # [doc = "< operand type"] pub type_ : arm64_op_type , # [doc = "< MSR/MRS SVCR instruction variant."] pub svcr : arm64_svcr_op , pub __bindgen_anon_1 : cs_arm64_op__bindgen_ty_2 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm64_op__bindgen_ty_1 { # [doc = "< shifter type of this operand"] pub type_ : arm64_shifter , # [doc = "< shifter value of this operand"] pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm64_op__bindgen_ty_2 { # [doc = "< register value for REG operand"] pub reg : arm64_reg , # [doc = "< immediate value, or index for C-IMM or IMM operand"] pub imm : i64 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm64_op_mem , # [doc = "< PState field of MSR instruction."] pub pstate : arm64_pstate , # [doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op,\n< arm64_dc_op, arm64_at_op, arm64_tlbi_op)"] pub sys : arm64_sys_op , # [doc = "< PRFM operation."] pub prefetch : arm64_prefetch_op , # [doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."] pub barrier : arm64_barrier_op , # [doc = "< base/disp value for matrix tile slice\n< instructions."] pub sme_index : arm64_op_sme_index , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_2 > () - 16usize] ; ["Alignment of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::pstate"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , pstate) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sys"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sys) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::prefetch"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , prefetch) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::barrier"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , barrier) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sme_index"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sme_index) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op"] [:: std :: mem :: size_of :: < cs_arm64_op > () - 56usize] ; ["Alignment of cs_arm64_op"] [:: std :: mem :: align_of :: < cs_arm64_op > () - 8usize] ; ["Offset of field: cs_arm64_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm64_op , vector_index) - 0usize] ; ["Offset of field: cs_arm64_op::vas"] [:: std :: mem :: offset_of ! (cs_arm64_op , vas) - 4usize] ; ["Offset of field: cs_arm64_op::shift"] [:: std :: mem :: offset_of ! (cs_arm64_op , shift) - 8usize] ; ["Offset of field: cs_arm64_op::ext"] [:: std :: mem :: offset_of ! (cs_arm64_op , ext) - 16usize] ; ["Offset of field: cs_arm64_op::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op , type_) - 20usize] ; ["Offset of field: cs_arm64_op::svcr"] [:: std :: mem :: offset_of ! (cs_arm64_op , svcr) - 24usize] ; ["Offset of field: cs_arm64_op::access"] [:: std :: mem :: offset_of ! (cs_arm64_op , access) - 48usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, svcr: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . svcr , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64 { # [doc = "< conditional code for this insn"] pub cc : arm64_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn request writeback? 'True' means 'yes'"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm64_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64"] [:: std :: mem :: size_of :: < cs_arm64 > () - 456usize] ; ["Alignment of cs_arm64"] [:: std :: mem :: align_of :: < cs_arm64 > () - 8usize] ; ["Offset of field: cs_arm64::cc"] [:: std :: mem :: offset_of ! (cs_arm64 , cc) - 0usize] ; ["Offset of field: cs_arm64::update_flags"] [:: std :: mem :: offset_of ! (cs_arm64 , update_flags) - 4usize] ; ["Offset of field: cs_arm64::writeback"] [:: std :: mem :: offset_of ! (cs_arm64 , writeback) - 5usize] ; ["Offset of field: cs_arm64::post_index"] [:: std :: mem :: offset_of ! (cs_arm64 , post_index) - 6usize] ; ["Offset of field: cs_arm64::op_count"] [:: std :: mem :: offset_of ! (cs_arm64 , op_count) - 7usize] ; ["Offset of field: cs_arm64::operands"] [:: std :: mem :: offset_of ! (cs_arm64 , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . post_index , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM64 instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn { ARM64_INS_INVALID = 0 , ARM64_INS_ABS = 1 , ARM64_INS_ADC = 2 , ARM64_INS_ADCLB = 3 , ARM64_INS_ADCLT = 4 , ARM64_INS_ADCS = 5 , ARM64_INS_ADD = 6 , ARM64_INS_ADDG = 7 , ARM64_INS_ADDHA = 8 , ARM64_INS_ADDHN = 9 , ARM64_INS_ADDHN2 = 10 , ARM64_INS_ADDHNB = 11 , ARM64_INS_ADDHNT = 12 , ARM64_INS_ADDP = 13 , ARM64_INS_ADDPL = 14 , ARM64_INS_ADDS = 15 , ARM64_INS_ADDV = 16 , ARM64_INS_ADDVA = 17 , ARM64_INS_ADDVL = 18 , ARM64_INS_ADR = 19 , ARM64_INS_ADRP = 20 , ARM64_INS_AESD = 21 , ARM64_INS_AESE = 22 , ARM64_INS_AESIMC = 23 , ARM64_INS_AESMC = 24 , ARM64_INS_AND = 25 , ARM64_INS_ANDS = 26 , ARM64_INS_ANDV = 27 , ARM64_INS_ASR = 28 , ARM64_INS_ASRD = 29 , ARM64_INS_ASRR = 30 , ARM64_INS_ASRV = 31 , ARM64_INS_AUTDA = 32 , ARM64_INS_AUTDB = 33 , ARM64_INS_AUTDZA = 34 , ARM64_INS_AUTDZB = 35 , ARM64_INS_AUTIA = 36 , ARM64_INS_AUTIA1716 = 37 , ARM64_INS_AUTIASP = 38 , ARM64_INS_AUTIAZ = 39 , ARM64_INS_AUTIB = 40 , ARM64_INS_AUTIB1716 = 41 , ARM64_INS_AUTIBSP = 42 , ARM64_INS_AUTIBZ = 43 , ARM64_INS_AUTIZA = 44 , ARM64_INS_AUTIZB = 45 , ARM64_INS_AXFLAG = 46 , ARM64_INS_B = 47 , ARM64_INS_BC = 48 , ARM64_INS_BCAX = 49 , ARM64_INS_BDEP = 50 , ARM64_INS_BEXT = 51 , ARM64_INS_BFCVT = 52 , ARM64_INS_BFCVTN = 53 , ARM64_INS_BFCVTN2 = 54 , ARM64_INS_BFCVTNT = 55 , ARM64_INS_BFDOT = 56 , ARM64_INS_BFM = 57 , ARM64_INS_BFMLALB = 58 , ARM64_INS_BFMLALT = 59 , ARM64_INS_BFMMLA = 60 , ARM64_INS_BFMOPA = 61 , ARM64_INS_BFMOPS = 62 , ARM64_INS_BGRP = 63 , ARM64_INS_BIC = 64 , ARM64_INS_BICS = 65 , ARM64_INS_BIF = 66 , ARM64_INS_BIT = 67 , ARM64_INS_BL = 68 , ARM64_INS_BLR = 69 , ARM64_INS_BLRAA = 70 , ARM64_INS_BLRAAZ = 71 , ARM64_INS_BLRAB = 72 , ARM64_INS_BLRABZ = 73 , ARM64_INS_BR = 74 , ARM64_INS_BRAA = 75 , ARM64_INS_BRAAZ = 76 , ARM64_INS_BRAB = 77 , ARM64_INS_BRABZ = 78 , ARM64_INS_BRB = 79 , ARM64_INS_BRK = 80 , ARM64_INS_BRKA = 81 , ARM64_INS_BRKAS = 82 , ARM64_INS_BRKB = 83 , ARM64_INS_BRKBS = 84 , ARM64_INS_BRKN = 85 , ARM64_INS_BRKNS = 86 , ARM64_INS_BRKPA = 87 , ARM64_INS_BRKPAS = 88 , ARM64_INS_BRKPB = 89 , ARM64_INS_BRKPBS = 90 , ARM64_INS_BSL = 91 , ARM64_INS_BSL1N = 92 , ARM64_INS_BSL2N = 93 , ARM64_INS_BTI = 94 , ARM64_INS_CADD = 95 , ARM64_INS_CAS = 96 , ARM64_INS_CASA = 97 , ARM64_INS_CASAB = 98 , ARM64_INS_CASAH = 99 , ARM64_INS_CASAL = 100 , ARM64_INS_CASALB = 101 , ARM64_INS_CASALH = 102 , ARM64_INS_CASB = 103 , ARM64_INS_CASH = 104 , ARM64_INS_CASL = 105 , ARM64_INS_CASLB = 106 , ARM64_INS_CASLH = 107 , ARM64_INS_CASP = 108 , ARM64_INS_CASPA = 109 , ARM64_INS_CASPAL = 110 , ARM64_INS_CASPL = 111 , ARM64_INS_CBNZ = 112 , ARM64_INS_CBZ = 113 , ARM64_INS_CCMN = 114 , ARM64_INS_CCMP = 115 , ARM64_INS_CDOT = 116 , ARM64_INS_CFINV = 117 , ARM64_INS_CINC = 118 , ARM64_INS_CINV = 119 , ARM64_INS_CLASTA = 120 , ARM64_INS_CLASTB = 121 , ARM64_INS_CLREX = 122 , ARM64_INS_CLS = 123 , ARM64_INS_CLZ = 124 , ARM64_INS_CMEQ = 125 , ARM64_INS_CMGE = 126 , ARM64_INS_CMGT = 127 , ARM64_INS_CMHI = 128 , ARM64_INS_CMHS = 129 , ARM64_INS_CMLA = 130 , ARM64_INS_CMLE = 131 , ARM64_INS_CMLO = 132 , ARM64_INS_CMLS = 133 , ARM64_INS_CMLT = 134 , ARM64_INS_CMN = 135 , ARM64_INS_CMP = 136 , ARM64_INS_CMPEQ = 137 , ARM64_INS_CMPGE = 138 , ARM64_INS_CMPGT = 139 , ARM64_INS_CMPHI = 140 , ARM64_INS_CMPHS = 141 , ARM64_INS_CMPLE = 142 , ARM64_INS_CMPLO = 143 , ARM64_INS_CMPLS = 144 , ARM64_INS_CMPLT = 145 , ARM64_INS_CMPNE = 146 , ARM64_INS_CMPP = 147 , ARM64_INS_CMTST = 148 , ARM64_INS_CNEG = 149 , ARM64_INS_CNOT = 150 , ARM64_INS_CNT = 151 , ARM64_INS_CNTB = 152 , ARM64_INS_CNTD = 153 , ARM64_INS_CNTH = 154 , ARM64_INS_CNTP = 155 , ARM64_INS_CNTW = 156 , ARM64_INS_COMPACT = 157 , ARM64_INS_CPY = 158 , ARM64_INS_CPYE = 159 , ARM64_INS_CPYEN = 160 , ARM64_INS_CPYERN = 161 , ARM64_INS_CPYERT = 162 , ARM64_INS_CPYERTN = 163 , ARM64_INS_CPYERTRN = 164 , ARM64_INS_CPYERTWN = 165 , ARM64_INS_CPYET = 166 , ARM64_INS_CPYETN = 167 , ARM64_INS_CPYETRN = 168 , ARM64_INS_CPYETWN = 169 , ARM64_INS_CPYEWN = 170 , ARM64_INS_CPYEWT = 171 , ARM64_INS_CPYEWTN = 172 , ARM64_INS_CPYEWTRN = 173 , ARM64_INS_CPYEWTWN = 174 , ARM64_INS_CPYFE = 175 , ARM64_INS_CPYFEN = 176 , ARM64_INS_CPYFERN = 177 , ARM64_INS_CPYFERT = 178 , ARM64_INS_CPYFERTN = 179 , ARM64_INS_CPYFERTRN = 180 , ARM64_INS_CPYFERTWN = 181 , ARM64_INS_CPYFET = 182 , ARM64_INS_CPYFETN = 183 , ARM64_INS_CPYFETRN = 184 , ARM64_INS_CPYFETWN = 185 , ARM64_INS_CPYFEWN = 186 , ARM64_INS_CPYFEWT = 187 , ARM64_INS_CPYFEWTN = 188 , ARM64_INS_CPYFEWTRN = 189 , ARM64_INS_CPYFEWTWN = 190 , ARM64_INS_CPYFM = 191 , ARM64_INS_CPYFMN = 192 , ARM64_INS_CPYFMRN = 193 , ARM64_INS_CPYFMRT = 194 , ARM64_INS_CPYFMRTN = 195 , ARM64_INS_CPYFMRTRN = 196 , ARM64_INS_CPYFMRTWN = 197 , ARM64_INS_CPYFMT = 198 , ARM64_INS_CPYFMTN = 199 , ARM64_INS_CPYFMTRN = 200 , ARM64_INS_CPYFMTWN = 201 , ARM64_INS_CPYFMWN = 202 , ARM64_INS_CPYFMWT = 203 , ARM64_INS_CPYFMWTN = 204 , ARM64_INS_CPYFMWTRN = 205 , ARM64_INS_CPYFMWTWN = 206 , ARM64_INS_CPYFP = 207 , ARM64_INS_CPYFPN = 208 , ARM64_INS_CPYFPRN = 209 , ARM64_INS_CPYFPRT = 210 , ARM64_INS_CPYFPRTN = 211 , ARM64_INS_CPYFPRTRN = 212 , ARM64_INS_CPYFPRTWN = 213 , ARM64_INS_CPYFPT = 214 , ARM64_INS_CPYFPTN = 215 , ARM64_INS_CPYFPTRN = 216 , ARM64_INS_CPYFPTWN = 217 , ARM64_INS_CPYFPWN = 218 , ARM64_INS_CPYFPWT = 219 , ARM64_INS_CPYFPWTN = 220 , ARM64_INS_CPYFPWTRN = 221 , ARM64_INS_CPYFPWTWN = 222 , ARM64_INS_CPYM = 223 , ARM64_INS_CPYMN = 224 , ARM64_INS_CPYMRN = 225 , ARM64_INS_CPYMRT = 226 , ARM64_INS_CPYMRTN = 227 , ARM64_INS_CPYMRTRN = 228 , ARM64_INS_CPYMRTWN = 229 , ARM64_INS_CPYMT = 230 , ARM64_INS_CPYMTN = 231 , ARM64_INS_CPYMTRN = 232 , ARM64_INS_CPYMTWN = 233 , ARM64_INS_CPYMWN = 234 , ARM64_INS_CPYMWT = 235 , ARM64_INS_CPYMWTN = 236 , ARM64_INS_CPYMWTRN = 237 , ARM64_INS_CPYMWTWN = 238 , ARM64_INS_CPYP = 239 , ARM64_INS_CPYPN = 240 , ARM64_INS_CPYPRN = 241 , ARM64_INS_CPYPRT = 242 , ARM64_INS_CPYPRTN = 243 , ARM64_INS_CPYPRTRN = 244 , ARM64_INS_CPYPRTWN = 245 , ARM64_INS_CPYPT = 246 , ARM64_INS_CPYPTN = 247 , ARM64_INS_CPYPTRN = 248 , ARM64_INS_CPYPTWN = 249 , ARM64_INS_CPYPWN = 250 , ARM64_INS_CPYPWT = 251 , ARM64_INS_CPYPWTN = 252 , ARM64_INS_CPYPWTRN = 253 , ARM64_INS_CPYPWTWN = 254 , ARM64_INS_CRC32B = 255 , ARM64_INS_CRC32CB = 256 , ARM64_INS_CRC32CH = 257 , ARM64_INS_CRC32CW = 258 , ARM64_INS_CRC32CX = 259 , ARM64_INS_CRC32H = 260 , ARM64_INS_CRC32W = 261 , ARM64_INS_CRC32X = 262 , ARM64_INS_CSDB = 263 , ARM64_INS_CSEL = 264 , ARM64_INS_CSET = 265 , ARM64_INS_CSETM = 266 , ARM64_INS_CSINC = 267 , ARM64_INS_CSINV = 268 , ARM64_INS_CSNEG = 269 , ARM64_INS_CTERMEQ = 270 , ARM64_INS_CTERMNE = 271 , ARM64_INS_DCPS1 = 272 , ARM64_INS_DCPS2 = 273 , ARM64_INS_DCPS3 = 274 , ARM64_INS_DECB = 275 , ARM64_INS_DECD = 276 , ARM64_INS_DECH = 277 , ARM64_INS_DECP = 278 , ARM64_INS_DECW = 279 , ARM64_INS_DFB = 280 , ARM64_INS_DGH = 281 , ARM64_INS_DMB = 282 , ARM64_INS_DRPS = 283 , ARM64_INS_DSB = 284 , ARM64_INS_DUP = 285 , ARM64_INS_DUPM = 286 , ARM64_INS_EON = 287 , ARM64_INS_EOR = 288 , ARM64_INS_EOR3 = 289 , ARM64_INS_EORBT = 290 , ARM64_INS_EORS = 291 , ARM64_INS_EORTB = 292 , ARM64_INS_EORV = 293 , ARM64_INS_ERET = 294 , ARM64_INS_ERETAA = 295 , ARM64_INS_ERETAB = 296 , ARM64_INS_ESB = 297 , ARM64_INS_EXT = 298 , ARM64_INS_EXTR = 299 , ARM64_INS_FABD = 300 , ARM64_INS_FABS = 301 , ARM64_INS_FACGE = 302 , ARM64_INS_FACGT = 303 , ARM64_INS_FACLE = 304 , ARM64_INS_FACLT = 305 , ARM64_INS_FADD = 306 , ARM64_INS_FADDA = 307 , ARM64_INS_FADDP = 308 , ARM64_INS_FADDV = 309 , ARM64_INS_FCADD = 310 , ARM64_INS_FCCMP = 311 , ARM64_INS_FCCMPE = 312 , ARM64_INS_FCMEQ = 313 , ARM64_INS_FCMGE = 314 , ARM64_INS_FCMGT = 315 , ARM64_INS_FCMLA = 316 , ARM64_INS_FCMLE = 317 , ARM64_INS_FCMLT = 318 , ARM64_INS_FCMNE = 319 , ARM64_INS_FCMP = 320 , ARM64_INS_FCMPE = 321 , ARM64_INS_FCMUO = 322 , ARM64_INS_FCPY = 323 , ARM64_INS_FCSEL = 324 , ARM64_INS_FCVT = 325 , ARM64_INS_FCVTAS = 326 , ARM64_INS_FCVTAU = 327 , ARM64_INS_FCVTL = 328 , ARM64_INS_FCVTL2 = 329 , ARM64_INS_FCVTLT = 330 , ARM64_INS_FCVTMS = 331 , ARM64_INS_FCVTMU = 332 , ARM64_INS_FCVTN = 333 , ARM64_INS_FCVTN2 = 334 , ARM64_INS_FCVTNS = 335 , ARM64_INS_FCVTNT = 336 , ARM64_INS_FCVTNU = 337 , ARM64_INS_FCVTPS = 338 , ARM64_INS_FCVTPU = 339 , ARM64_INS_FCVTX = 340 , ARM64_INS_FCVTXN = 341 , ARM64_INS_FCVTXN2 = 342 , ARM64_INS_FCVTXNT = 343 , ARM64_INS_FCVTZS = 344 , ARM64_INS_FCVTZU = 345 , ARM64_INS_FDIV = 346 , ARM64_INS_FDIVR = 347 , ARM64_INS_FDUP = 348 , ARM64_INS_FEXPA = 349 , ARM64_INS_FJCVTZS = 350 , ARM64_INS_FLOGB = 351 , ARM64_INS_FMAD = 352 , ARM64_INS_FMADD = 353 , ARM64_INS_FMAX = 354 , ARM64_INS_FMAXNM = 355 , ARM64_INS_FMAXNMP = 356 , ARM64_INS_FMAXNMV = 357 , ARM64_INS_FMAXP = 358 , ARM64_INS_FMAXV = 359 , ARM64_INS_FMIN = 360 , ARM64_INS_FMINNM = 361 , ARM64_INS_FMINNMP = 362 , ARM64_INS_FMINNMV = 363 , ARM64_INS_FMINP = 364 , ARM64_INS_FMINV = 365 , ARM64_INS_FMLA = 366 , ARM64_INS_FMLAL = 367 , ARM64_INS_FMLAL2 = 368 , ARM64_INS_FMLALB = 369 , ARM64_INS_FMLALT = 370 , ARM64_INS_FMLS = 371 , ARM64_INS_FMLSL = 372 , ARM64_INS_FMLSL2 = 373 , ARM64_INS_FMLSLB = 374 , ARM64_INS_FMLSLT = 375 , ARM64_INS_FMMLA = 376 , ARM64_INS_FMOPA = 377 , ARM64_INS_FMOPS = 378 , ARM64_INS_FMOV = 379 , ARM64_INS_FMSB = 380 , ARM64_INS_FMSUB = 381 , ARM64_INS_FMUL = 382 , ARM64_INS_FMULX = 383 , ARM64_INS_FNEG = 384 , ARM64_INS_FNMAD = 385 , ARM64_INS_FNMADD = 386 , ARM64_INS_FNMLA = 387 , ARM64_INS_FNMLS = 388 , ARM64_INS_FNMSB = 389 , ARM64_INS_FNMSUB = 390 , ARM64_INS_FNMUL = 391 , ARM64_INS_FRECPE = 392 , ARM64_INS_FRECPS = 393 , ARM64_INS_FRECPX = 394 , ARM64_INS_FRINT32X = 395 , ARM64_INS_FRINT32Z = 396 , ARM64_INS_FRINT64X = 397 , ARM64_INS_FRINT64Z = 398 , ARM64_INS_FRINTA = 399 , ARM64_INS_FRINTI = 400 , ARM64_INS_FRINTM = 401 , ARM64_INS_FRINTN = 402 , ARM64_INS_FRINTP = 403 , ARM64_INS_FRINTX = 404 , ARM64_INS_FRINTZ = 405 , ARM64_INS_FRSQRTE = 406 , ARM64_INS_FRSQRTS = 407 , ARM64_INS_FSCALE = 408 , ARM64_INS_FSQRT = 409 , ARM64_INS_FSUB = 410 , ARM64_INS_FSUBR = 411 , ARM64_INS_FTMAD = 412 , ARM64_INS_FTSMUL = 413 , ARM64_INS_FTSSEL = 414 , ARM64_INS_GMI = 415 , ARM64_INS_HINT = 416 , ARM64_INS_HISTCNT = 417 , ARM64_INS_HISTSEG = 418 , ARM64_INS_HLT = 419 , ARM64_INS_HVC = 420 , ARM64_INS_INCB = 421 , ARM64_INS_INCD = 422 , ARM64_INS_INCH = 423 , ARM64_INS_INCP = 424 , ARM64_INS_INCW = 425 , ARM64_INS_INDEX = 426 , ARM64_INS_INS = 427 , ARM64_INS_INSR = 428 , ARM64_INS_IRG = 429 , ARM64_INS_ISB = 430 , ARM64_INS_LASTA = 431 , ARM64_INS_LASTB = 432 , ARM64_INS_LD1 = 433 , ARM64_INS_LD1B = 434 , ARM64_INS_LD1D = 435 , ARM64_INS_LD1H = 436 , ARM64_INS_LD1Q = 437 , ARM64_INS_LD1R = 438 , ARM64_INS_LD1RB = 439 , ARM64_INS_LD1RD = 440 , ARM64_INS_LD1RH = 441 , ARM64_INS_LD1ROB = 442 , ARM64_INS_LD1ROD = 443 , ARM64_INS_LD1ROH = 444 , ARM64_INS_LD1ROW = 445 , ARM64_INS_LD1RQB = 446 , ARM64_INS_LD1RQD = 447 , ARM64_INS_LD1RQH = 448 , ARM64_INS_LD1RQW = 449 , ARM64_INS_LD1RSB = 450 , ARM64_INS_LD1RSH = 451 , ARM64_INS_LD1RSW = 452 , ARM64_INS_LD1RW = 453 , ARM64_INS_LD1SB = 454 , ARM64_INS_LD1SH = 455 , ARM64_INS_LD1SW = 456 , ARM64_INS_LD1W = 457 , ARM64_INS_LD2 = 458 , ARM64_INS_LD2B = 459 , ARM64_INS_LD2D = 460 , ARM64_INS_LD2H = 461 , ARM64_INS_LD2R = 462 , ARM64_INS_LD2W = 463 , ARM64_INS_LD3 = 464 , ARM64_INS_LD3B = 465 , ARM64_INS_LD3D = 466 , ARM64_INS_LD3H = 467 , ARM64_INS_LD3R = 468 , ARM64_INS_LD3W = 469 , ARM64_INS_LD4 = 470 , ARM64_INS_LD4B = 471 , ARM64_INS_LD4D = 472 , ARM64_INS_LD4H = 473 , ARM64_INS_LD4R = 474 , ARM64_INS_LD4W = 475 , ARM64_INS_LD64B = 476 , ARM64_INS_LDADD = 477 , ARM64_INS_LDADDA = 478 , ARM64_INS_LDADDAB = 479 , ARM64_INS_LDADDAH = 480 , ARM64_INS_LDADDAL = 481 , ARM64_INS_LDADDALB = 482 , ARM64_INS_LDADDALH = 483 , ARM64_INS_LDADDB = 484 , ARM64_INS_LDADDH = 485 , ARM64_INS_LDADDL = 486 , ARM64_INS_LDADDLB = 487 , ARM64_INS_LDADDLH = 488 , ARM64_INS_LDAPR = 489 , ARM64_INS_LDAPRB = 490 , ARM64_INS_LDAPRH = 491 , ARM64_INS_LDAPUR = 492 , ARM64_INS_LDAPURB = 493 , ARM64_INS_LDAPURH = 494 , ARM64_INS_LDAPURSB = 495 , ARM64_INS_LDAPURSH = 496 , ARM64_INS_LDAPURSW = 497 , ARM64_INS_LDAR = 498 , ARM64_INS_LDARB = 499 , ARM64_INS_LDARH = 500 , ARM64_INS_LDAXP = 501 , ARM64_INS_LDAXR = 502 , ARM64_INS_LDAXRB = 503 , ARM64_INS_LDAXRH = 504 , ARM64_INS_LDCLR = 505 , ARM64_INS_LDCLRA = 506 , ARM64_INS_LDCLRAB = 507 , ARM64_INS_LDCLRAH = 508 , ARM64_INS_LDCLRAL = 509 , ARM64_INS_LDCLRALB = 510 , ARM64_INS_LDCLRALH = 511 , ARM64_INS_LDCLRB = 512 , ARM64_INS_LDCLRH = 513 , ARM64_INS_LDCLRL = 514 , ARM64_INS_LDCLRLB = 515 , ARM64_INS_LDCLRLH = 516 , ARM64_INS_LDEOR = 517 , ARM64_INS_LDEORA = 518 , ARM64_INS_LDEORAB = 519 , ARM64_INS_LDEORAH = 520 , ARM64_INS_LDEORAL = 521 , ARM64_INS_LDEORALB = 522 , ARM64_INS_LDEORALH = 523 , ARM64_INS_LDEORB = 524 , ARM64_INS_LDEORH = 525 , ARM64_INS_LDEORL = 526 , ARM64_INS_LDEORLB = 527 , ARM64_INS_LDEORLH = 528 , ARM64_INS_LDFF1B = 529 , ARM64_INS_LDFF1D = 530 , ARM64_INS_LDFF1H = 531 , ARM64_INS_LDFF1SB = 532 , ARM64_INS_LDFF1SH = 533 , ARM64_INS_LDFF1SW = 534 , ARM64_INS_LDFF1W = 535 , ARM64_INS_LDG = 536 , ARM64_INS_LDGM = 537 , ARM64_INS_LDLAR = 538 , ARM64_INS_LDLARB = 539 , ARM64_INS_LDLARH = 540 , ARM64_INS_LDNF1B = 541 , ARM64_INS_LDNF1D = 542 , ARM64_INS_LDNF1H = 543 , ARM64_INS_LDNF1SB = 544 , ARM64_INS_LDNF1SH = 545 , ARM64_INS_LDNF1SW = 546 , ARM64_INS_LDNF1W = 547 , ARM64_INS_LDNP = 548 , ARM64_INS_LDNT1B = 549 , ARM64_INS_LDNT1D = 550 , ARM64_INS_LDNT1H = 551 , ARM64_INS_LDNT1SB = 552 , ARM64_INS_LDNT1SH = 553 , ARM64_INS_LDNT1SW = 554 , ARM64_INS_LDNT1W = 555 , ARM64_INS_LDP = 556 , ARM64_INS_LDPSW = 557 , ARM64_INS_LDR = 558 , ARM64_INS_LDRAA = 559 , ARM64_INS_LDRAB = 560 , ARM64_INS_LDRB = 561 , ARM64_INS_LDRH = 562 , ARM64_INS_LDRSB = 563 , ARM64_INS_LDRSH = 564 , ARM64_INS_LDRSW = 565 , ARM64_INS_LDSET = 566 , ARM64_INS_LDSETA = 567 , ARM64_INS_LDSETAB = 568 , ARM64_INS_LDSETAH = 569 , ARM64_INS_LDSETAL = 570 , ARM64_INS_LDSETALB = 571 , ARM64_INS_LDSETALH = 572 , ARM64_INS_LDSETB = 573 , ARM64_INS_LDSETH = 574 , ARM64_INS_LDSETL = 575 , ARM64_INS_LDSETLB = 576 , ARM64_INS_LDSETLH = 577 , ARM64_INS_LDSMAX = 578 , ARM64_INS_LDSMAXA = 579 , ARM64_INS_LDSMAXAB = 580 , ARM64_INS_LDSMAXAH = 581 , ARM64_INS_LDSMAXAL = 582 , ARM64_INS_LDSMAXALB = 583 , ARM64_INS_LDSMAXALH = 584 , ARM64_INS_LDSMAXB = 585 , ARM64_INS_LDSMAXH = 586 , ARM64_INS_LDSMAXL = 587 , ARM64_INS_LDSMAXLB = 588 , ARM64_INS_LDSMAXLH = 589 , ARM64_INS_LDSMIN = 590 , ARM64_INS_LDSMINA = 591 , ARM64_INS_LDSMINAB = 592 , ARM64_INS_LDSMINAH = 593 , ARM64_INS_LDSMINAL = 594 , ARM64_INS_LDSMINALB = 595 , ARM64_INS_LDSMINALH = 596 , ARM64_INS_LDSMINB = 597 , ARM64_INS_LDSMINH = 598 , ARM64_INS_LDSMINL = 599 , ARM64_INS_LDSMINLB = 600 , ARM64_INS_LDSMINLH = 601 , ARM64_INS_LDTR = 602 , ARM64_INS_LDTRB = 603 , ARM64_INS_LDTRH = 604 , ARM64_INS_LDTRSB = 605 , ARM64_INS_LDTRSH = 606 , ARM64_INS_LDTRSW = 607 , ARM64_INS_LDUMAX = 608 , ARM64_INS_LDUMAXA = 609 , ARM64_INS_LDUMAXAB = 610 , ARM64_INS_LDUMAXAH = 611 , ARM64_INS_LDUMAXAL = 612 , ARM64_INS_LDUMAXALB = 613 , ARM64_INS_LDUMAXALH = 614 , ARM64_INS_LDUMAXB = 615 , ARM64_INS_LDUMAXH = 616 , ARM64_INS_LDUMAXL = 617 , ARM64_INS_LDUMAXLB = 618 , ARM64_INS_LDUMAXLH = 619 , ARM64_INS_LDUMIN = 620 , ARM64_INS_LDUMINA = 621 , ARM64_INS_LDUMINAB = 622 , ARM64_INS_LDUMINAH = 623 , ARM64_INS_LDUMINAL = 624 , ARM64_INS_LDUMINALB = 625 , ARM64_INS_LDUMINALH = 626 , ARM64_INS_LDUMINB = 627 , ARM64_INS_LDUMINH = 628 , ARM64_INS_LDUMINL = 629 , ARM64_INS_LDUMINLB = 630 , ARM64_INS_LDUMINLH = 631 , ARM64_INS_LDUR = 632 , ARM64_INS_LDURB = 633 , ARM64_INS_LDURH = 634 , ARM64_INS_LDURSB = 635 , ARM64_INS_LDURSH = 636 , ARM64_INS_LDURSW = 637 , ARM64_INS_LDXP = 638 , ARM64_INS_LDXR = 639 , ARM64_INS_LDXRB = 640 , ARM64_INS_LDXRH = 641 , ARM64_INS_LSL = 642 , ARM64_INS_LSLR = 643 , ARM64_INS_LSLV = 644 , ARM64_INS_LSR = 645 , ARM64_INS_LSRR = 646 , ARM64_INS_LSRV = 647 , ARM64_INS_MAD = 648 , ARM64_INS_MADD = 649 , ARM64_INS_MATCH = 650 , ARM64_INS_MLA = 651 , ARM64_INS_MLS = 652 , ARM64_INS_MNEG = 653 , ARM64_INS_MOV = 654 , ARM64_INS_MOVA = 655 , ARM64_INS_MOVI = 656 , ARM64_INS_MOVK = 657 , ARM64_INS_MOVN = 658 , ARM64_INS_MOVPRFX = 659 , ARM64_INS_MOVS = 660 , ARM64_INS_MOVZ = 661 , ARM64_INS_MRS = 662 , ARM64_INS_MSB = 663 , ARM64_INS_MSR = 664 , ARM64_INS_MSUB = 665 , ARM64_INS_MUL = 666 , ARM64_INS_MVN = 667 , ARM64_INS_MVNI = 668 , ARM64_INS_NAND = 669 , ARM64_INS_NANDS = 670 , ARM64_INS_NBSL = 671 , ARM64_INS_NEG = 672 , ARM64_INS_NEGS = 673 , ARM64_INS_NGC = 674 , ARM64_INS_NGCS = 675 , ARM64_INS_NMATCH = 676 , ARM64_INS_NOP = 677 , ARM64_INS_NOR = 678 , ARM64_INS_NORS = 679 , ARM64_INS_NOT = 680 , ARM64_INS_NOTS = 681 , ARM64_INS_ORN = 682 , ARM64_INS_ORNS = 683 , ARM64_INS_ORR = 684 , ARM64_INS_ORRS = 685 , ARM64_INS_ORV = 686 , ARM64_INS_PACDA = 687 , ARM64_INS_PACDB = 688 , ARM64_INS_PACDZA = 689 , ARM64_INS_PACDZB = 690 , ARM64_INS_PACGA = 691 , ARM64_INS_PACIA = 692 , ARM64_INS_PACIA1716 = 693 , ARM64_INS_PACIASP = 694 , ARM64_INS_PACIAZ = 695 , ARM64_INS_PACIB = 696 , ARM64_INS_PACIB1716 = 697 , ARM64_INS_PACIBSP = 698 , ARM64_INS_PACIBZ = 699 , ARM64_INS_PACIZA = 700 , ARM64_INS_PACIZB = 701 , ARM64_INS_PFALSE = 702 , ARM64_INS_PFIRST = 703 , ARM64_INS_PMUL = 704 , ARM64_INS_PMULL = 705 , ARM64_INS_PMULL2 = 706 , ARM64_INS_PMULLB = 707 , ARM64_INS_PMULLT = 708 , ARM64_INS_PNEXT = 709 , ARM64_INS_PRFB = 710 , ARM64_INS_PRFD = 711 , ARM64_INS_PRFH = 712 , ARM64_INS_PRFM = 713 , ARM64_INS_PRFUM = 714 , ARM64_INS_PRFW = 715 , ARM64_INS_PSB = 716 , ARM64_INS_PSEL = 717 , ARM64_INS_PSSBB = 718 , ARM64_INS_PTEST = 719 , ARM64_INS_PTRUE = 720 , ARM64_INS_PTRUES = 721 , ARM64_INS_PUNPKHI = 722 , ARM64_INS_PUNPKLO = 723 , ARM64_INS_RADDHN = 724 , ARM64_INS_RADDHN2 = 725 , ARM64_INS_RADDHNB = 726 , ARM64_INS_RADDHNT = 727 , ARM64_INS_RAX1 = 728 , ARM64_INS_RBIT = 729 , ARM64_INS_RDFFR = 730 , ARM64_INS_RDFFRS = 731 , ARM64_INS_RDVL = 732 , ARM64_INS_RET = 733 , ARM64_INS_RETAA = 734 , ARM64_INS_RETAB = 735 , ARM64_INS_REV = 736 , ARM64_INS_REV16 = 737 , ARM64_INS_REV32 = 738 , ARM64_INS_REV64 = 739 , ARM64_INS_REVB = 740 , ARM64_INS_REVD = 741 , ARM64_INS_REVH = 742 , ARM64_INS_REVW = 743 , ARM64_INS_RMIF = 744 , ARM64_INS_ROR = 745 , ARM64_INS_RORV = 746 , ARM64_INS_RSHRN = 747 , ARM64_INS_RSHRN2 = 748 , ARM64_INS_RSHRNB = 749 , ARM64_INS_RSHRNT = 750 , ARM64_INS_RSUBHN = 751 , ARM64_INS_RSUBHN2 = 752 , ARM64_INS_RSUBHNB = 753 , ARM64_INS_RSUBHNT = 754 , ARM64_INS_SABA = 755 , ARM64_INS_SABAL = 756 , ARM64_INS_SABAL2 = 757 , ARM64_INS_SABALB = 758 , ARM64_INS_SABALT = 759 , ARM64_INS_SABD = 760 , ARM64_INS_SABDL = 761 , ARM64_INS_SABDL2 = 762 , ARM64_INS_SABDLB = 763 , ARM64_INS_SABDLT = 764 , ARM64_INS_SADALP = 765 , ARM64_INS_SADDL = 766 , ARM64_INS_SADDL2 = 767 , ARM64_INS_SADDLB = 768 , ARM64_INS_SADDLBT = 769 , ARM64_INS_SADDLP = 770 , ARM64_INS_SADDLT = 771 , ARM64_INS_SADDLV = 772 , ARM64_INS_SADDV = 773 , ARM64_INS_SADDW = 774 , ARM64_INS_SADDW2 = 775 , ARM64_INS_SADDWB = 776 , ARM64_INS_SADDWT = 777 , ARM64_INS_SB = 778 , ARM64_INS_SBC = 779 , ARM64_INS_SBCLB = 780 , ARM64_INS_SBCLT = 781 , ARM64_INS_SBCS = 782 , ARM64_INS_SBFM = 783 , ARM64_INS_SCLAMP = 784 , ARM64_INS_SCVTF = 785 , ARM64_INS_SDIV = 786 , ARM64_INS_SDIVR = 787 , ARM64_INS_SDOT = 788 , ARM64_INS_SEL = 789 , ARM64_INS_SETE = 790 , ARM64_INS_SETEN = 791 , ARM64_INS_SETET = 792 , ARM64_INS_SETETN = 793 , ARM64_INS_SETF16 = 794 , ARM64_INS_SETF8 = 795 , ARM64_INS_SETFFR = 796 , ARM64_INS_SETGE = 797 , ARM64_INS_SETGEN = 798 , ARM64_INS_SETGET = 799 , ARM64_INS_SETGETN = 800 , ARM64_INS_SETGM = 801 , ARM64_INS_SETGMN = 802 , ARM64_INS_SETGMT = 803 , ARM64_INS_SETGMTN = 804 , ARM64_INS_SETGP = 805 , ARM64_INS_SETGPN = 806 , ARM64_INS_SETGPT = 807 , ARM64_INS_SETGPTN = 808 , ARM64_INS_SETM = 809 , ARM64_INS_SETMN = 810 , ARM64_INS_SETMT = 811 , ARM64_INS_SETMTN = 812 , ARM64_INS_SETP = 813 , ARM64_INS_SETPN = 814 , ARM64_INS_SETPT = 815 , ARM64_INS_SETPTN = 816 , ARM64_INS_SEV = 817 , ARM64_INS_SEVL = 818 , ARM64_INS_SHA1C = 819 , ARM64_INS_SHA1H = 820 , ARM64_INS_SHA1M = 821 , ARM64_INS_SHA1P = 822 , ARM64_INS_SHA1SU0 = 823 , ARM64_INS_SHA1SU1 = 824 , ARM64_INS_SHA256H = 825 , ARM64_INS_SHA256H2 = 826 , ARM64_INS_SHA256SU0 = 827 , ARM64_INS_SHA256SU1 = 828 , ARM64_INS_SHA512H = 829 , ARM64_INS_SHA512H2 = 830 , ARM64_INS_SHA512SU0 = 831 , ARM64_INS_SHA512SU1 = 832 , ARM64_INS_SHADD = 833 , ARM64_INS_SHL = 834 , ARM64_INS_SHLL = 835 , ARM64_INS_SHLL2 = 836 , ARM64_INS_SHRN = 837 , ARM64_INS_SHRN2 = 838 , ARM64_INS_SHRNB = 839 , ARM64_INS_SHRNT = 840 , ARM64_INS_SHSUB = 841 , ARM64_INS_SHSUBR = 842 , ARM64_INS_SLI = 843 , ARM64_INS_SM3PARTW1 = 844 , ARM64_INS_SM3PARTW2 = 845 , ARM64_INS_SM3SS1 = 846 , ARM64_INS_SM3TT1A = 847 , ARM64_INS_SM3TT1B = 848 , ARM64_INS_SM3TT2A = 849 , ARM64_INS_SM3TT2B = 850 , ARM64_INS_SM4E = 851 , ARM64_INS_SM4EKEY = 852 , ARM64_INS_SMADDL = 853 , ARM64_INS_SMAX = 854 , ARM64_INS_SMAXP = 855 , ARM64_INS_SMAXV = 856 , ARM64_INS_SMC = 857 , ARM64_INS_SMIN = 858 , ARM64_INS_SMINP = 859 , ARM64_INS_SMINV = 860 , ARM64_INS_SMLAL = 861 , ARM64_INS_SMLAL2 = 862 , ARM64_INS_SMLALB = 863 , ARM64_INS_SMLALT = 864 , ARM64_INS_SMLSL = 865 , ARM64_INS_SMLSL2 = 866 , ARM64_INS_SMLSLB = 867 , ARM64_INS_SMLSLT = 868 , ARM64_INS_SMMLA = 869 , ARM64_INS_SMNEGL = 870 , ARM64_INS_SMOPA = 871 , ARM64_INS_SMOPS = 872 , ARM64_INS_SMOV = 873 , ARM64_INS_SMSTART = 874 , ARM64_INS_SMSTOP = 875 , ARM64_INS_SMSUBL = 876 , ARM64_INS_SMULH = 877 , ARM64_INS_SMULL = 878 , ARM64_INS_SMULL2 = 879 , ARM64_INS_SMULLB = 880 , ARM64_INS_SMULLT = 881 , ARM64_INS_SPLICE = 882 , ARM64_INS_SQABS = 883 , ARM64_INS_SQADD = 884 , ARM64_INS_SQCADD = 885 , ARM64_INS_SQDECB = 886 , ARM64_INS_SQDECD = 887 , ARM64_INS_SQDECH = 888 , ARM64_INS_SQDECP = 889 , ARM64_INS_SQDECW = 890 , ARM64_INS_SQDMLAL = 891 , ARM64_INS_SQDMLAL2 = 892 , ARM64_INS_SQDMLALB = 893 , ARM64_INS_SQDMLALBT = 894 , ARM64_INS_SQDMLALT = 895 , ARM64_INS_SQDMLSL = 896 , ARM64_INS_SQDMLSL2 = 897 , ARM64_INS_SQDMLSLB = 898 , ARM64_INS_SQDMLSLBT = 899 , ARM64_INS_SQDMLSLT = 900 , ARM64_INS_SQDMULH = 901 , ARM64_INS_SQDMULL = 902 , ARM64_INS_SQDMULL2 = 903 , ARM64_INS_SQDMULLB = 904 , ARM64_INS_SQDMULLT = 905 , ARM64_INS_SQINCB = 906 , ARM64_INS_SQINCD = 907 , ARM64_INS_SQINCH = 908 , ARM64_INS_SQINCP = 909 , ARM64_INS_SQINCW = 910 , ARM64_INS_SQNEG = 911 , ARM64_INS_SQRDCMLAH = 912 , ARM64_INS_SQRDMLAH = 913 , ARM64_INS_SQRDMLSH = 914 , ARM64_INS_SQRDMULH = 915 , ARM64_INS_SQRSHL = 916 , ARM64_INS_SQRSHLR = 917 , ARM64_INS_SQRSHRN = 918 , ARM64_INS_SQRSHRN2 = 919 , ARM64_INS_SQRSHRNB = 920 , ARM64_INS_SQRSHRNT = 921 , ARM64_INS_SQRSHRUN = 922 , ARM64_INS_SQRSHRUN2 = 923 , ARM64_INS_SQRSHRUNB = 924 , ARM64_INS_SQRSHRUNT = 925 , ARM64_INS_SQSHL = 926 , ARM64_INS_SQSHLR = 927 , ARM64_INS_SQSHLU = 928 , ARM64_INS_SQSHRN = 929 , ARM64_INS_SQSHRN2 = 930 , ARM64_INS_SQSHRNB = 931 , ARM64_INS_SQSHRNT = 932 , ARM64_INS_SQSHRUN = 933 , ARM64_INS_SQSHRUN2 = 934 , ARM64_INS_SQSHRUNB = 935 , ARM64_INS_SQSHRUNT = 936 , ARM64_INS_SQSUB = 937 , ARM64_INS_SQSUBR = 938 , ARM64_INS_SQXTN = 939 , ARM64_INS_SQXTN2 = 940 , ARM64_INS_SQXTNB = 941 , ARM64_INS_SQXTNT = 942 , ARM64_INS_SQXTUN = 943 , ARM64_INS_SQXTUN2 = 944 , ARM64_INS_SQXTUNB = 945 , ARM64_INS_SQXTUNT = 946 , ARM64_INS_SRHADD = 947 , ARM64_INS_SRI = 948 , ARM64_INS_SRSHL = 949 , ARM64_INS_SRSHLR = 950 , ARM64_INS_SRSHR = 951 , ARM64_INS_SRSRA = 952 , ARM64_INS_SSBB = 953 , ARM64_INS_SSHL = 954 , ARM64_INS_SSHLL = 955 , ARM64_INS_SSHLL2 = 956 , ARM64_INS_SSHLLB = 957 , ARM64_INS_SSHLLT = 958 , ARM64_INS_SSHR = 959 , ARM64_INS_SSRA = 960 , ARM64_INS_SSUBL = 961 , ARM64_INS_SSUBL2 = 962 , ARM64_INS_SSUBLB = 963 , ARM64_INS_SSUBLBT = 964 , ARM64_INS_SSUBLT = 965 , ARM64_INS_SSUBLTB = 966 , ARM64_INS_SSUBW = 967 , ARM64_INS_SSUBW2 = 968 , ARM64_INS_SSUBWB = 969 , ARM64_INS_SSUBWT = 970 , ARM64_INS_ST1 = 971 , ARM64_INS_ST1B = 972 , ARM64_INS_ST1D = 973 , ARM64_INS_ST1H = 974 , ARM64_INS_ST1Q = 975 , ARM64_INS_ST1W = 976 , ARM64_INS_ST2 = 977 , ARM64_INS_ST2B = 978 , ARM64_INS_ST2D = 979 , ARM64_INS_ST2G = 980 , ARM64_INS_ST2H = 981 , ARM64_INS_ST2W = 982 , ARM64_INS_ST3 = 983 , ARM64_INS_ST3B = 984 , ARM64_INS_ST3D = 985 , ARM64_INS_ST3H = 986 , ARM64_INS_ST3W = 987 , ARM64_INS_ST4 = 988 , ARM64_INS_ST4B = 989 , ARM64_INS_ST4D = 990 , ARM64_INS_ST4H = 991 , ARM64_INS_ST4W = 992 , ARM64_INS_ST64B = 993 , ARM64_INS_ST64BV = 994 , ARM64_INS_ST64BV0 = 995 , ARM64_INS_STADD = 996 , ARM64_INS_STADDB = 997 , ARM64_INS_STADDH = 998 , ARM64_INS_STADDL = 999 , ARM64_INS_STADDLB = 1000 , ARM64_INS_STADDLH = 1001 , ARM64_INS_STCLR = 1002 , ARM64_INS_STCLRB = 1003 , ARM64_INS_STCLRH = 1004 , ARM64_INS_STCLRL = 1005 , ARM64_INS_STCLRLB = 1006 , ARM64_INS_STCLRLH = 1007 , ARM64_INS_STEOR = 1008 , ARM64_INS_STEORB = 1009 , ARM64_INS_STEORH = 1010 , ARM64_INS_STEORL = 1011 , ARM64_INS_STEORLB = 1012 , ARM64_INS_STEORLH = 1013 , ARM64_INS_STG = 1014 , ARM64_INS_STGM = 1015 , ARM64_INS_STGP = 1016 , ARM64_INS_STLLR = 1017 , ARM64_INS_STLLRB = 1018 , ARM64_INS_STLLRH = 1019 , ARM64_INS_STLR = 1020 , ARM64_INS_STLRB = 1021 , ARM64_INS_STLRH = 1022 , ARM64_INS_STLUR = 1023 , ARM64_INS_STLURB = 1024 , ARM64_INS_STLURH = 1025 , ARM64_INS_STLXP = 1026 , ARM64_INS_STLXR = 1027 , ARM64_INS_STLXRB = 1028 , ARM64_INS_STLXRH = 1029 , ARM64_INS_STNP = 1030 , ARM64_INS_STNT1B = 1031 , ARM64_INS_STNT1D = 1032 , ARM64_INS_STNT1H = 1033 , ARM64_INS_STNT1W = 1034 , ARM64_INS_STP = 1035 , ARM64_INS_STR = 1036 , ARM64_INS_STRB = 1037 , ARM64_INS_STRH = 1038 , ARM64_INS_STSET = 1039 , ARM64_INS_STSETB = 1040 , ARM64_INS_STSETH = 1041 , ARM64_INS_STSETL = 1042 , ARM64_INS_STSETLB = 1043 , ARM64_INS_STSETLH = 1044 , ARM64_INS_STSMAX = 1045 , ARM64_INS_STSMAXB = 1046 , ARM64_INS_STSMAXH = 1047 , ARM64_INS_STSMAXL = 1048 , ARM64_INS_STSMAXLB = 1049 , ARM64_INS_STSMAXLH = 1050 , ARM64_INS_STSMIN = 1051 , ARM64_INS_STSMINB = 1052 , ARM64_INS_STSMINH = 1053 , ARM64_INS_STSMINL = 1054 , ARM64_INS_STSMINLB = 1055 , ARM64_INS_STSMINLH = 1056 , ARM64_INS_STTR = 1057 , ARM64_INS_STTRB = 1058 , ARM64_INS_STTRH = 1059 , ARM64_INS_STUMAX = 1060 , ARM64_INS_STUMAXB = 1061 , ARM64_INS_STUMAXH = 1062 , ARM64_INS_STUMAXL = 1063 , ARM64_INS_STUMAXLB = 1064 , ARM64_INS_STUMAXLH = 1065 , ARM64_INS_STUMIN = 1066 , ARM64_INS_STUMINB = 1067 , ARM64_INS_STUMINH = 1068 , ARM64_INS_STUMINL = 1069 , ARM64_INS_STUMINLB = 1070 , ARM64_INS_STUMINLH = 1071 , ARM64_INS_STUR = 1072 , ARM64_INS_STURB = 1073 , ARM64_INS_STURH = 1074 , ARM64_INS_STXP = 1075 , ARM64_INS_STXR = 1076 , ARM64_INS_STXRB = 1077 , ARM64_INS_STXRH = 1078 , ARM64_INS_STZ2G = 1079 , ARM64_INS_STZG = 1080 , ARM64_INS_STZGM = 1081 , ARM64_INS_SUB = 1082 , ARM64_INS_SUBG = 1083 , ARM64_INS_SUBHN = 1084 , ARM64_INS_SUBHN2 = 1085 , ARM64_INS_SUBHNB = 1086 , ARM64_INS_SUBHNT = 1087 , ARM64_INS_SUBP = 1088 , ARM64_INS_SUBPS = 1089 , ARM64_INS_SUBR = 1090 , ARM64_INS_SUBS = 1091 , ARM64_INS_SUDOT = 1092 , ARM64_INS_SUMOPA = 1093 , ARM64_INS_SUMOPS = 1094 , ARM64_INS_SUNPKHI = 1095 , ARM64_INS_SUNPKLO = 1096 , ARM64_INS_SUQADD = 1097 , ARM64_INS_SVC = 1098 , ARM64_INS_SWP = 1099 , ARM64_INS_SWPA = 1100 , ARM64_INS_SWPAB = 1101 , ARM64_INS_SWPAH = 1102 , ARM64_INS_SWPAL = 1103 , ARM64_INS_SWPALB = 1104 , ARM64_INS_SWPALH = 1105 , ARM64_INS_SWPB = 1106 , ARM64_INS_SWPH = 1107 , ARM64_INS_SWPL = 1108 , ARM64_INS_SWPLB = 1109 , ARM64_INS_SWPLH = 1110 , ARM64_INS_SXTB = 1111 , ARM64_INS_SXTH = 1112 , ARM64_INS_SXTL = 1113 , ARM64_INS_SXTL2 = 1114 , ARM64_INS_SXTW = 1115 , ARM64_INS_SYS = 1116 , ARM64_INS_SYSL = 1117 , ARM64_INS_TBL = 1118 , ARM64_INS_TBNZ = 1119 , ARM64_INS_TBX = 1120 , ARM64_INS_TBZ = 1121 , ARM64_INS_TCANCEL = 1122 , ARM64_INS_TCOMMIT = 1123 , ARM64_INS_TRN1 = 1124 , ARM64_INS_TRN2 = 1125 , ARM64_INS_TSB = 1126 , ARM64_INS_TST = 1127 , ARM64_INS_TSTART = 1128 , ARM64_INS_TTEST = 1129 , ARM64_INS_UABA = 1130 , ARM64_INS_UABAL = 1131 , ARM64_INS_UABAL2 = 1132 , ARM64_INS_UABALB = 1133 , ARM64_INS_UABALT = 1134 , ARM64_INS_UABD = 1135 , ARM64_INS_UABDL = 1136 , ARM64_INS_UABDL2 = 1137 , ARM64_INS_UABDLB = 1138 , ARM64_INS_UABDLT = 1139 , ARM64_INS_UADALP = 1140 , ARM64_INS_UADDL = 1141 , ARM64_INS_UADDL2 = 1142 , ARM64_INS_UADDLB = 1143 , ARM64_INS_UADDLP = 1144 , ARM64_INS_UADDLT = 1145 , ARM64_INS_UADDLV = 1146 , ARM64_INS_UADDV = 1147 , ARM64_INS_UADDW = 1148 , ARM64_INS_UADDW2 = 1149 , ARM64_INS_UADDWB = 1150 , ARM64_INS_UADDWT = 1151 , ARM64_INS_UBFM = 1152 , ARM64_INS_UCLAMP = 1153 , ARM64_INS_UCVTF = 1154 , ARM64_INS_UDF = 1155 , ARM64_INS_UDIV = 1156 , ARM64_INS_UDIVR = 1157 , ARM64_INS_UDOT = 1158 , ARM64_INS_UHADD = 1159 , ARM64_INS_UHSUB = 1160 , ARM64_INS_UHSUBR = 1161 , ARM64_INS_UMADDL = 1162 , ARM64_INS_UMAX = 1163 , ARM64_INS_UMAXP = 1164 , ARM64_INS_UMAXV = 1165 , ARM64_INS_UMIN = 1166 , ARM64_INS_UMINP = 1167 , ARM64_INS_UMINV = 1168 , ARM64_INS_UMLAL = 1169 , ARM64_INS_UMLAL2 = 1170 , ARM64_INS_UMLALB = 1171 , ARM64_INS_UMLALT = 1172 , ARM64_INS_UMLSL = 1173 , ARM64_INS_UMLSL2 = 1174 , ARM64_INS_UMLSLB = 1175 , ARM64_INS_UMLSLT = 1176 , ARM64_INS_UMMLA = 1177 , ARM64_INS_UMNEGL = 1178 , ARM64_INS_UMOPA = 1179 , ARM64_INS_UMOPS = 1180 , ARM64_INS_UMOV = 1181 , ARM64_INS_UMSUBL = 1182 , ARM64_INS_UMULH = 1183 , ARM64_INS_UMULL = 1184 , ARM64_INS_UMULL2 = 1185 , ARM64_INS_UMULLB = 1186 , ARM64_INS_UMULLT = 1187 , ARM64_INS_UQADD = 1188 , ARM64_INS_UQDECB = 1189 , ARM64_INS_UQDECD = 1190 , ARM64_INS_UQDECH = 1191 , ARM64_INS_UQDECP = 1192 , ARM64_INS_UQDECW = 1193 , ARM64_INS_UQINCB = 1194 , ARM64_INS_UQINCD = 1195 , ARM64_INS_UQINCH = 1196 , ARM64_INS_UQINCP = 1197 , ARM64_INS_UQINCW = 1198 , ARM64_INS_UQRSHL = 1199 , ARM64_INS_UQRSHLR = 1200 , ARM64_INS_UQRSHRN = 1201 , ARM64_INS_UQRSHRN2 = 1202 , ARM64_INS_UQRSHRNB = 1203 , ARM64_INS_UQRSHRNT = 1204 , ARM64_INS_UQSHL = 1205 , ARM64_INS_UQSHLR = 1206 , ARM64_INS_UQSHRN = 1207 , ARM64_INS_UQSHRN2 = 1208 , ARM64_INS_UQSHRNB = 1209 , ARM64_INS_UQSHRNT = 1210 , ARM64_INS_UQSUB = 1211 , ARM64_INS_UQSUBR = 1212 , ARM64_INS_UQXTN = 1213 , ARM64_INS_UQXTN2 = 1214 , ARM64_INS_UQXTNB = 1215 , ARM64_INS_UQXTNT = 1216 , ARM64_INS_URECPE = 1217 , ARM64_INS_URHADD = 1218 , ARM64_INS_URSHL = 1219 , ARM64_INS_URSHLR = 1220 , ARM64_INS_URSHR = 1221 , ARM64_INS_URSQRTE = 1222 , ARM64_INS_URSRA = 1223 , ARM64_INS_USDOT = 1224 , ARM64_INS_USHL = 1225 , ARM64_INS_USHLL = 1226 , ARM64_INS_USHLL2 = 1227 , ARM64_INS_USHLLB = 1228 , ARM64_INS_USHLLT = 1229 , ARM64_INS_USHR = 1230 , ARM64_INS_USMMLA = 1231 , ARM64_INS_USMOPA = 1232 , ARM64_INS_USMOPS = 1233 , ARM64_INS_USQADD = 1234 , ARM64_INS_USRA = 1235 , ARM64_INS_USUBL = 1236 , ARM64_INS_USUBL2 = 1237 , ARM64_INS_USUBLB = 1238 , ARM64_INS_USUBLT = 1239 , ARM64_INS_USUBW = 1240 , ARM64_INS_USUBW2 = 1241 , ARM64_INS_USUBWB = 1242 , ARM64_INS_USUBWT = 1243 , ARM64_INS_UUNPKHI = 1244 , ARM64_INS_UUNPKLO = 1245 , ARM64_INS_UXTB = 1246 , ARM64_INS_UXTH = 1247 , ARM64_INS_UXTL = 1248 , ARM64_INS_UXTL2 = 1249 , ARM64_INS_UXTW = 1250 , ARM64_INS_UZP1 = 1251 , ARM64_INS_UZP2 = 1252 , ARM64_INS_WFE = 1253 , ARM64_INS_WFET = 1254 , ARM64_INS_WFI = 1255 , ARM64_INS_WFIT = 1256 , ARM64_INS_WHILEGE = 1257 , ARM64_INS_WHILEGT = 1258 , ARM64_INS_WHILEHI = 1259 , ARM64_INS_WHILEHS = 1260 , ARM64_INS_WHILELE = 1261 , ARM64_INS_WHILELO = 1262 , ARM64_INS_WHILELS = 1263 , ARM64_INS_WHILELT = 1264 , ARM64_INS_WHILERW = 1265 , ARM64_INS_WHILEWR = 1266 , ARM64_INS_WRFFR = 1267 , ARM64_INS_XAFLAG = 1268 , ARM64_INS_XAR = 1269 , ARM64_INS_XPACD = 1270 , ARM64_INS_XPACI = 1271 , ARM64_INS_XPACLRI = 1272 , ARM64_INS_XTN = 1273 , ARM64_INS_XTN2 = 1274 , ARM64_INS_YIELD = 1275 , ARM64_INS_ZERO = 1276 , ARM64_INS_ZIP1 = 1277 , ARM64_INS_ZIP2 = 1278 , ARM64_INS_SBFIZ = 1279 , ARM64_INS_UBFIZ = 1280 , ARM64_INS_SBFX = 1281 , ARM64_INS_UBFX = 1282 , ARM64_INS_BFI = 1283 , ARM64_INS_BFXIL = 1284 , ARM64_INS_IC = 1285 , ARM64_INS_DC = 1286 , ARM64_INS_AT = 1287 , ARM64_INS_TLBI = 1288 , ARM64_INS_ENDING = 1289 , } # [repr (u32)] # [doc = " Group of ARM64 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM64_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM64_GRP_JUMP = 1 , ARM64_GRP_CALL = 2 , ARM64_GRP_RET = 3 , ARM64_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM64_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM64_GRP_BRANCH_RELATIVE = 7 , ARM64_GRP_PAC = 8 , ARM64_GRP_CRYPTO = 128 , ARM64_GRP_FPARMV8 = 129 , ARM64_GRP_NEON = 130 , ARM64_GRP_CRC = 131 , ARM64_GRP_AES = 132 , ARM64_GRP_DOTPROD = 133 , ARM64_GRP_FULLFP16 = 134 , ARM64_GRP_LSE = 135 , ARM64_GRP_RCPC = 136 , ARM64_GRP_RDM = 137 , ARM64_GRP_SHA2 = 138 , ARM64_GRP_SHA3 = 139 , ARM64_GRP_SM4 = 140 , ARM64_GRP_SVE = 141 , ARM64_GRP_SVE2 = 142 , ARM64_GRP_SVE2AES = 143 , ARM64_GRP_SVE2BitPerm = 144 , ARM64_GRP_SVE2SHA3 = 145 , ARM64_GRP_SVE2SM4 = 146 , ARM64_GRP_SME = 147 , ARM64_GRP_SMEF64 = 148 , ARM64_GRP_SMEI64 = 149 , ARM64_GRP_MatMulFP32 = 150 , ARM64_GRP_MatMulFP64 = 151 , ARM64_GRP_MatMulInt8 = 152 , ARM64_GRP_V8_1A = 153 , ARM64_GRP_V8_3A = 154 , ARM64_GRP_V8_4A = 155 , ARM64_GRP_ENDING = 156 , } # [repr (u32)] # [doc = " M68K registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_reg { M68K_REG_INVALID = 0 , M68K_REG_D0 = 1 , M68K_REG_D1 = 2 , M68K_REG_D2 = 3 , M68K_REG_D3 = 4 , M68K_REG_D4 = 5 , M68K_REG_D5 = 6 , M68K_REG_D6 = 7 , M68K_REG_D7 = 8 , M68K_REG_A0 = 9 , M68K_REG_A1 = 10 , M68K_REG_A2 = 11 , M68K_REG_A3 = 12 , M68K_REG_A4 = 13 , M68K_REG_A5 = 14 , M68K_REG_A6 = 15 , M68K_REG_A7 = 16 , M68K_REG_FP0 = 17 , M68K_REG_FP1 = 18 , M68K_REG_FP2 = 19 , M68K_REG_FP3 = 20 , M68K_REG_FP4 = 21 , M68K_REG_FP5 = 22 , M68K_REG_FP6 = 23 , M68K_REG_FP7 = 24 , M68K_REG_PC = 25 , M68K_REG_SR = 26 , M68K_REG_CCR = 27 , M68K_REG_SFC = 28 , M68K_REG_DFC = 29 , M68K_REG_USP = 30 , M68K_REG_VBR = 31 , M68K_REG_CACR = 32 , M68K_REG_CAAR = 33 , M68K_REG_MSP = 34 , M68K_REG_ISP = 35 , M68K_REG_TC = 36 , M68K_REG_ITT0 = 37 , M68K_REG_ITT1 = 38 , M68K_REG_DTT0 = 39 , M68K_REG_DTT1 = 40 , M68K_REG_MMUSR = 41 , M68K_REG_URP = 42 , M68K_REG_SRP = 43 , M68K_REG_FPCR = 44 , M68K_REG_FPSR = 45 , M68K_REG_FPIAR = 46 , M68K_REG_ENDING = 47 , } # [repr (u32)] # [doc = " M68K Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_address_mode { # [doc = "< No address mode."] M68K_AM_NONE = 0 , # [doc = "< Register Direct - Data"] M68K_AM_REG_DIRECT_DATA = 1 , # [doc = "< Register Direct - Address"] M68K_AM_REG_DIRECT_ADDR = 2 , # [doc = "< Register Indirect - Address"] M68K_AM_REGI_ADDR = 3 , # [doc = "< Register Indirect - Address with Postincrement"] M68K_AM_REGI_ADDR_POST_INC = 4 , # [doc = "< Register Indirect - Address with Predecrement"] M68K_AM_REGI_ADDR_PRE_DEC = 5 , # [doc = "< Register Indirect - Address with Displacement"] M68K_AM_REGI_ADDR_DISP = 6 , # [doc = "< Address Register Indirect With Index- 8-bit displacement"] M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 , # [doc = "< Address Register Indirect With Index- Base displacement"] M68K_AM_AREGI_INDEX_BASE_DISP = 8 , # [doc = "< Memory indirect - Postindex"] M68K_AM_MEMI_POST_INDEX = 9 , # [doc = "< Memory indirect - Preindex"] M68K_AM_MEMI_PRE_INDEX = 10 , # [doc = "< Program Counter Indirect - with Displacement"] M68K_AM_PCI_DISP = 11 , # [doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"] M68K_AM_PCI_INDEX_8_BIT_DISP = 12 , # [doc = "< Program Counter Indirect with Index - with Base Displacement"] M68K_AM_PCI_INDEX_BASE_DISP = 13 , # [doc = "< Program Counter Memory Indirect - Postindexed"] M68K_AM_PC_MEMI_POST_INDEX = 14 , # [doc = "< Program Counter Memory Indirect - Preindexed"] M68K_AM_PC_MEMI_PRE_INDEX = 15 , # [doc = "< Absolute Data Addressing  - Short"] M68K_AM_ABSOLUTE_DATA_SHORT = 16 , # [doc = "< Absolute Data Addressing  - Long"] M68K_AM_ABSOLUTE_DATA_LONG = 17 , # [doc = "< Immediate value"] M68K_AM_IMMEDIATE = 18 , # [doc = "< Address as displacement from (PC+2) used by branches"] M68K_AM_BRANCH_DISPLACEMENT = 19 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] M68K_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] M68K_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] M68K_OP_MEM = 3 , # [doc = "< single precision Floating-Point operand"] M68K_OP_FP_SINGLE = 4 , # [doc = "< double precision Floating-Point operand"] M68K_OP_FP_DOUBLE = 5 , # [doc = "< Register bits move"] M68K_OP_REG_BITS = 6 , # [doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"] M68K_OP_REG_PAIR = 7 , # [doc = "< Branch displacement"] M68K_OP_BR_DISP = 8 , } # [doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_mem { # [doc = "< base register (or M68K_REG_INVALID if irrelevant)"] pub base_reg : m68k_reg , # [doc = "< index register (or M68K_REG_INVALID if irrelevant)"] pub index_reg : m68k_reg , # [doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"] pub in_base_reg : m68k_reg , # [doc = "< indirect displacement"] pub in_disp : u32 , # [doc = "< other displacement"] pub out_disp : u32 , # [doc = "< displacement value"] pub disp : i16 , # [doc = "< scale for index register"] pub scale : u8 , # [doc = "< set to true if the two values below should be used"] pub bitfield : u8 , # [doc = "< used for bf* instructions"] pub width : u8 , # [doc = "< used for bf* instructions"] pub offset : u8 , # [doc = "< 0 = w, 1 = l"] pub index_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_mem"] [:: std :: mem :: size_of :: < m68k_op_mem > () - 28usize] ; ["Alignment of m68k_op_mem"] [:: std :: mem :: align_of :: < m68k_op_mem > () - 4usize] ; ["Offset of field: m68k_op_mem::base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , base_reg) - 0usize] ; ["Offset of field: m68k_op_mem::index_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_reg) - 4usize] ; ["Offset of field: m68k_op_mem::in_base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_base_reg) - 8usize] ; ["Offset of field: m68k_op_mem::in_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_disp) - 12usize] ; ["Offset of field: m68k_op_mem::out_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , out_disp) - 16usize] ; ["Offset of field: m68k_op_mem::disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , disp) - 20usize] ; ["Offset of field: m68k_op_mem::scale"] [:: std :: mem :: offset_of ! (m68k_op_mem , scale) - 22usize] ; ["Offset of field: m68k_op_mem::bitfield"] [:: std :: mem :: offset_of ! (m68k_op_mem , bitfield) - 23usize] ; ["Offset of field: m68k_op_mem::width"] [:: std :: mem :: offset_of ! (m68k_op_mem , width) - 24usize] ; ["Offset of field: m68k_op_mem::offset"] [:: std :: mem :: offset_of ! (m68k_op_mem , offset) - 25usize] ; ["Offset of field: m68k_op_mem::index_size"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_size) - 26usize] ; } ; # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_br_disp_size { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_BR_DISP_SIZE_INVALID = 0 , # [doc = "< signed 8-bit displacement"] M68K_OP_BR_DISP_SIZE_BYTE = 1 , # [doc = "< signed 16-bit displacement"] M68K_OP_BR_DISP_SIZE_WORD = 2 , # [doc = "< signed 32-bit displacement"] M68K_OP_BR_DISP_SIZE_LONG = 4 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_br_disp { # [doc = "< displacement value"] pub disp : i32 , # [doc = "< Size from m68k_op_br_disp_size type above"] pub disp_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_br_disp"] [:: std :: mem :: size_of :: < m68k_op_br_disp > () - 8usize] ; ["Alignment of m68k_op_br_disp"] [:: std :: mem :: align_of :: < m68k_op_br_disp > () - 4usize] ; ["Offset of field: m68k_op_br_disp::disp"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp) - 0usize] ; ["Offset of field: m68k_op_br_disp::disp_size"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp_size) - 4usize] ; } ; # [doc = " Register pair in one operand."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_m68k_op_reg_pair { pub reg_0 : m68k_reg , pub reg_1 : m68k_reg , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op_reg_pair"] [:: std :: mem :: size_of :: < cs_m68k_op_reg_pair > () - 8usize] ; ["Alignment of cs_m68k_op_reg_pair"] [:: std :: mem :: align_of :: < cs_m68k_op_reg_pair > () - 4usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_0"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_0) - 0usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_1"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_1) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k_op { pub __bindgen_anon_1 : cs_m68k_op__bindgen_ty_1 , # [doc = "< data when operand is targeting memory"] pub mem : m68k_op_mem , # [doc = "< data when operand is a branch displacement"] pub br_disp : m68k_op_br_disp , # [doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"] pub register_bits : u32 , pub type_ : m68k_op_type , # [doc = "< M68K addressing mode for this op"] pub address_mode : m68k_address_mode , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m68k_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< double imm"] pub dimm : f64 , # [doc = "< float imm"] pub simm : f32 , # [doc = "< register value for REG operand"] pub reg : m68k_reg , # [doc = "< register pair in one operand"] pub reg_pair : cs_m68k_op_reg_pair , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::dimm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , dimm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::simm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , simm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg_pair"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg_pair) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op"] [:: std :: mem :: size_of :: < cs_m68k_op > () - 56usize] ; ["Alignment of cs_m68k_op"] [:: std :: mem :: align_of :: < cs_m68k_op > () - 8usize] ; ["Offset of field: cs_m68k_op::mem"] [:: std :: mem :: offset_of ! (cs_m68k_op , mem) - 8usize] ; ["Offset of field: cs_m68k_op::br_disp"] [:: std :: mem :: offset_of ! (cs_m68k_op , br_disp) - 36usize] ; ["Offset of field: cs_m68k_op::register_bits"] [:: std :: mem :: offset_of ! (cs_m68k_op , register_bits) - 44usize] ; ["Offset of field: cs_m68k_op::type_"] [:: std :: mem :: offset_of ! (cs_m68k_op , type_) - 48usize] ; ["Offset of field: cs_m68k_op::address_mode"] [:: std :: mem :: offset_of ! (cs_m68k_op , address_mode) - 52usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode) } } # [repr (u32)] # [doc = " Operation size of the CPU instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_cpu_size { # [doc = "< unsized or unspecified"] M68K_CPU_SIZE_NONE = 0 , # [doc = "< 1 byte in size"] M68K_CPU_SIZE_BYTE = 1 , # [doc = "< 2 bytes in size"] M68K_CPU_SIZE_WORD = 2 , # [doc = "< 4 bytes in size"] M68K_CPU_SIZE_LONG = 4 , } # [repr (u32)] # [doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_fpu_size { # [doc = "< unsized like fsave/frestore"] M68K_FPU_SIZE_NONE = 0 , # [doc = "< 4 byte in size (single float)"] M68K_FPU_SIZE_SINGLE = 4 , # [doc = "< 8 byte in size (double)"] M68K_FPU_SIZE_DOUBLE = 8 , # [doc = "< 12 byte in size (extended real format)"] M68K_FPU_SIZE_EXTENDED = 12 , } # [repr (u32)] # [doc = " Type of size that is being used for the current instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0 , M68K_SIZE_TYPE_CPU = 1 , M68K_SIZE_TYPE_FPU = 2 , } # [doc = " Operation size of the current instruction (NOT the actually size of instruction)"] # [repr (C)] # [derive (Copy , Clone)] pub struct m68k_op_size { pub type_ : m68k_size_type , pub __bindgen_anon_1 : m68k_op_size__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union m68k_op_size__bindgen_ty_1 { pub cpu_size : m68k_cpu_size , pub fpu_size : m68k_fpu_size , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: size_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Alignment of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: align_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::cpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , cpu_size) - 0usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::fpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , fpu_size) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size"] [:: std :: mem :: size_of :: < m68k_op_size > () - 8usize] ; ["Alignment of m68k_op_size"] [:: std :: mem :: align_of :: < m68k_op_size > () - 4usize] ; ["Offset of field: m68k_op_size::type_"] [:: std :: mem :: offset_of ! (m68k_op_size , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The M68K instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k { # [doc = "< operands for this instruction."] pub operands : [cs_m68k_op ; 4usize] , # [doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"] pub op_size : m68k_op_size , # [doc = "< number of operands for the instruction"] pub op_count : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k"] [:: std :: mem :: size_of :: < cs_m68k > () - 240usize] ; ["Alignment of cs_m68k"] [:: std :: mem :: align_of :: < cs_m68k > () - 8usize] ; ["Offset of field: cs_m68k::operands"] [:: std :: mem :: offset_of ! (cs_m68k , operands) - 0usize] ; ["Offset of field: cs_m68k::op_size"] [:: std :: mem :: offset_of ! (cs_m68k , op_size) - 224usize] ; ["Offset of field: cs_m68k::op_count"] [:: std :: mem :: offset_of ! (cs_m68k , op_count) - 232usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}" , self . operands , self . op_size , self . op_count) } } # [repr (u32)] # [doc = " M68K instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_insn { M68K_INS_INVALID = 0 , M68K_INS_ABCD = 1 , M68K_INS_ADD = 2 , M68K_INS_ADDA = 3 , M68K_INS_ADDI = 4 , M68K_INS_ADDQ = 5 , M68K_INS_ADDX = 6 , M68K_INS_AND = 7 , M68K_INS_ANDI = 8 , M68K_INS_ASL = 9 , M68K_INS_ASR = 10 , M68K_INS_BHS = 11 , M68K_INS_BLO = 12 , M68K_INS_BHI = 13 , M68K_INS_BLS = 14 , M68K_INS_BCC = 15 , M68K_INS_BCS = 16 , M68K_INS_BNE = 17 , M68K_INS_BEQ = 18 , M68K_INS_BVC = 19 , M68K_INS_BVS = 20 , M68K_INS_BPL = 21 , M68K_INS_BMI = 22 , M68K_INS_BGE = 23 , M68K_INS_BLT = 24 , M68K_INS_BGT = 25 , M68K_INS_BLE = 26 , M68K_INS_BRA = 27 , M68K_INS_BSR = 28 , M68K_INS_BCHG = 29 , M68K_INS_BCLR = 30 , M68K_INS_BSET = 31 , M68K_INS_BTST = 32 , M68K_INS_BFCHG = 33 , M68K_INS_BFCLR = 34 , M68K_INS_BFEXTS = 35 , M68K_INS_BFEXTU = 36 , M68K_INS_BFFFO = 37 , M68K_INS_BFINS = 38 , M68K_INS_BFSET = 39 , M68K_INS_BFTST = 40 , M68K_INS_BKPT = 41 , M68K_INS_CALLM = 42 , M68K_INS_CAS = 43 , M68K_INS_CAS2 = 44 , M68K_INS_CHK = 45 , M68K_INS_CHK2 = 46 , M68K_INS_CLR = 47 , M68K_INS_CMP = 48 , M68K_INS_CMPA = 49 , M68K_INS_CMPI = 50 , M68K_INS_CMPM = 51 , M68K_INS_CMP2 = 52 , M68K_INS_CINVL = 53 , M68K_INS_CINVP = 54 , M68K_INS_CINVA = 55 , M68K_INS_CPUSHL = 56 , M68K_INS_CPUSHP = 57 , M68K_INS_CPUSHA = 58 , M68K_INS_DBT = 59 , M68K_INS_DBF = 60 , M68K_INS_DBHI = 61 , M68K_INS_DBLS = 62 , M68K_INS_DBCC = 63 , M68K_INS_DBCS = 64 , M68K_INS_DBNE = 65 , M68K_INS_DBEQ = 66 , M68K_INS_DBVC = 67 , M68K_INS_DBVS = 68 , M68K_INS_DBPL = 69 , M68K_INS_DBMI = 70 , M68K_INS_DBGE = 71 , M68K_INS_DBLT = 72 , M68K_INS_DBGT = 73 , M68K_INS_DBLE = 74 , M68K_INS_DBRA = 75 , M68K_INS_DIVS = 76 , M68K_INS_DIVSL = 77 , M68K_INS_DIVU = 78 , M68K_INS_DIVUL = 79 , M68K_INS_EOR = 80 , M68K_INS_EORI = 81 , M68K_INS_EXG = 82 , M68K_INS_EXT = 83 , M68K_INS_EXTB = 84 , M68K_INS_FABS = 85 , M68K_INS_FSABS = 86 , M68K_INS_FDABS = 87 , M68K_INS_FACOS = 88 , M68K_INS_FADD = 89 , M68K_INS_FSADD = 90 , M68K_INS_FDADD = 91 , M68K_INS_FASIN = 92 , M68K_INS_FATAN = 93 , M68K_INS_FATANH = 94 , M68K_INS_FBF = 95 , M68K_INS_FBEQ = 96 , M68K_INS_FBOGT = 97 , M68K_INS_FBOGE = 98 , M68K_INS_FBOLT = 99 , M68K_INS_FBOLE = 100 , M68K_INS_FBOGL = 101 , M68K_INS_FBOR = 102 , M68K_INS_FBUN = 103 , M68K_INS_FBUEQ = 104 , M68K_INS_FBUGT = 105 , M68K_INS_FBUGE = 106 , M68K_INS_FBULT = 107 , M68K_INS_FBULE = 108 , M68K_INS_FBNE = 109 , M68K_INS_FBT = 110 , M68K_INS_FBSF = 111 , M68K_INS_FBSEQ = 112 , M68K_INS_FBGT = 113 , M68K_INS_FBGE = 114 , M68K_INS_FBLT = 115 , M68K_INS_FBLE = 116 , M68K_INS_FBGL = 117 , M68K_INS_FBGLE = 118 , M68K_INS_FBNGLE = 119 , M68K_INS_FBNGL = 120 , M68K_INS_FBNLE = 121 , M68K_INS_FBNLT = 122 , M68K_INS_FBNGE = 123 , M68K_INS_FBNGT = 124 , M68K_INS_FBSNE = 125 , M68K_INS_FBST = 126 , M68K_INS_FCMP = 127 , M68K_INS_FCOS = 128 , M68K_INS_FCOSH = 129 , M68K_INS_FDBF = 130 , M68K_INS_FDBEQ = 131 , M68K_INS_FDBOGT = 132 , M68K_INS_FDBOGE = 133 , M68K_INS_FDBOLT = 134 , M68K_INS_FDBOLE = 135 , M68K_INS_FDBOGL = 136 , M68K_INS_FDBOR = 137 , M68K_INS_FDBUN = 138 , M68K_INS_FDBUEQ = 139 , M68K_INS_FDBUGT = 140 , M68K_INS_FDBUGE = 141 , M68K_INS_FDBULT = 142 , M68K_INS_FDBULE = 143 , M68K_INS_FDBNE = 144 , M68K_INS_FDBT = 145 , M68K_INS_FDBSF = 146 , M68K_INS_FDBSEQ = 147 , M68K_INS_FDBGT = 148 , M68K_INS_FDBGE = 149 , M68K_INS_FDBLT = 150 , M68K_INS_FDBLE = 151 , M68K_INS_FDBGL = 152 , M68K_INS_FDBGLE = 153 , M68K_INS_FDBNGLE = 154 , M68K_INS_FDBNGL = 155 , M68K_INS_FDBNLE = 156 , M68K_INS_FDBNLT = 157 , M68K_INS_FDBNGE = 158 , M68K_INS_FDBNGT = 159 , M68K_INS_FDBSNE = 160 , M68K_INS_FDBST = 161 , M68K_INS_FDIV = 162 , M68K_INS_FSDIV = 163 , M68K_INS_FDDIV = 164 , M68K_INS_FETOX = 165 , M68K_INS_FETOXM1 = 166 , M68K_INS_FGETEXP = 167 , M68K_INS_FGETMAN = 168 , M68K_INS_FINT = 169 , M68K_INS_FINTRZ = 170 , M68K_INS_FLOG10 = 171 , M68K_INS_FLOG2 = 172 , M68K_INS_FLOGN = 173 , M68K_INS_FLOGNP1 = 174 , M68K_INS_FMOD = 175 , M68K_INS_FMOVE = 176 , M68K_INS_FSMOVE = 177 , M68K_INS_FDMOVE = 178 , M68K_INS_FMOVECR = 179 , M68K_INS_FMOVEM = 180 , M68K_INS_FMUL = 181 , M68K_INS_FSMUL = 182 , M68K_INS_FDMUL = 183 , M68K_INS_FNEG = 184 , M68K_INS_FSNEG = 185 , M68K_INS_FDNEG = 186 , M68K_INS_FNOP = 187 , M68K_INS_FREM = 188 , M68K_INS_FRESTORE = 189 , M68K_INS_FSAVE = 190 , M68K_INS_FSCALE = 191 , M68K_INS_FSGLDIV = 192 , M68K_INS_FSGLMUL = 193 , M68K_INS_FSIN = 194 , M68K_INS_FSINCOS = 195 , M68K_INS_FSINH = 196 , M68K_INS_FSQRT = 197 , M68K_INS_FSSQRT = 198 , M68K_INS_FDSQRT = 199 , M68K_INS_FSF = 200 , M68K_INS_FSBEQ = 201 , M68K_INS_FSOGT = 202 , M68K_INS_FSOGE = 203 , M68K_INS_FSOLT = 204 , M68K_INS_FSOLE = 205 , M68K_INS_FSOGL = 206 , M68K_INS_FSOR = 207 , M68K_INS_FSUN = 208 , M68K_INS_FSUEQ = 209 , M68K_INS_FSUGT = 210 , M68K_INS_FSUGE = 211 , M68K_INS_FSULT = 212 , M68K_INS_FSULE = 213 , M68K_INS_FSNE = 214 , M68K_INS_FST = 215 , M68K_INS_FSSF = 216 , M68K_INS_FSSEQ = 217 , M68K_INS_FSGT = 218 , M68K_INS_FSGE = 219 , M68K_INS_FSLT = 220 , M68K_INS_FSLE = 221 , M68K_INS_FSGL = 222 , M68K_INS_FSGLE = 223 , M68K_INS_FSNGLE = 224 , M68K_INS_FSNGL = 225 , M68K_INS_FSNLE = 226 , M68K_INS_FSNLT = 227 , M68K_INS_FSNGE = 228 , M68K_INS_FSNGT = 229 , M68K_INS_FSSNE = 230 , M68K_INS_FSST = 231 , M68K_INS_FSUB = 232 , M68K_INS_FSSUB = 233 , M68K_INS_FDSUB = 234 , M68K_INS_FTAN = 235 , M68K_INS_FTANH = 236 , M68K_INS_FTENTOX = 237 , M68K_INS_FTRAPF = 238 , M68K_INS_FTRAPEQ = 239 , M68K_INS_FTRAPOGT = 240 , M68K_INS_FTRAPOGE = 241 , M68K_INS_FTRAPOLT = 242 , M68K_INS_FTRAPOLE = 243 , M68K_INS_FTRAPOGL = 244 , M68K_INS_FTRAPOR = 245 , M68K_INS_FTRAPUN = 246 , M68K_INS_FTRAPUEQ = 247 , M68K_INS_FTRAPUGT = 248 , M68K_INS_FTRAPUGE = 249 , M68K_INS_FTRAPULT = 250 , M68K_INS_FTRAPULE = 251 , M68K_INS_FTRAPNE = 252 , M68K_INS_FTRAPT = 253 , M68K_INS_FTRAPSF = 254 , M68K_INS_FTRAPSEQ = 255 , M68K_INS_FTRAPGT = 256 , M68K_INS_FTRAPGE = 257 , M68K_INS_FTRAPLT = 258 , M68K_INS_FTRAPLE = 259 , M68K_INS_FTRAPGL = 260 , M68K_INS_FTRAPGLE = 261 , M68K_INS_FTRAPNGLE = 262 , M68K_INS_FTRAPNGL = 263 , M68K_INS_FTRAPNLE = 264 , M68K_INS_FTRAPNLT = 265 , M68K_INS_FTRAPNGE = 266 , M68K_INS_FTRAPNGT = 267 , M68K_INS_FTRAPSNE = 268 , M68K_INS_FTRAPST = 269 , M68K_INS_FTST = 270 , M68K_INS_FTWOTOX = 271 , M68K_INS_HALT = 272 , M68K_INS_ILLEGAL = 273 , M68K_INS_JMP = 274 , M68K_INS_JSR = 275 , M68K_INS_LEA = 276 , M68K_INS_LINK = 277 , M68K_INS_LPSTOP = 278 , M68K_INS_LSL = 279 , M68K_INS_LSR = 280 , M68K_INS_MOVE = 281 , M68K_INS_MOVEA = 282 , M68K_INS_MOVEC = 283 , M68K_INS_MOVEM = 284 , M68K_INS_MOVEP = 285 , M68K_INS_MOVEQ = 286 , M68K_INS_MOVES = 287 , M68K_INS_MOVE16 = 288 , M68K_INS_MULS = 289 , M68K_INS_MULU = 290 , M68K_INS_NBCD = 291 , M68K_INS_NEG = 292 , M68K_INS_NEGX = 293 , M68K_INS_NOP = 294 , M68K_INS_NOT = 295 , M68K_INS_OR = 296 , M68K_INS_ORI = 297 , M68K_INS_PACK = 298 , M68K_INS_PEA = 299 , M68K_INS_PFLUSH = 300 , M68K_INS_PFLUSHA = 301 , M68K_INS_PFLUSHAN = 302 , M68K_INS_PFLUSHN = 303 , M68K_INS_PLOADR = 304 , M68K_INS_PLOADW = 305 , M68K_INS_PLPAR = 306 , M68K_INS_PLPAW = 307 , M68K_INS_PMOVE = 308 , M68K_INS_PMOVEFD = 309 , M68K_INS_PTESTR = 310 , M68K_INS_PTESTW = 311 , M68K_INS_PULSE = 312 , M68K_INS_REMS = 313 , M68K_INS_REMU = 314 , M68K_INS_RESET = 315 , M68K_INS_ROL = 316 , M68K_INS_ROR = 317 , M68K_INS_ROXL = 318 , M68K_INS_ROXR = 319 , M68K_INS_RTD = 320 , M68K_INS_RTE = 321 , M68K_INS_RTM = 322 , M68K_INS_RTR = 323 , M68K_INS_RTS = 324 , M68K_INS_SBCD = 325 , M68K_INS_ST = 326 , M68K_INS_SF = 327 , M68K_INS_SHI = 328 , M68K_INS_SLS = 329 , M68K_INS_SCC = 330 , M68K_INS_SHS = 331 , M68K_INS_SCS = 332 , M68K_INS_SLO = 333 , M68K_INS_SNE = 334 , M68K_INS_SEQ = 335 , M68K_INS_SVC = 336 , M68K_INS_SVS = 337 , M68K_INS_SPL = 338 , M68K_INS_SMI = 339 , M68K_INS_SGE = 340 , M68K_INS_SLT = 341 , M68K_INS_SGT = 342 , M68K_INS_SLE = 343 , M68K_INS_STOP = 344 , M68K_INS_SUB = 345 , M68K_INS_SUBA = 346 , M68K_INS_SUBI = 347 , M68K_INS_SUBQ = 348 , M68K_INS_SUBX = 349 , M68K_INS_SWAP = 350 , M68K_INS_TAS = 351 , M68K_INS_TRAP = 352 , M68K_INS_TRAPV = 353 , M68K_INS_TRAPT = 354 , M68K_INS_TRAPF = 355 , M68K_INS_TRAPHI = 356 , M68K_INS_TRAPLS = 357 , M68K_INS_TRAPCC = 358 , M68K_INS_TRAPHS = 359 , M68K_INS_TRAPCS = 360 , M68K_INS_TRAPLO = 361 , M68K_INS_TRAPNE = 362 , M68K_INS_TRAPEQ = 363 , M68K_INS_TRAPVC = 364 , M68K_INS_TRAPVS = 365 , M68K_INS_TRAPPL = 366 , M68K_INS_TRAPMI = 367 , M68K_INS_TRAPGE = 368 , M68K_INS_TRAPLT = 369 , M68K_INS_TRAPGT = 370 , M68K_INS_TRAPLE = 371 , M68K_INS_TST = 372 , M68K_INS_UNLK = 373 , M68K_INS_UNPK = 374 , M68K_INS_ENDING = 375 , } # [repr (u32)] # [doc = " Group of M68K instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_group_type { # [doc = "< CS_GRUP_INVALID"] M68K_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M68K_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] M68K_GRP_RET = 3 , # [doc = "< = CS_GRP_IRET"] M68K_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M68K_GRP_BRANCH_RELATIVE = 7 , M68K_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MIPS_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MIPS_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MIPS_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MIPS_OP_MEM = 3 , } impl mips_reg { pub const MIPS_REG_ZERO : mips_reg = mips_reg :: MIPS_REG_0 ; } impl mips_reg { pub const MIPS_REG_AT : mips_reg = mips_reg :: MIPS_REG_1 ; } impl mips_reg { pub const MIPS_REG_V0 : mips_reg = mips_reg :: MIPS_REG_2 ; } impl mips_reg { pub const MIPS_REG_V1 : mips_reg = mips_reg :: MIPS_REG_3 ; } impl mips_reg { pub const MIPS_REG_A0 : mips_reg = mips_reg :: MIPS_REG_4 ; } impl mips_reg { pub const MIPS_REG_A1 : mips_reg = mips_reg :: MIPS_REG_5 ; } impl mips_reg { pub const MIPS_REG_A2 : mips_reg = mips_reg :: MIPS_REG_6 ; } impl mips_reg { pub const MIPS_REG_A3 : mips_reg = mips_reg :: MIPS_REG_7 ; } impl mips_reg { pub const MIPS_REG_T0 : mips_reg = mips_reg :: MIPS_REG_8 ; } impl mips_reg { pub const MIPS_REG_T1 : mips_reg = mips_reg :: MIPS_REG_9 ; } impl mips_reg { pub const MIPS_REG_T2 : mips_reg = mips_reg :: MIPS_REG_10 ; } impl mips_reg { pub const MIPS_REG_T3 : mips_reg = mips_reg :: MIPS_REG_11 ; } impl mips_reg { pub const MIPS_REG_T4 : mips_reg = mips_reg :: MIPS_REG_12 ; } impl mips_reg { pub const MIPS_REG_T5 : mips_reg = mips_reg :: MIPS_REG_13 ; } impl mips_reg { pub const MIPS_REG_T6 : mips_reg = mips_reg :: MIPS_REG_14 ; } impl mips_reg { pub const MIPS_REG_T7 : mips_reg = mips_reg :: MIPS_REG_15 ; } impl mips_reg { pub const MIPS_REG_S0 : mips_reg = mips_reg :: MIPS_REG_16 ; } impl mips_reg { pub const MIPS_REG_S1 : mips_reg = mips_reg :: MIPS_REG_17 ; } impl mips_reg { pub const MIPS_REG_S2 : mips_reg = mips_reg :: MIPS_REG_18 ; } impl mips_reg { pub const MIPS_REG_S3 : mips_reg = mips_reg :: MIPS_REG_19 ; } impl mips_reg { pub const MIPS_REG_S4 : mips_reg = mips_reg :: MIPS_REG_20 ; } impl mips_reg { pub const MIPS_REG_S5 : mips_reg = mips_reg :: MIPS_REG_21 ; } impl mips_reg { pub const MIPS_REG_S6 : mips_reg = mips_reg :: MIPS_REG_22 ; } impl mips_reg { pub const MIPS_REG_S7 : mips_reg = mips_reg :: MIPS_REG_23 ; } impl mips_reg { pub const MIPS_REG_T8 : mips_reg = mips_reg :: MIPS_REG_24 ; } impl mips_reg { pub const MIPS_REG_T9 : mips_reg = mips_reg :: MIPS_REG_25 ; } impl mips_reg { pub const MIPS_REG_K0 : mips_reg = mips_reg :: MIPS_REG_26 ; } impl mips_reg { pub const MIPS_REG_K1 : mips_reg = mips_reg :: MIPS_REG_27 ; } impl mips_reg { pub const MIPS_REG_GP : mips_reg = mips_reg :: MIPS_REG_28 ; } impl mips_reg { pub const MIPS_REG_SP : mips_reg = mips_reg :: MIPS_REG_29 ; } impl mips_reg { pub const MIPS_REG_FP : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_S8 : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_RA : mips_reg = mips_reg :: MIPS_REG_31 ; } impl mips_reg { pub const MIPS_REG_HI0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_HI1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_HI2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_HI3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } impl mips_reg { pub const MIPS_REG_LO0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_LO1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_LO2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_LO3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } # [repr (u32)] # [doc = " MIPS registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_reg { MIPS_REG_INVALID = 0 , MIPS_REG_PC = 1 , MIPS_REG_0 = 2 , MIPS_REG_1 = 3 , MIPS_REG_2 = 4 , MIPS_REG_3 = 5 , MIPS_REG_4 = 6 , MIPS_REG_5 = 7 , MIPS_REG_6 = 8 , MIPS_REG_7 = 9 , MIPS_REG_8 = 10 , MIPS_REG_9 = 11 , MIPS_REG_10 = 12 , MIPS_REG_11 = 13 , MIPS_REG_12 = 14 , MIPS_REG_13 = 15 , MIPS_REG_14 = 16 , MIPS_REG_15 = 17 , MIPS_REG_16 = 18 , MIPS_REG_17 = 19 , MIPS_REG_18 = 20 , MIPS_REG_19 = 21 , MIPS_REG_20 = 22 , MIPS_REG_21 = 23 , MIPS_REG_22 = 24 , MIPS_REG_23 = 25 , MIPS_REG_24 = 26 , MIPS_REG_25 = 27 , MIPS_REG_26 = 28 , MIPS_REG_27 = 29 , MIPS_REG_28 = 30 , MIPS_REG_29 = 31 , MIPS_REG_30 = 32 , MIPS_REG_31 = 33 , MIPS_REG_DSPCCOND = 34 , MIPS_REG_DSPCARRY = 35 , MIPS_REG_DSPEFI = 36 , MIPS_REG_DSPOUTFLAG = 37 , MIPS_REG_DSPOUTFLAG16_19 = 38 , MIPS_REG_DSPOUTFLAG20 = 39 , MIPS_REG_DSPOUTFLAG21 = 40 , MIPS_REG_DSPOUTFLAG22 = 41 , MIPS_REG_DSPOUTFLAG23 = 42 , MIPS_REG_DSPPOS = 43 , MIPS_REG_DSPSCOUNT = 44 , MIPS_REG_AC0 = 45 , MIPS_REG_AC1 = 46 , MIPS_REG_AC2 = 47 , MIPS_REG_AC3 = 48 , MIPS_REG_CC0 = 49 , MIPS_REG_CC1 = 50 , MIPS_REG_CC2 = 51 , MIPS_REG_CC3 = 52 , MIPS_REG_CC4 = 53 , MIPS_REG_CC5 = 54 , MIPS_REG_CC6 = 55 , MIPS_REG_CC7 = 56 , MIPS_REG_F0 = 57 , MIPS_REG_F1 = 58 , MIPS_REG_F2 = 59 , MIPS_REG_F3 = 60 , MIPS_REG_F4 = 61 , MIPS_REG_F5 = 62 , MIPS_REG_F6 = 63 , MIPS_REG_F7 = 64 , MIPS_REG_F8 = 65 , MIPS_REG_F9 = 66 , MIPS_REG_F10 = 67 , MIPS_REG_F11 = 68 , MIPS_REG_F12 = 69 , MIPS_REG_F13 = 70 , MIPS_REG_F14 = 71 , MIPS_REG_F15 = 72 , MIPS_REG_F16 = 73 , MIPS_REG_F17 = 74 , MIPS_REG_F18 = 75 , MIPS_REG_F19 = 76 , MIPS_REG_F20 = 77 , MIPS_REG_F21 = 78 , MIPS_REG_F22 = 79 , MIPS_REG_F23 = 80 , MIPS_REG_F24 = 81 , MIPS_REG_F25 = 82 , MIPS_REG_F26 = 83 , MIPS_REG_F27 = 84 , MIPS_REG_F28 = 85 , MIPS_REG_F29 = 86 , MIPS_REG_F30 = 87 , MIPS_REG_F31 = 88 , MIPS_REG_FCC0 = 89 , MIPS_REG_FCC1 = 90 , MIPS_REG_FCC2 = 91 , MIPS_REG_FCC3 = 92 , MIPS_REG_FCC4 = 93 , MIPS_REG_FCC5 = 94 , MIPS_REG_FCC6 = 95 , MIPS_REG_FCC7 = 96 , MIPS_REG_W0 = 97 , MIPS_REG_W1 = 98 , MIPS_REG_W2 = 99 , MIPS_REG_W3 = 100 , MIPS_REG_W4 = 101 , MIPS_REG_W5 = 102 , MIPS_REG_W6 = 103 , MIPS_REG_W7 = 104 , MIPS_REG_W8 = 105 , MIPS_REG_W9 = 106 , MIPS_REG_W10 = 107 , MIPS_REG_W11 = 108 , MIPS_REG_W12 = 109 , MIPS_REG_W13 = 110 , MIPS_REG_W14 = 111 , MIPS_REG_W15 = 112 , MIPS_REG_W16 = 113 , MIPS_REG_W17 = 114 , MIPS_REG_W18 = 115 , MIPS_REG_W19 = 116 , MIPS_REG_W20 = 117 , MIPS_REG_W21 = 118 , MIPS_REG_W22 = 119 , MIPS_REG_W23 = 120 , MIPS_REG_W24 = 121 , MIPS_REG_W25 = 122 , MIPS_REG_W26 = 123 , MIPS_REG_W27 = 124 , MIPS_REG_W28 = 125 , MIPS_REG_W29 = 126 , MIPS_REG_W30 = 127 , MIPS_REG_W31 = 128 , MIPS_REG_HI = 129 , MIPS_REG_LO = 130 , MIPS_REG_P0 = 131 , MIPS_REG_P1 = 132 , MIPS_REG_P2 = 133 , MIPS_REG_MPL0 = 134 , MIPS_REG_MPL1 = 135 , MIPS_REG_MPL2 = 136 , MIPS_REG_ENDING = 137 , } # [doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct mips_op_mem { # [doc = "< base register"] pub base : mips_reg , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of mips_op_mem"] [:: std :: mem :: size_of :: < mips_op_mem > () - 16usize] ; ["Alignment of mips_op_mem"] [:: std :: mem :: align_of :: < mips_op_mem > () - 8usize] ; ["Offset of field: mips_op_mem::base"] [:: std :: mem :: offset_of ! (mips_op_mem , base) - 0usize] ; ["Offset of field: mips_op_mem::disp"] [:: std :: mem :: offset_of ! (mips_op_mem , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips_op { # [doc = "< operand type"] pub type_ : mips_op_type , pub __bindgen_anon_1 : cs_mips_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mips_op__bindgen_ty_1 { # [doc = "< register id for REG operand"] pub reg : mips_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : mips_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mips_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mips_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op"] [:: std :: mem :: size_of :: < cs_mips_op > () - 24usize] ; ["Alignment of cs_mips_op"] [:: std :: mem :: align_of :: < cs_mips_op > () - 8usize] ; ["Offset of field: cs_mips_op::type_"] [:: std :: mem :: offset_of ! (cs_mips_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mips_op ; 10usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips"] [:: std :: mem :: size_of :: < cs_mips > () - 248usize] ; ["Alignment of cs_mips"] [:: std :: mem :: align_of :: < cs_mips > () - 8usize] ; ["Offset of field: cs_mips::op_count"] [:: std :: mem :: offset_of ! (cs_mips , op_count) - 0usize] ; ["Offset of field: cs_mips::operands"] [:: std :: mem :: offset_of ! (cs_mips , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mips { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " MIPS instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn { MIPS_INS_INVALID = 0 , MIPS_INS_ABSQ_S = 1 , MIPS_INS_ADD = 2 , MIPS_INS_ADDIUPC = 3 , MIPS_INS_ADDIUR1SP = 4 , MIPS_INS_ADDIUR2 = 5 , MIPS_INS_ADDIUS5 = 6 , MIPS_INS_ADDIUSP = 7 , MIPS_INS_ADDQH = 8 , MIPS_INS_ADDQH_R = 9 , MIPS_INS_ADDQ = 10 , MIPS_INS_ADDQ_S = 11 , MIPS_INS_ADDSC = 12 , MIPS_INS_ADDS_A = 13 , MIPS_INS_ADDS_S = 14 , MIPS_INS_ADDS_U = 15 , MIPS_INS_ADDU16 = 16 , MIPS_INS_ADDUH = 17 , MIPS_INS_ADDUH_R = 18 , MIPS_INS_ADDU = 19 , MIPS_INS_ADDU_S = 20 , MIPS_INS_ADDVI = 21 , MIPS_INS_ADDV = 22 , MIPS_INS_ADDWC = 23 , MIPS_INS_ADD_A = 24 , MIPS_INS_ADDI = 25 , MIPS_INS_ADDIU = 26 , MIPS_INS_ALIGN = 27 , MIPS_INS_ALUIPC = 28 , MIPS_INS_AND = 29 , MIPS_INS_AND16 = 30 , MIPS_INS_ANDI16 = 31 , MIPS_INS_ANDI = 32 , MIPS_INS_APPEND = 33 , MIPS_INS_ASUB_S = 34 , MIPS_INS_ASUB_U = 35 , MIPS_INS_AUI = 36 , MIPS_INS_AUIPC = 37 , MIPS_INS_AVER_S = 38 , MIPS_INS_AVER_U = 39 , MIPS_INS_AVE_S = 40 , MIPS_INS_AVE_U = 41 , MIPS_INS_B16 = 42 , MIPS_INS_BADDU = 43 , MIPS_INS_BAL = 44 , MIPS_INS_BALC = 45 , MIPS_INS_BALIGN = 46 , MIPS_INS_BBIT0 = 47 , MIPS_INS_BBIT032 = 48 , MIPS_INS_BBIT1 = 49 , MIPS_INS_BBIT132 = 50 , MIPS_INS_BC = 51 , MIPS_INS_BC0F = 52 , MIPS_INS_BC0FL = 53 , MIPS_INS_BC0T = 54 , MIPS_INS_BC0TL = 55 , MIPS_INS_BC1EQZ = 56 , MIPS_INS_BC1F = 57 , MIPS_INS_BC1FL = 58 , MIPS_INS_BC1NEZ = 59 , MIPS_INS_BC1T = 60 , MIPS_INS_BC1TL = 61 , MIPS_INS_BC2EQZ = 62 , MIPS_INS_BC2F = 63 , MIPS_INS_BC2FL = 64 , MIPS_INS_BC2NEZ = 65 , MIPS_INS_BC2T = 66 , MIPS_INS_BC2TL = 67 , MIPS_INS_BC3F = 68 , MIPS_INS_BC3FL = 69 , MIPS_INS_BC3T = 70 , MIPS_INS_BC3TL = 71 , MIPS_INS_BCLRI = 72 , MIPS_INS_BCLR = 73 , MIPS_INS_BEQ = 74 , MIPS_INS_BEQC = 75 , MIPS_INS_BEQL = 76 , MIPS_INS_BEQZ16 = 77 , MIPS_INS_BEQZALC = 78 , MIPS_INS_BEQZC = 79 , MIPS_INS_BGEC = 80 , MIPS_INS_BGEUC = 81 , MIPS_INS_BGEZ = 82 , MIPS_INS_BGEZAL = 83 , MIPS_INS_BGEZALC = 84 , MIPS_INS_BGEZALL = 85 , MIPS_INS_BGEZALS = 86 , MIPS_INS_BGEZC = 87 , MIPS_INS_BGEZL = 88 , MIPS_INS_BGTZ = 89 , MIPS_INS_BGTZALC = 90 , MIPS_INS_BGTZC = 91 , MIPS_INS_BGTZL = 92 , MIPS_INS_BINSLI = 93 , MIPS_INS_BINSL = 94 , MIPS_INS_BINSRI = 95 , MIPS_INS_BINSR = 96 , MIPS_INS_BITREV = 97 , MIPS_INS_BITSWAP = 98 , MIPS_INS_BLEZ = 99 , MIPS_INS_BLEZALC = 100 , MIPS_INS_BLEZC = 101 , MIPS_INS_BLEZL = 102 , MIPS_INS_BLTC = 103 , MIPS_INS_BLTUC = 104 , MIPS_INS_BLTZ = 105 , MIPS_INS_BLTZAL = 106 , MIPS_INS_BLTZALC = 107 , MIPS_INS_BLTZALL = 108 , MIPS_INS_BLTZALS = 109 , MIPS_INS_BLTZC = 110 , MIPS_INS_BLTZL = 111 , MIPS_INS_BMNZI = 112 , MIPS_INS_BMNZ = 113 , MIPS_INS_BMZI = 114 , MIPS_INS_BMZ = 115 , MIPS_INS_BNE = 116 , MIPS_INS_BNEC = 117 , MIPS_INS_BNEGI = 118 , MIPS_INS_BNEG = 119 , MIPS_INS_BNEL = 120 , MIPS_INS_BNEZ16 = 121 , MIPS_INS_BNEZALC = 122 , MIPS_INS_BNEZC = 123 , MIPS_INS_BNVC = 124 , MIPS_INS_BNZ = 125 , MIPS_INS_BOVC = 126 , MIPS_INS_BPOSGE32 = 127 , MIPS_INS_BREAK = 128 , MIPS_INS_BREAK16 = 129 , MIPS_INS_BSELI = 130 , MIPS_INS_BSEL = 131 , MIPS_INS_BSETI = 132 , MIPS_INS_BSET = 133 , MIPS_INS_BZ = 134 , MIPS_INS_BEQZ = 135 , MIPS_INS_B = 136 , MIPS_INS_BNEZ = 137 , MIPS_INS_BTEQZ = 138 , MIPS_INS_BTNEZ = 139 , MIPS_INS_CACHE = 140 , MIPS_INS_CEIL = 141 , MIPS_INS_CEQI = 142 , MIPS_INS_CEQ = 143 , MIPS_INS_CFC1 = 144 , MIPS_INS_CFCMSA = 145 , MIPS_INS_CINS = 146 , MIPS_INS_CINS32 = 147 , MIPS_INS_CLASS = 148 , MIPS_INS_CLEI_S = 149 , MIPS_INS_CLEI_U = 150 , MIPS_INS_CLE_S = 151 , MIPS_INS_CLE_U = 152 , MIPS_INS_CLO = 153 , MIPS_INS_CLTI_S = 154 , MIPS_INS_CLTI_U = 155 , MIPS_INS_CLT_S = 156 , MIPS_INS_CLT_U = 157 , MIPS_INS_CLZ = 158 , MIPS_INS_CMPGDU = 159 , MIPS_INS_CMPGU = 160 , MIPS_INS_CMPU = 161 , MIPS_INS_CMP = 162 , MIPS_INS_COPY_S = 163 , MIPS_INS_COPY_U = 164 , MIPS_INS_CTC1 = 165 , MIPS_INS_CTCMSA = 166 , MIPS_INS_CVT = 167 , MIPS_INS_C = 168 , MIPS_INS_CMPI = 169 , MIPS_INS_DADD = 170 , MIPS_INS_DADDI = 171 , MIPS_INS_DADDIU = 172 , MIPS_INS_DADDU = 173 , MIPS_INS_DAHI = 174 , MIPS_INS_DALIGN = 175 , MIPS_INS_DATI = 176 , MIPS_INS_DAUI = 177 , MIPS_INS_DBITSWAP = 178 , MIPS_INS_DCLO = 179 , MIPS_INS_DCLZ = 180 , MIPS_INS_DDIV = 181 , MIPS_INS_DDIVU = 182 , MIPS_INS_DERET = 183 , MIPS_INS_DEXT = 184 , MIPS_INS_DEXTM = 185 , MIPS_INS_DEXTU = 186 , MIPS_INS_DI = 187 , MIPS_INS_DINS = 188 , MIPS_INS_DINSM = 189 , MIPS_INS_DINSU = 190 , MIPS_INS_DIV = 191 , MIPS_INS_DIVU = 192 , MIPS_INS_DIV_S = 193 , MIPS_INS_DIV_U = 194 , MIPS_INS_DLSA = 195 , MIPS_INS_DMFC0 = 196 , MIPS_INS_DMFC1 = 197 , MIPS_INS_DMFC2 = 198 , MIPS_INS_DMOD = 199 , MIPS_INS_DMODU = 200 , MIPS_INS_DMTC0 = 201 , MIPS_INS_DMTC1 = 202 , MIPS_INS_DMTC2 = 203 , MIPS_INS_DMUH = 204 , MIPS_INS_DMUHU = 205 , MIPS_INS_DMUL = 206 , MIPS_INS_DMULT = 207 , MIPS_INS_DMULTU = 208 , MIPS_INS_DMULU = 209 , MIPS_INS_DOTP_S = 210 , MIPS_INS_DOTP_U = 211 , MIPS_INS_DPADD_S = 212 , MIPS_INS_DPADD_U = 213 , MIPS_INS_DPAQX_SA = 214 , MIPS_INS_DPAQX_S = 215 , MIPS_INS_DPAQ_SA = 216 , MIPS_INS_DPAQ_S = 217 , MIPS_INS_DPAU = 218 , MIPS_INS_DPAX = 219 , MIPS_INS_DPA = 220 , MIPS_INS_DPOP = 221 , MIPS_INS_DPSQX_SA = 222 , MIPS_INS_DPSQX_S = 223 , MIPS_INS_DPSQ_SA = 224 , MIPS_INS_DPSQ_S = 225 , MIPS_INS_DPSUB_S = 226 , MIPS_INS_DPSUB_U = 227 , MIPS_INS_DPSU = 228 , MIPS_INS_DPSX = 229 , MIPS_INS_DPS = 230 , MIPS_INS_DROTR = 231 , MIPS_INS_DROTR32 = 232 , MIPS_INS_DROTRV = 233 , MIPS_INS_DSBH = 234 , MIPS_INS_DSHD = 235 , MIPS_INS_DSLL = 236 , MIPS_INS_DSLL32 = 237 , MIPS_INS_DSLLV = 238 , MIPS_INS_DSRA = 239 , MIPS_INS_DSRA32 = 240 , MIPS_INS_DSRAV = 241 , MIPS_INS_DSRL = 242 , MIPS_INS_DSRL32 = 243 , MIPS_INS_DSRLV = 244 , MIPS_INS_DSUB = 245 , MIPS_INS_DSUBU = 246 , MIPS_INS_EHB = 247 , MIPS_INS_EI = 248 , MIPS_INS_ERET = 249 , MIPS_INS_EXT = 250 , MIPS_INS_EXTP = 251 , MIPS_INS_EXTPDP = 252 , MIPS_INS_EXTPDPV = 253 , MIPS_INS_EXTPV = 254 , MIPS_INS_EXTRV_RS = 255 , MIPS_INS_EXTRV_R = 256 , MIPS_INS_EXTRV_S = 257 , MIPS_INS_EXTRV = 258 , MIPS_INS_EXTR_RS = 259 , MIPS_INS_EXTR_R = 260 , MIPS_INS_EXTR_S = 261 , MIPS_INS_EXTR = 262 , MIPS_INS_EXTS = 263 , MIPS_INS_EXTS32 = 264 , MIPS_INS_ABS = 265 , MIPS_INS_FADD = 266 , MIPS_INS_FCAF = 267 , MIPS_INS_FCEQ = 268 , MIPS_INS_FCLASS = 269 , MIPS_INS_FCLE = 270 , MIPS_INS_FCLT = 271 , MIPS_INS_FCNE = 272 , MIPS_INS_FCOR = 273 , MIPS_INS_FCUEQ = 274 , MIPS_INS_FCULE = 275 , MIPS_INS_FCULT = 276 , MIPS_INS_FCUNE = 277 , MIPS_INS_FCUN = 278 , MIPS_INS_FDIV = 279 , MIPS_INS_FEXDO = 280 , MIPS_INS_FEXP2 = 281 , MIPS_INS_FEXUPL = 282 , MIPS_INS_FEXUPR = 283 , MIPS_INS_FFINT_S = 284 , MIPS_INS_FFINT_U = 285 , MIPS_INS_FFQL = 286 , MIPS_INS_FFQR = 287 , MIPS_INS_FILL = 288 , MIPS_INS_FLOG2 = 289 , MIPS_INS_FLOOR = 290 , MIPS_INS_FMADD = 291 , MIPS_INS_FMAX_A = 292 , MIPS_INS_FMAX = 293 , MIPS_INS_FMIN_A = 294 , MIPS_INS_FMIN = 295 , MIPS_INS_MOV = 296 , MIPS_INS_FMSUB = 297 , MIPS_INS_FMUL = 298 , MIPS_INS_MUL = 299 , MIPS_INS_NEG = 300 , MIPS_INS_FRCP = 301 , MIPS_INS_FRINT = 302 , MIPS_INS_FRSQRT = 303 , MIPS_INS_FSAF = 304 , MIPS_INS_FSEQ = 305 , MIPS_INS_FSLE = 306 , MIPS_INS_FSLT = 307 , MIPS_INS_FSNE = 308 , MIPS_INS_FSOR = 309 , MIPS_INS_FSQRT = 310 , MIPS_INS_SQRT = 311 , MIPS_INS_FSUB = 312 , MIPS_INS_SUB = 313 , MIPS_INS_FSUEQ = 314 , MIPS_INS_FSULE = 315 , MIPS_INS_FSULT = 316 , MIPS_INS_FSUNE = 317 , MIPS_INS_FSUN = 318 , MIPS_INS_FTINT_S = 319 , MIPS_INS_FTINT_U = 320 , MIPS_INS_FTQ = 321 , MIPS_INS_FTRUNC_S = 322 , MIPS_INS_FTRUNC_U = 323 , MIPS_INS_HADD_S = 324 , MIPS_INS_HADD_U = 325 , MIPS_INS_HSUB_S = 326 , MIPS_INS_HSUB_U = 327 , MIPS_INS_ILVEV = 328 , MIPS_INS_ILVL = 329 , MIPS_INS_ILVOD = 330 , MIPS_INS_ILVR = 331 , MIPS_INS_INS = 332 , MIPS_INS_INSERT = 333 , MIPS_INS_INSV = 334 , MIPS_INS_INSVE = 335 , MIPS_INS_J = 336 , MIPS_INS_JAL = 337 , MIPS_INS_JALR = 338 , MIPS_INS_JALRS16 = 339 , MIPS_INS_JALRS = 340 , MIPS_INS_JALS = 341 , MIPS_INS_JALX = 342 , MIPS_INS_JIALC = 343 , MIPS_INS_JIC = 344 , MIPS_INS_JR = 345 , MIPS_INS_JR16 = 346 , MIPS_INS_JRADDIUSP = 347 , MIPS_INS_JRC = 348 , MIPS_INS_JALRC = 349 , MIPS_INS_LB = 350 , MIPS_INS_LBU16 = 351 , MIPS_INS_LBUX = 352 , MIPS_INS_LBU = 353 , MIPS_INS_LD = 354 , MIPS_INS_LDC1 = 355 , MIPS_INS_LDC2 = 356 , MIPS_INS_LDC3 = 357 , MIPS_INS_LDI = 358 , MIPS_INS_LDL = 359 , MIPS_INS_LDPC = 360 , MIPS_INS_LDR = 361 , MIPS_INS_LDXC1 = 362 , MIPS_INS_LH = 363 , MIPS_INS_LHU16 = 364 , MIPS_INS_LHX = 365 , MIPS_INS_LHU = 366 , MIPS_INS_LI16 = 367 , MIPS_INS_LL = 368 , MIPS_INS_LLD = 369 , MIPS_INS_LSA = 370 , MIPS_INS_LUXC1 = 371 , MIPS_INS_LUI = 372 , MIPS_INS_LW = 373 , MIPS_INS_LW16 = 374 , MIPS_INS_LWC1 = 375 , MIPS_INS_LWC2 = 376 , MIPS_INS_LWC3 = 377 , MIPS_INS_LWL = 378 , MIPS_INS_LWM16 = 379 , MIPS_INS_LWM32 = 380 , MIPS_INS_LWPC = 381 , MIPS_INS_LWP = 382 , MIPS_INS_LWR = 383 , MIPS_INS_LWUPC = 384 , MIPS_INS_LWU = 385 , MIPS_INS_LWX = 386 , MIPS_INS_LWXC1 = 387 , MIPS_INS_LWXS = 388 , MIPS_INS_LI = 389 , MIPS_INS_MADD = 390 , MIPS_INS_MADDF = 391 , MIPS_INS_MADDR_Q = 392 , MIPS_INS_MADDU = 393 , MIPS_INS_MADDV = 394 , MIPS_INS_MADD_Q = 395 , MIPS_INS_MAQ_SA = 396 , MIPS_INS_MAQ_S = 397 , MIPS_INS_MAXA = 398 , MIPS_INS_MAXI_S = 399 , MIPS_INS_MAXI_U = 400 , MIPS_INS_MAX_A = 401 , MIPS_INS_MAX = 402 , MIPS_INS_MAX_S = 403 , MIPS_INS_MAX_U = 404 , MIPS_INS_MFC0 = 405 , MIPS_INS_MFC1 = 406 , MIPS_INS_MFC2 = 407 , MIPS_INS_MFHC1 = 408 , MIPS_INS_MFHI = 409 , MIPS_INS_MFLO = 410 , MIPS_INS_MINA = 411 , MIPS_INS_MINI_S = 412 , MIPS_INS_MINI_U = 413 , MIPS_INS_MIN_A = 414 , MIPS_INS_MIN = 415 , MIPS_INS_MIN_S = 416 , MIPS_INS_MIN_U = 417 , MIPS_INS_MOD = 418 , MIPS_INS_MODSUB = 419 , MIPS_INS_MODU = 420 , MIPS_INS_MOD_S = 421 , MIPS_INS_MOD_U = 422 , MIPS_INS_MOVE = 423 , MIPS_INS_MOVEP = 424 , MIPS_INS_MOVF = 425 , MIPS_INS_MOVN = 426 , MIPS_INS_MOVT = 427 , MIPS_INS_MOVZ = 428 , MIPS_INS_MSUB = 429 , MIPS_INS_MSUBF = 430 , MIPS_INS_MSUBR_Q = 431 , MIPS_INS_MSUBU = 432 , MIPS_INS_MSUBV = 433 , MIPS_INS_MSUB_Q = 434 , MIPS_INS_MTC0 = 435 , MIPS_INS_MTC1 = 436 , MIPS_INS_MTC2 = 437 , MIPS_INS_MTHC1 = 438 , MIPS_INS_MTHI = 439 , MIPS_INS_MTHLIP = 440 , MIPS_INS_MTLO = 441 , MIPS_INS_MTM0 = 442 , MIPS_INS_MTM1 = 443 , MIPS_INS_MTM2 = 444 , MIPS_INS_MTP0 = 445 , MIPS_INS_MTP1 = 446 , MIPS_INS_MTP2 = 447 , MIPS_INS_MUH = 448 , MIPS_INS_MUHU = 449 , MIPS_INS_MULEQ_S = 450 , MIPS_INS_MULEU_S = 451 , MIPS_INS_MULQ_RS = 452 , MIPS_INS_MULQ_S = 453 , MIPS_INS_MULR_Q = 454 , MIPS_INS_MULSAQ_S = 455 , MIPS_INS_MULSA = 456 , MIPS_INS_MULT = 457 , MIPS_INS_MULTU = 458 , MIPS_INS_MULU = 459 , MIPS_INS_MULV = 460 , MIPS_INS_MUL_Q = 461 , MIPS_INS_MUL_S = 462 , MIPS_INS_NLOC = 463 , MIPS_INS_NLZC = 464 , MIPS_INS_NMADD = 465 , MIPS_INS_NMSUB = 466 , MIPS_INS_NOR = 467 , MIPS_INS_NORI = 468 , MIPS_INS_NOT16 = 469 , MIPS_INS_NOT = 470 , MIPS_INS_OR = 471 , MIPS_INS_OR16 = 472 , MIPS_INS_ORI = 473 , MIPS_INS_PACKRL = 474 , MIPS_INS_PAUSE = 475 , MIPS_INS_PCKEV = 476 , MIPS_INS_PCKOD = 477 , MIPS_INS_PCNT = 478 , MIPS_INS_PICK = 479 , MIPS_INS_POP = 480 , MIPS_INS_PRECEQU = 481 , MIPS_INS_PRECEQ = 482 , MIPS_INS_PRECEU = 483 , MIPS_INS_PRECRQU_S = 484 , MIPS_INS_PRECRQ = 485 , MIPS_INS_PRECRQ_RS = 486 , MIPS_INS_PRECR = 487 , MIPS_INS_PRECR_SRA = 488 , MIPS_INS_PRECR_SRA_R = 489 , MIPS_INS_PREF = 490 , MIPS_INS_PREPEND = 491 , MIPS_INS_RADDU = 492 , MIPS_INS_RDDSP = 493 , MIPS_INS_RDHWR = 494 , MIPS_INS_REPLV = 495 , MIPS_INS_REPL = 496 , MIPS_INS_RINT = 497 , MIPS_INS_ROTR = 498 , MIPS_INS_ROTRV = 499 , MIPS_INS_ROUND = 500 , MIPS_INS_SAT_S = 501 , MIPS_INS_SAT_U = 502 , MIPS_INS_SB = 503 , MIPS_INS_SB16 = 504 , MIPS_INS_SC = 505 , MIPS_INS_SCD = 506 , MIPS_INS_SD = 507 , MIPS_INS_SDBBP = 508 , MIPS_INS_SDBBP16 = 509 , MIPS_INS_SDC1 = 510 , MIPS_INS_SDC2 = 511 , MIPS_INS_SDC3 = 512 , MIPS_INS_SDL = 513 , MIPS_INS_SDR = 514 , MIPS_INS_SDXC1 = 515 , MIPS_INS_SEB = 516 , MIPS_INS_SEH = 517 , MIPS_INS_SELEQZ = 518 , MIPS_INS_SELNEZ = 519 , MIPS_INS_SEL = 520 , MIPS_INS_SEQ = 521 , MIPS_INS_SEQI = 522 , MIPS_INS_SH = 523 , MIPS_INS_SH16 = 524 , MIPS_INS_SHF = 525 , MIPS_INS_SHILO = 526 , MIPS_INS_SHILOV = 527 , MIPS_INS_SHLLV = 528 , MIPS_INS_SHLLV_S = 529 , MIPS_INS_SHLL = 530 , MIPS_INS_SHLL_S = 531 , MIPS_INS_SHRAV = 532 , MIPS_INS_SHRAV_R = 533 , MIPS_INS_SHRA = 534 , MIPS_INS_SHRA_R = 535 , MIPS_INS_SHRLV = 536 , MIPS_INS_SHRL = 537 , MIPS_INS_SLDI = 538 , MIPS_INS_SLD = 539 , MIPS_INS_SLL = 540 , MIPS_INS_SLL16 = 541 , MIPS_INS_SLLI = 542 , MIPS_INS_SLLV = 543 , MIPS_INS_SLT = 544 , MIPS_INS_SLTI = 545 , MIPS_INS_SLTIU = 546 , MIPS_INS_SLTU = 547 , MIPS_INS_SNE = 548 , MIPS_INS_SNEI = 549 , MIPS_INS_SPLATI = 550 , MIPS_INS_SPLAT = 551 , MIPS_INS_SRA = 552 , MIPS_INS_SRAI = 553 , MIPS_INS_SRARI = 554 , MIPS_INS_SRAR = 555 , MIPS_INS_SRAV = 556 , MIPS_INS_SRL = 557 , MIPS_INS_SRL16 = 558 , MIPS_INS_SRLI = 559 , MIPS_INS_SRLRI = 560 , MIPS_INS_SRLR = 561 , MIPS_INS_SRLV = 562 , MIPS_INS_SSNOP = 563 , MIPS_INS_ST = 564 , MIPS_INS_SUBQH = 565 , MIPS_INS_SUBQH_R = 566 , MIPS_INS_SUBQ = 567 , MIPS_INS_SUBQ_S = 568 , MIPS_INS_SUBSUS_U = 569 , MIPS_INS_SUBSUU_S = 570 , MIPS_INS_SUBS_S = 571 , MIPS_INS_SUBS_U = 572 , MIPS_INS_SUBU16 = 573 , MIPS_INS_SUBUH = 574 , MIPS_INS_SUBUH_R = 575 , MIPS_INS_SUBU = 576 , MIPS_INS_SUBU_S = 577 , MIPS_INS_SUBVI = 578 , MIPS_INS_SUBV = 579 , MIPS_INS_SUXC1 = 580 , MIPS_INS_SW = 581 , MIPS_INS_SW16 = 582 , MIPS_INS_SWC1 = 583 , MIPS_INS_SWC2 = 584 , MIPS_INS_SWC3 = 585 , MIPS_INS_SWL = 586 , MIPS_INS_SWM16 = 587 , MIPS_INS_SWM32 = 588 , MIPS_INS_SWP = 589 , MIPS_INS_SWR = 590 , MIPS_INS_SWXC1 = 591 , MIPS_INS_SYNC = 592 , MIPS_INS_SYNCI = 593 , MIPS_INS_SYSCALL = 594 , MIPS_INS_TEQ = 595 , MIPS_INS_TEQI = 596 , MIPS_INS_TGE = 597 , MIPS_INS_TGEI = 598 , MIPS_INS_TGEIU = 599 , MIPS_INS_TGEU = 600 , MIPS_INS_TLBP = 601 , MIPS_INS_TLBR = 602 , MIPS_INS_TLBWI = 603 , MIPS_INS_TLBWR = 604 , MIPS_INS_TLT = 605 , MIPS_INS_TLTI = 606 , MIPS_INS_TLTIU = 607 , MIPS_INS_TLTU = 608 , MIPS_INS_TNE = 609 , MIPS_INS_TNEI = 610 , MIPS_INS_TRUNC = 611 , MIPS_INS_V3MULU = 612 , MIPS_INS_VMM0 = 613 , MIPS_INS_VMULU = 614 , MIPS_INS_VSHF = 615 , MIPS_INS_WAIT = 616 , MIPS_INS_WRDSP = 617 , MIPS_INS_WSBH = 618 , MIPS_INS_XOR = 619 , MIPS_INS_XOR16 = 620 , MIPS_INS_XORI = 621 , MIPS_INS_NOP = 622 , MIPS_INS_NEGU = 623 , MIPS_INS_JALR_HB = 624 , MIPS_INS_JR_HB = 625 , MIPS_INS_ENDING = 626 , } # [repr (u32)] # [doc = " Group of MIPS instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn_group { # [doc = "< = CS_GRP_INVALID"] MIPS_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MIPS_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] MIPS_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MIPS_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MIPS_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MIPS_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] MIPS_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MIPS_GRP_BRANCH_RELATIVE = 7 , MIPS_GRP_BITCOUNT = 128 , MIPS_GRP_DSP = 129 , MIPS_GRP_DSPR2 = 130 , MIPS_GRP_FPIDX = 131 , MIPS_GRP_MSA = 132 , MIPS_GRP_MIPS32R2 = 133 , MIPS_GRP_MIPS64 = 134 , MIPS_GRP_MIPS64R2 = 135 , MIPS_GRP_SEINREG = 136 , MIPS_GRP_STDENC = 137 , MIPS_GRP_SWAP = 138 , MIPS_GRP_MICROMIPS = 139 , MIPS_GRP_MIPS16MODE = 140 , MIPS_GRP_FP64BIT = 141 , MIPS_GRP_NONANSFPMATH = 142 , MIPS_GRP_NOTFP64BIT = 143 , MIPS_GRP_NOTINMICROMIPS = 144 , MIPS_GRP_NOTNACL = 145 , MIPS_GRP_NOTMIPS32R6 = 146 , MIPS_GRP_NOTMIPS64R6 = 147 , MIPS_GRP_CNMIPS = 148 , MIPS_GRP_MIPS32 = 149 , MIPS_GRP_MIPS32R6 = 150 , MIPS_GRP_MIPS64R6 = 151 , MIPS_GRP_MIPS2 = 152 , MIPS_GRP_MIPS3 = 153 , MIPS_GRP_MIPS3_32 = 154 , MIPS_GRP_MIPS3_32R2 = 155 , MIPS_GRP_MIPS4_32 = 156 , MIPS_GRP_MIPS4_32R2 = 157 , MIPS_GRP_MIPS5_32R2 = 158 , MIPS_GRP_GP32BIT = 159 , MIPS_GRP_GP64BIT = 160 , MIPS_GRP_ENDING = 161 , } # [repr (u32)] # [doc = " PPC branch codes for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bc { PPC_BC_INVALID = 0 , PPC_BC_LT = 12 , PPC_BC_LE = 36 , PPC_BC_EQ = 76 , PPC_BC_GE = 4 , PPC_BC_GT = 44 , PPC_BC_NE = 68 , PPC_BC_UN = 108 , PPC_BC_NU = 100 , # [doc = "< summary overflow"] PPC_BC_SO = 140 , # [doc = "< not summary overflow"] PPC_BC_NS = 132 , } # [repr (u32)] # [doc = " PPC branch hint for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bh { # [doc = "< no hint"] PPC_BH_INVALID = 0 , # [doc = "< PLUS hint"] PPC_BH_PLUS = 1 , # [doc = "< MINUS hint"] PPC_BH_MINUS = 2 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] PPC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] PPC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] PPC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] PPC_OP_MEM = 3 , # [doc = "< Condition Register field"] PPC_OP_CRX = 64 , } # [repr (u32)] # [doc = " PPC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_reg { PPC_REG_INVALID = 0 , PPC_REG_CARRY = 2 , PPC_REG_CTR = 3 , PPC_REG_LR = 5 , PPC_REG_RM = 6 , PPC_REG_VRSAVE = 8 , PPC_REG_XER = 9 , PPC_REG_ZERO = 10 , PPC_REG_CR0 = 12 , PPC_REG_CR1 = 13 , PPC_REG_CR2 = 14 , PPC_REG_CR3 = 15 , PPC_REG_CR4 = 16 , PPC_REG_CR5 = 17 , PPC_REG_CR6 = 18 , PPC_REG_CR7 = 19 , PPC_REG_CTR8 = 20 , PPC_REG_F0 = 21 , PPC_REG_F1 = 22 , PPC_REG_F2 = 23 , PPC_REG_F3 = 24 , PPC_REG_F4 = 25 , PPC_REG_F5 = 26 , PPC_REG_F6 = 27 , PPC_REG_F7 = 28 , PPC_REG_F8 = 29 , PPC_REG_F9 = 30 , PPC_REG_F10 = 31 , PPC_REG_F11 = 32 , PPC_REG_F12 = 33 , PPC_REG_F13 = 34 , PPC_REG_F14 = 35 , PPC_REG_F15 = 36 , PPC_REG_F16 = 37 , PPC_REG_F17 = 38 , PPC_REG_F18 = 39 , PPC_REG_F19 = 40 , PPC_REG_F20 = 41 , PPC_REG_F21 = 42 , PPC_REG_F22 = 43 , PPC_REG_F23 = 44 , PPC_REG_F24 = 45 , PPC_REG_F25 = 46 , PPC_REG_F26 = 47 , PPC_REG_F27 = 48 , PPC_REG_F28 = 49 , PPC_REG_F29 = 50 , PPC_REG_F30 = 51 , PPC_REG_F31 = 52 , PPC_REG_LR8 = 54 , PPC_REG_Q0 = 55 , PPC_REG_Q1 = 56 , PPC_REG_Q2 = 57 , PPC_REG_Q3 = 58 , PPC_REG_Q4 = 59 , PPC_REG_Q5 = 60 , PPC_REG_Q6 = 61 , PPC_REG_Q7 = 62 , PPC_REG_Q8 = 63 , PPC_REG_Q9 = 64 , PPC_REG_Q10 = 65 , PPC_REG_Q11 = 66 , PPC_REG_Q12 = 67 , PPC_REG_Q13 = 68 , PPC_REG_Q14 = 69 , PPC_REG_Q15 = 70 , PPC_REG_Q16 = 71 , PPC_REG_Q17 = 72 , PPC_REG_Q18 = 73 , PPC_REG_Q19 = 74 , PPC_REG_Q20 = 75 , PPC_REG_Q21 = 76 , PPC_REG_Q22 = 77 , PPC_REG_Q23 = 78 , PPC_REG_Q24 = 79 , PPC_REG_Q25 = 80 , PPC_REG_Q26 = 81 , PPC_REG_Q27 = 82 , PPC_REG_Q28 = 83 , PPC_REG_Q29 = 84 , PPC_REG_Q30 = 85 , PPC_REG_Q31 = 86 , PPC_REG_R0 = 87 , PPC_REG_R1 = 88 , PPC_REG_R2 = 89 , PPC_REG_R3 = 90 , PPC_REG_R4 = 91 , PPC_REG_R5 = 92 , PPC_REG_R6 = 93 , PPC_REG_R7 = 94 , PPC_REG_R8 = 95 , PPC_REG_R9 = 96 , PPC_REG_R10 = 97 , PPC_REG_R11 = 98 , PPC_REG_R12 = 99 , PPC_REG_R13 = 100 , PPC_REG_R14 = 101 , PPC_REG_R15 = 102 , PPC_REG_R16 = 103 , PPC_REG_R17 = 104 , PPC_REG_R18 = 105 , PPC_REG_R19 = 106 , PPC_REG_R20 = 107 , PPC_REG_R21 = 108 , PPC_REG_R22 = 109 , PPC_REG_R23 = 110 , PPC_REG_R24 = 111 , PPC_REG_R25 = 112 , PPC_REG_R26 = 113 , PPC_REG_R27 = 114 , PPC_REG_R28 = 115 , PPC_REG_R29 = 116 , PPC_REG_R30 = 117 , PPC_REG_R31 = 118 , PPC_REG_V0 = 151 , PPC_REG_V1 = 152 , PPC_REG_V2 = 153 , PPC_REG_V3 = 154 , PPC_REG_V4 = 155 , PPC_REG_V5 = 156 , PPC_REG_V6 = 157 , PPC_REG_V7 = 158 , PPC_REG_V8 = 159 , PPC_REG_V9 = 160 , PPC_REG_V10 = 161 , PPC_REG_V11 = 162 , PPC_REG_V12 = 163 , PPC_REG_V13 = 164 , PPC_REG_V14 = 165 , PPC_REG_V15 = 166 , PPC_REG_V16 = 167 , PPC_REG_V17 = 168 , PPC_REG_V18 = 169 , PPC_REG_V19 = 170 , PPC_REG_V20 = 171 , PPC_REG_V21 = 172 , PPC_REG_V22 = 173 , PPC_REG_V23 = 174 , PPC_REG_V24 = 175 , PPC_REG_V25 = 176 , PPC_REG_V26 = 177 , PPC_REG_V27 = 178 , PPC_REG_V28 = 179 , PPC_REG_V29 = 180 , PPC_REG_V30 = 181 , PPC_REG_V31 = 182 , PPC_REG_VS0 = 215 , PPC_REG_VS1 = 216 , PPC_REG_VS2 = 217 , PPC_REG_VS3 = 218 , PPC_REG_VS4 = 219 , PPC_REG_VS5 = 220 , PPC_REG_VS6 = 221 , PPC_REG_VS7 = 222 , PPC_REG_VS8 = 223 , PPC_REG_VS9 = 224 , PPC_REG_VS10 = 225 , PPC_REG_VS11 = 226 , PPC_REG_VS12 = 227 , PPC_REG_VS13 = 228 , PPC_REG_VS14 = 229 , PPC_REG_VS15 = 230 , PPC_REG_VS16 = 231 , PPC_REG_VS17 = 232 , PPC_REG_VS18 = 233 , PPC_REG_VS19 = 234 , PPC_REG_VS20 = 235 , PPC_REG_VS21 = 236 , PPC_REG_VS22 = 237 , PPC_REG_VS23 = 238 , PPC_REG_VS24 = 239 , PPC_REG_VS25 = 240 , PPC_REG_VS26 = 241 , PPC_REG_VS27 = 242 , PPC_REG_VS28 = 243 , PPC_REG_VS29 = 244 , PPC_REG_VS30 = 245 , PPC_REG_VS31 = 246 , PPC_REG_VS32 = 247 , PPC_REG_VS33 = 248 , PPC_REG_VS34 = 249 , PPC_REG_VS35 = 250 , PPC_REG_VS36 = 251 , PPC_REG_VS37 = 252 , PPC_REG_VS38 = 253 , PPC_REG_VS39 = 254 , PPC_REG_VS40 = 255 , PPC_REG_VS41 = 256 , PPC_REG_VS42 = 257 , PPC_REG_VS43 = 258 , PPC_REG_VS44 = 259 , PPC_REG_VS45 = 260 , PPC_REG_VS46 = 261 , PPC_REG_VS47 = 262 , PPC_REG_VS48 = 263 , PPC_REG_VS49 = 264 , PPC_REG_VS50 = 265 , PPC_REG_VS51 = 266 , PPC_REG_VS52 = 267 , PPC_REG_VS53 = 268 , PPC_REG_VS54 = 269 , PPC_REG_VS55 = 270 , PPC_REG_VS56 = 271 , PPC_REG_VS57 = 272 , PPC_REG_VS58 = 273 , PPC_REG_VS59 = 274 , PPC_REG_VS60 = 275 , PPC_REG_VS61 = 276 , PPC_REG_VS62 = 277 , PPC_REG_VS63 = 278 , PPC_REG_CR0EQ = 312 , PPC_REG_CR1EQ = 313 , PPC_REG_CR2EQ = 314 , PPC_REG_CR3EQ = 315 , PPC_REG_CR4EQ = 316 , PPC_REG_CR5EQ = 317 , PPC_REG_CR6EQ = 318 , PPC_REG_CR7EQ = 319 , PPC_REG_CR0GT = 320 , PPC_REG_CR1GT = 321 , PPC_REG_CR2GT = 322 , PPC_REG_CR3GT = 323 , PPC_REG_CR4GT = 324 , PPC_REG_CR5GT = 325 , PPC_REG_CR6GT = 326 , PPC_REG_CR7GT = 327 , PPC_REG_CR0LT = 328 , PPC_REG_CR1LT = 329 , PPC_REG_CR2LT = 330 , PPC_REG_CR3LT = 331 , PPC_REG_CR4LT = 332 , PPC_REG_CR5LT = 333 , PPC_REG_CR6LT = 334 , PPC_REG_CR7LT = 335 , PPC_REG_CR0UN = 336 , PPC_REG_CR1UN = 337 , PPC_REG_CR2UN = 338 , PPC_REG_CR3UN = 339 , PPC_REG_CR4UN = 340 , PPC_REG_CR5UN = 341 , PPC_REG_CR6UN = 342 , PPC_REG_CR7UN = 343 , PPC_REG_ENDING = 344 , } # [doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_mem { # [doc = "< base register"] pub base : ppc_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_mem"] [:: std :: mem :: size_of :: < ppc_op_mem > () - 8usize] ; ["Alignment of ppc_op_mem"] [:: std :: mem :: align_of :: < ppc_op_mem > () - 4usize] ; ["Offset of field: ppc_op_mem::base"] [:: std :: mem :: offset_of ! (ppc_op_mem , base) - 0usize] ; ["Offset of field: ppc_op_mem::disp"] [:: std :: mem :: offset_of ! (ppc_op_mem , disp) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_crx { pub scale : :: std :: os :: raw :: c_uint , pub reg : ppc_reg , pub cond : ppc_bc , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_crx"] [:: std :: mem :: size_of :: < ppc_op_crx > () - 12usize] ; ["Alignment of ppc_op_crx"] [:: std :: mem :: align_of :: < ppc_op_crx > () - 4usize] ; ["Offset of field: ppc_op_crx::scale"] [:: std :: mem :: offset_of ! (ppc_op_crx , scale) - 0usize] ; ["Offset of field: ppc_op_crx::reg"] [:: std :: mem :: offset_of ! (ppc_op_crx , reg) - 4usize] ; ["Offset of field: ppc_op_crx::cond"] [:: std :: mem :: offset_of ! (ppc_op_crx , cond) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc_op { # [doc = "< operand type"] pub type_ : ppc_op_type , pub __bindgen_anon_1 : cs_ppc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_ppc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : ppc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : ppc_op_mem , # [doc = "< operand with condition register"] pub crx : ppc_op_crx , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_ppc_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_ppc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::crx"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , crx) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op"] [:: std :: mem :: size_of :: < cs_ppc_op > () - 24usize] ; ["Alignment of cs_ppc_op"] [:: std :: mem :: align_of :: < cs_ppc_op > () - 8usize] ; ["Offset of field: cs_ppc_op::type_"] [:: std :: mem :: offset_of ! (cs_ppc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc { # [doc = " branch code for branch instructions"] pub bc : ppc_bc , # [doc = " branch hint for branch instructions"] pub bh : ppc_bh , # [doc = " if update_cr0 = True, then this 'dot' insn updates CR0"] pub update_cr0 : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_ppc_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc"] [:: std :: mem :: size_of :: < cs_ppc > () - 208usize] ; ["Alignment of cs_ppc"] [:: std :: mem :: align_of :: < cs_ppc > () - 8usize] ; ["Offset of field: cs_ppc::bc"] [:: std :: mem :: offset_of ! (cs_ppc , bc) - 0usize] ; ["Offset of field: cs_ppc::bh"] [:: std :: mem :: offset_of ! (cs_ppc , bh) - 4usize] ; ["Offset of field: cs_ppc::update_cr0"] [:: std :: mem :: offset_of ! (cs_ppc , update_cr0) - 8usize] ; ["Offset of field: cs_ppc::op_count"] [:: std :: mem :: offset_of ! (cs_ppc , op_count) - 9usize] ; ["Offset of field: cs_ppc::operands"] [:: std :: mem :: offset_of ! (cs_ppc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}" , self . bc , self . bh , self . update_cr0 , self . op_count , self . operands) } } # [repr (u32)] # [doc = " PPC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn { PPC_INS_INVALID = 0 , PPC_INS_ADD = 1 , PPC_INS_ADDC = 2 , PPC_INS_ADDE = 3 , PPC_INS_ADDI = 4 , PPC_INS_ADDIC = 5 , PPC_INS_ADDIS = 6 , PPC_INS_ADDME = 7 , PPC_INS_ADDPCIS = 8 , PPC_INS_ADDZE = 9 , PPC_INS_AND = 10 , PPC_INS_ANDC = 11 , PPC_INS_ANDI = 12 , PPC_INS_ANDIS = 13 , PPC_INS_ATTN = 14 , PPC_INS_B = 15 , PPC_INS_BA = 16 , PPC_INS_BC = 17 , PPC_INS_BCA = 18 , PPC_INS_BCCTR = 19 , PPC_INS_BCCTRL = 20 , PPC_INS_BCDCFN = 21 , PPC_INS_BCDCFSQ = 22 , PPC_INS_BCDCFZ = 23 , PPC_INS_BCDCPSGN = 24 , PPC_INS_BCDCTN = 25 , PPC_INS_BCDCTSQ = 26 , PPC_INS_BCDCTZ = 27 , PPC_INS_BCDS = 28 , PPC_INS_BCDSETSGN = 29 , PPC_INS_BCDSR = 30 , PPC_INS_BCDTRUNC = 31 , PPC_INS_BCDUS = 32 , PPC_INS_BCDUTRUNC = 33 , PPC_INS_BCL = 34 , PPC_INS_BCLA = 35 , PPC_INS_BCLR = 36 , PPC_INS_BCLRL = 37 , PPC_INS_BCTR = 38 , PPC_INS_BCTRL = 39 , PPC_INS_BDNZ = 40 , PPC_INS_BDNZA = 41 , PPC_INS_BDNZF = 42 , PPC_INS_BDNZFA = 43 , PPC_INS_BDNZFL = 44 , PPC_INS_BDNZFLA = 45 , PPC_INS_BDNZFLR = 46 , PPC_INS_BDNZFLRL = 47 , PPC_INS_BDNZL = 48 , PPC_INS_BDNZLA = 49 , PPC_INS_BDNZLR = 50 , PPC_INS_BDNZLRL = 51 , PPC_INS_BDNZT = 52 , PPC_INS_BDNZTA = 53 , PPC_INS_BDNZTL = 54 , PPC_INS_BDNZTLA = 55 , PPC_INS_BDNZTLR = 56 , PPC_INS_BDNZTLRL = 57 , PPC_INS_BDZ = 58 , PPC_INS_BDZA = 59 , PPC_INS_BDZF = 60 , PPC_INS_BDZFA = 61 , PPC_INS_BDZFL = 62 , PPC_INS_BDZFLA = 63 , PPC_INS_BDZFLR = 64 , PPC_INS_BDZFLRL = 65 , PPC_INS_BDZL = 66 , PPC_INS_BDZLA = 67 , PPC_INS_BDZLR = 68 , PPC_INS_BDZLRL = 69 , PPC_INS_BDZT = 70 , PPC_INS_BDZTA = 71 , PPC_INS_BDZTL = 72 , PPC_INS_BDZTLA = 73 , PPC_INS_BDZTLR = 74 , PPC_INS_BDZTLRL = 75 , PPC_INS_BEQ = 76 , PPC_INS_BEQA = 77 , PPC_INS_BEQCTR = 78 , PPC_INS_BEQCTRL = 79 , PPC_INS_BEQL = 80 , PPC_INS_BEQLA = 81 , PPC_INS_BEQLR = 82 , PPC_INS_BEQLRL = 83 , PPC_INS_BF = 84 , PPC_INS_BFA = 85 , PPC_INS_BFCTR = 86 , PPC_INS_BFCTRL = 87 , PPC_INS_BFL = 88 , PPC_INS_BFLA = 89 , PPC_INS_BFLR = 90 , PPC_INS_BFLRL = 91 , PPC_INS_BGE = 92 , PPC_INS_BGEA = 93 , PPC_INS_BGECTR = 94 , PPC_INS_BGECTRL = 95 , PPC_INS_BGEL = 96 , PPC_INS_BGELA = 97 , PPC_INS_BGELR = 98 , PPC_INS_BGELRL = 99 , PPC_INS_BGT = 100 , PPC_INS_BGTA = 101 , PPC_INS_BGTCTR = 102 , PPC_INS_BGTCTRL = 103 , PPC_INS_BGTL = 104 , PPC_INS_BGTLA = 105 , PPC_INS_BGTLR = 106 , PPC_INS_BGTLRL = 107 , PPC_INS_BL = 108 , PPC_INS_BLA = 109 , PPC_INS_BLE = 110 , PPC_INS_BLEA = 111 , PPC_INS_BLECTR = 112 , PPC_INS_BLECTRL = 113 , PPC_INS_BLEL = 114 , PPC_INS_BLELA = 115 , PPC_INS_BLELR = 116 , PPC_INS_BLELRL = 117 , PPC_INS_BLR = 118 , PPC_INS_BLRL = 119 , PPC_INS_BLT = 120 , PPC_INS_BLTA = 121 , PPC_INS_BLTCTR = 122 , PPC_INS_BLTCTRL = 123 , PPC_INS_BLTL = 124 , PPC_INS_BLTLA = 125 , PPC_INS_BLTLR = 126 , PPC_INS_BLTLRL = 127 , PPC_INS_BNE = 128 , PPC_INS_BNEA = 129 , PPC_INS_BNECTR = 130 , PPC_INS_BNECTRL = 131 , PPC_INS_BNEL = 132 , PPC_INS_BNELA = 133 , PPC_INS_BNELR = 134 , PPC_INS_BNELRL = 135 , PPC_INS_BNG = 136 , PPC_INS_BNGA = 137 , PPC_INS_BNGCTR = 138 , PPC_INS_BNGCTRL = 139 , PPC_INS_BNGL = 140 , PPC_INS_BNGLA = 141 , PPC_INS_BNGLR = 142 , PPC_INS_BNGLRL = 143 , PPC_INS_BNL = 144 , PPC_INS_BNLA = 145 , PPC_INS_BNLCTR = 146 , PPC_INS_BNLCTRL = 147 , PPC_INS_BNLL = 148 , PPC_INS_BNLLA = 149 , PPC_INS_BNLLR = 150 , PPC_INS_BNLLRL = 151 , PPC_INS_BNS = 152 , PPC_INS_BNSA = 153 , PPC_INS_BNSCTR = 154 , PPC_INS_BNSCTRL = 155 , PPC_INS_BNSL = 156 , PPC_INS_BNSLA = 157 , PPC_INS_BNSLR = 158 , PPC_INS_BNSLRL = 159 , PPC_INS_BNU = 160 , PPC_INS_BNUA = 161 , PPC_INS_BNUCTR = 162 , PPC_INS_BNUCTRL = 163 , PPC_INS_BNUL = 164 , PPC_INS_BNULA = 165 , PPC_INS_BNULR = 166 , PPC_INS_BNULRL = 167 , PPC_INS_BPERMD = 168 , PPC_INS_BRINC = 169 , PPC_INS_BSO = 170 , PPC_INS_BSOA = 171 , PPC_INS_BSOCTR = 172 , PPC_INS_BSOCTRL = 173 , PPC_INS_BSOL = 174 , PPC_INS_BSOLA = 175 , PPC_INS_BSOLR = 176 , PPC_INS_BSOLRL = 177 , PPC_INS_BT = 178 , PPC_INS_BTA = 179 , PPC_INS_BTCTR = 180 , PPC_INS_BTCTRL = 181 , PPC_INS_BTL = 182 , PPC_INS_BTLA = 183 , PPC_INS_BTLR = 184 , PPC_INS_BTLRL = 185 , PPC_INS_BUN = 186 , PPC_INS_BUNA = 187 , PPC_INS_BUNCTR = 188 , PPC_INS_BUNCTRL = 189 , PPC_INS_BUNL = 190 , PPC_INS_BUNLA = 191 , PPC_INS_BUNLR = 192 , PPC_INS_BUNLRL = 193 , PPC_INS_CLRBHRB = 194 , PPC_INS_CLRLDI = 195 , PPC_INS_CLRLSLDI = 196 , PPC_INS_CLRLSLWI = 197 , PPC_INS_CLRLWI = 198 , PPC_INS_CLRRDI = 199 , PPC_INS_CLRRWI = 200 , PPC_INS_CMP = 201 , PPC_INS_CMPB = 202 , PPC_INS_CMPD = 203 , PPC_INS_CMPDI = 204 , PPC_INS_CMPEQB = 205 , PPC_INS_CMPI = 206 , PPC_INS_CMPL = 207 , PPC_INS_CMPLD = 208 , PPC_INS_CMPLDI = 209 , PPC_INS_CMPLI = 210 , PPC_INS_CMPLW = 211 , PPC_INS_CMPLWI = 212 , PPC_INS_CMPRB = 213 , PPC_INS_CMPW = 214 , PPC_INS_CMPWI = 215 , PPC_INS_CNTLZD = 216 , PPC_INS_CNTLZW = 217 , PPC_INS_CNTTZD = 218 , PPC_INS_CNTTZW = 219 , PPC_INS_COPY = 220 , PPC_INS_COPY_FIRST = 221 , PPC_INS_CP_ABORT = 222 , PPC_INS_CRAND = 223 , PPC_INS_CRANDC = 224 , PPC_INS_CRCLR = 225 , PPC_INS_CREQV = 226 , PPC_INS_CRMOVE = 227 , PPC_INS_CRNAND = 228 , PPC_INS_CRNOR = 229 , PPC_INS_CRNOT = 230 , PPC_INS_CROR = 231 , PPC_INS_CRORC = 232 , PPC_INS_CRSET = 233 , PPC_INS_CRXOR = 234 , PPC_INS_DARN = 235 , PPC_INS_DCBA = 236 , PPC_INS_DCBF = 237 , PPC_INS_DCBFEP = 238 , PPC_INS_DCBFL = 239 , PPC_INS_DCBFLP = 240 , PPC_INS_DCBI = 241 , PPC_INS_DCBST = 242 , PPC_INS_DCBSTEP = 243 , PPC_INS_DCBT = 244 , PPC_INS_DCBTCT = 245 , PPC_INS_DCBTDS = 246 , PPC_INS_DCBTEP = 247 , PPC_INS_DCBTST = 248 , PPC_INS_DCBTSTCT = 249 , PPC_INS_DCBTSTDS = 250 , PPC_INS_DCBTSTEP = 251 , PPC_INS_DCBTSTT = 252 , PPC_INS_DCBTT = 253 , PPC_INS_DCBZ = 254 , PPC_INS_DCBZEP = 255 , PPC_INS_DCBZL = 256 , PPC_INS_DCBZLEP = 257 , PPC_INS_DCCCI = 258 , PPC_INS_DCI = 259 , PPC_INS_DIVD = 260 , PPC_INS_DIVDE = 261 , PPC_INS_DIVDEU = 262 , PPC_INS_DIVDU = 263 , PPC_INS_DIVW = 264 , PPC_INS_DIVWE = 265 , PPC_INS_DIVWEU = 266 , PPC_INS_DIVWU = 267 , PPC_INS_DSS = 268 , PPC_INS_DSSALL = 269 , PPC_INS_DST = 270 , PPC_INS_DSTST = 271 , PPC_INS_DSTSTT = 272 , PPC_INS_DSTT = 273 , PPC_INS_EFDABS = 274 , PPC_INS_EFDADD = 275 , PPC_INS_EFDCFS = 276 , PPC_INS_EFDCFSF = 277 , PPC_INS_EFDCFSI = 278 , PPC_INS_EFDCFSID = 279 , PPC_INS_EFDCFUF = 280 , PPC_INS_EFDCFUI = 281 , PPC_INS_EFDCFUID = 282 , PPC_INS_EFDCMPEQ = 283 , PPC_INS_EFDCMPGT = 284 , PPC_INS_EFDCMPLT = 285 , PPC_INS_EFDCTSF = 286 , PPC_INS_EFDCTSI = 287 , PPC_INS_EFDCTSIDZ = 288 , PPC_INS_EFDCTSIZ = 289 , PPC_INS_EFDCTUF = 290 , PPC_INS_EFDCTUI = 291 , PPC_INS_EFDCTUIDZ = 292 , PPC_INS_EFDCTUIZ = 293 , PPC_INS_EFDDIV = 294 , PPC_INS_EFDMUL = 295 , PPC_INS_EFDNABS = 296 , PPC_INS_EFDNEG = 297 , PPC_INS_EFDSUB = 298 , PPC_INS_EFDTSTEQ = 299 , PPC_INS_EFDTSTGT = 300 , PPC_INS_EFDTSTLT = 301 , PPC_INS_EFSABS = 302 , PPC_INS_EFSADD = 303 , PPC_INS_EFSCFD = 304 , PPC_INS_EFSCFSF = 305 , PPC_INS_EFSCFSI = 306 , PPC_INS_EFSCFUF = 307 , PPC_INS_EFSCFUI = 308 , PPC_INS_EFSCMPEQ = 309 , PPC_INS_EFSCMPGT = 310 , PPC_INS_EFSCMPLT = 311 , PPC_INS_EFSCTSF = 312 , PPC_INS_EFSCTSI = 313 , PPC_INS_EFSCTSIZ = 314 , PPC_INS_EFSCTUF = 315 , PPC_INS_EFSCTUI = 316 , PPC_INS_EFSCTUIZ = 317 , PPC_INS_EFSDIV = 318 , PPC_INS_EFSMUL = 319 , PPC_INS_EFSNABS = 320 , PPC_INS_EFSNEG = 321 , PPC_INS_EFSSUB = 322 , PPC_INS_EFSTSTEQ = 323 , PPC_INS_EFSTSTGT = 324 , PPC_INS_EFSTSTLT = 325 , PPC_INS_EIEIO = 326 , PPC_INS_EQV = 327 , PPC_INS_EVABS = 328 , PPC_INS_EVADDIW = 329 , PPC_INS_EVADDSMIAAW = 330 , PPC_INS_EVADDSSIAAW = 331 , PPC_INS_EVADDUMIAAW = 332 , PPC_INS_EVADDUSIAAW = 333 , PPC_INS_EVADDW = 334 , PPC_INS_EVAND = 335 , PPC_INS_EVANDC = 336 , PPC_INS_EVCMPEQ = 337 , PPC_INS_EVCMPGTS = 338 , PPC_INS_EVCMPGTU = 339 , PPC_INS_EVCMPLTS = 340 , PPC_INS_EVCMPLTU = 341 , PPC_INS_EVCNTLSW = 342 , PPC_INS_EVCNTLZW = 343 , PPC_INS_EVDIVWS = 344 , PPC_INS_EVDIVWU = 345 , PPC_INS_EVEQV = 346 , PPC_INS_EVEXTSB = 347 , PPC_INS_EVEXTSH = 348 , PPC_INS_EVFSABS = 349 , PPC_INS_EVFSADD = 350 , PPC_INS_EVFSCFSF = 351 , PPC_INS_EVFSCFSI = 352 , PPC_INS_EVFSCFUF = 353 , PPC_INS_EVFSCFUI = 354 , PPC_INS_EVFSCMPEQ = 355 , PPC_INS_EVFSCMPGT = 356 , PPC_INS_EVFSCMPLT = 357 , PPC_INS_EVFSCTSF = 358 , PPC_INS_EVFSCTSI = 359 , PPC_INS_EVFSCTSIZ = 360 , PPC_INS_EVFSCTUI = 361 , PPC_INS_EVFSDIV = 362 , PPC_INS_EVFSMUL = 363 , PPC_INS_EVFSNABS = 364 , PPC_INS_EVFSNEG = 365 , PPC_INS_EVFSSUB = 366 , PPC_INS_EVFSTSTEQ = 367 , PPC_INS_EVFSTSTGT = 368 , PPC_INS_EVFSTSTLT = 369 , PPC_INS_EVLDD = 370 , PPC_INS_EVLDDX = 371 , PPC_INS_EVLDH = 372 , PPC_INS_EVLDHX = 373 , PPC_INS_EVLDW = 374 , PPC_INS_EVLDWX = 375 , PPC_INS_EVLHHESPLAT = 376 , PPC_INS_EVLHHESPLATX = 377 , PPC_INS_EVLHHOSSPLAT = 378 , PPC_INS_EVLHHOSSPLATX = 379 , PPC_INS_EVLHHOUSPLAT = 380 , PPC_INS_EVLHHOUSPLATX = 381 , PPC_INS_EVLWHE = 382 , PPC_INS_EVLWHEX = 383 , PPC_INS_EVLWHOS = 384 , PPC_INS_EVLWHOSX = 385 , PPC_INS_EVLWHOU = 386 , PPC_INS_EVLWHOUX = 387 , PPC_INS_EVLWHSPLAT = 388 , PPC_INS_EVLWHSPLATX = 389 , PPC_INS_EVLWWSPLAT = 390 , PPC_INS_EVLWWSPLATX = 391 , PPC_INS_EVMERGEHI = 392 , PPC_INS_EVMERGEHILO = 393 , PPC_INS_EVMERGELO = 394 , PPC_INS_EVMERGELOHI = 395 , PPC_INS_EVMHEGSMFAA = 396 , PPC_INS_EVMHEGSMFAN = 397 , PPC_INS_EVMHEGSMIAA = 398 , PPC_INS_EVMHEGSMIAN = 399 , PPC_INS_EVMHEGUMIAA = 400 , PPC_INS_EVMHEGUMIAN = 401 , PPC_INS_EVMHESMF = 402 , PPC_INS_EVMHESMFA = 403 , PPC_INS_EVMHESMFAAW = 404 , PPC_INS_EVMHESMFANW = 405 , PPC_INS_EVMHESMI = 406 , PPC_INS_EVMHESMIA = 407 , PPC_INS_EVMHESMIAAW = 408 , PPC_INS_EVMHESMIANW = 409 , PPC_INS_EVMHESSF = 410 , PPC_INS_EVMHESSFA = 411 , PPC_INS_EVMHESSFAAW = 412 , PPC_INS_EVMHESSFANW = 413 , PPC_INS_EVMHESSIAAW = 414 , PPC_INS_EVMHESSIANW = 415 , PPC_INS_EVMHEUMI = 416 , PPC_INS_EVMHEUMIA = 417 , PPC_INS_EVMHEUMIAAW = 418 , PPC_INS_EVMHEUMIANW = 419 , PPC_INS_EVMHEUSIAAW = 420 , PPC_INS_EVMHEUSIANW = 421 , PPC_INS_EVMHOGSMFAA = 422 , PPC_INS_EVMHOGSMFAN = 423 , PPC_INS_EVMHOGSMIAA = 424 , PPC_INS_EVMHOGSMIAN = 425 , PPC_INS_EVMHOGUMIAA = 426 , PPC_INS_EVMHOGUMIAN = 427 , PPC_INS_EVMHOSMF = 428 , PPC_INS_EVMHOSMFA = 429 , PPC_INS_EVMHOSMFAAW = 430 , PPC_INS_EVMHOSMFANW = 431 , PPC_INS_EVMHOSMI = 432 , PPC_INS_EVMHOSMIA = 433 , PPC_INS_EVMHOSMIAAW = 434 , PPC_INS_EVMHOSMIANW = 435 , PPC_INS_EVMHOSSF = 436 , PPC_INS_EVMHOSSFA = 437 , PPC_INS_EVMHOSSFAAW = 438 , PPC_INS_EVMHOSSFANW = 439 , PPC_INS_EVMHOSSIAAW = 440 , PPC_INS_EVMHOSSIANW = 441 , PPC_INS_EVMHOUMI = 442 , PPC_INS_EVMHOUMIA = 443 , PPC_INS_EVMHOUMIAAW = 444 , PPC_INS_EVMHOUMIANW = 445 , PPC_INS_EVMHOUSIAAW = 446 , PPC_INS_EVMHOUSIANW = 447 , PPC_INS_EVMRA = 448 , PPC_INS_EVMWHSMF = 449 , PPC_INS_EVMWHSMFA = 450 , PPC_INS_EVMWHSMI = 451 , PPC_INS_EVMWHSMIA = 452 , PPC_INS_EVMWHSSF = 453 , PPC_INS_EVMWHSSFA = 454 , PPC_INS_EVMWHUMI = 455 , PPC_INS_EVMWHUMIA = 456 , PPC_INS_EVMWLSMIAAW = 457 , PPC_INS_EVMWLSMIANW = 458 , PPC_INS_EVMWLSSIAAW = 459 , PPC_INS_EVMWLSSIANW = 460 , PPC_INS_EVMWLUMI = 461 , PPC_INS_EVMWLUMIA = 462 , PPC_INS_EVMWLUMIAAW = 463 , PPC_INS_EVMWLUMIANW = 464 , PPC_INS_EVMWLUSIAAW = 465 , PPC_INS_EVMWLUSIANW = 466 , PPC_INS_EVMWSMF = 467 , PPC_INS_EVMWSMFA = 468 , PPC_INS_EVMWSMFAA = 469 , PPC_INS_EVMWSMFAN = 470 , PPC_INS_EVMWSMI = 471 , PPC_INS_EVMWSMIA = 472 , PPC_INS_EVMWSMIAA = 473 , PPC_INS_EVMWSMIAN = 474 , PPC_INS_EVMWSSF = 475 , PPC_INS_EVMWSSFA = 476 , PPC_INS_EVMWSSFAA = 477 , PPC_INS_EVMWSSFAN = 478 , PPC_INS_EVMWUMI = 479 , PPC_INS_EVMWUMIA = 480 , PPC_INS_EVMWUMIAA = 481 , PPC_INS_EVMWUMIAN = 482 , PPC_INS_EVNAND = 483 , PPC_INS_EVNEG = 484 , PPC_INS_EVNOR = 485 , PPC_INS_EVOR = 486 , PPC_INS_EVORC = 487 , PPC_INS_EVRLW = 488 , PPC_INS_EVRLWI = 489 , PPC_INS_EVRNDW = 490 , PPC_INS_EVSEL = 491 , PPC_INS_EVSLW = 492 , PPC_INS_EVSLWI = 493 , PPC_INS_EVSPLATFI = 494 , PPC_INS_EVSPLATI = 495 , PPC_INS_EVSRWIS = 496 , PPC_INS_EVSRWIU = 497 , PPC_INS_EVSRWS = 498 , PPC_INS_EVSRWU = 499 , PPC_INS_EVSTDD = 500 , PPC_INS_EVSTDDX = 501 , PPC_INS_EVSTDH = 502 , PPC_INS_EVSTDHX = 503 , PPC_INS_EVSTDW = 504 , PPC_INS_EVSTDWX = 505 , PPC_INS_EVSTWHE = 506 , PPC_INS_EVSTWHEX = 507 , PPC_INS_EVSTWHO = 508 , PPC_INS_EVSTWHOX = 509 , PPC_INS_EVSTWWE = 510 , PPC_INS_EVSTWWEX = 511 , PPC_INS_EVSTWWO = 512 , PPC_INS_EVSTWWOX = 513 , PPC_INS_EVSUBFSMIAAW = 514 , PPC_INS_EVSUBFSSIAAW = 515 , PPC_INS_EVSUBFUMIAAW = 516 , PPC_INS_EVSUBFUSIAAW = 517 , PPC_INS_EVSUBFW = 518 , PPC_INS_EVSUBIFW = 519 , PPC_INS_EVXOR = 520 , PPC_INS_EXTLDI = 521 , PPC_INS_EXTLWI = 522 , PPC_INS_EXTRDI = 523 , PPC_INS_EXTRWI = 524 , PPC_INS_EXTSB = 525 , PPC_INS_EXTSH = 526 , PPC_INS_EXTSW = 527 , PPC_INS_EXTSWSLI = 528 , PPC_INS_FABS = 529 , PPC_INS_FADD = 530 , PPC_INS_FADDS = 531 , PPC_INS_FCFID = 532 , PPC_INS_FCFIDS = 533 , PPC_INS_FCFIDU = 534 , PPC_INS_FCFIDUS = 535 , PPC_INS_FCMPU = 536 , PPC_INS_FCPSGN = 537 , PPC_INS_FCTID = 538 , PPC_INS_FCTIDU = 539 , PPC_INS_FCTIDUZ = 540 , PPC_INS_FCTIDZ = 541 , PPC_INS_FCTIW = 542 , PPC_INS_FCTIWU = 543 , PPC_INS_FCTIWUZ = 544 , PPC_INS_FCTIWZ = 545 , PPC_INS_FDIV = 546 , PPC_INS_FDIVS = 547 , PPC_INS_FMADD = 548 , PPC_INS_FMADDS = 549 , PPC_INS_FMR = 550 , PPC_INS_FMSUB = 551 , PPC_INS_FMSUBS = 552 , PPC_INS_FMUL = 553 , PPC_INS_FMULS = 554 , PPC_INS_FNABS = 555 , PPC_INS_FNEG = 556 , PPC_INS_FNMADD = 557 , PPC_INS_FNMADDS = 558 , PPC_INS_FNMSUB = 559 , PPC_INS_FNMSUBS = 560 , PPC_INS_FRE = 561 , PPC_INS_FRES = 562 , PPC_INS_FRIM = 563 , PPC_INS_FRIN = 564 , PPC_INS_FRIP = 565 , PPC_INS_FRIZ = 566 , PPC_INS_FRSP = 567 , PPC_INS_FRSQRTE = 568 , PPC_INS_FRSQRTES = 569 , PPC_INS_FSEL = 570 , PPC_INS_FSQRT = 571 , PPC_INS_FSQRTS = 572 , PPC_INS_FSUB = 573 , PPC_INS_FSUBS = 574 , PPC_INS_FTDIV = 575 , PPC_INS_FTSQRT = 576 , PPC_INS_HRFID = 577 , PPC_INS_ICBI = 578 , PPC_INS_ICBIEP = 579 , PPC_INS_ICBLC = 580 , PPC_INS_ICBLQ = 581 , PPC_INS_ICBT = 582 , PPC_INS_ICBTLS = 583 , PPC_INS_ICCCI = 584 , PPC_INS_ICI = 585 , PPC_INS_INSLWI = 586 , PPC_INS_INSRDI = 587 , PPC_INS_INSRWI = 588 , PPC_INS_ISEL = 589 , PPC_INS_ISYNC = 590 , PPC_INS_LA = 591 , PPC_INS_LBARX = 592 , PPC_INS_LBEPX = 593 , PPC_INS_LBZ = 594 , PPC_INS_LBZCIX = 595 , PPC_INS_LBZU = 596 , PPC_INS_LBZUX = 597 , PPC_INS_LBZX = 598 , PPC_INS_LD = 599 , PPC_INS_LDARX = 600 , PPC_INS_LDAT = 601 , PPC_INS_LDBRX = 602 , PPC_INS_LDCIX = 603 , PPC_INS_LDMX = 604 , PPC_INS_LDU = 605 , PPC_INS_LDUX = 606 , PPC_INS_LDX = 607 , PPC_INS_LFD = 608 , PPC_INS_LFDEPX = 609 , PPC_INS_LFDU = 610 , PPC_INS_LFDUX = 611 , PPC_INS_LFDX = 612 , PPC_INS_LFIWAX = 613 , PPC_INS_LFIWZX = 614 , PPC_INS_LFS = 615 , PPC_INS_LFSU = 616 , PPC_INS_LFSUX = 617 , PPC_INS_LFSX = 618 , PPC_INS_LHA = 619 , PPC_INS_LHARX = 620 , PPC_INS_LHAU = 621 , PPC_INS_LHAUX = 622 , PPC_INS_LHAX = 623 , PPC_INS_LHBRX = 624 , PPC_INS_LHEPX = 625 , PPC_INS_LHZ = 626 , PPC_INS_LHZCIX = 627 , PPC_INS_LHZU = 628 , PPC_INS_LHZUX = 629 , PPC_INS_LHZX = 630 , PPC_INS_LI = 631 , PPC_INS_LIS = 632 , PPC_INS_LMW = 633 , PPC_INS_LNIA = 634 , PPC_INS_LSWI = 635 , PPC_INS_LVEBX = 636 , PPC_INS_LVEHX = 637 , PPC_INS_LVEWX = 638 , PPC_INS_LVSL = 639 , PPC_INS_LVSR = 640 , PPC_INS_LVX = 641 , PPC_INS_LVXL = 642 , PPC_INS_LWA = 643 , PPC_INS_LWARX = 644 , PPC_INS_LWAT = 645 , PPC_INS_LWAUX = 646 , PPC_INS_LWAX = 647 , PPC_INS_LWBRX = 648 , PPC_INS_LWEPX = 649 , PPC_INS_LWSYNC = 650 , PPC_INS_LWZ = 651 , PPC_INS_LWZCIX = 652 , PPC_INS_LWZU = 653 , PPC_INS_LWZUX = 654 , PPC_INS_LWZX = 655 , PPC_INS_LXSD = 656 , PPC_INS_LXSDX = 657 , PPC_INS_LXSIBZX = 658 , PPC_INS_LXSIHZX = 659 , PPC_INS_LXSIWAX = 660 , PPC_INS_LXSIWZX = 661 , PPC_INS_LXSSP = 662 , PPC_INS_LXSSPX = 663 , PPC_INS_LXV = 664 , PPC_INS_LXVB16X = 665 , PPC_INS_LXVD2X = 666 , PPC_INS_LXVDSX = 667 , PPC_INS_LXVH8X = 668 , PPC_INS_LXVL = 669 , PPC_INS_LXVLL = 670 , PPC_INS_LXVW4X = 671 , PPC_INS_LXVWSX = 672 , PPC_INS_LXVX = 673 , PPC_INS_MADDHD = 674 , PPC_INS_MADDHDU = 675 , PPC_INS_MADDLD = 676 , PPC_INS_MBAR = 677 , PPC_INS_MCRF = 678 , PPC_INS_MCRFS = 679 , PPC_INS_MCRXRX = 680 , PPC_INS_MFAMR = 681 , PPC_INS_MFASR = 682 , PPC_INS_MFBHRBE = 683 , PPC_INS_MFBR0 = 684 , PPC_INS_MFBR1 = 685 , PPC_INS_MFBR2 = 686 , PPC_INS_MFBR3 = 687 , PPC_INS_MFBR4 = 688 , PPC_INS_MFBR5 = 689 , PPC_INS_MFBR6 = 690 , PPC_INS_MFBR7 = 691 , PPC_INS_MFCFAR = 692 , PPC_INS_MFCR = 693 , PPC_INS_MFCTR = 694 , PPC_INS_MFDAR = 695 , PPC_INS_MFDBATL = 696 , PPC_INS_MFDBATU = 697 , PPC_INS_MFDCCR = 698 , PPC_INS_MFDCR = 699 , PPC_INS_MFDEAR = 700 , PPC_INS_MFDEC = 701 , PPC_INS_MFDSCR = 702 , PPC_INS_MFDSISR = 703 , PPC_INS_MFESR = 704 , PPC_INS_MFFPRD = 705 , PPC_INS_MFFS = 706 , PPC_INS_MFFSCDRN = 707 , PPC_INS_MFFSCDRNI = 708 , PPC_INS_MFFSCE = 709 , PPC_INS_MFFSCRN = 710 , PPC_INS_MFFSCRNI = 711 , PPC_INS_MFFSL = 712 , PPC_INS_MFIBATL = 713 , PPC_INS_MFIBATU = 714 , PPC_INS_MFICCR = 715 , PPC_INS_MFLR = 716 , PPC_INS_MFMSR = 717 , PPC_INS_MFOCRF = 718 , PPC_INS_MFPID = 719 , PPC_INS_MFPMR = 720 , PPC_INS_MFPVR = 721 , PPC_INS_MFRTCL = 722 , PPC_INS_MFRTCU = 723 , PPC_INS_MFSDR1 = 724 , PPC_INS_MFSPEFSCR = 725 , PPC_INS_MFSPR = 726 , PPC_INS_MFSPRG = 727 , PPC_INS_MFSPRG0 = 728 , PPC_INS_MFSPRG1 = 729 , PPC_INS_MFSPRG2 = 730 , PPC_INS_MFSPRG3 = 731 , PPC_INS_MFSPRG4 = 732 , PPC_INS_MFSPRG5 = 733 , PPC_INS_MFSPRG6 = 734 , PPC_INS_MFSPRG7 = 735 , PPC_INS_MFSR = 736 , PPC_INS_MFSRIN = 737 , PPC_INS_MFSRR0 = 738 , PPC_INS_MFSRR1 = 739 , PPC_INS_MFSRR2 = 740 , PPC_INS_MFSRR3 = 741 , PPC_INS_MFTB = 742 , PPC_INS_MFTBHI = 743 , PPC_INS_MFTBL = 744 , PPC_INS_MFTBLO = 745 , PPC_INS_MFTBU = 746 , PPC_INS_MFTCR = 747 , PPC_INS_MFVRD = 748 , PPC_INS_MFVRSAVE = 749 , PPC_INS_MFVSCR = 750 , PPC_INS_MFVSRD = 751 , PPC_INS_MFVSRLD = 752 , PPC_INS_MFVSRWZ = 753 , PPC_INS_MFXER = 754 , PPC_INS_MODSD = 755 , PPC_INS_MODSW = 756 , PPC_INS_MODUD = 757 , PPC_INS_MODUW = 758 , PPC_INS_MR = 759 , PPC_INS_MSGSYNC = 760 , PPC_INS_MSYNC = 761 , PPC_INS_MTAMR = 762 , PPC_INS_MTASR = 763 , PPC_INS_MTBR0 = 764 , PPC_INS_MTBR1 = 765 , PPC_INS_MTBR2 = 766 , PPC_INS_MTBR3 = 767 , PPC_INS_MTBR4 = 768 , PPC_INS_MTBR5 = 769 , PPC_INS_MTBR6 = 770 , PPC_INS_MTBR7 = 771 , PPC_INS_MTCFAR = 772 , PPC_INS_MTCR = 773 , PPC_INS_MTCRF = 774 , PPC_INS_MTCTR = 775 , PPC_INS_MTDAR = 776 , PPC_INS_MTDBATL = 777 , PPC_INS_MTDBATU = 778 , PPC_INS_MTDCCR = 779 , PPC_INS_MTDCR = 780 , PPC_INS_MTDEAR = 781 , PPC_INS_MTDEC = 782 , PPC_INS_MTDSCR = 783 , PPC_INS_MTDSISR = 784 , PPC_INS_MTESR = 785 , PPC_INS_MTFSB0 = 786 , PPC_INS_MTFSB1 = 787 , PPC_INS_MTFSF = 788 , PPC_INS_MTFSFI = 789 , PPC_INS_MTIBATL = 790 , PPC_INS_MTIBATU = 791 , PPC_INS_MTICCR = 792 , PPC_INS_MTLR = 793 , PPC_INS_MTMSR = 794 , PPC_INS_MTMSRD = 795 , PPC_INS_MTOCRF = 796 , PPC_INS_MTPID = 797 , PPC_INS_MTPMR = 798 , PPC_INS_MTSDR1 = 799 , PPC_INS_MTSPEFSCR = 800 , PPC_INS_MTSPR = 801 , PPC_INS_MTSPRG = 802 , PPC_INS_MTSPRG0 = 803 , PPC_INS_MTSPRG1 = 804 , PPC_INS_MTSPRG2 = 805 , PPC_INS_MTSPRG3 = 806 , PPC_INS_MTSPRG4 = 807 , PPC_INS_MTSPRG5 = 808 , PPC_INS_MTSPRG6 = 809 , PPC_INS_MTSPRG7 = 810 , PPC_INS_MTSR = 811 , PPC_INS_MTSRIN = 812 , PPC_INS_MTSRR0 = 813 , PPC_INS_MTSRR1 = 814 , PPC_INS_MTSRR2 = 815 , PPC_INS_MTSRR3 = 816 , PPC_INS_MTTBHI = 817 , PPC_INS_MTTBL = 818 , PPC_INS_MTTBLO = 819 , PPC_INS_MTTBU = 820 , PPC_INS_MTTCR = 821 , PPC_INS_MTVRSAVE = 822 , PPC_INS_MTVSCR = 823 , PPC_INS_MTVSRD = 824 , PPC_INS_MTVSRDD = 825 , PPC_INS_MTVSRWA = 826 , PPC_INS_MTVSRWS = 827 , PPC_INS_MTVSRWZ = 828 , PPC_INS_MTXER = 829 , PPC_INS_MULHD = 830 , PPC_INS_MULHDU = 831 , PPC_INS_MULHW = 832 , PPC_INS_MULHWU = 833 , PPC_INS_MULLD = 834 , PPC_INS_MULLI = 835 , PPC_INS_MULLW = 836 , PPC_INS_NAND = 837 , PPC_INS_NAP = 838 , PPC_INS_NEG = 839 , PPC_INS_NOP = 840 , PPC_INS_NOR = 841 , PPC_INS_NOT = 842 , PPC_INS_OR = 843 , PPC_INS_ORC = 844 , PPC_INS_ORI = 845 , PPC_INS_ORIS = 846 , PPC_INS_PASTE = 847 , PPC_INS_PASTE_LAST = 848 , PPC_INS_POPCNTB = 849 , PPC_INS_POPCNTD = 850 , PPC_INS_POPCNTW = 851 , PPC_INS_PTESYNC = 852 , PPC_INS_QVALIGNI = 853 , PPC_INS_QVESPLATI = 854 , PPC_INS_QVFABS = 855 , PPC_INS_QVFADD = 856 , PPC_INS_QVFADDS = 857 , PPC_INS_QVFAND = 858 , PPC_INS_QVFANDC = 859 , PPC_INS_QVFCFID = 860 , PPC_INS_QVFCFIDS = 861 , PPC_INS_QVFCFIDU = 862 , PPC_INS_QVFCFIDUS = 863 , PPC_INS_QVFCLR = 864 , PPC_INS_QVFCMPEQ = 865 , PPC_INS_QVFCMPGT = 866 , PPC_INS_QVFCMPLT = 867 , PPC_INS_QVFCPSGN = 868 , PPC_INS_QVFCTFB = 869 , PPC_INS_QVFCTID = 870 , PPC_INS_QVFCTIDU = 871 , PPC_INS_QVFCTIDUZ = 872 , PPC_INS_QVFCTIDZ = 873 , PPC_INS_QVFCTIW = 874 , PPC_INS_QVFCTIWU = 875 , PPC_INS_QVFCTIWUZ = 876 , PPC_INS_QVFCTIWZ = 877 , PPC_INS_QVFEQU = 878 , PPC_INS_QVFLOGICAL = 879 , PPC_INS_QVFMADD = 880 , PPC_INS_QVFMADDS = 881 , PPC_INS_QVFMR = 882 , PPC_INS_QVFMSUB = 883 , PPC_INS_QVFMSUBS = 884 , PPC_INS_QVFMUL = 885 , PPC_INS_QVFMULS = 886 , PPC_INS_QVFNABS = 887 , PPC_INS_QVFNAND = 888 , PPC_INS_QVFNEG = 889 , PPC_INS_QVFNMADD = 890 , PPC_INS_QVFNMADDS = 891 , PPC_INS_QVFNMSUB = 892 , PPC_INS_QVFNMSUBS = 893 , PPC_INS_QVFNOR = 894 , PPC_INS_QVFNOT = 895 , PPC_INS_QVFOR = 896 , PPC_INS_QVFORC = 897 , PPC_INS_QVFPERM = 898 , PPC_INS_QVFRE = 899 , PPC_INS_QVFRES = 900 , PPC_INS_QVFRIM = 901 , PPC_INS_QVFRIN = 902 , PPC_INS_QVFRIP = 903 , PPC_INS_QVFRIZ = 904 , PPC_INS_QVFRSP = 905 , PPC_INS_QVFRSQRTE = 906 , PPC_INS_QVFRSQRTES = 907 , PPC_INS_QVFSEL = 908 , PPC_INS_QVFSET = 909 , PPC_INS_QVFSUB = 910 , PPC_INS_QVFSUBS = 911 , PPC_INS_QVFTSTNAN = 912 , PPC_INS_QVFXMADD = 913 , PPC_INS_QVFXMADDS = 914 , PPC_INS_QVFXMUL = 915 , PPC_INS_QVFXMULS = 916 , PPC_INS_QVFXOR = 917 , PPC_INS_QVFXXCPNMADD = 918 , PPC_INS_QVFXXCPNMADDS = 919 , PPC_INS_QVFXXMADD = 920 , PPC_INS_QVFXXMADDS = 921 , PPC_INS_QVFXXNPMADD = 922 , PPC_INS_QVFXXNPMADDS = 923 , PPC_INS_QVGPCI = 924 , PPC_INS_QVLFCDUX = 925 , PPC_INS_QVLFCDUXA = 926 , PPC_INS_QVLFCDX = 927 , PPC_INS_QVLFCDXA = 928 , PPC_INS_QVLFCSUX = 929 , PPC_INS_QVLFCSUXA = 930 , PPC_INS_QVLFCSX = 931 , PPC_INS_QVLFCSXA = 932 , PPC_INS_QVLFDUX = 933 , PPC_INS_QVLFDUXA = 934 , PPC_INS_QVLFDX = 935 , PPC_INS_QVLFDXA = 936 , PPC_INS_QVLFIWAX = 937 , PPC_INS_QVLFIWAXA = 938 , PPC_INS_QVLFIWZX = 939 , PPC_INS_QVLFIWZXA = 940 , PPC_INS_QVLFSUX = 941 , PPC_INS_QVLFSUXA = 942 , PPC_INS_QVLFSX = 943 , PPC_INS_QVLFSXA = 944 , PPC_INS_QVLPCLDX = 945 , PPC_INS_QVLPCLSX = 946 , PPC_INS_QVLPCRDX = 947 , PPC_INS_QVLPCRSX = 948 , PPC_INS_QVSTFCDUX = 949 , PPC_INS_QVSTFCDUXA = 950 , PPC_INS_QVSTFCDUXI = 951 , PPC_INS_QVSTFCDUXIA = 952 , PPC_INS_QVSTFCDX = 953 , PPC_INS_QVSTFCDXA = 954 , PPC_INS_QVSTFCDXI = 955 , PPC_INS_QVSTFCDXIA = 956 , PPC_INS_QVSTFCSUX = 957 , PPC_INS_QVSTFCSUXA = 958 , PPC_INS_QVSTFCSUXI = 959 , PPC_INS_QVSTFCSUXIA = 960 , PPC_INS_QVSTFCSX = 961 , PPC_INS_QVSTFCSXA = 962 , PPC_INS_QVSTFCSXI = 963 , PPC_INS_QVSTFCSXIA = 964 , PPC_INS_QVSTFDUX = 965 , PPC_INS_QVSTFDUXA = 966 , PPC_INS_QVSTFDUXI = 967 , PPC_INS_QVSTFDUXIA = 968 , PPC_INS_QVSTFDX = 969 , PPC_INS_QVSTFDXA = 970 , PPC_INS_QVSTFDXI = 971 , PPC_INS_QVSTFDXIA = 972 , PPC_INS_QVSTFIWX = 973 , PPC_INS_QVSTFIWXA = 974 , PPC_INS_QVSTFSUX = 975 , PPC_INS_QVSTFSUXA = 976 , PPC_INS_QVSTFSUXI = 977 , PPC_INS_QVSTFSUXIA = 978 , PPC_INS_QVSTFSX = 979 , PPC_INS_QVSTFSXA = 980 , PPC_INS_QVSTFSXI = 981 , PPC_INS_QVSTFSXIA = 982 , PPC_INS_RFCI = 983 , PPC_INS_RFDI = 984 , PPC_INS_RFEBB = 985 , PPC_INS_RFI = 986 , PPC_INS_RFID = 987 , PPC_INS_RFMCI = 988 , PPC_INS_RLDCL = 989 , PPC_INS_RLDCR = 990 , PPC_INS_RLDIC = 991 , PPC_INS_RLDICL = 992 , PPC_INS_RLDICR = 993 , PPC_INS_RLDIMI = 994 , PPC_INS_RLWIMI = 995 , PPC_INS_RLWINM = 996 , PPC_INS_RLWNM = 997 , PPC_INS_ROTLD = 998 , PPC_INS_ROTLDI = 999 , PPC_INS_ROTLW = 1000 , PPC_INS_ROTLWI = 1001 , PPC_INS_ROTRDI = 1002 , PPC_INS_ROTRWI = 1003 , PPC_INS_SC = 1004 , PPC_INS_SETB = 1005 , PPC_INS_SLBIA = 1006 , PPC_INS_SLBIE = 1007 , PPC_INS_SLBIEG = 1008 , PPC_INS_SLBMFEE = 1009 , PPC_INS_SLBMFEV = 1010 , PPC_INS_SLBMTE = 1011 , PPC_INS_SLBSYNC = 1012 , PPC_INS_SLD = 1013 , PPC_INS_SLDI = 1014 , PPC_INS_SLW = 1015 , PPC_INS_SLWI = 1016 , PPC_INS_SRAD = 1017 , PPC_INS_SRADI = 1018 , PPC_INS_SRAW = 1019 , PPC_INS_SRAWI = 1020 , PPC_INS_SRD = 1021 , PPC_INS_SRDI = 1022 , PPC_INS_SRW = 1023 , PPC_INS_SRWI = 1024 , PPC_INS_STB = 1025 , PPC_INS_STBCIX = 1026 , PPC_INS_STBCX = 1027 , PPC_INS_STBEPX = 1028 , PPC_INS_STBU = 1029 , PPC_INS_STBUX = 1030 , PPC_INS_STBX = 1031 , PPC_INS_STD = 1032 , PPC_INS_STDAT = 1033 , PPC_INS_STDBRX = 1034 , PPC_INS_STDCIX = 1035 , PPC_INS_STDCX = 1036 , PPC_INS_STDU = 1037 , PPC_INS_STDUX = 1038 , PPC_INS_STDX = 1039 , PPC_INS_STFD = 1040 , PPC_INS_STFDEPX = 1041 , PPC_INS_STFDU = 1042 , PPC_INS_STFDUX = 1043 , PPC_INS_STFDX = 1044 , PPC_INS_STFIWX = 1045 , PPC_INS_STFS = 1046 , PPC_INS_STFSU = 1047 , PPC_INS_STFSUX = 1048 , PPC_INS_STFSX = 1049 , PPC_INS_STH = 1050 , PPC_INS_STHBRX = 1051 , PPC_INS_STHCIX = 1052 , PPC_INS_STHCX = 1053 , PPC_INS_STHEPX = 1054 , PPC_INS_STHU = 1055 , PPC_INS_STHUX = 1056 , PPC_INS_STHX = 1057 , PPC_INS_STMW = 1058 , PPC_INS_STOP = 1059 , PPC_INS_STSWI = 1060 , PPC_INS_STVEBX = 1061 , PPC_INS_STVEHX = 1062 , PPC_INS_STVEWX = 1063 , PPC_INS_STVX = 1064 , PPC_INS_STVXL = 1065 , PPC_INS_STW = 1066 , PPC_INS_STWAT = 1067 , PPC_INS_STWBRX = 1068 , PPC_INS_STWCIX = 1069 , PPC_INS_STWCX = 1070 , PPC_INS_STWEPX = 1071 , PPC_INS_STWU = 1072 , PPC_INS_STWUX = 1073 , PPC_INS_STWX = 1074 , PPC_INS_STXSD = 1075 , PPC_INS_STXSDX = 1076 , PPC_INS_STXSIBX = 1077 , PPC_INS_STXSIHX = 1078 , PPC_INS_STXSIWX = 1079 , PPC_INS_STXSSP = 1080 , PPC_INS_STXSSPX = 1081 , PPC_INS_STXV = 1082 , PPC_INS_STXVB16X = 1083 , PPC_INS_STXVD2X = 1084 , PPC_INS_STXVH8X = 1085 , PPC_INS_STXVL = 1086 , PPC_INS_STXVLL = 1087 , PPC_INS_STXVW4X = 1088 , PPC_INS_STXVX = 1089 , PPC_INS_SUB = 1090 , PPC_INS_SUBC = 1091 , PPC_INS_SUBF = 1092 , PPC_INS_SUBFC = 1093 , PPC_INS_SUBFE = 1094 , PPC_INS_SUBFIC = 1095 , PPC_INS_SUBFME = 1096 , PPC_INS_SUBFZE = 1097 , PPC_INS_SUBI = 1098 , PPC_INS_SUBIC = 1099 , PPC_INS_SUBIS = 1100 , PPC_INS_SUBPCIS = 1101 , PPC_INS_SYNC = 1102 , PPC_INS_TABORT = 1103 , PPC_INS_TABORTDC = 1104 , PPC_INS_TABORTDCI = 1105 , PPC_INS_TABORTWC = 1106 , PPC_INS_TABORTWCI = 1107 , PPC_INS_TBEGIN = 1108 , PPC_INS_TCHECK = 1109 , PPC_INS_TD = 1110 , PPC_INS_TDEQ = 1111 , PPC_INS_TDEQI = 1112 , PPC_INS_TDGE = 1113 , PPC_INS_TDGEI = 1114 , PPC_INS_TDGT = 1115 , PPC_INS_TDGTI = 1116 , PPC_INS_TDI = 1117 , PPC_INS_TDLE = 1118 , PPC_INS_TDLEI = 1119 , PPC_INS_TDLGE = 1120 , PPC_INS_TDLGEI = 1121 , PPC_INS_TDLGT = 1122 , PPC_INS_TDLGTI = 1123 , PPC_INS_TDLLE = 1124 , PPC_INS_TDLLEI = 1125 , PPC_INS_TDLLT = 1126 , PPC_INS_TDLLTI = 1127 , PPC_INS_TDLNG = 1128 , PPC_INS_TDLNGI = 1129 , PPC_INS_TDLNL = 1130 , PPC_INS_TDLNLI = 1131 , PPC_INS_TDLT = 1132 , PPC_INS_TDLTI = 1133 , PPC_INS_TDNE = 1134 , PPC_INS_TDNEI = 1135 , PPC_INS_TDNG = 1136 , PPC_INS_TDNGI = 1137 , PPC_INS_TDNL = 1138 , PPC_INS_TDNLI = 1139 , PPC_INS_TDU = 1140 , PPC_INS_TDUI = 1141 , PPC_INS_TEND = 1142 , PPC_INS_TLBIA = 1143 , PPC_INS_TLBIE = 1144 , PPC_INS_TLBIEL = 1145 , PPC_INS_TLBIVAX = 1146 , PPC_INS_TLBLD = 1147 , PPC_INS_TLBLI = 1148 , PPC_INS_TLBRE = 1149 , PPC_INS_TLBREHI = 1150 , PPC_INS_TLBRELO = 1151 , PPC_INS_TLBSX = 1152 , PPC_INS_TLBSYNC = 1153 , PPC_INS_TLBWE = 1154 , PPC_INS_TLBWEHI = 1155 , PPC_INS_TLBWELO = 1156 , PPC_INS_TRAP = 1157 , PPC_INS_TRECHKPT = 1158 , PPC_INS_TRECLAIM = 1159 , PPC_INS_TSR = 1160 , PPC_INS_TW = 1161 , PPC_INS_TWEQ = 1162 , PPC_INS_TWEQI = 1163 , PPC_INS_TWGE = 1164 , PPC_INS_TWGEI = 1165 , PPC_INS_TWGT = 1166 , PPC_INS_TWGTI = 1167 , PPC_INS_TWI = 1168 , PPC_INS_TWLE = 1169 , PPC_INS_TWLEI = 1170 , PPC_INS_TWLGE = 1171 , PPC_INS_TWLGEI = 1172 , PPC_INS_TWLGT = 1173 , PPC_INS_TWLGTI = 1174 , PPC_INS_TWLLE = 1175 , PPC_INS_TWLLEI = 1176 , PPC_INS_TWLLT = 1177 , PPC_INS_TWLLTI = 1178 , PPC_INS_TWLNG = 1179 , PPC_INS_TWLNGI = 1180 , PPC_INS_TWLNL = 1181 , PPC_INS_TWLNLI = 1182 , PPC_INS_TWLT = 1183 , PPC_INS_TWLTI = 1184 , PPC_INS_TWNE = 1185 , PPC_INS_TWNEI = 1186 , PPC_INS_TWNG = 1187 , PPC_INS_TWNGI = 1188 , PPC_INS_TWNL = 1189 , PPC_INS_TWNLI = 1190 , PPC_INS_TWU = 1191 , PPC_INS_TWUI = 1192 , PPC_INS_VABSDUB = 1193 , PPC_INS_VABSDUH = 1194 , PPC_INS_VABSDUW = 1195 , PPC_INS_VADDCUQ = 1196 , PPC_INS_VADDCUW = 1197 , PPC_INS_VADDECUQ = 1198 , PPC_INS_VADDEUQM = 1199 , PPC_INS_VADDFP = 1200 , PPC_INS_VADDSBS = 1201 , PPC_INS_VADDSHS = 1202 , PPC_INS_VADDSWS = 1203 , PPC_INS_VADDUBM = 1204 , PPC_INS_VADDUBS = 1205 , PPC_INS_VADDUDM = 1206 , PPC_INS_VADDUHM = 1207 , PPC_INS_VADDUHS = 1208 , PPC_INS_VADDUQM = 1209 , PPC_INS_VADDUWM = 1210 , PPC_INS_VADDUWS = 1211 , PPC_INS_VAND = 1212 , PPC_INS_VANDC = 1213 , PPC_INS_VAVGSB = 1214 , PPC_INS_VAVGSH = 1215 , PPC_INS_VAVGSW = 1216 , PPC_INS_VAVGUB = 1217 , PPC_INS_VAVGUH = 1218 , PPC_INS_VAVGUW = 1219 , PPC_INS_VBPERMD = 1220 , PPC_INS_VBPERMQ = 1221 , PPC_INS_VCFSX = 1222 , PPC_INS_VCFUX = 1223 , PPC_INS_VCIPHER = 1224 , PPC_INS_VCIPHERLAST = 1225 , PPC_INS_VCLZB = 1226 , PPC_INS_VCLZD = 1227 , PPC_INS_VCLZH = 1228 , PPC_INS_VCLZLSBB = 1229 , PPC_INS_VCLZW = 1230 , PPC_INS_VCMPBFP = 1231 , PPC_INS_VCMPEQFP = 1232 , PPC_INS_VCMPEQUB = 1233 , PPC_INS_VCMPEQUD = 1234 , PPC_INS_VCMPEQUH = 1235 , PPC_INS_VCMPEQUW = 1236 , PPC_INS_VCMPGEFP = 1237 , PPC_INS_VCMPGTFP = 1238 , PPC_INS_VCMPGTSB = 1239 , PPC_INS_VCMPGTSD = 1240 , PPC_INS_VCMPGTSH = 1241 , PPC_INS_VCMPGTSW = 1242 , PPC_INS_VCMPGTUB = 1243 , PPC_INS_VCMPGTUD = 1244 , PPC_INS_VCMPGTUH = 1245 , PPC_INS_VCMPGTUW = 1246 , PPC_INS_VCMPNEB = 1247 , PPC_INS_VCMPNEH = 1248 , PPC_INS_VCMPNEW = 1249 , PPC_INS_VCMPNEZB = 1250 , PPC_INS_VCMPNEZH = 1251 , PPC_INS_VCMPNEZW = 1252 , PPC_INS_VCTSXS = 1253 , PPC_INS_VCTUXS = 1254 , PPC_INS_VCTZB = 1255 , PPC_INS_VCTZD = 1256 , PPC_INS_VCTZH = 1257 , PPC_INS_VCTZLSBB = 1258 , PPC_INS_VCTZW = 1259 , PPC_INS_VEQV = 1260 , PPC_INS_VEXPTEFP = 1261 , PPC_INS_VEXTRACTD = 1262 , PPC_INS_VEXTRACTUB = 1263 , PPC_INS_VEXTRACTUH = 1264 , PPC_INS_VEXTRACTUW = 1265 , PPC_INS_VEXTSB2D = 1266 , PPC_INS_VEXTSB2W = 1267 , PPC_INS_VEXTSH2D = 1268 , PPC_INS_VEXTSH2W = 1269 , PPC_INS_VEXTSW2D = 1270 , PPC_INS_VEXTUBLX = 1271 , PPC_INS_VEXTUBRX = 1272 , PPC_INS_VEXTUHLX = 1273 , PPC_INS_VEXTUHRX = 1274 , PPC_INS_VEXTUWLX = 1275 , PPC_INS_VEXTUWRX = 1276 , PPC_INS_VGBBD = 1277 , PPC_INS_VINSERTB = 1278 , PPC_INS_VINSERTD = 1279 , PPC_INS_VINSERTH = 1280 , PPC_INS_VINSERTW = 1281 , PPC_INS_VLOGEFP = 1282 , PPC_INS_VMADDFP = 1283 , PPC_INS_VMAXFP = 1284 , PPC_INS_VMAXSB = 1285 , PPC_INS_VMAXSD = 1286 , PPC_INS_VMAXSH = 1287 , PPC_INS_VMAXSW = 1288 , PPC_INS_VMAXUB = 1289 , PPC_INS_VMAXUD = 1290 , PPC_INS_VMAXUH = 1291 , PPC_INS_VMAXUW = 1292 , PPC_INS_VMHADDSHS = 1293 , PPC_INS_VMHRADDSHS = 1294 , PPC_INS_VMINFP = 1295 , PPC_INS_VMINSB = 1296 , PPC_INS_VMINSD = 1297 , PPC_INS_VMINSH = 1298 , PPC_INS_VMINSW = 1299 , PPC_INS_VMINUB = 1300 , PPC_INS_VMINUD = 1301 , PPC_INS_VMINUH = 1302 , PPC_INS_VMINUW = 1303 , PPC_INS_VMLADDUHM = 1304 , PPC_INS_VMR = 1305 , PPC_INS_VMRGEW = 1306 , PPC_INS_VMRGHB = 1307 , PPC_INS_VMRGHH = 1308 , PPC_INS_VMRGHW = 1309 , PPC_INS_VMRGLB = 1310 , PPC_INS_VMRGLH = 1311 , PPC_INS_VMRGLW = 1312 , PPC_INS_VMRGOW = 1313 , PPC_INS_VMSUMMBM = 1314 , PPC_INS_VMSUMSHM = 1315 , PPC_INS_VMSUMSHS = 1316 , PPC_INS_VMSUMUBM = 1317 , PPC_INS_VMSUMUHM = 1318 , PPC_INS_VMSUMUHS = 1319 , PPC_INS_VMUL10CUQ = 1320 , PPC_INS_VMUL10ECUQ = 1321 , PPC_INS_VMUL10EUQ = 1322 , PPC_INS_VMUL10UQ = 1323 , PPC_INS_VMULESB = 1324 , PPC_INS_VMULESH = 1325 , PPC_INS_VMULESW = 1326 , PPC_INS_VMULEUB = 1327 , PPC_INS_VMULEUH = 1328 , PPC_INS_VMULEUW = 1329 , PPC_INS_VMULOSB = 1330 , PPC_INS_VMULOSH = 1331 , PPC_INS_VMULOSW = 1332 , PPC_INS_VMULOUB = 1333 , PPC_INS_VMULOUH = 1334 , PPC_INS_VMULOUW = 1335 , PPC_INS_VMULUWM = 1336 , PPC_INS_VNAND = 1337 , PPC_INS_VNCIPHER = 1338 , PPC_INS_VNCIPHERLAST = 1339 , PPC_INS_VNEGD = 1340 , PPC_INS_VNEGW = 1341 , PPC_INS_VNMSUBFP = 1342 , PPC_INS_VNOR = 1343 , PPC_INS_VNOT = 1344 , PPC_INS_VOR = 1345 , PPC_INS_VORC = 1346 , PPC_INS_VPERM = 1347 , PPC_INS_VPERMR = 1348 , PPC_INS_VPERMXOR = 1349 , PPC_INS_VPKPX = 1350 , PPC_INS_VPKSDSS = 1351 , PPC_INS_VPKSDUS = 1352 , PPC_INS_VPKSHSS = 1353 , PPC_INS_VPKSHUS = 1354 , PPC_INS_VPKSWSS = 1355 , PPC_INS_VPKSWUS = 1356 , PPC_INS_VPKUDUM = 1357 , PPC_INS_VPKUDUS = 1358 , PPC_INS_VPKUHUM = 1359 , PPC_INS_VPKUHUS = 1360 , PPC_INS_VPKUWUM = 1361 , PPC_INS_VPKUWUS = 1362 , PPC_INS_VPMSUMB = 1363 , PPC_INS_VPMSUMD = 1364 , PPC_INS_VPMSUMH = 1365 , PPC_INS_VPMSUMW = 1366 , PPC_INS_VPOPCNTB = 1367 , PPC_INS_VPOPCNTD = 1368 , PPC_INS_VPOPCNTH = 1369 , PPC_INS_VPOPCNTW = 1370 , PPC_INS_VPRTYBD = 1371 , PPC_INS_VPRTYBQ = 1372 , PPC_INS_VPRTYBW = 1373 , PPC_INS_VREFP = 1374 , PPC_INS_VRFIM = 1375 , PPC_INS_VRFIN = 1376 , PPC_INS_VRFIP = 1377 , PPC_INS_VRFIZ = 1378 , PPC_INS_VRLB = 1379 , PPC_INS_VRLD = 1380 , PPC_INS_VRLDMI = 1381 , PPC_INS_VRLDNM = 1382 , PPC_INS_VRLH = 1383 , PPC_INS_VRLW = 1384 , PPC_INS_VRLWMI = 1385 , PPC_INS_VRLWNM = 1386 , PPC_INS_VRSQRTEFP = 1387 , PPC_INS_VSBOX = 1388 , PPC_INS_VSEL = 1389 , PPC_INS_VSHASIGMAD = 1390 , PPC_INS_VSHASIGMAW = 1391 , PPC_INS_VSL = 1392 , PPC_INS_VSLB = 1393 , PPC_INS_VSLD = 1394 , PPC_INS_VSLDOI = 1395 , PPC_INS_VSLH = 1396 , PPC_INS_VSLO = 1397 , PPC_INS_VSLV = 1398 , PPC_INS_VSLW = 1399 , PPC_INS_VSPLTB = 1400 , PPC_INS_VSPLTH = 1401 , PPC_INS_VSPLTISB = 1402 , PPC_INS_VSPLTISH = 1403 , PPC_INS_VSPLTISW = 1404 , PPC_INS_VSPLTW = 1405 , PPC_INS_VSR = 1406 , PPC_INS_VSRAB = 1407 , PPC_INS_VSRAD = 1408 , PPC_INS_VSRAH = 1409 , PPC_INS_VSRAW = 1410 , PPC_INS_VSRB = 1411 , PPC_INS_VSRD = 1412 , PPC_INS_VSRH = 1413 , PPC_INS_VSRO = 1414 , PPC_INS_VSRV = 1415 , PPC_INS_VSRW = 1416 , PPC_INS_VSUBCUQ = 1417 , PPC_INS_VSUBCUW = 1418 , PPC_INS_VSUBECUQ = 1419 , PPC_INS_VSUBEUQM = 1420 , PPC_INS_VSUBFP = 1421 , PPC_INS_VSUBSBS = 1422 , PPC_INS_VSUBSHS = 1423 , PPC_INS_VSUBSWS = 1424 , PPC_INS_VSUBUBM = 1425 , PPC_INS_VSUBUBS = 1426 , PPC_INS_VSUBUDM = 1427 , PPC_INS_VSUBUHM = 1428 , PPC_INS_VSUBUHS = 1429 , PPC_INS_VSUBUQM = 1430 , PPC_INS_VSUBUWM = 1431 , PPC_INS_VSUBUWS = 1432 , PPC_INS_VSUM2SWS = 1433 , PPC_INS_VSUM4SBS = 1434 , PPC_INS_VSUM4SHS = 1435 , PPC_INS_VSUM4UBS = 1436 , PPC_INS_VSUMSWS = 1437 , PPC_INS_VUPKHPX = 1438 , PPC_INS_VUPKHSB = 1439 , PPC_INS_VUPKHSH = 1440 , PPC_INS_VUPKHSW = 1441 , PPC_INS_VUPKLPX = 1442 , PPC_INS_VUPKLSB = 1443 , PPC_INS_VUPKLSH = 1444 , PPC_INS_VUPKLSW = 1445 , PPC_INS_VXOR = 1446 , PPC_INS_WAIT = 1447 , PPC_INS_WAITIMPL = 1448 , PPC_INS_WAITRSV = 1449 , PPC_INS_WRTEE = 1450 , PPC_INS_WRTEEI = 1451 , PPC_INS_XNOP = 1452 , PPC_INS_XOR = 1453 , PPC_INS_XORI = 1454 , PPC_INS_XORIS = 1455 , PPC_INS_XSABSDP = 1456 , PPC_INS_XSABSQP = 1457 , PPC_INS_XSADDDP = 1458 , PPC_INS_XSADDQP = 1459 , PPC_INS_XSADDQPO = 1460 , PPC_INS_XSADDSP = 1461 , PPC_INS_XSCMPEQDP = 1462 , PPC_INS_XSCMPEXPDP = 1463 , PPC_INS_XSCMPEXPQP = 1464 , PPC_INS_XSCMPGEDP = 1465 , PPC_INS_XSCMPGTDP = 1466 , PPC_INS_XSCMPODP = 1467 , PPC_INS_XSCMPOQP = 1468 , PPC_INS_XSCMPUDP = 1469 , PPC_INS_XSCMPUQP = 1470 , PPC_INS_XSCPSGNDP = 1471 , PPC_INS_XSCPSGNQP = 1472 , PPC_INS_XSCVDPHP = 1473 , PPC_INS_XSCVDPQP = 1474 , PPC_INS_XSCVDPSP = 1475 , PPC_INS_XSCVDPSPN = 1476 , PPC_INS_XSCVDPSXDS = 1477 , PPC_INS_XSCVDPSXWS = 1478 , PPC_INS_XSCVDPUXDS = 1479 , PPC_INS_XSCVDPUXWS = 1480 , PPC_INS_XSCVHPDP = 1481 , PPC_INS_XSCVQPDP = 1482 , PPC_INS_XSCVQPDPO = 1483 , PPC_INS_XSCVQPSDZ = 1484 , PPC_INS_XSCVQPSWZ = 1485 , PPC_INS_XSCVQPUDZ = 1486 , PPC_INS_XSCVQPUWZ = 1487 , PPC_INS_XSCVSDQP = 1488 , PPC_INS_XSCVSPDP = 1489 , PPC_INS_XSCVSPDPN = 1490 , PPC_INS_XSCVSXDDP = 1491 , PPC_INS_XSCVSXDSP = 1492 , PPC_INS_XSCVUDQP = 1493 , PPC_INS_XSCVUXDDP = 1494 , PPC_INS_XSCVUXDSP = 1495 , PPC_INS_XSDIVDP = 1496 , PPC_INS_XSDIVQP = 1497 , PPC_INS_XSDIVQPO = 1498 , PPC_INS_XSDIVSP = 1499 , PPC_INS_XSIEXPDP = 1500 , PPC_INS_XSIEXPQP = 1501 , PPC_INS_XSMADDADP = 1502 , PPC_INS_XSMADDASP = 1503 , PPC_INS_XSMADDMDP = 1504 , PPC_INS_XSMADDMSP = 1505 , PPC_INS_XSMADDQP = 1506 , PPC_INS_XSMADDQPO = 1507 , PPC_INS_XSMAXCDP = 1508 , PPC_INS_XSMAXDP = 1509 , PPC_INS_XSMAXJDP = 1510 , PPC_INS_XSMINCDP = 1511 , PPC_INS_XSMINDP = 1512 , PPC_INS_XSMINJDP = 1513 , PPC_INS_XSMSUBADP = 1514 , PPC_INS_XSMSUBASP = 1515 , PPC_INS_XSMSUBMDP = 1516 , PPC_INS_XSMSUBMSP = 1517 , PPC_INS_XSMSUBQP = 1518 , PPC_INS_XSMSUBQPO = 1519 , PPC_INS_XSMULDP = 1520 , PPC_INS_XSMULQP = 1521 , PPC_INS_XSMULQPO = 1522 , PPC_INS_XSMULSP = 1523 , PPC_INS_XSNABSDP = 1524 , PPC_INS_XSNABSQP = 1525 , PPC_INS_XSNEGDP = 1526 , PPC_INS_XSNEGQP = 1527 , PPC_INS_XSNMADDADP = 1528 , PPC_INS_XSNMADDASP = 1529 , PPC_INS_XSNMADDMDP = 1530 , PPC_INS_XSNMADDMSP = 1531 , PPC_INS_XSNMADDQP = 1532 , PPC_INS_XSNMADDQPO = 1533 , PPC_INS_XSNMSUBADP = 1534 , PPC_INS_XSNMSUBASP = 1535 , PPC_INS_XSNMSUBMDP = 1536 , PPC_INS_XSNMSUBMSP = 1537 , PPC_INS_XSNMSUBQP = 1538 , PPC_INS_XSNMSUBQPO = 1539 , PPC_INS_XSRDPI = 1540 , PPC_INS_XSRDPIC = 1541 , PPC_INS_XSRDPIM = 1542 , PPC_INS_XSRDPIP = 1543 , PPC_INS_XSRDPIZ = 1544 , PPC_INS_XSREDP = 1545 , PPC_INS_XSRESP = 1546 , PPC_INS_XSRQPI = 1547 , PPC_INS_XSRQPIX = 1548 , PPC_INS_XSRQPXP = 1549 , PPC_INS_XSRSP = 1550 , PPC_INS_XSRSQRTEDP = 1551 , PPC_INS_XSRSQRTESP = 1552 , PPC_INS_XSSQRTDP = 1553 , PPC_INS_XSSQRTQP = 1554 , PPC_INS_XSSQRTQPO = 1555 , PPC_INS_XSSQRTSP = 1556 , PPC_INS_XSSUBDP = 1557 , PPC_INS_XSSUBQP = 1558 , PPC_INS_XSSUBQPO = 1559 , PPC_INS_XSSUBSP = 1560 , PPC_INS_XSTDIVDP = 1561 , PPC_INS_XSTSQRTDP = 1562 , PPC_INS_XSTSTDCDP = 1563 , PPC_INS_XSTSTDCQP = 1564 , PPC_INS_XSTSTDCSP = 1565 , PPC_INS_XSXEXPDP = 1566 , PPC_INS_XSXEXPQP = 1567 , PPC_INS_XSXSIGDP = 1568 , PPC_INS_XSXSIGQP = 1569 , PPC_INS_XVABSDP = 1570 , PPC_INS_XVABSSP = 1571 , PPC_INS_XVADDDP = 1572 , PPC_INS_XVADDSP = 1573 , PPC_INS_XVCMPEQDP = 1574 , PPC_INS_XVCMPEQSP = 1575 , PPC_INS_XVCMPGEDP = 1576 , PPC_INS_XVCMPGESP = 1577 , PPC_INS_XVCMPGTDP = 1578 , PPC_INS_XVCMPGTSP = 1579 , PPC_INS_XVCPSGNDP = 1580 , PPC_INS_XVCPSGNSP = 1581 , PPC_INS_XVCVDPSP = 1582 , PPC_INS_XVCVDPSXDS = 1583 , PPC_INS_XVCVDPSXWS = 1584 , PPC_INS_XVCVDPUXDS = 1585 , PPC_INS_XVCVDPUXWS = 1586 , PPC_INS_XVCVHPSP = 1587 , PPC_INS_XVCVSPDP = 1588 , PPC_INS_XVCVSPHP = 1589 , PPC_INS_XVCVSPSXDS = 1590 , PPC_INS_XVCVSPSXWS = 1591 , PPC_INS_XVCVSPUXDS = 1592 , PPC_INS_XVCVSPUXWS = 1593 , PPC_INS_XVCVSXDDP = 1594 , PPC_INS_XVCVSXDSP = 1595 , PPC_INS_XVCVSXWDP = 1596 , PPC_INS_XVCVSXWSP = 1597 , PPC_INS_XVCVUXDDP = 1598 , PPC_INS_XVCVUXDSP = 1599 , PPC_INS_XVCVUXWDP = 1600 , PPC_INS_XVCVUXWSP = 1601 , PPC_INS_XVDIVDP = 1602 , PPC_INS_XVDIVSP = 1603 , PPC_INS_XVIEXPDP = 1604 , PPC_INS_XVIEXPSP = 1605 , PPC_INS_XVMADDADP = 1606 , PPC_INS_XVMADDASP = 1607 , PPC_INS_XVMADDMDP = 1608 , PPC_INS_XVMADDMSP = 1609 , PPC_INS_XVMAXDP = 1610 , PPC_INS_XVMAXSP = 1611 , PPC_INS_XVMINDP = 1612 , PPC_INS_XVMINSP = 1613 , PPC_INS_XVMOVDP = 1614 , PPC_INS_XVMOVSP = 1615 , PPC_INS_XVMSUBADP = 1616 , PPC_INS_XVMSUBASP = 1617 , PPC_INS_XVMSUBMDP = 1618 , PPC_INS_XVMSUBMSP = 1619 , PPC_INS_XVMULDP = 1620 , PPC_INS_XVMULSP = 1621 , PPC_INS_XVNABSDP = 1622 , PPC_INS_XVNABSSP = 1623 , PPC_INS_XVNEGDP = 1624 , PPC_INS_XVNEGSP = 1625 , PPC_INS_XVNMADDADP = 1626 , PPC_INS_XVNMADDASP = 1627 , PPC_INS_XVNMADDMDP = 1628 , PPC_INS_XVNMADDMSP = 1629 , PPC_INS_XVNMSUBADP = 1630 , PPC_INS_XVNMSUBASP = 1631 , PPC_INS_XVNMSUBMDP = 1632 , PPC_INS_XVNMSUBMSP = 1633 , PPC_INS_XVRDPI = 1634 , PPC_INS_XVRDPIC = 1635 , PPC_INS_XVRDPIM = 1636 , PPC_INS_XVRDPIP = 1637 , PPC_INS_XVRDPIZ = 1638 , PPC_INS_XVREDP = 1639 , PPC_INS_XVRESP = 1640 , PPC_INS_XVRSPI = 1641 , PPC_INS_XVRSPIC = 1642 , PPC_INS_XVRSPIM = 1643 , PPC_INS_XVRSPIP = 1644 , PPC_INS_XVRSPIZ = 1645 , PPC_INS_XVRSQRTEDP = 1646 , PPC_INS_XVRSQRTESP = 1647 , PPC_INS_XVSQRTDP = 1648 , PPC_INS_XVSQRTSP = 1649 , PPC_INS_XVSUBDP = 1650 , PPC_INS_XVSUBSP = 1651 , PPC_INS_XVTDIVDP = 1652 , PPC_INS_XVTDIVSP = 1653 , PPC_INS_XVTSQRTDP = 1654 , PPC_INS_XVTSQRTSP = 1655 , PPC_INS_XVTSTDCDP = 1656 , PPC_INS_XVTSTDCSP = 1657 , PPC_INS_XVXEXPDP = 1658 , PPC_INS_XVXEXPSP = 1659 , PPC_INS_XVXSIGDP = 1660 , PPC_INS_XVXSIGSP = 1661 , PPC_INS_XXBRD = 1662 , PPC_INS_XXBRH = 1663 , PPC_INS_XXBRQ = 1664 , PPC_INS_XXBRW = 1665 , PPC_INS_XXEXTRACTUW = 1666 , PPC_INS_XXINSERTW = 1667 , PPC_INS_XXLAND = 1668 , PPC_INS_XXLANDC = 1669 , PPC_INS_XXLEQV = 1670 , PPC_INS_XXLNAND = 1671 , PPC_INS_XXLNOR = 1672 , PPC_INS_XXLOR = 1673 , PPC_INS_XXLORC = 1674 , PPC_INS_XXLXOR = 1675 , PPC_INS_XXMRGHD = 1676 , PPC_INS_XXMRGHW = 1677 , PPC_INS_XXMRGLD = 1678 , PPC_INS_XXMRGLW = 1679 , PPC_INS_XXPERM = 1680 , PPC_INS_XXPERMDI = 1681 , PPC_INS_XXPERMR = 1682 , PPC_INS_XXSEL = 1683 , PPC_INS_XXSLDWI = 1684 , PPC_INS_XXSPLTD = 1685 , PPC_INS_XXSPLTIB = 1686 , PPC_INS_XXSPLTW = 1687 , PPC_INS_XXSWAPD = 1688 , PPC_INS_DCBZ_L = 1689 , PPC_INS_PSQ_L = 1690 , PPC_INS_PSQ_LU = 1691 , PPC_INS_PSQ_LUX = 1692 , PPC_INS_PSQ_LX = 1693 , PPC_INS_PSQ_ST = 1694 , PPC_INS_PSQ_STU = 1695 , PPC_INS_PSQ_STUX = 1696 , PPC_INS_PSQ_STX = 1697 , PPC_INS_PS_ABS = 1698 , PPC_INS_PS_ADD = 1699 , PPC_INS_PS_CMPO0 = 1700 , PPC_INS_PS_CMPO1 = 1701 , PPC_INS_PS_CMPU0 = 1702 , PPC_INS_PS_CMPU1 = 1703 , PPC_INS_PS_DIV = 1704 , PPC_INS_PS_MADD = 1705 , PPC_INS_PS_MADDS0 = 1706 , PPC_INS_PS_MADDS1 = 1707 , PPC_INS_PS_MERGE00 = 1708 , PPC_INS_PS_MERGE01 = 1709 , PPC_INS_PS_MERGE10 = 1710 , PPC_INS_PS_MERGE11 = 1711 , PPC_INS_PS_MR = 1712 , PPC_INS_PS_MSUB = 1713 , PPC_INS_PS_MUL = 1714 , PPC_INS_PS_MULS0 = 1715 , PPC_INS_PS_MULS1 = 1716 , PPC_INS_PS_NABS = 1717 , PPC_INS_PS_NEG = 1718 , PPC_INS_PS_NMADD = 1719 , PPC_INS_PS_NMSUB = 1720 , PPC_INS_PS_RES = 1721 , PPC_INS_PS_RSQRTE = 1722 , PPC_INS_PS_SEL = 1723 , PPC_INS_PS_SUB = 1724 , PPC_INS_PS_SUM0 = 1725 , PPC_INS_PS_SUM1 = 1726 , PPC_INS_ENDING = 1727 , } # [repr (u32)] # [doc = " Group of PPC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn_group { # [doc = "< = CS_GRP_INVALID"] PPC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] PPC_GRP_JUMP = 1 , PPC_GRP_ALTIVEC = 128 , PPC_GRP_MODE32 = 129 , PPC_GRP_MODE64 = 130 , PPC_GRP_BOOKE = 131 , PPC_GRP_NOTBOOKE = 132 , PPC_GRP_SPE = 133 , PPC_GRP_VSX = 134 , PPC_GRP_E500 = 135 , PPC_GRP_PPC4XX = 136 , PPC_GRP_PPC6XX = 137 , PPC_GRP_ICBT = 138 , PPC_GRP_P8ALTIVEC = 139 , PPC_GRP_P8VECTOR = 140 , PPC_GRP_QPX = 141 , PPC_GRP_PS = 142 , PPC_GRP_ENDING = 143 , } # [repr (u32)] # [doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_cc { # [doc = "< invalid CC (default)"] SPARC_CC_INVALID = 0 , # [doc = "< Always"] SPARC_CC_ICC_A = 264 , # [doc = "< Never"] SPARC_CC_ICC_N = 256 , # [doc = "< Not Equal"] SPARC_CC_ICC_NE = 265 , # [doc = "< Equal"] SPARC_CC_ICC_E = 257 , # [doc = "< Greater"] SPARC_CC_ICC_G = 266 , # [doc = "< Less or Equal"] SPARC_CC_ICC_LE = 258 , # [doc = "< Greater or Equal"] SPARC_CC_ICC_GE = 267 , # [doc = "< Less"] SPARC_CC_ICC_L = 259 , # [doc = "< Greater Unsigned"] SPARC_CC_ICC_GU = 268 , # [doc = "< Less or Equal Unsigned"] SPARC_CC_ICC_LEU = 260 , # [doc = "< Carry Clear/Great or Equal Unsigned"] SPARC_CC_ICC_CC = 269 , # [doc = "< Carry Set/Less Unsigned"] SPARC_CC_ICC_CS = 261 , # [doc = "< Positive"] SPARC_CC_ICC_POS = 270 , # [doc = "< Negative"] SPARC_CC_ICC_NEG = 262 , # [doc = "< Overflow Clear"] SPARC_CC_ICC_VC = 271 , # [doc = "< Overflow Set"] SPARC_CC_ICC_VS = 263 , # [doc = "< Always"] SPARC_CC_FCC_A = 280 , # [doc = "< Never"] SPARC_CC_FCC_N = 272 , # [doc = "< Unordered"] SPARC_CC_FCC_U = 279 , # [doc = "< Greater"] SPARC_CC_FCC_G = 278 , # [doc = "< Unordered or Greater"] SPARC_CC_FCC_UG = 277 , # [doc = "< Less"] SPARC_CC_FCC_L = 276 , # [doc = "< Unordered or Less"] SPARC_CC_FCC_UL = 275 , # [doc = "< Less or Greater"] SPARC_CC_FCC_LG = 274 , # [doc = "< Not Equal"] SPARC_CC_FCC_NE = 273 , # [doc = "< Equal"] SPARC_CC_FCC_E = 281 , # [doc = "< Unordered or Equal"] SPARC_CC_FCC_UE = 282 , # [doc = "< Greater or Equal"] SPARC_CC_FCC_GE = 283 , # [doc = "< Unordered or Greater or Equal"] SPARC_CC_FCC_UGE = 284 , # [doc = "< Less or Equal"] SPARC_CC_FCC_LE = 285 , # [doc = "< Unordered or Less or Equal"] SPARC_CC_FCC_ULE = 286 , # [doc = "< Ordered"] SPARC_CC_FCC_O = 287 , } # [repr (u32)] # [doc = " Branch hint"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_hint { # [doc = "< no hint"] SPARC_HINT_INVALID = 0 , # [doc = "< annul delay slot instruction"] SPARC_HINT_A = 1 , # [doc = "< branch taken"] SPARC_HINT_PT = 2 , # [doc = "< branch NOT taken"] SPARC_HINT_PN = 4 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SPARC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SPARC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SPARC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SPARC_OP_MEM = 3 , } impl sparc_reg { pub const SPARC_REG_O6 : sparc_reg = sparc_reg :: SPARC_REG_SP ; } impl sparc_reg { pub const SPARC_REG_I6 : sparc_reg = sparc_reg :: SPARC_REG_FP ; } # [repr (u32)] # [doc = " SPARC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_reg { SPARC_REG_INVALID = 0 , SPARC_REG_F0 = 1 , SPARC_REG_F1 = 2 , SPARC_REG_F2 = 3 , SPARC_REG_F3 = 4 , SPARC_REG_F4 = 5 , SPARC_REG_F5 = 6 , SPARC_REG_F6 = 7 , SPARC_REG_F7 = 8 , SPARC_REG_F8 = 9 , SPARC_REG_F9 = 10 , SPARC_REG_F10 = 11 , SPARC_REG_F11 = 12 , SPARC_REG_F12 = 13 , SPARC_REG_F13 = 14 , SPARC_REG_F14 = 15 , SPARC_REG_F15 = 16 , SPARC_REG_F16 = 17 , SPARC_REG_F17 = 18 , SPARC_REG_F18 = 19 , SPARC_REG_F19 = 20 , SPARC_REG_F20 = 21 , SPARC_REG_F21 = 22 , SPARC_REG_F22 = 23 , SPARC_REG_F23 = 24 , SPARC_REG_F24 = 25 , SPARC_REG_F25 = 26 , SPARC_REG_F26 = 27 , SPARC_REG_F27 = 28 , SPARC_REG_F28 = 29 , SPARC_REG_F29 = 30 , SPARC_REG_F30 = 31 , SPARC_REG_F31 = 32 , SPARC_REG_F32 = 33 , SPARC_REG_F34 = 34 , SPARC_REG_F36 = 35 , SPARC_REG_F38 = 36 , SPARC_REG_F40 = 37 , SPARC_REG_F42 = 38 , SPARC_REG_F44 = 39 , SPARC_REG_F46 = 40 , SPARC_REG_F48 = 41 , SPARC_REG_F50 = 42 , SPARC_REG_F52 = 43 , SPARC_REG_F54 = 44 , SPARC_REG_F56 = 45 , SPARC_REG_F58 = 46 , SPARC_REG_F60 = 47 , SPARC_REG_F62 = 48 , SPARC_REG_FCC0 = 49 , SPARC_REG_FCC1 = 50 , SPARC_REG_FCC2 = 51 , SPARC_REG_FCC3 = 52 , SPARC_REG_FP = 53 , SPARC_REG_G0 = 54 , SPARC_REG_G1 = 55 , SPARC_REG_G2 = 56 , SPARC_REG_G3 = 57 , SPARC_REG_G4 = 58 , SPARC_REG_G5 = 59 , SPARC_REG_G6 = 60 , SPARC_REG_G7 = 61 , SPARC_REG_I0 = 62 , SPARC_REG_I1 = 63 , SPARC_REG_I2 = 64 , SPARC_REG_I3 = 65 , SPARC_REG_I4 = 66 , SPARC_REG_I5 = 67 , SPARC_REG_I7 = 68 , SPARC_REG_ICC = 69 , SPARC_REG_L0 = 70 , SPARC_REG_L1 = 71 , SPARC_REG_L2 = 72 , SPARC_REG_L3 = 73 , SPARC_REG_L4 = 74 , SPARC_REG_L5 = 75 , SPARC_REG_L6 = 76 , SPARC_REG_L7 = 77 , SPARC_REG_O0 = 78 , SPARC_REG_O1 = 79 , SPARC_REG_O2 = 80 , SPARC_REG_O3 = 81 , SPARC_REG_O4 = 82 , SPARC_REG_O5 = 83 , SPARC_REG_O7 = 84 , SPARC_REG_SP = 85 , SPARC_REG_Y = 86 , SPARC_REG_XCC = 87 , SPARC_REG_ENDING = 88 , } # [doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sparc_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sparc_op_mem"] [:: std :: mem :: size_of :: < sparc_op_mem > () - 8usize] ; ["Alignment of sparc_op_mem"] [:: std :: mem :: align_of :: < sparc_op_mem > () - 4usize] ; ["Offset of field: sparc_op_mem::base"] [:: std :: mem :: offset_of ! (sparc_op_mem , base) - 0usize] ; ["Offset of field: sparc_op_mem::index"] [:: std :: mem :: offset_of ! (sparc_op_mem , index) - 1usize] ; ["Offset of field: sparc_op_mem::disp"] [:: std :: mem :: offset_of ! (sparc_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc_op { # [doc = "< operand type"] pub type_ : sparc_op_type , pub __bindgen_anon_1 : cs_sparc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sparc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sparc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sparc_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op"] [:: std :: mem :: size_of :: < cs_sparc_op > () - 16usize] ; ["Alignment of cs_sparc_op"] [:: std :: mem :: align_of :: < cs_sparc_op > () - 8usize] ; ["Offset of field: cs_sparc_op::type_"] [:: std :: mem :: offset_of ! (cs_sparc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc { # [doc = "< code condition for this insn"] pub cc : sparc_cc , # [doc = "< branch hint: encoding as bitwise OR of sparc_hint."] pub hint : sparc_hint , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sparc_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc"] [:: std :: mem :: size_of :: < cs_sparc > () - 80usize] ; ["Alignment of cs_sparc"] [:: std :: mem :: align_of :: < cs_sparc > () - 8usize] ; ["Offset of field: cs_sparc::cc"] [:: std :: mem :: offset_of ! (cs_sparc , cc) - 0usize] ; ["Offset of field: cs_sparc::hint"] [:: std :: mem :: offset_of ! (cs_sparc , hint) - 4usize] ; ["Offset of field: cs_sparc::op_count"] [:: std :: mem :: offset_of ! (cs_sparc , op_count) - 8usize] ; ["Offset of field: cs_sparc::operands"] [:: std :: mem :: offset_of ! (cs_sparc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . hint , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SPARC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn { SPARC_INS_INVALID = 0 , SPARC_INS_ADDCC = 1 , SPARC_INS_ADDX = 2 , SPARC_INS_ADDXCC = 3 , SPARC_INS_ADDXC = 4 , SPARC_INS_ADDXCCC = 5 , SPARC_INS_ADD = 6 , SPARC_INS_ALIGNADDR = 7 , SPARC_INS_ALIGNADDRL = 8 , SPARC_INS_ANDCC = 9 , SPARC_INS_ANDNCC = 10 , SPARC_INS_ANDN = 11 , SPARC_INS_AND = 12 , SPARC_INS_ARRAY16 = 13 , SPARC_INS_ARRAY32 = 14 , SPARC_INS_ARRAY8 = 15 , SPARC_INS_B = 16 , SPARC_INS_JMP = 17 , SPARC_INS_BMASK = 18 , SPARC_INS_FB = 19 , SPARC_INS_BRGEZ = 20 , SPARC_INS_BRGZ = 21 , SPARC_INS_BRLEZ = 22 , SPARC_INS_BRLZ = 23 , SPARC_INS_BRNZ = 24 , SPARC_INS_BRZ = 25 , SPARC_INS_BSHUFFLE = 26 , SPARC_INS_CALL = 27 , SPARC_INS_CASX = 28 , SPARC_INS_CAS = 29 , SPARC_INS_CMASK16 = 30 , SPARC_INS_CMASK32 = 31 , SPARC_INS_CMASK8 = 32 , SPARC_INS_CMP = 33 , SPARC_INS_EDGE16 = 34 , SPARC_INS_EDGE16L = 35 , SPARC_INS_EDGE16LN = 36 , SPARC_INS_EDGE16N = 37 , SPARC_INS_EDGE32 = 38 , SPARC_INS_EDGE32L = 39 , SPARC_INS_EDGE32LN = 40 , SPARC_INS_EDGE32N = 41 , SPARC_INS_EDGE8 = 42 , SPARC_INS_EDGE8L = 43 , SPARC_INS_EDGE8LN = 44 , SPARC_INS_EDGE8N = 45 , SPARC_INS_FABSD = 46 , SPARC_INS_FABSQ = 47 , SPARC_INS_FABSS = 48 , SPARC_INS_FADDD = 49 , SPARC_INS_FADDQ = 50 , SPARC_INS_FADDS = 51 , SPARC_INS_FALIGNDATA = 52 , SPARC_INS_FAND = 53 , SPARC_INS_FANDNOT1 = 54 , SPARC_INS_FANDNOT1S = 55 , SPARC_INS_FANDNOT2 = 56 , SPARC_INS_FANDNOT2S = 57 , SPARC_INS_FANDS = 58 , SPARC_INS_FCHKSM16 = 59 , SPARC_INS_FCMPD = 60 , SPARC_INS_FCMPEQ16 = 61 , SPARC_INS_FCMPEQ32 = 62 , SPARC_INS_FCMPGT16 = 63 , SPARC_INS_FCMPGT32 = 64 , SPARC_INS_FCMPLE16 = 65 , SPARC_INS_FCMPLE32 = 66 , SPARC_INS_FCMPNE16 = 67 , SPARC_INS_FCMPNE32 = 68 , SPARC_INS_FCMPQ = 69 , SPARC_INS_FCMPS = 70 , SPARC_INS_FDIVD = 71 , SPARC_INS_FDIVQ = 72 , SPARC_INS_FDIVS = 73 , SPARC_INS_FDMULQ = 74 , SPARC_INS_FDTOI = 75 , SPARC_INS_FDTOQ = 76 , SPARC_INS_FDTOS = 77 , SPARC_INS_FDTOX = 78 , SPARC_INS_FEXPAND = 79 , SPARC_INS_FHADDD = 80 , SPARC_INS_FHADDS = 81 , SPARC_INS_FHSUBD = 82 , SPARC_INS_FHSUBS = 83 , SPARC_INS_FITOD = 84 , SPARC_INS_FITOQ = 85 , SPARC_INS_FITOS = 86 , SPARC_INS_FLCMPD = 87 , SPARC_INS_FLCMPS = 88 , SPARC_INS_FLUSHW = 89 , SPARC_INS_FMEAN16 = 90 , SPARC_INS_FMOVD = 91 , SPARC_INS_FMOVQ = 92 , SPARC_INS_FMOVRDGEZ = 93 , SPARC_INS_FMOVRQGEZ = 94 , SPARC_INS_FMOVRSGEZ = 95 , SPARC_INS_FMOVRDGZ = 96 , SPARC_INS_FMOVRQGZ = 97 , SPARC_INS_FMOVRSGZ = 98 , SPARC_INS_FMOVRDLEZ = 99 , SPARC_INS_FMOVRQLEZ = 100 , SPARC_INS_FMOVRSLEZ = 101 , SPARC_INS_FMOVRDLZ = 102 , SPARC_INS_FMOVRQLZ = 103 , SPARC_INS_FMOVRSLZ = 104 , SPARC_INS_FMOVRDNZ = 105 , SPARC_INS_FMOVRQNZ = 106 , SPARC_INS_FMOVRSNZ = 107 , SPARC_INS_FMOVRDZ = 108 , SPARC_INS_FMOVRQZ = 109 , SPARC_INS_FMOVRSZ = 110 , SPARC_INS_FMOVS = 111 , SPARC_INS_FMUL8SUX16 = 112 , SPARC_INS_FMUL8ULX16 = 113 , SPARC_INS_FMUL8X16 = 114 , SPARC_INS_FMUL8X16AL = 115 , SPARC_INS_FMUL8X16AU = 116 , SPARC_INS_FMULD = 117 , SPARC_INS_FMULD8SUX16 = 118 , SPARC_INS_FMULD8ULX16 = 119 , SPARC_INS_FMULQ = 120 , SPARC_INS_FMULS = 121 , SPARC_INS_FNADDD = 122 , SPARC_INS_FNADDS = 123 , SPARC_INS_FNAND = 124 , SPARC_INS_FNANDS = 125 , SPARC_INS_FNEGD = 126 , SPARC_INS_FNEGQ = 127 , SPARC_INS_FNEGS = 128 , SPARC_INS_FNHADDD = 129 , SPARC_INS_FNHADDS = 130 , SPARC_INS_FNOR = 131 , SPARC_INS_FNORS = 132 , SPARC_INS_FNOT1 = 133 , SPARC_INS_FNOT1S = 134 , SPARC_INS_FNOT2 = 135 , SPARC_INS_FNOT2S = 136 , SPARC_INS_FONE = 137 , SPARC_INS_FONES = 138 , SPARC_INS_FOR = 139 , SPARC_INS_FORNOT1 = 140 , SPARC_INS_FORNOT1S = 141 , SPARC_INS_FORNOT2 = 142 , SPARC_INS_FORNOT2S = 143 , SPARC_INS_FORS = 144 , SPARC_INS_FPACK16 = 145 , SPARC_INS_FPACK32 = 146 , SPARC_INS_FPACKFIX = 147 , SPARC_INS_FPADD16 = 148 , SPARC_INS_FPADD16S = 149 , SPARC_INS_FPADD32 = 150 , SPARC_INS_FPADD32S = 151 , SPARC_INS_FPADD64 = 152 , SPARC_INS_FPMERGE = 153 , SPARC_INS_FPSUB16 = 154 , SPARC_INS_FPSUB16S = 155 , SPARC_INS_FPSUB32 = 156 , SPARC_INS_FPSUB32S = 157 , SPARC_INS_FQTOD = 158 , SPARC_INS_FQTOI = 159 , SPARC_INS_FQTOS = 160 , SPARC_INS_FQTOX = 161 , SPARC_INS_FSLAS16 = 162 , SPARC_INS_FSLAS32 = 163 , SPARC_INS_FSLL16 = 164 , SPARC_INS_FSLL32 = 165 , SPARC_INS_FSMULD = 166 , SPARC_INS_FSQRTD = 167 , SPARC_INS_FSQRTQ = 168 , SPARC_INS_FSQRTS = 169 , SPARC_INS_FSRA16 = 170 , SPARC_INS_FSRA32 = 171 , SPARC_INS_FSRC1 = 172 , SPARC_INS_FSRC1S = 173 , SPARC_INS_FSRC2 = 174 , SPARC_INS_FSRC2S = 175 , SPARC_INS_FSRL16 = 176 , SPARC_INS_FSRL32 = 177 , SPARC_INS_FSTOD = 178 , SPARC_INS_FSTOI = 179 , SPARC_INS_FSTOQ = 180 , SPARC_INS_FSTOX = 181 , SPARC_INS_FSUBD = 182 , SPARC_INS_FSUBQ = 183 , SPARC_INS_FSUBS = 184 , SPARC_INS_FXNOR = 185 , SPARC_INS_FXNORS = 186 , SPARC_INS_FXOR = 187 , SPARC_INS_FXORS = 188 , SPARC_INS_FXTOD = 189 , SPARC_INS_FXTOQ = 190 , SPARC_INS_FXTOS = 191 , SPARC_INS_FZERO = 192 , SPARC_INS_FZEROS = 193 , SPARC_INS_JMPL = 194 , SPARC_INS_LDD = 195 , SPARC_INS_LD = 196 , SPARC_INS_LDQ = 197 , SPARC_INS_LDSB = 198 , SPARC_INS_LDSH = 199 , SPARC_INS_LDSW = 200 , SPARC_INS_LDUB = 201 , SPARC_INS_LDUH = 202 , SPARC_INS_LDX = 203 , SPARC_INS_LZCNT = 204 , SPARC_INS_MEMBAR = 205 , SPARC_INS_MOVDTOX = 206 , SPARC_INS_MOV = 207 , SPARC_INS_MOVRGEZ = 208 , SPARC_INS_MOVRGZ = 209 , SPARC_INS_MOVRLEZ = 210 , SPARC_INS_MOVRLZ = 211 , SPARC_INS_MOVRNZ = 212 , SPARC_INS_MOVRZ = 213 , SPARC_INS_MOVSTOSW = 214 , SPARC_INS_MOVSTOUW = 215 , SPARC_INS_MULX = 216 , SPARC_INS_NOP = 217 , SPARC_INS_ORCC = 218 , SPARC_INS_ORNCC = 219 , SPARC_INS_ORN = 220 , SPARC_INS_OR = 221 , SPARC_INS_PDIST = 222 , SPARC_INS_PDISTN = 223 , SPARC_INS_POPC = 224 , SPARC_INS_RD = 225 , SPARC_INS_RESTORE = 226 , SPARC_INS_RETT = 227 , SPARC_INS_SAVE = 228 , SPARC_INS_SDIVCC = 229 , SPARC_INS_SDIVX = 230 , SPARC_INS_SDIV = 231 , SPARC_INS_SETHI = 232 , SPARC_INS_SHUTDOWN = 233 , SPARC_INS_SIAM = 234 , SPARC_INS_SLLX = 235 , SPARC_INS_SLL = 236 , SPARC_INS_SMULCC = 237 , SPARC_INS_SMUL = 238 , SPARC_INS_SRAX = 239 , SPARC_INS_SRA = 240 , SPARC_INS_SRLX = 241 , SPARC_INS_SRL = 242 , SPARC_INS_STBAR = 243 , SPARC_INS_STB = 244 , SPARC_INS_STD = 245 , SPARC_INS_ST = 246 , SPARC_INS_STH = 247 , SPARC_INS_STQ = 248 , SPARC_INS_STX = 249 , SPARC_INS_SUBCC = 250 , SPARC_INS_SUBX = 251 , SPARC_INS_SUBXCC = 252 , SPARC_INS_SUB = 253 , SPARC_INS_SWAP = 254 , SPARC_INS_TADDCCTV = 255 , SPARC_INS_TADDCC = 256 , SPARC_INS_T = 257 , SPARC_INS_TSUBCCTV = 258 , SPARC_INS_TSUBCC = 259 , SPARC_INS_UDIVCC = 260 , SPARC_INS_UDIVX = 261 , SPARC_INS_UDIV = 262 , SPARC_INS_UMULCC = 263 , SPARC_INS_UMULXHI = 264 , SPARC_INS_UMUL = 265 , SPARC_INS_UNIMP = 266 , SPARC_INS_FCMPED = 267 , SPARC_INS_FCMPEQ = 268 , SPARC_INS_FCMPES = 269 , SPARC_INS_WR = 270 , SPARC_INS_XMULX = 271 , SPARC_INS_XMULXHI = 272 , SPARC_INS_XNORCC = 273 , SPARC_INS_XNOR = 274 , SPARC_INS_XORCC = 275 , SPARC_INS_XOR = 276 , SPARC_INS_RET = 277 , SPARC_INS_RETL = 278 , SPARC_INS_ENDING = 279 , } # [repr (u32)] # [doc = " Group of SPARC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn_group { # [doc = "< = CS_GRP_INVALID"] SPARC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SPARC_GRP_JUMP = 1 , SPARC_GRP_HARDQUAD = 128 , SPARC_GRP_V9 = 129 , SPARC_GRP_VIS = 130 , SPARC_GRP_VIS2 = 131 , SPARC_GRP_VIS3 = 132 , SPARC_GRP_32BIT = 133 , SPARC_GRP_64BIT = 134 , SPARC_GRP_ENDING = 135 , } # [repr (u32)] # [doc = " Enums corresponding to SystemZ condition codes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_cc { # [doc = "< invalid CC (default)"] SYSZ_CC_INVALID = 0 , SYSZ_CC_O = 1 , SYSZ_CC_H = 2 , SYSZ_CC_NLE = 3 , SYSZ_CC_L = 4 , SYSZ_CC_NHE = 5 , SYSZ_CC_LH = 6 , SYSZ_CC_NE = 7 , SYSZ_CC_E = 8 , SYSZ_CC_NLH = 9 , SYSZ_CC_HE = 10 , SYSZ_CC_NL = 11 , SYSZ_CC_LE = 12 , SYSZ_CC_NH = 13 , SYSZ_CC_NO = 14 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SYSZ_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SYSZ_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SYSZ_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SYSZ_OP_MEM = 3 , # [doc = "< Access register operand."] SYSZ_OP_ACREG = 64 , } # [repr (u32)] # [doc = " SystemZ registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_reg { SYSZ_REG_INVALID = 0 , SYSZ_REG_0 = 1 , SYSZ_REG_1 = 2 , SYSZ_REG_2 = 3 , SYSZ_REG_3 = 4 , SYSZ_REG_4 = 5 , SYSZ_REG_5 = 6 , SYSZ_REG_6 = 7 , SYSZ_REG_7 = 8 , SYSZ_REG_8 = 9 , SYSZ_REG_9 = 10 , SYSZ_REG_10 = 11 , SYSZ_REG_11 = 12 , SYSZ_REG_12 = 13 , SYSZ_REG_13 = 14 , SYSZ_REG_14 = 15 , SYSZ_REG_15 = 16 , SYSZ_REG_CC = 17 , SYSZ_REG_F0 = 18 , SYSZ_REG_F1 = 19 , SYSZ_REG_F2 = 20 , SYSZ_REG_F3 = 21 , SYSZ_REG_F4 = 22 , SYSZ_REG_F5 = 23 , SYSZ_REG_F6 = 24 , SYSZ_REG_F7 = 25 , SYSZ_REG_F8 = 26 , SYSZ_REG_F9 = 27 , SYSZ_REG_F10 = 28 , SYSZ_REG_F11 = 29 , SYSZ_REG_F12 = 30 , SYSZ_REG_F13 = 31 , SYSZ_REG_F14 = 32 , SYSZ_REG_F15 = 33 , SYSZ_REG_R0L = 34 , SYSZ_REG_A0 = 35 , SYSZ_REG_A1 = 36 , SYSZ_REG_A2 = 37 , SYSZ_REG_A3 = 38 , SYSZ_REG_A4 = 39 , SYSZ_REG_A5 = 40 , SYSZ_REG_A6 = 41 , SYSZ_REG_A7 = 42 , SYSZ_REG_A8 = 43 , SYSZ_REG_A9 = 44 , SYSZ_REG_A10 = 45 , SYSZ_REG_A11 = 46 , SYSZ_REG_A12 = 47 , SYSZ_REG_A13 = 48 , SYSZ_REG_A14 = 49 , SYSZ_REG_A15 = 50 , SYSZ_REG_C0 = 51 , SYSZ_REG_C1 = 52 , SYSZ_REG_C2 = 53 , SYSZ_REG_C3 = 54 , SYSZ_REG_C4 = 55 , SYSZ_REG_C5 = 56 , SYSZ_REG_C6 = 57 , SYSZ_REG_C7 = 58 , SYSZ_REG_C8 = 59 , SYSZ_REG_C9 = 60 , SYSZ_REG_C10 = 61 , SYSZ_REG_C11 = 62 , SYSZ_REG_C12 = 63 , SYSZ_REG_C13 = 64 , SYSZ_REG_C14 = 65 , SYSZ_REG_C15 = 66 , SYSZ_REG_V0 = 67 , SYSZ_REG_V1 = 68 , SYSZ_REG_V2 = 69 , SYSZ_REG_V3 = 70 , SYSZ_REG_V4 = 71 , SYSZ_REG_V5 = 72 , SYSZ_REG_V6 = 73 , SYSZ_REG_V7 = 74 , SYSZ_REG_V8 = 75 , SYSZ_REG_V9 = 76 , SYSZ_REG_V10 = 77 , SYSZ_REG_V11 = 78 , SYSZ_REG_V12 = 79 , SYSZ_REG_V13 = 80 , SYSZ_REG_V14 = 81 , SYSZ_REG_V15 = 82 , SYSZ_REG_V16 = 83 , SYSZ_REG_V17 = 84 , SYSZ_REG_V18 = 85 , SYSZ_REG_V19 = 86 , SYSZ_REG_V20 = 87 , SYSZ_REG_V21 = 88 , SYSZ_REG_V22 = 89 , SYSZ_REG_V23 = 90 , SYSZ_REG_V24 = 91 , SYSZ_REG_V25 = 92 , SYSZ_REG_V26 = 93 , SYSZ_REG_V27 = 94 , SYSZ_REG_V28 = 95 , SYSZ_REG_V29 = 96 , SYSZ_REG_V30 = 97 , SYSZ_REG_V31 = 98 , SYSZ_REG_F16 = 99 , SYSZ_REG_F17 = 100 , SYSZ_REG_F18 = 101 , SYSZ_REG_F19 = 102 , SYSZ_REG_F20 = 103 , SYSZ_REG_F21 = 104 , SYSZ_REG_F22 = 105 , SYSZ_REG_F23 = 106 , SYSZ_REG_F24 = 107 , SYSZ_REG_F25 = 108 , SYSZ_REG_F26 = 109 , SYSZ_REG_F27 = 110 , SYSZ_REG_F28 = 111 , SYSZ_REG_F29 = 112 , SYSZ_REG_F30 = 113 , SYSZ_REG_F31 = 114 , SYSZ_REG_F0Q = 115 , SYSZ_REG_F4Q = 116 , SYSZ_REG_ENDING = 117 , } # [doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sysz_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< BDLAddr operand"] pub length : u64 , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sysz_op_mem"] [:: std :: mem :: size_of :: < sysz_op_mem > () - 24usize] ; ["Alignment of sysz_op_mem"] [:: std :: mem :: align_of :: < sysz_op_mem > () - 8usize] ; ["Offset of field: sysz_op_mem::base"] [:: std :: mem :: offset_of ! (sysz_op_mem , base) - 0usize] ; ["Offset of field: sysz_op_mem::index"] [:: std :: mem :: offset_of ! (sysz_op_mem , index) - 1usize] ; ["Offset of field: sysz_op_mem::length"] [:: std :: mem :: offset_of ! (sysz_op_mem , length) - 8usize] ; ["Offset of field: sysz_op_mem::disp"] [:: std :: mem :: offset_of ! (sysz_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz_op { # [doc = "< operand type"] pub type_ : sysz_op_type , pub __bindgen_anon_1 : cs_sysz_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sysz_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sysz_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sysz_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sysz_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sysz_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op"] [:: std :: mem :: size_of :: < cs_sysz_op > () - 32usize] ; ["Alignment of cs_sysz_op"] [:: std :: mem :: align_of :: < cs_sysz_op > () - 8usize] ; ["Offset of field: cs_sysz_op::type_"] [:: std :: mem :: offset_of ! (cs_sysz_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz { # [doc = "< Code condition"] pub cc : sysz_cc , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sysz_op ; 6usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz"] [:: std :: mem :: size_of :: < cs_sysz > () - 200usize] ; ["Alignment of cs_sysz"] [:: std :: mem :: align_of :: < cs_sysz > () - 8usize] ; ["Offset of field: cs_sysz::cc"] [:: std :: mem :: offset_of ! (cs_sysz , cc) - 0usize] ; ["Offset of field: cs_sysz::op_count"] [:: std :: mem :: offset_of ! (cs_sysz , op_count) - 4usize] ; ["Offset of field: cs_sysz::operands"] [:: std :: mem :: offset_of ! (cs_sysz , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SystemZ instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn { SYSZ_INS_INVALID = 0 , SYSZ_INS_A = 1 , SYSZ_INS_ADB = 2 , SYSZ_INS_ADBR = 3 , SYSZ_INS_AEB = 4 , SYSZ_INS_AEBR = 5 , SYSZ_INS_AFI = 6 , SYSZ_INS_AG = 7 , SYSZ_INS_AGF = 8 , SYSZ_INS_AGFI = 9 , SYSZ_INS_AGFR = 10 , SYSZ_INS_AGHI = 11 , SYSZ_INS_AGHIK = 12 , SYSZ_INS_AGR = 13 , SYSZ_INS_AGRK = 14 , SYSZ_INS_AGSI = 15 , SYSZ_INS_AH = 16 , SYSZ_INS_AHI = 17 , SYSZ_INS_AHIK = 18 , SYSZ_INS_AHY = 19 , SYSZ_INS_AIH = 20 , SYSZ_INS_AL = 21 , SYSZ_INS_ALC = 22 , SYSZ_INS_ALCG = 23 , SYSZ_INS_ALCGR = 24 , SYSZ_INS_ALCR = 25 , SYSZ_INS_ALFI = 26 , SYSZ_INS_ALG = 27 , SYSZ_INS_ALGF = 28 , SYSZ_INS_ALGFI = 29 , SYSZ_INS_ALGFR = 30 , SYSZ_INS_ALGHSIK = 31 , SYSZ_INS_ALGR = 32 , SYSZ_INS_ALGRK = 33 , SYSZ_INS_ALHSIK = 34 , SYSZ_INS_ALR = 35 , SYSZ_INS_ALRK = 36 , SYSZ_INS_ALY = 37 , SYSZ_INS_AR = 38 , SYSZ_INS_ARK = 39 , SYSZ_INS_ASI = 40 , SYSZ_INS_AXBR = 41 , SYSZ_INS_AY = 42 , SYSZ_INS_BCR = 43 , SYSZ_INS_BRC = 44 , SYSZ_INS_BRCL = 45 , SYSZ_INS_CGIJ = 46 , SYSZ_INS_CGRJ = 47 , SYSZ_INS_CIJ = 48 , SYSZ_INS_CLGIJ = 49 , SYSZ_INS_CLGRJ = 50 , SYSZ_INS_CLIJ = 51 , SYSZ_INS_CLRJ = 52 , SYSZ_INS_CRJ = 53 , SYSZ_INS_BER = 54 , SYSZ_INS_JE = 55 , SYSZ_INS_JGE = 56 , SYSZ_INS_LOCE = 57 , SYSZ_INS_LOCGE = 58 , SYSZ_INS_LOCGRE = 59 , SYSZ_INS_LOCRE = 60 , SYSZ_INS_STOCE = 61 , SYSZ_INS_STOCGE = 62 , SYSZ_INS_BHR = 63 , SYSZ_INS_BHER = 64 , SYSZ_INS_JHE = 65 , SYSZ_INS_JGHE = 66 , SYSZ_INS_LOCHE = 67 , SYSZ_INS_LOCGHE = 68 , SYSZ_INS_LOCGRHE = 69 , SYSZ_INS_LOCRHE = 70 , SYSZ_INS_STOCHE = 71 , SYSZ_INS_STOCGHE = 72 , SYSZ_INS_JH = 73 , SYSZ_INS_JGH = 74 , SYSZ_INS_LOCH = 75 , SYSZ_INS_LOCGH = 76 , SYSZ_INS_LOCGRH = 77 , SYSZ_INS_LOCRH = 78 , SYSZ_INS_STOCH = 79 , SYSZ_INS_STOCGH = 80 , SYSZ_INS_CGIJNLH = 81 , SYSZ_INS_CGRJNLH = 82 , SYSZ_INS_CIJNLH = 83 , SYSZ_INS_CLGIJNLH = 84 , SYSZ_INS_CLGRJNLH = 85 , SYSZ_INS_CLIJNLH = 86 , SYSZ_INS_CLRJNLH = 87 , SYSZ_INS_CRJNLH = 88 , SYSZ_INS_CGIJE = 89 , SYSZ_INS_CGRJE = 90 , SYSZ_INS_CIJE = 91 , SYSZ_INS_CLGIJE = 92 , SYSZ_INS_CLGRJE = 93 , SYSZ_INS_CLIJE = 94 , SYSZ_INS_CLRJE = 95 , SYSZ_INS_CRJE = 96 , SYSZ_INS_CGIJNLE = 97 , SYSZ_INS_CGRJNLE = 98 , SYSZ_INS_CIJNLE = 99 , SYSZ_INS_CLGIJNLE = 100 , SYSZ_INS_CLGRJNLE = 101 , SYSZ_INS_CLIJNLE = 102 , SYSZ_INS_CLRJNLE = 103 , SYSZ_INS_CRJNLE = 104 , SYSZ_INS_CGIJH = 105 , SYSZ_INS_CGRJH = 106 , SYSZ_INS_CIJH = 107 , SYSZ_INS_CLGIJH = 108 , SYSZ_INS_CLGRJH = 109 , SYSZ_INS_CLIJH = 110 , SYSZ_INS_CLRJH = 111 , SYSZ_INS_CRJH = 112 , SYSZ_INS_CGIJNL = 113 , SYSZ_INS_CGRJNL = 114 , SYSZ_INS_CIJNL = 115 , SYSZ_INS_CLGIJNL = 116 , SYSZ_INS_CLGRJNL = 117 , SYSZ_INS_CLIJNL = 118 , SYSZ_INS_CLRJNL = 119 , SYSZ_INS_CRJNL = 120 , SYSZ_INS_CGIJHE = 121 , SYSZ_INS_CGRJHE = 122 , SYSZ_INS_CIJHE = 123 , SYSZ_INS_CLGIJHE = 124 , SYSZ_INS_CLGRJHE = 125 , SYSZ_INS_CLIJHE = 126 , SYSZ_INS_CLRJHE = 127 , SYSZ_INS_CRJHE = 128 , SYSZ_INS_CGIJNHE = 129 , SYSZ_INS_CGRJNHE = 130 , SYSZ_INS_CIJNHE = 131 , SYSZ_INS_CLGIJNHE = 132 , SYSZ_INS_CLGRJNHE = 133 , SYSZ_INS_CLIJNHE = 134 , SYSZ_INS_CLRJNHE = 135 , SYSZ_INS_CRJNHE = 136 , SYSZ_INS_CGIJL = 137 , SYSZ_INS_CGRJL = 138 , SYSZ_INS_CIJL = 139 , SYSZ_INS_CLGIJL = 140 , SYSZ_INS_CLGRJL = 141 , SYSZ_INS_CLIJL = 142 , SYSZ_INS_CLRJL = 143 , SYSZ_INS_CRJL = 144 , SYSZ_INS_CGIJNH = 145 , SYSZ_INS_CGRJNH = 146 , SYSZ_INS_CIJNH = 147 , SYSZ_INS_CLGIJNH = 148 , SYSZ_INS_CLGRJNH = 149 , SYSZ_INS_CLIJNH = 150 , SYSZ_INS_CLRJNH = 151 , SYSZ_INS_CRJNH = 152 , SYSZ_INS_CGIJLE = 153 , SYSZ_INS_CGRJLE = 154 , SYSZ_INS_CIJLE = 155 , SYSZ_INS_CLGIJLE = 156 , SYSZ_INS_CLGRJLE = 157 , SYSZ_INS_CLIJLE = 158 , SYSZ_INS_CLRJLE = 159 , SYSZ_INS_CRJLE = 160 , SYSZ_INS_CGIJNE = 161 , SYSZ_INS_CGRJNE = 162 , SYSZ_INS_CIJNE = 163 , SYSZ_INS_CLGIJNE = 164 , SYSZ_INS_CLGRJNE = 165 , SYSZ_INS_CLIJNE = 166 , SYSZ_INS_CLRJNE = 167 , SYSZ_INS_CRJNE = 168 , SYSZ_INS_CGIJLH = 169 , SYSZ_INS_CGRJLH = 170 , SYSZ_INS_CIJLH = 171 , SYSZ_INS_CLGIJLH = 172 , SYSZ_INS_CLGRJLH = 173 , SYSZ_INS_CLIJLH = 174 , SYSZ_INS_CLRJLH = 175 , SYSZ_INS_CRJLH = 176 , SYSZ_INS_BLR = 177 , SYSZ_INS_BLER = 178 , SYSZ_INS_JLE = 179 , SYSZ_INS_JGLE = 180 , SYSZ_INS_LOCLE = 181 , SYSZ_INS_LOCGLE = 182 , SYSZ_INS_LOCGRLE = 183 , SYSZ_INS_LOCRLE = 184 , SYSZ_INS_STOCLE = 185 , SYSZ_INS_STOCGLE = 186 , SYSZ_INS_BLHR = 187 , SYSZ_INS_JLH = 188 , SYSZ_INS_JGLH = 189 , SYSZ_INS_LOCLH = 190 , SYSZ_INS_LOCGLH = 191 , SYSZ_INS_LOCGRLH = 192 , SYSZ_INS_LOCRLH = 193 , SYSZ_INS_STOCLH = 194 , SYSZ_INS_STOCGLH = 195 , SYSZ_INS_JL = 196 , SYSZ_INS_JGL = 197 , SYSZ_INS_LOCL = 198 , SYSZ_INS_LOCGL = 199 , SYSZ_INS_LOCGRL = 200 , SYSZ_INS_LOCRL = 201 , SYSZ_INS_LOC = 202 , SYSZ_INS_LOCG = 203 , SYSZ_INS_LOCGR = 204 , SYSZ_INS_LOCR = 205 , SYSZ_INS_STOCL = 206 , SYSZ_INS_STOCGL = 207 , SYSZ_INS_BNER = 208 , SYSZ_INS_JNE = 209 , SYSZ_INS_JGNE = 210 , SYSZ_INS_LOCNE = 211 , SYSZ_INS_LOCGNE = 212 , SYSZ_INS_LOCGRNE = 213 , SYSZ_INS_LOCRNE = 214 , SYSZ_INS_STOCNE = 215 , SYSZ_INS_STOCGNE = 216 , SYSZ_INS_BNHR = 217 , SYSZ_INS_BNHER = 218 , SYSZ_INS_JNHE = 219 , SYSZ_INS_JGNHE = 220 , SYSZ_INS_LOCNHE = 221 , SYSZ_INS_LOCGNHE = 222 , SYSZ_INS_LOCGRNHE = 223 , SYSZ_INS_LOCRNHE = 224 , SYSZ_INS_STOCNHE = 225 , SYSZ_INS_STOCGNHE = 226 , SYSZ_INS_JNH = 227 , SYSZ_INS_JGNH = 228 , SYSZ_INS_LOCNH = 229 , SYSZ_INS_LOCGNH = 230 , SYSZ_INS_LOCGRNH = 231 , SYSZ_INS_LOCRNH = 232 , SYSZ_INS_STOCNH = 233 , SYSZ_INS_STOCGNH = 234 , SYSZ_INS_BNLR = 235 , SYSZ_INS_BNLER = 236 , SYSZ_INS_JNLE = 237 , SYSZ_INS_JGNLE = 238 , SYSZ_INS_LOCNLE = 239 , SYSZ_INS_LOCGNLE = 240 , SYSZ_INS_LOCGRNLE = 241 , SYSZ_INS_LOCRNLE = 242 , SYSZ_INS_STOCNLE = 243 , SYSZ_INS_STOCGNLE = 244 , SYSZ_INS_BNLHR = 245 , SYSZ_INS_JNLH = 246 , SYSZ_INS_JGNLH = 247 , SYSZ_INS_LOCNLH = 248 , SYSZ_INS_LOCGNLH = 249 , SYSZ_INS_LOCGRNLH = 250 , SYSZ_INS_LOCRNLH = 251 , SYSZ_INS_STOCNLH = 252 , SYSZ_INS_STOCGNLH = 253 , SYSZ_INS_JNL = 254 , SYSZ_INS_JGNL = 255 , SYSZ_INS_LOCNL = 256 , SYSZ_INS_LOCGNL = 257 , SYSZ_INS_LOCGRNL = 258 , SYSZ_INS_LOCRNL = 259 , SYSZ_INS_STOCNL = 260 , SYSZ_INS_STOCGNL = 261 , SYSZ_INS_BNOR = 262 , SYSZ_INS_JNO = 263 , SYSZ_INS_JGNO = 264 , SYSZ_INS_LOCNO = 265 , SYSZ_INS_LOCGNO = 266 , SYSZ_INS_LOCGRNO = 267 , SYSZ_INS_LOCRNO = 268 , SYSZ_INS_STOCNO = 269 , SYSZ_INS_STOCGNO = 270 , SYSZ_INS_BOR = 271 , SYSZ_INS_JO = 272 , SYSZ_INS_JGO = 273 , SYSZ_INS_LOCO = 274 , SYSZ_INS_LOCGO = 275 , SYSZ_INS_LOCGRO = 276 , SYSZ_INS_LOCRO = 277 , SYSZ_INS_STOCO = 278 , SYSZ_INS_STOCGO = 279 , SYSZ_INS_STOC = 280 , SYSZ_INS_STOCG = 281 , SYSZ_INS_BASR = 282 , SYSZ_INS_BR = 283 , SYSZ_INS_BRAS = 284 , SYSZ_INS_BRASL = 285 , SYSZ_INS_J = 286 , SYSZ_INS_JG = 287 , SYSZ_INS_BRCT = 288 , SYSZ_INS_BRCTG = 289 , SYSZ_INS_C = 290 , SYSZ_INS_CDB = 291 , SYSZ_INS_CDBR = 292 , SYSZ_INS_CDFBR = 293 , SYSZ_INS_CDGBR = 294 , SYSZ_INS_CDLFBR = 295 , SYSZ_INS_CDLGBR = 296 , SYSZ_INS_CEB = 297 , SYSZ_INS_CEBR = 298 , SYSZ_INS_CEFBR = 299 , SYSZ_INS_CEGBR = 300 , SYSZ_INS_CELFBR = 301 , SYSZ_INS_CELGBR = 302 , SYSZ_INS_CFDBR = 303 , SYSZ_INS_CFEBR = 304 , SYSZ_INS_CFI = 305 , SYSZ_INS_CFXBR = 306 , SYSZ_INS_CG = 307 , SYSZ_INS_CGDBR = 308 , SYSZ_INS_CGEBR = 309 , SYSZ_INS_CGF = 310 , SYSZ_INS_CGFI = 311 , SYSZ_INS_CGFR = 312 , SYSZ_INS_CGFRL = 313 , SYSZ_INS_CGH = 314 , SYSZ_INS_CGHI = 315 , SYSZ_INS_CGHRL = 316 , SYSZ_INS_CGHSI = 317 , SYSZ_INS_CGR = 318 , SYSZ_INS_CGRL = 319 , SYSZ_INS_CGXBR = 320 , SYSZ_INS_CH = 321 , SYSZ_INS_CHF = 322 , SYSZ_INS_CHHSI = 323 , SYSZ_INS_CHI = 324 , SYSZ_INS_CHRL = 325 , SYSZ_INS_CHSI = 326 , SYSZ_INS_CHY = 327 , SYSZ_INS_CIH = 328 , SYSZ_INS_CL = 329 , SYSZ_INS_CLC = 330 , SYSZ_INS_CLFDBR = 331 , SYSZ_INS_CLFEBR = 332 , SYSZ_INS_CLFHSI = 333 , SYSZ_INS_CLFI = 334 , SYSZ_INS_CLFXBR = 335 , SYSZ_INS_CLG = 336 , SYSZ_INS_CLGDBR = 337 , SYSZ_INS_CLGEBR = 338 , SYSZ_INS_CLGF = 339 , SYSZ_INS_CLGFI = 340 , SYSZ_INS_CLGFR = 341 , SYSZ_INS_CLGFRL = 342 , SYSZ_INS_CLGHRL = 343 , SYSZ_INS_CLGHSI = 344 , SYSZ_INS_CLGR = 345 , SYSZ_INS_CLGRL = 346 , SYSZ_INS_CLGXBR = 347 , SYSZ_INS_CLHF = 348 , SYSZ_INS_CLHHSI = 349 , SYSZ_INS_CLHRL = 350 , SYSZ_INS_CLI = 351 , SYSZ_INS_CLIH = 352 , SYSZ_INS_CLIY = 353 , SYSZ_INS_CLR = 354 , SYSZ_INS_CLRL = 355 , SYSZ_INS_CLST = 356 , SYSZ_INS_CLY = 357 , SYSZ_INS_CPSDR = 358 , SYSZ_INS_CR = 359 , SYSZ_INS_CRL = 360 , SYSZ_INS_CS = 361 , SYSZ_INS_CSG = 362 , SYSZ_INS_CSY = 363 , SYSZ_INS_CXBR = 364 , SYSZ_INS_CXFBR = 365 , SYSZ_INS_CXGBR = 366 , SYSZ_INS_CXLFBR = 367 , SYSZ_INS_CXLGBR = 368 , SYSZ_INS_CY = 369 , SYSZ_INS_DDB = 370 , SYSZ_INS_DDBR = 371 , SYSZ_INS_DEB = 372 , SYSZ_INS_DEBR = 373 , SYSZ_INS_DL = 374 , SYSZ_INS_DLG = 375 , SYSZ_INS_DLGR = 376 , SYSZ_INS_DLR = 377 , SYSZ_INS_DSG = 378 , SYSZ_INS_DSGF = 379 , SYSZ_INS_DSGFR = 380 , SYSZ_INS_DSGR = 381 , SYSZ_INS_DXBR = 382 , SYSZ_INS_EAR = 383 , SYSZ_INS_FIDBR = 384 , SYSZ_INS_FIDBRA = 385 , SYSZ_INS_FIEBR = 386 , SYSZ_INS_FIEBRA = 387 , SYSZ_INS_FIXBR = 388 , SYSZ_INS_FIXBRA = 389 , SYSZ_INS_FLOGR = 390 , SYSZ_INS_IC = 391 , SYSZ_INS_ICY = 392 , SYSZ_INS_IIHF = 393 , SYSZ_INS_IIHH = 394 , SYSZ_INS_IIHL = 395 , SYSZ_INS_IILF = 396 , SYSZ_INS_IILH = 397 , SYSZ_INS_IILL = 398 , SYSZ_INS_IPM = 399 , SYSZ_INS_L = 400 , SYSZ_INS_LA = 401 , SYSZ_INS_LAA = 402 , SYSZ_INS_LAAG = 403 , SYSZ_INS_LAAL = 404 , SYSZ_INS_LAALG = 405 , SYSZ_INS_LAN = 406 , SYSZ_INS_LANG = 407 , SYSZ_INS_LAO = 408 , SYSZ_INS_LAOG = 409 , SYSZ_INS_LARL = 410 , SYSZ_INS_LAX = 411 , SYSZ_INS_LAXG = 412 , SYSZ_INS_LAY = 413 , SYSZ_INS_LB = 414 , SYSZ_INS_LBH = 415 , SYSZ_INS_LBR = 416 , SYSZ_INS_LCDBR = 417 , SYSZ_INS_LCEBR = 418 , SYSZ_INS_LCGFR = 419 , SYSZ_INS_LCGR = 420 , SYSZ_INS_LCR = 421 , SYSZ_INS_LCXBR = 422 , SYSZ_INS_LD = 423 , SYSZ_INS_LDEB = 424 , SYSZ_INS_LDEBR = 425 , SYSZ_INS_LDGR = 426 , SYSZ_INS_LDR = 427 , SYSZ_INS_LDXBR = 428 , SYSZ_INS_LDXBRA = 429 , SYSZ_INS_LDY = 430 , SYSZ_INS_LE = 431 , SYSZ_INS_LEDBR = 432 , SYSZ_INS_LEDBRA = 433 , SYSZ_INS_LER = 434 , SYSZ_INS_LEXBR = 435 , SYSZ_INS_LEXBRA = 436 , SYSZ_INS_LEY = 437 , SYSZ_INS_LFH = 438 , SYSZ_INS_LG = 439 , SYSZ_INS_LGB = 440 , SYSZ_INS_LGBR = 441 , SYSZ_INS_LGDR = 442 , SYSZ_INS_LGF = 443 , SYSZ_INS_LGFI = 444 , SYSZ_INS_LGFR = 445 , SYSZ_INS_LGFRL = 446 , SYSZ_INS_LGH = 447 , SYSZ_INS_LGHI = 448 , SYSZ_INS_LGHR = 449 , SYSZ_INS_LGHRL = 450 , SYSZ_INS_LGR = 451 , SYSZ_INS_LGRL = 452 , SYSZ_INS_LH = 453 , SYSZ_INS_LHH = 454 , SYSZ_INS_LHI = 455 , SYSZ_INS_LHR = 456 , SYSZ_INS_LHRL = 457 , SYSZ_INS_LHY = 458 , SYSZ_INS_LLC = 459 , SYSZ_INS_LLCH = 460 , SYSZ_INS_LLCR = 461 , SYSZ_INS_LLGC = 462 , SYSZ_INS_LLGCR = 463 , SYSZ_INS_LLGF = 464 , SYSZ_INS_LLGFR = 465 , SYSZ_INS_LLGFRL = 466 , SYSZ_INS_LLGH = 467 , SYSZ_INS_LLGHR = 468 , SYSZ_INS_LLGHRL = 469 , SYSZ_INS_LLH = 470 , SYSZ_INS_LLHH = 471 , SYSZ_INS_LLHR = 472 , SYSZ_INS_LLHRL = 473 , SYSZ_INS_LLIHF = 474 , SYSZ_INS_LLIHH = 475 , SYSZ_INS_LLIHL = 476 , SYSZ_INS_LLILF = 477 , SYSZ_INS_LLILH = 478 , SYSZ_INS_LLILL = 479 , SYSZ_INS_LMG = 480 , SYSZ_INS_LNDBR = 481 , SYSZ_INS_LNEBR = 482 , SYSZ_INS_LNGFR = 483 , SYSZ_INS_LNGR = 484 , SYSZ_INS_LNR = 485 , SYSZ_INS_LNXBR = 486 , SYSZ_INS_LPDBR = 487 , SYSZ_INS_LPEBR = 488 , SYSZ_INS_LPGFR = 489 , SYSZ_INS_LPGR = 490 , SYSZ_INS_LPR = 491 , SYSZ_INS_LPXBR = 492 , SYSZ_INS_LR = 493 , SYSZ_INS_LRL = 494 , SYSZ_INS_LRV = 495 , SYSZ_INS_LRVG = 496 , SYSZ_INS_LRVGR = 497 , SYSZ_INS_LRVR = 498 , SYSZ_INS_LT = 499 , SYSZ_INS_LTDBR = 500 , SYSZ_INS_LTEBR = 501 , SYSZ_INS_LTG = 502 , SYSZ_INS_LTGF = 503 , SYSZ_INS_LTGFR = 504 , SYSZ_INS_LTGR = 505 , SYSZ_INS_LTR = 506 , SYSZ_INS_LTXBR = 507 , SYSZ_INS_LXDB = 508 , SYSZ_INS_LXDBR = 509 , SYSZ_INS_LXEB = 510 , SYSZ_INS_LXEBR = 511 , SYSZ_INS_LXR = 512 , SYSZ_INS_LY = 513 , SYSZ_INS_LZDR = 514 , SYSZ_INS_LZER = 515 , SYSZ_INS_LZXR = 516 , SYSZ_INS_MADB = 517 , SYSZ_INS_MADBR = 518 , SYSZ_INS_MAEB = 519 , SYSZ_INS_MAEBR = 520 , SYSZ_INS_MDB = 521 , SYSZ_INS_MDBR = 522 , SYSZ_INS_MDEB = 523 , SYSZ_INS_MDEBR = 524 , SYSZ_INS_MEEB = 525 , SYSZ_INS_MEEBR = 526 , SYSZ_INS_MGHI = 527 , SYSZ_INS_MH = 528 , SYSZ_INS_MHI = 529 , SYSZ_INS_MHY = 530 , SYSZ_INS_MLG = 531 , SYSZ_INS_MLGR = 532 , SYSZ_INS_MS = 533 , SYSZ_INS_MSDB = 534 , SYSZ_INS_MSDBR = 535 , SYSZ_INS_MSEB = 536 , SYSZ_INS_MSEBR = 537 , SYSZ_INS_MSFI = 538 , SYSZ_INS_MSG = 539 , SYSZ_INS_MSGF = 540 , SYSZ_INS_MSGFI = 541 , SYSZ_INS_MSGFR = 542 , SYSZ_INS_MSGR = 543 , SYSZ_INS_MSR = 544 , SYSZ_INS_MSY = 545 , SYSZ_INS_MVC = 546 , SYSZ_INS_MVGHI = 547 , SYSZ_INS_MVHHI = 548 , SYSZ_INS_MVHI = 549 , SYSZ_INS_MVI = 550 , SYSZ_INS_MVIY = 551 , SYSZ_INS_MVST = 552 , SYSZ_INS_MXBR = 553 , SYSZ_INS_MXDB = 554 , SYSZ_INS_MXDBR = 555 , SYSZ_INS_N = 556 , SYSZ_INS_NC = 557 , SYSZ_INS_NG = 558 , SYSZ_INS_NGR = 559 , SYSZ_INS_NGRK = 560 , SYSZ_INS_NI = 561 , SYSZ_INS_NIHF = 562 , SYSZ_INS_NIHH = 563 , SYSZ_INS_NIHL = 564 , SYSZ_INS_NILF = 565 , SYSZ_INS_NILH = 566 , SYSZ_INS_NILL = 567 , SYSZ_INS_NIY = 568 , SYSZ_INS_NR = 569 , SYSZ_INS_NRK = 570 , SYSZ_INS_NY = 571 , SYSZ_INS_O = 572 , SYSZ_INS_OC = 573 , SYSZ_INS_OG = 574 , SYSZ_INS_OGR = 575 , SYSZ_INS_OGRK = 576 , SYSZ_INS_OI = 577 , SYSZ_INS_OIHF = 578 , SYSZ_INS_OIHH = 579 , SYSZ_INS_OIHL = 580 , SYSZ_INS_OILF = 581 , SYSZ_INS_OILH = 582 , SYSZ_INS_OILL = 583 , SYSZ_INS_OIY = 584 , SYSZ_INS_OR = 585 , SYSZ_INS_ORK = 586 , SYSZ_INS_OY = 587 , SYSZ_INS_PFD = 588 , SYSZ_INS_PFDRL = 589 , SYSZ_INS_RISBG = 590 , SYSZ_INS_RISBHG = 591 , SYSZ_INS_RISBLG = 592 , SYSZ_INS_RLL = 593 , SYSZ_INS_RLLG = 594 , SYSZ_INS_RNSBG = 595 , SYSZ_INS_ROSBG = 596 , SYSZ_INS_RXSBG = 597 , SYSZ_INS_S = 598 , SYSZ_INS_SDB = 599 , SYSZ_INS_SDBR = 600 , SYSZ_INS_SEB = 601 , SYSZ_INS_SEBR = 602 , SYSZ_INS_SG = 603 , SYSZ_INS_SGF = 604 , SYSZ_INS_SGFR = 605 , SYSZ_INS_SGR = 606 , SYSZ_INS_SGRK = 607 , SYSZ_INS_SH = 608 , SYSZ_INS_SHY = 609 , SYSZ_INS_SL = 610 , SYSZ_INS_SLB = 611 , SYSZ_INS_SLBG = 612 , SYSZ_INS_SLBR = 613 , SYSZ_INS_SLFI = 614 , SYSZ_INS_SLG = 615 , SYSZ_INS_SLBGR = 616 , SYSZ_INS_SLGF = 617 , SYSZ_INS_SLGFI = 618 , SYSZ_INS_SLGFR = 619 , SYSZ_INS_SLGR = 620 , SYSZ_INS_SLGRK = 621 , SYSZ_INS_SLL = 622 , SYSZ_INS_SLLG = 623 , SYSZ_INS_SLLK = 624 , SYSZ_INS_SLR = 625 , SYSZ_INS_SLRK = 626 , SYSZ_INS_SLY = 627 , SYSZ_INS_SQDB = 628 , SYSZ_INS_SQDBR = 629 , SYSZ_INS_SQEB = 630 , SYSZ_INS_SQEBR = 631 , SYSZ_INS_SQXBR = 632 , SYSZ_INS_SR = 633 , SYSZ_INS_SRA = 634 , SYSZ_INS_SRAG = 635 , SYSZ_INS_SRAK = 636 , SYSZ_INS_SRK = 637 , SYSZ_INS_SRL = 638 , SYSZ_INS_SRLG = 639 , SYSZ_INS_SRLK = 640 , SYSZ_INS_SRST = 641 , SYSZ_INS_ST = 642 , SYSZ_INS_STC = 643 , SYSZ_INS_STCH = 644 , SYSZ_INS_STCY = 645 , SYSZ_INS_STD = 646 , SYSZ_INS_STDY = 647 , SYSZ_INS_STE = 648 , SYSZ_INS_STEY = 649 , SYSZ_INS_STFH = 650 , SYSZ_INS_STG = 651 , SYSZ_INS_STGRL = 652 , SYSZ_INS_STH = 653 , SYSZ_INS_STHH = 654 , SYSZ_INS_STHRL = 655 , SYSZ_INS_STHY = 656 , SYSZ_INS_STMG = 657 , SYSZ_INS_STRL = 658 , SYSZ_INS_STRV = 659 , SYSZ_INS_STRVG = 660 , SYSZ_INS_STY = 661 , SYSZ_INS_SXBR = 662 , SYSZ_INS_SY = 663 , SYSZ_INS_TM = 664 , SYSZ_INS_TMHH = 665 , SYSZ_INS_TMHL = 666 , SYSZ_INS_TMLH = 667 , SYSZ_INS_TMLL = 668 , SYSZ_INS_TMY = 669 , SYSZ_INS_X = 670 , SYSZ_INS_XC = 671 , SYSZ_INS_XG = 672 , SYSZ_INS_XGR = 673 , SYSZ_INS_XGRK = 674 , SYSZ_INS_XI = 675 , SYSZ_INS_XIHF = 676 , SYSZ_INS_XILF = 677 , SYSZ_INS_XIY = 678 , SYSZ_INS_XR = 679 , SYSZ_INS_XRK = 680 , SYSZ_INS_XY = 681 , SYSZ_INS_AD = 682 , SYSZ_INS_ADR = 683 , SYSZ_INS_ADTR = 684 , SYSZ_INS_ADTRA = 685 , SYSZ_INS_AE = 686 , SYSZ_INS_AER = 687 , SYSZ_INS_AGH = 688 , SYSZ_INS_AHHHR = 689 , SYSZ_INS_AHHLR = 690 , SYSZ_INS_ALGSI = 691 , SYSZ_INS_ALHHHR = 692 , SYSZ_INS_ALHHLR = 693 , SYSZ_INS_ALSI = 694 , SYSZ_INS_ALSIH = 695 , SYSZ_INS_ALSIHN = 696 , SYSZ_INS_AP = 697 , SYSZ_INS_AU = 698 , SYSZ_INS_AUR = 699 , SYSZ_INS_AW = 700 , SYSZ_INS_AWR = 701 , SYSZ_INS_AXR = 702 , SYSZ_INS_AXTR = 703 , SYSZ_INS_AXTRA = 704 , SYSZ_INS_B = 705 , SYSZ_INS_BAKR = 706 , SYSZ_INS_BAL = 707 , SYSZ_INS_BALR = 708 , SYSZ_INS_BAS = 709 , SYSZ_INS_BASSM = 710 , SYSZ_INS_BC = 711 , SYSZ_INS_BCT = 712 , SYSZ_INS_BCTG = 713 , SYSZ_INS_BCTGR = 714 , SYSZ_INS_BCTR = 715 , SYSZ_INS_BE = 716 , SYSZ_INS_BH = 717 , SYSZ_INS_BHE = 718 , SYSZ_INS_BI = 719 , SYSZ_INS_BIC = 720 , SYSZ_INS_BIE = 721 , SYSZ_INS_BIH = 722 , SYSZ_INS_BIHE = 723 , SYSZ_INS_BIL = 724 , SYSZ_INS_BILE = 725 , SYSZ_INS_BILH = 726 , SYSZ_INS_BIM = 727 , SYSZ_INS_BINE = 728 , SYSZ_INS_BINH = 729 , SYSZ_INS_BINHE = 730 , SYSZ_INS_BINL = 731 , SYSZ_INS_BINLE = 732 , SYSZ_INS_BINLH = 733 , SYSZ_INS_BINM = 734 , SYSZ_INS_BINO = 735 , SYSZ_INS_BINP = 736 , SYSZ_INS_BINZ = 737 , SYSZ_INS_BIO = 738 , SYSZ_INS_BIP = 739 , SYSZ_INS_BIZ = 740 , SYSZ_INS_BL = 741 , SYSZ_INS_BLE = 742 , SYSZ_INS_BLH = 743 , SYSZ_INS_BM = 744 , SYSZ_INS_BMR = 745 , SYSZ_INS_BNE = 746 , SYSZ_INS_BNH = 747 , SYSZ_INS_BNHE = 748 , SYSZ_INS_BNL = 749 , SYSZ_INS_BNLE = 750 , SYSZ_INS_BNLH = 751 , SYSZ_INS_BNM = 752 , SYSZ_INS_BNMR = 753 , SYSZ_INS_BNO = 754 , SYSZ_INS_BNP = 755 , SYSZ_INS_BNPR = 756 , SYSZ_INS_BNZ = 757 , SYSZ_INS_BNZR = 758 , SYSZ_INS_BO = 759 , SYSZ_INS_BP = 760 , SYSZ_INS_BPP = 761 , SYSZ_INS_BPR = 762 , SYSZ_INS_BPRP = 763 , SYSZ_INS_BRCTH = 764 , SYSZ_INS_BRXH = 765 , SYSZ_INS_BRXHG = 766 , SYSZ_INS_BRXLE = 767 , SYSZ_INS_BRXLG = 768 , SYSZ_INS_BSA = 769 , SYSZ_INS_BSG = 770 , SYSZ_INS_BSM = 771 , SYSZ_INS_BXH = 772 , SYSZ_INS_BXHG = 773 , SYSZ_INS_BXLE = 774 , SYSZ_INS_BXLEG = 775 , SYSZ_INS_BZ = 776 , SYSZ_INS_BZR = 777 , SYSZ_INS_CD = 778 , SYSZ_INS_CDFBRA = 779 , SYSZ_INS_CDFR = 780 , SYSZ_INS_CDFTR = 781 , SYSZ_INS_CDGBRA = 782 , SYSZ_INS_CDGR = 783 , SYSZ_INS_CDGTR = 784 , SYSZ_INS_CDGTRA = 785 , SYSZ_INS_CDLFTR = 786 , SYSZ_INS_CDLGTR = 787 , SYSZ_INS_CDPT = 788 , SYSZ_INS_CDR = 789 , SYSZ_INS_CDS = 790 , SYSZ_INS_CDSG = 791 , SYSZ_INS_CDSTR = 792 , SYSZ_INS_CDSY = 793 , SYSZ_INS_CDTR = 794 , SYSZ_INS_CDUTR = 795 , SYSZ_INS_CDZT = 796 , SYSZ_INS_CE = 797 , SYSZ_INS_CEDTR = 798 , SYSZ_INS_CEFBRA = 799 , SYSZ_INS_CEFR = 800 , SYSZ_INS_CEGBRA = 801 , SYSZ_INS_CEGR = 802 , SYSZ_INS_CER = 803 , SYSZ_INS_CEXTR = 804 , SYSZ_INS_CFC = 805 , SYSZ_INS_CFDBRA = 806 , SYSZ_INS_CFDR = 807 , SYSZ_INS_CFDTR = 808 , SYSZ_INS_CFEBRA = 809 , SYSZ_INS_CFER = 810 , SYSZ_INS_CFXBRA = 811 , SYSZ_INS_CFXR = 812 , SYSZ_INS_CFXTR = 813 , SYSZ_INS_CGDBRA = 814 , SYSZ_INS_CGDR = 815 , SYSZ_INS_CGDTR = 816 , SYSZ_INS_CGDTRA = 817 , SYSZ_INS_CGEBRA = 818 , SYSZ_INS_CGER = 819 , SYSZ_INS_CGIB = 820 , SYSZ_INS_CGIBE = 821 , SYSZ_INS_CGIBH = 822 , SYSZ_INS_CGIBHE = 823 , SYSZ_INS_CGIBL = 824 , SYSZ_INS_CGIBLE = 825 , SYSZ_INS_CGIBLH = 826 , SYSZ_INS_CGIBNE = 827 , SYSZ_INS_CGIBNH = 828 , SYSZ_INS_CGIBNHE = 829 , SYSZ_INS_CGIBNL = 830 , SYSZ_INS_CGIBNLE = 831 , SYSZ_INS_CGIBNLH = 832 , SYSZ_INS_CGIT = 833 , SYSZ_INS_CGITE = 834 , SYSZ_INS_CGITH = 835 , SYSZ_INS_CGITHE = 836 , SYSZ_INS_CGITL = 837 , SYSZ_INS_CGITLE = 838 , SYSZ_INS_CGITLH = 839 , SYSZ_INS_CGITNE = 840 , SYSZ_INS_CGITNH = 841 , SYSZ_INS_CGITNHE = 842 , SYSZ_INS_CGITNL = 843 , SYSZ_INS_CGITNLE = 844 , SYSZ_INS_CGITNLH = 845 , SYSZ_INS_CGRB = 846 , SYSZ_INS_CGRBE = 847 , SYSZ_INS_CGRBH = 848 , SYSZ_INS_CGRBHE = 849 , SYSZ_INS_CGRBL = 850 , SYSZ_INS_CGRBLE = 851 , SYSZ_INS_CGRBLH = 852 , SYSZ_INS_CGRBNE = 853 , SYSZ_INS_CGRBNH = 854 , SYSZ_INS_CGRBNHE = 855 , SYSZ_INS_CGRBNL = 856 , SYSZ_INS_CGRBNLE = 857 , SYSZ_INS_CGRBNLH = 858 , SYSZ_INS_CGRT = 859 , SYSZ_INS_CGRTE = 860 , SYSZ_INS_CGRTH = 861 , SYSZ_INS_CGRTHE = 862 , SYSZ_INS_CGRTL = 863 , SYSZ_INS_CGRTLE = 864 , SYSZ_INS_CGRTLH = 865 , SYSZ_INS_CGRTNE = 866 , SYSZ_INS_CGRTNH = 867 , SYSZ_INS_CGRTNHE = 868 , SYSZ_INS_CGRTNL = 869 , SYSZ_INS_CGRTNLE = 870 , SYSZ_INS_CGRTNLH = 871 , SYSZ_INS_CGXBRA = 872 , SYSZ_INS_CGXR = 873 , SYSZ_INS_CGXTR = 874 , SYSZ_INS_CGXTRA = 875 , SYSZ_INS_CHHR = 876 , SYSZ_INS_CHLR = 877 , SYSZ_INS_CIB = 878 , SYSZ_INS_CIBE = 879 , SYSZ_INS_CIBH = 880 , SYSZ_INS_CIBHE = 881 , SYSZ_INS_CIBL = 882 , SYSZ_INS_CIBLE = 883 , SYSZ_INS_CIBLH = 884 , SYSZ_INS_CIBNE = 885 , SYSZ_INS_CIBNH = 886 , SYSZ_INS_CIBNHE = 887 , SYSZ_INS_CIBNL = 888 , SYSZ_INS_CIBNLE = 889 , SYSZ_INS_CIBNLH = 890 , SYSZ_INS_CIT = 891 , SYSZ_INS_CITE = 892 , SYSZ_INS_CITH = 893 , SYSZ_INS_CITHE = 894 , SYSZ_INS_CITL = 895 , SYSZ_INS_CITLE = 896 , SYSZ_INS_CITLH = 897 , SYSZ_INS_CITNE = 898 , SYSZ_INS_CITNH = 899 , SYSZ_INS_CITNHE = 900 , SYSZ_INS_CITNL = 901 , SYSZ_INS_CITNLE = 902 , SYSZ_INS_CITNLH = 903 , SYSZ_INS_CKSM = 904 , SYSZ_INS_CLCL = 905 , SYSZ_INS_CLCLE = 906 , SYSZ_INS_CLCLU = 907 , SYSZ_INS_CLFDTR = 908 , SYSZ_INS_CLFIT = 909 , SYSZ_INS_CLFITE = 910 , SYSZ_INS_CLFITH = 911 , SYSZ_INS_CLFITHE = 912 , SYSZ_INS_CLFITL = 913 , SYSZ_INS_CLFITLE = 914 , SYSZ_INS_CLFITLH = 915 , SYSZ_INS_CLFITNE = 916 , SYSZ_INS_CLFITNH = 917 , SYSZ_INS_CLFITNHE = 918 , SYSZ_INS_CLFITNL = 919 , SYSZ_INS_CLFITNLE = 920 , SYSZ_INS_CLFITNLH = 921 , SYSZ_INS_CLFXTR = 922 , SYSZ_INS_CLGDTR = 923 , SYSZ_INS_CLGIB = 924 , SYSZ_INS_CLGIBE = 925 , SYSZ_INS_CLGIBH = 926 , SYSZ_INS_CLGIBHE = 927 , SYSZ_INS_CLGIBL = 928 , SYSZ_INS_CLGIBLE = 929 , SYSZ_INS_CLGIBLH = 930 , SYSZ_INS_CLGIBNE = 931 , SYSZ_INS_CLGIBNH = 932 , SYSZ_INS_CLGIBNHE = 933 , SYSZ_INS_CLGIBNL = 934 , SYSZ_INS_CLGIBNLE = 935 , SYSZ_INS_CLGIBNLH = 936 , SYSZ_INS_CLGIT = 937 , SYSZ_INS_CLGITE = 938 , SYSZ_INS_CLGITH = 939 , SYSZ_INS_CLGITHE = 940 , SYSZ_INS_CLGITL = 941 , SYSZ_INS_CLGITLE = 942 , SYSZ_INS_CLGITLH = 943 , SYSZ_INS_CLGITNE = 944 , SYSZ_INS_CLGITNH = 945 , SYSZ_INS_CLGITNHE = 946 , SYSZ_INS_CLGITNL = 947 , SYSZ_INS_CLGITNLE = 948 , SYSZ_INS_CLGITNLH = 949 , SYSZ_INS_CLGRB = 950 , SYSZ_INS_CLGRBE = 951 , SYSZ_INS_CLGRBH = 952 , SYSZ_INS_CLGRBHE = 953 , SYSZ_INS_CLGRBL = 954 , SYSZ_INS_CLGRBLE = 955 , SYSZ_INS_CLGRBLH = 956 , SYSZ_INS_CLGRBNE = 957 , SYSZ_INS_CLGRBNH = 958 , SYSZ_INS_CLGRBNHE = 959 , SYSZ_INS_CLGRBNL = 960 , SYSZ_INS_CLGRBNLE = 961 , SYSZ_INS_CLGRBNLH = 962 , SYSZ_INS_CLGRT = 963 , SYSZ_INS_CLGRTE = 964 , SYSZ_INS_CLGRTH = 965 , SYSZ_INS_CLGRTHE = 966 , SYSZ_INS_CLGRTL = 967 , SYSZ_INS_CLGRTLE = 968 , SYSZ_INS_CLGRTLH = 969 , SYSZ_INS_CLGRTNE = 970 , SYSZ_INS_CLGRTNH = 971 , SYSZ_INS_CLGRTNHE = 972 , SYSZ_INS_CLGRTNL = 973 , SYSZ_INS_CLGRTNLE = 974 , SYSZ_INS_CLGRTNLH = 975 , SYSZ_INS_CLGT = 976 , SYSZ_INS_CLGTE = 977 , SYSZ_INS_CLGTH = 978 , SYSZ_INS_CLGTHE = 979 , SYSZ_INS_CLGTL = 980 , SYSZ_INS_CLGTLE = 981 , SYSZ_INS_CLGTLH = 982 , SYSZ_INS_CLGTNE = 983 , SYSZ_INS_CLGTNH = 984 , SYSZ_INS_CLGTNHE = 985 , SYSZ_INS_CLGTNL = 986 , SYSZ_INS_CLGTNLE = 987 , SYSZ_INS_CLGTNLH = 988 , SYSZ_INS_CLGXTR = 989 , SYSZ_INS_CLHHR = 990 , SYSZ_INS_CLHLR = 991 , SYSZ_INS_CLIB = 992 , SYSZ_INS_CLIBE = 993 , SYSZ_INS_CLIBH = 994 , SYSZ_INS_CLIBHE = 995 , SYSZ_INS_CLIBL = 996 , SYSZ_INS_CLIBLE = 997 , SYSZ_INS_CLIBLH = 998 , SYSZ_INS_CLIBNE = 999 , SYSZ_INS_CLIBNH = 1000 , SYSZ_INS_CLIBNHE = 1001 , SYSZ_INS_CLIBNL = 1002 , SYSZ_INS_CLIBNLE = 1003 , SYSZ_INS_CLIBNLH = 1004 , SYSZ_INS_CLM = 1005 , SYSZ_INS_CLMH = 1006 , SYSZ_INS_CLMY = 1007 , SYSZ_INS_CLRB = 1008 , SYSZ_INS_CLRBE = 1009 , SYSZ_INS_CLRBH = 1010 , SYSZ_INS_CLRBHE = 1011 , SYSZ_INS_CLRBL = 1012 , SYSZ_INS_CLRBLE = 1013 , SYSZ_INS_CLRBLH = 1014 , SYSZ_INS_CLRBNE = 1015 , SYSZ_INS_CLRBNH = 1016 , SYSZ_INS_CLRBNHE = 1017 , SYSZ_INS_CLRBNL = 1018 , SYSZ_INS_CLRBNLE = 1019 , SYSZ_INS_CLRBNLH = 1020 , SYSZ_INS_CLRT = 1021 , SYSZ_INS_CLRTE = 1022 , SYSZ_INS_CLRTH = 1023 , SYSZ_INS_CLRTHE = 1024 , SYSZ_INS_CLRTL = 1025 , SYSZ_INS_CLRTLE = 1026 , SYSZ_INS_CLRTLH = 1027 , SYSZ_INS_CLRTNE = 1028 , SYSZ_INS_CLRTNH = 1029 , SYSZ_INS_CLRTNHE = 1030 , SYSZ_INS_CLRTNL = 1031 , SYSZ_INS_CLRTNLE = 1032 , SYSZ_INS_CLRTNLH = 1033 , SYSZ_INS_CLT = 1034 , SYSZ_INS_CLTE = 1035 , SYSZ_INS_CLTH = 1036 , SYSZ_INS_CLTHE = 1037 , SYSZ_INS_CLTL = 1038 , SYSZ_INS_CLTLE = 1039 , SYSZ_INS_CLTLH = 1040 , SYSZ_INS_CLTNE = 1041 , SYSZ_INS_CLTNH = 1042 , SYSZ_INS_CLTNHE = 1043 , SYSZ_INS_CLTNL = 1044 , SYSZ_INS_CLTNLE = 1045 , SYSZ_INS_CLTNLH = 1046 , SYSZ_INS_CMPSC = 1047 , SYSZ_INS_CP = 1048 , SYSZ_INS_CPDT = 1049 , SYSZ_INS_CPXT = 1050 , SYSZ_INS_CPYA = 1051 , SYSZ_INS_CRB = 1052 , SYSZ_INS_CRBE = 1053 , SYSZ_INS_CRBH = 1054 , SYSZ_INS_CRBHE = 1055 , SYSZ_INS_CRBL = 1056 , SYSZ_INS_CRBLE = 1057 , SYSZ_INS_CRBLH = 1058 , SYSZ_INS_CRBNE = 1059 , SYSZ_INS_CRBNH = 1060 , SYSZ_INS_CRBNHE = 1061 , SYSZ_INS_CRBNL = 1062 , SYSZ_INS_CRBNLE = 1063 , SYSZ_INS_CRBNLH = 1064 , SYSZ_INS_CRDTE = 1065 , SYSZ_INS_CRT = 1066 , SYSZ_INS_CRTE = 1067 , SYSZ_INS_CRTH = 1068 , SYSZ_INS_CRTHE = 1069 , SYSZ_INS_CRTL = 1070 , SYSZ_INS_CRTLE = 1071 , SYSZ_INS_CRTLH = 1072 , SYSZ_INS_CRTNE = 1073 , SYSZ_INS_CRTNH = 1074 , SYSZ_INS_CRTNHE = 1075 , SYSZ_INS_CRTNL = 1076 , SYSZ_INS_CRTNLE = 1077 , SYSZ_INS_CRTNLH = 1078 , SYSZ_INS_CSCH = 1079 , SYSZ_INS_CSDTR = 1080 , SYSZ_INS_CSP = 1081 , SYSZ_INS_CSPG = 1082 , SYSZ_INS_CSST = 1083 , SYSZ_INS_CSXTR = 1084 , SYSZ_INS_CU12 = 1085 , SYSZ_INS_CU14 = 1086 , SYSZ_INS_CU21 = 1087 , SYSZ_INS_CU24 = 1088 , SYSZ_INS_CU41 = 1089 , SYSZ_INS_CU42 = 1090 , SYSZ_INS_CUDTR = 1091 , SYSZ_INS_CUSE = 1092 , SYSZ_INS_CUTFU = 1093 , SYSZ_INS_CUUTF = 1094 , SYSZ_INS_CUXTR = 1095 , SYSZ_INS_CVB = 1096 , SYSZ_INS_CVBG = 1097 , SYSZ_INS_CVBY = 1098 , SYSZ_INS_CVD = 1099 , SYSZ_INS_CVDG = 1100 , SYSZ_INS_CVDY = 1101 , SYSZ_INS_CXFBRA = 1102 , SYSZ_INS_CXFR = 1103 , SYSZ_INS_CXFTR = 1104 , SYSZ_INS_CXGBRA = 1105 , SYSZ_INS_CXGR = 1106 , SYSZ_INS_CXGTR = 1107 , SYSZ_INS_CXGTRA = 1108 , SYSZ_INS_CXLFTR = 1109 , SYSZ_INS_CXLGTR = 1110 , SYSZ_INS_CXPT = 1111 , SYSZ_INS_CXR = 1112 , SYSZ_INS_CXSTR = 1113 , SYSZ_INS_CXTR = 1114 , SYSZ_INS_CXUTR = 1115 , SYSZ_INS_CXZT = 1116 , SYSZ_INS_CZDT = 1117 , SYSZ_INS_CZXT = 1118 , SYSZ_INS_D = 1119 , SYSZ_INS_DD = 1120 , SYSZ_INS_DDR = 1121 , SYSZ_INS_DDTR = 1122 , SYSZ_INS_DDTRA = 1123 , SYSZ_INS_DE = 1124 , SYSZ_INS_DER = 1125 , SYSZ_INS_DIAG = 1126 , SYSZ_INS_DIDBR = 1127 , SYSZ_INS_DIEBR = 1128 , SYSZ_INS_DP = 1129 , SYSZ_INS_DR = 1130 , SYSZ_INS_DXR = 1131 , SYSZ_INS_DXTR = 1132 , SYSZ_INS_DXTRA = 1133 , SYSZ_INS_ECAG = 1134 , SYSZ_INS_ECCTR = 1135 , SYSZ_INS_ECPGA = 1136 , SYSZ_INS_ECTG = 1137 , SYSZ_INS_ED = 1138 , SYSZ_INS_EDMK = 1139 , SYSZ_INS_EEDTR = 1140 , SYSZ_INS_EEXTR = 1141 , SYSZ_INS_EFPC = 1142 , SYSZ_INS_EPAIR = 1143 , SYSZ_INS_EPAR = 1144 , SYSZ_INS_EPCTR = 1145 , SYSZ_INS_EPSW = 1146 , SYSZ_INS_EREG = 1147 , SYSZ_INS_EREGG = 1148 , SYSZ_INS_ESAIR = 1149 , SYSZ_INS_ESAR = 1150 , SYSZ_INS_ESDTR = 1151 , SYSZ_INS_ESEA = 1152 , SYSZ_INS_ESTA = 1153 , SYSZ_INS_ESXTR = 1154 , SYSZ_INS_ETND = 1155 , SYSZ_INS_EX = 1156 , SYSZ_INS_EXRL = 1157 , SYSZ_INS_FIDR = 1158 , SYSZ_INS_FIDTR = 1159 , SYSZ_INS_FIER = 1160 , SYSZ_INS_FIXR = 1161 , SYSZ_INS_FIXTR = 1162 , SYSZ_INS_HDR = 1163 , SYSZ_INS_HER = 1164 , SYSZ_INS_HSCH = 1165 , SYSZ_INS_IAC = 1166 , SYSZ_INS_ICM = 1167 , SYSZ_INS_ICMH = 1168 , SYSZ_INS_ICMY = 1169 , SYSZ_INS_IDTE = 1170 , SYSZ_INS_IEDTR = 1171 , SYSZ_INS_IEXTR = 1172 , SYSZ_INS_IPK = 1173 , SYSZ_INS_IPTE = 1174 , SYSZ_INS_IRBM = 1175 , SYSZ_INS_ISKE = 1176 , SYSZ_INS_IVSK = 1177 , SYSZ_INS_JGM = 1178 , SYSZ_INS_JGNM = 1179 , SYSZ_INS_JGNP = 1180 , SYSZ_INS_JGNZ = 1181 , SYSZ_INS_JGP = 1182 , SYSZ_INS_JGZ = 1183 , SYSZ_INS_JM = 1184 , SYSZ_INS_JNM = 1185 , SYSZ_INS_JNP = 1186 , SYSZ_INS_JNZ = 1187 , SYSZ_INS_JP = 1188 , SYSZ_INS_JZ = 1189 , SYSZ_INS_KDB = 1190 , SYSZ_INS_KDBR = 1191 , SYSZ_INS_KDTR = 1192 , SYSZ_INS_KEB = 1193 , SYSZ_INS_KEBR = 1194 , SYSZ_INS_KIMD = 1195 , SYSZ_INS_KLMD = 1196 , SYSZ_INS_KM = 1197 , SYSZ_INS_KMA = 1198 , SYSZ_INS_KMAC = 1199 , SYSZ_INS_KMC = 1200 , SYSZ_INS_KMCTR = 1201 , SYSZ_INS_KMF = 1202 , SYSZ_INS_KMO = 1203 , SYSZ_INS_KXBR = 1204 , SYSZ_INS_KXTR = 1205 , SYSZ_INS_LAE = 1206 , SYSZ_INS_LAEY = 1207 , SYSZ_INS_LAM = 1208 , SYSZ_INS_LAMY = 1209 , SYSZ_INS_LASP = 1210 , SYSZ_INS_LAT = 1211 , SYSZ_INS_LCBB = 1212 , SYSZ_INS_LCCTL = 1213 , SYSZ_INS_LCDFR = 1214 , SYSZ_INS_LCDR = 1215 , SYSZ_INS_LCER = 1216 , SYSZ_INS_LCTL = 1217 , SYSZ_INS_LCTLG = 1218 , SYSZ_INS_LCXR = 1219 , SYSZ_INS_LDE = 1220 , SYSZ_INS_LDER = 1221 , SYSZ_INS_LDETR = 1222 , SYSZ_INS_LDXR = 1223 , SYSZ_INS_LDXTR = 1224 , SYSZ_INS_LEDR = 1225 , SYSZ_INS_LEDTR = 1226 , SYSZ_INS_LEXR = 1227 , SYSZ_INS_LFAS = 1228 , SYSZ_INS_LFHAT = 1229 , SYSZ_INS_LFPC = 1230 , SYSZ_INS_LGAT = 1231 , SYSZ_INS_LGG = 1232 , SYSZ_INS_LGSC = 1233 , SYSZ_INS_LLGFAT = 1234 , SYSZ_INS_LLGFSG = 1235 , SYSZ_INS_LLGT = 1236 , SYSZ_INS_LLGTAT = 1237 , SYSZ_INS_LLGTR = 1238 , SYSZ_INS_LLZRGF = 1239 , SYSZ_INS_LM = 1240 , SYSZ_INS_LMD = 1241 , SYSZ_INS_LMH = 1242 , SYSZ_INS_LMY = 1243 , SYSZ_INS_LNDFR = 1244 , SYSZ_INS_LNDR = 1245 , SYSZ_INS_LNER = 1246 , SYSZ_INS_LNXR = 1247 , SYSZ_INS_LOCFH = 1248 , SYSZ_INS_LOCFHE = 1249 , SYSZ_INS_LOCFHH = 1250 , SYSZ_INS_LOCFHHE = 1251 , SYSZ_INS_LOCFHL = 1252 , SYSZ_INS_LOCFHLE = 1253 , SYSZ_INS_LOCFHLH = 1254 , SYSZ_INS_LOCFHM = 1255 , SYSZ_INS_LOCFHNE = 1256 , SYSZ_INS_LOCFHNH = 1257 , SYSZ_INS_LOCFHNHE = 1258 , SYSZ_INS_LOCFHNL = 1259 , SYSZ_INS_LOCFHNLE = 1260 , SYSZ_INS_LOCFHNLH = 1261 , SYSZ_INS_LOCFHNM = 1262 , SYSZ_INS_LOCFHNO = 1263 , SYSZ_INS_LOCFHNP = 1264 , SYSZ_INS_LOCFHNZ = 1265 , SYSZ_INS_LOCFHO = 1266 , SYSZ_INS_LOCFHP = 1267 , SYSZ_INS_LOCFHR = 1268 , SYSZ_INS_LOCFHRE = 1269 , SYSZ_INS_LOCFHRH = 1270 , SYSZ_INS_LOCFHRHE = 1271 , SYSZ_INS_LOCFHRL = 1272 , SYSZ_INS_LOCFHRLE = 1273 , SYSZ_INS_LOCFHRLH = 1274 , SYSZ_INS_LOCFHRM = 1275 , SYSZ_INS_LOCFHRNE = 1276 , SYSZ_INS_LOCFHRNH = 1277 , SYSZ_INS_LOCFHRNHE = 1278 , SYSZ_INS_LOCFHRNL = 1279 , SYSZ_INS_LOCFHRNLE = 1280 , SYSZ_INS_LOCFHRNLH = 1281 , SYSZ_INS_LOCFHRNM = 1282 , SYSZ_INS_LOCFHRNO = 1283 , SYSZ_INS_LOCFHRNP = 1284 , SYSZ_INS_LOCFHRNZ = 1285 , SYSZ_INS_LOCFHRO = 1286 , SYSZ_INS_LOCFHRP = 1287 , SYSZ_INS_LOCFHRZ = 1288 , SYSZ_INS_LOCFHZ = 1289 , SYSZ_INS_LOCGHI = 1290 , SYSZ_INS_LOCGHIE = 1291 , SYSZ_INS_LOCGHIH = 1292 , SYSZ_INS_LOCGHIHE = 1293 , SYSZ_INS_LOCGHIL = 1294 , SYSZ_INS_LOCGHILE = 1295 , SYSZ_INS_LOCGHILH = 1296 , SYSZ_INS_LOCGHIM = 1297 , SYSZ_INS_LOCGHINE = 1298 , SYSZ_INS_LOCGHINH = 1299 , SYSZ_INS_LOCGHINHE = 1300 , SYSZ_INS_LOCGHINL = 1301 , SYSZ_INS_LOCGHINLE = 1302 , SYSZ_INS_LOCGHINLH = 1303 , SYSZ_INS_LOCGHINM = 1304 , SYSZ_INS_LOCGHINO = 1305 , SYSZ_INS_LOCGHINP = 1306 , SYSZ_INS_LOCGHINZ = 1307 , SYSZ_INS_LOCGHIO = 1308 , SYSZ_INS_LOCGHIP = 1309 , SYSZ_INS_LOCGHIZ = 1310 , SYSZ_INS_LOCGM = 1311 , SYSZ_INS_LOCGNM = 1312 , SYSZ_INS_LOCGNP = 1313 , SYSZ_INS_LOCGNZ = 1314 , SYSZ_INS_LOCGP = 1315 , SYSZ_INS_LOCGRM = 1316 , SYSZ_INS_LOCGRNM = 1317 , SYSZ_INS_LOCGRNP = 1318 , SYSZ_INS_LOCGRNZ = 1319 , SYSZ_INS_LOCGRP = 1320 , SYSZ_INS_LOCGRZ = 1321 , SYSZ_INS_LOCGZ = 1322 , SYSZ_INS_LOCHHI = 1323 , SYSZ_INS_LOCHHIE = 1324 , SYSZ_INS_LOCHHIH = 1325 , SYSZ_INS_LOCHHIHE = 1326 , SYSZ_INS_LOCHHIL = 1327 , SYSZ_INS_LOCHHILE = 1328 , SYSZ_INS_LOCHHILH = 1329 , SYSZ_INS_LOCHHIM = 1330 , SYSZ_INS_LOCHHINE = 1331 , SYSZ_INS_LOCHHINH = 1332 , SYSZ_INS_LOCHHINHE = 1333 , SYSZ_INS_LOCHHINL = 1334 , SYSZ_INS_LOCHHINLE = 1335 , SYSZ_INS_LOCHHINLH = 1336 , SYSZ_INS_LOCHHINM = 1337 , SYSZ_INS_LOCHHINO = 1338 , SYSZ_INS_LOCHHINP = 1339 , SYSZ_INS_LOCHHINZ = 1340 , SYSZ_INS_LOCHHIO = 1341 , SYSZ_INS_LOCHHIP = 1342 , SYSZ_INS_LOCHHIZ = 1343 , SYSZ_INS_LOCHI = 1344 , SYSZ_INS_LOCHIE = 1345 , SYSZ_INS_LOCHIH = 1346 , SYSZ_INS_LOCHIHE = 1347 , SYSZ_INS_LOCHIL = 1348 , SYSZ_INS_LOCHILE = 1349 , SYSZ_INS_LOCHILH = 1350 , SYSZ_INS_LOCHIM = 1351 , SYSZ_INS_LOCHINE = 1352 , SYSZ_INS_LOCHINH = 1353 , SYSZ_INS_LOCHINHE = 1354 , SYSZ_INS_LOCHINL = 1355 , SYSZ_INS_LOCHINLE = 1356 , SYSZ_INS_LOCHINLH = 1357 , SYSZ_INS_LOCHINM = 1358 , SYSZ_INS_LOCHINO = 1359 , SYSZ_INS_LOCHINP = 1360 , SYSZ_INS_LOCHINZ = 1361 , SYSZ_INS_LOCHIO = 1362 , SYSZ_INS_LOCHIP = 1363 , SYSZ_INS_LOCHIZ = 1364 , SYSZ_INS_LOCM = 1365 , SYSZ_INS_LOCNM = 1366 , SYSZ_INS_LOCNP = 1367 , SYSZ_INS_LOCNZ = 1368 , SYSZ_INS_LOCP = 1369 , SYSZ_INS_LOCRM = 1370 , SYSZ_INS_LOCRNM = 1371 , SYSZ_INS_LOCRNP = 1372 , SYSZ_INS_LOCRNZ = 1373 , SYSZ_INS_LOCRP = 1374 , SYSZ_INS_LOCRZ = 1375 , SYSZ_INS_LOCZ = 1376 , SYSZ_INS_LPCTL = 1377 , SYSZ_INS_LPD = 1378 , SYSZ_INS_LPDFR = 1379 , SYSZ_INS_LPDG = 1380 , SYSZ_INS_LPDR = 1381 , SYSZ_INS_LPER = 1382 , SYSZ_INS_LPP = 1383 , SYSZ_INS_LPQ = 1384 , SYSZ_INS_LPSW = 1385 , SYSZ_INS_LPSWE = 1386 , SYSZ_INS_LPTEA = 1387 , SYSZ_INS_LPXR = 1388 , SYSZ_INS_LRA = 1389 , SYSZ_INS_LRAG = 1390 , SYSZ_INS_LRAY = 1391 , SYSZ_INS_LRDR = 1392 , SYSZ_INS_LRER = 1393 , SYSZ_INS_LRVH = 1394 , SYSZ_INS_LSCTL = 1395 , SYSZ_INS_LTDR = 1396 , SYSZ_INS_LTDTR = 1397 , SYSZ_INS_LTER = 1398 , SYSZ_INS_LTXR = 1399 , SYSZ_INS_LTXTR = 1400 , SYSZ_INS_LURA = 1401 , SYSZ_INS_LURAG = 1402 , SYSZ_INS_LXD = 1403 , SYSZ_INS_LXDR = 1404 , SYSZ_INS_LXDTR = 1405 , SYSZ_INS_LXE = 1406 , SYSZ_INS_LXER = 1407 , SYSZ_INS_LZRF = 1408 , SYSZ_INS_LZRG = 1409 , SYSZ_INS_M = 1410 , SYSZ_INS_MAD = 1411 , SYSZ_INS_MADR = 1412 , SYSZ_INS_MAE = 1413 , SYSZ_INS_MAER = 1414 , SYSZ_INS_MAY = 1415 , SYSZ_INS_MAYH = 1416 , SYSZ_INS_MAYHR = 1417 , SYSZ_INS_MAYL = 1418 , SYSZ_INS_MAYLR = 1419 , SYSZ_INS_MAYR = 1420 , SYSZ_INS_MC = 1421 , SYSZ_INS_MD = 1422 , SYSZ_INS_MDE = 1423 , SYSZ_INS_MDER = 1424 , SYSZ_INS_MDR = 1425 , SYSZ_INS_MDTR = 1426 , SYSZ_INS_MDTRA = 1427 , SYSZ_INS_ME = 1428 , SYSZ_INS_MEE = 1429 , SYSZ_INS_MEER = 1430 , SYSZ_INS_MER = 1431 , SYSZ_INS_MFY = 1432 , SYSZ_INS_MG = 1433 , SYSZ_INS_MGH = 1434 , SYSZ_INS_MGRK = 1435 , SYSZ_INS_ML = 1436 , SYSZ_INS_MLR = 1437 , SYSZ_INS_MP = 1438 , SYSZ_INS_MR = 1439 , SYSZ_INS_MSC = 1440 , SYSZ_INS_MSCH = 1441 , SYSZ_INS_MSD = 1442 , SYSZ_INS_MSDR = 1443 , SYSZ_INS_MSE = 1444 , SYSZ_INS_MSER = 1445 , SYSZ_INS_MSGC = 1446 , SYSZ_INS_MSGRKC = 1447 , SYSZ_INS_MSRKC = 1448 , SYSZ_INS_MSTA = 1449 , SYSZ_INS_MVCDK = 1450 , SYSZ_INS_MVCIN = 1451 , SYSZ_INS_MVCK = 1452 , SYSZ_INS_MVCL = 1453 , SYSZ_INS_MVCLE = 1454 , SYSZ_INS_MVCLU = 1455 , SYSZ_INS_MVCOS = 1456 , SYSZ_INS_MVCP = 1457 , SYSZ_INS_MVCS = 1458 , SYSZ_INS_MVCSK = 1459 , SYSZ_INS_MVN = 1460 , SYSZ_INS_MVO = 1461 , SYSZ_INS_MVPG = 1462 , SYSZ_INS_MVZ = 1463 , SYSZ_INS_MXD = 1464 , SYSZ_INS_MXDR = 1465 , SYSZ_INS_MXR = 1466 , SYSZ_INS_MXTR = 1467 , SYSZ_INS_MXTRA = 1468 , SYSZ_INS_MY = 1469 , SYSZ_INS_MYH = 1470 , SYSZ_INS_MYHR = 1471 , SYSZ_INS_MYL = 1472 , SYSZ_INS_MYLR = 1473 , SYSZ_INS_MYR = 1474 , SYSZ_INS_NIAI = 1475 , SYSZ_INS_NTSTG = 1476 , SYSZ_INS_PACK = 1477 , SYSZ_INS_PALB = 1478 , SYSZ_INS_PC = 1479 , SYSZ_INS_PCC = 1480 , SYSZ_INS_PCKMO = 1481 , SYSZ_INS_PFMF = 1482 , SYSZ_INS_PFPO = 1483 , SYSZ_INS_PGIN = 1484 , SYSZ_INS_PGOUT = 1485 , SYSZ_INS_PKA = 1486 , SYSZ_INS_PKU = 1487 , SYSZ_INS_PLO = 1488 , SYSZ_INS_POPCNT = 1489 , SYSZ_INS_PPA = 1490 , SYSZ_INS_PPNO = 1491 , SYSZ_INS_PR = 1492 , SYSZ_INS_PRNO = 1493 , SYSZ_INS_PT = 1494 , SYSZ_INS_PTF = 1495 , SYSZ_INS_PTFF = 1496 , SYSZ_INS_PTI = 1497 , SYSZ_INS_PTLB = 1498 , SYSZ_INS_QADTR = 1499 , SYSZ_INS_QAXTR = 1500 , SYSZ_INS_QCTRI = 1501 , SYSZ_INS_QSI = 1502 , SYSZ_INS_RCHP = 1503 , SYSZ_INS_RISBGN = 1504 , SYSZ_INS_RP = 1505 , SYSZ_INS_RRBE = 1506 , SYSZ_INS_RRBM = 1507 , SYSZ_INS_RRDTR = 1508 , SYSZ_INS_RRXTR = 1509 , SYSZ_INS_RSCH = 1510 , SYSZ_INS_SAC = 1511 , SYSZ_INS_SACF = 1512 , SYSZ_INS_SAL = 1513 , SYSZ_INS_SAM24 = 1514 , SYSZ_INS_SAM31 = 1515 , SYSZ_INS_SAM64 = 1516 , SYSZ_INS_SAR = 1517 , SYSZ_INS_SCCTR = 1518 , SYSZ_INS_SCHM = 1519 , SYSZ_INS_SCK = 1520 , SYSZ_INS_SCKC = 1521 , SYSZ_INS_SCKPF = 1522 , SYSZ_INS_SD = 1523 , SYSZ_INS_SDR = 1524 , SYSZ_INS_SDTR = 1525 , SYSZ_INS_SDTRA = 1526 , SYSZ_INS_SE = 1527 , SYSZ_INS_SER = 1528 , SYSZ_INS_SFASR = 1529 , SYSZ_INS_SFPC = 1530 , SYSZ_INS_SGH = 1531 , SYSZ_INS_SHHHR = 1532 , SYSZ_INS_SHHLR = 1533 , SYSZ_INS_SIE = 1534 , SYSZ_INS_SIGA = 1535 , SYSZ_INS_SIGP = 1536 , SYSZ_INS_SLA = 1537 , SYSZ_INS_SLAG = 1538 , SYSZ_INS_SLAK = 1539 , SYSZ_INS_SLDA = 1540 , SYSZ_INS_SLDL = 1541 , SYSZ_INS_SLDT = 1542 , SYSZ_INS_SLHHHR = 1543 , SYSZ_INS_SLHHLR = 1544 , SYSZ_INS_SLXT = 1545 , SYSZ_INS_SP = 1546 , SYSZ_INS_SPCTR = 1547 , SYSZ_INS_SPKA = 1548 , SYSZ_INS_SPM = 1549 , SYSZ_INS_SPT = 1550 , SYSZ_INS_SPX = 1551 , SYSZ_INS_SQD = 1552 , SYSZ_INS_SQDR = 1553 , SYSZ_INS_SQE = 1554 , SYSZ_INS_SQER = 1555 , SYSZ_INS_SQXR = 1556 , SYSZ_INS_SRDA = 1557 , SYSZ_INS_SRDL = 1558 , SYSZ_INS_SRDT = 1559 , SYSZ_INS_SRNM = 1560 , SYSZ_INS_SRNMB = 1561 , SYSZ_INS_SRNMT = 1562 , SYSZ_INS_SRP = 1563 , SYSZ_INS_SRSTU = 1564 , SYSZ_INS_SRXT = 1565 , SYSZ_INS_SSAIR = 1566 , SYSZ_INS_SSAR = 1567 , SYSZ_INS_SSCH = 1568 , SYSZ_INS_SSKE = 1569 , SYSZ_INS_SSM = 1570 , SYSZ_INS_STAM = 1571 , SYSZ_INS_STAMY = 1572 , SYSZ_INS_STAP = 1573 , SYSZ_INS_STCK = 1574 , SYSZ_INS_STCKC = 1575 , SYSZ_INS_STCKE = 1576 , SYSZ_INS_STCKF = 1577 , SYSZ_INS_STCM = 1578 , SYSZ_INS_STCMH = 1579 , SYSZ_INS_STCMY = 1580 , SYSZ_INS_STCPS = 1581 , SYSZ_INS_STCRW = 1582 , SYSZ_INS_STCTG = 1583 , SYSZ_INS_STCTL = 1584 , SYSZ_INS_STFL = 1585 , SYSZ_INS_STFLE = 1586 , SYSZ_INS_STFPC = 1587 , SYSZ_INS_STGSC = 1588 , SYSZ_INS_STIDP = 1589 , SYSZ_INS_STM = 1590 , SYSZ_INS_STMH = 1591 , SYSZ_INS_STMY = 1592 , SYSZ_INS_STNSM = 1593 , SYSZ_INS_STOCFH = 1594 , SYSZ_INS_STOCFHE = 1595 , SYSZ_INS_STOCFHH = 1596 , SYSZ_INS_STOCFHHE = 1597 , SYSZ_INS_STOCFHL = 1598 , SYSZ_INS_STOCFHLE = 1599 , SYSZ_INS_STOCFHLH = 1600 , SYSZ_INS_STOCFHM = 1601 , SYSZ_INS_STOCFHNE = 1602 , SYSZ_INS_STOCFHNH = 1603 , SYSZ_INS_STOCFHNHE = 1604 , SYSZ_INS_STOCFHNL = 1605 , SYSZ_INS_STOCFHNLE = 1606 , SYSZ_INS_STOCFHNLH = 1607 , SYSZ_INS_STOCFHNM = 1608 , SYSZ_INS_STOCFHNO = 1609 , SYSZ_INS_STOCFHNP = 1610 , SYSZ_INS_STOCFHNZ = 1611 , SYSZ_INS_STOCFHO = 1612 , SYSZ_INS_STOCFHP = 1613 , SYSZ_INS_STOCFHZ = 1614 , SYSZ_INS_STOCGM = 1615 , SYSZ_INS_STOCGNM = 1616 , SYSZ_INS_STOCGNP = 1617 , SYSZ_INS_STOCGNZ = 1618 , SYSZ_INS_STOCGP = 1619 , SYSZ_INS_STOCGZ = 1620 , SYSZ_INS_STOCM = 1621 , SYSZ_INS_STOCNM = 1622 , SYSZ_INS_STOCNP = 1623 , SYSZ_INS_STOCNZ = 1624 , SYSZ_INS_STOCP = 1625 , SYSZ_INS_STOCZ = 1626 , SYSZ_INS_STOSM = 1627 , SYSZ_INS_STPQ = 1628 , SYSZ_INS_STPT = 1629 , SYSZ_INS_STPX = 1630 , SYSZ_INS_STRAG = 1631 , SYSZ_INS_STRVH = 1632 , SYSZ_INS_STSCH = 1633 , SYSZ_INS_STSI = 1634 , SYSZ_INS_STURA = 1635 , SYSZ_INS_STURG = 1636 , SYSZ_INS_SU = 1637 , SYSZ_INS_SUR = 1638 , SYSZ_INS_SVC = 1639 , SYSZ_INS_SW = 1640 , SYSZ_INS_SWR = 1641 , SYSZ_INS_SXR = 1642 , SYSZ_INS_SXTR = 1643 , SYSZ_INS_SXTRA = 1644 , SYSZ_INS_TABORT = 1645 , SYSZ_INS_TAM = 1646 , SYSZ_INS_TAR = 1647 , SYSZ_INS_TB = 1648 , SYSZ_INS_TBDR = 1649 , SYSZ_INS_TBEDR = 1650 , SYSZ_INS_TBEGIN = 1651 , SYSZ_INS_TBEGINC = 1652 , SYSZ_INS_TCDB = 1653 , SYSZ_INS_TCEB = 1654 , SYSZ_INS_TCXB = 1655 , SYSZ_INS_TDCDT = 1656 , SYSZ_INS_TDCET = 1657 , SYSZ_INS_TDCXT = 1658 , SYSZ_INS_TDGDT = 1659 , SYSZ_INS_TDGET = 1660 , SYSZ_INS_TDGXT = 1661 , SYSZ_INS_TEND = 1662 , SYSZ_INS_THDER = 1663 , SYSZ_INS_THDR = 1664 , SYSZ_INS_TP = 1665 , SYSZ_INS_TPI = 1666 , SYSZ_INS_TPROT = 1667 , SYSZ_INS_TR = 1668 , SYSZ_INS_TRACE = 1669 , SYSZ_INS_TRACG = 1670 , SYSZ_INS_TRAP2 = 1671 , SYSZ_INS_TRAP4 = 1672 , SYSZ_INS_TRE = 1673 , SYSZ_INS_TROO = 1674 , SYSZ_INS_TROT = 1675 , SYSZ_INS_TRT = 1676 , SYSZ_INS_TRTE = 1677 , SYSZ_INS_TRTO = 1678 , SYSZ_INS_TRTR = 1679 , SYSZ_INS_TRTRE = 1680 , SYSZ_INS_TRTT = 1681 , SYSZ_INS_TS = 1682 , SYSZ_INS_TSCH = 1683 , SYSZ_INS_UNPK = 1684 , SYSZ_INS_UNPKA = 1685 , SYSZ_INS_UNPKU = 1686 , SYSZ_INS_UPT = 1687 , SYSZ_INS_VA = 1688 , SYSZ_INS_VAB = 1689 , SYSZ_INS_VAC = 1690 , SYSZ_INS_VACC = 1691 , SYSZ_INS_VACCB = 1692 , SYSZ_INS_VACCC = 1693 , SYSZ_INS_VACCCQ = 1694 , SYSZ_INS_VACCF = 1695 , SYSZ_INS_VACCG = 1696 , SYSZ_INS_VACCH = 1697 , SYSZ_INS_VACCQ = 1698 , SYSZ_INS_VACQ = 1699 , SYSZ_INS_VAF = 1700 , SYSZ_INS_VAG = 1701 , SYSZ_INS_VAH = 1702 , SYSZ_INS_VAP = 1703 , SYSZ_INS_VAQ = 1704 , SYSZ_INS_VAVG = 1705 , SYSZ_INS_VAVGB = 1706 , SYSZ_INS_VAVGF = 1707 , SYSZ_INS_VAVGG = 1708 , SYSZ_INS_VAVGH = 1709 , SYSZ_INS_VAVGL = 1710 , SYSZ_INS_VAVGLB = 1711 , SYSZ_INS_VAVGLF = 1712 , SYSZ_INS_VAVGLG = 1713 , SYSZ_INS_VAVGLH = 1714 , SYSZ_INS_VBPERM = 1715 , SYSZ_INS_VCDG = 1716 , SYSZ_INS_VCDGB = 1717 , SYSZ_INS_VCDLG = 1718 , SYSZ_INS_VCDLGB = 1719 , SYSZ_INS_VCEQ = 1720 , SYSZ_INS_VCEQB = 1721 , SYSZ_INS_VCEQBS = 1722 , SYSZ_INS_VCEQF = 1723 , SYSZ_INS_VCEQFS = 1724 , SYSZ_INS_VCEQG = 1725 , SYSZ_INS_VCEQGS = 1726 , SYSZ_INS_VCEQH = 1727 , SYSZ_INS_VCEQHS = 1728 , SYSZ_INS_VCGD = 1729 , SYSZ_INS_VCGDB = 1730 , SYSZ_INS_VCH = 1731 , SYSZ_INS_VCHB = 1732 , SYSZ_INS_VCHBS = 1733 , SYSZ_INS_VCHF = 1734 , SYSZ_INS_VCHFS = 1735 , SYSZ_INS_VCHG = 1736 , SYSZ_INS_VCHGS = 1737 , SYSZ_INS_VCHH = 1738 , SYSZ_INS_VCHHS = 1739 , SYSZ_INS_VCHL = 1740 , SYSZ_INS_VCHLB = 1741 , SYSZ_INS_VCHLBS = 1742 , SYSZ_INS_VCHLF = 1743 , SYSZ_INS_VCHLFS = 1744 , SYSZ_INS_VCHLG = 1745 , SYSZ_INS_VCHLGS = 1746 , SYSZ_INS_VCHLH = 1747 , SYSZ_INS_VCHLHS = 1748 , SYSZ_INS_VCKSM = 1749 , SYSZ_INS_VCLGD = 1750 , SYSZ_INS_VCLGDB = 1751 , SYSZ_INS_VCLZ = 1752 , SYSZ_INS_VCLZB = 1753 , SYSZ_INS_VCLZF = 1754 , SYSZ_INS_VCLZG = 1755 , SYSZ_INS_VCLZH = 1756 , SYSZ_INS_VCP = 1757 , SYSZ_INS_VCTZ = 1758 , SYSZ_INS_VCTZB = 1759 , SYSZ_INS_VCTZF = 1760 , SYSZ_INS_VCTZG = 1761 , SYSZ_INS_VCTZH = 1762 , SYSZ_INS_VCVB = 1763 , SYSZ_INS_VCVBG = 1764 , SYSZ_INS_VCVD = 1765 , SYSZ_INS_VCVDG = 1766 , SYSZ_INS_VDP = 1767 , SYSZ_INS_VEC = 1768 , SYSZ_INS_VECB = 1769 , SYSZ_INS_VECF = 1770 , SYSZ_INS_VECG = 1771 , SYSZ_INS_VECH = 1772 , SYSZ_INS_VECL = 1773 , SYSZ_INS_VECLB = 1774 , SYSZ_INS_VECLF = 1775 , SYSZ_INS_VECLG = 1776 , SYSZ_INS_VECLH = 1777 , SYSZ_INS_VERIM = 1778 , SYSZ_INS_VERIMB = 1779 , SYSZ_INS_VERIMF = 1780 , SYSZ_INS_VERIMG = 1781 , SYSZ_INS_VERIMH = 1782 , SYSZ_INS_VERLL = 1783 , SYSZ_INS_VERLLB = 1784 , SYSZ_INS_VERLLF = 1785 , SYSZ_INS_VERLLG = 1786 , SYSZ_INS_VERLLH = 1787 , SYSZ_INS_VERLLV = 1788 , SYSZ_INS_VERLLVB = 1789 , SYSZ_INS_VERLLVF = 1790 , SYSZ_INS_VERLLVG = 1791 , SYSZ_INS_VERLLVH = 1792 , SYSZ_INS_VESL = 1793 , SYSZ_INS_VESLB = 1794 , SYSZ_INS_VESLF = 1795 , SYSZ_INS_VESLG = 1796 , SYSZ_INS_VESLH = 1797 , SYSZ_INS_VESLV = 1798 , SYSZ_INS_VESLVB = 1799 , SYSZ_INS_VESLVF = 1800 , SYSZ_INS_VESLVG = 1801 , SYSZ_INS_VESLVH = 1802 , SYSZ_INS_VESRA = 1803 , SYSZ_INS_VESRAB = 1804 , SYSZ_INS_VESRAF = 1805 , SYSZ_INS_VESRAG = 1806 , SYSZ_INS_VESRAH = 1807 , SYSZ_INS_VESRAV = 1808 , SYSZ_INS_VESRAVB = 1809 , SYSZ_INS_VESRAVF = 1810 , SYSZ_INS_VESRAVG = 1811 , SYSZ_INS_VESRAVH = 1812 , SYSZ_INS_VESRL = 1813 , SYSZ_INS_VESRLB = 1814 , SYSZ_INS_VESRLF = 1815 , SYSZ_INS_VESRLG = 1816 , SYSZ_INS_VESRLH = 1817 , SYSZ_INS_VESRLV = 1818 , SYSZ_INS_VESRLVB = 1819 , SYSZ_INS_VESRLVF = 1820 , SYSZ_INS_VESRLVG = 1821 , SYSZ_INS_VESRLVH = 1822 , SYSZ_INS_VFA = 1823 , SYSZ_INS_VFADB = 1824 , SYSZ_INS_VFAE = 1825 , SYSZ_INS_VFAEB = 1826 , SYSZ_INS_VFAEBS = 1827 , SYSZ_INS_VFAEF = 1828 , SYSZ_INS_VFAEFS = 1829 , SYSZ_INS_VFAEH = 1830 , SYSZ_INS_VFAEHS = 1831 , SYSZ_INS_VFAEZB = 1832 , SYSZ_INS_VFAEZBS = 1833 , SYSZ_INS_VFAEZF = 1834 , SYSZ_INS_VFAEZFS = 1835 , SYSZ_INS_VFAEZH = 1836 , SYSZ_INS_VFAEZHS = 1837 , SYSZ_INS_VFASB = 1838 , SYSZ_INS_VFCE = 1839 , SYSZ_INS_VFCEDB = 1840 , SYSZ_INS_VFCEDBS = 1841 , SYSZ_INS_VFCESB = 1842 , SYSZ_INS_VFCESBS = 1843 , SYSZ_INS_VFCH = 1844 , SYSZ_INS_VFCHDB = 1845 , SYSZ_INS_VFCHDBS = 1846 , SYSZ_INS_VFCHE = 1847 , SYSZ_INS_VFCHEDB = 1848 , SYSZ_INS_VFCHEDBS = 1849 , SYSZ_INS_VFCHESB = 1850 , SYSZ_INS_VFCHESBS = 1851 , SYSZ_INS_VFCHSB = 1852 , SYSZ_INS_VFCHSBS = 1853 , SYSZ_INS_VFD = 1854 , SYSZ_INS_VFDDB = 1855 , SYSZ_INS_VFDSB = 1856 , SYSZ_INS_VFEE = 1857 , SYSZ_INS_VFEEB = 1858 , SYSZ_INS_VFEEBS = 1859 , SYSZ_INS_VFEEF = 1860 , SYSZ_INS_VFEEFS = 1861 , SYSZ_INS_VFEEH = 1862 , SYSZ_INS_VFEEHS = 1863 , SYSZ_INS_VFEEZB = 1864 , SYSZ_INS_VFEEZBS = 1865 , SYSZ_INS_VFEEZF = 1866 , SYSZ_INS_VFEEZFS = 1867 , SYSZ_INS_VFEEZH = 1868 , SYSZ_INS_VFEEZHS = 1869 , SYSZ_INS_VFENE = 1870 , SYSZ_INS_VFENEB = 1871 , SYSZ_INS_VFENEBS = 1872 , SYSZ_INS_VFENEF = 1873 , SYSZ_INS_VFENEFS = 1874 , SYSZ_INS_VFENEH = 1875 , SYSZ_INS_VFENEHS = 1876 , SYSZ_INS_VFENEZB = 1877 , SYSZ_INS_VFENEZBS = 1878 , SYSZ_INS_VFENEZF = 1879 , SYSZ_INS_VFENEZFS = 1880 , SYSZ_INS_VFENEZH = 1881 , SYSZ_INS_VFENEZHS = 1882 , SYSZ_INS_VFI = 1883 , SYSZ_INS_VFIDB = 1884 , SYSZ_INS_VFISB = 1885 , SYSZ_INS_VFKEDB = 1886 , SYSZ_INS_VFKEDBS = 1887 , SYSZ_INS_VFKESB = 1888 , SYSZ_INS_VFKESBS = 1889 , SYSZ_INS_VFKHDB = 1890 , SYSZ_INS_VFKHDBS = 1891 , SYSZ_INS_VFKHEDB = 1892 , SYSZ_INS_VFKHEDBS = 1893 , SYSZ_INS_VFKHESB = 1894 , SYSZ_INS_VFKHESBS = 1895 , SYSZ_INS_VFKHSB = 1896 , SYSZ_INS_VFKHSBS = 1897 , SYSZ_INS_VFLCDB = 1898 , SYSZ_INS_VFLCSB = 1899 , SYSZ_INS_VFLL = 1900 , SYSZ_INS_VFLLS = 1901 , SYSZ_INS_VFLNDB = 1902 , SYSZ_INS_VFLNSB = 1903 , SYSZ_INS_VFLPDB = 1904 , SYSZ_INS_VFLPSB = 1905 , SYSZ_INS_VFLR = 1906 , SYSZ_INS_VFLRD = 1907 , SYSZ_INS_VFM = 1908 , SYSZ_INS_VFMA = 1909 , SYSZ_INS_VFMADB = 1910 , SYSZ_INS_VFMASB = 1911 , SYSZ_INS_VFMAX = 1912 , SYSZ_INS_VFMAXDB = 1913 , SYSZ_INS_VFMAXSB = 1914 , SYSZ_INS_VFMDB = 1915 , SYSZ_INS_VFMIN = 1916 , SYSZ_INS_VFMINDB = 1917 , SYSZ_INS_VFMINSB = 1918 , SYSZ_INS_VFMS = 1919 , SYSZ_INS_VFMSB = 1920 , SYSZ_INS_VFMSDB = 1921 , SYSZ_INS_VFMSSB = 1922 , SYSZ_INS_VFNMA = 1923 , SYSZ_INS_VFNMADB = 1924 , SYSZ_INS_VFNMASB = 1925 , SYSZ_INS_VFNMS = 1926 , SYSZ_INS_VFNMSDB = 1927 , SYSZ_INS_VFNMSSB = 1928 , SYSZ_INS_VFPSO = 1929 , SYSZ_INS_VFPSODB = 1930 , SYSZ_INS_VFPSOSB = 1931 , SYSZ_INS_VFS = 1932 , SYSZ_INS_VFSDB = 1933 , SYSZ_INS_VFSQ = 1934 , SYSZ_INS_VFSQDB = 1935 , SYSZ_INS_VFSQSB = 1936 , SYSZ_INS_VFSSB = 1937 , SYSZ_INS_VFTCI = 1938 , SYSZ_INS_VFTCIDB = 1939 , SYSZ_INS_VFTCISB = 1940 , SYSZ_INS_VGBM = 1941 , SYSZ_INS_VGEF = 1942 , SYSZ_INS_VGEG = 1943 , SYSZ_INS_VGFM = 1944 , SYSZ_INS_VGFMA = 1945 , SYSZ_INS_VGFMAB = 1946 , SYSZ_INS_VGFMAF = 1947 , SYSZ_INS_VGFMAG = 1948 , SYSZ_INS_VGFMAH = 1949 , SYSZ_INS_VGFMB = 1950 , SYSZ_INS_VGFMF = 1951 , SYSZ_INS_VGFMG = 1952 , SYSZ_INS_VGFMH = 1953 , SYSZ_INS_VGM = 1954 , SYSZ_INS_VGMB = 1955 , SYSZ_INS_VGMF = 1956 , SYSZ_INS_VGMG = 1957 , SYSZ_INS_VGMH = 1958 , SYSZ_INS_VISTR = 1959 , SYSZ_INS_VISTRB = 1960 , SYSZ_INS_VISTRBS = 1961 , SYSZ_INS_VISTRF = 1962 , SYSZ_INS_VISTRFS = 1963 , SYSZ_INS_VISTRH = 1964 , SYSZ_INS_VISTRHS = 1965 , SYSZ_INS_VL = 1966 , SYSZ_INS_VLBB = 1967 , SYSZ_INS_VLC = 1968 , SYSZ_INS_VLCB = 1969 , SYSZ_INS_VLCF = 1970 , SYSZ_INS_VLCG = 1971 , SYSZ_INS_VLCH = 1972 , SYSZ_INS_VLDE = 1973 , SYSZ_INS_VLDEB = 1974 , SYSZ_INS_VLEB = 1975 , SYSZ_INS_VLED = 1976 , SYSZ_INS_VLEDB = 1977 , SYSZ_INS_VLEF = 1978 , SYSZ_INS_VLEG = 1979 , SYSZ_INS_VLEH = 1980 , SYSZ_INS_VLEIB = 1981 , SYSZ_INS_VLEIF = 1982 , SYSZ_INS_VLEIG = 1983 , SYSZ_INS_VLEIH = 1984 , SYSZ_INS_VLGV = 1985 , SYSZ_INS_VLGVB = 1986 , SYSZ_INS_VLGVF = 1987 , SYSZ_INS_VLGVG = 1988 , SYSZ_INS_VLGVH = 1989 , SYSZ_INS_VLIP = 1990 , SYSZ_INS_VLL = 1991 , SYSZ_INS_VLLEZ = 1992 , SYSZ_INS_VLLEZB = 1993 , SYSZ_INS_VLLEZF = 1994 , SYSZ_INS_VLLEZG = 1995 , SYSZ_INS_VLLEZH = 1996 , SYSZ_INS_VLLEZLF = 1997 , SYSZ_INS_VLM = 1998 , SYSZ_INS_VLP = 1999 , SYSZ_INS_VLPB = 2000 , SYSZ_INS_VLPF = 2001 , SYSZ_INS_VLPG = 2002 , SYSZ_INS_VLPH = 2003 , SYSZ_INS_VLR = 2004 , SYSZ_INS_VLREP = 2005 , SYSZ_INS_VLREPB = 2006 , SYSZ_INS_VLREPF = 2007 , SYSZ_INS_VLREPG = 2008 , SYSZ_INS_VLREPH = 2009 , SYSZ_INS_VLRL = 2010 , SYSZ_INS_VLRLR = 2011 , SYSZ_INS_VLVG = 2012 , SYSZ_INS_VLVGB = 2013 , SYSZ_INS_VLVGF = 2014 , SYSZ_INS_VLVGG = 2015 , SYSZ_INS_VLVGH = 2016 , SYSZ_INS_VLVGP = 2017 , SYSZ_INS_VMAE = 2018 , SYSZ_INS_VMAEB = 2019 , SYSZ_INS_VMAEF = 2020 , SYSZ_INS_VMAEH = 2021 , SYSZ_INS_VMAH = 2022 , SYSZ_INS_VMAHB = 2023 , SYSZ_INS_VMAHF = 2024 , SYSZ_INS_VMAHH = 2025 , SYSZ_INS_VMAL = 2026 , SYSZ_INS_VMALB = 2027 , SYSZ_INS_VMALE = 2028 , SYSZ_INS_VMALEB = 2029 , SYSZ_INS_VMALEF = 2030 , SYSZ_INS_VMALEH = 2031 , SYSZ_INS_VMALF = 2032 , SYSZ_INS_VMALH = 2033 , SYSZ_INS_VMALHB = 2034 , SYSZ_INS_VMALHF = 2035 , SYSZ_INS_VMALHH = 2036 , SYSZ_INS_VMALHW = 2037 , SYSZ_INS_VMALO = 2038 , SYSZ_INS_VMALOB = 2039 , SYSZ_INS_VMALOF = 2040 , SYSZ_INS_VMALOH = 2041 , SYSZ_INS_VMAO = 2042 , SYSZ_INS_VMAOB = 2043 , SYSZ_INS_VMAOF = 2044 , SYSZ_INS_VMAOH = 2045 , SYSZ_INS_VME = 2046 , SYSZ_INS_VMEB = 2047 , SYSZ_INS_VMEF = 2048 , SYSZ_INS_VMEH = 2049 , SYSZ_INS_VMH = 2050 , SYSZ_INS_VMHB = 2051 , SYSZ_INS_VMHF = 2052 , SYSZ_INS_VMHH = 2053 , SYSZ_INS_VML = 2054 , SYSZ_INS_VMLB = 2055 , SYSZ_INS_VMLE = 2056 , SYSZ_INS_VMLEB = 2057 , SYSZ_INS_VMLEF = 2058 , SYSZ_INS_VMLEH = 2059 , SYSZ_INS_VMLF = 2060 , SYSZ_INS_VMLH = 2061 , SYSZ_INS_VMLHB = 2062 , SYSZ_INS_VMLHF = 2063 , SYSZ_INS_VMLHH = 2064 , SYSZ_INS_VMLHW = 2065 , SYSZ_INS_VMLO = 2066 , SYSZ_INS_VMLOB = 2067 , SYSZ_INS_VMLOF = 2068 , SYSZ_INS_VMLOH = 2069 , SYSZ_INS_VMN = 2070 , SYSZ_INS_VMNB = 2071 , SYSZ_INS_VMNF = 2072 , SYSZ_INS_VMNG = 2073 , SYSZ_INS_VMNH = 2074 , SYSZ_INS_VMNL = 2075 , SYSZ_INS_VMNLB = 2076 , SYSZ_INS_VMNLF = 2077 , SYSZ_INS_VMNLG = 2078 , SYSZ_INS_VMNLH = 2079 , SYSZ_INS_VMO = 2080 , SYSZ_INS_VMOB = 2081 , SYSZ_INS_VMOF = 2082 , SYSZ_INS_VMOH = 2083 , SYSZ_INS_VMP = 2084 , SYSZ_INS_VMRH = 2085 , SYSZ_INS_VMRHB = 2086 , SYSZ_INS_VMRHF = 2087 , SYSZ_INS_VMRHG = 2088 , SYSZ_INS_VMRHH = 2089 , SYSZ_INS_VMRL = 2090 , SYSZ_INS_VMRLB = 2091 , SYSZ_INS_VMRLF = 2092 , SYSZ_INS_VMRLG = 2093 , SYSZ_INS_VMRLH = 2094 , SYSZ_INS_VMSL = 2095 , SYSZ_INS_VMSLG = 2096 , SYSZ_INS_VMSP = 2097 , SYSZ_INS_VMX = 2098 , SYSZ_INS_VMXB = 2099 , SYSZ_INS_VMXF = 2100 , SYSZ_INS_VMXG = 2101 , SYSZ_INS_VMXH = 2102 , SYSZ_INS_VMXL = 2103 , SYSZ_INS_VMXLB = 2104 , SYSZ_INS_VMXLF = 2105 , SYSZ_INS_VMXLG = 2106 , SYSZ_INS_VMXLH = 2107 , SYSZ_INS_VN = 2108 , SYSZ_INS_VNC = 2109 , SYSZ_INS_VNN = 2110 , SYSZ_INS_VNO = 2111 , SYSZ_INS_VNX = 2112 , SYSZ_INS_VO = 2113 , SYSZ_INS_VOC = 2114 , SYSZ_INS_VONE = 2115 , SYSZ_INS_VPDI = 2116 , SYSZ_INS_VPERM = 2117 , SYSZ_INS_VPK = 2118 , SYSZ_INS_VPKF = 2119 , SYSZ_INS_VPKG = 2120 , SYSZ_INS_VPKH = 2121 , SYSZ_INS_VPKLS = 2122 , SYSZ_INS_VPKLSF = 2123 , SYSZ_INS_VPKLSFS = 2124 , SYSZ_INS_VPKLSG = 2125 , SYSZ_INS_VPKLSGS = 2126 , SYSZ_INS_VPKLSH = 2127 , SYSZ_INS_VPKLSHS = 2128 , SYSZ_INS_VPKS = 2129 , SYSZ_INS_VPKSF = 2130 , SYSZ_INS_VPKSFS = 2131 , SYSZ_INS_VPKSG = 2132 , SYSZ_INS_VPKSGS = 2133 , SYSZ_INS_VPKSH = 2134 , SYSZ_INS_VPKSHS = 2135 , SYSZ_INS_VPKZ = 2136 , SYSZ_INS_VPOPCT = 2137 , SYSZ_INS_VPOPCTB = 2138 , SYSZ_INS_VPOPCTF = 2139 , SYSZ_INS_VPOPCTG = 2140 , SYSZ_INS_VPOPCTH = 2141 , SYSZ_INS_VPSOP = 2142 , SYSZ_INS_VREP = 2143 , SYSZ_INS_VREPB = 2144 , SYSZ_INS_VREPF = 2145 , SYSZ_INS_VREPG = 2146 , SYSZ_INS_VREPH = 2147 , SYSZ_INS_VREPI = 2148 , SYSZ_INS_VREPIB = 2149 , SYSZ_INS_VREPIF = 2150 , SYSZ_INS_VREPIG = 2151 , SYSZ_INS_VREPIH = 2152 , SYSZ_INS_VRP = 2153 , SYSZ_INS_VS = 2154 , SYSZ_INS_VSB = 2155 , SYSZ_INS_VSBCBI = 2156 , SYSZ_INS_VSBCBIQ = 2157 , SYSZ_INS_VSBI = 2158 , SYSZ_INS_VSBIQ = 2159 , SYSZ_INS_VSCBI = 2160 , SYSZ_INS_VSCBIB = 2161 , SYSZ_INS_VSCBIF = 2162 , SYSZ_INS_VSCBIG = 2163 , SYSZ_INS_VSCBIH = 2164 , SYSZ_INS_VSCBIQ = 2165 , SYSZ_INS_VSCEF = 2166 , SYSZ_INS_VSCEG = 2167 , SYSZ_INS_VSDP = 2168 , SYSZ_INS_VSEG = 2169 , SYSZ_INS_VSEGB = 2170 , SYSZ_INS_VSEGF = 2171 , SYSZ_INS_VSEGH = 2172 , SYSZ_INS_VSEL = 2173 , SYSZ_INS_VSF = 2174 , SYSZ_INS_VSG = 2175 , SYSZ_INS_VSH = 2176 , SYSZ_INS_VSL = 2177 , SYSZ_INS_VSLB = 2178 , SYSZ_INS_VSLDB = 2179 , SYSZ_INS_VSP = 2180 , SYSZ_INS_VSQ = 2181 , SYSZ_INS_VSRA = 2182 , SYSZ_INS_VSRAB = 2183 , SYSZ_INS_VSRL = 2184 , SYSZ_INS_VSRLB = 2185 , SYSZ_INS_VSRP = 2186 , SYSZ_INS_VST = 2187 , SYSZ_INS_VSTEB = 2188 , SYSZ_INS_VSTEF = 2189 , SYSZ_INS_VSTEG = 2190 , SYSZ_INS_VSTEH = 2191 , SYSZ_INS_VSTL = 2192 , SYSZ_INS_VSTM = 2193 , SYSZ_INS_VSTRC = 2194 , SYSZ_INS_VSTRCB = 2195 , SYSZ_INS_VSTRCBS = 2196 , SYSZ_INS_VSTRCF = 2197 , SYSZ_INS_VSTRCFS = 2198 , SYSZ_INS_VSTRCH = 2199 , SYSZ_INS_VSTRCHS = 2200 , SYSZ_INS_VSTRCZB = 2201 , SYSZ_INS_VSTRCZBS = 2202 , SYSZ_INS_VSTRCZF = 2203 , SYSZ_INS_VSTRCZFS = 2204 , SYSZ_INS_VSTRCZH = 2205 , SYSZ_INS_VSTRCZHS = 2206 , SYSZ_INS_VSTRL = 2207 , SYSZ_INS_VSTRLR = 2208 , SYSZ_INS_VSUM = 2209 , SYSZ_INS_VSUMB = 2210 , SYSZ_INS_VSUMG = 2211 , SYSZ_INS_VSUMGF = 2212 , SYSZ_INS_VSUMGH = 2213 , SYSZ_INS_VSUMH = 2214 , SYSZ_INS_VSUMQ = 2215 , SYSZ_INS_VSUMQF = 2216 , SYSZ_INS_VSUMQG = 2217 , SYSZ_INS_VTM = 2218 , SYSZ_INS_VTP = 2219 , SYSZ_INS_VUPH = 2220 , SYSZ_INS_VUPHB = 2221 , SYSZ_INS_VUPHF = 2222 , SYSZ_INS_VUPHH = 2223 , SYSZ_INS_VUPKZ = 2224 , SYSZ_INS_VUPL = 2225 , SYSZ_INS_VUPLB = 2226 , SYSZ_INS_VUPLF = 2227 , SYSZ_INS_VUPLH = 2228 , SYSZ_INS_VUPLHB = 2229 , SYSZ_INS_VUPLHF = 2230 , SYSZ_INS_VUPLHH = 2231 , SYSZ_INS_VUPLHW = 2232 , SYSZ_INS_VUPLL = 2233 , SYSZ_INS_VUPLLB = 2234 , SYSZ_INS_VUPLLF = 2235 , SYSZ_INS_VUPLLH = 2236 , SYSZ_INS_VX = 2237 , SYSZ_INS_VZERO = 2238 , SYSZ_INS_WCDGB = 2239 , SYSZ_INS_WCDLGB = 2240 , SYSZ_INS_WCGDB = 2241 , SYSZ_INS_WCLGDB = 2242 , SYSZ_INS_WFADB = 2243 , SYSZ_INS_WFASB = 2244 , SYSZ_INS_WFAXB = 2245 , SYSZ_INS_WFC = 2246 , SYSZ_INS_WFCDB = 2247 , SYSZ_INS_WFCEDB = 2248 , SYSZ_INS_WFCEDBS = 2249 , SYSZ_INS_WFCESB = 2250 , SYSZ_INS_WFCESBS = 2251 , SYSZ_INS_WFCEXB = 2252 , SYSZ_INS_WFCEXBS = 2253 , SYSZ_INS_WFCHDB = 2254 , SYSZ_INS_WFCHDBS = 2255 , SYSZ_INS_WFCHEDB = 2256 , SYSZ_INS_WFCHEDBS = 2257 , SYSZ_INS_WFCHESB = 2258 , SYSZ_INS_WFCHESBS = 2259 , SYSZ_INS_WFCHEXB = 2260 , SYSZ_INS_WFCHEXBS = 2261 , SYSZ_INS_WFCHSB = 2262 , SYSZ_INS_WFCHSBS = 2263 , SYSZ_INS_WFCHXB = 2264 , SYSZ_INS_WFCHXBS = 2265 , SYSZ_INS_WFCSB = 2266 , SYSZ_INS_WFCXB = 2267 , SYSZ_INS_WFDDB = 2268 , SYSZ_INS_WFDSB = 2269 , SYSZ_INS_WFDXB = 2270 , SYSZ_INS_WFIDB = 2271 , SYSZ_INS_WFISB = 2272 , SYSZ_INS_WFIXB = 2273 , SYSZ_INS_WFK = 2274 , SYSZ_INS_WFKDB = 2275 , SYSZ_INS_WFKEDB = 2276 , SYSZ_INS_WFKEDBS = 2277 , SYSZ_INS_WFKESB = 2278 , SYSZ_INS_WFKESBS = 2279 , SYSZ_INS_WFKEXB = 2280 , SYSZ_INS_WFKEXBS = 2281 , SYSZ_INS_WFKHDB = 2282 , SYSZ_INS_WFKHDBS = 2283 , SYSZ_INS_WFKHEDB = 2284 , SYSZ_INS_WFKHEDBS = 2285 , SYSZ_INS_WFKHESB = 2286 , SYSZ_INS_WFKHESBS = 2287 , SYSZ_INS_WFKHEXB = 2288 , SYSZ_INS_WFKHEXBS = 2289 , SYSZ_INS_WFKHSB = 2290 , SYSZ_INS_WFKHSBS = 2291 , SYSZ_INS_WFKHXB = 2292 , SYSZ_INS_WFKHXBS = 2293 , SYSZ_INS_WFKSB = 2294 , SYSZ_INS_WFKXB = 2295 , SYSZ_INS_WFLCDB = 2296 , SYSZ_INS_WFLCSB = 2297 , SYSZ_INS_WFLCXB = 2298 , SYSZ_INS_WFLLD = 2299 , SYSZ_INS_WFLLS = 2300 , SYSZ_INS_WFLNDB = 2301 , SYSZ_INS_WFLNSB = 2302 , SYSZ_INS_WFLNXB = 2303 , SYSZ_INS_WFLPDB = 2304 , SYSZ_INS_WFLPSB = 2305 , SYSZ_INS_WFLPXB = 2306 , SYSZ_INS_WFLRD = 2307 , SYSZ_INS_WFLRX = 2308 , SYSZ_INS_WFMADB = 2309 , SYSZ_INS_WFMASB = 2310 , SYSZ_INS_WFMAXB = 2311 , SYSZ_INS_WFMAXDB = 2312 , SYSZ_INS_WFMAXSB = 2313 , SYSZ_INS_WFMAXXB = 2314 , SYSZ_INS_WFMDB = 2315 , SYSZ_INS_WFMINDB = 2316 , SYSZ_INS_WFMINSB = 2317 , SYSZ_INS_WFMINXB = 2318 , SYSZ_INS_WFMSB = 2319 , SYSZ_INS_WFMSDB = 2320 , SYSZ_INS_WFMSSB = 2321 , SYSZ_INS_WFMSXB = 2322 , SYSZ_INS_WFMXB = 2323 , SYSZ_INS_WFNMADB = 2324 , SYSZ_INS_WFNMASB = 2325 , SYSZ_INS_WFNMAXB = 2326 , SYSZ_INS_WFNMSDB = 2327 , SYSZ_INS_WFNMSSB = 2328 , SYSZ_INS_WFNMSXB = 2329 , SYSZ_INS_WFPSODB = 2330 , SYSZ_INS_WFPSOSB = 2331 , SYSZ_INS_WFPSOXB = 2332 , SYSZ_INS_WFSDB = 2333 , SYSZ_INS_WFSQDB = 2334 , SYSZ_INS_WFSQSB = 2335 , SYSZ_INS_WFSQXB = 2336 , SYSZ_INS_WFSSB = 2337 , SYSZ_INS_WFSXB = 2338 , SYSZ_INS_WFTCIDB = 2339 , SYSZ_INS_WFTCISB = 2340 , SYSZ_INS_WFTCIXB = 2341 , SYSZ_INS_WLDEB = 2342 , SYSZ_INS_WLEDB = 2343 , SYSZ_INS_XSCH = 2344 , SYSZ_INS_ZAP = 2345 , SYSZ_INS_ENDING = 2346 , } # [repr (u32)] # [doc = " Group of SystemZ instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn_group { # [doc = "< = CS_GRP_INVALID"] SYSZ_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SYSZ_GRP_JUMP = 1 , SYSZ_GRP_DISTINCTOPS = 128 , SYSZ_GRP_FPEXTENSION = 129 , SYSZ_GRP_HIGHWORD = 130 , SYSZ_GRP_INTERLOCKEDACCESS1 = 131 , SYSZ_GRP_LOADSTOREONCOND = 132 , SYSZ_GRP_DFPPACKEDCONVERSION = 133 , SYSZ_GRP_DFPZONEDCONVERSION = 134 , SYSZ_GRP_ENHANCEDDAT2 = 135 , SYSZ_GRP_EXECUTIONHINT = 136 , SYSZ_GRP_GUARDEDSTORAGE = 137 , SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 , SYSZ_GRP_LOADANDTRAP = 139 , SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 , SYSZ_GRP_LOADSTOREONCOND2 = 141 , SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 , SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 , SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 , SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 , SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 , SYSZ_GRP_NOVECTOR = 149 , SYSZ_GRP_POPULATIONCOUNT = 150 , SYSZ_GRP_PROCESSORASSIST = 151 , SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 , SYSZ_GRP_TRANSACTIONALEXECUTION = 153 , SYSZ_GRP_VECTOR = 154 , SYSZ_GRP_VECTORENHANCEMENTS1 = 155 , SYSZ_GRP_VECTORPACKEDDECIMAL = 156 , SYSZ_GRP_ENDING = 157 , } # [repr (u32)] # [doc = " X86 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_reg { X86_REG_INVALID = 0 , X86_REG_AH = 1 , X86_REG_AL = 2 , X86_REG_AX = 3 , X86_REG_BH = 4 , X86_REG_BL = 5 , X86_REG_BP = 6 , X86_REG_BPL = 7 , X86_REG_BX = 8 , X86_REG_CH = 9 , X86_REG_CL = 10 , X86_REG_CS = 11 , X86_REG_CX = 12 , X86_REG_DH = 13 , X86_REG_DI = 14 , X86_REG_DIL = 15 , X86_REG_DL = 16 , X86_REG_DS = 17 , X86_REG_DX = 18 , X86_REG_EAX = 19 , X86_REG_EBP = 20 , X86_REG_EBX = 21 , X86_REG_ECX = 22 , X86_REG_EDI = 23 , X86_REG_EDX = 24 , X86_REG_EFLAGS = 25 , X86_REG_EIP = 26 , X86_REG_EIZ = 27 , X86_REG_ES = 28 , X86_REG_ESI = 29 , X86_REG_ESP = 30 , X86_REG_FPSW = 31 , X86_REG_FS = 32 , X86_REG_GS = 33 , X86_REG_IP = 34 , X86_REG_RAX = 35 , X86_REG_RBP = 36 , X86_REG_RBX = 37 , X86_REG_RCX = 38 , X86_REG_RDI = 39 , X86_REG_RDX = 40 , X86_REG_RIP = 41 , X86_REG_RIZ = 42 , X86_REG_RSI = 43 , X86_REG_RSP = 44 , X86_REG_SI = 45 , X86_REG_SIL = 46 , X86_REG_SP = 47 , X86_REG_SPL = 48 , X86_REG_SS = 49 , X86_REG_CR0 = 50 , X86_REG_CR1 = 51 , X86_REG_CR2 = 52 , X86_REG_CR3 = 53 , X86_REG_CR4 = 54 , X86_REG_CR5 = 55 , X86_REG_CR6 = 56 , X86_REG_CR7 = 57 , X86_REG_CR8 = 58 , X86_REG_CR9 = 59 , X86_REG_CR10 = 60 , X86_REG_CR11 = 61 , X86_REG_CR12 = 62 , X86_REG_CR13 = 63 , X86_REG_CR14 = 64 , X86_REG_CR15 = 65 , X86_REG_DR0 = 66 , X86_REG_DR1 = 67 , X86_REG_DR2 = 68 , X86_REG_DR3 = 69 , X86_REG_DR4 = 70 , X86_REG_DR5 = 71 , X86_REG_DR6 = 72 , X86_REG_DR7 = 73 , X86_REG_DR8 = 74 , X86_REG_DR9 = 75 , X86_REG_DR10 = 76 , X86_REG_DR11 = 77 , X86_REG_DR12 = 78 , X86_REG_DR13 = 79 , X86_REG_DR14 = 80 , X86_REG_DR15 = 81 , X86_REG_FP0 = 82 , X86_REG_FP1 = 83 , X86_REG_FP2 = 84 , X86_REG_FP3 = 85 , X86_REG_FP4 = 86 , X86_REG_FP5 = 87 , X86_REG_FP6 = 88 , X86_REG_FP7 = 89 , X86_REG_K0 = 90 , X86_REG_K1 = 91 , X86_REG_K2 = 92 , X86_REG_K3 = 93 , X86_REG_K4 = 94 , X86_REG_K5 = 95 , X86_REG_K6 = 96 , X86_REG_K7 = 97 , X86_REG_MM0 = 98 , X86_REG_MM1 = 99 , X86_REG_MM2 = 100 , X86_REG_MM3 = 101 , X86_REG_MM4 = 102 , X86_REG_MM5 = 103 , X86_REG_MM6 = 104 , X86_REG_MM7 = 105 , X86_REG_R8 = 106 , X86_REG_R9 = 107 , X86_REG_R10 = 108 , X86_REG_R11 = 109 , X86_REG_R12 = 110 , X86_REG_R13 = 111 , X86_REG_R14 = 112 , X86_REG_R15 = 113 , X86_REG_ST0 = 114 , X86_REG_ST1 = 115 , X86_REG_ST2 = 116 , X86_REG_ST3 = 117 , X86_REG_ST4 = 118 , X86_REG_ST5 = 119 , X86_REG_ST6 = 120 , X86_REG_ST7 = 121 , X86_REG_XMM0 = 122 , X86_REG_XMM1 = 123 , X86_REG_XMM2 = 124 , X86_REG_XMM3 = 125 , X86_REG_XMM4 = 126 , X86_REG_XMM5 = 127 , X86_REG_XMM6 = 128 , X86_REG_XMM7 = 129 , X86_REG_XMM8 = 130 , X86_REG_XMM9 = 131 , X86_REG_XMM10 = 132 , X86_REG_XMM11 = 133 , X86_REG_XMM12 = 134 , X86_REG_XMM13 = 135 , X86_REG_XMM14 = 136 , X86_REG_XMM15 = 137 , X86_REG_XMM16 = 138 , X86_REG_XMM17 = 139 , X86_REG_XMM18 = 140 , X86_REG_XMM19 = 141 , X86_REG_XMM20 = 142 , X86_REG_XMM21 = 143 , X86_REG_XMM22 = 144 , X86_REG_XMM23 = 145 , X86_REG_XMM24 = 146 , X86_REG_XMM25 = 147 , X86_REG_XMM26 = 148 , X86_REG_XMM27 = 149 , X86_REG_XMM28 = 150 , X86_REG_XMM29 = 151 , X86_REG_XMM30 = 152 , X86_REG_XMM31 = 153 , X86_REG_YMM0 = 154 , X86_REG_YMM1 = 155 , X86_REG_YMM2 = 156 , X86_REG_YMM3 = 157 , X86_REG_YMM4 = 158 , X86_REG_YMM5 = 159 , X86_REG_YMM6 = 160 , X86_REG_YMM7 = 161 , X86_REG_YMM8 = 162 , X86_REG_YMM9 = 163 , X86_REG_YMM10 = 164 , X86_REG_YMM11 = 165 , X86_REG_YMM12 = 166 , X86_REG_YMM13 = 167 , X86_REG_YMM14 = 168 , X86_REG_YMM15 = 169 , X86_REG_YMM16 = 170 , X86_REG_YMM17 = 171 , X86_REG_YMM18 = 172 , X86_REG_YMM19 = 173 , X86_REG_YMM20 = 174 , X86_REG_YMM21 = 175 , X86_REG_YMM22 = 176 , X86_REG_YMM23 = 177 , X86_REG_YMM24 = 178 , X86_REG_YMM25 = 179 , X86_REG_YMM26 = 180 , X86_REG_YMM27 = 181 , X86_REG_YMM28 = 182 , X86_REG_YMM29 = 183 , X86_REG_YMM30 = 184 , X86_REG_YMM31 = 185 , X86_REG_ZMM0 = 186 , X86_REG_ZMM1 = 187 , X86_REG_ZMM2 = 188 , X86_REG_ZMM3 = 189 , X86_REG_ZMM4 = 190 , X86_REG_ZMM5 = 191 , X86_REG_ZMM6 = 192 , X86_REG_ZMM7 = 193 , X86_REG_ZMM8 = 194 , X86_REG_ZMM9 = 195 , X86_REG_ZMM10 = 196 , X86_REG_ZMM11 = 197 , X86_REG_ZMM12 = 198 , X86_REG_ZMM13 = 199 , X86_REG_ZMM14 = 200 , X86_REG_ZMM15 = 201 , X86_REG_ZMM16 = 202 , X86_REG_ZMM17 = 203 , X86_REG_ZMM18 = 204 , X86_REG_ZMM19 = 205 , X86_REG_ZMM20 = 206 , X86_REG_ZMM21 = 207 , X86_REG_ZMM22 = 208 , X86_REG_ZMM23 = 209 , X86_REG_ZMM24 = 210 , X86_REG_ZMM25 = 211 , X86_REG_ZMM26 = 212 , X86_REG_ZMM27 = 213 , X86_REG_ZMM28 = 214 , X86_REG_ZMM29 = 215 , X86_REG_ZMM30 = 216 , X86_REG_ZMM31 = 217 , X86_REG_R8B = 218 , X86_REG_R9B = 219 , X86_REG_R10B = 220 , X86_REG_R11B = 221 , X86_REG_R12B = 222 , X86_REG_R13B = 223 , X86_REG_R14B = 224 , X86_REG_R15B = 225 , X86_REG_R8D = 226 , X86_REG_R9D = 227 , X86_REG_R10D = 228 , X86_REG_R11D = 229 , X86_REG_R12D = 230 , X86_REG_R13D = 231 , X86_REG_R14D = 232 , X86_REG_R15D = 233 , X86_REG_R8W = 234 , X86_REG_R9W = 235 , X86_REG_R10W = 236 , X86_REG_R11W = 237 , X86_REG_R12W = 238 , X86_REG_R13W = 239 , X86_REG_R14W = 240 , X86_REG_R15W = 241 , X86_REG_BND0 = 242 , X86_REG_BND1 = 243 , X86_REG_BND2 = 244 , X86_REG_BND3 = 245 , X86_REG_ENDING = 246 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] X86_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] X86_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] X86_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] X86_OP_MEM = 3 , } # [repr (u32)] # [doc = " XOP Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_xop_cc { # [doc = "< Uninitialized."] X86_XOP_CC_INVALID = 0 , X86_XOP_CC_LT = 1 , X86_XOP_CC_LE = 2 , X86_XOP_CC_GT = 3 , X86_XOP_CC_GE = 4 , X86_XOP_CC_EQ = 5 , X86_XOP_CC_NEQ = 6 , X86_XOP_CC_FALSE = 7 , X86_XOP_CC_TRUE = 8 , } # [repr (u32)] # [doc = " AVX broadcast type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_bcast { # [doc = "< Uninitialized."] X86_AVX_BCAST_INVALID = 0 , # [doc = "< AVX512 broadcast type {1to2}"] X86_AVX_BCAST_2 = 1 , # [doc = "< AVX512 broadcast type {1to4}"] X86_AVX_BCAST_4 = 2 , # [doc = "< AVX512 broadcast type {1to8}"] X86_AVX_BCAST_8 = 3 , # [doc = "< AVX512 broadcast type {1to16}"] X86_AVX_BCAST_16 = 4 , } # [repr (u32)] # [doc = " SSE Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_sse_cc { # [doc = "< Uninitialized."] X86_SSE_CC_INVALID = 0 , X86_SSE_CC_EQ = 1 , X86_SSE_CC_LT = 2 , X86_SSE_CC_LE = 3 , X86_SSE_CC_UNORD = 4 , X86_SSE_CC_NEQ = 5 , X86_SSE_CC_NLT = 6 , X86_SSE_CC_NLE = 7 , X86_SSE_CC_ORD = 8 , } # [repr (u32)] # [doc = " AVX Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_cc { # [doc = "< Uninitialized."] X86_AVX_CC_INVALID = 0 , X86_AVX_CC_EQ = 1 , X86_AVX_CC_LT = 2 , X86_AVX_CC_LE = 3 , X86_AVX_CC_UNORD = 4 , X86_AVX_CC_NEQ = 5 , X86_AVX_CC_NLT = 6 , X86_AVX_CC_NLE = 7 , X86_AVX_CC_ORD = 8 , X86_AVX_CC_EQ_UQ = 9 , X86_AVX_CC_NGE = 10 , X86_AVX_CC_NGT = 11 , X86_AVX_CC_FALSE = 12 , X86_AVX_CC_NEQ_OQ = 13 , X86_AVX_CC_GE = 14 , X86_AVX_CC_GT = 15 , X86_AVX_CC_TRUE = 16 , X86_AVX_CC_EQ_OS = 17 , X86_AVX_CC_LT_OQ = 18 , X86_AVX_CC_LE_OQ = 19 , X86_AVX_CC_UNORD_S = 20 , X86_AVX_CC_NEQ_US = 21 , X86_AVX_CC_NLT_UQ = 22 , X86_AVX_CC_NLE_UQ = 23 , X86_AVX_CC_ORD_S = 24 , X86_AVX_CC_EQ_US = 25 , X86_AVX_CC_NGE_UQ = 26 , X86_AVX_CC_NGT_UQ = 27 , X86_AVX_CC_FALSE_OS = 28 , X86_AVX_CC_NEQ_OS = 29 , X86_AVX_CC_GE_OQ = 30 , X86_AVX_CC_GT_OQ = 31 , X86_AVX_CC_TRUE_US = 32 , } # [repr (u32)] # [doc = " AVX static rounding mode type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_rm { # [doc = "< Uninitialized."] X86_AVX_RM_INVALID = 0 , # [doc = "< Round to nearest"] X86_AVX_RM_RN = 1 , # [doc = "< Round down"] X86_AVX_RM_RD = 2 , # [doc = "< Round up"] X86_AVX_RM_RU = 3 , # [doc = "< Round toward zero"] X86_AVX_RM_RZ = 4 , } impl x86_prefix { pub const X86_PREFIX_REPE : x86_prefix = x86_prefix :: X86_PREFIX_REP ; } # [repr (u32)] # [doc = " Instruction prefixes - to be used in cs_x86.prefix[]"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_prefix { # [doc = "< lock (cs_x86.prefix[0]"] X86_PREFIX_LOCK = 240 , # [doc = "< rep (cs_x86.prefix[0]"] X86_PREFIX_REP = 243 , # [doc = "< repne/repnz (cs_x86.prefix[0]"] X86_PREFIX_REPNE = 242 , # [doc = "< segment override CS (cs_x86.prefix[1]"] X86_PREFIX_CS = 46 , # [doc = "< segment override SS (cs_x86.prefix[1]"] X86_PREFIX_SS = 54 , # [doc = "< segment override DS (cs_x86.prefix[1]"] X86_PREFIX_DS = 62 , # [doc = "< segment override ES (cs_x86.prefix[1]"] X86_PREFIX_ES = 38 , # [doc = "< segment override FS (cs_x86.prefix[1]"] X86_PREFIX_FS = 100 , # [doc = "< segment override GS (cs_x86.prefix[1]"] X86_PREFIX_GS = 101 , # [doc = "< operand-size override (cs_x86.prefix[2]"] X86_PREFIX_OPSIZE = 102 , # [doc = "< address-size override (cs_x86.prefix[3]"] X86_PREFIX_ADDRSIZE = 103 , } # [doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct x86_op_mem { # [doc = "< segment register (or X86_REG_INVALID if irrelevant)"] pub segment : x86_reg , # [doc = "< base register (or X86_REG_INVALID if irrelevant)"] pub base : x86_reg , # [doc = "< index register (or X86_REG_INVALID if irrelevant)"] pub index : x86_reg , # [doc = "< scale for index register"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of x86_op_mem"] [:: std :: mem :: size_of :: < x86_op_mem > () - 24usize] ; ["Alignment of x86_op_mem"] [:: std :: mem :: align_of :: < x86_op_mem > () - 8usize] ; ["Offset of field: x86_op_mem::segment"] [:: std :: mem :: offset_of ! (x86_op_mem , segment) - 0usize] ; ["Offset of field: x86_op_mem::base"] [:: std :: mem :: offset_of ! (x86_op_mem , base) - 4usize] ; ["Offset of field: x86_op_mem::index"] [:: std :: mem :: offset_of ! (x86_op_mem , index) - 8usize] ; ["Offset of field: x86_op_mem::scale"] [:: std :: mem :: offset_of ! (x86_op_mem , scale) - 12usize] ; ["Offset of field: x86_op_mem::disp"] [:: std :: mem :: offset_of ! (x86_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86_op { # [doc = "< operand type"] pub type_ : x86_op_type , pub __bindgen_anon_1 : cs_x86_op__bindgen_ty_1 , # [doc = " size of this operand (in bytes)."] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " AVX broadcast type, or 0 if irrelevant"] pub avx_bcast : x86_avx_bcast , # [doc = " AVX zero opmask {z}"] pub avx_zero_opmask : bool , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : x86_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : x86_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op"] [:: std :: mem :: size_of :: < cs_x86_op > () - 48usize] ; ["Alignment of cs_x86_op"] [:: std :: mem :: align_of :: < cs_x86_op > () - 8usize] ; ["Offset of field: cs_x86_op::type_"] [:: std :: mem :: offset_of ! (cs_x86_op , type_) - 0usize] ; ["Offset of field: cs_x86_op::size"] [:: std :: mem :: offset_of ! (cs_x86_op , size) - 32usize] ; ["Offset of field: cs_x86_op::access"] [:: std :: mem :: offset_of ! (cs_x86_op , access) - 33usize] ; ["Offset of field: cs_x86_op::avx_bcast"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_bcast) - 36usize] ; ["Offset of field: cs_x86_op::avx_zero_opmask"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_zero_opmask) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask) } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_x86_encoding { # [doc = " ModR/M offset, or 0 when irrelevant"] pub modrm_offset : u8 , # [doc = " Displacement offset, or 0 when irrelevant."] pub disp_offset : u8 , pub disp_size : u8 , # [doc = " Immediate offset, or 0 when irrelevant."] pub imm_offset : u8 , pub imm_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_encoding"] [:: std :: mem :: size_of :: < cs_x86_encoding > () - 5usize] ; ["Alignment of cs_x86_encoding"] [:: std :: mem :: align_of :: < cs_x86_encoding > () - 1usize] ; ["Offset of field: cs_x86_encoding::modrm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , modrm_offset) - 0usize] ; ["Offset of field: cs_x86_encoding::disp_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_offset) - 1usize] ; ["Offset of field: cs_x86_encoding::disp_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_size) - 2usize] ; ["Offset of field: cs_x86_encoding::imm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_offset) - 3usize] ; ["Offset of field: cs_x86_encoding::imm_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_size) - 4usize] ; } ; # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86 { # [doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"] pub prefix : [u8 ; 4usize] , # [doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."] pub opcode : [u8 ; 4usize] , # [doc = " REX prefix: only a non-zero value is relevant for x86_64"] pub rex : u8 , # [doc = " Address size, which can be overridden with above prefix[5]."] pub addr_size : u8 , # [doc = " ModR/M byte"] pub modrm : u8 , # [doc = " SIB value, or 0 when irrelevant."] pub sib : u8 , # [doc = " Displacement value, valid if encoding.disp_offset != 0"] pub disp : i64 , # [doc = " SIB index register, or X86_REG_INVALID when irrelevant."] pub sib_index : x86_reg , # [doc = " SIB scale, only applicable if sib_index is valid."] pub sib_scale : i8 , # [doc = " SIB base register, or X86_REG_INVALID when irrelevant."] pub sib_base : x86_reg , # [doc = " XOP Code Condition"] pub xop_cc : x86_xop_cc , # [doc = " SSE Code Condition"] pub sse_cc : x86_sse_cc , # [doc = " AVX Code Condition"] pub avx_cc : x86_avx_cc , # [doc = " AVX Suppress all Exception"] pub avx_sae : bool , # [doc = " AVX static rounding mode"] pub avx_rm : x86_avx_rm , pub __bindgen_anon_1 : cs_x86__bindgen_ty_1 , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_x86_op ; 8usize] , # [doc = "< encoding information"] pub encoding : cs_x86_encoding , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86__bindgen_ty_1 { # [doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"] pub eflags : u64 , # [doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"] pub fpu_flags : u64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_x86__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86__bindgen_ty_1::eflags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , eflags) - 0usize] ; ["Offset of field: cs_x86__bindgen_ty_1::fpu_flags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , fpu_flags) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86"] [:: std :: mem :: size_of :: < cs_x86 > () - 464usize] ; ["Alignment of cs_x86"] [:: std :: mem :: align_of :: < cs_x86 > () - 8usize] ; ["Offset of field: cs_x86::prefix"] [:: std :: mem :: offset_of ! (cs_x86 , prefix) - 0usize] ; ["Offset of field: cs_x86::opcode"] [:: std :: mem :: offset_of ! (cs_x86 , opcode) - 4usize] ; ["Offset of field: cs_x86::rex"] [:: std :: mem :: offset_of ! (cs_x86 , rex) - 8usize] ; ["Offset of field: cs_x86::addr_size"] [:: std :: mem :: offset_of ! (cs_x86 , addr_size) - 9usize] ; ["Offset of field: cs_x86::modrm"] [:: std :: mem :: offset_of ! (cs_x86 , modrm) - 10usize] ; ["Offset of field: cs_x86::sib"] [:: std :: mem :: offset_of ! (cs_x86 , sib) - 11usize] ; ["Offset of field: cs_x86::disp"] [:: std :: mem :: offset_of ! (cs_x86 , disp) - 16usize] ; ["Offset of field: cs_x86::sib_index"] [:: std :: mem :: offset_of ! (cs_x86 , sib_index) - 24usize] ; ["Offset of field: cs_x86::sib_scale"] [:: std :: mem :: offset_of ! (cs_x86 , sib_scale) - 28usize] ; ["Offset of field: cs_x86::sib_base"] [:: std :: mem :: offset_of ! (cs_x86 , sib_base) - 32usize] ; ["Offset of field: cs_x86::xop_cc"] [:: std :: mem :: offset_of ! (cs_x86 , xop_cc) - 36usize] ; ["Offset of field: cs_x86::sse_cc"] [:: std :: mem :: offset_of ! (cs_x86 , sse_cc) - 40usize] ; ["Offset of field: cs_x86::avx_cc"] [:: std :: mem :: offset_of ! (cs_x86 , avx_cc) - 44usize] ; ["Offset of field: cs_x86::avx_sae"] [:: std :: mem :: offset_of ! (cs_x86 , avx_sae) - 48usize] ; ["Offset of field: cs_x86::avx_rm"] [:: std :: mem :: offset_of ! (cs_x86 , avx_rm) - 52usize] ; ["Offset of field: cs_x86::op_count"] [:: std :: mem :: offset_of ! (cs_x86 , op_count) - 64usize] ; ["Offset of field: cs_x86::operands"] [:: std :: mem :: offset_of ! (cs_x86 , operands) - 72usize] ; ["Offset of field: cs_x86::encoding"] [:: std :: mem :: offset_of ! (cs_x86 , encoding) - 456usize] ; } ; impl :: std :: fmt :: Debug for cs_x86 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding) } } # [repr (u32)] # [doc = " X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn { X86_INS_INVALID = 0 , X86_INS_AAA = 1 , X86_INS_AAD = 2 , X86_INS_AAM = 3 , X86_INS_AAS = 4 , X86_INS_FABS = 5 , X86_INS_ADC = 6 , X86_INS_ADCX = 7 , X86_INS_ADD = 8 , X86_INS_ADDPD = 9 , X86_INS_ADDPS = 10 , X86_INS_ADDSD = 11 , X86_INS_ADDSS = 12 , X86_INS_ADDSUBPD = 13 , X86_INS_ADDSUBPS = 14 , X86_INS_FADD = 15 , X86_INS_FIADD = 16 , X86_INS_ADOX = 17 , X86_INS_AESDECLAST = 18 , X86_INS_AESDEC = 19 , X86_INS_AESENCLAST = 20 , X86_INS_AESENC = 21 , X86_INS_AESIMC = 22 , X86_INS_AESKEYGENASSIST = 23 , X86_INS_AND = 24 , X86_INS_ANDN = 25 , X86_INS_ANDNPD = 26 , X86_INS_ANDNPS = 27 , X86_INS_ANDPD = 28 , X86_INS_ANDPS = 29 , X86_INS_ARPL = 30 , X86_INS_BEXTR = 31 , X86_INS_BLCFILL = 32 , X86_INS_BLCI = 33 , X86_INS_BLCIC = 34 , X86_INS_BLCMSK = 35 , X86_INS_BLCS = 36 , X86_INS_BLENDPD = 37 , X86_INS_BLENDPS = 38 , X86_INS_BLENDVPD = 39 , X86_INS_BLENDVPS = 40 , X86_INS_BLSFILL = 41 , X86_INS_BLSI = 42 , X86_INS_BLSIC = 43 , X86_INS_BLSMSK = 44 , X86_INS_BLSR = 45 , X86_INS_BNDCL = 46 , X86_INS_BNDCN = 47 , X86_INS_BNDCU = 48 , X86_INS_BNDLDX = 49 , X86_INS_BNDMK = 50 , X86_INS_BNDMOV = 51 , X86_INS_BNDSTX = 52 , X86_INS_BOUND = 53 , X86_INS_BSF = 54 , X86_INS_BSR = 55 , X86_INS_BSWAP = 56 , X86_INS_BT = 57 , X86_INS_BTC = 58 , X86_INS_BTR = 59 , X86_INS_BTS = 60 , X86_INS_BZHI = 61 , X86_INS_CALL = 62 , X86_INS_CBW = 63 , X86_INS_CDQ = 64 , X86_INS_CDQE = 65 , X86_INS_FCHS = 66 , X86_INS_CLAC = 67 , X86_INS_CLC = 68 , X86_INS_CLD = 69 , X86_INS_CLDEMOTE = 70 , X86_INS_CLFLUSH = 71 , X86_INS_CLFLUSHOPT = 72 , X86_INS_CLGI = 73 , X86_INS_CLI = 74 , X86_INS_CLRSSBSY = 75 , X86_INS_CLTS = 76 , X86_INS_CLWB = 77 , X86_INS_CLZERO = 78 , X86_INS_CMC = 79 , X86_INS_CMOVA = 80 , X86_INS_CMOVAE = 81 , X86_INS_CMOVB = 82 , X86_INS_CMOVBE = 83 , X86_INS_FCMOVBE = 84 , X86_INS_FCMOVB = 85 , X86_INS_CMOVE = 86 , X86_INS_FCMOVE = 87 , X86_INS_CMOVG = 88 , X86_INS_CMOVGE = 89 , X86_INS_CMOVL = 90 , X86_INS_CMOVLE = 91 , X86_INS_FCMOVNBE = 92 , X86_INS_FCMOVNB = 93 , X86_INS_CMOVNE = 94 , X86_INS_FCMOVNE = 95 , X86_INS_CMOVNO = 96 , X86_INS_CMOVNP = 97 , X86_INS_FCMOVNU = 98 , X86_INS_FCMOVNP = 99 , X86_INS_CMOVNS = 100 , X86_INS_CMOVO = 101 , X86_INS_CMOVP = 102 , X86_INS_FCMOVU = 103 , X86_INS_CMOVS = 104 , X86_INS_CMP = 105 , X86_INS_CMPPD = 106 , X86_INS_CMPPS = 107 , X86_INS_CMPSB = 108 , X86_INS_CMPSD = 109 , X86_INS_CMPSQ = 110 , X86_INS_CMPSS = 111 , X86_INS_CMPSW = 112 , X86_INS_CMPXCHG16B = 113 , X86_INS_CMPXCHG = 114 , X86_INS_CMPXCHG8B = 115 , X86_INS_COMISD = 116 , X86_INS_COMISS = 117 , X86_INS_FCOMP = 118 , X86_INS_FCOMPI = 119 , X86_INS_FCOMI = 120 , X86_INS_FCOM = 121 , X86_INS_FCOS = 122 , X86_INS_CPUID = 123 , X86_INS_CQO = 124 , X86_INS_CRC32 = 125 , X86_INS_CVTDQ2PD = 126 , X86_INS_CVTDQ2PS = 127 , X86_INS_CVTPD2DQ = 128 , X86_INS_CVTPD2PS = 129 , X86_INS_CVTPS2DQ = 130 , X86_INS_CVTPS2PD = 131 , X86_INS_CVTSD2SI = 132 , X86_INS_CVTSD2SS = 133 , X86_INS_CVTSI2SD = 134 , X86_INS_CVTSI2SS = 135 , X86_INS_CVTSS2SD = 136 , X86_INS_CVTSS2SI = 137 , X86_INS_CVTTPD2DQ = 138 , X86_INS_CVTTPS2DQ = 139 , X86_INS_CVTTSD2SI = 140 , X86_INS_CVTTSS2SI = 141 , X86_INS_CWD = 142 , X86_INS_CWDE = 143 , X86_INS_DAA = 144 , X86_INS_DAS = 145 , X86_INS_DATA16 = 146 , X86_INS_DEC = 147 , X86_INS_DIV = 148 , X86_INS_DIVPD = 149 , X86_INS_DIVPS = 150 , X86_INS_FDIVR = 151 , X86_INS_FIDIVR = 152 , X86_INS_FDIVRP = 153 , X86_INS_DIVSD = 154 , X86_INS_DIVSS = 155 , X86_INS_FDIV = 156 , X86_INS_FIDIV = 157 , X86_INS_FDIVP = 158 , X86_INS_DPPD = 159 , X86_INS_DPPS = 160 , X86_INS_ENCLS = 161 , X86_INS_ENCLU = 162 , X86_INS_ENCLV = 163 , X86_INS_ENDBR32 = 164 , X86_INS_ENDBR64 = 165 , X86_INS_ENTER = 166 , X86_INS_EXTRACTPS = 167 , X86_INS_EXTRQ = 168 , X86_INS_F2XM1 = 169 , X86_INS_LCALL = 170 , X86_INS_LJMP = 171 , X86_INS_JMP = 172 , X86_INS_FBLD = 173 , X86_INS_FBSTP = 174 , X86_INS_FCOMPP = 175 , X86_INS_FDECSTP = 176 , X86_INS_FDISI8087_NOP = 177 , X86_INS_FEMMS = 178 , X86_INS_FENI8087_NOP = 179 , X86_INS_FFREE = 180 , X86_INS_FFREEP = 181 , X86_INS_FICOM = 182 , X86_INS_FICOMP = 183 , X86_INS_FINCSTP = 184 , X86_INS_FLDCW = 185 , X86_INS_FLDENV = 186 , X86_INS_FLDL2E = 187 , X86_INS_FLDL2T = 188 , X86_INS_FLDLG2 = 189 , X86_INS_FLDLN2 = 190 , X86_INS_FLDPI = 191 , X86_INS_FNCLEX = 192 , X86_INS_FNINIT = 193 , X86_INS_FNOP = 194 , X86_INS_FNSTCW = 195 , X86_INS_FNSTSW = 196 , X86_INS_FPATAN = 197 , X86_INS_FSTPNCE = 198 , X86_INS_FPREM = 199 , X86_INS_FPREM1 = 200 , X86_INS_FPTAN = 201 , X86_INS_FRNDINT = 202 , X86_INS_FRSTOR = 203 , X86_INS_FNSAVE = 204 , X86_INS_FSCALE = 205 , X86_INS_FSETPM = 206 , X86_INS_FSINCOS = 207 , X86_INS_FNSTENV = 208 , X86_INS_FXAM = 209 , X86_INS_FXRSTOR = 210 , X86_INS_FXRSTOR64 = 211 , X86_INS_FXSAVE = 212 , X86_INS_FXSAVE64 = 213 , X86_INS_FXTRACT = 214 , X86_INS_FYL2X = 215 , X86_INS_FYL2XP1 = 216 , X86_INS_GETSEC = 217 , X86_INS_GF2P8AFFINEINVQB = 218 , X86_INS_GF2P8AFFINEQB = 219 , X86_INS_GF2P8MULB = 220 , X86_INS_HADDPD = 221 , X86_INS_HADDPS = 222 , X86_INS_HLT = 223 , X86_INS_HSUBPD = 224 , X86_INS_HSUBPS = 225 , X86_INS_IDIV = 226 , X86_INS_FILD = 227 , X86_INS_IMUL = 228 , X86_INS_IN = 229 , X86_INS_INC = 230 , X86_INS_INCSSPD = 231 , X86_INS_INCSSPQ = 232 , X86_INS_INSB = 233 , X86_INS_INSERTPS = 234 , X86_INS_INSERTQ = 235 , X86_INS_INSD = 236 , X86_INS_INSW = 237 , X86_INS_INT = 238 , X86_INS_INT1 = 239 , X86_INS_INT3 = 240 , X86_INS_INTO = 241 , X86_INS_INVD = 242 , X86_INS_INVEPT = 243 , X86_INS_INVLPG = 244 , X86_INS_INVLPGA = 245 , X86_INS_INVPCID = 246 , X86_INS_INVVPID = 247 , X86_INS_IRET = 248 , X86_INS_IRETD = 249 , X86_INS_IRETQ = 250 , X86_INS_FISTTP = 251 , X86_INS_FIST = 252 , X86_INS_FISTP = 253 , X86_INS_JAE = 254 , X86_INS_JA = 255 , X86_INS_JBE = 256 , X86_INS_JB = 257 , X86_INS_JCXZ = 258 , X86_INS_JECXZ = 259 , X86_INS_JE = 260 , X86_INS_JGE = 261 , X86_INS_JG = 262 , X86_INS_JLE = 263 , X86_INS_JL = 264 , X86_INS_JNE = 265 , X86_INS_JNO = 266 , X86_INS_JNP = 267 , X86_INS_JNS = 268 , X86_INS_JO = 269 , X86_INS_JP = 270 , X86_INS_JRCXZ = 271 , X86_INS_JS = 272 , X86_INS_KADDB = 273 , X86_INS_KADDD = 274 , X86_INS_KADDQ = 275 , X86_INS_KADDW = 276 , X86_INS_KANDB = 277 , X86_INS_KANDD = 278 , X86_INS_KANDNB = 279 , X86_INS_KANDND = 280 , X86_INS_KANDNQ = 281 , X86_INS_KANDNW = 282 , X86_INS_KANDQ = 283 , X86_INS_KANDW = 284 , X86_INS_KMOVB = 285 , X86_INS_KMOVD = 286 , X86_INS_KMOVQ = 287 , X86_INS_KMOVW = 288 , X86_INS_KNOTB = 289 , X86_INS_KNOTD = 290 , X86_INS_KNOTQ = 291 , X86_INS_KNOTW = 292 , X86_INS_KORB = 293 , X86_INS_KORD = 294 , X86_INS_KORQ = 295 , X86_INS_KORTESTB = 296 , X86_INS_KORTESTD = 297 , X86_INS_KORTESTQ = 298 , X86_INS_KORTESTW = 299 , X86_INS_KORW = 300 , X86_INS_KSHIFTLB = 301 , X86_INS_KSHIFTLD = 302 , X86_INS_KSHIFTLQ = 303 , X86_INS_KSHIFTLW = 304 , X86_INS_KSHIFTRB = 305 , X86_INS_KSHIFTRD = 306 , X86_INS_KSHIFTRQ = 307 , X86_INS_KSHIFTRW = 308 , X86_INS_KTESTB = 309 , X86_INS_KTESTD = 310 , X86_INS_KTESTQ = 311 , X86_INS_KTESTW = 312 , X86_INS_KUNPCKBW = 313 , X86_INS_KUNPCKDQ = 314 , X86_INS_KUNPCKWD = 315 , X86_INS_KXNORB = 316 , X86_INS_KXNORD = 317 , X86_INS_KXNORQ = 318 , X86_INS_KXNORW = 319 , X86_INS_KXORB = 320 , X86_INS_KXORD = 321 , X86_INS_KXORQ = 322 , X86_INS_KXORW = 323 , X86_INS_LAHF = 324 , X86_INS_LAR = 325 , X86_INS_LDDQU = 326 , X86_INS_LDMXCSR = 327 , X86_INS_LDS = 328 , X86_INS_FLDZ = 329 , X86_INS_FLD1 = 330 , X86_INS_FLD = 331 , X86_INS_LEA = 332 , X86_INS_LEAVE = 333 , X86_INS_LES = 334 , X86_INS_LFENCE = 335 , X86_INS_LFS = 336 , X86_INS_LGDT = 337 , X86_INS_LGS = 338 , X86_INS_LIDT = 339 , X86_INS_LLDT = 340 , X86_INS_LLWPCB = 341 , X86_INS_LMSW = 342 , X86_INS_LOCK = 343 , X86_INS_LODSB = 344 , X86_INS_LODSD = 345 , X86_INS_LODSQ = 346 , X86_INS_LODSW = 347 , X86_INS_LOOP = 348 , X86_INS_LOOPE = 349 , X86_INS_LOOPNE = 350 , X86_INS_RETF = 351 , X86_INS_RETFQ = 352 , X86_INS_LSL = 353 , X86_INS_LSS = 354 , X86_INS_LTR = 355 , X86_INS_LWPINS = 356 , X86_INS_LWPVAL = 357 , X86_INS_LZCNT = 358 , X86_INS_MASKMOVDQU = 359 , X86_INS_MAXPD = 360 , X86_INS_MAXPS = 361 , X86_INS_MAXSD = 362 , X86_INS_MAXSS = 363 , X86_INS_MFENCE = 364 , X86_INS_MINPD = 365 , X86_INS_MINPS = 366 , X86_INS_MINSD = 367 , X86_INS_MINSS = 368 , X86_INS_CVTPD2PI = 369 , X86_INS_CVTPI2PD = 370 , X86_INS_CVTPI2PS = 371 , X86_INS_CVTPS2PI = 372 , X86_INS_CVTTPD2PI = 373 , X86_INS_CVTTPS2PI = 374 , X86_INS_EMMS = 375 , X86_INS_MASKMOVQ = 376 , X86_INS_MOVD = 377 , X86_INS_MOVQ = 378 , X86_INS_MOVDQ2Q = 379 , X86_INS_MOVNTQ = 380 , X86_INS_MOVQ2DQ = 381 , X86_INS_PABSB = 382 , X86_INS_PABSD = 383 , X86_INS_PABSW = 384 , X86_INS_PACKSSDW = 385 , X86_INS_PACKSSWB = 386 , X86_INS_PACKUSWB = 387 , X86_INS_PADDB = 388 , X86_INS_PADDD = 389 , X86_INS_PADDQ = 390 , X86_INS_PADDSB = 391 , X86_INS_PADDSW = 392 , X86_INS_PADDUSB = 393 , X86_INS_PADDUSW = 394 , X86_INS_PADDW = 395 , X86_INS_PALIGNR = 396 , X86_INS_PANDN = 397 , X86_INS_PAND = 398 , X86_INS_PAVGB = 399 , X86_INS_PAVGW = 400 , X86_INS_PCMPEQB = 401 , X86_INS_PCMPEQD = 402 , X86_INS_PCMPEQW = 403 , X86_INS_PCMPGTB = 404 , X86_INS_PCMPGTD = 405 , X86_INS_PCMPGTW = 406 , X86_INS_PEXTRW = 407 , X86_INS_PHADDD = 408 , X86_INS_PHADDSW = 409 , X86_INS_PHADDW = 410 , X86_INS_PHSUBD = 411 , X86_INS_PHSUBSW = 412 , X86_INS_PHSUBW = 413 , X86_INS_PINSRW = 414 , X86_INS_PMADDUBSW = 415 , X86_INS_PMADDWD = 416 , X86_INS_PMAXSW = 417 , X86_INS_PMAXUB = 418 , X86_INS_PMINSW = 419 , X86_INS_PMINUB = 420 , X86_INS_PMOVMSKB = 421 , X86_INS_PMULHRSW = 422 , X86_INS_PMULHUW = 423 , X86_INS_PMULHW = 424 , X86_INS_PMULLW = 425 , X86_INS_PMULUDQ = 426 , X86_INS_POR = 427 , X86_INS_PSADBW = 428 , X86_INS_PSHUFB = 429 , X86_INS_PSHUFW = 430 , X86_INS_PSIGNB = 431 , X86_INS_PSIGND = 432 , X86_INS_PSIGNW = 433 , X86_INS_PSLLD = 434 , X86_INS_PSLLQ = 435 , X86_INS_PSLLW = 436 , X86_INS_PSRAD = 437 , X86_INS_PSRAW = 438 , X86_INS_PSRLD = 439 , X86_INS_PSRLQ = 440 , X86_INS_PSRLW = 441 , X86_INS_PSUBB = 442 , X86_INS_PSUBD = 443 , X86_INS_PSUBQ = 444 , X86_INS_PSUBSB = 445 , X86_INS_PSUBSW = 446 , X86_INS_PSUBUSB = 447 , X86_INS_PSUBUSW = 448 , X86_INS_PSUBW = 449 , X86_INS_PUNPCKHBW = 450 , X86_INS_PUNPCKHDQ = 451 , X86_INS_PUNPCKHWD = 452 , X86_INS_PUNPCKLBW = 453 , X86_INS_PUNPCKLDQ = 454 , X86_INS_PUNPCKLWD = 455 , X86_INS_PXOR = 456 , X86_INS_MONITORX = 457 , X86_INS_MONITOR = 458 , X86_INS_MONTMUL = 459 , X86_INS_MOV = 460 , X86_INS_MOVABS = 461 , X86_INS_MOVAPD = 462 , X86_INS_MOVAPS = 463 , X86_INS_MOVBE = 464 , X86_INS_MOVDDUP = 465 , X86_INS_MOVDIR64B = 466 , X86_INS_MOVDIRI = 467 , X86_INS_MOVDQA = 468 , X86_INS_MOVDQU = 469 , X86_INS_MOVHLPS = 470 , X86_INS_MOVHPD = 471 , X86_INS_MOVHPS = 472 , X86_INS_MOVLHPS = 473 , X86_INS_MOVLPD = 474 , X86_INS_MOVLPS = 475 , X86_INS_MOVMSKPD = 476 , X86_INS_MOVMSKPS = 477 , X86_INS_MOVNTDQA = 478 , X86_INS_MOVNTDQ = 479 , X86_INS_MOVNTI = 480 , X86_INS_MOVNTPD = 481 , X86_INS_MOVNTPS = 482 , X86_INS_MOVNTSD = 483 , X86_INS_MOVNTSS = 484 , X86_INS_MOVSB = 485 , X86_INS_MOVSD = 486 , X86_INS_MOVSHDUP = 487 , X86_INS_MOVSLDUP = 488 , X86_INS_MOVSQ = 489 , X86_INS_MOVSS = 490 , X86_INS_MOVSW = 491 , X86_INS_MOVSX = 492 , X86_INS_MOVSXD = 493 , X86_INS_MOVUPD = 494 , X86_INS_MOVUPS = 495 , X86_INS_MOVZX = 496 , X86_INS_MPSADBW = 497 , X86_INS_MUL = 498 , X86_INS_MULPD = 499 , X86_INS_MULPS = 500 , X86_INS_MULSD = 501 , X86_INS_MULSS = 502 , X86_INS_MULX = 503 , X86_INS_FMUL = 504 , X86_INS_FIMUL = 505 , X86_INS_FMULP = 506 , X86_INS_MWAITX = 507 , X86_INS_MWAIT = 508 , X86_INS_NEG = 509 , X86_INS_NOP = 510 , X86_INS_NOT = 511 , X86_INS_OR = 512 , X86_INS_ORPD = 513 , X86_INS_ORPS = 514 , X86_INS_OUT = 515 , X86_INS_OUTSB = 516 , X86_INS_OUTSD = 517 , X86_INS_OUTSW = 518 , X86_INS_PACKUSDW = 519 , X86_INS_PAUSE = 520 , X86_INS_PAVGUSB = 521 , X86_INS_PBLENDVB = 522 , X86_INS_PBLENDW = 523 , X86_INS_PCLMULQDQ = 524 , X86_INS_PCMPEQQ = 525 , X86_INS_PCMPESTRI = 526 , X86_INS_PCMPESTRM = 527 , X86_INS_PCMPGTQ = 528 , X86_INS_PCMPISTRI = 529 , X86_INS_PCMPISTRM = 530 , X86_INS_PCONFIG = 531 , X86_INS_PDEP = 532 , X86_INS_PEXT = 533 , X86_INS_PEXTRB = 534 , X86_INS_PEXTRD = 535 , X86_INS_PEXTRQ = 536 , X86_INS_PF2ID = 537 , X86_INS_PF2IW = 538 , X86_INS_PFACC = 539 , X86_INS_PFADD = 540 , X86_INS_PFCMPEQ = 541 , X86_INS_PFCMPGE = 542 , X86_INS_PFCMPGT = 543 , X86_INS_PFMAX = 544 , X86_INS_PFMIN = 545 , X86_INS_PFMUL = 546 , X86_INS_PFNACC = 547 , X86_INS_PFPNACC = 548 , X86_INS_PFRCPIT1 = 549 , X86_INS_PFRCPIT2 = 550 , X86_INS_PFRCP = 551 , X86_INS_PFRSQIT1 = 552 , X86_INS_PFRSQRT = 553 , X86_INS_PFSUBR = 554 , X86_INS_PFSUB = 555 , X86_INS_PHMINPOSUW = 556 , X86_INS_PI2FD = 557 , X86_INS_PI2FW = 558 , X86_INS_PINSRB = 559 , X86_INS_PINSRD = 560 , X86_INS_PINSRQ = 561 , X86_INS_PMAXSB = 562 , X86_INS_PMAXSD = 563 , X86_INS_PMAXUD = 564 , X86_INS_PMAXUW = 565 , X86_INS_PMINSB = 566 , X86_INS_PMINSD = 567 , X86_INS_PMINUD = 568 , X86_INS_PMINUW = 569 , X86_INS_PMOVSXBD = 570 , X86_INS_PMOVSXBQ = 571 , X86_INS_PMOVSXBW = 572 , X86_INS_PMOVSXDQ = 573 , X86_INS_PMOVSXWD = 574 , X86_INS_PMOVSXWQ = 575 , X86_INS_PMOVZXBD = 576 , X86_INS_PMOVZXBQ = 577 , X86_INS_PMOVZXBW = 578 , X86_INS_PMOVZXDQ = 579 , X86_INS_PMOVZXWD = 580 , X86_INS_PMOVZXWQ = 581 , X86_INS_PMULDQ = 582 , X86_INS_PMULHRW = 583 , X86_INS_PMULLD = 584 , X86_INS_POP = 585 , X86_INS_POPAW = 586 , X86_INS_POPAL = 587 , X86_INS_POPCNT = 588 , X86_INS_POPF = 589 , X86_INS_POPFD = 590 , X86_INS_POPFQ = 591 , X86_INS_PREFETCH = 592 , X86_INS_PREFETCHNTA = 593 , X86_INS_PREFETCHT0 = 594 , X86_INS_PREFETCHT1 = 595 , X86_INS_PREFETCHT2 = 596 , X86_INS_PREFETCHW = 597 , X86_INS_PREFETCHWT1 = 598 , X86_INS_PSHUFD = 599 , X86_INS_PSHUFHW = 600 , X86_INS_PSHUFLW = 601 , X86_INS_PSLLDQ = 602 , X86_INS_PSRLDQ = 603 , X86_INS_PSWAPD = 604 , X86_INS_PTEST = 605 , X86_INS_PTWRITE = 606 , X86_INS_PUNPCKHQDQ = 607 , X86_INS_PUNPCKLQDQ = 608 , X86_INS_PUSH = 609 , X86_INS_PUSHAW = 610 , X86_INS_PUSHAL = 611 , X86_INS_PUSHF = 612 , X86_INS_PUSHFD = 613 , X86_INS_PUSHFQ = 614 , X86_INS_RCL = 615 , X86_INS_RCPPS = 616 , X86_INS_RCPSS = 617 , X86_INS_RCR = 618 , X86_INS_RDFSBASE = 619 , X86_INS_RDGSBASE = 620 , X86_INS_RDMSR = 621 , X86_INS_RDPID = 622 , X86_INS_RDPKRU = 623 , X86_INS_RDPMC = 624 , X86_INS_RDRAND = 625 , X86_INS_RDSEED = 626 , X86_INS_RDSSPD = 627 , X86_INS_RDSSPQ = 628 , X86_INS_RDTSC = 629 , X86_INS_RDTSCP = 630 , X86_INS_REPNE = 631 , X86_INS_REP = 632 , X86_INS_RET = 633 , X86_INS_REX64 = 634 , X86_INS_ROL = 635 , X86_INS_ROR = 636 , X86_INS_RORX = 637 , X86_INS_ROUNDPD = 638 , X86_INS_ROUNDPS = 639 , X86_INS_ROUNDSD = 640 , X86_INS_ROUNDSS = 641 , X86_INS_RSM = 642 , X86_INS_RSQRTPS = 643 , X86_INS_RSQRTSS = 644 , X86_INS_RSTORSSP = 645 , X86_INS_SAHF = 646 , X86_INS_SAL = 647 , X86_INS_SALC = 648 , X86_INS_SAR = 649 , X86_INS_SARX = 650 , X86_INS_SAVEPREVSSP = 651 , X86_INS_SBB = 652 , X86_INS_SCASB = 653 , X86_INS_SCASD = 654 , X86_INS_SCASQ = 655 , X86_INS_SCASW = 656 , X86_INS_SETAE = 657 , X86_INS_SETA = 658 , X86_INS_SETBE = 659 , X86_INS_SETB = 660 , X86_INS_SETE = 661 , X86_INS_SETGE = 662 , X86_INS_SETG = 663 , X86_INS_SETLE = 664 , X86_INS_SETL = 665 , X86_INS_SETNE = 666 , X86_INS_SETNO = 667 , X86_INS_SETNP = 668 , X86_INS_SETNS = 669 , X86_INS_SETO = 670 , X86_INS_SETP = 671 , X86_INS_SETSSBSY = 672 , X86_INS_SETS = 673 , X86_INS_SFENCE = 674 , X86_INS_SGDT = 675 , X86_INS_SHA1MSG1 = 676 , X86_INS_SHA1MSG2 = 677 , X86_INS_SHA1NEXTE = 678 , X86_INS_SHA1RNDS4 = 679 , X86_INS_SHA256MSG1 = 680 , X86_INS_SHA256MSG2 = 681 , X86_INS_SHA256RNDS2 = 682 , X86_INS_SHL = 683 , X86_INS_SHLD = 684 , X86_INS_SHLX = 685 , X86_INS_SHR = 686 , X86_INS_SHRD = 687 , X86_INS_SHRX = 688 , X86_INS_SHUFPD = 689 , X86_INS_SHUFPS = 690 , X86_INS_SIDT = 691 , X86_INS_FSIN = 692 , X86_INS_SKINIT = 693 , X86_INS_SLDT = 694 , X86_INS_SLWPCB = 695 , X86_INS_SMSW = 696 , X86_INS_SQRTPD = 697 , X86_INS_SQRTPS = 698 , X86_INS_SQRTSD = 699 , X86_INS_SQRTSS = 700 , X86_INS_FSQRT = 701 , X86_INS_STAC = 702 , X86_INS_STC = 703 , X86_INS_STD = 704 , X86_INS_STGI = 705 , X86_INS_STI = 706 , X86_INS_STMXCSR = 707 , X86_INS_STOSB = 708 , X86_INS_STOSD = 709 , X86_INS_STOSQ = 710 , X86_INS_STOSW = 711 , X86_INS_STR = 712 , X86_INS_FST = 713 , X86_INS_FSTP = 714 , X86_INS_SUB = 715 , X86_INS_SUBPD = 716 , X86_INS_SUBPS = 717 , X86_INS_FSUBR = 718 , X86_INS_FISUBR = 719 , X86_INS_FSUBRP = 720 , X86_INS_SUBSD = 721 , X86_INS_SUBSS = 722 , X86_INS_FSUB = 723 , X86_INS_FISUB = 724 , X86_INS_FSUBP = 725 , X86_INS_SWAPGS = 726 , X86_INS_SYSCALL = 727 , X86_INS_SYSENTER = 728 , X86_INS_SYSEXIT = 729 , X86_INS_SYSEXITQ = 730 , X86_INS_SYSRET = 731 , X86_INS_SYSRETQ = 732 , X86_INS_T1MSKC = 733 , X86_INS_TEST = 734 , X86_INS_TPAUSE = 735 , X86_INS_FTST = 736 , X86_INS_TZCNT = 737 , X86_INS_TZMSK = 738 , X86_INS_UCOMISD = 739 , X86_INS_UCOMISS = 740 , X86_INS_FUCOMPI = 741 , X86_INS_FUCOMI = 742 , X86_INS_FUCOMPP = 743 , X86_INS_FUCOMP = 744 , X86_INS_FUCOM = 745 , X86_INS_UD0 = 746 , X86_INS_UD1 = 747 , X86_INS_UD2 = 748 , X86_INS_UMONITOR = 749 , X86_INS_UMWAIT = 750 , X86_INS_UNPCKHPD = 751 , X86_INS_UNPCKHPS = 752 , X86_INS_UNPCKLPD = 753 , X86_INS_UNPCKLPS = 754 , X86_INS_V4FMADDPS = 755 , X86_INS_V4FMADDSS = 756 , X86_INS_V4FNMADDPS = 757 , X86_INS_V4FNMADDSS = 758 , X86_INS_VADDPD = 759 , X86_INS_VADDPS = 760 , X86_INS_VADDSD = 761 , X86_INS_VADDSS = 762 , X86_INS_VADDSUBPD = 763 , X86_INS_VADDSUBPS = 764 , X86_INS_VAESDECLAST = 765 , X86_INS_VAESDEC = 766 , X86_INS_VAESENCLAST = 767 , X86_INS_VAESENC = 768 , X86_INS_VAESIMC = 769 , X86_INS_VAESKEYGENASSIST = 770 , X86_INS_VALIGND = 771 , X86_INS_VALIGNQ = 772 , X86_INS_VANDNPD = 773 , X86_INS_VANDNPS = 774 , X86_INS_VANDPD = 775 , X86_INS_VANDPS = 776 , X86_INS_VBLENDMPD = 777 , X86_INS_VBLENDMPS = 778 , X86_INS_VBLENDPD = 779 , X86_INS_VBLENDPS = 780 , X86_INS_VBLENDVPD = 781 , X86_INS_VBLENDVPS = 782 , X86_INS_VBROADCASTF128 = 783 , X86_INS_VBROADCASTF32X2 = 784 , X86_INS_VBROADCASTF32X4 = 785 , X86_INS_VBROADCASTF32X8 = 786 , X86_INS_VBROADCASTF64X2 = 787 , X86_INS_VBROADCASTF64X4 = 788 , X86_INS_VBROADCASTI128 = 789 , X86_INS_VBROADCASTI32X2 = 790 , X86_INS_VBROADCASTI32X4 = 791 , X86_INS_VBROADCASTI32X8 = 792 , X86_INS_VBROADCASTI64X2 = 793 , X86_INS_VBROADCASTI64X4 = 794 , X86_INS_VBROADCASTSD = 795 , X86_INS_VBROADCASTSS = 796 , X86_INS_VCMP = 797 , X86_INS_VCMPPD = 798 , X86_INS_VCMPPS = 799 , X86_INS_VCMPSD = 800 , X86_INS_VCMPSS = 801 , X86_INS_VCOMISD = 802 , X86_INS_VCOMISS = 803 , X86_INS_VCOMPRESSPD = 804 , X86_INS_VCOMPRESSPS = 805 , X86_INS_VCVTDQ2PD = 806 , X86_INS_VCVTDQ2PS = 807 , X86_INS_VCVTPD2DQ = 808 , X86_INS_VCVTPD2PS = 809 , X86_INS_VCVTPD2QQ = 810 , X86_INS_VCVTPD2UDQ = 811 , X86_INS_VCVTPD2UQQ = 812 , X86_INS_VCVTPH2PS = 813 , X86_INS_VCVTPS2DQ = 814 , X86_INS_VCVTPS2PD = 815 , X86_INS_VCVTPS2PH = 816 , X86_INS_VCVTPS2QQ = 817 , X86_INS_VCVTPS2UDQ = 818 , X86_INS_VCVTPS2UQQ = 819 , X86_INS_VCVTQQ2PD = 820 , X86_INS_VCVTQQ2PS = 821 , X86_INS_VCVTSD2SI = 822 , X86_INS_VCVTSD2SS = 823 , X86_INS_VCVTSD2USI = 824 , X86_INS_VCVTSI2SD = 825 , X86_INS_VCVTSI2SS = 826 , X86_INS_VCVTSS2SD = 827 , X86_INS_VCVTSS2SI = 828 , X86_INS_VCVTSS2USI = 829 , X86_INS_VCVTTPD2DQ = 830 , X86_INS_VCVTTPD2QQ = 831 , X86_INS_VCVTTPD2UDQ = 832 , X86_INS_VCVTTPD2UQQ = 833 , X86_INS_VCVTTPS2DQ = 834 , X86_INS_VCVTTPS2QQ = 835 , X86_INS_VCVTTPS2UDQ = 836 , X86_INS_VCVTTPS2UQQ = 837 , X86_INS_VCVTTSD2SI = 838 , X86_INS_VCVTTSD2USI = 839 , X86_INS_VCVTTSS2SI = 840 , X86_INS_VCVTTSS2USI = 841 , X86_INS_VCVTUDQ2PD = 842 , X86_INS_VCVTUDQ2PS = 843 , X86_INS_VCVTUQQ2PD = 844 , X86_INS_VCVTUQQ2PS = 845 , X86_INS_VCVTUSI2SD = 846 , X86_INS_VCVTUSI2SS = 847 , X86_INS_VDBPSADBW = 848 , X86_INS_VDIVPD = 849 , X86_INS_VDIVPS = 850 , X86_INS_VDIVSD = 851 , X86_INS_VDIVSS = 852 , X86_INS_VDPPD = 853 , X86_INS_VDPPS = 854 , X86_INS_VERR = 855 , X86_INS_VERW = 856 , X86_INS_VEXP2PD = 857 , X86_INS_VEXP2PS = 858 , X86_INS_VEXPANDPD = 859 , X86_INS_VEXPANDPS = 860 , X86_INS_VEXTRACTF128 = 861 , X86_INS_VEXTRACTF32X4 = 862 , X86_INS_VEXTRACTF32X8 = 863 , X86_INS_VEXTRACTF64X2 = 864 , X86_INS_VEXTRACTF64X4 = 865 , X86_INS_VEXTRACTI128 = 866 , X86_INS_VEXTRACTI32X4 = 867 , X86_INS_VEXTRACTI32X8 = 868 , X86_INS_VEXTRACTI64X2 = 869 , X86_INS_VEXTRACTI64X4 = 870 , X86_INS_VEXTRACTPS = 871 , X86_INS_VFIXUPIMMPD = 872 , X86_INS_VFIXUPIMMPS = 873 , X86_INS_VFIXUPIMMSD = 874 , X86_INS_VFIXUPIMMSS = 875 , X86_INS_VFMADD132PD = 876 , X86_INS_VFMADD132PS = 877 , X86_INS_VFMADD132SD = 878 , X86_INS_VFMADD132SS = 879 , X86_INS_VFMADD213PD = 880 , X86_INS_VFMADD213PS = 881 , X86_INS_VFMADD213SD = 882 , X86_INS_VFMADD213SS = 883 , X86_INS_VFMADD231PD = 884 , X86_INS_VFMADD231PS = 885 , X86_INS_VFMADD231SD = 886 , X86_INS_VFMADD231SS = 887 , X86_INS_VFMADDPD = 888 , X86_INS_VFMADDPS = 889 , X86_INS_VFMADDSD = 890 , X86_INS_VFMADDSS = 891 , X86_INS_VFMADDSUB132PD = 892 , X86_INS_VFMADDSUB132PS = 893 , X86_INS_VFMADDSUB213PD = 894 , X86_INS_VFMADDSUB213PS = 895 , X86_INS_VFMADDSUB231PD = 896 , X86_INS_VFMADDSUB231PS = 897 , X86_INS_VFMADDSUBPD = 898 , X86_INS_VFMADDSUBPS = 899 , X86_INS_VFMSUB132PD = 900 , X86_INS_VFMSUB132PS = 901 , X86_INS_VFMSUB132SD = 902 , X86_INS_VFMSUB132SS = 903 , X86_INS_VFMSUB213PD = 904 , X86_INS_VFMSUB213PS = 905 , X86_INS_VFMSUB213SD = 906 , X86_INS_VFMSUB213SS = 907 , X86_INS_VFMSUB231PD = 908 , X86_INS_VFMSUB231PS = 909 , X86_INS_VFMSUB231SD = 910 , X86_INS_VFMSUB231SS = 911 , X86_INS_VFMSUBADD132PD = 912 , X86_INS_VFMSUBADD132PS = 913 , X86_INS_VFMSUBADD213PD = 914 , X86_INS_VFMSUBADD213PS = 915 , X86_INS_VFMSUBADD231PD = 916 , X86_INS_VFMSUBADD231PS = 917 , X86_INS_VFMSUBADDPD = 918 , X86_INS_VFMSUBADDPS = 919 , X86_INS_VFMSUBPD = 920 , X86_INS_VFMSUBPS = 921 , X86_INS_VFMSUBSD = 922 , X86_INS_VFMSUBSS = 923 , X86_INS_VFNMADD132PD = 924 , X86_INS_VFNMADD132PS = 925 , X86_INS_VFNMADD132SD = 926 , X86_INS_VFNMADD132SS = 927 , X86_INS_VFNMADD213PD = 928 , X86_INS_VFNMADD213PS = 929 , X86_INS_VFNMADD213SD = 930 , X86_INS_VFNMADD213SS = 931 , X86_INS_VFNMADD231PD = 932 , X86_INS_VFNMADD231PS = 933 , X86_INS_VFNMADD231SD = 934 , X86_INS_VFNMADD231SS = 935 , X86_INS_VFNMADDPD = 936 , X86_INS_VFNMADDPS = 937 , X86_INS_VFNMADDSD = 938 , X86_INS_VFNMADDSS = 939 , X86_INS_VFNMSUB132PD = 940 , X86_INS_VFNMSUB132PS = 941 , X86_INS_VFNMSUB132SD = 942 , X86_INS_VFNMSUB132SS = 943 , X86_INS_VFNMSUB213PD = 944 , X86_INS_VFNMSUB213PS = 945 , X86_INS_VFNMSUB213SD = 946 , X86_INS_VFNMSUB213SS = 947 , X86_INS_VFNMSUB231PD = 948 , X86_INS_VFNMSUB231PS = 949 , X86_INS_VFNMSUB231SD = 950 , X86_INS_VFNMSUB231SS = 951 , X86_INS_VFNMSUBPD = 952 , X86_INS_VFNMSUBPS = 953 , X86_INS_VFNMSUBSD = 954 , X86_INS_VFNMSUBSS = 955 , X86_INS_VFPCLASSPD = 956 , X86_INS_VFPCLASSPS = 957 , X86_INS_VFPCLASSSD = 958 , X86_INS_VFPCLASSSS = 959 , X86_INS_VFRCZPD = 960 , X86_INS_VFRCZPS = 961 , X86_INS_VFRCZSD = 962 , X86_INS_VFRCZSS = 963 , X86_INS_VGATHERDPD = 964 , X86_INS_VGATHERDPS = 965 , X86_INS_VGATHERPF0DPD = 966 , X86_INS_VGATHERPF0DPS = 967 , X86_INS_VGATHERPF0QPD = 968 , X86_INS_VGATHERPF0QPS = 969 , X86_INS_VGATHERPF1DPD = 970 , X86_INS_VGATHERPF1DPS = 971 , X86_INS_VGATHERPF1QPD = 972 , X86_INS_VGATHERPF1QPS = 973 , X86_INS_VGATHERQPD = 974 , X86_INS_VGATHERQPS = 975 , X86_INS_VGETEXPPD = 976 , X86_INS_VGETEXPPS = 977 , X86_INS_VGETEXPSD = 978 , X86_INS_VGETEXPSS = 979 , X86_INS_VGETMANTPD = 980 , X86_INS_VGETMANTPS = 981 , X86_INS_VGETMANTSD = 982 , X86_INS_VGETMANTSS = 983 , X86_INS_VGF2P8AFFINEINVQB = 984 , X86_INS_VGF2P8AFFINEQB = 985 , X86_INS_VGF2P8MULB = 986 , X86_INS_VHADDPD = 987 , X86_INS_VHADDPS = 988 , X86_INS_VHSUBPD = 989 , X86_INS_VHSUBPS = 990 , X86_INS_VINSERTF128 = 991 , X86_INS_VINSERTF32X4 = 992 , X86_INS_VINSERTF32X8 = 993 , X86_INS_VINSERTF64X2 = 994 , X86_INS_VINSERTF64X4 = 995 , X86_INS_VINSERTI128 = 996 , X86_INS_VINSERTI32X4 = 997 , X86_INS_VINSERTI32X8 = 998 , X86_INS_VINSERTI64X2 = 999 , X86_INS_VINSERTI64X4 = 1000 , X86_INS_VINSERTPS = 1001 , X86_INS_VLDDQU = 1002 , X86_INS_VLDMXCSR = 1003 , X86_INS_VMASKMOVDQU = 1004 , X86_INS_VMASKMOVPD = 1005 , X86_INS_VMASKMOVPS = 1006 , X86_INS_VMAXPD = 1007 , X86_INS_VMAXPS = 1008 , X86_INS_VMAXSD = 1009 , X86_INS_VMAXSS = 1010 , X86_INS_VMCALL = 1011 , X86_INS_VMCLEAR = 1012 , X86_INS_VMFUNC = 1013 , X86_INS_VMINPD = 1014 , X86_INS_VMINPS = 1015 , X86_INS_VMINSD = 1016 , X86_INS_VMINSS = 1017 , X86_INS_VMLAUNCH = 1018 , X86_INS_VMLOAD = 1019 , X86_INS_VMMCALL = 1020 , X86_INS_VMOVQ = 1021 , X86_INS_VMOVAPD = 1022 , X86_INS_VMOVAPS = 1023 , X86_INS_VMOVDDUP = 1024 , X86_INS_VMOVD = 1025 , X86_INS_VMOVDQA32 = 1026 , X86_INS_VMOVDQA64 = 1027 , X86_INS_VMOVDQA = 1028 , X86_INS_VMOVDQU16 = 1029 , X86_INS_VMOVDQU32 = 1030 , X86_INS_VMOVDQU64 = 1031 , X86_INS_VMOVDQU8 = 1032 , X86_INS_VMOVDQU = 1033 , X86_INS_VMOVHLPS = 1034 , X86_INS_VMOVHPD = 1035 , X86_INS_VMOVHPS = 1036 , X86_INS_VMOVLHPS = 1037 , X86_INS_VMOVLPD = 1038 , X86_INS_VMOVLPS = 1039 , X86_INS_VMOVMSKPD = 1040 , X86_INS_VMOVMSKPS = 1041 , X86_INS_VMOVNTDQA = 1042 , X86_INS_VMOVNTDQ = 1043 , X86_INS_VMOVNTPD = 1044 , X86_INS_VMOVNTPS = 1045 , X86_INS_VMOVSD = 1046 , X86_INS_VMOVSHDUP = 1047 , X86_INS_VMOVSLDUP = 1048 , X86_INS_VMOVSS = 1049 , X86_INS_VMOVUPD = 1050 , X86_INS_VMOVUPS = 1051 , X86_INS_VMPSADBW = 1052 , X86_INS_VMPTRLD = 1053 , X86_INS_VMPTRST = 1054 , X86_INS_VMREAD = 1055 , X86_INS_VMRESUME = 1056 , X86_INS_VMRUN = 1057 , X86_INS_VMSAVE = 1058 , X86_INS_VMULPD = 1059 , X86_INS_VMULPS = 1060 , X86_INS_VMULSD = 1061 , X86_INS_VMULSS = 1062 , X86_INS_VMWRITE = 1063 , X86_INS_VMXOFF = 1064 , X86_INS_VMXON = 1065 , X86_INS_VORPD = 1066 , X86_INS_VORPS = 1067 , X86_INS_VP4DPWSSDS = 1068 , X86_INS_VP4DPWSSD = 1069 , X86_INS_VPABSB = 1070 , X86_INS_VPABSD = 1071 , X86_INS_VPABSQ = 1072 , X86_INS_VPABSW = 1073 , X86_INS_VPACKSSDW = 1074 , X86_INS_VPACKSSWB = 1075 , X86_INS_VPACKUSDW = 1076 , X86_INS_VPACKUSWB = 1077 , X86_INS_VPADDB = 1078 , X86_INS_VPADDD = 1079 , X86_INS_VPADDQ = 1080 , X86_INS_VPADDSB = 1081 , X86_INS_VPADDSW = 1082 , X86_INS_VPADDUSB = 1083 , X86_INS_VPADDUSW = 1084 , X86_INS_VPADDW = 1085 , X86_INS_VPALIGNR = 1086 , X86_INS_VPANDD = 1087 , X86_INS_VPANDND = 1088 , X86_INS_VPANDNQ = 1089 , X86_INS_VPANDN = 1090 , X86_INS_VPANDQ = 1091 , X86_INS_VPAND = 1092 , X86_INS_VPAVGB = 1093 , X86_INS_VPAVGW = 1094 , X86_INS_VPBLENDD = 1095 , X86_INS_VPBLENDMB = 1096 , X86_INS_VPBLENDMD = 1097 , X86_INS_VPBLENDMQ = 1098 , X86_INS_VPBLENDMW = 1099 , X86_INS_VPBLENDVB = 1100 , X86_INS_VPBLENDW = 1101 , X86_INS_VPBROADCASTB = 1102 , X86_INS_VPBROADCASTD = 1103 , X86_INS_VPBROADCASTMB2Q = 1104 , X86_INS_VPBROADCASTMW2D = 1105 , X86_INS_VPBROADCASTQ = 1106 , X86_INS_VPBROADCASTW = 1107 , X86_INS_VPCLMULQDQ = 1108 , X86_INS_VPCMOV = 1109 , X86_INS_VPCMP = 1110 , X86_INS_VPCMPB = 1111 , X86_INS_VPCMPD = 1112 , X86_INS_VPCMPEQB = 1113 , X86_INS_VPCMPEQD = 1114 , X86_INS_VPCMPEQQ = 1115 , X86_INS_VPCMPEQW = 1116 , X86_INS_VPCMPESTRI = 1117 , X86_INS_VPCMPESTRM = 1118 , X86_INS_VPCMPGTB = 1119 , X86_INS_VPCMPGTD = 1120 , X86_INS_VPCMPGTQ = 1121 , X86_INS_VPCMPGTW = 1122 , X86_INS_VPCMPISTRI = 1123 , X86_INS_VPCMPISTRM = 1124 , X86_INS_VPCMPQ = 1125 , X86_INS_VPCMPUB = 1126 , X86_INS_VPCMPUD = 1127 , X86_INS_VPCMPUQ = 1128 , X86_INS_VPCMPUW = 1129 , X86_INS_VPCMPW = 1130 , X86_INS_VPCOM = 1131 , X86_INS_VPCOMB = 1132 , X86_INS_VPCOMD = 1133 , X86_INS_VPCOMPRESSB = 1134 , X86_INS_VPCOMPRESSD = 1135 , X86_INS_VPCOMPRESSQ = 1136 , X86_INS_VPCOMPRESSW = 1137 , X86_INS_VPCOMQ = 1138 , X86_INS_VPCOMUB = 1139 , X86_INS_VPCOMUD = 1140 , X86_INS_VPCOMUQ = 1141 , X86_INS_VPCOMUW = 1142 , X86_INS_VPCOMW = 1143 , X86_INS_VPCONFLICTD = 1144 , X86_INS_VPCONFLICTQ = 1145 , X86_INS_VPDPBUSDS = 1146 , X86_INS_VPDPBUSD = 1147 , X86_INS_VPDPWSSDS = 1148 , X86_INS_VPDPWSSD = 1149 , X86_INS_VPERM2F128 = 1150 , X86_INS_VPERM2I128 = 1151 , X86_INS_VPERMB = 1152 , X86_INS_VPERMD = 1153 , X86_INS_VPERMI2B = 1154 , X86_INS_VPERMI2D = 1155 , X86_INS_VPERMI2PD = 1156 , X86_INS_VPERMI2PS = 1157 , X86_INS_VPERMI2Q = 1158 , X86_INS_VPERMI2W = 1159 , X86_INS_VPERMIL2PD = 1160 , X86_INS_VPERMILPD = 1161 , X86_INS_VPERMIL2PS = 1162 , X86_INS_VPERMILPS = 1163 , X86_INS_VPERMPD = 1164 , X86_INS_VPERMPS = 1165 , X86_INS_VPERMQ = 1166 , X86_INS_VPERMT2B = 1167 , X86_INS_VPERMT2D = 1168 , X86_INS_VPERMT2PD = 1169 , X86_INS_VPERMT2PS = 1170 , X86_INS_VPERMT2Q = 1171 , X86_INS_VPERMT2W = 1172 , X86_INS_VPERMW = 1173 , X86_INS_VPEXPANDB = 1174 , X86_INS_VPEXPANDD = 1175 , X86_INS_VPEXPANDQ = 1176 , X86_INS_VPEXPANDW = 1177 , X86_INS_VPEXTRB = 1178 , X86_INS_VPEXTRD = 1179 , X86_INS_VPEXTRQ = 1180 , X86_INS_VPEXTRW = 1181 , X86_INS_VPGATHERDD = 1182 , X86_INS_VPGATHERDQ = 1183 , X86_INS_VPGATHERQD = 1184 , X86_INS_VPGATHERQQ = 1185 , X86_INS_VPHADDBD = 1186 , X86_INS_VPHADDBQ = 1187 , X86_INS_VPHADDBW = 1188 , X86_INS_VPHADDDQ = 1189 , X86_INS_VPHADDD = 1190 , X86_INS_VPHADDSW = 1191 , X86_INS_VPHADDUBD = 1192 , X86_INS_VPHADDUBQ = 1193 , X86_INS_VPHADDUBW = 1194 , X86_INS_VPHADDUDQ = 1195 , X86_INS_VPHADDUWD = 1196 , X86_INS_VPHADDUWQ = 1197 , X86_INS_VPHADDWD = 1198 , X86_INS_VPHADDWQ = 1199 , X86_INS_VPHADDW = 1200 , X86_INS_VPHMINPOSUW = 1201 , X86_INS_VPHSUBBW = 1202 , X86_INS_VPHSUBDQ = 1203 , X86_INS_VPHSUBD = 1204 , X86_INS_VPHSUBSW = 1205 , X86_INS_VPHSUBWD = 1206 , X86_INS_VPHSUBW = 1207 , X86_INS_VPINSRB = 1208 , X86_INS_VPINSRD = 1209 , X86_INS_VPINSRQ = 1210 , X86_INS_VPINSRW = 1211 , X86_INS_VPLZCNTD = 1212 , X86_INS_VPLZCNTQ = 1213 , X86_INS_VPMACSDD = 1214 , X86_INS_VPMACSDQH = 1215 , X86_INS_VPMACSDQL = 1216 , X86_INS_VPMACSSDD = 1217 , X86_INS_VPMACSSDQH = 1218 , X86_INS_VPMACSSDQL = 1219 , X86_INS_VPMACSSWD = 1220 , X86_INS_VPMACSSWW = 1221 , X86_INS_VPMACSWD = 1222 , X86_INS_VPMACSWW = 1223 , X86_INS_VPMADCSSWD = 1224 , X86_INS_VPMADCSWD = 1225 , X86_INS_VPMADD52HUQ = 1226 , X86_INS_VPMADD52LUQ = 1227 , X86_INS_VPMADDUBSW = 1228 , X86_INS_VPMADDWD = 1229 , X86_INS_VPMASKMOVD = 1230 , X86_INS_VPMASKMOVQ = 1231 , X86_INS_VPMAXSB = 1232 , X86_INS_VPMAXSD = 1233 , X86_INS_VPMAXSQ = 1234 , X86_INS_VPMAXSW = 1235 , X86_INS_VPMAXUB = 1236 , X86_INS_VPMAXUD = 1237 , X86_INS_VPMAXUQ = 1238 , X86_INS_VPMAXUW = 1239 , X86_INS_VPMINSB = 1240 , X86_INS_VPMINSD = 1241 , X86_INS_VPMINSQ = 1242 , X86_INS_VPMINSW = 1243 , X86_INS_VPMINUB = 1244 , X86_INS_VPMINUD = 1245 , X86_INS_VPMINUQ = 1246 , X86_INS_VPMINUW = 1247 , X86_INS_VPMOVB2M = 1248 , X86_INS_VPMOVD2M = 1249 , X86_INS_VPMOVDB = 1250 , X86_INS_VPMOVDW = 1251 , X86_INS_VPMOVM2B = 1252 , X86_INS_VPMOVM2D = 1253 , X86_INS_VPMOVM2Q = 1254 , X86_INS_VPMOVM2W = 1255 , X86_INS_VPMOVMSKB = 1256 , X86_INS_VPMOVQ2M = 1257 , X86_INS_VPMOVQB = 1258 , X86_INS_VPMOVQD = 1259 , X86_INS_VPMOVQW = 1260 , X86_INS_VPMOVSDB = 1261 , X86_INS_VPMOVSDW = 1262 , X86_INS_VPMOVSQB = 1263 , X86_INS_VPMOVSQD = 1264 , X86_INS_VPMOVSQW = 1265 , X86_INS_VPMOVSWB = 1266 , X86_INS_VPMOVSXBD = 1267 , X86_INS_VPMOVSXBQ = 1268 , X86_INS_VPMOVSXBW = 1269 , X86_INS_VPMOVSXDQ = 1270 , X86_INS_VPMOVSXWD = 1271 , X86_INS_VPMOVSXWQ = 1272 , X86_INS_VPMOVUSDB = 1273 , X86_INS_VPMOVUSDW = 1274 , X86_INS_VPMOVUSQB = 1275 , X86_INS_VPMOVUSQD = 1276 , X86_INS_VPMOVUSQW = 1277 , X86_INS_VPMOVUSWB = 1278 , X86_INS_VPMOVW2M = 1279 , X86_INS_VPMOVWB = 1280 , X86_INS_VPMOVZXBD = 1281 , X86_INS_VPMOVZXBQ = 1282 , X86_INS_VPMOVZXBW = 1283 , X86_INS_VPMOVZXDQ = 1284 , X86_INS_VPMOVZXWD = 1285 , X86_INS_VPMOVZXWQ = 1286 , X86_INS_VPMULDQ = 1287 , X86_INS_VPMULHRSW = 1288 , X86_INS_VPMULHUW = 1289 , X86_INS_VPMULHW = 1290 , X86_INS_VPMULLD = 1291 , X86_INS_VPMULLQ = 1292 , X86_INS_VPMULLW = 1293 , X86_INS_VPMULTISHIFTQB = 1294 , X86_INS_VPMULUDQ = 1295 , X86_INS_VPOPCNTB = 1296 , X86_INS_VPOPCNTD = 1297 , X86_INS_VPOPCNTQ = 1298 , X86_INS_VPOPCNTW = 1299 , X86_INS_VPORD = 1300 , X86_INS_VPORQ = 1301 , X86_INS_VPOR = 1302 , X86_INS_VPPERM = 1303 , X86_INS_VPROLD = 1304 , X86_INS_VPROLQ = 1305 , X86_INS_VPROLVD = 1306 , X86_INS_VPROLVQ = 1307 , X86_INS_VPRORD = 1308 , X86_INS_VPRORQ = 1309 , X86_INS_VPRORVD = 1310 , X86_INS_VPRORVQ = 1311 , X86_INS_VPROTB = 1312 , X86_INS_VPROTD = 1313 , X86_INS_VPROTQ = 1314 , X86_INS_VPROTW = 1315 , X86_INS_VPSADBW = 1316 , X86_INS_VPSCATTERDD = 1317 , X86_INS_VPSCATTERDQ = 1318 , X86_INS_VPSCATTERQD = 1319 , X86_INS_VPSCATTERQQ = 1320 , X86_INS_VPSHAB = 1321 , X86_INS_VPSHAD = 1322 , X86_INS_VPSHAQ = 1323 , X86_INS_VPSHAW = 1324 , X86_INS_VPSHLB = 1325 , X86_INS_VPSHLDD = 1326 , X86_INS_VPSHLDQ = 1327 , X86_INS_VPSHLDVD = 1328 , X86_INS_VPSHLDVQ = 1329 , X86_INS_VPSHLDVW = 1330 , X86_INS_VPSHLDW = 1331 , X86_INS_VPSHLD = 1332 , X86_INS_VPSHLQ = 1333 , X86_INS_VPSHLW = 1334 , X86_INS_VPSHRDD = 1335 , X86_INS_VPSHRDQ = 1336 , X86_INS_VPSHRDVD = 1337 , X86_INS_VPSHRDVQ = 1338 , X86_INS_VPSHRDVW = 1339 , X86_INS_VPSHRDW = 1340 , X86_INS_VPSHUFBITQMB = 1341 , X86_INS_VPSHUFB = 1342 , X86_INS_VPSHUFD = 1343 , X86_INS_VPSHUFHW = 1344 , X86_INS_VPSHUFLW = 1345 , X86_INS_VPSIGNB = 1346 , X86_INS_VPSIGND = 1347 , X86_INS_VPSIGNW = 1348 , X86_INS_VPSLLDQ = 1349 , X86_INS_VPSLLD = 1350 , X86_INS_VPSLLQ = 1351 , X86_INS_VPSLLVD = 1352 , X86_INS_VPSLLVQ = 1353 , X86_INS_VPSLLVW = 1354 , X86_INS_VPSLLW = 1355 , X86_INS_VPSRAD = 1356 , X86_INS_VPSRAQ = 1357 , X86_INS_VPSRAVD = 1358 , X86_INS_VPSRAVQ = 1359 , X86_INS_VPSRAVW = 1360 , X86_INS_VPSRAW = 1361 , X86_INS_VPSRLDQ = 1362 , X86_INS_VPSRLD = 1363 , X86_INS_VPSRLQ = 1364 , X86_INS_VPSRLVD = 1365 , X86_INS_VPSRLVQ = 1366 , X86_INS_VPSRLVW = 1367 , X86_INS_VPSRLW = 1368 , X86_INS_VPSUBB = 1369 , X86_INS_VPSUBD = 1370 , X86_INS_VPSUBQ = 1371 , X86_INS_VPSUBSB = 1372 , X86_INS_VPSUBSW = 1373 , X86_INS_VPSUBUSB = 1374 , X86_INS_VPSUBUSW = 1375 , X86_INS_VPSUBW = 1376 , X86_INS_VPTERNLOGD = 1377 , X86_INS_VPTERNLOGQ = 1378 , X86_INS_VPTESTMB = 1379 , X86_INS_VPTESTMD = 1380 , X86_INS_VPTESTMQ = 1381 , X86_INS_VPTESTMW = 1382 , X86_INS_VPTESTNMB = 1383 , X86_INS_VPTESTNMD = 1384 , X86_INS_VPTESTNMQ = 1385 , X86_INS_VPTESTNMW = 1386 , X86_INS_VPTEST = 1387 , X86_INS_VPUNPCKHBW = 1388 , X86_INS_VPUNPCKHDQ = 1389 , X86_INS_VPUNPCKHQDQ = 1390 , X86_INS_VPUNPCKHWD = 1391 , X86_INS_VPUNPCKLBW = 1392 , X86_INS_VPUNPCKLDQ = 1393 , X86_INS_VPUNPCKLQDQ = 1394 , X86_INS_VPUNPCKLWD = 1395 , X86_INS_VPXORD = 1396 , X86_INS_VPXORQ = 1397 , X86_INS_VPXOR = 1398 , X86_INS_VRANGEPD = 1399 , X86_INS_VRANGEPS = 1400 , X86_INS_VRANGESD = 1401 , X86_INS_VRANGESS = 1402 , X86_INS_VRCP14PD = 1403 , X86_INS_VRCP14PS = 1404 , X86_INS_VRCP14SD = 1405 , X86_INS_VRCP14SS = 1406 , X86_INS_VRCP28PD = 1407 , X86_INS_VRCP28PS = 1408 , X86_INS_VRCP28SD = 1409 , X86_INS_VRCP28SS = 1410 , X86_INS_VRCPPS = 1411 , X86_INS_VRCPSS = 1412 , X86_INS_VREDUCEPD = 1413 , X86_INS_VREDUCEPS = 1414 , X86_INS_VREDUCESD = 1415 , X86_INS_VREDUCESS = 1416 , X86_INS_VRNDSCALEPD = 1417 , X86_INS_VRNDSCALEPS = 1418 , X86_INS_VRNDSCALESD = 1419 , X86_INS_VRNDSCALESS = 1420 , X86_INS_VROUNDPD = 1421 , X86_INS_VROUNDPS = 1422 , X86_INS_VROUNDSD = 1423 , X86_INS_VROUNDSS = 1424 , X86_INS_VRSQRT14PD = 1425 , X86_INS_VRSQRT14PS = 1426 , X86_INS_VRSQRT14SD = 1427 , X86_INS_VRSQRT14SS = 1428 , X86_INS_VRSQRT28PD = 1429 , X86_INS_VRSQRT28PS = 1430 , X86_INS_VRSQRT28SD = 1431 , X86_INS_VRSQRT28SS = 1432 , X86_INS_VRSQRTPS = 1433 , X86_INS_VRSQRTSS = 1434 , X86_INS_VSCALEFPD = 1435 , X86_INS_VSCALEFPS = 1436 , X86_INS_VSCALEFSD = 1437 , X86_INS_VSCALEFSS = 1438 , X86_INS_VSCATTERDPD = 1439 , X86_INS_VSCATTERDPS = 1440 , X86_INS_VSCATTERPF0DPD = 1441 , X86_INS_VSCATTERPF0DPS = 1442 , X86_INS_VSCATTERPF0QPD = 1443 , X86_INS_VSCATTERPF0QPS = 1444 , X86_INS_VSCATTERPF1DPD = 1445 , X86_INS_VSCATTERPF1DPS = 1446 , X86_INS_VSCATTERPF1QPD = 1447 , X86_INS_VSCATTERPF1QPS = 1448 , X86_INS_VSCATTERQPD = 1449 , X86_INS_VSCATTERQPS = 1450 , X86_INS_VSHUFF32X4 = 1451 , X86_INS_VSHUFF64X2 = 1452 , X86_INS_VSHUFI32X4 = 1453 , X86_INS_VSHUFI64X2 = 1454 , X86_INS_VSHUFPD = 1455 , X86_INS_VSHUFPS = 1456 , X86_INS_VSQRTPD = 1457 , X86_INS_VSQRTPS = 1458 , X86_INS_VSQRTSD = 1459 , X86_INS_VSQRTSS = 1460 , X86_INS_VSTMXCSR = 1461 , X86_INS_VSUBPD = 1462 , X86_INS_VSUBPS = 1463 , X86_INS_VSUBSD = 1464 , X86_INS_VSUBSS = 1465 , X86_INS_VTESTPD = 1466 , X86_INS_VTESTPS = 1467 , X86_INS_VUCOMISD = 1468 , X86_INS_VUCOMISS = 1469 , X86_INS_VUNPCKHPD = 1470 , X86_INS_VUNPCKHPS = 1471 , X86_INS_VUNPCKLPD = 1472 , X86_INS_VUNPCKLPS = 1473 , X86_INS_VXORPD = 1474 , X86_INS_VXORPS = 1475 , X86_INS_VZEROALL = 1476 , X86_INS_VZEROUPPER = 1477 , X86_INS_WAIT = 1478 , X86_INS_WBINVD = 1479 , X86_INS_WBNOINVD = 1480 , X86_INS_WRFSBASE = 1481 , X86_INS_WRGSBASE = 1482 , X86_INS_WRMSR = 1483 , X86_INS_WRPKRU = 1484 , X86_INS_WRSSD = 1485 , X86_INS_WRSSQ = 1486 , X86_INS_WRUSSD = 1487 , X86_INS_WRUSSQ = 1488 , X86_INS_XABORT = 1489 , X86_INS_XACQUIRE = 1490 , X86_INS_XADD = 1491 , X86_INS_XBEGIN = 1492 , X86_INS_XCHG = 1493 , X86_INS_FXCH = 1494 , X86_INS_XCRYPTCBC = 1495 , X86_INS_XCRYPTCFB = 1496 , X86_INS_XCRYPTCTR = 1497 , X86_INS_XCRYPTECB = 1498 , X86_INS_XCRYPTOFB = 1499 , X86_INS_XEND = 1500 , X86_INS_XGETBV = 1501 , X86_INS_XLATB = 1502 , X86_INS_XOR = 1503 , X86_INS_XORPD = 1504 , X86_INS_XORPS = 1505 , X86_INS_XRELEASE = 1506 , X86_INS_XRSTOR = 1507 , X86_INS_XRSTOR64 = 1508 , X86_INS_XRSTORS = 1509 , X86_INS_XRSTORS64 = 1510 , X86_INS_XSAVE = 1511 , X86_INS_XSAVE64 = 1512 , X86_INS_XSAVEC = 1513 , X86_INS_XSAVEC64 = 1514 , X86_INS_XSAVEOPT = 1515 , X86_INS_XSAVEOPT64 = 1516 , X86_INS_XSAVES = 1517 , X86_INS_XSAVES64 = 1518 , X86_INS_XSETBV = 1519 , X86_INS_XSHA1 = 1520 , X86_INS_XSHA256 = 1521 , X86_INS_XSTORE = 1522 , X86_INS_XTEST = 1523 , X86_INS_ENDING = 1524 , } # [repr (u32)] # [doc = " Group of X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn_group { # [doc = "< = CS_GRP_INVALID"] X86_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] X86_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] X86_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] X86_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] X86_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] X86_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] X86_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] X86_GRP_BRANCH_RELATIVE = 7 , # [doc = "< all virtualization instructions (VT-x + AMD-V)"] X86_GRP_VM = 128 , X86_GRP_3DNOW = 129 , X86_GRP_AES = 130 , X86_GRP_ADX = 131 , X86_GRP_AVX = 132 , X86_GRP_AVX2 = 133 , X86_GRP_AVX512 = 134 , X86_GRP_BMI = 135 , X86_GRP_BMI2 = 136 , X86_GRP_CMOV = 137 , X86_GRP_F16C = 138 , X86_GRP_FMA = 139 , X86_GRP_FMA4 = 140 , X86_GRP_FSGSBASE = 141 , X86_GRP_HLE = 142 , X86_GRP_MMX = 143 , X86_GRP_MODE32 = 144 , X86_GRP_MODE64 = 145 , X86_GRP_RTM = 146 , X86_GRP_SHA = 147 , X86_GRP_SSE1 = 148 , X86_GRP_SSE2 = 149 , X86_GRP_SSE3 = 150 , X86_GRP_SSE41 = 151 , X86_GRP_SSE42 = 152 , X86_GRP_SSE4A = 153 , X86_GRP_SSSE3 = 154 , X86_GRP_PCLMUL = 155 , X86_GRP_XOP = 156 , X86_GRP_CDI = 157 , X86_GRP_ERI = 158 , X86_GRP_TBM = 159 , X86_GRP_16BITMODE = 160 , X86_GRP_NOT64BITMODE = 161 , X86_GRP_SGX = 162 , X86_GRP_DQI = 163 , X86_GRP_BWI = 164 , X86_GRP_PFI = 165 , X86_GRP_VLX = 166 , X86_GRP_SMAP = 167 , X86_GRP_NOVLX = 168 , X86_GRP_FPU = 169 , X86_GRP_ENDING = 170 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] XCORE_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] XCORE_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] XCORE_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] XCORE_OP_MEM = 3 , } # [repr (u32)] # [doc = " XCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_reg { XCORE_REG_INVALID = 0 , XCORE_REG_CP = 1 , XCORE_REG_DP = 2 , XCORE_REG_LR = 3 , XCORE_REG_SP = 4 , XCORE_REG_R0 = 5 , XCORE_REG_R1 = 6 , XCORE_REG_R2 = 7 , XCORE_REG_R3 = 8 , XCORE_REG_R4 = 9 , XCORE_REG_R5 = 10 , XCORE_REG_R6 = 11 , XCORE_REG_R7 = 12 , XCORE_REG_R8 = 13 , XCORE_REG_R9 = 14 , XCORE_REG_R10 = 15 , XCORE_REG_R11 = 16 , # [doc = "< pc"] XCORE_REG_PC = 17 , # [doc = "< save pc"] XCORE_REG_SCP = 18 , XCORE_REG_SSR = 19 , XCORE_REG_ET = 20 , XCORE_REG_ED = 21 , XCORE_REG_SED = 22 , XCORE_REG_KEP = 23 , XCORE_REG_KSP = 24 , XCORE_REG_ID = 25 , XCORE_REG_ENDING = 26 , } # [doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct xcore_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , # [doc = "< +1: forward, -1: backward"] pub direct : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of xcore_op_mem"] [:: std :: mem :: size_of :: < xcore_op_mem > () - 12usize] ; ["Alignment of xcore_op_mem"] [:: std :: mem :: align_of :: < xcore_op_mem > () - 4usize] ; ["Offset of field: xcore_op_mem::base"] [:: std :: mem :: offset_of ! (xcore_op_mem , base) - 0usize] ; ["Offset of field: xcore_op_mem::index"] [:: std :: mem :: offset_of ! (xcore_op_mem , index) - 1usize] ; ["Offset of field: xcore_op_mem::disp"] [:: std :: mem :: offset_of ! (xcore_op_mem , disp) - 4usize] ; ["Offset of field: xcore_op_mem::direct"] [:: std :: mem :: offset_of ! (xcore_op_mem , direct) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore_op { # [doc = "< operand type"] pub type_ : xcore_op_type , pub __bindgen_anon_1 : cs_xcore_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_xcore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : xcore_reg , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : xcore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_xcore_op__bindgen_ty_1 > () - 12usize] ; ["Alignment of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_xcore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op"] [:: std :: mem :: size_of :: < cs_xcore_op > () - 16usize] ; ["Alignment of cs_xcore_op"] [:: std :: mem :: align_of :: < cs_xcore_op > () - 4usize] ; ["Offset of field: cs_xcore_op::type_"] [:: std :: mem :: offset_of ! (cs_xcore_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_xcore_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore"] [:: std :: mem :: size_of :: < cs_xcore > () - 132usize] ; ["Alignment of cs_xcore"] [:: std :: mem :: align_of :: < cs_xcore > () - 4usize] ; ["Offset of field: cs_xcore::op_count"] [:: std :: mem :: offset_of ! (cs_xcore , op_count) - 0usize] ; ["Offset of field: cs_xcore::operands"] [:: std :: mem :: offset_of ! (cs_xcore , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " XCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn { XCORE_INS_INVALID = 0 , XCORE_INS_ADD = 1 , XCORE_INS_ANDNOT = 2 , XCORE_INS_AND = 3 , XCORE_INS_ASHR = 4 , XCORE_INS_BAU = 5 , XCORE_INS_BITREV = 6 , XCORE_INS_BLA = 7 , XCORE_INS_BLAT = 8 , XCORE_INS_BL = 9 , XCORE_INS_BF = 10 , XCORE_INS_BT = 11 , XCORE_INS_BU = 12 , XCORE_INS_BRU = 13 , XCORE_INS_BYTEREV = 14 , XCORE_INS_CHKCT = 15 , XCORE_INS_CLRE = 16 , XCORE_INS_CLRPT = 17 , XCORE_INS_CLRSR = 18 , XCORE_INS_CLZ = 19 , XCORE_INS_CRC8 = 20 , XCORE_INS_CRC32 = 21 , XCORE_INS_DCALL = 22 , XCORE_INS_DENTSP = 23 , XCORE_INS_DGETREG = 24 , XCORE_INS_DIVS = 25 , XCORE_INS_DIVU = 26 , XCORE_INS_DRESTSP = 27 , XCORE_INS_DRET = 28 , XCORE_INS_ECALLF = 29 , XCORE_INS_ECALLT = 30 , XCORE_INS_EDU = 31 , XCORE_INS_EEF = 32 , XCORE_INS_EET = 33 , XCORE_INS_EEU = 34 , XCORE_INS_ENDIN = 35 , XCORE_INS_ENTSP = 36 , XCORE_INS_EQ = 37 , XCORE_INS_EXTDP = 38 , XCORE_INS_EXTSP = 39 , XCORE_INS_FREER = 40 , XCORE_INS_FREET = 41 , XCORE_INS_GETD = 42 , XCORE_INS_GET = 43 , XCORE_INS_GETN = 44 , XCORE_INS_GETR = 45 , XCORE_INS_GETSR = 46 , XCORE_INS_GETST = 47 , XCORE_INS_GETTS = 48 , XCORE_INS_INCT = 49 , XCORE_INS_INIT = 50 , XCORE_INS_INPW = 51 , XCORE_INS_INSHR = 52 , XCORE_INS_INT = 53 , XCORE_INS_IN = 54 , XCORE_INS_KCALL = 55 , XCORE_INS_KENTSP = 56 , XCORE_INS_KRESTSP = 57 , XCORE_INS_KRET = 58 , XCORE_INS_LADD = 59 , XCORE_INS_LD16S = 60 , XCORE_INS_LD8U = 61 , XCORE_INS_LDA16 = 62 , XCORE_INS_LDAP = 63 , XCORE_INS_LDAW = 64 , XCORE_INS_LDC = 65 , XCORE_INS_LDW = 66 , XCORE_INS_LDIVU = 67 , XCORE_INS_LMUL = 68 , XCORE_INS_LSS = 69 , XCORE_INS_LSUB = 70 , XCORE_INS_LSU = 71 , XCORE_INS_MACCS = 72 , XCORE_INS_MACCU = 73 , XCORE_INS_MJOIN = 74 , XCORE_INS_MKMSK = 75 , XCORE_INS_MSYNC = 76 , XCORE_INS_MUL = 77 , XCORE_INS_NEG = 78 , XCORE_INS_NOT = 79 , XCORE_INS_OR = 80 , XCORE_INS_OUTCT = 81 , XCORE_INS_OUTPW = 82 , XCORE_INS_OUTSHR = 83 , XCORE_INS_OUTT = 84 , XCORE_INS_OUT = 85 , XCORE_INS_PEEK = 86 , XCORE_INS_REMS = 87 , XCORE_INS_REMU = 88 , XCORE_INS_RETSP = 89 , XCORE_INS_SETCLK = 90 , XCORE_INS_SET = 91 , XCORE_INS_SETC = 92 , XCORE_INS_SETD = 93 , XCORE_INS_SETEV = 94 , XCORE_INS_SETN = 95 , XCORE_INS_SETPSC = 96 , XCORE_INS_SETPT = 97 , XCORE_INS_SETRDY = 98 , XCORE_INS_SETSR = 99 , XCORE_INS_SETTW = 100 , XCORE_INS_SETV = 101 , XCORE_INS_SEXT = 102 , XCORE_INS_SHL = 103 , XCORE_INS_SHR = 104 , XCORE_INS_SSYNC = 105 , XCORE_INS_ST16 = 106 , XCORE_INS_ST8 = 107 , XCORE_INS_STW = 108 , XCORE_INS_SUB = 109 , XCORE_INS_SYNCR = 110 , XCORE_INS_TESTCT = 111 , XCORE_INS_TESTLCL = 112 , XCORE_INS_TESTWCT = 113 , XCORE_INS_TSETMR = 114 , XCORE_INS_START = 115 , XCORE_INS_WAITEF = 116 , XCORE_INS_WAITET = 117 , XCORE_INS_WAITEU = 118 , XCORE_INS_XOR = 119 , XCORE_INS_ZEXT = 120 , XCORE_INS_ENDING = 121 , } # [repr (u32)] # [doc = " Group of XCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn_group { # [doc = "< = CS_GRP_INVALID"] XCORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] XCORE_GRP_JUMP = 1 , XCORE_GRP_ENDING = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] TMS320C64X_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] TMS320C64X_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] TMS320C64X_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] TMS320C64X_OP_MEM = 3 , # [doc = "< Register pair for double word ops"] TMS320C64X_OP_REGPAIR = 64 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0 , TMS320C64X_MEM_DISP_CONSTANT = 1 , TMS320C64X_MEM_DISP_REGISTER = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0 , TMS320C64X_MEM_DIR_FW = 1 , TMS320C64X_MEM_DIR_BW = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0 , TMS320C64X_MEM_MOD_NO = 1 , TMS320C64X_MEM_MOD_PRE = 2 , TMS320C64X_MEM_MOD_POST = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tms320c64x_op_mem { # [doc = "< base register"] pub base : :: std :: os :: raw :: c_uint , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_uint , # [doc = "< unit of base and offset register"] pub unit : :: std :: os :: raw :: c_uint , # [doc = "< offset scaled"] pub scaled : :: std :: os :: raw :: c_uint , # [doc = "< displacement type"] pub disptype : :: std :: os :: raw :: c_uint , # [doc = "< direction"] pub direction : :: std :: os :: raw :: c_uint , # [doc = "< modification"] pub modify : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tms320c64x_op_mem"] [:: std :: mem :: size_of :: < tms320c64x_op_mem > () - 28usize] ; ["Alignment of tms320c64x_op_mem"] [:: std :: mem :: align_of :: < tms320c64x_op_mem > () - 4usize] ; ["Offset of field: tms320c64x_op_mem::base"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , base) - 0usize] ; ["Offset of field: tms320c64x_op_mem::disp"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disp) - 4usize] ; ["Offset of field: tms320c64x_op_mem::unit"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , unit) - 8usize] ; ["Offset of field: tms320c64x_op_mem::scaled"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , scaled) - 12usize] ; ["Offset of field: tms320c64x_op_mem::disptype"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disptype) - 16usize] ; ["Offset of field: tms320c64x_op_mem::direction"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , direction) - 20usize] ; ["Offset of field: tms320c64x_op_mem::modify"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , modify) - 24usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x_op { # [doc = "< operand type"] pub type_ : tms320c64x_op_type , pub __bindgen_anon_1 : cs_tms320c64x_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tms320c64x_op__bindgen_ty_1 { # [doc = "< register value for REG operand or first register for REGPAIR operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tms320c64x_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 28usize] ; ["Alignment of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op"] [:: std :: mem :: size_of :: < cs_tms320c64x_op > () - 32usize] ; ["Alignment of cs_tms320c64x_op"] [:: std :: mem :: align_of :: < cs_tms320c64x_op > () - 4usize] ; ["Offset of field: cs_tms320c64x_op::type_"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x { pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tms320c64x_op ; 8usize] , pub condition : cs_tms320c64x__bindgen_ty_1 , pub funit : cs_tms320c64x__bindgen_ty_2 , pub parallel : :: std :: os :: raw :: c_uint , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub zero : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::zero"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , zero) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_2 { pub unit : :: std :: os :: raw :: c_uint , pub side : :: std :: os :: raw :: c_uint , pub crosspath : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_2 > () - 12usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_2 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::unit"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , unit) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::side"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , side) - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::crosspath"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , crosspath) - 8usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x"] [:: std :: mem :: size_of :: < cs_tms320c64x > () - 284usize] ; ["Alignment of cs_tms320c64x"] [:: std :: mem :: align_of :: < cs_tms320c64x > () - 4usize] ; ["Offset of field: cs_tms320c64x::op_count"] [:: std :: mem :: offset_of ! (cs_tms320c64x , op_count) - 0usize] ; ["Offset of field: cs_tms320c64x::operands"] [:: std :: mem :: offset_of ! (cs_tms320c64x , operands) - 4usize] ; ["Offset of field: cs_tms320c64x::condition"] [:: std :: mem :: offset_of ! (cs_tms320c64x , condition) - 260usize] ; ["Offset of field: cs_tms320c64x::funit"] [:: std :: mem :: offset_of ! (cs_tms320c64x , funit) - 268usize] ; ["Offset of field: cs_tms320c64x::parallel"] [:: std :: mem :: offset_of ! (cs_tms320c64x , parallel) - 280usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel) } } impl tms320c64x_reg { pub const TMS320C64X_REG_EFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ECR ; } impl tms320c64x_reg { pub const TMS320C64X_REG_IFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ISR ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0 , TMS320C64X_REG_AMR = 1 , TMS320C64X_REG_CSR = 2 , TMS320C64X_REG_DIER = 3 , TMS320C64X_REG_DNUM = 4 , TMS320C64X_REG_ECR = 5 , TMS320C64X_REG_GFPGFR = 6 , TMS320C64X_REG_GPLYA = 7 , TMS320C64X_REG_GPLYB = 8 , TMS320C64X_REG_ICR = 9 , TMS320C64X_REG_IER = 10 , TMS320C64X_REG_IERR = 11 , TMS320C64X_REG_ILC = 12 , TMS320C64X_REG_IRP = 13 , TMS320C64X_REG_ISR = 14 , TMS320C64X_REG_ISTP = 15 , TMS320C64X_REG_ITSR = 16 , TMS320C64X_REG_NRP = 17 , TMS320C64X_REG_NTSR = 18 , TMS320C64X_REG_REP = 19 , TMS320C64X_REG_RILC = 20 , TMS320C64X_REG_SSR = 21 , TMS320C64X_REG_TSCH = 22 , TMS320C64X_REG_TSCL = 23 , TMS320C64X_REG_TSR = 24 , TMS320C64X_REG_A0 = 25 , TMS320C64X_REG_A1 = 26 , TMS320C64X_REG_A2 = 27 , TMS320C64X_REG_A3 = 28 , TMS320C64X_REG_A4 = 29 , TMS320C64X_REG_A5 = 30 , TMS320C64X_REG_A6 = 31 , TMS320C64X_REG_A7 = 32 , TMS320C64X_REG_A8 = 33 , TMS320C64X_REG_A9 = 34 , TMS320C64X_REG_A10 = 35 , TMS320C64X_REG_A11 = 36 , TMS320C64X_REG_A12 = 37 , TMS320C64X_REG_A13 = 38 , TMS320C64X_REG_A14 = 39 , TMS320C64X_REG_A15 = 40 , TMS320C64X_REG_A16 = 41 , TMS320C64X_REG_A17 = 42 , TMS320C64X_REG_A18 = 43 , TMS320C64X_REG_A19 = 44 , TMS320C64X_REG_A20 = 45 , TMS320C64X_REG_A21 = 46 , TMS320C64X_REG_A22 = 47 , TMS320C64X_REG_A23 = 48 , TMS320C64X_REG_A24 = 49 , TMS320C64X_REG_A25 = 50 , TMS320C64X_REG_A26 = 51 , TMS320C64X_REG_A27 = 52 , TMS320C64X_REG_A28 = 53 , TMS320C64X_REG_A29 = 54 , TMS320C64X_REG_A30 = 55 , TMS320C64X_REG_A31 = 56 , TMS320C64X_REG_B0 = 57 , TMS320C64X_REG_B1 = 58 , TMS320C64X_REG_B2 = 59 , TMS320C64X_REG_B3 = 60 , TMS320C64X_REG_B4 = 61 , TMS320C64X_REG_B5 = 62 , TMS320C64X_REG_B6 = 63 , TMS320C64X_REG_B7 = 64 , TMS320C64X_REG_B8 = 65 , TMS320C64X_REG_B9 = 66 , TMS320C64X_REG_B10 = 67 , TMS320C64X_REG_B11 = 68 , TMS320C64X_REG_B12 = 69 , TMS320C64X_REG_B13 = 70 , TMS320C64X_REG_B14 = 71 , TMS320C64X_REG_B15 = 72 , TMS320C64X_REG_B16 = 73 , TMS320C64X_REG_B17 = 74 , TMS320C64X_REG_B18 = 75 , TMS320C64X_REG_B19 = 76 , TMS320C64X_REG_B20 = 77 , TMS320C64X_REG_B21 = 78 , TMS320C64X_REG_B22 = 79 , TMS320C64X_REG_B23 = 80 , TMS320C64X_REG_B24 = 81 , TMS320C64X_REG_B25 = 82 , TMS320C64X_REG_B26 = 83 , TMS320C64X_REG_B27 = 84 , TMS320C64X_REG_B28 = 85 , TMS320C64X_REG_B29 = 86 , TMS320C64X_REG_B30 = 87 , TMS320C64X_REG_B31 = 88 , TMS320C64X_REG_PCE1 = 89 , TMS320C64X_REG_ENDING = 90 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0 , TMS320C64X_INS_ABS = 1 , TMS320C64X_INS_ABS2 = 2 , TMS320C64X_INS_ADD = 3 , TMS320C64X_INS_ADD2 = 4 , TMS320C64X_INS_ADD4 = 5 , TMS320C64X_INS_ADDAB = 6 , TMS320C64X_INS_ADDAD = 7 , TMS320C64X_INS_ADDAH = 8 , TMS320C64X_INS_ADDAW = 9 , TMS320C64X_INS_ADDK = 10 , TMS320C64X_INS_ADDKPC = 11 , TMS320C64X_INS_ADDU = 12 , TMS320C64X_INS_AND = 13 , TMS320C64X_INS_ANDN = 14 , TMS320C64X_INS_AVG2 = 15 , TMS320C64X_INS_AVGU4 = 16 , TMS320C64X_INS_B = 17 , TMS320C64X_INS_BDEC = 18 , TMS320C64X_INS_BITC4 = 19 , TMS320C64X_INS_BNOP = 20 , TMS320C64X_INS_BPOS = 21 , TMS320C64X_INS_CLR = 22 , TMS320C64X_INS_CMPEQ = 23 , TMS320C64X_INS_CMPEQ2 = 24 , TMS320C64X_INS_CMPEQ4 = 25 , TMS320C64X_INS_CMPGT = 26 , TMS320C64X_INS_CMPGT2 = 27 , TMS320C64X_INS_CMPGTU4 = 28 , TMS320C64X_INS_CMPLT = 29 , TMS320C64X_INS_CMPLTU = 30 , TMS320C64X_INS_DEAL = 31 , TMS320C64X_INS_DOTP2 = 32 , TMS320C64X_INS_DOTPN2 = 33 , TMS320C64X_INS_DOTPNRSU2 = 34 , TMS320C64X_INS_DOTPRSU2 = 35 , TMS320C64X_INS_DOTPSU4 = 36 , TMS320C64X_INS_DOTPU4 = 37 , TMS320C64X_INS_EXT = 38 , TMS320C64X_INS_EXTU = 39 , TMS320C64X_INS_GMPGTU = 40 , TMS320C64X_INS_GMPY4 = 41 , TMS320C64X_INS_LDB = 42 , TMS320C64X_INS_LDBU = 43 , TMS320C64X_INS_LDDW = 44 , TMS320C64X_INS_LDH = 45 , TMS320C64X_INS_LDHU = 46 , TMS320C64X_INS_LDNDW = 47 , TMS320C64X_INS_LDNW = 48 , TMS320C64X_INS_LDW = 49 , TMS320C64X_INS_LMBD = 50 , TMS320C64X_INS_MAX2 = 51 , TMS320C64X_INS_MAXU4 = 52 , TMS320C64X_INS_MIN2 = 53 , TMS320C64X_INS_MINU4 = 54 , TMS320C64X_INS_MPY = 55 , TMS320C64X_INS_MPY2 = 56 , TMS320C64X_INS_MPYH = 57 , TMS320C64X_INS_MPYHI = 58 , TMS320C64X_INS_MPYHIR = 59 , TMS320C64X_INS_MPYHL = 60 , TMS320C64X_INS_MPYHLU = 61 , TMS320C64X_INS_MPYHSLU = 62 , TMS320C64X_INS_MPYHSU = 63 , TMS320C64X_INS_MPYHU = 64 , TMS320C64X_INS_MPYHULS = 65 , TMS320C64X_INS_MPYHUS = 66 , TMS320C64X_INS_MPYLH = 67 , TMS320C64X_INS_MPYLHU = 68 , TMS320C64X_INS_MPYLI = 69 , TMS320C64X_INS_MPYLIR = 70 , TMS320C64X_INS_MPYLSHU = 71 , TMS320C64X_INS_MPYLUHS = 72 , TMS320C64X_INS_MPYSU = 73 , TMS320C64X_INS_MPYSU4 = 74 , TMS320C64X_INS_MPYU = 75 , TMS320C64X_INS_MPYU4 = 76 , TMS320C64X_INS_MPYUS = 77 , TMS320C64X_INS_MVC = 78 , TMS320C64X_INS_MVD = 79 , TMS320C64X_INS_MVK = 80 , TMS320C64X_INS_MVKL = 81 , TMS320C64X_INS_MVKLH = 82 , TMS320C64X_INS_NOP = 83 , TMS320C64X_INS_NORM = 84 , TMS320C64X_INS_OR = 85 , TMS320C64X_INS_PACK2 = 86 , TMS320C64X_INS_PACKH2 = 87 , TMS320C64X_INS_PACKH4 = 88 , TMS320C64X_INS_PACKHL2 = 89 , TMS320C64X_INS_PACKL4 = 90 , TMS320C64X_INS_PACKLH2 = 91 , TMS320C64X_INS_ROTL = 92 , TMS320C64X_INS_SADD = 93 , TMS320C64X_INS_SADD2 = 94 , TMS320C64X_INS_SADDU4 = 95 , TMS320C64X_INS_SADDUS2 = 96 , TMS320C64X_INS_SAT = 97 , TMS320C64X_INS_SET = 98 , TMS320C64X_INS_SHFL = 99 , TMS320C64X_INS_SHL = 100 , TMS320C64X_INS_SHLMB = 101 , TMS320C64X_INS_SHR = 102 , TMS320C64X_INS_SHR2 = 103 , TMS320C64X_INS_SHRMB = 104 , TMS320C64X_INS_SHRU = 105 , TMS320C64X_INS_SHRU2 = 106 , TMS320C64X_INS_SMPY = 107 , TMS320C64X_INS_SMPY2 = 108 , TMS320C64X_INS_SMPYH = 109 , TMS320C64X_INS_SMPYHL = 110 , TMS320C64X_INS_SMPYLH = 111 , TMS320C64X_INS_SPACK2 = 112 , TMS320C64X_INS_SPACKU4 = 113 , TMS320C64X_INS_SSHL = 114 , TMS320C64X_INS_SSHVL = 115 , TMS320C64X_INS_SSHVR = 116 , TMS320C64X_INS_SSUB = 117 , TMS320C64X_INS_STB = 118 , TMS320C64X_INS_STDW = 119 , TMS320C64X_INS_STH = 120 , TMS320C64X_INS_STNDW = 121 , TMS320C64X_INS_STNW = 122 , TMS320C64X_INS_STW = 123 , TMS320C64X_INS_SUB = 124 , TMS320C64X_INS_SUB2 = 125 , TMS320C64X_INS_SUB4 = 126 , TMS320C64X_INS_SUBAB = 127 , TMS320C64X_INS_SUBABS4 = 128 , TMS320C64X_INS_SUBAH = 129 , TMS320C64X_INS_SUBAW = 130 , TMS320C64X_INS_SUBC = 131 , TMS320C64X_INS_SUBU = 132 , TMS320C64X_INS_SWAP4 = 133 , TMS320C64X_INS_UNPKHU4 = 134 , TMS320C64X_INS_UNPKLU4 = 135 , TMS320C64X_INS_XOR = 136 , TMS320C64X_INS_XPND2 = 137 , TMS320C64X_INS_XPND4 = 138 , TMS320C64X_INS_IDLE = 139 , TMS320C64X_INS_MV = 140 , TMS320C64X_INS_NEG = 141 , TMS320C64X_INS_NOT = 142 , TMS320C64X_INS_SWAP2 = 143 , TMS320C64X_INS_ZERO = 144 , TMS320C64X_INS_ENDING = 145 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn_group { # [doc = "< = CS_GRP_INVALID"] TMS320C64X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] TMS320C64X_GRP_JUMP = 1 , TMS320C64X_GRP_FUNIT_D = 128 , TMS320C64X_GRP_FUNIT_L = 129 , TMS320C64X_GRP_FUNIT_M = 130 , TMS320C64X_GRP_FUNIT_S = 131 , TMS320C64X_GRP_FUNIT_NO = 132 , TMS320C64X_GRP_ENDING = 133 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0 , TMS320C64X_FUNIT_D = 1 , TMS320C64X_FUNIT_L = 2 , TMS320C64X_FUNIT_M = 3 , TMS320C64X_FUNIT_S = 4 , TMS320C64X_FUNIT_NO = 5 , } # [repr (u32)] # [doc = " M680X registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_reg { M680X_REG_INVALID = 0 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_A = 1 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_B = 2 , # [doc = "< HD6309"] M680X_REG_E = 3 , # [doc = "< HD6309"] M680X_REG_F = 4 , # [doc = "< HD6309"] M680X_REG_0 = 5 , # [doc = "< M6801/3/9, HD6301/9"] M680X_REG_D = 6 , # [doc = "< HD6309"] M680X_REG_W = 7 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_CC = 8 , # [doc = "< M6809/M6309"] M680X_REG_DP = 9 , # [doc = "< M6309"] M680X_REG_MD = 10 , # [doc = "< M6808"] M680X_REG_HX = 11 , # [doc = "< M6808"] M680X_REG_H = 12 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_X = 13 , # [doc = "< M6809/M6309"] M680X_REG_Y = 14 , # [doc = "< M6809/M6309"] M680X_REG_S = 15 , # [doc = "< M6809/M6309"] M680X_REG_U = 16 , # [doc = "< M6309"] M680X_REG_V = 17 , # [doc = "< M6309"] M680X_REG_Q = 18 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_PC = 19 , # [doc = "< CPU12"] M680X_REG_TMP2 = 20 , # [doc = "< CPU12"] M680X_REG_TMP3 = 21 , # [doc = "< <-- mark the end of the list of registers"] M680X_REG_ENDING = 22 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M680X_OP_INVALID = 0 , # [doc = "< = Register operand."] M680X_OP_REGISTER = 1 , # [doc = "< = Immediate operand."] M680X_OP_IMMEDIATE = 2 , # [doc = "< = Indexed addressing operand."] M680X_OP_INDEXED = 3 , # [doc = "< = Extended addressing operand."] M680X_OP_EXTENDED = 4 , # [doc = "< = Direct addressing operand."] M680X_OP_DIRECT = 5 , # [doc = "< = Relative addressing operand."] M680X_OP_RELATIVE = 6 , # [doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."] M680X_OP_CONSTANT = 7 , } # [doc = " Instruction's operand referring to indexed addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_idx { # [doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"] pub base_reg : m680x_reg , # [doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"] pub offset_reg : m680x_reg , # [doc = "< 5-,8- or 16-bit offset. See also offset_bits."] pub offset : i16 , # [doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"] pub offset_addr : u16 , # [doc = "< offset width in bits for indexed addressing"] pub offset_bits : u8 , # [doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"] pub inc_dec : i8 , # [doc = "< 8-bit flags (see above)"] pub flags : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_idx"] [:: std :: mem :: size_of :: < m680x_op_idx > () - 16usize] ; ["Alignment of m680x_op_idx"] [:: std :: mem :: align_of :: < m680x_op_idx > () - 4usize] ; ["Offset of field: m680x_op_idx::base_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , base_reg) - 0usize] ; ["Offset of field: m680x_op_idx::offset_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_reg) - 4usize] ; ["Offset of field: m680x_op_idx::offset"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset) - 8usize] ; ["Offset of field: m680x_op_idx::offset_addr"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_addr) - 10usize] ; ["Offset of field: m680x_op_idx::offset_bits"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_bits) - 12usize] ; ["Offset of field: m680x_op_idx::inc_dec"] [:: std :: mem :: offset_of ! (m680x_op_idx , inc_dec) - 13usize] ; ["Offset of field: m680x_op_idx::flags"] [:: std :: mem :: offset_of ! (m680x_op_idx , flags) - 14usize] ; } ; # [doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_rel { # [doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."] pub address : u16 , # [doc = "< the offset/displacement value"] pub offset : i16 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_rel"] [:: std :: mem :: size_of :: < m680x_op_rel > () - 4usize] ; ["Alignment of m680x_op_rel"] [:: std :: mem :: align_of :: < m680x_op_rel > () - 2usize] ; ["Offset of field: m680x_op_rel::address"] [:: std :: mem :: offset_of ! (m680x_op_rel , address) - 0usize] ; ["Offset of field: m680x_op_rel::offset"] [:: std :: mem :: offset_of ! (m680x_op_rel , offset) - 2usize] ; } ; # [doc = " Instruction's operand referring to extended addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_ext { # [doc = "< The absolute address"] pub address : u16 , # [doc = "< true if extended indirect addressing"] pub indirect : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_ext"] [:: std :: mem :: size_of :: < m680x_op_ext > () - 4usize] ; ["Alignment of m680x_op_ext"] [:: std :: mem :: align_of :: < m680x_op_ext > () - 2usize] ; ["Offset of field: m680x_op_ext::address"] [:: std :: mem :: offset_of ! (m680x_op_ext , address) - 0usize] ; ["Offset of field: m680x_op_ext::indirect"] [:: std :: mem :: offset_of ! (m680x_op_ext , indirect) - 2usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x_op { pub type_ : m680x_op_type , pub __bindgen_anon_1 : cs_m680x_op__bindgen_ty_1 , # [doc = "< size of this operand (in bytes)"] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m680x_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< register value for REG operand"] pub reg : m680x_reg , # [doc = "< Indexed addressing operand"] pub idx : m680x_op_idx , # [doc = "< Relative address. operand (Bcc/LBcc)"] pub rel : m680x_op_rel , # [doc = "< Extended address"] pub ext : m680x_op_ext , # [doc = "<</ Direct address (lower 8-bit)"] pub direct_addr : u8 , # [doc = "< constant value (bit index, page nr.)"] pub const_val : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m680x_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m680x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::idx"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , idx) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::rel"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , rel) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , ext) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::direct_addr"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , direct_addr) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::const_val"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , const_val) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op"] [:: std :: mem :: size_of :: < cs_m680x_op > () - 24usize] ; ["Alignment of cs_m680x_op"] [:: std :: mem :: align_of :: < cs_m680x_op > () - 4usize] ; ["Offset of field: cs_m680x_op::type_"] [:: std :: mem :: offset_of ! (cs_m680x_op , type_) - 0usize] ; ["Offset of field: cs_m680x_op::size"] [:: std :: mem :: offset_of ! (cs_m680x_op , size) - 20usize] ; ["Offset of field: cs_m680x_op::access"] [:: std :: mem :: offset_of ! (cs_m680x_op , access) - 21usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access) } } # [repr (u32)] # [doc = " Group of M680X instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_group_type { M680X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M680X_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] M680X_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] M680X_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] M680X_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] M680X_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEDGE; not used"] M680X_GRP_PRIV = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M680X_GRP_BRAREL = 7 , M680X_GRP_ENDING = 8 , } # [doc = " The M680X instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x { # [doc = "< See: M680X instruction flags"] pub flags : u8 , # [doc = "< number of operands for the instruction or 0"] pub op_count : u8 , # [doc = "< operands for this insn."] pub operands : [cs_m680x_op ; 9usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x"] [:: std :: mem :: size_of :: < cs_m680x > () - 220usize] ; ["Alignment of cs_m680x"] [:: std :: mem :: align_of :: < cs_m680x > () - 4usize] ; ["Offset of field: cs_m680x::flags"] [:: std :: mem :: offset_of ! (cs_m680x , flags) - 0usize] ; ["Offset of field: cs_m680x::op_count"] [:: std :: mem :: offset_of ! (cs_m680x , op_count) - 1usize] ; ["Offset of field: cs_m680x::operands"] [:: std :: mem :: offset_of ! (cs_m680x , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " M680X instruction IDs"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_insn { M680X_INS_INVLD = 0 , # [doc = "< M6800/1/2/3"] M680X_INS_ABA = 1 , M680X_INS_ABX = 2 , M680X_INS_ABY = 3 , M680X_INS_ADC = 4 , M680X_INS_ADCA = 5 , M680X_INS_ADCB = 6 , M680X_INS_ADCD = 7 , M680X_INS_ADCR = 8 , M680X_INS_ADD = 9 , M680X_INS_ADDA = 10 , M680X_INS_ADDB = 11 , M680X_INS_ADDD = 12 , M680X_INS_ADDE = 13 , M680X_INS_ADDF = 14 , M680X_INS_ADDR = 15 , M680X_INS_ADDW = 16 , M680X_INS_AIM = 17 , M680X_INS_AIS = 18 , M680X_INS_AIX = 19 , M680X_INS_AND = 20 , M680X_INS_ANDA = 21 , M680X_INS_ANDB = 22 , M680X_INS_ANDCC = 23 , M680X_INS_ANDD = 24 , M680X_INS_ANDR = 25 , M680X_INS_ASL = 26 , M680X_INS_ASLA = 27 , M680X_INS_ASLB = 28 , # [doc = "< or LSLD"] M680X_INS_ASLD = 29 , M680X_INS_ASR = 30 , M680X_INS_ASRA = 31 , M680X_INS_ASRB = 32 , M680X_INS_ASRD = 33 , M680X_INS_ASRX = 34 , M680X_INS_BAND = 35 , # [doc = "< or BHS"] M680X_INS_BCC = 36 , M680X_INS_BCLR = 37 , # [doc = "< or BLO"] M680X_INS_BCS = 38 , M680X_INS_BEOR = 39 , M680X_INS_BEQ = 40 , M680X_INS_BGE = 41 , M680X_INS_BGND = 42 , M680X_INS_BGT = 43 , M680X_INS_BHCC = 44 , M680X_INS_BHCS = 45 , M680X_INS_BHI = 46 , M680X_INS_BIAND = 47 , M680X_INS_BIEOR = 48 , M680X_INS_BIH = 49 , M680X_INS_BIL = 50 , M680X_INS_BIOR = 51 , M680X_INS_BIT = 52 , M680X_INS_BITA = 53 , M680X_INS_BITB = 54 , M680X_INS_BITD = 55 , M680X_INS_BITMD = 56 , M680X_INS_BLE = 57 , M680X_INS_BLS = 58 , M680X_INS_BLT = 59 , M680X_INS_BMC = 60 , M680X_INS_BMI = 61 , M680X_INS_BMS = 62 , M680X_INS_BNE = 63 , M680X_INS_BOR = 64 , M680X_INS_BPL = 65 , M680X_INS_BRCLR = 66 , M680X_INS_BRSET = 67 , M680X_INS_BRA = 68 , M680X_INS_BRN = 69 , M680X_INS_BSET = 70 , M680X_INS_BSR = 71 , M680X_INS_BVC = 72 , M680X_INS_BVS = 73 , M680X_INS_CALL = 74 , # [doc = "< M6800/1/2/3"] M680X_INS_CBA = 75 , M680X_INS_CBEQ = 76 , M680X_INS_CBEQA = 77 , M680X_INS_CBEQX = 78 , # [doc = "< M6800/1/2/3"] M680X_INS_CLC = 79 , # [doc = "< M6800/1/2/3"] M680X_INS_CLI = 80 , M680X_INS_CLR = 81 , M680X_INS_CLRA = 82 , M680X_INS_CLRB = 83 , M680X_INS_CLRD = 84 , M680X_INS_CLRE = 85 , M680X_INS_CLRF = 86 , M680X_INS_CLRH = 87 , M680X_INS_CLRW = 88 , M680X_INS_CLRX = 89 , # [doc = "< M6800/1/2/3"] M680X_INS_CLV = 90 , M680X_INS_CMP = 91 , M680X_INS_CMPA = 92 , M680X_INS_CMPB = 93 , M680X_INS_CMPD = 94 , M680X_INS_CMPE = 95 , M680X_INS_CMPF = 96 , M680X_INS_CMPR = 97 , M680X_INS_CMPS = 98 , M680X_INS_CMPU = 99 , M680X_INS_CMPW = 100 , M680X_INS_CMPX = 101 , M680X_INS_CMPY = 102 , M680X_INS_COM = 103 , M680X_INS_COMA = 104 , M680X_INS_COMB = 105 , M680X_INS_COMD = 106 , M680X_INS_COME = 107 , M680X_INS_COMF = 108 , M680X_INS_COMW = 109 , M680X_INS_COMX = 110 , M680X_INS_CPD = 111 , M680X_INS_CPHX = 112 , M680X_INS_CPS = 113 , # [doc = "< M6800/1/2/3"] M680X_INS_CPX = 114 , M680X_INS_CPY = 115 , M680X_INS_CWAI = 116 , M680X_INS_DAA = 117 , M680X_INS_DBEQ = 118 , M680X_INS_DBNE = 119 , M680X_INS_DBNZ = 120 , M680X_INS_DBNZA = 121 , M680X_INS_DBNZX = 122 , M680X_INS_DEC = 123 , M680X_INS_DECA = 124 , M680X_INS_DECB = 125 , M680X_INS_DECD = 126 , M680X_INS_DECE = 127 , M680X_INS_DECF = 128 , M680X_INS_DECW = 129 , M680X_INS_DECX = 130 , # [doc = "< M6800/1/2/3"] M680X_INS_DES = 131 , # [doc = "< M6800/1/2/3"] M680X_INS_DEX = 132 , M680X_INS_DEY = 133 , M680X_INS_DIV = 134 , M680X_INS_DIVD = 135 , M680X_INS_DIVQ = 136 , M680X_INS_EDIV = 137 , M680X_INS_EDIVS = 138 , M680X_INS_EIM = 139 , M680X_INS_EMACS = 140 , M680X_INS_EMAXD = 141 , M680X_INS_EMAXM = 142 , M680X_INS_EMIND = 143 , M680X_INS_EMINM = 144 , M680X_INS_EMUL = 145 , M680X_INS_EMULS = 146 , M680X_INS_EOR = 147 , M680X_INS_EORA = 148 , M680X_INS_EORB = 149 , M680X_INS_EORD = 150 , M680X_INS_EORR = 151 , M680X_INS_ETBL = 152 , M680X_INS_EXG = 153 , M680X_INS_FDIV = 154 , M680X_INS_IBEQ = 155 , M680X_INS_IBNE = 156 , M680X_INS_IDIV = 157 , M680X_INS_IDIVS = 158 , M680X_INS_ILLGL = 159 , M680X_INS_INC = 160 , M680X_INS_INCA = 161 , M680X_INS_INCB = 162 , M680X_INS_INCD = 163 , M680X_INS_INCE = 164 , M680X_INS_INCF = 165 , M680X_INS_INCW = 166 , M680X_INS_INCX = 167 , # [doc = "< M6800/1/2/3"] M680X_INS_INS = 168 , # [doc = "< M6800/1/2/3"] M680X_INS_INX = 169 , M680X_INS_INY = 170 , M680X_INS_JMP = 171 , M680X_INS_JSR = 172 , # [doc = "< or LBHS"] M680X_INS_LBCC = 173 , # [doc = "< or LBLO"] M680X_INS_LBCS = 174 , M680X_INS_LBEQ = 175 , M680X_INS_LBGE = 176 , M680X_INS_LBGT = 177 , M680X_INS_LBHI = 178 , M680X_INS_LBLE = 179 , M680X_INS_LBLS = 180 , M680X_INS_LBLT = 181 , M680X_INS_LBMI = 182 , M680X_INS_LBNE = 183 , M680X_INS_LBPL = 184 , M680X_INS_LBRA = 185 , M680X_INS_LBRN = 186 , M680X_INS_LBSR = 187 , M680X_INS_LBVC = 188 , M680X_INS_LBVS = 189 , M680X_INS_LDA = 190 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAA = 191 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAB = 192 , M680X_INS_LDB = 193 , M680X_INS_LDBT = 194 , M680X_INS_LDD = 195 , M680X_INS_LDE = 196 , M680X_INS_LDF = 197 , M680X_INS_LDHX = 198 , M680X_INS_LDMD = 199 , M680X_INS_LDQ = 200 , M680X_INS_LDS = 201 , M680X_INS_LDU = 202 , M680X_INS_LDW = 203 , M680X_INS_LDX = 204 , M680X_INS_LDY = 205 , M680X_INS_LEAS = 206 , M680X_INS_LEAU = 207 , M680X_INS_LEAX = 208 , M680X_INS_LEAY = 209 , M680X_INS_LSL = 210 , M680X_INS_LSLA = 211 , M680X_INS_LSLB = 212 , M680X_INS_LSLD = 213 , M680X_INS_LSLX = 214 , M680X_INS_LSR = 215 , M680X_INS_LSRA = 216 , M680X_INS_LSRB = 217 , # [doc = "< or ASRD"] M680X_INS_LSRD = 218 , M680X_INS_LSRW = 219 , M680X_INS_LSRX = 220 , M680X_INS_MAXA = 221 , M680X_INS_MAXM = 222 , M680X_INS_MEM = 223 , M680X_INS_MINA = 224 , M680X_INS_MINM = 225 , M680X_INS_MOV = 226 , M680X_INS_MOVB = 227 , M680X_INS_MOVW = 228 , M680X_INS_MUL = 229 , M680X_INS_MULD = 230 , M680X_INS_NEG = 231 , M680X_INS_NEGA = 232 , M680X_INS_NEGB = 233 , M680X_INS_NEGD = 234 , M680X_INS_NEGX = 235 , M680X_INS_NOP = 236 , M680X_INS_NSA = 237 , M680X_INS_OIM = 238 , M680X_INS_ORA = 239 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAA = 240 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAB = 241 , M680X_INS_ORB = 242 , M680X_INS_ORCC = 243 , M680X_INS_ORD = 244 , M680X_INS_ORR = 245 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHA = 246 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHB = 247 , M680X_INS_PSHC = 248 , M680X_INS_PSHD = 249 , M680X_INS_PSHH = 250 , M680X_INS_PSHS = 251 , M680X_INS_PSHSW = 252 , M680X_INS_PSHU = 253 , M680X_INS_PSHUW = 254 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHX = 255 , M680X_INS_PSHY = 256 , # [doc = "< M6800/1/2/3"] M680X_INS_PULA = 257 , # [doc = "< M6800/1/2/3"] M680X_INS_PULB = 258 , M680X_INS_PULC = 259 , M680X_INS_PULD = 260 , M680X_INS_PULH = 261 , M680X_INS_PULS = 262 , M680X_INS_PULSW = 263 , M680X_INS_PULU = 264 , M680X_INS_PULUW = 265 , # [doc = "< M6800/1/2/3"] M680X_INS_PULX = 266 , M680X_INS_PULY = 267 , M680X_INS_REV = 268 , M680X_INS_REVW = 269 , M680X_INS_ROL = 270 , M680X_INS_ROLA = 271 , M680X_INS_ROLB = 272 , M680X_INS_ROLD = 273 , M680X_INS_ROLW = 274 , M680X_INS_ROLX = 275 , M680X_INS_ROR = 276 , M680X_INS_RORA = 277 , M680X_INS_RORB = 278 , M680X_INS_RORD = 279 , M680X_INS_RORW = 280 , M680X_INS_RORX = 281 , M680X_INS_RSP = 282 , M680X_INS_RTC = 283 , M680X_INS_RTI = 284 , M680X_INS_RTS = 285 , # [doc = "< M6800/1/2/3"] M680X_INS_SBA = 286 , M680X_INS_SBC = 287 , M680X_INS_SBCA = 288 , M680X_INS_SBCB = 289 , M680X_INS_SBCD = 290 , M680X_INS_SBCR = 291 , M680X_INS_SEC = 292 , M680X_INS_SEI = 293 , M680X_INS_SEV = 294 , M680X_INS_SEX = 295 , M680X_INS_SEXW = 296 , M680X_INS_SLP = 297 , M680X_INS_STA = 298 , # [doc = "< M6800/1/2/3"] M680X_INS_STAA = 299 , # [doc = "< M6800/1/2/3"] M680X_INS_STAB = 300 , M680X_INS_STB = 301 , M680X_INS_STBT = 302 , M680X_INS_STD = 303 , M680X_INS_STE = 304 , M680X_INS_STF = 305 , M680X_INS_STOP = 306 , M680X_INS_STHX = 307 , M680X_INS_STQ = 308 , M680X_INS_STS = 309 , M680X_INS_STU = 310 , M680X_INS_STW = 311 , M680X_INS_STX = 312 , M680X_INS_STY = 313 , M680X_INS_SUB = 314 , M680X_INS_SUBA = 315 , M680X_INS_SUBB = 316 , M680X_INS_SUBD = 317 , M680X_INS_SUBE = 318 , M680X_INS_SUBF = 319 , M680X_INS_SUBR = 320 , M680X_INS_SUBW = 321 , M680X_INS_SWI = 322 , M680X_INS_SWI2 = 323 , M680X_INS_SWI3 = 324 , M680X_INS_SYNC = 325 , # [doc = "< M6800/1/2/3"] M680X_INS_TAB = 326 , # [doc = "< M6800/1/2/3"] M680X_INS_TAP = 327 , M680X_INS_TAX = 328 , # [doc = "< M6800/1/2/3"] M680X_INS_TBA = 329 , M680X_INS_TBEQ = 330 , M680X_INS_TBL = 331 , M680X_INS_TBNE = 332 , M680X_INS_TEST = 333 , M680X_INS_TFM = 334 , M680X_INS_TFR = 335 , M680X_INS_TIM = 336 , # [doc = "< M6800/1/2/3"] M680X_INS_TPA = 337 , M680X_INS_TST = 338 , M680X_INS_TSTA = 339 , M680X_INS_TSTB = 340 , M680X_INS_TSTD = 341 , M680X_INS_TSTE = 342 , M680X_INS_TSTF = 343 , M680X_INS_TSTW = 344 , M680X_INS_TSTX = 345 , # [doc = "< M6800/1/2/3"] M680X_INS_TSX = 346 , M680X_INS_TSY = 347 , M680X_INS_TXA = 348 , # [doc = "< M6800/1/2/3"] M680X_INS_TXS = 349 , M680X_INS_TYS = 350 , # [doc = "< M6800/1/2/3"] M680X_INS_WAI = 351 , M680X_INS_WAIT = 352 , M680X_INS_WAV = 353 , M680X_INS_WAVR = 354 , # [doc = "< HD6301"] M680X_INS_XGDX = 355 , M680X_INS_XGDY = 356 , M680X_INS_ENDING = 357 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_evm { # [doc = "< number of items popped from the stack"] pub pop : :: std :: os :: raw :: c_uchar , # [doc = "< number of items pushed into the stack"] pub push : :: std :: os :: raw :: c_uchar , # [doc = "< gas fee for the instruction"] pub fee : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_evm"] [:: std :: mem :: size_of :: < cs_evm > () - 8usize] ; ["Alignment of cs_evm"] [:: std :: mem :: align_of :: < cs_evm > () - 4usize] ; ["Offset of field: cs_evm::pop"] [:: std :: mem :: offset_of ! (cs_evm , pop) - 0usize] ; ["Offset of field: cs_evm::push"] [:: std :: mem :: offset_of ! (cs_evm , push) - 1usize] ; ["Offset of field: cs_evm::fee"] [:: std :: mem :: offset_of ! (cs_evm , fee) - 4usize] ; } ; # [repr (u32)] # [doc = " EVM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn { EVM_INS_STOP = 0 , EVM_INS_ADD = 1 , EVM_INS_MUL = 2 , EVM_INS_SUB = 3 , EVM_INS_DIV = 4 , EVM_INS_SDIV = 5 , EVM_INS_MOD = 6 , EVM_INS_SMOD = 7 , EVM_INS_ADDMOD = 8 , EVM_INS_MULMOD = 9 , EVM_INS_EXP = 10 , EVM_INS_SIGNEXTEND = 11 , EVM_INS_LT = 16 , EVM_INS_GT = 17 , EVM_INS_SLT = 18 , EVM_INS_SGT = 19 , EVM_INS_EQ = 20 , EVM_INS_ISZERO = 21 , EVM_INS_AND = 22 , EVM_INS_OR = 23 , EVM_INS_XOR = 24 , EVM_INS_NOT = 25 , EVM_INS_BYTE = 26 , EVM_INS_SHA3 = 32 , EVM_INS_ADDRESS = 48 , EVM_INS_BALANCE = 49 , EVM_INS_ORIGIN = 50 , EVM_INS_CALLER = 51 , EVM_INS_CALLVALUE = 52 , EVM_INS_CALLDATALOAD = 53 , EVM_INS_CALLDATASIZE = 54 , EVM_INS_CALLDATACOPY = 55 , EVM_INS_CODESIZE = 56 , EVM_INS_CODECOPY = 57 , EVM_INS_GASPRICE = 58 , EVM_INS_EXTCODESIZE = 59 , EVM_INS_EXTCODECOPY = 60 , EVM_INS_RETURNDATASIZE = 61 , EVM_INS_RETURNDATACOPY = 62 , EVM_INS_BLOCKHASH = 64 , EVM_INS_COINBASE = 65 , EVM_INS_TIMESTAMP = 66 , EVM_INS_NUMBER = 67 , EVM_INS_DIFFICULTY = 68 , EVM_INS_GASLIMIT = 69 , EVM_INS_POP = 80 , EVM_INS_MLOAD = 81 , EVM_INS_MSTORE = 82 , EVM_INS_MSTORE8 = 83 , EVM_INS_SLOAD = 84 , EVM_INS_SSTORE = 85 , EVM_INS_JUMP = 86 , EVM_INS_JUMPI = 87 , EVM_INS_PC = 88 , EVM_INS_MSIZE = 89 , EVM_INS_GAS = 90 , EVM_INS_JUMPDEST = 91 , EVM_INS_PUSH1 = 96 , EVM_INS_PUSH2 = 97 , EVM_INS_PUSH3 = 98 , EVM_INS_PUSH4 = 99 , EVM_INS_PUSH5 = 100 , EVM_INS_PUSH6 = 101 , EVM_INS_PUSH7 = 102 , EVM_INS_PUSH8 = 103 , EVM_INS_PUSH9 = 104 , EVM_INS_PUSH10 = 105 , EVM_INS_PUSH11 = 106 , EVM_INS_PUSH12 = 107 , EVM_INS_PUSH13 = 108 , EVM_INS_PUSH14 = 109 , EVM_INS_PUSH15 = 110 , EVM_INS_PUSH16 = 111 , EVM_INS_PUSH17 = 112 , EVM_INS_PUSH18 = 113 , EVM_INS_PUSH19 = 114 , EVM_INS_PUSH20 = 115 , EVM_INS_PUSH21 = 116 , EVM_INS_PUSH22 = 117 , EVM_INS_PUSH23 = 118 , EVM_INS_PUSH24 = 119 , EVM_INS_PUSH25 = 120 , EVM_INS_PUSH26 = 121 , EVM_INS_PUSH27 = 122 , EVM_INS_PUSH28 = 123 , EVM_INS_PUSH29 = 124 , EVM_INS_PUSH30 = 125 , EVM_INS_PUSH31 = 126 , EVM_INS_PUSH32 = 127 , EVM_INS_DUP1 = 128 , EVM_INS_DUP2 = 129 , EVM_INS_DUP3 = 130 , EVM_INS_DUP4 = 131 , EVM_INS_DUP5 = 132 , EVM_INS_DUP6 = 133 , EVM_INS_DUP7 = 134 , EVM_INS_DUP8 = 135 , EVM_INS_DUP9 = 136 , EVM_INS_DUP10 = 137 , EVM_INS_DUP11 = 138 , EVM_INS_DUP12 = 139 , EVM_INS_DUP13 = 140 , EVM_INS_DUP14 = 141 , EVM_INS_DUP15 = 142 , EVM_INS_DUP16 = 143 , EVM_INS_SWAP1 = 144 , EVM_INS_SWAP2 = 145 , EVM_INS_SWAP3 = 146 , EVM_INS_SWAP4 = 147 , EVM_INS_SWAP5 = 148 , EVM_INS_SWAP6 = 149 , EVM_INS_SWAP7 = 150 , EVM_INS_SWAP8 = 151 , EVM_INS_SWAP9 = 152 , EVM_INS_SWAP10 = 153 , EVM_INS_SWAP11 = 154 , EVM_INS_SWAP12 = 155 , EVM_INS_SWAP13 = 156 , EVM_INS_SWAP14 = 157 , EVM_INS_SWAP15 = 158 , EVM_INS_SWAP16 = 159 , EVM_INS_LOG0 = 160 , EVM_INS_LOG1 = 161 , EVM_INS_LOG2 = 162 , EVM_INS_LOG3 = 163 , EVM_INS_LOG4 = 164 , EVM_INS_CREATE = 240 , EVM_INS_CALL = 241 , EVM_INS_CALLCODE = 242 , EVM_INS_RETURN = 243 , EVM_INS_DELEGATECALL = 244 , EVM_INS_CALLBLACKBOX = 245 , EVM_INS_STATICCALL = 250 , EVM_INS_REVERT = 253 , EVM_INS_SUICIDE = 255 , EVM_INS_INVALID = 512 , EVM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of EVM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn_group { # [doc = "< = CS_GRP_INVALID"] EVM_GRP_INVALID = 0 , # [doc = "< all jump instructions"] EVM_GRP_JUMP = 1 , # [doc = "< math instructions"] EVM_GRP_MATH = 8 , # [doc = "< instructions write to stack"] EVM_GRP_STACK_WRITE = 9 , # [doc = "< instructions read from stack"] EVM_GRP_STACK_READ = 10 , # [doc = "< instructions write to memory"] EVM_GRP_MEM_WRITE = 11 , # [doc = "< instructions read from memory"] EVM_GRP_MEM_READ = 12 , # [doc = "< instructions write to storage"] EVM_GRP_STORE_WRITE = 13 , # [doc = "< instructions read from storage"] EVM_GRP_STORE_READ = 14 , # [doc = "< instructions halt execution"] EVM_GRP_HALT = 15 , # [doc = "< <-- mark the end of the list of groups"] EVM_GRP_ENDING = 16 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_op_type { RISCV_OP_INVALID = 0 , RISCV_OP_REG = 1 , RISCV_OP_IMM = 2 , RISCV_OP_MEM = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct riscv_op_mem { pub base : :: std :: os :: raw :: c_uint , pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of riscv_op_mem"] [:: std :: mem :: size_of :: < riscv_op_mem > () - 16usize] ; ["Alignment of riscv_op_mem"] [:: std :: mem :: align_of :: < riscv_op_mem > () - 8usize] ; ["Offset of field: riscv_op_mem::base"] [:: std :: mem :: offset_of ! (riscv_op_mem , base) - 0usize] ; ["Offset of field: riscv_op_mem::disp"] [:: std :: mem :: offset_of ! (riscv_op_mem , disp) - 8usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv_op { pub type_ : riscv_op_type , pub __bindgen_anon_1 : cs_riscv_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_riscv_op__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub imm : i64 , pub mem : riscv_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_riscv_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_riscv_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op"] [:: std :: mem :: size_of :: < cs_riscv_op > () - 24usize] ; ["Alignment of cs_riscv_op"] [:: std :: mem :: align_of :: < cs_riscv_op > () - 8usize] ; ["Offset of field: cs_riscv_op::type_"] [:: std :: mem :: offset_of ! (cs_riscv_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv { pub need_effective_addr : bool , pub op_count : u8 , pub operands : [cs_riscv_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv"] [:: std :: mem :: size_of :: < cs_riscv > () - 200usize] ; ["Alignment of cs_riscv"] [:: std :: mem :: align_of :: < cs_riscv > () - 8usize] ; ["Offset of field: cs_riscv::need_effective_addr"] [:: std :: mem :: offset_of ! (cs_riscv , need_effective_addr) - 0usize] ; ["Offset of field: cs_riscv::op_count"] [:: std :: mem :: offset_of ! (cs_riscv , op_count) - 1usize] ; ["Offset of field: cs_riscv::operands"] [:: std :: mem :: offset_of ! (cs_riscv , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}" , self . need_effective_addr , self . op_count , self . operands) } } impl riscv_reg { pub const RISCV_REG_ZERO : riscv_reg = riscv_reg :: RISCV_REG_X0 ; } impl riscv_reg { pub const RISCV_REG_RA : riscv_reg = riscv_reg :: RISCV_REG_X1 ; } impl riscv_reg { pub const RISCV_REG_SP : riscv_reg = riscv_reg :: RISCV_REG_X2 ; } impl riscv_reg { pub const RISCV_REG_GP : riscv_reg = riscv_reg :: RISCV_REG_X3 ; } impl riscv_reg { pub const RISCV_REG_TP : riscv_reg = riscv_reg :: RISCV_REG_X4 ; } impl riscv_reg { pub const RISCV_REG_T0 : riscv_reg = riscv_reg :: RISCV_REG_X5 ; } impl riscv_reg { pub const RISCV_REG_T1 : riscv_reg = riscv_reg :: RISCV_REG_X6 ; } impl riscv_reg { pub const RISCV_REG_T2 : riscv_reg = riscv_reg :: RISCV_REG_X7 ; } impl riscv_reg { pub const RISCV_REG_S0 : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_FP : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_S1 : riscv_reg = riscv_reg :: RISCV_REG_X9 ; } impl riscv_reg { pub const RISCV_REG_A0 : riscv_reg = riscv_reg :: RISCV_REG_X10 ; } impl riscv_reg { pub const RISCV_REG_A1 : riscv_reg = riscv_reg :: RISCV_REG_X11 ; } impl riscv_reg { pub const RISCV_REG_A2 : riscv_reg = riscv_reg :: RISCV_REG_X12 ; } impl riscv_reg { pub const RISCV_REG_A3 : riscv_reg = riscv_reg :: RISCV_REG_X13 ; } impl riscv_reg { pub const RISCV_REG_A4 : riscv_reg = riscv_reg :: RISCV_REG_X14 ; } impl riscv_reg { pub const RISCV_REG_A5 : riscv_reg = riscv_reg :: RISCV_REG_X15 ; } impl riscv_reg { pub const RISCV_REG_A6 : riscv_reg = riscv_reg :: RISCV_REG_X16 ; } impl riscv_reg { pub const RISCV_REG_A7 : riscv_reg = riscv_reg :: RISCV_REG_X17 ; } impl riscv_reg { pub const RISCV_REG_S2 : riscv_reg = riscv_reg :: RISCV_REG_X18 ; } impl riscv_reg { pub const RISCV_REG_S3 : riscv_reg = riscv_reg :: RISCV_REG_X19 ; } impl riscv_reg { pub const RISCV_REG_S4 : riscv_reg = riscv_reg :: RISCV_REG_X20 ; } impl riscv_reg { pub const RISCV_REG_S5 : riscv_reg = riscv_reg :: RISCV_REG_X21 ; } impl riscv_reg { pub const RISCV_REG_S6 : riscv_reg = riscv_reg :: RISCV_REG_X22 ; } impl riscv_reg { pub const RISCV_REG_S7 : riscv_reg = riscv_reg :: RISCV_REG_X23 ; } impl riscv_reg { pub const RISCV_REG_S8 : riscv_reg = riscv_reg :: RISCV_REG_X24 ; } impl riscv_reg { pub const RISCV_REG_S9 : riscv_reg = riscv_reg :: RISCV_REG_X25 ; } impl riscv_reg { pub const RISCV_REG_S10 : riscv_reg = riscv_reg :: RISCV_REG_X26 ; } impl riscv_reg { pub const RISCV_REG_S11 : riscv_reg = riscv_reg :: RISCV_REG_X27 ; } impl riscv_reg { pub const RISCV_REG_T3 : riscv_reg = riscv_reg :: RISCV_REG_X28 ; } impl riscv_reg { pub const RISCV_REG_T4 : riscv_reg = riscv_reg :: RISCV_REG_X29 ; } impl riscv_reg { pub const RISCV_REG_T5 : riscv_reg = riscv_reg :: RISCV_REG_X30 ; } impl riscv_reg { pub const RISCV_REG_T6 : riscv_reg = riscv_reg :: RISCV_REG_X31 ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_reg { RISCV_REG_INVALID = 0 , RISCV_REG_X0 = 1 , RISCV_REG_X1 = 2 , RISCV_REG_X2 = 3 , RISCV_REG_X3 = 4 , RISCV_REG_X4 = 5 , RISCV_REG_X5 = 6 , RISCV_REG_X6 = 7 , RISCV_REG_X7 = 8 , RISCV_REG_X8 = 9 , RISCV_REG_X9 = 10 , RISCV_REG_X10 = 11 , RISCV_REG_X11 = 12 , RISCV_REG_X12 = 13 , RISCV_REG_X13 = 14 , RISCV_REG_X14 = 15 , RISCV_REG_X15 = 16 , RISCV_REG_X16 = 17 , RISCV_REG_X17 = 18 , RISCV_REG_X18 = 19 , RISCV_REG_X19 = 20 , RISCV_REG_X20 = 21 , RISCV_REG_X21 = 22 , RISCV_REG_X22 = 23 , RISCV_REG_X23 = 24 , RISCV_REG_X24 = 25 , RISCV_REG_X25 = 26 , RISCV_REG_X26 = 27 , RISCV_REG_X27 = 28 , RISCV_REG_X28 = 29 , RISCV_REG_X29 = 30 , RISCV_REG_X30 = 31 , RISCV_REG_X31 = 32 , RISCV_REG_F0_32 = 33 , RISCV_REG_F0_64 = 34 , RISCV_REG_F1_32 = 35 , RISCV_REG_F1_64 = 36 , RISCV_REG_F2_32 = 37 , RISCV_REG_F2_64 = 38 , RISCV_REG_F3_32 = 39 , RISCV_REG_F3_64 = 40 , RISCV_REG_F4_32 = 41 , RISCV_REG_F4_64 = 42 , RISCV_REG_F5_32 = 43 , RISCV_REG_F5_64 = 44 , RISCV_REG_F6_32 = 45 , RISCV_REG_F6_64 = 46 , RISCV_REG_F7_32 = 47 , RISCV_REG_F7_64 = 48 , RISCV_REG_F8_32 = 49 , RISCV_REG_F8_64 = 50 , RISCV_REG_F9_32 = 51 , RISCV_REG_F9_64 = 52 , RISCV_REG_F10_32 = 53 , RISCV_REG_F10_64 = 54 , RISCV_REG_F11_32 = 55 , RISCV_REG_F11_64 = 56 , RISCV_REG_F12_32 = 57 , RISCV_REG_F12_64 = 58 , RISCV_REG_F13_32 = 59 , RISCV_REG_F13_64 = 60 , RISCV_REG_F14_32 = 61 , RISCV_REG_F14_64 = 62 , RISCV_REG_F15_32 = 63 , RISCV_REG_F15_64 = 64 , RISCV_REG_F16_32 = 65 , RISCV_REG_F16_64 = 66 , RISCV_REG_F17_32 = 67 , RISCV_REG_F17_64 = 68 , RISCV_REG_F18_32 = 69 , RISCV_REG_F18_64 = 70 , RISCV_REG_F19_32 = 71 , RISCV_REG_F19_64 = 72 , RISCV_REG_F20_32 = 73 , RISCV_REG_F20_64 = 74 , RISCV_REG_F21_32 = 75 , RISCV_REG_F21_64 = 76 , RISCV_REG_F22_32 = 77 , RISCV_REG_F22_64 = 78 , RISCV_REG_F23_32 = 79 , RISCV_REG_F23_64 = 80 , RISCV_REG_F24_32 = 81 , RISCV_REG_F24_64 = 82 , RISCV_REG_F25_32 = 83 , RISCV_REG_F25_64 = 84 , RISCV_REG_F26_32 = 85 , RISCV_REG_F26_64 = 86 , RISCV_REG_F27_32 = 87 , RISCV_REG_F27_64 = 88 , RISCV_REG_F28_32 = 89 , RISCV_REG_F28_64 = 90 , RISCV_REG_F29_32 = 91 , RISCV_REG_F29_64 = 92 , RISCV_REG_F30_32 = 93 , RISCV_REG_F30_64 = 94 , RISCV_REG_F31_32 = 95 , RISCV_REG_F31_64 = 96 , RISCV_REG_ENDING = 97 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn { RISCV_INS_INVALID = 0 , RISCV_INS_ADD = 1 , RISCV_INS_ADDI = 2 , RISCV_INS_ADDIW = 3 , RISCV_INS_ADDW = 4 , RISCV_INS_AMOADD_D = 5 , RISCV_INS_AMOADD_D_AQ = 6 , RISCV_INS_AMOADD_D_AQ_RL = 7 , RISCV_INS_AMOADD_D_RL = 8 , RISCV_INS_AMOADD_W = 9 , RISCV_INS_AMOADD_W_AQ = 10 , RISCV_INS_AMOADD_W_AQ_RL = 11 , RISCV_INS_AMOADD_W_RL = 12 , RISCV_INS_AMOAND_D = 13 , RISCV_INS_AMOAND_D_AQ = 14 , RISCV_INS_AMOAND_D_AQ_RL = 15 , RISCV_INS_AMOAND_D_RL = 16 , RISCV_INS_AMOAND_W = 17 , RISCV_INS_AMOAND_W_AQ = 18 , RISCV_INS_AMOAND_W_AQ_RL = 19 , RISCV_INS_AMOAND_W_RL = 20 , RISCV_INS_AMOMAXU_D = 21 , RISCV_INS_AMOMAXU_D_AQ = 22 , RISCV_INS_AMOMAXU_D_AQ_RL = 23 , RISCV_INS_AMOMAXU_D_RL = 24 , RISCV_INS_AMOMAXU_W = 25 , RISCV_INS_AMOMAXU_W_AQ = 26 , RISCV_INS_AMOMAXU_W_AQ_RL = 27 , RISCV_INS_AMOMAXU_W_RL = 28 , RISCV_INS_AMOMAX_D = 29 , RISCV_INS_AMOMAX_D_AQ = 30 , RISCV_INS_AMOMAX_D_AQ_RL = 31 , RISCV_INS_AMOMAX_D_RL = 32 , RISCV_INS_AMOMAX_W = 33 , RISCV_INS_AMOMAX_W_AQ = 34 , RISCV_INS_AMOMAX_W_AQ_RL = 35 , RISCV_INS_AMOMAX_W_RL = 36 , RISCV_INS_AMOMINU_D = 37 , RISCV_INS_AMOMINU_D_AQ = 38 , RISCV_INS_AMOMINU_D_AQ_RL = 39 , RISCV_INS_AMOMINU_D_RL = 40 , RISCV_INS_AMOMINU_W = 41 , RISCV_INS_AMOMINU_W_AQ = 42 , RISCV_INS_AMOMINU_W_AQ_RL = 43 , RISCV_INS_AMOMINU_W_RL = 44 , RISCV_INS_AMOMIN_D = 45 , RISCV_INS_AMOMIN_D_AQ = 46 , RISCV_INS_AMOMIN_D_AQ_RL = 47 , RISCV_INS_AMOMIN_D_RL = 48 , RISCV_INS_AMOMIN_W = 49 , RISCV_INS_AMOMIN_W_AQ = 50 , RISCV_INS_AMOMIN_W_AQ_RL = 51 , RISCV_INS_AMOMIN_W_RL = 52 , RISCV_INS_AMOOR_D = 53 , RISCV_INS_AMOOR_D_AQ = 54 , RISCV_INS_AMOOR_D_AQ_RL = 55 , RISCV_INS_AMOOR_D_RL = 56 , RISCV_INS_AMOOR_W = 57 , RISCV_INS_AMOOR_W_AQ = 58 , RISCV_INS_AMOOR_W_AQ_RL = 59 , RISCV_INS_AMOOR_W_RL = 60 , RISCV_INS_AMOSWAP_D = 61 , RISCV_INS_AMOSWAP_D_AQ = 62 , RISCV_INS_AMOSWAP_D_AQ_RL = 63 , RISCV_INS_AMOSWAP_D_RL = 64 , RISCV_INS_AMOSWAP_W = 65 , RISCV_INS_AMOSWAP_W_AQ = 66 , RISCV_INS_AMOSWAP_W_AQ_RL = 67 , RISCV_INS_AMOSWAP_W_RL = 68 , RISCV_INS_AMOXOR_D = 69 , RISCV_INS_AMOXOR_D_AQ = 70 , RISCV_INS_AMOXOR_D_AQ_RL = 71 , RISCV_INS_AMOXOR_D_RL = 72 , RISCV_INS_AMOXOR_W = 73 , RISCV_INS_AMOXOR_W_AQ = 74 , RISCV_INS_AMOXOR_W_AQ_RL = 75 , RISCV_INS_AMOXOR_W_RL = 76 , RISCV_INS_AND = 77 , RISCV_INS_ANDI = 78 , RISCV_INS_AUIPC = 79 , RISCV_INS_BEQ = 80 , RISCV_INS_BGE = 81 , RISCV_INS_BGEU = 82 , RISCV_INS_BLT = 83 , RISCV_INS_BLTU = 84 , RISCV_INS_BNE = 85 , RISCV_INS_CSRRC = 86 , RISCV_INS_CSRRCI = 87 , RISCV_INS_CSRRS = 88 , RISCV_INS_CSRRSI = 89 , RISCV_INS_CSRRW = 90 , RISCV_INS_CSRRWI = 91 , RISCV_INS_C_ADD = 92 , RISCV_INS_C_ADDI = 93 , RISCV_INS_C_ADDI16SP = 94 , RISCV_INS_C_ADDI4SPN = 95 , RISCV_INS_C_ADDIW = 96 , RISCV_INS_C_ADDW = 97 , RISCV_INS_C_AND = 98 , RISCV_INS_C_ANDI = 99 , RISCV_INS_C_BEQZ = 100 , RISCV_INS_C_BNEZ = 101 , RISCV_INS_C_EBREAK = 102 , RISCV_INS_C_FLD = 103 , RISCV_INS_C_FLDSP = 104 , RISCV_INS_C_FLW = 105 , RISCV_INS_C_FLWSP = 106 , RISCV_INS_C_FSD = 107 , RISCV_INS_C_FSDSP = 108 , RISCV_INS_C_FSW = 109 , RISCV_INS_C_FSWSP = 110 , RISCV_INS_C_J = 111 , RISCV_INS_C_JAL = 112 , RISCV_INS_C_JALR = 113 , RISCV_INS_C_JR = 114 , RISCV_INS_C_LD = 115 , RISCV_INS_C_LDSP = 116 , RISCV_INS_C_LI = 117 , RISCV_INS_C_LUI = 118 , RISCV_INS_C_LW = 119 , RISCV_INS_C_LWSP = 120 , RISCV_INS_C_MV = 121 , RISCV_INS_C_NOP = 122 , RISCV_INS_C_OR = 123 , RISCV_INS_C_SD = 124 , RISCV_INS_C_SDSP = 125 , RISCV_INS_C_SLLI = 126 , RISCV_INS_C_SRAI = 127 , RISCV_INS_C_SRLI = 128 , RISCV_INS_C_SUB = 129 , RISCV_INS_C_SUBW = 130 , RISCV_INS_C_SW = 131 , RISCV_INS_C_SWSP = 132 , RISCV_INS_C_UNIMP = 133 , RISCV_INS_C_XOR = 134 , RISCV_INS_DIV = 135 , RISCV_INS_DIVU = 136 , RISCV_INS_DIVUW = 137 , RISCV_INS_DIVW = 138 , RISCV_INS_EBREAK = 139 , RISCV_INS_ECALL = 140 , RISCV_INS_FADD_D = 141 , RISCV_INS_FADD_S = 142 , RISCV_INS_FCLASS_D = 143 , RISCV_INS_FCLASS_S = 144 , RISCV_INS_FCVT_D_L = 145 , RISCV_INS_FCVT_D_LU = 146 , RISCV_INS_FCVT_D_S = 147 , RISCV_INS_FCVT_D_W = 148 , RISCV_INS_FCVT_D_WU = 149 , RISCV_INS_FCVT_LU_D = 150 , RISCV_INS_FCVT_LU_S = 151 , RISCV_INS_FCVT_L_D = 152 , RISCV_INS_FCVT_L_S = 153 , RISCV_INS_FCVT_S_D = 154 , RISCV_INS_FCVT_S_L = 155 , RISCV_INS_FCVT_S_LU = 156 , RISCV_INS_FCVT_S_W = 157 , RISCV_INS_FCVT_S_WU = 158 , RISCV_INS_FCVT_WU_D = 159 , RISCV_INS_FCVT_WU_S = 160 , RISCV_INS_FCVT_W_D = 161 , RISCV_INS_FCVT_W_S = 162 , RISCV_INS_FDIV_D = 163 , RISCV_INS_FDIV_S = 164 , RISCV_INS_FENCE = 165 , RISCV_INS_FENCE_I = 166 , RISCV_INS_FENCE_TSO = 167 , RISCV_INS_FEQ_D = 168 , RISCV_INS_FEQ_S = 169 , RISCV_INS_FLD = 170 , RISCV_INS_FLE_D = 171 , RISCV_INS_FLE_S = 172 , RISCV_INS_FLT_D = 173 , RISCV_INS_FLT_S = 174 , RISCV_INS_FLW = 175 , RISCV_INS_FMADD_D = 176 , RISCV_INS_FMADD_S = 177 , RISCV_INS_FMAX_D = 178 , RISCV_INS_FMAX_S = 179 , RISCV_INS_FMIN_D = 180 , RISCV_INS_FMIN_S = 181 , RISCV_INS_FMSUB_D = 182 , RISCV_INS_FMSUB_S = 183 , RISCV_INS_FMUL_D = 184 , RISCV_INS_FMUL_S = 185 , RISCV_INS_FMV_D_X = 186 , RISCV_INS_FMV_W_X = 187 , RISCV_INS_FMV_X_D = 188 , RISCV_INS_FMV_X_W = 189 , RISCV_INS_FNMADD_D = 190 , RISCV_INS_FNMADD_S = 191 , RISCV_INS_FNMSUB_D = 192 , RISCV_INS_FNMSUB_S = 193 , RISCV_INS_FSD = 194 , RISCV_INS_FSGNJN_D = 195 , RISCV_INS_FSGNJN_S = 196 , RISCV_INS_FSGNJX_D = 197 , RISCV_INS_FSGNJX_S = 198 , RISCV_INS_FSGNJ_D = 199 , RISCV_INS_FSGNJ_S = 200 , RISCV_INS_FSQRT_D = 201 , RISCV_INS_FSQRT_S = 202 , RISCV_INS_FSUB_D = 203 , RISCV_INS_FSUB_S = 204 , RISCV_INS_FSW = 205 , RISCV_INS_JAL = 206 , RISCV_INS_JALR = 207 , RISCV_INS_LB = 208 , RISCV_INS_LBU = 209 , RISCV_INS_LD = 210 , RISCV_INS_LH = 211 , RISCV_INS_LHU = 212 , RISCV_INS_LR_D = 213 , RISCV_INS_LR_D_AQ = 214 , RISCV_INS_LR_D_AQ_RL = 215 , RISCV_INS_LR_D_RL = 216 , RISCV_INS_LR_W = 217 , RISCV_INS_LR_W_AQ = 218 , RISCV_INS_LR_W_AQ_RL = 219 , RISCV_INS_LR_W_RL = 220 , RISCV_INS_LUI = 221 , RISCV_INS_LW = 222 , RISCV_INS_LWU = 223 , RISCV_INS_MRET = 224 , RISCV_INS_MUL = 225 , RISCV_INS_MULH = 226 , RISCV_INS_MULHSU = 227 , RISCV_INS_MULHU = 228 , RISCV_INS_MULW = 229 , RISCV_INS_OR = 230 , RISCV_INS_ORI = 231 , RISCV_INS_REM = 232 , RISCV_INS_REMU = 233 , RISCV_INS_REMUW = 234 , RISCV_INS_REMW = 235 , RISCV_INS_SB = 236 , RISCV_INS_SC_D = 237 , RISCV_INS_SC_D_AQ = 238 , RISCV_INS_SC_D_AQ_RL = 239 , RISCV_INS_SC_D_RL = 240 , RISCV_INS_SC_W = 241 , RISCV_INS_SC_W_AQ = 242 , RISCV_INS_SC_W_AQ_RL = 243 , RISCV_INS_SC_W_RL = 244 , RISCV_INS_SD = 245 , RISCV_INS_SFENCE_VMA = 246 , RISCV_INS_SH = 247 , RISCV_INS_SLL = 248 , RISCV_INS_SLLI = 249 , RISCV_INS_SLLIW = 250 , RISCV_INS_SLLW = 251 , RISCV_INS_SLT = 252 , RISCV_INS_SLTI = 253 , RISCV_INS_SLTIU = 254 , RISCV_INS_SLTU = 255 , RISCV_INS_SRA = 256 , RISCV_INS_SRAI = 257 , RISCV_INS_SRAIW = 258 , RISCV_INS_SRAW = 259 , RISCV_INS_SRET = 260 , RISCV_INS_SRL = 261 , RISCV_INS_SRLI = 262 , RISCV_INS_SRLIW = 263 , RISCV_INS_SRLW = 264 , RISCV_INS_SUB = 265 , RISCV_INS_SUBW = 266 , RISCV_INS_SW = 267 , RISCV_INS_UNIMP = 268 , RISCV_INS_URET = 269 , RISCV_INS_WFI = 270 , RISCV_INS_XOR = 271 , RISCV_INS_XORI = 272 , RISCV_INS_ENDING = 273 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn_group { # [doc = "< = CS_GRP_INVALID"] RISCV_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] RISCV_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] RISCV_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] RISCV_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] RISCV_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] RISCV_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] RISCV_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] RISCV_GRP_BRANCH_RELATIVE = 7 , RISCV_GRP_ISRV32 = 128 , RISCV_GRP_ISRV64 = 129 , RISCV_GRP_HASSTDEXTA = 130 , RISCV_GRP_HASSTDEXTC = 131 , RISCV_GRP_HASSTDEXTD = 132 , RISCV_GRP_HASSTDEXTF = 133 , RISCV_GRP_HASSTDEXTM = 134 , RISCV_GRP_ENDING = 135 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_op_type { WASM_OP_INVALID = 0 , WASM_OP_NONE = 1 , WASM_OP_INT7 = 2 , WASM_OP_VARUINT32 = 3 , WASM_OP_VARUINT64 = 4 , WASM_OP_UINT32 = 5 , WASM_OP_UINT64 = 6 , WASM_OP_IMM = 7 , WASM_OP_BRTABLE = 8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_wasm_brtable { pub length : u32 , pub address : u64 , pub default_target : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_brtable"] [:: std :: mem :: size_of :: < cs_wasm_brtable > () - 24usize] ; ["Alignment of cs_wasm_brtable"] [:: std :: mem :: align_of :: < cs_wasm_brtable > () - 8usize] ; ["Offset of field: cs_wasm_brtable::length"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , length) - 0usize] ; ["Offset of field: cs_wasm_brtable::address"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , address) - 8usize] ; ["Offset of field: cs_wasm_brtable::default_target"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , default_target) - 16usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm_op { pub type_ : wasm_op_type , pub size : u32 , pub __bindgen_anon_1 : cs_wasm_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_wasm_op__bindgen_ty_1 { pub int7 : i8 , pub varuint32 : u32 , pub varuint64 : u64 , pub uint32 : u32 , pub uint64 : u64 , pub immediate : [u32 ; 2usize] , pub brtable : cs_wasm_brtable , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_wasm_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_wasm_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::int7"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , int7) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::immediate"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , immediate) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::brtable"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , brtable) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op"] [:: std :: mem :: size_of :: < cs_wasm_op > () - 32usize] ; ["Alignment of cs_wasm_op"] [:: std :: mem :: align_of :: < cs_wasm_op > () - 8usize] ; ["Offset of field: cs_wasm_op::type_"] [:: std :: mem :: offset_of ! (cs_wasm_op , type_) - 0usize] ; ["Offset of field: cs_wasm_op::size"] [:: std :: mem :: offset_of ! (cs_wasm_op , size) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . size , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm { pub op_count : u8 , pub operands : [cs_wasm_op ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm"] [:: std :: mem :: size_of :: < cs_wasm > () - 72usize] ; ["Alignment of cs_wasm"] [:: std :: mem :: align_of :: < cs_wasm > () - 8usize] ; ["Offset of field: cs_wasm::op_count"] [:: std :: mem :: offset_of ! (cs_wasm , op_count) - 0usize] ; ["Offset of field: cs_wasm::operands"] [:: std :: mem :: offset_of ! (cs_wasm , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " WASM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn { WASM_INS_UNREACHABLE = 0 , WASM_INS_NOP = 1 , WASM_INS_BLOCK = 2 , WASM_INS_LOOP = 3 , WASM_INS_IF = 4 , WASM_INS_ELSE = 5 , WASM_INS_END = 11 , WASM_INS_BR = 12 , WASM_INS_BR_IF = 13 , WASM_INS_BR_TABLE = 14 , WASM_INS_RETURN = 15 , WASM_INS_CALL = 16 , WASM_INS_CALL_INDIRECT = 17 , WASM_INS_DROP = 26 , WASM_INS_SELECT = 27 , WASM_INS_GET_LOCAL = 32 , WASM_INS_SET_LOCAL = 33 , WASM_INS_TEE_LOCAL = 34 , WASM_INS_GET_GLOBAL = 35 , WASM_INS_SET_GLOBAL = 36 , WASM_INS_I32_LOAD = 40 , WASM_INS_I64_LOAD = 41 , WASM_INS_F32_LOAD = 42 , WASM_INS_F64_LOAD = 43 , WASM_INS_I32_LOAD8_S = 44 , WASM_INS_I32_LOAD8_U = 45 , WASM_INS_I32_LOAD16_S = 46 , WASM_INS_I32_LOAD16_U = 47 , WASM_INS_I64_LOAD8_S = 48 , WASM_INS_I64_LOAD8_U = 49 , WASM_INS_I64_LOAD16_S = 50 , WASM_INS_I64_LOAD16_U = 51 , WASM_INS_I64_LOAD32_S = 52 , WASM_INS_I64_LOAD32_U = 53 , WASM_INS_I32_STORE = 54 , WASM_INS_I64_STORE = 55 , WASM_INS_F32_STORE = 56 , WASM_INS_F64_STORE = 57 , WASM_INS_I32_STORE8 = 58 , WASM_INS_I32_STORE16 = 59 , WASM_INS_I64_STORE8 = 60 , WASM_INS_I64_STORE16 = 61 , WASM_INS_I64_STORE32 = 62 , WASM_INS_CURRENT_MEMORY = 63 , WASM_INS_GROW_MEMORY = 64 , WASM_INS_I32_CONST = 65 , WASM_INS_I64_CONST = 66 , WASM_INS_F32_CONST = 67 , WASM_INS_F64_CONST = 68 , WASM_INS_I32_EQZ = 69 , WASM_INS_I32_EQ = 70 , WASM_INS_I32_NE = 71 , WASM_INS_I32_LT_S = 72 , WASM_INS_I32_LT_U = 73 , WASM_INS_I32_GT_S = 74 , WASM_INS_I32_GT_U = 75 , WASM_INS_I32_LE_S = 76 , WASM_INS_I32_LE_U = 77 , WASM_INS_I32_GE_S = 78 , WASM_INS_I32_GE_U = 79 , WASM_INS_I64_EQZ = 80 , WASM_INS_I64_EQ = 81 , WASM_INS_I64_NE = 82 , WASM_INS_I64_LT_S = 83 , WASM_INS_I64_LT_U = 84 , WASN_INS_I64_GT_S = 85 , WASM_INS_I64_GT_U = 86 , WASM_INS_I64_LE_S = 87 , WASM_INS_I64_LE_U = 88 , WASM_INS_I64_GE_S = 89 , WASM_INS_I64_GE_U = 90 , WASM_INS_F32_EQ = 91 , WASM_INS_F32_NE = 92 , WASM_INS_F32_LT = 93 , WASM_INS_F32_GT = 94 , WASM_INS_F32_LE = 95 , WASM_INS_F32_GE = 96 , WASM_INS_F64_EQ = 97 , WASM_INS_F64_NE = 98 , WASM_INS_F64_LT = 99 , WASM_INS_F64_GT = 100 , WASM_INS_F64_LE = 101 , WASM_INS_F64_GE = 102 , WASM_INS_I32_CLZ = 103 , WASM_INS_I32_CTZ = 104 , WASM_INS_I32_POPCNT = 105 , WASM_INS_I32_ADD = 106 , WASM_INS_I32_SUB = 107 , WASM_INS_I32_MUL = 108 , WASM_INS_I32_DIV_S = 109 , WASM_INS_I32_DIV_U = 110 , WASM_INS_I32_REM_S = 111 , WASM_INS_I32_REM_U = 112 , WASM_INS_I32_AND = 113 , WASM_INS_I32_OR = 114 , WASM_INS_I32_XOR = 115 , WASM_INS_I32_SHL = 116 , WASM_INS_I32_SHR_S = 117 , WASM_INS_I32_SHR_U = 118 , WASM_INS_I32_ROTL = 119 , WASM_INS_I32_ROTR = 120 , WASM_INS_I64_CLZ = 121 , WASM_INS_I64_CTZ = 122 , WASM_INS_I64_POPCNT = 123 , WASM_INS_I64_ADD = 124 , WASM_INS_I64_SUB = 125 , WASM_INS_I64_MUL = 126 , WASM_INS_I64_DIV_S = 127 , WASM_INS_I64_DIV_U = 128 , WASM_INS_I64_REM_S = 129 , WASM_INS_I64_REM_U = 130 , WASM_INS_I64_AND = 131 , WASM_INS_I64_OR = 132 , WASM_INS_I64_XOR = 133 , WASM_INS_I64_SHL = 134 , WASM_INS_I64_SHR_S = 135 , WASM_INS_I64_SHR_U = 136 , WASM_INS_I64_ROTL = 137 , WASM_INS_I64_ROTR = 138 , WASM_INS_F32_ABS = 139 , WASM_INS_F32_NEG = 140 , WASM_INS_F32_CEIL = 141 , WASM_INS_F32_FLOOR = 142 , WASM_INS_F32_TRUNC = 143 , WASM_INS_F32_NEAREST = 144 , WASM_INS_F32_SQRT = 145 , WASM_INS_F32_ADD = 146 , WASM_INS_F32_SUB = 147 , WASM_INS_F32_MUL = 148 , WASM_INS_F32_DIV = 149 , WASM_INS_F32_MIN = 150 , WASM_INS_F32_MAX = 151 , WASM_INS_F32_COPYSIGN = 152 , WASM_INS_F64_ABS = 153 , WASM_INS_F64_NEG = 154 , WASM_INS_F64_CEIL = 155 , WASM_INS_F64_FLOOR = 156 , WASM_INS_F64_TRUNC = 157 , WASM_INS_F64_NEAREST = 158 , WASM_INS_F64_SQRT = 159 , WASM_INS_F64_ADD = 160 , WASM_INS_F64_SUB = 161 , WASM_INS_F64_MUL = 162 , WASM_INS_F64_DIV = 163 , WASM_INS_F64_MIN = 164 , WASM_INS_F64_MAX = 165 , WASM_INS_F64_COPYSIGN = 166 , WASM_INS_I32_WARP_I64 = 167 , WASP_INS_I32_TRUNC_S_F32 = 168 , WASM_INS_I32_TRUNC_U_F32 = 169 , WASM_INS_I32_TRUNC_S_F64 = 170 , WASM_INS_I32_TRUNC_U_F64 = 171 , WASM_INS_I64_EXTEND_S_I32 = 172 , WASM_INS_I64_EXTEND_U_I32 = 173 , WASM_INS_I64_TRUNC_S_F32 = 174 , WASM_INS_I64_TRUNC_U_F32 = 175 , WASM_INS_I64_TRUNC_S_F64 = 176 , WASM_INS_I64_TRUNC_U_F64 = 177 , WASM_INS_F32_CONVERT_S_I32 = 178 , WASM_INS_F32_CONVERT_U_I32 = 179 , WASM_INS_F32_CONVERT_S_I64 = 180 , WASM_INS_F32_CONVERT_U_I64 = 181 , WASM_INS_F32_DEMOTE_F64 = 182 , WASM_INS_F64_CONVERT_S_I32 = 183 , WASM_INS_F64_CONVERT_U_I32 = 184 , WASM_INS_F64_CONVERT_S_I64 = 185 , WASM_INS_F64_CONVERT_U_I64 = 186 , WASM_INS_F64_PROMOTE_F32 = 187 , WASM_INS_I32_REINTERPRET_F32 = 188 , WASM_INS_I64_REINTERPRET_F64 = 189 , WASM_INS_F32_REINTERPRET_I32 = 190 , WASM_INS_F64_REINTERPRET_I64 = 191 , WASM_INS_INVALID = 512 , WASM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of WASM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn_group { # [doc = "< = CS_GRP_INVALID"] WASM_GRP_INVALID = 0 , WASM_GRP_NUMBERIC = 8 , WASM_GRP_PARAMETRIC = 9 , WASM_GRP_VARIABLE = 10 , WASM_GRP_MEMORY = 11 , WASM_GRP_CONTROL = 12 , # [doc = "< <-- mark the end of the list of groups"] WASM_GRP_ENDING = 13 , } # [repr (u32)] # [doc = " MOS65XX registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_reg { MOS65XX_REG_INVALID = 0 , # [doc = "< accumulator"] MOS65XX_REG_ACC = 1 , # [doc = "< X index register"] MOS65XX_REG_X = 2 , # [doc = "< Y index register"] MOS65XX_REG_Y = 3 , # [doc = "< status register"] MOS65XX_REG_P = 4 , # [doc = "< stack pointer register"] MOS65XX_REG_SP = 5 , # [doc = "< direct page register"] MOS65XX_REG_DP = 6 , # [doc = "< data bank register"] MOS65XX_REG_B = 7 , # [doc = "< program bank register"] MOS65XX_REG_K = 8 , MOS65XX_REG_ENDING = 9 , } # [repr (u32)] # [doc = " MOS65XX Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_address_mode { # [doc = "< No address mode."] MOS65XX_AM_NONE = 0 , # [doc = "< implied addressing (no addressing mode)"] MOS65XX_AM_IMP = 1 , # [doc = "< accumulator addressing"] MOS65XX_AM_ACC = 2 , # [doc = "< 8/16 Bit immediate value"] MOS65XX_AM_IMM = 3 , # [doc = "< relative addressing used by branches"] MOS65XX_AM_REL = 4 , # [doc = "< interrupt addressing"] MOS65XX_AM_INT = 5 , # [doc = "< memory block addressing"] MOS65XX_AM_BLOCK = 6 , # [doc = "< zeropage addressing"] MOS65XX_AM_ZP = 7 , # [doc = "< indexed zeropage addressing by the X index register"] MOS65XX_AM_ZP_X = 8 , # [doc = "< indexed zeropage addressing by the Y index register"] MOS65XX_AM_ZP_Y = 9 , # [doc = "< zero page address, branch relative address"] MOS65XX_AM_ZP_REL = 10 , # [doc = "< indirect zeropage addressing"] MOS65XX_AM_ZP_IND = 11 , # [doc = "< indexed zeropage indirect addressing by the X index register"] MOS65XX_AM_ZP_X_IND = 12 , # [doc = "< indirect zeropage indexed addressing by the Y index register"] MOS65XX_AM_ZP_IND_Y = 13 , # [doc = "< zeropage indirect long addressing"] MOS65XX_AM_ZP_IND_LONG = 14 , # [doc = "< zeropage indirect long addressing indexed by Y register"] MOS65XX_AM_ZP_IND_LONG_Y = 15 , # [doc = "< absolute addressing"] MOS65XX_AM_ABS = 16 , # [doc = "< indexed absolute addressing by the X index register"] MOS65XX_AM_ABS_X = 17 , # [doc = "< indexed absolute addressing by the Y index register"] MOS65XX_AM_ABS_Y = 18 , # [doc = "< absolute indirect addressing"] MOS65XX_AM_ABS_IND = 19 , # [doc = "< indexed absolute indirect addressing by the X index register"] MOS65XX_AM_ABS_X_IND = 20 , # [doc = "< absolute indirect long addressing"] MOS65XX_AM_ABS_IND_LONG = 21 , # [doc = "< absolute long address mode"] MOS65XX_AM_ABS_LONG = 22 , # [doc = "< absolute long address mode, indexed by X register"] MOS65XX_AM_ABS_LONG_X = 23 , # [doc = "< stack relative addressing"] MOS65XX_AM_SR = 24 , # [doc = "< indirect stack relative addressing indexed by the Y index register"] MOS65XX_AM_SR_IND_Y = 25 , } # [repr (u32)] # [doc = " MOS65XX instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_insn { MOS65XX_INS_INVALID = 0 , MOS65XX_INS_ADC = 1 , MOS65XX_INS_AND = 2 , MOS65XX_INS_ASL = 3 , MOS65XX_INS_BBR = 4 , MOS65XX_INS_BBS = 5 , MOS65XX_INS_BCC = 6 , MOS65XX_INS_BCS = 7 , MOS65XX_INS_BEQ = 8 , MOS65XX_INS_BIT = 9 , MOS65XX_INS_BMI = 10 , MOS65XX_INS_BNE = 11 , MOS65XX_INS_BPL = 12 , MOS65XX_INS_BRA = 13 , MOS65XX_INS_BRK = 14 , MOS65XX_INS_BRL = 15 , MOS65XX_INS_BVC = 16 , MOS65XX_INS_BVS = 17 , MOS65XX_INS_CLC = 18 , MOS65XX_INS_CLD = 19 , MOS65XX_INS_CLI = 20 , MOS65XX_INS_CLV = 21 , MOS65XX_INS_CMP = 22 , MOS65XX_INS_COP = 23 , MOS65XX_INS_CPX = 24 , MOS65XX_INS_CPY = 25 , MOS65XX_INS_DEC = 26 , MOS65XX_INS_DEX = 27 , MOS65XX_INS_DEY = 28 , MOS65XX_INS_EOR = 29 , MOS65XX_INS_INC = 30 , MOS65XX_INS_INX = 31 , MOS65XX_INS_INY = 32 , MOS65XX_INS_JML = 33 , MOS65XX_INS_JMP = 34 , MOS65XX_INS_JSL = 35 , MOS65XX_INS_JSR = 36 , MOS65XX_INS_LDA = 37 , MOS65XX_INS_LDX = 38 , MOS65XX_INS_LDY = 39 , MOS65XX_INS_LSR = 40 , MOS65XX_INS_MVN = 41 , MOS65XX_INS_MVP = 42 , MOS65XX_INS_NOP = 43 , MOS65XX_INS_ORA = 44 , MOS65XX_INS_PEA = 45 , MOS65XX_INS_PEI = 46 , MOS65XX_INS_PER = 47 , MOS65XX_INS_PHA = 48 , MOS65XX_INS_PHB = 49 , MOS65XX_INS_PHD = 50 , MOS65XX_INS_PHK = 51 , MOS65XX_INS_PHP = 52 , MOS65XX_INS_PHX = 53 , MOS65XX_INS_PHY = 54 , MOS65XX_INS_PLA = 55 , MOS65XX_INS_PLB = 56 , MOS65XX_INS_PLD = 57 , MOS65XX_INS_PLP = 58 , MOS65XX_INS_PLX = 59 , MOS65XX_INS_PLY = 60 , MOS65XX_INS_REP = 61 , MOS65XX_INS_RMB = 62 , MOS65XX_INS_ROL = 63 , MOS65XX_INS_ROR = 64 , MOS65XX_INS_RTI = 65 , MOS65XX_INS_RTL = 66 , MOS65XX_INS_RTS = 67 , MOS65XX_INS_SBC = 68 , MOS65XX_INS_SEC = 69 , MOS65XX_INS_SED = 70 , MOS65XX_INS_SEI = 71 , MOS65XX_INS_SEP = 72 , MOS65XX_INS_SMB = 73 , MOS65XX_INS_STA = 74 , MOS65XX_INS_STP = 75 , MOS65XX_INS_STX = 76 , MOS65XX_INS_STY = 77 , MOS65XX_INS_STZ = 78 , MOS65XX_INS_TAX = 79 , MOS65XX_INS_TAY = 80 , MOS65XX_INS_TCD = 81 , MOS65XX_INS_TCS = 82 , MOS65XX_INS_TDC = 83 , MOS65XX_INS_TRB = 84 , MOS65XX_INS_TSB = 85 , MOS65XX_INS_TSC = 86 , MOS65XX_INS_TSX = 87 , MOS65XX_INS_TXA = 88 , MOS65XX_INS_TXS = 89 , MOS65XX_INS_TXY = 90 , MOS65XX_INS_TYA = 91 , MOS65XX_INS_TYX = 92 , MOS65XX_INS_WAI = 93 , MOS65XX_INS_WDM = 94 , MOS65XX_INS_XBA = 95 , MOS65XX_INS_XCE = 96 , MOS65XX_INS_ENDING = 97 , } # [repr (u32)] # [doc = " Group of MOS65XX instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_group_type { # [doc = "< CS_GRP_INVALID"] MOS65XX_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MOS65XX_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MOS65XX_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MOS65XX_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MOS65XX_GRP_BRANCH_RELATIVE = 6 , MOS65XX_GRP_ENDING = 7 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MOS65XX_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MOS65XX_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MOS65XX_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MOS65XX_OP_MEM = 3 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx_op { # [doc = "< operand type"] pub type_ : mos65xx_op_type , pub __bindgen_anon_1 : cs_mos65xx_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mos65xx_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : mos65xx_reg , # [doc = "< immediate value for IMM operand"] pub imm : u16 , # [doc = "< address for MEM operand"] pub mem : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Alignment of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op"] [:: std :: mem :: size_of :: < cs_mos65xx_op > () - 8usize] ; ["Alignment of cs_mos65xx_op"] [:: std :: mem :: align_of :: < cs_mos65xx_op > () - 4usize] ; ["Offset of field: cs_mos65xx_op::type_"] [:: std :: mem :: offset_of ! (cs_mos65xx_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The MOS65XX address mode and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx { pub am : mos65xx_address_mode , pub modifies_flags : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mos65xx_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx"] [:: std :: mem :: size_of :: < cs_mos65xx > () - 32usize] ; ["Alignment of cs_mos65xx"] [:: std :: mem :: align_of :: < cs_mos65xx > () - 4usize] ; ["Offset of field: cs_mos65xx::am"] [:: std :: mem :: offset_of ! (cs_mos65xx , am) - 0usize] ; ["Offset of field: cs_mos65xx::modifies_flags"] [:: std :: mem :: offset_of ! (cs_mos65xx , modifies_flags) - 4usize] ; ["Offset of field: cs_mos65xx::op_count"] [:: std :: mem :: offset_of ! (cs_mos65xx , op_count) - 5usize] ; ["Offset of field: cs_mos65xx::operands"] [:: std :: mem :: offset_of ! (cs_mos65xx , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . am , self . modifies_flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_op_type { BPF_OP_INVALID = 0 , BPF_OP_REG = 1 , BPF_OP_IMM = 2 , BPF_OP_OFF = 3 , BPF_OP_MEM = 4 , # [doc = "< M[k] in cBPF"] BPF_OP_MMEM = 5 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] BPF_OP_MSH = 6 , # [doc = "< cBPF's extension (not eBPF)"] BPF_OP_EXT = 7 , } # [repr (u32)] # [doc = " BPF registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_reg { BPF_REG_INVALID = 0 , BPF_REG_A = 1 , BPF_REG_X = 2 , BPF_REG_R0 = 3 , BPF_REG_R1 = 4 , BPF_REG_R2 = 5 , BPF_REG_R3 = 6 , BPF_REG_R4 = 7 , BPF_REG_R5 = 8 , BPF_REG_R6 = 9 , BPF_REG_R7 = 10 , BPF_REG_R8 = 11 , BPF_REG_R9 = 12 , BPF_REG_R10 = 13 , BPF_REG_ENDING = 14 , } # [doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct bpf_op_mem { # [doc = "< base register"] pub base : bpf_reg , # [doc = "< offset value"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of bpf_op_mem"] [:: std :: mem :: size_of :: < bpf_op_mem > () - 8usize] ; ["Alignment of bpf_op_mem"] [:: std :: mem :: align_of :: < bpf_op_mem > () - 4usize] ; ["Offset of field: bpf_op_mem::base"] [:: std :: mem :: offset_of ! (bpf_op_mem , base) - 0usize] ; ["Offset of field: bpf_op_mem::disp"] [:: std :: mem :: offset_of ! (bpf_op_mem , disp) - 4usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_ext_type { BPF_EXT_INVALID = 0 , BPF_EXT_LEN = 1 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf_op { pub type_ : bpf_op_type , pub __bindgen_anon_1 : cs_bpf_op__bindgen_ty_1 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_bpf_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : u8 , # [doc = "< immediate value IMM operand"] pub imm : u64 , # [doc = "< offset value, used in jump & call"] pub off : u32 , # [doc = "< base/disp value for MEM operand"] pub mem : bpf_op_mem , # [doc = "< M[k] in cBPF"] pub mmem : u32 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] pub msh : u32 , # [doc = "< cBPF's extension (not eBPF)"] pub ext : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::off"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , off) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mmem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mmem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::msh"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , msh) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , ext) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op"] [:: std :: mem :: size_of :: < cs_bpf_op > () - 24usize] ; ["Alignment of cs_bpf_op"] [:: std :: mem :: align_of :: < cs_bpf_op > () - 8usize] ; ["Offset of field: cs_bpf_op::type_"] [:: std :: mem :: offset_of ! (cs_bpf_op , type_) - 0usize] ; ["Offset of field: cs_bpf_op::access"] [:: std :: mem :: offset_of ! (cs_bpf_op , access) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf { pub op_count : u8 , pub operands : [cs_bpf_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf"] [:: std :: mem :: size_of :: < cs_bpf > () - 104usize] ; ["Alignment of cs_bpf"] [:: std :: mem :: align_of :: < cs_bpf > () - 8usize] ; ["Offset of field: cs_bpf::op_count"] [:: std :: mem :: offset_of ! (cs_bpf , op_count) - 0usize] ; ["Offset of field: cs_bpf::operands"] [:: std :: mem :: offset_of ! (cs_bpf , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } impl bpf_insn { pub const BPF_INS_LD : bpf_insn = bpf_insn :: BPF_INS_LDW ; } impl bpf_insn { pub const BPF_INS_LDX : bpf_insn = bpf_insn :: BPF_INS_LDXW ; } impl bpf_insn { pub const BPF_INS_ST : bpf_insn = bpf_insn :: BPF_INS_STW ; } impl bpf_insn { pub const BPF_INS_STX : bpf_insn = bpf_insn :: BPF_INS_STXW ; } # [repr (u32)] # [doc = " BPF instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn { BPF_INS_INVALID = 0 , BPF_INS_ADD = 1 , BPF_INS_SUB = 2 , BPF_INS_MUL = 3 , BPF_INS_DIV = 4 , BPF_INS_OR = 5 , BPF_INS_AND = 6 , BPF_INS_LSH = 7 , BPF_INS_RSH = 8 , BPF_INS_NEG = 9 , BPF_INS_MOD = 10 , BPF_INS_XOR = 11 , # [doc = "< eBPF only"] BPF_INS_MOV = 12 , # [doc = "< eBPF only"] BPF_INS_ARSH = 13 , BPF_INS_ADD64 = 14 , BPF_INS_SUB64 = 15 , BPF_INS_MUL64 = 16 , BPF_INS_DIV64 = 17 , BPF_INS_OR64 = 18 , BPF_INS_AND64 = 19 , BPF_INS_LSH64 = 20 , BPF_INS_RSH64 = 21 , BPF_INS_NEG64 = 22 , BPF_INS_MOD64 = 23 , BPF_INS_XOR64 = 24 , BPF_INS_MOV64 = 25 , BPF_INS_ARSH64 = 26 , BPF_INS_LE16 = 27 , BPF_INS_LE32 = 28 , BPF_INS_LE64 = 29 , BPF_INS_BE16 = 30 , BPF_INS_BE32 = 31 , BPF_INS_BE64 = 32 , # [doc = "< eBPF only"] BPF_INS_LDW = 33 , BPF_INS_LDH = 34 , BPF_INS_LDB = 35 , # [doc = "< eBPF only: load 64-bit imm"] BPF_INS_LDDW = 36 , # [doc = "< eBPF only"] BPF_INS_LDXW = 37 , # [doc = "< eBPF only"] BPF_INS_LDXH = 38 , # [doc = "< eBPF only"] BPF_INS_LDXB = 39 , # [doc = "< eBPF only"] BPF_INS_LDXDW = 40 , # [doc = "< eBPF only"] BPF_INS_STW = 41 , # [doc = "< eBPF only"] BPF_INS_STH = 42 , # [doc = "< eBPF only"] BPF_INS_STB = 43 , # [doc = "< eBPF only"] BPF_INS_STDW = 44 , # [doc = "< eBPF only"] BPF_INS_STXW = 45 , # [doc = "< eBPF only"] BPF_INS_STXH = 46 , # [doc = "< eBPF only"] BPF_INS_STXB = 47 , # [doc = "< eBPF only"] BPF_INS_STXDW = 48 , # [doc = "< eBPF only"] BPF_INS_XADDW = 49 , # [doc = "< eBPF only"] BPF_INS_XADDDW = 50 , BPF_INS_JMP = 51 , BPF_INS_JEQ = 52 , BPF_INS_JGT = 53 , BPF_INS_JGE = 54 , BPF_INS_JSET = 55 , # [doc = "< eBPF only"] BPF_INS_JNE = 56 , # [doc = "< eBPF only"] BPF_INS_JSGT = 57 , # [doc = "< eBPF only"] BPF_INS_JSGE = 58 , # [doc = "< eBPF only"] BPF_INS_CALL = 59 , # [doc = "< eBPF only"] BPF_INS_CALLX = 60 , # [doc = "< eBPF only"] BPF_INS_EXIT = 61 , # [doc = "< eBPF only"] BPF_INS_JLT = 62 , # [doc = "< eBPF only"] BPF_INS_JLE = 63 , # [doc = "< eBPF only"] BPF_INS_JSLT = 64 , # [doc = "< eBPF only"] BPF_INS_JSLE = 65 , BPF_INS_RET = 66 , BPF_INS_TAX = 67 , BPF_INS_TXA = 68 , BPF_INS_ENDING = 69 , } # [repr (u32)] # [doc = " Group of BPF instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn_group { # [doc = "< = CS_GRP_INVALID"] BPF_GRP_INVALID = 0 , BPF_GRP_LOAD = 1 , BPF_GRP_STORE = 2 , BPF_GRP_ALU = 3 , BPF_GRP_JUMP = 4 , # [doc = "< eBPF only"] BPF_GRP_CALL = 5 , BPF_GRP_RETURN = 6 , # [doc = "< cBPF only"] BPF_GRP_MISC = 7 , BPF_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " SH registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_reg { SH_REG_INVALID = 0 , SH_REG_R0 = 1 , SH_REG_R1 = 2 , SH_REG_R2 = 3 , SH_REG_R3 = 4 , SH_REG_R4 = 5 , SH_REG_R5 = 6 , SH_REG_R6 = 7 , SH_REG_R7 = 8 , SH_REG_R8 = 9 , SH_REG_R9 = 10 , SH_REG_R10 = 11 , SH_REG_R11 = 12 , SH_REG_R12 = 13 , SH_REG_R13 = 14 , SH_REG_R14 = 15 , SH_REG_R15 = 16 , SH_REG_R0_BANK = 17 , SH_REG_R1_BANK = 18 , SH_REG_R2_BANK = 19 , SH_REG_R3_BANK = 20 , SH_REG_R4_BANK = 21 , SH_REG_R5_BANK = 22 , SH_REG_R6_BANK = 23 , SH_REG_R7_BANK = 24 , SH_REG_FR0 = 25 , SH_REG_FR1 = 26 , SH_REG_FR2 = 27 , SH_REG_FR3 = 28 , SH_REG_FR4 = 29 , SH_REG_FR5 = 30 , SH_REG_FR6 = 31 , SH_REG_FR7 = 32 , SH_REG_FR8 = 33 , SH_REG_FR9 = 34 , SH_REG_FR10 = 35 , SH_REG_FR11 = 36 , SH_REG_FR12 = 37 , SH_REG_FR13 = 38 , SH_REG_FR14 = 39 , SH_REG_FR15 = 40 , SH_REG_DR0 = 41 , SH_REG_DR2 = 42 , SH_REG_DR4 = 43 , SH_REG_DR6 = 44 , SH_REG_DR8 = 45 , SH_REG_DR10 = 46 , SH_REG_DR12 = 47 , SH_REG_DR14 = 48 , SH_REG_XD0 = 49 , SH_REG_XD2 = 50 , SH_REG_XD4 = 51 , SH_REG_XD6 = 52 , SH_REG_XD8 = 53 , SH_REG_XD10 = 54 , SH_REG_XD12 = 55 , SH_REG_XD14 = 56 , SH_REG_XF0 = 57 , SH_REG_XF1 = 58 , SH_REG_XF2 = 59 , SH_REG_XF3 = 60 , SH_REG_XF4 = 61 , SH_REG_XF5 = 62 , SH_REG_XF6 = 63 , SH_REG_XF7 = 64 , SH_REG_XF8 = 65 , SH_REG_XF9 = 66 , SH_REG_XF10 = 67 , SH_REG_XF11 = 68 , SH_REG_XF12 = 69 , SH_REG_XF13 = 70 , SH_REG_XF14 = 71 , SH_REG_XF15 = 72 , SH_REG_FV0 = 73 , SH_REG_FV4 = 74 , SH_REG_FV8 = 75 , SH_REG_FV12 = 76 , SH_REG_XMATRX = 77 , SH_REG_PC = 78 , SH_REG_PR = 79 , SH_REG_MACH = 80 , SH_REG_MACL = 81 , SH_REG_SR = 82 , SH_REG_GBR = 83 , SH_REG_SSR = 84 , SH_REG_SPC = 85 , SH_REG_SGR = 86 , SH_REG_DBR = 87 , SH_REG_VBR = 88 , SH_REG_TBR = 89 , SH_REG_RS = 90 , SH_REG_RE = 91 , SH_REG_MOD = 92 , SH_REG_FPUL = 93 , SH_REG_FPSCR = 94 , SH_REG_DSP_X0 = 95 , SH_REG_DSP_X1 = 96 , SH_REG_DSP_Y0 = 97 , SH_REG_DSP_Y1 = 98 , SH_REG_DSP_A0 = 99 , SH_REG_DSP_A1 = 100 , SH_REG_DSP_A0G = 101 , SH_REG_DSP_A1G = 102 , SH_REG_DSP_M0 = 103 , SH_REG_DSP_M1 = 104 , SH_REG_DSP_DSR = 105 , SH_REG_DSP_RSV0 = 106 , SH_REG_DSP_RSV1 = 107 , SH_REG_DSP_RSV2 = 108 , SH_REG_DSP_RSV3 = 109 , SH_REG_DSP_RSV4 = 110 , SH_REG_DSP_RSV5 = 111 , SH_REG_DSP_RSV6 = 112 , SH_REG_DSP_RSV7 = 113 , SH_REG_DSP_RSV8 = 114 , SH_REG_DSP_RSV9 = 115 , SH_REG_DSP_RSVA = 116 , SH_REG_DSP_RSVB = 117 , SH_REG_DSP_RSVC = 118 , SH_REG_DSP_RSVD = 119 , SH_REG_DSP_RSVE = 120 , SH_REG_DSP_RSVF = 121 , SH_REG_ENDING = 122 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SH_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SH_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SH_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SH_OP_MEM = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_mem_type { SH_OP_MEM_INVALID = 0 , # [doc = " <= Invalid"] SH_OP_MEM_REG_IND = 1 , # [doc = " <= Register indirect"] SH_OP_MEM_REG_POST = 2 , # [doc = " <= Register post increment"] SH_OP_MEM_REG_PRE = 3 , # [doc = " <= Register pre decrement"] SH_OP_MEM_REG_DISP = 4 , # [doc = " <= displacement"] SH_OP_MEM_REG_R0 = 5 , # [doc = " <= R0 indexed"] SH_OP_MEM_GBR_DISP = 6 , # [doc = " <= GBR based displacement"] SH_OP_MEM_GBR_R0 = 7 , # [doc = " <= GBR based R0 indexed"] SH_OP_MEM_PCR = 8 , # [doc = " <= PC relative"] SH_OP_MEM_TBR_DISP = 9 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_mem { pub address : sh_op_mem_type , # [doc = " <= memory address"] pub reg : sh_reg , # [doc = " <= base register"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_mem"] [:: std :: mem :: size_of :: < sh_op_mem > () - 12usize] ; ["Alignment of sh_op_mem"] [:: std :: mem :: align_of :: < sh_op_mem > () - 4usize] ; ["Offset of field: sh_op_mem::address"] [:: std :: mem :: offset_of ! (sh_op_mem , address) - 0usize] ; ["Offset of field: sh_op_mem::reg"] [:: std :: mem :: offset_of ! (sh_op_mem , reg) - 4usize] ; ["Offset of field: sh_op_mem::disp"] [:: std :: mem :: offset_of ! (sh_op_mem , disp) - 8usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn_type { SH_INS_DSP_INVALID = 0 , SH_INS_DSP_DOUBLE = 1 , SH_INS_DSP_SINGLE = 2 , SH_INS_DSP_PARALLEL = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn { SH_INS_DSP_NOP = 1 , SH_INS_DSP_MOV = 2 , SH_INS_DSP_PSHL = 3 , SH_INS_DSP_PSHA = 4 , SH_INS_DSP_PMULS = 5 , SH_INS_DSP_PCLR_PMULS = 6 , SH_INS_DSP_PSUB_PMULS = 7 , SH_INS_DSP_PADD_PMULS = 8 , SH_INS_DSP_PSUBC = 9 , SH_INS_DSP_PADDC = 10 , SH_INS_DSP_PCMP = 11 , SH_INS_DSP_PABS = 12 , SH_INS_DSP_PRND = 13 , SH_INS_DSP_PSUB = 14 , SH_INS_DSP_PSUBr = 15 , SH_INS_DSP_PADD = 16 , SH_INS_DSP_PAND = 17 , SH_INS_DSP_PXOR = 18 , SH_INS_DSP_POR = 19 , SH_INS_DSP_PDEC = 20 , SH_INS_DSP_PINC = 21 , SH_INS_DSP_PCLR = 22 , SH_INS_DSP_PDMSB = 23 , SH_INS_DSP_PNEG = 24 , SH_INS_DSP_PCOPY = 25 , SH_INS_DSP_PSTS = 26 , SH_INS_DSP_PLDS = 27 , SH_INS_DSP_PSWAP = 28 , SH_INS_DSP_PWAD = 29 , SH_INS_DSP_PWSB = 30 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_operand { SH_OP_DSP_INVALID = 0 , SH_OP_DSP_REG_PRE = 1 , SH_OP_DSP_REG_IND = 2 , SH_OP_DSP_REG_POST = 3 , SH_OP_DSP_REG_INDEX = 4 , SH_OP_DSP_REG = 5 , SH_OP_DSP_IMM = 6 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_cc { SH_DSP_CC_INVALID = 0 , SH_DSP_CC_NONE = 1 , SH_DSP_CC_DCT = 2 , SH_DSP_CC_DCF = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_dsp { pub insn : sh_dsp_insn , pub operand : [sh_dsp_operand ; 2usize] , pub r : [sh_reg ; 6usize] , pub cc : sh_dsp_cc , pub imm : u8 , pub size : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_dsp"] [:: std :: mem :: size_of :: < sh_op_dsp > () - 48usize] ; ["Alignment of sh_op_dsp"] [:: std :: mem :: align_of :: < sh_op_dsp > () - 4usize] ; ["Offset of field: sh_op_dsp::insn"] [:: std :: mem :: offset_of ! (sh_op_dsp , insn) - 0usize] ; ["Offset of field: sh_op_dsp::operand"] [:: std :: mem :: offset_of ! (sh_op_dsp , operand) - 4usize] ; ["Offset of field: sh_op_dsp::r"] [:: std :: mem :: offset_of ! (sh_op_dsp , r) - 12usize] ; ["Offset of field: sh_op_dsp::cc"] [:: std :: mem :: offset_of ! (sh_op_dsp , cc) - 36usize] ; ["Offset of field: sh_op_dsp::imm"] [:: std :: mem :: offset_of ! (sh_op_dsp , imm) - 40usize] ; ["Offset of field: sh_op_dsp::size"] [:: std :: mem :: offset_of ! (sh_op_dsp , size) - 44usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh_op { pub type_ : sh_op_type , pub __bindgen_anon_1 : cs_sh_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sh_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< register value for REG operand"] pub reg : sh_reg , # [doc = "< data when operand is targeting memory"] pub mem : sh_op_mem , # [doc = "< dsp instruction"] pub dsp : sh_op_dsp , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sh_op__bindgen_ty_1 > () - 48usize] ; ["Alignment of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sh_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::dsp"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , dsp) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op"] [:: std :: mem :: size_of :: < cs_sh_op > () - 56usize] ; ["Alignment of cs_sh_op"] [:: std :: mem :: align_of :: < cs_sh_op > () - 8usize] ; ["Offset of field: cs_sh_op::type_"] [:: std :: mem :: offset_of ! (cs_sh_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (u32)] # [doc = " SH instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn { SH_INS_INVALID = 0 , SH_INS_ADD_r = 1 , SH_INS_ADD = 2 , SH_INS_ADDC = 3 , SH_INS_ADDV = 4 , SH_INS_AND = 5 , SH_INS_BAND = 6 , SH_INS_BANDNOT = 7 , SH_INS_BCLR = 8 , SH_INS_BF = 9 , SH_INS_BF_S = 10 , SH_INS_BLD = 11 , SH_INS_BLDNOT = 12 , SH_INS_BOR = 13 , SH_INS_BORNOT = 14 , SH_INS_BRA = 15 , SH_INS_BRAF = 16 , SH_INS_BSET = 17 , SH_INS_BSR = 18 , SH_INS_BSRF = 19 , SH_INS_BST = 20 , SH_INS_BT = 21 , SH_INS_BT_S = 22 , SH_INS_BXOR = 23 , SH_INS_CLIPS = 24 , SH_INS_CLIPU = 25 , SH_INS_CLRDMXY = 26 , SH_INS_CLRMAC = 27 , SH_INS_CLRS = 28 , SH_INS_CLRT = 29 , SH_INS_CMP_EQ = 30 , SH_INS_CMP_GE = 31 , SH_INS_CMP_GT = 32 , SH_INS_CMP_HI = 33 , SH_INS_CMP_HS = 34 , SH_INS_CMP_PL = 35 , SH_INS_CMP_PZ = 36 , SH_INS_CMP_STR = 37 , SH_INS_DIV0S = 38 , SH_INS_DIV0U = 39 , SH_INS_DIV1 = 40 , SH_INS_DIVS = 41 , SH_INS_DIVU = 42 , SH_INS_DMULS_L = 43 , SH_INS_DMULU_L = 44 , SH_INS_DT = 45 , SH_INS_EXTS_B = 46 , SH_INS_EXTS_W = 47 , SH_INS_EXTU_B = 48 , SH_INS_EXTU_W = 49 , SH_INS_FABS = 50 , SH_INS_FADD = 51 , SH_INS_FCMP_EQ = 52 , SH_INS_FCMP_GT = 53 , SH_INS_FCNVDS = 54 , SH_INS_FCNVSD = 55 , SH_INS_FDIV = 56 , SH_INS_FIPR = 57 , SH_INS_FLDI0 = 58 , SH_INS_FLDI1 = 59 , SH_INS_FLDS = 60 , SH_INS_FLOAT = 61 , SH_INS_FMAC = 62 , SH_INS_FMOV = 63 , SH_INS_FMUL = 64 , SH_INS_FNEG = 65 , SH_INS_FPCHG = 66 , SH_INS_FRCHG = 67 , SH_INS_FSCA = 68 , SH_INS_FSCHG = 69 , SH_INS_FSQRT = 70 , SH_INS_FSRRA = 71 , SH_INS_FSTS = 72 , SH_INS_FSUB = 73 , SH_INS_FTRC = 74 , SH_INS_FTRV = 75 , SH_INS_ICBI = 76 , SH_INS_JMP = 77 , SH_INS_JSR = 78 , SH_INS_JSR_N = 79 , SH_INS_LDBANK = 80 , SH_INS_LDC = 81 , SH_INS_LDRC = 82 , SH_INS_LDRE = 83 , SH_INS_LDRS = 84 , SH_INS_LDS = 85 , SH_INS_LDTLB = 86 , SH_INS_MAC_L = 87 , SH_INS_MAC_W = 88 , SH_INS_MOV = 89 , SH_INS_MOVA = 90 , SH_INS_MOVCA = 91 , SH_INS_MOVCO = 92 , SH_INS_MOVI20 = 93 , SH_INS_MOVI20S = 94 , SH_INS_MOVLI = 95 , SH_INS_MOVML = 96 , SH_INS_MOVMU = 97 , SH_INS_MOVRT = 98 , SH_INS_MOVT = 99 , SH_INS_MOVU = 100 , SH_INS_MOVUA = 101 , SH_INS_MUL_L = 102 , SH_INS_MULR = 103 , SH_INS_MULS_W = 104 , SH_INS_MULU_W = 105 , SH_INS_NEG = 106 , SH_INS_NEGC = 107 , SH_INS_NOP = 108 , SH_INS_NOT = 109 , SH_INS_NOTT = 110 , SH_INS_OCBI = 111 , SH_INS_OCBP = 112 , SH_INS_OCBWB = 113 , SH_INS_OR = 114 , SH_INS_PREF = 115 , SH_INS_PREFI = 116 , SH_INS_RESBANK = 117 , SH_INS_ROTCL = 118 , SH_INS_ROTCR = 119 , SH_INS_ROTL = 120 , SH_INS_ROTR = 121 , SH_INS_RTE = 122 , SH_INS_RTS = 123 , SH_INS_RTS_N = 124 , SH_INS_RTV_N = 125 , SH_INS_SETDMX = 126 , SH_INS_SETDMY = 127 , SH_INS_SETRC = 128 , SH_INS_SETS = 129 , SH_INS_SETT = 130 , SH_INS_SHAD = 131 , SH_INS_SHAL = 132 , SH_INS_SHAR = 133 , SH_INS_SHLD = 134 , SH_INS_SHLL = 135 , SH_INS_SHLL16 = 136 , SH_INS_SHLL2 = 137 , SH_INS_SHLL8 = 138 , SH_INS_SHLR = 139 , SH_INS_SHLR16 = 140 , SH_INS_SHLR2 = 141 , SH_INS_SHLR8 = 142 , SH_INS_SLEEP = 143 , SH_INS_STBANK = 144 , SH_INS_STC = 145 , SH_INS_STS = 146 , SH_INS_SUB = 147 , SH_INS_SUBC = 148 , SH_INS_SUBV = 149 , SH_INS_SWAP_B = 150 , SH_INS_SWAP_W = 151 , SH_INS_SYNCO = 152 , SH_INS_TAS = 153 , SH_INS_TRAPA = 154 , SH_INS_TST = 155 , SH_INS_XOR = 156 , SH_INS_XTRCT = 157 , SH_INS_DSP = 158 , SH_INS_ENDING = 159 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh { pub insn : sh_insn , pub size : u8 , pub op_count : u8 , pub operands : [cs_sh_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh"] [:: std :: mem :: size_of :: < cs_sh > () - 176usize] ; ["Alignment of cs_sh"] [:: std :: mem :: align_of :: < cs_sh > () - 8usize] ; ["Offset of field: cs_sh::insn"] [:: std :: mem :: offset_of ! (cs_sh , insn) - 0usize] ; ["Offset of field: cs_sh::size"] [:: std :: mem :: offset_of ! (cs_sh , size) - 4usize] ; ["Offset of field: cs_sh::op_count"] [:: std :: mem :: offset_of ! (cs_sh , op_count) - 5usize] ; ["Offset of field: cs_sh::operands"] [:: std :: mem :: offset_of ! (cs_sh , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sh { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh {{ insn: {:?}, size: {:?}, op_count: {:?}, operands: {:?} }}" , self . insn , self . size , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Group of SH instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn_group { # [doc = "< CS_GRUP_INVALID"] SH_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SH_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] SH_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] SH_GRP_INT = 3 , # [doc = "< = CS_GRP_RET"] SH_GRP_RET = 4 , # [doc = "< = CS_GRP_IRET"] SH_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] SH_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] SH_GRP_BRANCH_RELATIVE = 7 , SH_GRP_SH1 = 8 , SH_GRP_SH2 = 9 , SH_GRP_SH2E = 10 , SH_GRP_SH2DSP = 11 , SH_GRP_SH2A = 12 , SH_GRP_SH2AFPU = 13 , SH_GRP_SH3 = 14 , SH_GRP_SH3DSP = 15 , SH_GRP_SH4 = 16 , SH_GRP_SH4A = 17 , SH_GRP_ENDING = 18 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_op_type { # [doc = "< CS_OP_INVALID (Uninitialized)."] TRICORE_OP_INVALID = 0 , # [doc = "< CS_OP_REG (Register operand)."] TRICORE_OP_REG = 1 , # [doc = "< CS_OP_IMM (Immediate operand)."] TRICORE_OP_IMM = 2 , # [doc = "< CS_OP_MEM (Memory operand)."] TRICORE_OP_MEM = 3 , } # [doc = " Instruction's operand referring to memory\n This is associated with TRICORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tricore_op_mem { # [doc = "< base register"] pub base : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tricore_op_mem"] [:: std :: mem :: size_of :: < tricore_op_mem > () - 8usize] ; ["Alignment of tricore_op_mem"] [:: std :: mem :: align_of :: < tricore_op_mem > () - 4usize] ; ["Offset of field: tricore_op_mem::base"] [:: std :: mem :: offset_of ! (tricore_op_mem , base) - 0usize] ; ["Offset of field: tricore_op_mem::disp"] [:: std :: mem :: offset_of ! (tricore_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore_op { # [doc = "< operand type"] pub type_ : tricore_op_type , pub __bindgen_anon_1 : cs_tricore_op__bindgen_ty_1 , # [doc = "< How is this operand accessed? (READ, WRITE or READ|WRITE)"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tricore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tricore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tricore_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tricore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op"] [:: std :: mem :: size_of :: < cs_tricore_op > () - 16usize] ; ["Alignment of cs_tricore_op"] [:: std :: mem :: align_of :: < cs_tricore_op > () - 4usize] ; ["Offset of field: cs_tricore_op::type_"] [:: std :: mem :: offset_of ! (cs_tricore_op , type_) - 0usize] ; ["Offset of field: cs_tricore_op::access"] [:: std :: mem :: offset_of ! (cs_tricore_op , access) - 12usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore { # [doc = "< number of operands of this instruction."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tricore_op ; 8usize] , # [doc = "< whether the flags register is updated."] pub update_flags : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore"] [:: std :: mem :: size_of :: < cs_tricore > () - 136usize] ; ["Alignment of cs_tricore"] [:: std :: mem :: align_of :: < cs_tricore > () - 4usize] ; ["Offset of field: cs_tricore::op_count"] [:: std :: mem :: offset_of ! (cs_tricore , op_count) - 0usize] ; ["Offset of field: cs_tricore::operands"] [:: std :: mem :: offset_of ! (cs_tricore , operands) - 4usize] ; ["Offset of field: cs_tricore::update_flags"] [:: std :: mem :: offset_of ! (cs_tricore , update_flags) - 132usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore {{ op_count: {:?}, operands: {:?}, update_flags: {:?} }}" , self . op_count , self . operands , self . update_flags) } } # [repr (u32)] # [doc = " TriCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_reg { TRICORE_REG_INVALID = 0 , TRICORE_REG_FCX = 1 , TRICORE_REG_PC = 2 , TRICORE_REG_PCXI = 3 , TRICORE_REG_PSW = 4 , TRICORE_REG_A0 = 5 , TRICORE_REG_A1 = 6 , TRICORE_REG_A2 = 7 , TRICORE_REG_A3 = 8 , TRICORE_REG_A4 = 9 , TRICORE_REG_A5 = 10 , TRICORE_REG_A6 = 11 , TRICORE_REG_A7 = 12 , TRICORE_REG_A8 = 13 , TRICORE_REG_A9 = 14 , TRICORE_REG_A10 = 15 , TRICORE_REG_A11 = 16 , TRICORE_REG_A12 = 17 , TRICORE_REG_A13 = 18 , TRICORE_REG_A14 = 19 , TRICORE_REG_A15 = 20 , TRICORE_REG_D0 = 21 , TRICORE_REG_D1 = 22 , TRICORE_REG_D2 = 23 , TRICORE_REG_D3 = 24 , TRICORE_REG_D4 = 25 , TRICORE_REG_D5 = 26 , TRICORE_REG_D6 = 27 , TRICORE_REG_D7 = 28 , TRICORE_REG_D8 = 29 , TRICORE_REG_D9 = 30 , TRICORE_REG_D10 = 31 , TRICORE_REG_D11 = 32 , TRICORE_REG_D12 = 33 , TRICORE_REG_D13 = 34 , TRICORE_REG_D14 = 35 , TRICORE_REG_D15 = 36 , TRICORE_REG_E0 = 37 , TRICORE_REG_E2 = 38 , TRICORE_REG_E4 = 39 , TRICORE_REG_E6 = 40 , TRICORE_REG_E8 = 41 , TRICORE_REG_E10 = 42 , TRICORE_REG_E12 = 43 , TRICORE_REG_E14 = 44 , TRICORE_REG_P0 = 45 , TRICORE_REG_P2 = 46 , TRICORE_REG_P4 = 47 , TRICORE_REG_P6 = 48 , TRICORE_REG_P8 = 49 , TRICORE_REG_P10 = 50 , TRICORE_REG_P12 = 51 , TRICORE_REG_P14 = 52 , TRICORE_REG_A0_A1 = 53 , TRICORE_REG_A2_A3 = 54 , TRICORE_REG_A4_A5 = 55 , TRICORE_REG_A6_A7 = 56 , TRICORE_REG_A8_A9 = 57 , TRICORE_REG_A10_A11 = 58 , TRICORE_REG_A12_A13 = 59 , TRICORE_REG_A14_A15 = 60 , TRICORE_REG_ENDING = 61 , } # [repr (u32)] # [doc = " TriCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn { TRICORE_INS_INVALID = 0 , TRICORE_INS_XOR_T = 1 , TRICORE_INS_ABSDIFS_B = 2 , TRICORE_INS_ABSDIFS_H = 3 , TRICORE_INS_ABSDIFS = 4 , TRICORE_INS_ABSDIF_B = 5 , TRICORE_INS_ABSDIF_H = 6 , TRICORE_INS_ABSDIF = 7 , TRICORE_INS_ABSS_B = 8 , TRICORE_INS_ABSS_H = 9 , TRICORE_INS_ABSS = 10 , TRICORE_INS_ABS_B = 11 , TRICORE_INS_ABS_H = 12 , TRICORE_INS_ABS = 13 , TRICORE_INS_ADDC = 14 , TRICORE_INS_ADDIH_A = 15 , TRICORE_INS_ADDIH = 16 , TRICORE_INS_ADDI = 17 , TRICORE_INS_ADDSC_AT = 18 , TRICORE_INS_ADDSC_A = 19 , TRICORE_INS_ADDS_BU = 20 , TRICORE_INS_ADDS_B = 21 , TRICORE_INS_ADDS_H = 22 , TRICORE_INS_ADDS_HU = 23 , TRICORE_INS_ADDS_U = 24 , TRICORE_INS_ADDS = 25 , TRICORE_INS_ADDX = 26 , TRICORE_INS_ADD_A = 27 , TRICORE_INS_ADD_B = 28 , TRICORE_INS_ADD_F = 29 , TRICORE_INS_ADD_H = 30 , TRICORE_INS_ADD = 31 , TRICORE_INS_ANDN_T = 32 , TRICORE_INS_ANDN = 33 , TRICORE_INS_AND_ANDN_T = 34 , TRICORE_INS_AND_AND_T = 35 , TRICORE_INS_AND_EQ = 36 , TRICORE_INS_AND_GE_U = 37 , TRICORE_INS_AND_GE = 38 , TRICORE_INS_AND_LT_U = 39 , TRICORE_INS_AND_LT = 40 , TRICORE_INS_AND_NE = 41 , TRICORE_INS_AND_NOR_T = 42 , TRICORE_INS_AND_OR_T = 43 , TRICORE_INS_AND_T = 44 , TRICORE_INS_AND = 45 , TRICORE_INS_BISR = 46 , TRICORE_INS_BMERGE = 47 , TRICORE_INS_BSPLIT = 48 , TRICORE_INS_CACHEA_I = 49 , TRICORE_INS_CACHEA_WI = 50 , TRICORE_INS_CACHEA_W = 51 , TRICORE_INS_CACHEI_I = 52 , TRICORE_INS_CACHEI_WI = 53 , TRICORE_INS_CACHEI_W = 54 , TRICORE_INS_CADDN_A = 55 , TRICORE_INS_CADDN = 56 , TRICORE_INS_CADD_A = 57 , TRICORE_INS_CADD = 58 , TRICORE_INS_CALLA = 59 , TRICORE_INS_CALLI = 60 , TRICORE_INS_CALL = 61 , TRICORE_INS_CLO_B = 62 , TRICORE_INS_CLO_H = 63 , TRICORE_INS_CLO = 64 , TRICORE_INS_CLS_B = 65 , TRICORE_INS_CLS_H = 66 , TRICORE_INS_CLS = 67 , TRICORE_INS_CLZ_B = 68 , TRICORE_INS_CLZ_H = 69 , TRICORE_INS_CLZ = 70 , TRICORE_INS_CMOVN = 71 , TRICORE_INS_CMOV = 72 , TRICORE_INS_CMPSWAP_W = 73 , TRICORE_INS_CMP_F = 74 , TRICORE_INS_CRC32B_W = 75 , TRICORE_INS_CRC32L_W = 76 , TRICORE_INS_CRC32_B = 77 , TRICORE_INS_CRCN = 78 , TRICORE_INS_CSUBN_A = 79 , TRICORE_INS_CSUBN = 80 , TRICORE_INS_CSUB_A = 81 , TRICORE_INS_CSUB = 82 , TRICORE_INS_DEBUG = 83 , TRICORE_INS_DEXTR = 84 , TRICORE_INS_DIFSC_A = 85 , TRICORE_INS_DISABLE = 86 , TRICORE_INS_DIV_F = 87 , TRICORE_INS_DIV_U = 88 , TRICORE_INS_DIV = 89 , TRICORE_INS_DSYNC = 90 , TRICORE_INS_DVADJ = 91 , TRICORE_INS_DVINIT_BU = 92 , TRICORE_INS_DVINIT_B = 93 , TRICORE_INS_DVINIT_HU = 94 , TRICORE_INS_DVINIT_H = 95 , TRICORE_INS_DVINIT_U = 96 , TRICORE_INS_DVINIT = 97 , TRICORE_INS_DVSTEP_U = 98 , TRICORE_INS_DVSTEP = 99 , TRICORE_INS_ENABLE = 100 , TRICORE_INS_EQANY_B = 101 , TRICORE_INS_EQANY_H = 102 , TRICORE_INS_EQZ_A = 103 , TRICORE_INS_EQ_A = 104 , TRICORE_INS_EQ_B = 105 , TRICORE_INS_EQ_H = 106 , TRICORE_INS_EQ_W = 107 , TRICORE_INS_EQ = 108 , TRICORE_INS_EXTR_U = 109 , TRICORE_INS_EXTR = 110 , TRICORE_INS_FCALLA = 111 , TRICORE_INS_FCALLI = 112 , TRICORE_INS_FCALL = 113 , TRICORE_INS_FRET = 114 , TRICORE_INS_FTOHP = 115 , TRICORE_INS_FTOIZ = 116 , TRICORE_INS_FTOI = 117 , TRICORE_INS_FTOQ31Z = 118 , TRICORE_INS_FTOQ31 = 119 , TRICORE_INS_FTOUZ = 120 , TRICORE_INS_FTOU = 121 , TRICORE_INS_GE_A = 122 , TRICORE_INS_GE_U = 123 , TRICORE_INS_GE = 124 , TRICORE_INS_HPTOF = 125 , TRICORE_INS_IMASK = 126 , TRICORE_INS_INSERT = 127 , TRICORE_INS_INSN_T = 128 , TRICORE_INS_INS_T = 129 , TRICORE_INS_ISYNC = 130 , TRICORE_INS_ITOF = 131 , TRICORE_INS_IXMAX_U = 132 , TRICORE_INS_IXMAX = 133 , TRICORE_INS_IXMIN_U = 134 , TRICORE_INS_IXMIN = 135 , TRICORE_INS_JA = 136 , TRICORE_INS_JEQ_A = 137 , TRICORE_INS_JEQ = 138 , TRICORE_INS_JGEZ = 139 , TRICORE_INS_JGE_U = 140 , TRICORE_INS_JGE = 141 , TRICORE_INS_JGTZ = 142 , TRICORE_INS_JI = 143 , TRICORE_INS_JLA = 144 , TRICORE_INS_JLEZ = 145 , TRICORE_INS_JLI = 146 , TRICORE_INS_JLTZ = 147 , TRICORE_INS_JLT_U = 148 , TRICORE_INS_JLT = 149 , TRICORE_INS_JL = 150 , TRICORE_INS_JNED = 151 , TRICORE_INS_JNEI = 152 , TRICORE_INS_JNE_A = 153 , TRICORE_INS_JNE = 154 , TRICORE_INS_JNZ_A = 155 , TRICORE_INS_JNZ_T = 156 , TRICORE_INS_JNZ = 157 , TRICORE_INS_JZ_A = 158 , TRICORE_INS_JZ_T = 159 , TRICORE_INS_JZ = 160 , TRICORE_INS_J = 161 , TRICORE_INS_LDLCX = 162 , TRICORE_INS_LDMST = 163 , TRICORE_INS_LDUCX = 164 , TRICORE_INS_LD_A = 165 , TRICORE_INS_LD_BU = 166 , TRICORE_INS_LD_B = 167 , TRICORE_INS_LD_DA = 168 , TRICORE_INS_LD_D = 169 , TRICORE_INS_LD_HU = 170 , TRICORE_INS_LD_H = 171 , TRICORE_INS_LD_Q = 172 , TRICORE_INS_LD_W = 173 , TRICORE_INS_LEA = 174 , TRICORE_INS_LHA = 175 , TRICORE_INS_LOOPU = 176 , TRICORE_INS_LOOP = 177 , TRICORE_INS_LT_A = 178 , TRICORE_INS_LT_B = 179 , TRICORE_INS_LT_BU = 180 , TRICORE_INS_LT_H = 181 , TRICORE_INS_LT_HU = 182 , TRICORE_INS_LT_U = 183 , TRICORE_INS_LT_W = 184 , TRICORE_INS_LT_WU = 185 , TRICORE_INS_LT = 186 , TRICORE_INS_MADDMS_H = 187 , TRICORE_INS_MADDMS_U = 188 , TRICORE_INS_MADDMS = 189 , TRICORE_INS_MADDM_H = 190 , TRICORE_INS_MADDM_Q = 191 , TRICORE_INS_MADDM_U = 192 , TRICORE_INS_MADDM = 193 , TRICORE_INS_MADDRS_H = 194 , TRICORE_INS_MADDRS_Q = 195 , TRICORE_INS_MADDR_H = 196 , TRICORE_INS_MADDR_Q = 197 , TRICORE_INS_MADDSUMS_H = 198 , TRICORE_INS_MADDSUM_H = 199 , TRICORE_INS_MADDSURS_H = 200 , TRICORE_INS_MADDSUR_H = 201 , TRICORE_INS_MADDSUS_H = 202 , TRICORE_INS_MADDSU_H = 203 , TRICORE_INS_MADDS_H = 204 , TRICORE_INS_MADDS_Q = 205 , TRICORE_INS_MADDS_U = 206 , TRICORE_INS_MADDS = 207 , TRICORE_INS_MADD_F = 208 , TRICORE_INS_MADD_H = 209 , TRICORE_INS_MADD_Q = 210 , TRICORE_INS_MADD_U = 211 , TRICORE_INS_MADD = 212 , TRICORE_INS_MAX_B = 213 , TRICORE_INS_MAX_BU = 214 , TRICORE_INS_MAX_H = 215 , TRICORE_INS_MAX_HU = 216 , TRICORE_INS_MAX_U = 217 , TRICORE_INS_MAX = 218 , TRICORE_INS_MFCR = 219 , TRICORE_INS_MIN_B = 220 , TRICORE_INS_MIN_BU = 221 , TRICORE_INS_MIN_H = 222 , TRICORE_INS_MIN_HU = 223 , TRICORE_INS_MIN_U = 224 , TRICORE_INS_MIN = 225 , TRICORE_INS_MOVH_A = 226 , TRICORE_INS_MOVH = 227 , TRICORE_INS_MOVZ_A = 228 , TRICORE_INS_MOV_AA = 229 , TRICORE_INS_MOV_A = 230 , TRICORE_INS_MOV_D = 231 , TRICORE_INS_MOV_U = 232 , TRICORE_INS_MOV = 233 , TRICORE_INS_MSUBADMS_H = 234 , TRICORE_INS_MSUBADM_H = 235 , TRICORE_INS_MSUBADRS_H = 236 , TRICORE_INS_MSUBADR_H = 237 , TRICORE_INS_MSUBADS_H = 238 , TRICORE_INS_MSUBAD_H = 239 , TRICORE_INS_MSUBMS_H = 240 , TRICORE_INS_MSUBMS_U = 241 , TRICORE_INS_MSUBMS = 242 , TRICORE_INS_MSUBM_H = 243 , TRICORE_INS_MSUBM_Q = 244 , TRICORE_INS_MSUBM_U = 245 , TRICORE_INS_MSUBM = 246 , TRICORE_INS_MSUBRS_H = 247 , TRICORE_INS_MSUBRS_Q = 248 , TRICORE_INS_MSUBR_H = 249 , TRICORE_INS_MSUBR_Q = 250 , TRICORE_INS_MSUBS_H = 251 , TRICORE_INS_MSUBS_Q = 252 , TRICORE_INS_MSUBS_U = 253 , TRICORE_INS_MSUBS = 254 , TRICORE_INS_MSUB_F = 255 , TRICORE_INS_MSUB_H = 256 , TRICORE_INS_MSUB_Q = 257 , TRICORE_INS_MSUB_U = 258 , TRICORE_INS_MSUB = 259 , TRICORE_INS_MTCR = 260 , TRICORE_INS_MULMS_H = 261 , TRICORE_INS_MULM_H = 262 , TRICORE_INS_MULM_U = 263 , TRICORE_INS_MULM = 264 , TRICORE_INS_MULR_H = 265 , TRICORE_INS_MULR_Q = 266 , TRICORE_INS_MULS_U = 267 , TRICORE_INS_MULS = 268 , TRICORE_INS_MUL_F = 269 , TRICORE_INS_MUL_H = 270 , TRICORE_INS_MUL_Q = 271 , TRICORE_INS_MUL_U = 272 , TRICORE_INS_MUL = 273 , TRICORE_INS_NAND_T = 274 , TRICORE_INS_NAND = 275 , TRICORE_INS_NEZ_A = 276 , TRICORE_INS_NE_A = 277 , TRICORE_INS_NE = 278 , TRICORE_INS_NOP = 279 , TRICORE_INS_NOR_T = 280 , TRICORE_INS_NOR = 281 , TRICORE_INS_NOT = 282 , TRICORE_INS_ORN_T = 283 , TRICORE_INS_ORN = 284 , TRICORE_INS_OR_ANDN_T = 285 , TRICORE_INS_OR_AND_T = 286 , TRICORE_INS_OR_EQ = 287 , TRICORE_INS_OR_GE_U = 288 , TRICORE_INS_OR_GE = 289 , TRICORE_INS_OR_LT_U = 290 , TRICORE_INS_OR_LT = 291 , TRICORE_INS_OR_NE = 292 , TRICORE_INS_OR_NOR_T = 293 , TRICORE_INS_OR_OR_T = 294 , TRICORE_INS_OR_T = 295 , TRICORE_INS_OR = 296 , TRICORE_INS_PACK = 297 , TRICORE_INS_PARITY = 298 , TRICORE_INS_POPCNT_W = 299 , TRICORE_INS_Q31TOF = 300 , TRICORE_INS_QSEED_F = 301 , TRICORE_INS_RESTORE = 302 , TRICORE_INS_RET = 303 , TRICORE_INS_RFE = 304 , TRICORE_INS_RFM = 305 , TRICORE_INS_RSLCX = 306 , TRICORE_INS_RSTV = 307 , TRICORE_INS_RSUBS_U = 308 , TRICORE_INS_RSUBS = 309 , TRICORE_INS_RSUB = 310 , TRICORE_INS_SAT_BU = 311 , TRICORE_INS_SAT_B = 312 , TRICORE_INS_SAT_HU = 313 , TRICORE_INS_SAT_H = 314 , TRICORE_INS_SELN_A = 315 , TRICORE_INS_SELN = 316 , TRICORE_INS_SEL_A = 317 , TRICORE_INS_SEL = 318 , TRICORE_INS_SHAS = 319 , TRICORE_INS_SHA_B = 320 , TRICORE_INS_SHA_H = 321 , TRICORE_INS_SHA = 322 , TRICORE_INS_SHUFFLE = 323 , TRICORE_INS_SH_ANDN_T = 324 , TRICORE_INS_SH_AND_T = 325 , TRICORE_INS_SH_B = 326 , TRICORE_INS_SH_EQ = 327 , TRICORE_INS_SH_GE_U = 328 , TRICORE_INS_SH_GE = 329 , TRICORE_INS_SH_H = 330 , TRICORE_INS_SH_LT_U = 331 , TRICORE_INS_SH_LT = 332 , TRICORE_INS_SH_NAND_T = 333 , TRICORE_INS_SH_NE = 334 , TRICORE_INS_SH_NOR_T = 335 , TRICORE_INS_SH_ORN_T = 336 , TRICORE_INS_SH_OR_T = 337 , TRICORE_INS_SH_XNOR_T = 338 , TRICORE_INS_SH_XOR_T = 339 , TRICORE_INS_SH = 340 , TRICORE_INS_STLCX = 341 , TRICORE_INS_STUCX = 342 , TRICORE_INS_ST_A = 343 , TRICORE_INS_ST_B = 344 , TRICORE_INS_ST_DA = 345 , TRICORE_INS_ST_D = 346 , TRICORE_INS_ST_H = 347 , TRICORE_INS_ST_Q = 348 , TRICORE_INS_ST_T = 349 , TRICORE_INS_ST_W = 350 , TRICORE_INS_SUBC = 351 , TRICORE_INS_SUBSC_A = 352 , TRICORE_INS_SUBS_BU = 353 , TRICORE_INS_SUBS_B = 354 , TRICORE_INS_SUBS_HU = 355 , TRICORE_INS_SUBS_H = 356 , TRICORE_INS_SUBS_U = 357 , TRICORE_INS_SUBS = 358 , TRICORE_INS_SUBX = 359 , TRICORE_INS_SUB_A = 360 , TRICORE_INS_SUB_B = 361 , TRICORE_INS_SUB_F = 362 , TRICORE_INS_SUB_H = 363 , TRICORE_INS_SUB = 364 , TRICORE_INS_SVLCX = 365 , TRICORE_INS_SWAPMSK_W = 366 , TRICORE_INS_SWAP_A = 367 , TRICORE_INS_SWAP_W = 368 , TRICORE_INS_SYSCALL = 369 , TRICORE_INS_TLBDEMAP = 370 , TRICORE_INS_TLBFLUSH_A = 371 , TRICORE_INS_TLBFLUSH_B = 372 , TRICORE_INS_TLBMAP = 373 , TRICORE_INS_TLBPROBE_A = 374 , TRICORE_INS_TLBPROBE_I = 375 , TRICORE_INS_TRAPSV = 376 , TRICORE_INS_TRAPV = 377 , TRICORE_INS_UNPACK = 378 , TRICORE_INS_UPDFL = 379 , TRICORE_INS_UTOF = 380 , TRICORE_INS_WAIT = 381 , TRICORE_INS_XNOR_T = 382 , TRICORE_INS_XNOR = 383 , TRICORE_INS_XOR_EQ = 384 , TRICORE_INS_XOR_GE_U = 385 , TRICORE_INS_XOR_GE = 386 , TRICORE_INS_XOR_LT_U = 387 , TRICORE_INS_XOR_LT = 388 , TRICORE_INS_XOR_NE = 389 , TRICORE_INS_XOR = 390 , TRICORE_INS_ENDING = 391 , } # [repr (u32)] # [doc = " Group of TriCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn_group { # [doc = "< = CS_GRP_INVALID"] TRICORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_CALL"] TRICORE_GRP_CALL = 1 , # [doc = "< = CS_GRP_JUMP"] TRICORE_GRP_JUMP = 2 , # [doc = "< mark the end of the list of groups"] TRICORE_GRP_ENDING = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_feature_t { TRICORE_FEATURE_INVALID = 0 , TRICORE_FEATURE_HasV110 = 128 , TRICORE_FEATURE_HasV120_UP = 129 , TRICORE_FEATURE_HasV130_UP = 130 , TRICORE_FEATURE_HasV161 = 131 , TRICORE_FEATURE_HasV160_UP = 132 , TRICORE_FEATURE_HasV131_UP = 133 , TRICORE_FEATURE_HasV161_UP = 134 , TRICORE_FEATURE_HasV162 = 135 , TRICORE_FEATURE_HasV162_UP = 136 , # [doc = "< mark the end of the list of features"] TRICORE_FEATURE_ENDING = 137 , } pub use self :: tricore_feature_t as tricore_feature ; # [doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_detail { pub regs_read : [u16 ; 20usize] , # [doc = "< number of implicit registers read by this insn"] pub regs_read_count : u8 , pub regs_write : [u16 ; 20usize] , # [doc = "< number of implicit registers modified by this insn"] pub regs_write_count : u8 , # [doc = "< list of group this instruction belong to"] pub groups : [u8 ; 8usize] , # [doc = "< number of groups this insn belongs to"] pub groups_count : u8 , # [doc = "< Instruction has writeback operands."] pub writeback : bool , pub __bindgen_anon_1 : cs_detail__bindgen_ty_1 , } # [doc = " Architecture-specific instruction info"] # [repr (C)] # [derive (Copy , Clone)] pub union cs_detail__bindgen_ty_1 { # [doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"] pub x86 : cs_x86 , # [doc = "< ARM64 architecture (aka AArch64)"] pub arm64 : cs_arm64 , # [doc = "< ARM architecture (including Thumb/Thumb2)"] pub arm : cs_arm , # [doc = "< M68K architecture"] pub m68k : cs_m68k , # [doc = "< MIPS architecture"] pub mips : cs_mips , # [doc = "< PowerPC architecture"] pub ppc : cs_ppc , # [doc = "< Sparc architecture"] pub sparc : cs_sparc , # [doc = "< SystemZ architecture"] pub sysz : cs_sysz , # [doc = "< XCore architecture"] pub xcore : cs_xcore , # [doc = "< TMS320C64x architecture"] pub tms320c64x : cs_tms320c64x , # [doc = "< M680X architecture"] pub m680x : cs_m680x , # [doc = "< Ethereum architecture"] pub evm : cs_evm , # [doc = "< MOS65XX architecture (including MOS6502)"] pub mos65xx : cs_mos65xx , # [doc = "< Web Assembly architecture"] pub wasm : cs_wasm , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] pub bpf : cs_bpf , # [doc = "< RISCV architecture"] pub riscv : cs_riscv , # [doc = "< SH architecture"] pub sh : cs_sh , # [doc = "< TriCore architecture"] pub tricore : cs_tricore , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_detail__bindgen_ty_1 > () - 1768usize] ; ["Alignment of cs_detail__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_detail__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_detail__bindgen_ty_1::x86"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , x86) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm64"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm64) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m68k"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m68k) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mips"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mips) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::ppc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , ppc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sparc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sparc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sysz"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sysz) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::xcore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , xcore) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tms320c64x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tms320c64x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m680x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m680x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::evm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , evm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mos65xx"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mos65xx) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::wasm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , wasm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::bpf"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , bpf) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::riscv"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , riscv) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sh"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sh) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tricore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tricore) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_detail__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail"] [:: std :: mem :: size_of :: < cs_detail > () - 1864usize] ; ["Alignment of cs_detail"] [:: std :: mem :: align_of :: < cs_detail > () - 8usize] ; ["Offset of field: cs_detail::regs_read"] [:: std :: mem :: offset_of ! (cs_detail , regs_read) - 0usize] ; ["Offset of field: cs_detail::regs_read_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_read_count) - 40usize] ; ["Offset of field: cs_detail::regs_write"] [:: std :: mem :: offset_of ! (cs_detail , regs_write) - 42usize] ; ["Offset of field: cs_detail::regs_write_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_write_count) - 82usize] ; ["Offset of field: cs_detail::groups"] [:: std :: mem :: offset_of ! (cs_detail , groups) - 83usize] ; ["Offset of field: cs_detail::groups_count"] [:: std :: mem :: offset_of ! (cs_detail , groups_count) - 91usize] ; ["Offset of field: cs_detail::writeback"] [:: std :: mem :: offset_of ! (cs_detail , writeback) - 92usize] ; } ; impl :: std :: fmt :: Debug for cs_detail { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, writeback: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . writeback , self . __bindgen_anon_1) } } # [doc = " Detail information of disassembled instruction"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_insn { # [doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub address : u64 , # [doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub size : u16 , # [doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub bytes : [u8 ; 24usize] , # [doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub mnemonic : [:: std :: os :: raw :: c_char ; 32usize] , # [doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub op_str : [:: std :: os :: raw :: c_char ; 160usize] , # [doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."] pub detail : * mut cs_detail , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_insn"] [:: std :: mem :: size_of :: < cs_insn > () - 248usize] ; ["Alignment of cs_insn"] [:: std :: mem :: align_of :: < cs_insn > () - 8usize] ; ["Offset of field: cs_insn::id"] [:: std :: mem :: offset_of ! (cs_insn , id) - 0usize] ; ["Offset of field: cs_insn::address"] [:: std :: mem :: offset_of ! (cs_insn , address) - 8usize] ; ["Offset of field: cs_insn::size"] [:: std :: mem :: offset_of ! (cs_insn , size) - 16usize] ; ["Offset of field: cs_insn::bytes"] [:: std :: mem :: offset_of ! (cs_insn , bytes) - 18usize] ; ["Offset of field: cs_insn::mnemonic"] [:: std :: mem :: offset_of ! (cs_insn , mnemonic) - 42usize] ; ["Offset of field: cs_insn::op_str"] [:: std :: mem :: offset_of ! (cs_insn , op_str) - 74usize] ; ["Offset of field: cs_insn::detail"] [:: std :: mem :: offset_of ! (cs_insn , detail) - 240usize] ; } ; # [repr (u32)] # [doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_err { # [doc = "< No error: everything was fine"] CS_ERR_OK = 0 , # [doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"] CS_ERR_MEM = 1 , # [doc = "< Unsupported architecture: cs_open()"] CS_ERR_ARCH = 2 , # [doc = "< Invalid handle: cs_op_count(), cs_op_index()"] CS_ERR_HANDLE = 3 , # [doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"] CS_ERR_CSH = 4 , # [doc = "< Invalid/unsupported mode: cs_open()"] CS_ERR_MODE = 5 , # [doc = "< Invalid/unsupported option: cs_option()"] CS_ERR_OPTION = 6 , # [doc = "< Information is unavailable because detail option is OFF"] CS_ERR_DETAIL = 7 , # [doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"] CS_ERR_MEMSETUP = 8 , # [doc = "< Unsupported version (bindings)"] CS_ERR_VERSION = 9 , # [doc = "< Access irrelevant data in \"diet\" engine"] CS_ERR_DIET = 10 , # [doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"] CS_ERR_SKIPDATA = 11 , # [doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_ATT = 12 , # [doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_INTEL = 13 , # [doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_MASM = 14 , } unsafe extern "C" { # [doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."] pub fn cs_version (major : * mut :: std :: os :: raw :: c_int , minor : * mut :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_uint ; } unsafe extern "C" { # [doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."] pub fn cs_support (query : :: std :: os :: raw :: c_int) -> bool ; } unsafe extern "C" { # [doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_open (arch : cs_arch , mode : cs_mode , handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_close (handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"] pub fn cs_option (handle : csh , type_ : cs_opt_type , value : usize) -> cs_err ; } unsafe extern "C" { # [doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"] pub fn cs_errno (handle : csh) -> cs_err ; } unsafe extern "C" { # [doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"] pub fn cs_strerror (code : cs_err) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm (handle : csh , code : * const u8 , code_size : usize , address : u64 , count : usize , insn : * mut * mut cs_insn) -> usize ; } unsafe extern "C" { # [doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."] pub fn cs_free (insn : * mut cs_insn , count : usize) ; } unsafe extern "C" { # [doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"] pub fn cs_malloc (handle : csh) -> * mut cs_insn ; } unsafe extern "C" { # [doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm_iter (handle : csh , code : * mut * const u8 , size : * mut usize , address : * mut u64 , insn : * mut cs_insn) -> bool ; } unsafe extern "C" { # [doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."] pub fn cs_reg_name (handle : csh , reg_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."] pub fn cs_insn_name (handle : csh , insn_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."] pub fn cs_group_name (handle : csh , group_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."] pub fn cs_insn_group (handle : csh , insn : * const cs_insn , group_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."] pub fn cs_reg_read (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."] pub fn cs_reg_write (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."] pub fn cs_op_count (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."] pub fn cs_op_index (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint , position : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } # [doc = " Type of array to keep the list of registers"] pub type cs_regs = [u16 ; 64usize] ; unsafe extern "C" { # [doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_regs_access (handle : csh , insn : * const cs_insn , regs_read : * mut u16 , regs_read_count : * mut u8 , regs_write : * mut u16 , regs_write_count : * mut u8) -> cs_err ; } pub type __builtin_va_list = [__va_list_tag ; 1usize] ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __va_list_tag { pub gp_offset : :: std :: os :: raw :: c_uint , pub fp_offset : :: std :: os :: raw :: c_uint , pub overflow_arg_area : * mut :: std :: os :: raw :: c_void , pub reg_save_area : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __va_list_tag"] [:: std :: mem :: size_of :: < __va_list_tag > () - 24usize] ; ["Alignment of __va_list_tag"] [:: std :: mem :: align_of :: < __va_list_tag > () - 8usize] ; ["Offset of field: __va_list_tag::gp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , gp_offset) - 0usize] ; ["Offset of field: __va_list_tag::fp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , fp_offset) - 4usize] ; ["Offset of field: __va_list_tag::overflow_arg_area"] [:: std :: mem :: offset_of ! (__va_list_tag , overflow_arg_area) - 8usize] ; ["Offset of field: __va_list_tag::reg_save_area"] [:: std :: mem :: offset_of ! (__va_list_tag , reg_save_area) - 16usize] ; } ;
[INFO] [stdout] 3 + # [repr (C)] # [derive (Copy , Clone , Debug , Default , Eq , Hash , Ord , PartialEq , PartialOrd)] pub struct __BindgenBitfieldUnit < Storage > { storage : Storage , } impl < Storage > __BindgenBitfieldUnit < Storage > { # [inline] pub const fn new (storage : Storage) -> Self { Self { storage } } } impl < Storage > __BindgenBitfieldUnit < Storage > where Storage : AsRef < [u8] > + AsMut < [u8] >, { # [inline] fn extract_bit (byte : u8 , index : usize) -> bool { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; byte & mask == mask } # [inline] pub fn get_bit (& self , index : usize) -> bool { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = self . storage . as_ref () [byte_index] ; Self :: extract_bit (byte , index) } # [inline] pub unsafe fn raw_get_bit (this : * const Self , index : usize) -> bool { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { * (core :: ptr :: addr_of ! ((* this) . storage) as * const u8) . offset (byte_index as isize) } ; Self :: extract_bit (byte , index) } # [inline] fn change_bit (byte : u8 , index : usize , val : bool) -> u8 { let bit_index = if cfg ! (target_endian = "big") { 7 - (index % 8) } else { index % 8 } ; let mask = 1 << bit_index ; if val { byte | mask } else { byte & ! mask } } # [inline] pub fn set_bit (& mut self , index : usize , val : bool) { debug_assert ! (index / 8 < self . storage . as_ref () . len ()) ; let byte_index = index / 8 ; let byte = & mut self . storage . as_mut () [byte_index] ; * byte = Self :: change_bit (* byte , index , val) ; } # [inline] pub unsafe fn raw_set_bit (this : * mut Self , index : usize , val : bool) { debug_assert ! (index / 8 < core :: mem :: size_of ::< Storage > ()) ; let byte_index = index / 8 ; let byte = unsafe { (core :: ptr :: addr_of_mut ! ((* this) . storage) as * mut u8) . offset (byte_index as isize) } ; unsafe { * byte = Self :: change_bit (* byte , index , val) } ; } # [inline] pub fn get (& self , bit_offset : usize , bit_width : u8) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if self . get_bit (i + bit_offset) { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub unsafe fn raw_get (this : * const Self , bit_offset : usize , bit_width : u8 ,) -> u64 { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; let mut val = 0 ; for i in 0 .. (bit_width as usize) { if unsafe { Self :: raw_get_bit (this , i + bit_offset) } { let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; val |= 1 << index ; } } val } # [inline] pub fn set (& mut self , bit_offset : usize , bit_width : u8 , val : u64) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < self . storage . as_ref () . len ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= self . storage . as_ref () . len ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; self . set_bit (index + bit_offset , val_bit_is_set) ; } } # [inline] pub unsafe fn raw_set (this : * mut Self , bit_offset : usize , bit_width : u8 , val : u64 ,) { debug_assert ! (bit_width <= 64) ; debug_assert ! (bit_offset / 8 < core :: mem :: size_of ::< Storage > ()) ; debug_assert ! ((bit_offset + (bit_width as usize)) / 8 <= core :: mem :: size_of ::< Storage > ()) ; for i in 0 .. (bit_width as usize) { let mask = 1 << i ; let val_bit_is_set = val & mask == mask ; let index = if cfg ! (target_endian = "big") { bit_width as usize - 1 - i } else { i } ; unsafe { Self :: raw_set_bit (this , index + bit_offset , val_bit_is_set) } ; } } } # [derive (PartialEq , Copy , Clone , Hash , Debug , Default)] # [repr (C)] pub struct __BindgenComplex < T > { pub re : T , pub im : T } pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __GLIBC_USE_ISOC2Y : u32 = 0 ; pub const __GLIBC_USE_ISOC23 : u32 = 0 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 202405 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_XOPEN2K24 : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const __TIMESIZE : u32 = 64 ; pub const __USE_TIME_BITS64 : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_GETS : u32 = 0 ; pub const __GLIBC_USE_DEPRECATED_SCANF : u32 = 0 ; pub const __GLIBC_USE_C23_STRTOL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_60559_BFP__ : u32 = 201404 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_IEC_60559_COMPLEX__ : u32 = 201404 ; pub const __STDC_ISO_10646__ : u32 = 201706 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 43 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __glibc_c99_flexarr_available : u32 = 1 ; pub const __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI : u32 = 0 ; pub const __HAVE_GENERIC_SELECTION : u32 = 1 ; pub const __GLIBC_USE_LIB_EXT2 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_BFP_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_FUNCS_EXT_C23 : u32 = 0 ; pub const __GLIBC_USE_IEC_60559_TYPES_EXT : u32 = 0 ; pub const _STDLIB_H : u32 = 1 ; pub const WNOHANG : u32 = 1 ; pub const WUNTRACED : u32 = 2 ; pub const WSTOPPED : u32 = 2 ; pub const WEXITED : u32 = 4 ; pub const WCONTINUED : u32 = 8 ; pub const WNOWAIT : u32 = 16777216 ; pub const __WNOTHREAD : u32 = 536870912 ; pub const __WALL : u32 = 1073741824 ; pub const __WCLONE : u32 = 2147483648 ; pub const __W_CONTINUED : u32 = 65535 ; pub const __WCOREFLAG : u32 = 128 ; pub const __HAVE_FLOAT128 : u32 = 1 ; pub const __HAVE_DISTINCT_FLOAT128 : u32 = 1 ; pub const __HAVE_FLOAT64X : u32 = 1 ; pub const __HAVE_FLOAT64X_LONG_DOUBLE : u32 = 1 ; pub const __HAVE_FLOAT16 : u32 = 0 ; pub const __HAVE_FLOAT32 : u32 = 1 ; pub const __HAVE_FLOAT64 : u32 = 1 ; pub const __HAVE_FLOAT32X : u32 = 1 ; pub const __HAVE_FLOAT128X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT16 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64 : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT32X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT64X : u32 = 0 ; pub const __HAVE_DISTINCT_FLOAT128X : u32 = 0 ; pub const __HAVE_FLOATN_NOT_TYPEDEF : u32 = 0 ; pub const __ldiv_t_defined : u32 = 1 ; pub const __lldiv_t_defined : u32 = 1 ; pub const RAND_MAX : u32 = 2147483647 ; pub const EXIT_FAILURE : u32 = 1 ; pub const EXIT_SUCCESS : u32 = 0 ; pub const _SYS_TYPES_H : u32 = 1 ; pub const _BITS_TYPES_H : u32 = 1 ; pub const _BITS_TYPESIZES_H : u32 = 1 ; pub const __OFF_T_MATCHES_OFF64_T : u32 = 1 ; pub const __INO_T_MATCHES_INO64_T : u32 = 1 ; pub const __RLIM_T_MATCHES_RLIM64_T : u32 = 1 ; pub const __STATFS_MATCHES_STATFS64 : u32 = 1 ; pub const __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 : u32 = 1 ; pub const __FD_SETSIZE : u32 = 1024 ; pub const _BITS_TIME64_H : u32 = 1 ; pub const __clock_t_defined : u32 = 1 ; pub const __clockid_t_defined : u32 = 1 ; pub const __time_t_defined : u32 = 1 ; pub const __timer_t_defined : u32 = 1 ; pub const _BITS_STDINT_INTN_H : u32 = 1 ; pub const __BIT_TYPES_DEFINED__ : u32 = 1 ; pub const _ENDIAN_H : u32 = 1 ; pub const _BITS_ENDIAN_H : u32 = 1 ; pub const __LITTLE_ENDIAN : u32 = 1234 ; pub const __BIG_ENDIAN : u32 = 4321 ; pub const __PDP_ENDIAN : u32 = 3412 ; pub const _BITS_ENDIANNESS_H : u32 = 1 ; pub const __BYTE_ORDER : u32 = 1234 ; pub const __FLOAT_WORD_ORDER : u32 = 1234 ; pub const LITTLE_ENDIAN : u32 = 1234 ; pub const BIG_ENDIAN : u32 = 4321 ; pub const PDP_ENDIAN : u32 = 3412 ; pub const BYTE_ORDER : u32 = 1234 ; pub const _BITS_BYTESWAP_H : u32 = 1 ; pub const _BITS_UINTN_IDENTITY_H : u32 = 1 ; pub const _SYS_SELECT_H : u32 = 1 ; pub const __sigset_t_defined : u32 = 1 ; pub const __timeval_defined : u32 = 1 ; pub const _STRUCT_TIMESPEC : u32 = 1 ; pub const FD_SETSIZE : u32 = 1024 ; pub const _BITS_PTHREADTYPES_COMMON_H : u32 = 1 ; pub const _THREAD_SHARED_TYPES_H : u32 = 1 ; pub const _BITS_PTHREADTYPES_ARCH_H : u32 = 1 ; pub const __SIZEOF_PTHREAD_MUTEX_T : u32 = 40 ; pub const __SIZEOF_PTHREAD_ATTR_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_RWLOCK_T : u32 = 56 ; pub const __SIZEOF_PTHREAD_BARRIER_T : u32 = 32 ; pub const __SIZEOF_PTHREAD_MUTEXATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_COND_T : u32 = 48 ; pub const __SIZEOF_PTHREAD_CONDATTR_T : u32 = 4 ; pub const __SIZEOF_PTHREAD_RWLOCKATTR_T : u32 = 8 ; pub const __SIZEOF_PTHREAD_BARRIERATTR_T : u32 = 4 ; pub const _THREAD_MUTEX_INTERNAL_H : u32 = 1 ; pub const __PTHREAD_MUTEX_HAVE_PREV : u32 = 1 ; pub const __have_pthread_attr_t : u32 = 1 ; pub const _ALLOCA_H : u32 = 1 ; pub const _STDIO_H : u32 = 1 ; pub const _____fpos_t_defined : u32 = 1 ; pub const ____mbstate_t_defined : u32 = 1 ; pub const _____fpos64_t_defined : u32 = 1 ; pub const ____FILE_defined : u32 = 1 ; pub const __FILE_defined : u32 = 1 ; pub const __struct_FILE_defined : u32 = 1 ; pub const _IO_EOF_SEEN : u32 = 16 ; pub const _IO_ERR_SEEN : u32 = 32 ; pub const _IO_USER_LOCK : u32 = 32768 ; pub const __cookie_io_functions_t_defined : u32 = 1 ; pub const _IOFBF : u32 = 0 ; pub const _IOLBF : u32 = 1 ; pub const _IONBF : u32 = 2 ; pub const BUFSIZ : u32 = 8192 ; pub const EOF : i32 = - 1 ; pub const SEEK_SET : u32 = 0 ; pub const SEEK_CUR : u32 = 1 ; pub const SEEK_END : u32 = 2 ; pub const P_tmpdir : & [u8 ; 5] = b"/tmp\0" ; pub const L_tmpnam : u32 = 20 ; pub const TMP_MAX : u32 = 238328 ; pub const _BITS_STDIO_LIM_H : u32 = 1 ; pub const FILENAME_MAX : u32 = 4096 ; pub const L_ctermid : u32 = 9 ; pub const FOPEN_MAX : u32 = 16 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const _INTTYPES_H : u32 = 1 ; pub const _STDINT_H : u32 = 1 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const _BITS_STDINT_UINTN_H : u32 = 1 ; pub const _BITS_STDINT_LEAST_H : u32 = 1 ; pub const INT8_MIN : i32 = - 128 ; pub const INT16_MIN : i32 = - 32768 ; pub const INT32_MIN : i32 = - 2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = - 128 ; pub const INT_LEAST16_MIN : i32 = - 32768 ; pub const INT_LEAST32_MIN : i32 = - 2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = - 128 ; pub const INT_FAST16_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST32_MIN : i64 = - 9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = - 1 ; pub const UINT_FAST32_MAX : i32 = - 1 ; pub const INTPTR_MIN : i64 = - 9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = - 1 ; pub const PTRDIFF_MIN : i64 = - 9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = - 2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = - 1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const ____gwchar_t_defined : u32 = 1 ; pub const __PRI64_PREFIX : & [u8 ; 2] = b"l\0" ; pub const __PRIPTR_PREFIX : & [u8 ; 2] = b"l\0" ; pub const PRId8 : & [u8 ; 4] = b"hhd\0" ; pub const PRId16 : & [u8 ; 3] = b"hd\0" ; pub const PRId32 : & [u8 ; 2] = b"d\0" ; pub const PRId64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const PRIdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const PRIdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const PRIdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const PRIdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const PRIi8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIi16 : & [u8 ; 3] = b"hi\0" ; pub const PRIi32 : & [u8 ; 2] = b"i\0" ; pub const PRIi64 : & [u8 ; 3] = b"li\0" ; pub const PRIiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const PRIiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const PRIiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const PRIiFAST16 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST32 : & [u8 ; 3] = b"li\0" ; pub const PRIiFAST64 : & [u8 ; 3] = b"li\0" ; pub const PRIo8 : & [u8 ; 4] = b"hho\0" ; pub const PRIo16 : & [u8 ; 3] = b"ho\0" ; pub const PRIo32 : & [u8 ; 2] = b"o\0" ; pub const PRIo64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const PRIoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const PRIoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const PRIoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const PRIoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const PRIu8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIu16 : & [u8 ; 3] = b"hu\0" ; pub const PRIu32 : & [u8 ; 2] = b"u\0" ; pub const PRIu64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const PRIuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const PRIuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const PRIuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const PRIuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const PRIx8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIx16 : & [u8 ; 3] = b"hx\0" ; pub const PRIx32 : & [u8 ; 2] = b"x\0" ; pub const PRIx64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const PRIxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const PRIxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const PRIxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const PRIxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const PRIX8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIX16 : & [u8 ; 3] = b"hX\0" ; pub const PRIX32 : & [u8 ; 2] = b"X\0" ; pub const PRIX64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXLEAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXLEAST16 : & [u8 ; 3] = b"hX\0" ; pub const PRIXLEAST32 : & [u8 ; 2] = b"X\0" ; pub const PRIXLEAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST8 : & [u8 ; 4] = b"hhX\0" ; pub const PRIXFAST16 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST32 : & [u8 ; 3] = b"lX\0" ; pub const PRIXFAST64 : & [u8 ; 3] = b"lX\0" ; pub const PRIdMAX : & [u8 ; 3] = b"ld\0" ; pub const PRIiMAX : & [u8 ; 3] = b"li\0" ; pub const PRIoMAX : & [u8 ; 3] = b"lo\0" ; pub const PRIuMAX : & [u8 ; 3] = b"lu\0" ; pub const PRIxMAX : & [u8 ; 3] = b"lx\0" ; pub const PRIXMAX : & [u8 ; 3] = b"lX\0" ; pub const PRIdPTR : & [u8 ; 3] = b"ld\0" ; pub const PRIiPTR : & [u8 ; 3] = b"li\0" ; pub const PRIoPTR : & [u8 ; 3] = b"lo\0" ; pub const PRIuPTR : & [u8 ; 3] = b"lu\0" ; pub const PRIxPTR : & [u8 ; 3] = b"lx\0" ; pub const PRIXPTR : & [u8 ; 3] = b"lX\0" ; pub const SCNd8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNd16 : & [u8 ; 3] = b"hd\0" ; pub const SCNd32 : & [u8 ; 2] = b"d\0" ; pub const SCNd64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdLEAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdLEAST16 : & [u8 ; 3] = b"hd\0" ; pub const SCNdLEAST32 : & [u8 ; 2] = b"d\0" ; pub const SCNdLEAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST8 : & [u8 ; 4] = b"hhd\0" ; pub const SCNdFAST16 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST32 : & [u8 ; 3] = b"ld\0" ; pub const SCNdFAST64 : & [u8 ; 3] = b"ld\0" ; pub const SCNi8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNi16 : & [u8 ; 3] = b"hi\0" ; pub const SCNi32 : & [u8 ; 2] = b"i\0" ; pub const SCNi64 : & [u8 ; 3] = b"li\0" ; pub const SCNiLEAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiLEAST16 : & [u8 ; 3] = b"hi\0" ; pub const SCNiLEAST32 : & [u8 ; 2] = b"i\0" ; pub const SCNiLEAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST8 : & [u8 ; 4] = b"hhi\0" ; pub const SCNiFAST16 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST32 : & [u8 ; 3] = b"li\0" ; pub const SCNiFAST64 : & [u8 ; 3] = b"li\0" ; pub const SCNu8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNu16 : & [u8 ; 3] = b"hu\0" ; pub const SCNu32 : & [u8 ; 2] = b"u\0" ; pub const SCNu64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuLEAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuLEAST16 : & [u8 ; 3] = b"hu\0" ; pub const SCNuLEAST32 : & [u8 ; 2] = b"u\0" ; pub const SCNuLEAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST8 : & [u8 ; 4] = b"hhu\0" ; pub const SCNuFAST16 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST32 : & [u8 ; 3] = b"lu\0" ; pub const SCNuFAST64 : & [u8 ; 3] = b"lu\0" ; pub const SCNo8 : & [u8 ; 4] = b"hho\0" ; pub const SCNo16 : & [u8 ; 3] = b"ho\0" ; pub const SCNo32 : & [u8 ; 2] = b"o\0" ; pub const SCNo64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoLEAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoLEAST16 : & [u8 ; 3] = b"ho\0" ; pub const SCNoLEAST32 : & [u8 ; 2] = b"o\0" ; pub const SCNoLEAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST8 : & [u8 ; 4] = b"hho\0" ; pub const SCNoFAST16 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST32 : & [u8 ; 3] = b"lo\0" ; pub const SCNoFAST64 : & [u8 ; 3] = b"lo\0" ; pub const SCNx8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNx16 : & [u8 ; 3] = b"hx\0" ; pub const SCNx32 : & [u8 ; 2] = b"x\0" ; pub const SCNx64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxLEAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxLEAST16 : & [u8 ; 3] = b"hx\0" ; pub const SCNxLEAST32 : & [u8 ; 2] = b"x\0" ; pub const SCNxLEAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST8 : & [u8 ; 4] = b"hhx\0" ; pub const SCNxFAST16 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST32 : & [u8 ; 3] = b"lx\0" ; pub const SCNxFAST64 : & [u8 ; 3] = b"lx\0" ; pub const SCNdMAX : & [u8 ; 3] = b"ld\0" ; pub const SCNiMAX : & [u8 ; 3] = b"li\0" ; pub const SCNoMAX : & [u8 ; 3] = b"lo\0" ; pub const SCNuMAX : & [u8 ; 3] = b"lu\0" ; pub const SCNxMAX : & [u8 ; 3] = b"lx\0" ; pub const SCNdPTR : & [u8 ; 3] = b"ld\0" ; pub const SCNiPTR : & [u8 ; 3] = b"li\0" ; pub const SCNoPTR : & [u8 ; 3] = b"lo\0" ; pub const SCNuPTR : & [u8 ; 3] = b"lu\0" ; pub const SCNxPTR : & [u8 ; 3] = b"lx\0" ; pub const CS_API_MAJOR : u32 = 5 ; pub const CS_API_MINOR : u32 = 0 ; pub const CS_NEXT_VERSION : u32 = 5 ; pub const CS_VERSION_MAJOR : u32 = 5 ; pub const CS_VERSION_MINOR : u32 = 0 ; pub const CS_VERSION_EXTRA : u32 = 7 ; pub const CS_MNEMONIC_SIZE : u32 = 32 ; pub const M68K_OPERAND_COUNT : u32 = 4 ; pub const X86_EFLAGS_MODIFY_AF : u32 = 1 ; pub const X86_EFLAGS_MODIFY_CF : u32 = 2 ; pub const X86_EFLAGS_MODIFY_SF : u32 = 4 ; pub const X86_EFLAGS_MODIFY_ZF : u32 = 8 ; pub const X86_EFLAGS_MODIFY_PF : u32 = 16 ; pub const X86_EFLAGS_MODIFY_OF : u32 = 32 ; pub const X86_EFLAGS_MODIFY_TF : u32 = 64 ; pub const X86_EFLAGS_MODIFY_IF : u32 = 128 ; pub const X86_EFLAGS_MODIFY_DF : u32 = 256 ; pub const X86_EFLAGS_MODIFY_NT : u32 = 512 ; pub const X86_EFLAGS_MODIFY_RF : u32 = 1024 ; pub const X86_EFLAGS_PRIOR_OF : u32 = 2048 ; pub const X86_EFLAGS_PRIOR_SF : u32 = 4096 ; pub const X86_EFLAGS_PRIOR_ZF : u32 = 8192 ; pub const X86_EFLAGS_PRIOR_AF : u32 = 16384 ; pub const X86_EFLAGS_PRIOR_PF : u32 = 32768 ; pub const X86_EFLAGS_PRIOR_CF : u32 = 65536 ; pub const X86_EFLAGS_PRIOR_TF : u32 = 131072 ; pub const X86_EFLAGS_PRIOR_IF : u32 = 262144 ; pub const X86_EFLAGS_PRIOR_DF : u32 = 524288 ; pub const X86_EFLAGS_PRIOR_NT : u32 = 1048576 ; pub const X86_EFLAGS_RESET_OF : u32 = 2097152 ; pub const X86_EFLAGS_RESET_CF : u32 = 4194304 ; pub const X86_EFLAGS_RESET_DF : u32 = 8388608 ; pub const X86_EFLAGS_RESET_IF : u32 = 16777216 ; pub const X86_EFLAGS_RESET_SF : u32 = 33554432 ; pub const X86_EFLAGS_RESET_AF : u32 = 67108864 ; pub const X86_EFLAGS_RESET_TF : u32 = 134217728 ; pub const X86_EFLAGS_RESET_NT : u32 = 268435456 ; pub const X86_EFLAGS_RESET_PF : u32 = 536870912 ; pub const X86_EFLAGS_SET_CF : u32 = 1073741824 ; pub const X86_EFLAGS_SET_DF : u32 = 2147483648 ; pub const X86_EFLAGS_SET_IF : u64 = 4294967296 ; pub const X86_EFLAGS_TEST_OF : u64 = 8589934592 ; pub const X86_EFLAGS_TEST_SF : u64 = 17179869184 ; pub const X86_EFLAGS_TEST_ZF : u64 = 34359738368 ; pub const X86_EFLAGS_TEST_PF : u64 = 68719476736 ; pub const X86_EFLAGS_TEST_CF : u64 = 137438953472 ; pub const X86_EFLAGS_TEST_NT : u64 = 274877906944 ; pub const X86_EFLAGS_TEST_DF : u64 = 549755813888 ; pub const X86_EFLAGS_UNDEFINED_OF : u64 = 1099511627776 ; pub const X86_EFLAGS_UNDEFINED_SF : u64 = 2199023255552 ; pub const X86_EFLAGS_UNDEFINED_ZF : u64 = 4398046511104 ; pub const X86_EFLAGS_UNDEFINED_PF : u64 = 8796093022208 ; pub const X86_EFLAGS_UNDEFINED_AF : u64 = 17592186044416 ; pub const X86_EFLAGS_UNDEFINED_CF : u64 = 35184372088832 ; pub const X86_EFLAGS_RESET_RF : u64 = 70368744177664 ; pub const X86_EFLAGS_TEST_RF : u64 = 140737488355328 ; pub const X86_EFLAGS_TEST_IF : u64 = 281474976710656 ; pub const X86_EFLAGS_TEST_TF : u64 = 562949953421312 ; pub const X86_EFLAGS_TEST_AF : u64 = 1125899906842624 ; pub const X86_EFLAGS_RESET_ZF : u64 = 2251799813685248 ; pub const X86_EFLAGS_SET_OF : u64 = 4503599627370496 ; pub const X86_EFLAGS_SET_SF : u64 = 9007199254740992 ; pub const X86_EFLAGS_SET_ZF : u64 = 18014398509481984 ; pub const X86_EFLAGS_SET_AF : u64 = 36028797018963968 ; pub const X86_EFLAGS_SET_PF : u64 = 72057594037927936 ; pub const X86_EFLAGS_RESET_0F : u64 = 144115188075855872 ; pub const X86_EFLAGS_RESET_AC : u64 = 288230376151711744 ; pub const X86_FPU_FLAGS_MODIFY_C0 : u32 = 1 ; pub const X86_FPU_FLAGS_MODIFY_C1 : u32 = 2 ; pub const X86_FPU_FLAGS_MODIFY_C2 : u32 = 4 ; pub const X86_FPU_FLAGS_MODIFY_C3 : u32 = 8 ; pub const X86_FPU_FLAGS_RESET_C0 : u32 = 16 ; pub const X86_FPU_FLAGS_RESET_C1 : u32 = 32 ; pub const X86_FPU_FLAGS_RESET_C2 : u32 = 64 ; pub const X86_FPU_FLAGS_RESET_C3 : u32 = 128 ; pub const X86_FPU_FLAGS_SET_C0 : u32 = 256 ; pub const X86_FPU_FLAGS_SET_C1 : u32 = 512 ; pub const X86_FPU_FLAGS_SET_C2 : u32 = 1024 ; pub const X86_FPU_FLAGS_SET_C3 : u32 = 2048 ; pub const X86_FPU_FLAGS_UNDEFINED_C0 : u32 = 4096 ; pub const X86_FPU_FLAGS_UNDEFINED_C1 : u32 = 8192 ; pub const X86_FPU_FLAGS_UNDEFINED_C2 : u32 = 16384 ; pub const X86_FPU_FLAGS_UNDEFINED_C3 : u32 = 32768 ; pub const X86_FPU_FLAGS_TEST_C0 : u32 = 65536 ; pub const X86_FPU_FLAGS_TEST_C1 : u32 = 131072 ; pub const X86_FPU_FLAGS_TEST_C2 : u32 = 262144 ; pub const X86_FPU_FLAGS_TEST_C3 : u32 = 524288 ; pub const M680X_OPERAND_COUNT : u32 = 9 ; pub const M680X_OFFSET_NONE : u32 = 0 ; pub const M680X_OFFSET_BITS_5 : u32 = 5 ; pub const M680X_OFFSET_BITS_8 : u32 = 8 ; pub const M680X_OFFSET_BITS_9 : u32 = 9 ; pub const M680X_OFFSET_BITS_16 : u32 = 16 ; pub const M680X_IDX_INDIRECT : u32 = 1 ; pub const M680X_IDX_NO_COMMA : u32 = 2 ; pub const M680X_IDX_POST_INC_DEC : u32 = 4 ; pub const M680X_FIRST_OP_IN_MNEM : u32 = 1 ; pub const M680X_SECOND_OP_IN_MNEM : u32 = 2 ; pub const TRICORE_OP_COUNT : u32 = 8 ; pub const MAX_IMPL_W_REGS : u32 = 20 ; pub const MAX_IMPL_R_REGS : u32 = 20 ; pub const MAX_NUM_GROUPS : u32 = 8 ; pub type __gnuc_va_list = __builtin_va_list ; pub type va_list = __builtin_va_list ; pub type wchar_t = :: std :: os :: raw :: c_int ; pub type __cfloat128 = __BindgenComplex < u128 > ; pub type _Float128 = u128 ; pub type _Float32 = f32 ; pub type _Float64 = f64 ; pub type _Float32x = f64 ; pub type _Float64x = u128 ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct div_t { pub quot : :: std :: os :: raw :: c_int , pub rem : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of div_t"] [:: std :: mem :: size_of :: < div_t > () - 8usize] ; ["Alignment of div_t"] [:: std :: mem :: align_of :: < div_t > () - 4usize] ; ["Offset of field: div_t::quot"] [:: std :: mem :: offset_of ! (div_t , quot) - 0usize] ; ["Offset of field: div_t::rem"] [:: std :: mem :: offset_of ! (div_t , rem) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ldiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ldiv_t"] [:: std :: mem :: size_of :: < ldiv_t > () - 16usize] ; ["Alignment of ldiv_t"] [:: std :: mem :: align_of :: < ldiv_t > () - 8usize] ; ["Offset of field: ldiv_t::quot"] [:: std :: mem :: offset_of ! (ldiv_t , quot) - 0usize] ; ["Offset of field: ldiv_t::rem"] [:: std :: mem :: offset_of ! (ldiv_t , rem) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct lldiv_t { pub quot : :: std :: os :: raw :: c_longlong , pub rem : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of lldiv_t"] [:: std :: mem :: size_of :: < lldiv_t > () - 16usize] ; ["Alignment of lldiv_t"] [:: std :: mem :: align_of :: < lldiv_t > () - 8usize] ; ["Offset of field: lldiv_t::quot"] [:: std :: mem :: offset_of ! (lldiv_t , quot) - 0usize] ; ["Offset of field: lldiv_t::rem"] [:: std :: mem :: offset_of ! (lldiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn __ctype_get_mb_cur_max () -> usize ; } unsafe extern "C" { pub fn atof (__nptr : * const :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn atoi (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn atol (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn atoll (__nptr : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtod (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f64 ; } unsafe extern "C" { pub fn strtof (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> f32 ; } unsafe extern "C" { pub fn strtold (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char) -> u128 ; } unsafe extern "C" { pub fn strtol (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn strtoul (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn strtoq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtouq (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn strtoll (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn strtoull (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_ulonglong ; } unsafe extern "C" { pub fn l64a (__n : :: std :: os :: raw :: c_long) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn a64l (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_long ; } pub type __u_char = :: std :: os :: raw :: c_uchar ; pub type __u_short = :: std :: os :: raw :: c_ushort ; pub type __u_int = :: std :: os :: raw :: c_uint ; pub type __u_long = :: std :: os :: raw :: c_ulong ; pub type __int8_t = :: std :: os :: raw :: c_schar ; pub type __uint8_t = :: std :: os :: raw :: c_uchar ; pub type __int16_t = :: std :: os :: raw :: c_short ; pub type __uint16_t = :: std :: os :: raw :: c_ushort ; pub type __int32_t = :: std :: os :: raw :: c_int ; pub type __uint32_t = :: std :: os :: raw :: c_uint ; pub type __int64_t = :: std :: os :: raw :: c_long ; pub type __uint64_t = :: std :: os :: raw :: c_ulong ; pub type __int_least8_t = __int8_t ; pub type __uint_least8_t = __uint8_t ; pub type __int_least16_t = __int16_t ; pub type __uint_least16_t = __uint16_t ; pub type __int_least32_t = __int32_t ; pub type __uint_least32_t = __uint32_t ; pub type __int_least64_t = __int64_t ; pub type __uint_least64_t = __uint64_t ; pub type __quad_t = :: std :: os :: raw :: c_long ; pub type __u_quad_t = :: std :: os :: raw :: c_ulong ; pub type __intmax_t = :: std :: os :: raw :: c_long ; pub type __uintmax_t = :: std :: os :: raw :: c_ulong ; pub type __dev_t = :: std :: os :: raw :: c_ulong ; pub type __uid_t = :: std :: os :: raw :: c_uint ; pub type __gid_t = :: std :: os :: raw :: c_uint ; pub type __ino_t = :: std :: os :: raw :: c_ulong ; pub type __ino64_t = :: std :: os :: raw :: c_ulong ; pub type __mode_t = :: std :: os :: raw :: c_uint ; pub type __nlink_t = :: std :: os :: raw :: c_ulong ; pub type __off_t = :: std :: os :: raw :: c_long ; pub type __off64_t = :: std :: os :: raw :: c_long ; pub type __pid_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __fsid_t { pub __val : [:: std :: os :: raw :: c_int ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __fsid_t"] [:: std :: mem :: size_of :: < __fsid_t > () - 8usize] ; ["Alignment of __fsid_t"] [:: std :: mem :: align_of :: < __fsid_t > () - 4usize] ; ["Offset of field: __fsid_t::__val"] [:: std :: mem :: offset_of ! (__fsid_t , __val) - 0usize] ; } ; pub type __clock_t = :: std :: os :: raw :: c_long ; pub type __rlim_t = :: std :: os :: raw :: c_ulong ; pub type __rlim64_t = :: std :: os :: raw :: c_ulong ; pub type __id_t = :: std :: os :: raw :: c_uint ; pub type __time_t = :: std :: os :: raw :: c_long ; pub type __useconds_t = :: std :: os :: raw :: c_uint ; pub type __suseconds_t = :: std :: os :: raw :: c_long ; pub type __suseconds64_t = :: std :: os :: raw :: c_long ; pub type __daddr_t = :: std :: os :: raw :: c_int ; pub type __key_t = :: std :: os :: raw :: c_int ; pub type __clockid_t = :: std :: os :: raw :: c_int ; pub type __timer_t = * mut :: std :: os :: raw :: c_void ; pub type __blksize_t = :: std :: os :: raw :: c_long ; pub type __blkcnt_t = :: std :: os :: raw :: c_long ; pub type __blkcnt64_t = :: std :: os :: raw :: c_long ; pub type __fsblkcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsblkcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt_t = :: std :: os :: raw :: c_ulong ; pub type __fsfilcnt64_t = :: std :: os :: raw :: c_ulong ; pub type __fsword_t = :: std :: os :: raw :: c_long ; pub type __ssize_t = :: std :: os :: raw :: c_long ; pub type __syscall_slong_t = :: std :: os :: raw :: c_long ; pub type __syscall_ulong_t = :: std :: os :: raw :: c_ulong ; pub type __loff_t = __off64_t ; pub type __caddr_t = * mut :: std :: os :: raw :: c_char ; pub type __intptr_t = :: std :: os :: raw :: c_long ; pub type __socklen_t = :: std :: os :: raw :: c_uint ; pub type __sig_atomic_t = :: std :: os :: raw :: c_int ; pub type u_char = __u_char ; pub type u_short = __u_short ; pub type u_int = __u_int ; pub type u_long = __u_long ; pub type quad_t = __quad_t ; pub type u_quad_t = __u_quad_t ; pub type fsid_t = __fsid_t ; pub type loff_t = __loff_t ; pub type ino_t = __ino_t ; pub type dev_t = __dev_t ; pub type gid_t = __gid_t ; pub type mode_t = __mode_t ; pub type nlink_t = __nlink_t ; pub type uid_t = __uid_t ; pub type off_t = __off_t ; pub type pid_t = __pid_t ; pub type id_t = __id_t ; pub type daddr_t = __daddr_t ; pub type caddr_t = __caddr_t ; pub type key_t = __key_t ; pub type clock_t = __clock_t ; pub type clockid_t = __clockid_t ; pub type time_t = __time_t ; pub type timer_t = __timer_t ; pub type ulong = :: std :: os :: raw :: c_ulong ; pub type ushort = :: std :: os :: raw :: c_ushort ; pub type uint = :: std :: os :: raw :: c_uint ; pub type u_int8_t = __uint8_t ; pub type u_int16_t = __uint16_t ; pub type u_int32_t = __uint32_t ; pub type u_int64_t = __uint64_t ; pub type register_t = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __sigset_t { pub __val : [:: std :: os :: raw :: c_ulong ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __sigset_t"] [:: std :: mem :: size_of :: < __sigset_t > () - 128usize] ; ["Alignment of __sigset_t"] [:: std :: mem :: align_of :: < __sigset_t > () - 8usize] ; ["Offset of field: __sigset_t::__val"] [:: std :: mem :: offset_of ! (__sigset_t , __val) - 0usize] ; } ; pub type sigset_t = __sigset_t ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timeval { pub tv_sec : __time_t , pub tv_usec : __suseconds_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timeval"] [:: std :: mem :: size_of :: < timeval > () - 16usize] ; ["Alignment of timeval"] [:: std :: mem :: align_of :: < timeval > () - 8usize] ; ["Offset of field: timeval::tv_sec"] [:: std :: mem :: offset_of ! (timeval , tv_sec) - 0usize] ; ["Offset of field: timeval::tv_usec"] [:: std :: mem :: offset_of ! (timeval , tv_usec) - 8usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct timespec { pub tv_sec : __time_t , pub tv_nsec : __syscall_slong_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of timespec"] [:: std :: mem :: size_of :: < timespec > () - 16usize] ; ["Alignment of timespec"] [:: std :: mem :: align_of :: < timespec > () - 8usize] ; ["Offset of field: timespec::tv_sec"] [:: std :: mem :: offset_of ! (timespec , tv_sec) - 0usize] ; ["Offset of field: timespec::tv_nsec"] [:: std :: mem :: offset_of ! (timespec , tv_nsec) - 8usize] ; } ; pub type suseconds_t = __suseconds_t ; pub type __fd_mask = :: std :: os :: raw :: c_long ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct fd_set { pub __fds_bits : [__fd_mask ; 16usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of fd_set"] [:: std :: mem :: size_of :: < fd_set > () - 128usize] ; ["Alignment of fd_set"] [:: std :: mem :: align_of :: < fd_set > () - 8usize] ; ["Offset of field: fd_set::__fds_bits"] [:: std :: mem :: offset_of ! (fd_set , __fds_bits) - 0usize] ; } ; pub type fd_mask = __fd_mask ; unsafe extern "C" { pub fn select (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * mut timeval) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pselect (__nfds : :: std :: os :: raw :: c_int , __readfds : * mut fd_set , __writefds : * mut fd_set , __exceptfds : * mut fd_set , __timeout : * const timespec , __sigmask : * const __sigset_t) -> :: std :: os :: raw :: c_int ; } pub type blksize_t = __blksize_t ; pub type blkcnt_t = __blkcnt_t ; pub type fsblkcnt_t = __fsblkcnt_t ; pub type fsfilcnt_t = __fsfilcnt_t ; # [repr (C)] # [derive (Copy , Clone)] pub union __atomic_wide_counter { pub __value64 : :: std :: os :: raw :: c_ulonglong , pub __value32 : __atomic_wide_counter__bindgen_ty_1 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __atomic_wide_counter__bindgen_ty_1 { pub __low : :: std :: os :: raw :: c_uint , pub __high : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: size_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 8usize] ; ["Alignment of __atomic_wide_counter__bindgen_ty_1"] [:: std :: mem :: align_of :: < __atomic_wide_counter__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__low"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __low) - 0usize] ; ["Offset of field: __atomic_wide_counter__bindgen_ty_1::__high"] [:: std :: mem :: offset_of ! (__atomic_wide_counter__bindgen_ty_1 , __high) - 4usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __atomic_wide_counter"] [:: std :: mem :: size_of :: < __atomic_wide_counter > () - 8usize] ; ["Alignment of __atomic_wide_counter"] [:: std :: mem :: align_of :: < __atomic_wide_counter > () - 8usize] ; ["Offset of field: __atomic_wide_counter::__value64"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value64) - 0usize] ; ["Offset of field: __atomic_wide_counter::__value32"] [:: std :: mem :: offset_of ! (__atomic_wide_counter , __value32) - 0usize] ; } ; impl :: std :: fmt :: Debug for __atomic_wide_counter { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__atomic_wide_counter {{ union }}") } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_list { pub __prev : * mut __pthread_internal_list , pub __next : * mut __pthread_internal_list , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_list"] [:: std :: mem :: size_of :: < __pthread_internal_list > () - 16usize] ; ["Alignment of __pthread_internal_list"] [:: std :: mem :: align_of :: < __pthread_internal_list > () - 8usize] ; ["Offset of field: __pthread_internal_list::__prev"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __prev) - 0usize] ; ["Offset of field: __pthread_internal_list::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_list , __next) - 8usize] ; } ; pub type __pthread_list_t = __pthread_internal_list ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_internal_slist { pub __next : * mut __pthread_internal_slist , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_internal_slist"] [:: std :: mem :: size_of :: < __pthread_internal_slist > () - 8usize] ; ["Alignment of __pthread_internal_slist"] [:: std :: mem :: align_of :: < __pthread_internal_slist > () - 8usize] ; ["Offset of field: __pthread_internal_slist::__next"] [:: std :: mem :: offset_of ! (__pthread_internal_slist , __next) - 0usize] ; } ; pub type __pthread_slist_t = __pthread_internal_slist ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_mutex_s { pub __lock : :: std :: os :: raw :: c_int , pub __count : :: std :: os :: raw :: c_uint , pub __owner : :: std :: os :: raw :: c_int , pub __nusers : :: std :: os :: raw :: c_uint , pub __kind : :: std :: os :: raw :: c_int , pub __spins : :: std :: os :: raw :: c_short , pub __unused : :: std :: os :: raw :: c_short , pub __list : __pthread_list_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_mutex_s"] [:: std :: mem :: size_of :: < __pthread_mutex_s > () - 40usize] ; ["Alignment of __pthread_mutex_s"] [:: std :: mem :: align_of :: < __pthread_mutex_s > () - 8usize] ; ["Offset of field: __pthread_mutex_s::__lock"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __lock) - 0usize] ; ["Offset of field: __pthread_mutex_s::__count"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __count) - 4usize] ; ["Offset of field: __pthread_mutex_s::__owner"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __owner) - 8usize] ; ["Offset of field: __pthread_mutex_s::__nusers"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __nusers) - 12usize] ; ["Offset of field: __pthread_mutex_s::__kind"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __kind) - 16usize] ; ["Offset of field: __pthread_mutex_s::__spins"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __spins) - 20usize] ; ["Offset of field: __pthread_mutex_s::__unused"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __unused) - 22usize] ; ["Offset of field: __pthread_mutex_s::__list"] [:: std :: mem :: offset_of ! (__pthread_mutex_s , __list) - 24usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __pthread_rwlock_arch_t { pub __readers : :: std :: os :: raw :: c_uint , pub __writers : :: std :: os :: raw :: c_uint , pub __wrphase_futex : :: std :: os :: raw :: c_uint , pub __writers_futex : :: std :: os :: raw :: c_uint , pub __pad3 : :: std :: os :: raw :: c_uint , pub __pad4 : :: std :: os :: raw :: c_uint , pub __cur_writer : :: std :: os :: raw :: c_int , pub __shared : :: std :: os :: raw :: c_int , pub __pad1 : :: std :: os :: raw :: c_ulong , pub __pad2 : :: std :: os :: raw :: c_ulong , pub __flags : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_rwlock_arch_t"] [:: std :: mem :: size_of :: < __pthread_rwlock_arch_t > () - 56usize] ; ["Alignment of __pthread_rwlock_arch_t"] [:: std :: mem :: align_of :: < __pthread_rwlock_arch_t > () - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__readers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __readers) - 0usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers) - 4usize] ; ["Offset of field: __pthread_rwlock_arch_t::__wrphase_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __wrphase_futex) - 8usize] ; ["Offset of field: __pthread_rwlock_arch_t::__writers_futex"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __writers_futex) - 12usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad3"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad3) - 16usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad4"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad4) - 20usize] ; ["Offset of field: __pthread_rwlock_arch_t::__cur_writer"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __cur_writer) - 24usize] ; ["Offset of field: __pthread_rwlock_arch_t::__shared"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __shared) - 28usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad1"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad1) - 32usize] ; ["Offset of field: __pthread_rwlock_arch_t::__pad2"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __pad2) - 40usize] ; ["Offset of field: __pthread_rwlock_arch_t::__flags"] [:: std :: mem :: offset_of ! (__pthread_rwlock_arch_t , __flags) - 48usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct __pthread_cond_s { pub __wseq : __atomic_wide_counter , pub __g1_start : __atomic_wide_counter , pub __g_size : [:: std :: os :: raw :: c_uint ; 2usize] , pub __g1_orig_size : :: std :: os :: raw :: c_uint , pub __wrefs : :: std :: os :: raw :: c_uint , pub __g_signals : [:: std :: os :: raw :: c_uint ; 2usize] , pub __unused_initialized_1 : :: std :: os :: raw :: c_uint , pub __unused_initialized_2 : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __pthread_cond_s"] [:: std :: mem :: size_of :: < __pthread_cond_s > () - 48usize] ; ["Alignment of __pthread_cond_s"] [:: std :: mem :: align_of :: < __pthread_cond_s > () - 8usize] ; ["Offset of field: __pthread_cond_s::__wseq"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wseq) - 0usize] ; ["Offset of field: __pthread_cond_s::__g1_start"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_start) - 8usize] ; ["Offset of field: __pthread_cond_s::__g_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_size) - 16usize] ; ["Offset of field: __pthread_cond_s::__g1_orig_size"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g1_orig_size) - 24usize] ; ["Offset of field: __pthread_cond_s::__wrefs"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __wrefs) - 28usize] ; ["Offset of field: __pthread_cond_s::__g_signals"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __g_signals) - 32usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_1"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_1) - 40usize] ; ["Offset of field: __pthread_cond_s::__unused_initialized_2"] [:: std :: mem :: offset_of ! (__pthread_cond_s , __unused_initialized_2) - 44usize] ; } ; impl :: std :: fmt :: Debug for __pthread_cond_s { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__pthread_cond_s {{ __wseq: {:?}, __g1_start: {:?}, __g_size: {:?}, __g1_orig_size: {:?}, __wrefs: {:?}, __g_signals: {:?}, __unused_initialized_1: {:?}, __unused_initialized_2: {:?} }}" , self . __wseq , self . __g1_start , self . __g_size , self . __g1_orig_size , self . __wrefs , self . __g_signals , self . __unused_initialized_1 , self . __unused_initialized_2) } } pub type __tss_t = :: std :: os :: raw :: c_uint ; pub type __thrd_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __once_flag { pub __data : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __once_flag"] [:: std :: mem :: size_of :: < __once_flag > () - 4usize] ; ["Alignment of __once_flag"] [:: std :: mem :: align_of :: < __once_flag > () - 4usize] ; ["Offset of field: __once_flag::__data"] [:: std :: mem :: offset_of ! (__once_flag , __data) - 0usize] ; } ; pub type pthread_t = :: std :: os :: raw :: c_ulong ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutexattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutexattr_t"] [:: std :: mem :: size_of :: < pthread_mutexattr_t > () - 4usize] ; ["Alignment of pthread_mutexattr_t"] [:: std :: mem :: align_of :: < pthread_mutexattr_t > () - 4usize] ; ["Offset of field: pthread_mutexattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __size) - 0usize] ; ["Offset of field: pthread_mutexattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutexattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutexattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutexattr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_condattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_condattr_t"] [:: std :: mem :: size_of :: < pthread_condattr_t > () - 4usize] ; ["Alignment of pthread_condattr_t"] [:: std :: mem :: align_of :: < pthread_condattr_t > () - 4usize] ; ["Offset of field: pthread_condattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __size) - 0usize] ; ["Offset of field: pthread_condattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_condattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_condattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_condattr_t {{ union }}") } } pub type pthread_key_t = :: std :: os :: raw :: c_uint ; pub type pthread_once_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_attr_t { pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_attr_t"] [:: std :: mem :: size_of :: < pthread_attr_t > () - 56usize] ; ["Alignment of pthread_attr_t"] [:: std :: mem :: align_of :: < pthread_attr_t > () - 8usize] ; ["Offset of field: pthread_attr_t::__size"] [:: std :: mem :: offset_of ! (pthread_attr_t , __size) - 0usize] ; ["Offset of field: pthread_attr_t::__align"] [:: std :: mem :: offset_of ! (pthread_attr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_attr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_attr_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_mutex_t { pub __data : __pthread_mutex_s , pub __size : [:: std :: os :: raw :: c_char ; 40usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_mutex_t"] [:: std :: mem :: size_of :: < pthread_mutex_t > () - 40usize] ; ["Alignment of pthread_mutex_t"] [:: std :: mem :: align_of :: < pthread_mutex_t > () - 8usize] ; ["Offset of field: pthread_mutex_t::__data"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __data) - 0usize] ; ["Offset of field: pthread_mutex_t::__size"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __size) - 0usize] ; ["Offset of field: pthread_mutex_t::__align"] [:: std :: mem :: offset_of ! (pthread_mutex_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_mutex_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_mutex_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_cond_t { pub __data : __pthread_cond_s , pub __size : [:: std :: os :: raw :: c_char ; 48usize] , pub __align : :: std :: os :: raw :: c_longlong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_cond_t"] [:: std :: mem :: size_of :: < pthread_cond_t > () - 48usize] ; ["Alignment of pthread_cond_t"] [:: std :: mem :: align_of :: < pthread_cond_t > () - 8usize] ; ["Offset of field: pthread_cond_t::__data"] [:: std :: mem :: offset_of ! (pthread_cond_t , __data) - 0usize] ; ["Offset of field: pthread_cond_t::__size"] [:: std :: mem :: offset_of ! (pthread_cond_t , __size) - 0usize] ; ["Offset of field: pthread_cond_t::__align"] [:: std :: mem :: offset_of ! (pthread_cond_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_cond_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_cond_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlock_t { pub __data : __pthread_rwlock_arch_t , pub __size : [:: std :: os :: raw :: c_char ; 56usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlock_t"] [:: std :: mem :: size_of :: < pthread_rwlock_t > () - 56usize] ; ["Alignment of pthread_rwlock_t"] [:: std :: mem :: align_of :: < pthread_rwlock_t > () - 8usize] ; ["Offset of field: pthread_rwlock_t::__data"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __data) - 0usize] ; ["Offset of field: pthread_rwlock_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __size) - 0usize] ; ["Offset of field: pthread_rwlock_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlock_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlock_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlock_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_rwlockattr_t { pub __size : [:: std :: os :: raw :: c_char ; 8usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_rwlockattr_t"] [:: std :: mem :: size_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Alignment of pthread_rwlockattr_t"] [:: std :: mem :: align_of :: < pthread_rwlockattr_t > () - 8usize] ; ["Offset of field: pthread_rwlockattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __size) - 0usize] ; ["Offset of field: pthread_rwlockattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_rwlockattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_rwlockattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_rwlockattr_t {{ union }}") } } pub type pthread_spinlock_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrier_t { pub __size : [:: std :: os :: raw :: c_char ; 32usize] , pub __align : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrier_t"] [:: std :: mem :: size_of :: < pthread_barrier_t > () - 32usize] ; ["Alignment of pthread_barrier_t"] [:: std :: mem :: align_of :: < pthread_barrier_t > () - 8usize] ; ["Offset of field: pthread_barrier_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __size) - 0usize] ; ["Offset of field: pthread_barrier_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrier_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrier_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrier_t {{ union }}") } } # [repr (C)] # [derive (Copy , Clone)] pub union pthread_barrierattr_t { pub __size : [:: std :: os :: raw :: c_char ; 4usize] , pub __align : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of pthread_barrierattr_t"] [:: std :: mem :: size_of :: < pthread_barrierattr_t > () - 4usize] ; ["Alignment of pthread_barrierattr_t"] [:: std :: mem :: align_of :: < pthread_barrierattr_t > () - 4usize] ; ["Offset of field: pthread_barrierattr_t::__size"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __size) - 0usize] ; ["Offset of field: pthread_barrierattr_t::__align"] [:: std :: mem :: offset_of ! (pthread_barrierattr_t , __align) - 0usize] ; } ; impl :: std :: fmt :: Debug for pthread_barrierattr_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "pthread_barrierattr_t {{ union }}") } } unsafe extern "C" { pub fn random () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srandom (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn initstate (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn setstate (__statebuf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct random_data { pub fptr : * mut i32 , pub rptr : * mut i32 , pub state : * mut i32 , pub rand_type : :: std :: os :: raw :: c_int , pub rand_deg : :: std :: os :: raw :: c_int , pub rand_sep : :: std :: os :: raw :: c_int , pub end_ptr : * mut i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of random_data"] [:: std :: mem :: size_of :: < random_data > () - 48usize] ; ["Alignment of random_data"] [:: std :: mem :: align_of :: < random_data > () - 8usize] ; ["Offset of field: random_data::fptr"] [:: std :: mem :: offset_of ! (random_data , fptr) - 0usize] ; ["Offset of field: random_data::rptr"] [:: std :: mem :: offset_of ! (random_data , rptr) - 8usize] ; ["Offset of field: random_data::state"] [:: std :: mem :: offset_of ! (random_data , state) - 16usize] ; ["Offset of field: random_data::rand_type"] [:: std :: mem :: offset_of ! (random_data , rand_type) - 24usize] ; ["Offset of field: random_data::rand_deg"] [:: std :: mem :: offset_of ! (random_data , rand_deg) - 28usize] ; ["Offset of field: random_data::rand_sep"] [:: std :: mem :: offset_of ! (random_data , rand_sep) - 32usize] ; ["Offset of field: random_data::end_ptr"] [:: std :: mem :: offset_of ! (random_data , end_ptr) - 40usize] ; } ; unsafe extern "C" { pub fn random_r (__buf : * mut random_data , __result : * mut i32) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srandom_r (__seed : :: std :: os :: raw :: c_uint , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn initstate_r (__seed : :: std :: os :: raw :: c_uint , __statebuf : * mut :: std :: os :: raw :: c_char , __statelen : usize , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setstate_r (__statebuf : * mut :: std :: os :: raw :: c_char , __buf : * mut random_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rand () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand (__seed : :: std :: os :: raw :: c_uint) ; } unsafe extern "C" { pub fn rand_r (__seed : * mut :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn drand48 () -> f64 ; } unsafe extern "C" { pub fn erand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> f64 ; } unsafe extern "C" { pub fn lrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn nrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn mrand48 () -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn jrand48 (__xsubi : * mut :: std :: os :: raw :: c_ushort) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn srand48 (__seedval : :: std :: os :: raw :: c_long) ; } unsafe extern "C" { pub fn seed48 (__seed16v : * mut :: std :: os :: raw :: c_ushort) -> * mut :: std :: os :: raw :: c_ushort ; } unsafe extern "C" { pub fn lcong48 (__param : * mut :: std :: os :: raw :: c_ushort) ; } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct drand48_data { pub __x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __old_x : [:: std :: os :: raw :: c_ushort ; 3usize] , pub __c : :: std :: os :: raw :: c_ushort , pub __init : :: std :: os :: raw :: c_ushort , pub __a : :: std :: os :: raw :: c_ulonglong , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of drand48_data"] [:: std :: mem :: size_of :: < drand48_data > () - 24usize] ; ["Alignment of drand48_data"] [:: std :: mem :: align_of :: < drand48_data > () - 8usize] ; ["Offset of field: drand48_data::__x"] [:: std :: mem :: offset_of ! (drand48_data , __x) - 0usize] ; ["Offset of field: drand48_data::__old_x"] [:: std :: mem :: offset_of ! (drand48_data , __old_x) - 6usize] ; ["Offset of field: drand48_data::__c"] [:: std :: mem :: offset_of ! (drand48_data , __c) - 12usize] ; ["Offset of field: drand48_data::__init"] [:: std :: mem :: offset_of ! (drand48_data , __init) - 14usize] ; ["Offset of field: drand48_data::__a"] [:: std :: mem :: offset_of ! (drand48_data , __a) - 16usize] ; } ; unsafe extern "C" { pub fn drand48_r (__buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn erand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut f64) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn nrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mrand48_r (__buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn jrand48_r (__xsubi : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data , __result : * mut :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn srand48_r (__seedval : :: std :: os :: raw :: c_long , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn seed48_r (__seed16v : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn lcong48_r (__param : * mut :: std :: os :: raw :: c_ushort , __buffer : * mut drand48_data) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn arc4random () -> __uint32_t ; } unsafe extern "C" { pub fn arc4random_buf (__buf : * mut :: std :: os :: raw :: c_void , __size : usize) ; } unsafe extern "C" { pub fn arc4random_uniform (__upper_bound : __uint32_t) -> __uint32_t ; } unsafe extern "C" { pub fn malloc (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn calloc (__nmemb : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn realloc (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn free (__ptr : * mut :: std :: os :: raw :: c_void) ; } unsafe extern "C" { pub fn reallocarray (__ptr : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn alloca (__size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn valloc (__size : usize) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn posix_memalign (__memptr : * mut * mut :: std :: os :: raw :: c_void , __alignment : usize , __size : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn aligned_alloc (__alignment : :: std :: os :: raw :: c_ulong , __size : :: std :: os :: raw :: c_ulong) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn abort () -> ! ; } unsafe extern "C" { pub fn atexit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn at_quick_exit (__func : :: std :: option :: Option < unsafe extern "C" fn () >) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn on_exit (__func : :: std :: option :: Option < unsafe extern "C" fn (__status : :: std :: os :: raw :: c_int , __arg : * mut :: std :: os :: raw :: c_void) > , __arg : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn quick_exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn _Exit (__status : :: std :: os :: raw :: c_int) -> ! ; } unsafe extern "C" { pub fn getenv (__name : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn putenv (__string : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setenv (__name : * const :: std :: os :: raw :: c_char , __value : * const :: std :: os :: raw :: c_char , __replace : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn unsetenv (__name : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearenv () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mktemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn mkstemp (__template : * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkstemps (__template : * mut :: std :: os :: raw :: c_char , __suffixlen : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mkdtemp (__template : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn system (__command : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn realpath (__name : * const :: std :: os :: raw :: c_char , __resolved : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } pub type __compar_fn_t = :: std :: option :: Option < unsafe extern "C" fn (arg1 : * const :: std :: os :: raw :: c_void , arg2 : * const :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; unsafe extern "C" { pub fn bsearch (__key : * const :: std :: os :: raw :: c_void , __base : * const :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) -> * mut :: std :: os :: raw :: c_void ; } unsafe extern "C" { pub fn qsort (__base : * mut :: std :: os :: raw :: c_void , __nmemb : usize , __size : usize , __compar : __compar_fn_t) ; } unsafe extern "C" { pub fn abs (__x : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn labs (__x : :: std :: os :: raw :: c_long) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn llabs (__x : :: std :: os :: raw :: c_longlong) -> :: std :: os :: raw :: c_longlong ; } unsafe extern "C" { pub fn div (__numer : :: std :: os :: raw :: c_int , __denom : :: std :: os :: raw :: c_int) -> div_t ; } unsafe extern "C" { pub fn ldiv (__numer : :: std :: os :: raw :: c_long , __denom : :: std :: os :: raw :: c_long) -> ldiv_t ; } unsafe extern "C" { pub fn lldiv (__numer : :: std :: os :: raw :: c_longlong , __denom : :: std :: os :: raw :: c_longlong) -> lldiv_t ; } unsafe extern "C" { pub fn ecvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn gcvt (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qecvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qfcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn qgcvt (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn ecvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fcvt_r (__value : f64 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qecvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn qfcvt_r (__value : u128 , __ndigit : :: std :: os :: raw :: c_int , __decpt : * mut :: std :: os :: raw :: c_int , __sign : * mut :: std :: os :: raw :: c_int , __buf : * mut :: std :: os :: raw :: c_char , __len : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mblen (__s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbtowc (__pwc : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn wctomb (__s : * mut :: std :: os :: raw :: c_char , __wchar : wchar_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn mbstowcs (__pwcs : * mut wchar_t , __s : * const :: std :: os :: raw :: c_char , __n : usize) -> usize ; } unsafe extern "C" { pub fn wcstombs (__s : * mut :: std :: os :: raw :: c_char , __pwcs : * const wchar_t , __n : usize) -> usize ; } unsafe extern "C" { pub fn rpmatch (__response : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getsubopt (__optionp : * mut * mut :: std :: os :: raw :: c_char , __tokens : * const * mut :: std :: os :: raw :: c_char , __valuep : * mut * mut :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getloadavg (__loadavg : * mut f64 , __nelem : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } # [repr (C)] # [derive (Copy , Clone)] pub struct __mbstate_t { pub __count : :: std :: os :: raw :: c_int , pub __value : __mbstate_t__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union __mbstate_t__bindgen_ty_1 { pub __wch : :: std :: os :: raw :: c_uint , pub __wchb : [:: std :: os :: raw :: c_char ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: size_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Alignment of __mbstate_t__bindgen_ty_1"] [:: std :: mem :: align_of :: < __mbstate_t__bindgen_ty_1 > () - 4usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wch"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wch) - 0usize] ; ["Offset of field: __mbstate_t__bindgen_ty_1::__wchb"] [:: std :: mem :: offset_of ! (__mbstate_t__bindgen_ty_1 , __wchb) - 0usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __mbstate_t"] [:: std :: mem :: size_of :: < __mbstate_t > () - 8usize] ; ["Alignment of __mbstate_t"] [:: std :: mem :: align_of :: < __mbstate_t > () - 4usize] ; ["Offset of field: __mbstate_t::__count"] [:: std :: mem :: offset_of ! (__mbstate_t , __count) - 0usize] ; ["Offset of field: __mbstate_t::__value"] [:: std :: mem :: offset_of ! (__mbstate_t , __value) - 4usize] ; } ; impl :: std :: fmt :: Debug for __mbstate_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "__mbstate_t {{ __count: {:?}, __value: {:?} }}" , self . __count , self . __value) } } # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos_t { pub __pos : __off_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos_t"] [:: std :: mem :: size_of :: < _G_fpos_t > () - 16usize] ; ["Alignment of _G_fpos_t"] [:: std :: mem :: align_of :: < _G_fpos_t > () - 8usize] ; ["Offset of field: _G_fpos_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos_t , __pos) - 0usize] ; ["Offset of field: _G_fpos_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos_t = _G_fpos_t ; # [repr (C)] # [derive (Copy , Clone)] pub struct _G_fpos64_t { pub __pos : __off64_t , pub __state : __mbstate_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _G_fpos64_t"] [:: std :: mem :: size_of :: < _G_fpos64_t > () - 16usize] ; ["Alignment of _G_fpos64_t"] [:: std :: mem :: align_of :: < _G_fpos64_t > () - 8usize] ; ["Offset of field: _G_fpos64_t::__pos"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __pos) - 0usize] ; ["Offset of field: _G_fpos64_t::__state"] [:: std :: mem :: offset_of ! (_G_fpos64_t , __state) - 8usize] ; } ; impl :: std :: fmt :: Debug for _G_fpos64_t { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "_G_fpos64_t {{ __pos: {:?}, __state: {:?} }}" , self . __pos , self . __state) } } pub type __fpos64_t = _G_fpos64_t ; pub type __FILE = _IO_FILE ; pub type FILE = _IO_FILE ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_marker { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_codecvt { _unused : [u8 ; 0] , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_wide_data { _unused : [u8 ; 0] , } pub type _IO_lock_t = :: std :: os :: raw :: c_void ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_FILE { pub _flags : :: std :: os :: raw :: c_int , pub _IO_read_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_read_end : * mut :: std :: os :: raw :: c_char , pub _IO_read_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_base : * mut :: std :: os :: raw :: c_char , pub _IO_write_ptr : * mut :: std :: os :: raw :: c_char , pub _IO_write_end : * mut :: std :: os :: raw :: c_char , pub _IO_buf_base : * mut :: std :: os :: raw :: c_char , pub _IO_buf_end : * mut :: std :: os :: raw :: c_char , pub _IO_save_base : * mut :: std :: os :: raw :: c_char , pub _IO_backup_base : * mut :: std :: os :: raw :: c_char , pub _IO_save_end : * mut :: std :: os :: raw :: c_char , pub _markers : * mut _IO_marker , pub _chain : * mut _IO_FILE , pub _fileno : :: std :: os :: raw :: c_int , pub _bitfield_align_1 : [u32 ; 0] , pub _bitfield_1 : __BindgenBitfieldUnit < [u8 ; 3usize] > , pub _short_backupbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _old_offset : __off_t , pub _cur_column : :: std :: os :: raw :: c_ushort , pub _vtable_offset : :: std :: os :: raw :: c_schar , pub _shortbuf : [:: std :: os :: raw :: c_char ; 1usize] , pub _lock : * mut _IO_lock_t , pub _offset : __off64_t , pub _codecvt : * mut _IO_codecvt , pub _wide_data : * mut _IO_wide_data , pub _freeres_list : * mut _IO_FILE , pub _freeres_buf : * mut :: std :: os :: raw :: c_void , pub _prevchain : * mut * mut _IO_FILE , pub _mode : :: std :: os :: raw :: c_int , pub _unused3 : :: std :: os :: raw :: c_int , pub _total_written : __uint64_t , pub _unused2 : [:: std :: os :: raw :: c_char ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_FILE"] [:: std :: mem :: size_of :: < _IO_FILE > () - 216usize] ; ["Alignment of _IO_FILE"] [:: std :: mem :: align_of :: < _IO_FILE > () - 8usize] ; ["Offset of field: _IO_FILE::_flags"] [:: std :: mem :: offset_of ! (_IO_FILE , _flags) - 0usize] ; ["Offset of field: _IO_FILE::_IO_read_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_ptr) - 8usize] ; ["Offset of field: _IO_FILE::_IO_read_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_end) - 16usize] ; ["Offset of field: _IO_FILE::_IO_read_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_read_base) - 24usize] ; ["Offset of field: _IO_FILE::_IO_write_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_base) - 32usize] ; ["Offset of field: _IO_FILE::_IO_write_ptr"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_ptr) - 40usize] ; ["Offset of field: _IO_FILE::_IO_write_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_write_end) - 48usize] ; ["Offset of field: _IO_FILE::_IO_buf_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_base) - 56usize] ; ["Offset of field: _IO_FILE::_IO_buf_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_buf_end) - 64usize] ; ["Offset of field: _IO_FILE::_IO_save_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_base) - 72usize] ; ["Offset of field: _IO_FILE::_IO_backup_base"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_backup_base) - 80usize] ; ["Offset of field: _IO_FILE::_IO_save_end"] [:: std :: mem :: offset_of ! (_IO_FILE , _IO_save_end) - 88usize] ; ["Offset of field: _IO_FILE::_markers"] [:: std :: mem :: offset_of ! (_IO_FILE , _markers) - 96usize] ; ["Offset of field: _IO_FILE::_chain"] [:: std :: mem :: offset_of ! (_IO_FILE , _chain) - 104usize] ; ["Offset of field: _IO_FILE::_fileno"] [:: std :: mem :: offset_of ! (_IO_FILE , _fileno) - 112usize] ; ["Offset of field: _IO_FILE::_short_backupbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _short_backupbuf) - 119usize] ; ["Offset of field: _IO_FILE::_old_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _old_offset) - 120usize] ; ["Offset of field: _IO_FILE::_cur_column"] [:: std :: mem :: offset_of ! (_IO_FILE , _cur_column) - 128usize] ; ["Offset of field: _IO_FILE::_vtable_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _vtable_offset) - 130usize] ; ["Offset of field: _IO_FILE::_shortbuf"] [:: std :: mem :: offset_of ! (_IO_FILE , _shortbuf) - 131usize] ; ["Offset of field: _IO_FILE::_lock"] [:: std :: mem :: offset_of ! (_IO_FILE , _lock) - 136usize] ; ["Offset of field: _IO_FILE::_offset"] [:: std :: mem :: offset_of ! (_IO_FILE , _offset) - 144usize] ; ["Offset of field: _IO_FILE::_codecvt"] [:: std :: mem :: offset_of ! (_IO_FILE , _codecvt) - 152usize] ; ["Offset of field: _IO_FILE::_wide_data"] [:: std :: mem :: offset_of ! (_IO_FILE , _wide_data) - 160usize] ; ["Offset of field: _IO_FILE::_freeres_list"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_list) - 168usize] ; ["Offset of field: _IO_FILE::_freeres_buf"] [:: std :: mem :: offset_of ! (_IO_FILE , _freeres_buf) - 176usize] ; ["Offset of field: _IO_FILE::_prevchain"] [:: std :: mem :: offset_of ! (_IO_FILE , _prevchain) - 184usize] ; ["Offset of field: _IO_FILE::_mode"] [:: std :: mem :: offset_of ! (_IO_FILE , _mode) - 192usize] ; ["Offset of field: _IO_FILE::_unused3"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused3) - 196usize] ; ["Offset of field: _IO_FILE::_total_written"] [:: std :: mem :: offset_of ! (_IO_FILE , _total_written) - 200usize] ; ["Offset of field: _IO_FILE::_unused2"] [:: std :: mem :: offset_of ! (_IO_FILE , _unused2) - 208usize] ; } ; impl _IO_FILE { # [inline] pub fn _flags2 (& self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (self . _bitfield_1 . get (0usize , 24u8) as u32) } } # [inline] pub fn set__flags2 (& mut self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = :: std :: mem :: transmute (val) ; self . _bitfield_1 . set (0usize , 24u8 , val as u64) } } # [inline] pub unsafe fn _flags2_raw (this : * const Self) -> :: std :: os :: raw :: c_int { unsafe { :: std :: mem :: transmute (< __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_get (:: std :: ptr :: addr_of ! ((* this) . _bitfield_1) , 0usize , 24u8 ,) as u32) } } # [inline] pub unsafe fn set__flags2_raw (this : * mut Self , val : :: std :: os :: raw :: c_int) { unsafe { let val : u32 = i32::cast_unsigned (val) ; < __BindgenBitfieldUnit < [u8 ; 3usize] > > :: raw_set (:: std :: ptr :: addr_of_mut ! ((* this) . _bitfield_1) , 0usize , 24u8 , val as u64 ,) } } # [inline] pub fn new_bitfield_1 (_flags2 : :: std :: os :: raw :: c_int) -> __BindgenBitfieldUnit < [u8 ; 3usize] > { let mut __bindgen_bitfield_unit : __BindgenBitfieldUnit < [u8 ; 3usize] > = Default :: default () ; __bindgen_bitfield_unit . set (0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_unit } } pub type cookie_read_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * mut :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_write_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __buf : * const :: std :: os :: raw :: c_char , __nbytes : usize) -> __ssize_t > ; pub type cookie_seek_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void , __pos : * mut __off64_t , __w : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int > ; pub type cookie_close_function_t = :: std :: option :: Option < unsafe extern "C" fn (__cookie : * mut :: std :: os :: raw :: c_void) -> :: std :: os :: raw :: c_int > ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct _IO_cookie_io_functions_t { pub read : cookie_read_function_t , pub write : cookie_write_function_t , pub seek : cookie_seek_function_t , pub close : cookie_close_function_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of _IO_cookie_io_functions_t"] [:: std :: mem :: size_of :: < _IO_cookie_io_functions_t > () - 32usize] ; ["Alignment of _IO_cookie_io_functions_t"] [:: std :: mem :: align_of :: < _IO_cookie_io_functions_t > () - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::read"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , read) - 0usize] ; ["Offset of field: _IO_cookie_io_functions_t::write"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , write) - 8usize] ; ["Offset of field: _IO_cookie_io_functions_t::seek"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , seek) - 16usize] ; ["Offset of field: _IO_cookie_io_functions_t::close"] [:: std :: mem :: offset_of ! (_IO_cookie_io_functions_t , close) - 24usize] ; } ; pub type cookie_io_functions_t = _IO_cookie_io_functions_t ; pub type fpos_t = __fpos_t ; unsafe extern "C" { pub static mut stdin : * mut FILE ; } unsafe extern "C" { pub static mut stdout : * mut FILE ; } unsafe extern "C" { pub static mut stderr : * mut FILE ; } unsafe extern "C" { pub fn remove (__filename : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn rename (__old : * const :: std :: os :: raw :: c_char , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn renameat (__oldfd : :: std :: os :: raw :: c_int , __old : * const :: std :: os :: raw :: c_char , __newfd : :: std :: os :: raw :: c_int , __new : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn tmpfile () -> * mut FILE ; } unsafe extern "C" { pub fn tmpnam (arg1 : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tmpnam_r (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn tempnam (__dir : * const :: std :: os :: raw :: c_char , __pfx : * const :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn fflush (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fflush_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn freopen (__filename : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> * mut FILE ; } unsafe extern "C" { pub fn fdopen (__fd : :: std :: os :: raw :: c_int , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn fopencookie (__magic_cookie : * mut :: std :: os :: raw :: c_void , __modes : * const :: std :: os :: raw :: c_char , __io_funcs : cookie_io_functions_t) -> * mut FILE ; } unsafe extern "C" { pub fn fmemopen (__s : * mut :: std :: os :: raw :: c_void , __len : usize , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn open_memstream (__bufloc : * mut * mut :: std :: os :: raw :: c_char , __sizeloc : * mut usize) -> * mut FILE ; } unsafe extern "C" { pub fn setbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn setvbuf (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __modes : :: std :: os :: raw :: c_int , __n : usize) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn setbuffer (__stream : * mut FILE , __buf : * mut :: std :: os :: raw :: c_char , __size : usize) ; } unsafe extern "C" { pub fn setlinebuf (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fprintf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn printf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfprintf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vprintf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsprintf (__s : * mut :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn snprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsnprintf (__s : * mut :: std :: os :: raw :: c_char , __maxlen : :: std :: os :: raw :: c_ulong , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vasprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __f : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn asprintf (__ptr : * mut * mut :: std :: os :: raw :: c_char , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vdprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn dprintf (__fd : :: std :: os :: raw :: c_int , __fmt : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fscanf (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn scanf (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn sscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_fscanf"] pub fn fscanf1 (__stream : * mut FILE , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_scanf"] pub fn scanf1 (__format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_sscanf"] pub fn sscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , ...) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vfscanf (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vscanf (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn vsscanf (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vfscanf"] pub fn vfscanf1 (__s : * mut FILE , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vscanf"] pub fn vscanf1 (__format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [link_name = "\u{1}__isoc99_vsscanf"] pub fn vsscanf1 (__s : * const :: std :: os :: raw :: c_char , __format : * const :: std :: os :: raw :: c_char , __arg : * mut __va_list_tag) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getchar_unlocked () -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgetc_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fputc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putc_unlocked (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putchar_unlocked (__c : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn getw (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn putw (__w : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fgets (__s : * mut :: std :: os :: raw :: c_char , __n : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn __getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getdelim (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __delimiter : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn getline (__lineptr : * mut * mut :: std :: os :: raw :: c_char , __n : * mut usize , __stream : * mut FILE) -> __ssize_t ; } unsafe extern "C" { pub fn fputs (__s : * const :: std :: os :: raw :: c_char , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn puts (__s : * const :: std :: os :: raw :: c_char) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ungetc (__c : :: std :: os :: raw :: c_int , __stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fread (__ptr : * mut :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __stream : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fwrite (__ptr : * const :: std :: os :: raw :: c_void , __size : :: std :: os :: raw :: c_ulong , __n : :: std :: os :: raw :: c_ulong , __s : * mut FILE) -> :: std :: os :: raw :: c_ulong ; } unsafe extern "C" { pub fn fread_unlocked (__ptr : * mut :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fwrite_unlocked (__ptr : * const :: std :: os :: raw :: c_void , __size : usize , __n : usize , __stream : * mut FILE) -> usize ; } unsafe extern "C" { pub fn fseek (__stream : * mut FILE , __off : :: std :: os :: raw :: c_long , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftell (__stream : * mut FILE) -> :: std :: os :: raw :: c_long ; } unsafe extern "C" { pub fn rewind (__stream : * mut FILE) ; } unsafe extern "C" { pub fn fseeko (__stream : * mut FILE , __off : __off_t , __whence : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ftello (__stream : * mut FILE) -> __off_t ; } unsafe extern "C" { pub fn fgetpos (__stream : * mut FILE , __pos : * mut fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fsetpos (__stream : * mut FILE , __pos : * const fpos_t) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn clearerr_unlocked (__stream : * mut FILE) ; } unsafe extern "C" { pub fn feof_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn ferror_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn perror (__s : * const :: std :: os :: raw :: c_char) ; } unsafe extern "C" { pub fn fileno (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn fileno_unlocked (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn pclose (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn popen (__command : * const :: std :: os :: raw :: c_char , __modes : * const :: std :: os :: raw :: c_char) -> * mut FILE ; } unsafe extern "C" { pub fn ctermid (__s : * mut :: std :: os :: raw :: c_char) -> * mut :: std :: os :: raw :: c_char ; } unsafe extern "C" { pub fn flockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn ftrylockfile (__stream : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn funlockfile (__stream : * mut FILE) ; } unsafe extern "C" { pub fn __uflow (arg1 : * mut FILE) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { pub fn __overflow (arg1 : * mut FILE , arg2 : :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_int ; } pub type int_least8_t = __int_least8_t ; pub type int_least16_t = __int_least16_t ; pub type int_least32_t = __int_least32_t ; pub type int_least64_t = __int_least64_t ; pub type uint_least8_t = __uint_least8_t ; pub type uint_least16_t = __uint_least16_t ; pub type uint_least32_t = __uint_least32_t ; pub type uint_least64_t = __uint_least64_t ; pub type int_fast8_t = :: std :: os :: raw :: c_schar ; pub type int_fast16_t = :: std :: os :: raw :: c_long ; pub type int_fast32_t = :: std :: os :: raw :: c_long ; pub type int_fast64_t = :: std :: os :: raw :: c_long ; pub type uint_fast8_t = :: std :: os :: raw :: c_uchar ; pub type uint_fast16_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast32_t = :: std :: os :: raw :: c_ulong ; pub type uint_fast64_t = :: std :: os :: raw :: c_ulong ; pub type intmax_t = __intmax_t ; pub type uintmax_t = __uintmax_t ; pub type __gwchar_t = :: std :: os :: raw :: c_int ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct imaxdiv_t { pub quot : :: std :: os :: raw :: c_long , pub rem : :: std :: os :: raw :: c_long , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of imaxdiv_t"] [:: std :: mem :: size_of :: < imaxdiv_t > () - 16usize] ; ["Alignment of imaxdiv_t"] [:: std :: mem :: align_of :: < imaxdiv_t > () - 8usize] ; ["Offset of field: imaxdiv_t::quot"] [:: std :: mem :: offset_of ! (imaxdiv_t , quot) - 0usize] ; ["Offset of field: imaxdiv_t::rem"] [:: std :: mem :: offset_of ! (imaxdiv_t , rem) - 8usize] ; } ; unsafe extern "C" { pub fn imaxabs (__n : intmax_t) -> intmax_t ; } unsafe extern "C" { pub fn imaxdiv (__numer : intmax_t , __denom : intmax_t) -> imaxdiv_t ; } unsafe extern "C" { pub fn strtoimax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn strtoumax (__nptr : * const :: std :: os :: raw :: c_char , __endptr : * mut * mut :: std :: os :: raw :: c_char , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } unsafe extern "C" { pub fn wcstoimax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> intmax_t ; } unsafe extern "C" { pub fn wcstoumax (__nptr : * const __gwchar_t , __endptr : * mut * mut __gwchar_t , __base : :: std :: os :: raw :: c_int) -> uintmax_t ; } pub type csh = usize ; # [repr (u32)] # [doc = " Architecture type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_arch { # [doc = "< ARM architecture (including Thumb, Thumb-2)"] CS_ARCH_ARM = 0 , # [doc = "< ARM-64, also called AArch64"] CS_ARCH_ARM64 = 1 , # [doc = "< Mips architecture"] CS_ARCH_MIPS = 2 , # [doc = "< X86 architecture (including x86 & x86-64)"] CS_ARCH_X86 = 3 , # [doc = "< PowerPC architecture"] CS_ARCH_PPC = 4 , # [doc = "< Sparc architecture"] CS_ARCH_SPARC = 5 , # [doc = "< SystemZ architecture"] CS_ARCH_SYSZ = 6 , # [doc = "< XCore architecture"] CS_ARCH_XCORE = 7 , # [doc = "< 68K architecture"] CS_ARCH_M68K = 8 , # [doc = "< TMS320C64x architecture"] CS_ARCH_TMS320C64X = 9 , # [doc = "< 680X architecture"] CS_ARCH_M680X = 10 , # [doc = "< Ethereum architecture"] CS_ARCH_EVM = 11 , # [doc = "< MOS65XX architecture (including MOS6502)"] CS_ARCH_MOS65XX = 12 , # [doc = "< WebAssembly architecture"] CS_ARCH_WASM = 13 , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] CS_ARCH_BPF = 14 , # [doc = "< RISCV architecture"] CS_ARCH_RISCV = 15 , # [doc = "< SH architecture"] CS_ARCH_SH = 16 , # [doc = "< TriCore architecture"] CS_ARCH_TRICORE = 17 , CS_ARCH_MAX = 18 , CS_ARCH_ALL = 65535 , } # [doc = "< little-endian mode (default mode)"] pub const cs_mode_CS_MODE_LITTLE_ENDIAN : cs_mode = 0 ; # [doc = "< 32-bit ARM"] pub const cs_mode_CS_MODE_ARM : cs_mode = 0 ; # [doc = "< 16-bit mode (X86)"] pub const cs_mode_CS_MODE_16 : cs_mode = 2 ; # [doc = "< 32-bit mode (X86)"] pub const cs_mode_CS_MODE_32 : cs_mode = 4 ; # [doc = "< 64-bit mode (X86, PPC)"] pub const cs_mode_CS_MODE_64 : cs_mode = 8 ; # [doc = "< ARM's Thumb mode, including Thumb-2"] pub const cs_mode_CS_MODE_THUMB : cs_mode = 16 ; # [doc = "< ARM's Cortex-M series"] pub const cs_mode_CS_MODE_MCLASS : cs_mode = 32 ; # [doc = "< ARMv8 A32 encodings for ARM"] pub const cs_mode_CS_MODE_V8 : cs_mode = 64 ; # [doc = "< MicroMips mode (MIPS)"] pub const cs_mode_CS_MODE_MICRO : cs_mode = 16 ; # [doc = "< Mips III ISA"] pub const cs_mode_CS_MODE_MIPS3 : cs_mode = 32 ; # [doc = "< Mips32r6 ISA"] pub const cs_mode_CS_MODE_MIPS32R6 : cs_mode = 64 ; # [doc = "< Mips II ISA"] pub const cs_mode_CS_MODE_MIPS2 : cs_mode = 128 ; # [doc = "< SparcV9 mode (Sparc)"] pub const cs_mode_CS_MODE_V9 : cs_mode = 16 ; # [doc = "< Quad Processing eXtensions mode (PPC)"] pub const cs_mode_CS_MODE_QPX : cs_mode = 16 ; # [doc = "< Signal Processing Engine mode (PPC)"] pub const cs_mode_CS_MODE_SPE : cs_mode = 32 ; # [doc = "< Book-E mode (PPC)"] pub const cs_mode_CS_MODE_BOOKE : cs_mode = 64 ; # [doc = "< Paired-singles mode (PPC)"] pub const cs_mode_CS_MODE_PS : cs_mode = 128 ; # [doc = "< M68K 68000 mode"] pub const cs_mode_CS_MODE_M68K_000 : cs_mode = 2 ; # [doc = "< M68K 68010 mode"] pub const cs_mode_CS_MODE_M68K_010 : cs_mode = 4 ; # [doc = "< M68K 68020 mode"] pub const cs_mode_CS_MODE_M68K_020 : cs_mode = 8 ; # [doc = "< M68K 68030 mode"] pub const cs_mode_CS_MODE_M68K_030 : cs_mode = 16 ; # [doc = "< M68K 68040 mode"] pub const cs_mode_CS_MODE_M68K_040 : cs_mode = 32 ; # [doc = "< M68K 68060 mode"] pub const cs_mode_CS_MODE_M68K_060 : cs_mode = 64 ; # [doc = "< big-endian mode"] pub const cs_mode_CS_MODE_BIG_ENDIAN : cs_mode = 2147483648 ; # [doc = "< Mips32 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS32 : cs_mode = 4 ; # [doc = "< Mips64 ISA (Mips)"] pub const cs_mode_CS_MODE_MIPS64 : cs_mode = 8 ; # [doc = "< M680X Hitachi 6301,6303 mode"] pub const cs_mode_CS_MODE_M680X_6301 : cs_mode = 2 ; # [doc = "< M680X Hitachi 6309 mode"] pub const cs_mode_CS_MODE_M680X_6309 : cs_mode = 4 ; # [doc = "< M680X Motorola 6800,6802 mode"] pub const cs_mode_CS_MODE_M680X_6800 : cs_mode = 8 ; # [doc = "< M680X Motorola 6801,6803 mode"] pub const cs_mode_CS_MODE_M680X_6801 : cs_mode = 16 ; # [doc = "< M680X Motorola/Freescale 6805 mode"] pub const cs_mode_CS_MODE_M680X_6805 : cs_mode = 32 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"] pub const cs_mode_CS_MODE_M680X_6808 : cs_mode = 64 ; # [doc = "< M680X Motorola 6809 mode"] pub const cs_mode_CS_MODE_M680X_6809 : cs_mode = 128 ; # [doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"] pub const cs_mode_CS_MODE_M680X_6811 : cs_mode = 256 ; # [doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"] pub const cs_mode_CS_MODE_M680X_CPU12 : cs_mode = 512 ; # [doc = "< M680X Freescale/NXP HCS08 mode"] pub const cs_mode_CS_MODE_M680X_HCS08 : cs_mode = 1024 ; # [doc = "< Classic BPF mode (default)"] pub const cs_mode_CS_MODE_BPF_CLASSIC : cs_mode = 0 ; # [doc = "< Extended BPF mode"] pub const cs_mode_CS_MODE_BPF_EXTENDED : cs_mode = 1 ; # [doc = "< RISCV RV32G"] pub const cs_mode_CS_MODE_RISCV32 : cs_mode = 1 ; # [doc = "< RISCV RV64G"] pub const cs_mode_CS_MODE_RISCV64 : cs_mode = 2 ; # [doc = "< RISCV compressed instructure mode"] pub const cs_mode_CS_MODE_RISCVC : cs_mode = 4 ; # [doc = "< MOS65XXX MOS 6502"] pub const cs_mode_CS_MODE_MOS65XX_6502 : cs_mode = 2 ; # [doc = "< MOS65XXX WDC 65c02"] pub const cs_mode_CS_MODE_MOS65XX_65C02 : cs_mode = 4 ; # [doc = "< MOS65XXX WDC W65c02"] pub const cs_mode_CS_MODE_MOS65XX_W65C02 : cs_mode = 8 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m/x"] pub const cs_mode_CS_MODE_MOS65XX_65816 : cs_mode = 16 ; # [doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_M : cs_mode = 32 ; # [doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"] pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_X : cs_mode = 64 ; pub const cs_mode_CS_MODE_MOS65XX_65816_LONG_MX : cs_mode = 96 ; # [doc = "< SH2"] pub const cs_mode_CS_MODE_SH2 : cs_mode = 2 ; # [doc = "< SH2A"] pub const cs_mode_CS_MODE_SH2A : cs_mode = 4 ; # [doc = "< SH3"] pub const cs_mode_CS_MODE_SH3 : cs_mode = 8 ; # [doc = "< SH4"] pub const cs_mode_CS_MODE_SH4 : cs_mode = 16 ; # [doc = "< SH4A"] pub const cs_mode_CS_MODE_SH4A : cs_mode = 32 ; # [doc = "< w/ FPU"] pub const cs_mode_CS_MODE_SHFPU : cs_mode = 64 ; # [doc = "< w/ DSP"] pub const cs_mode_CS_MODE_SHDSP : cs_mode = 128 ; # [doc = "< Tricore 1.1"] pub const cs_mode_CS_MODE_TRICORE_110 : cs_mode = 2 ; # [doc = "< Tricore 1.2"] pub const cs_mode_CS_MODE_TRICORE_120 : cs_mode = 4 ; # [doc = "< Tricore 1.3"] pub const cs_mode_CS_MODE_TRICORE_130 : cs_mode = 8 ; # [doc = "< Tricore 1.3.1"] pub const cs_mode_CS_MODE_TRICORE_131 : cs_mode = 16 ; # [doc = "< Tricore 1.6"] pub const cs_mode_CS_MODE_TRICORE_160 : cs_mode = 32 ; # [doc = "< Tricore 1.6.1"] pub const cs_mode_CS_MODE_TRICORE_161 : cs_mode = 64 ; # [doc = "< Tricore 1.6.2"] pub const cs_mode_CS_MODE_TRICORE_162 : cs_mode = 128 ; # [doc = " Mode type"] pub type cs_mode = :: std :: os :: raw :: c_uint ; pub type cs_malloc_t = :: std :: option :: Option < unsafe extern "C" fn (size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_calloc_t = :: std :: option :: Option < unsafe extern "C" fn (nmemb : usize , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_realloc_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void , size : usize) -> * mut :: std :: os :: raw :: c_void > ; pub type cs_free_t = :: std :: option :: Option < unsafe extern "C" fn (ptr : * mut :: std :: os :: raw :: c_void) > ; pub type cs_vsnprintf_t = :: std :: option :: Option < unsafe extern "C" fn (str_ : * mut :: std :: os :: raw :: c_char , size : usize , format : * const :: std :: os :: raw :: c_char , ap : * mut __va_list_tag) -> :: std :: os :: raw :: c_int > ; # [doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mem { pub malloc : cs_malloc_t , pub calloc : cs_calloc_t , pub realloc : cs_realloc_t , pub free : cs_free_t , pub vsnprintf : cs_vsnprintf_t , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mem"] [:: std :: mem :: size_of :: < cs_opt_mem > () - 40usize] ; ["Alignment of cs_opt_mem"] [:: std :: mem :: align_of :: < cs_opt_mem > () - 8usize] ; ["Offset of field: cs_opt_mem::malloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , malloc) - 0usize] ; ["Offset of field: cs_opt_mem::calloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , calloc) - 8usize] ; ["Offset of field: cs_opt_mem::realloc"] [:: std :: mem :: offset_of ! (cs_opt_mem , realloc) - 16usize] ; ["Offset of field: cs_opt_mem::free"] [:: std :: mem :: offset_of ! (cs_opt_mem , free) - 24usize] ; ["Offset of field: cs_opt_mem::vsnprintf"] [:: std :: mem :: offset_of ! (cs_opt_mem , vsnprintf) - 32usize] ; } ; # [doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_mnem { # [doc = " ID of instruction to be customized."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Customized instruction mnemonic."] pub mnemonic : * const :: std :: os :: raw :: c_char , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_mnem"] [:: std :: mem :: size_of :: < cs_opt_mnem > () - 16usize] ; ["Alignment of cs_opt_mnem"] [:: std :: mem :: align_of :: < cs_opt_mnem > () - 8usize] ; ["Offset of field: cs_opt_mnem::id"] [:: std :: mem :: offset_of ! (cs_opt_mnem , id) - 0usize] ; ["Offset of field: cs_opt_mnem::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_mnem , mnemonic) - 8usize] ; } ; # [repr (u32)] # [doc = " Runtime option for the disassembled engine"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_type { # [doc = "< No option specified"] CS_OPT_INVALID = 0 , # [doc = "< Assembly output syntax"] CS_OPT_SYNTAX = 1 , # [doc = "< Break down instruction structure into details"] CS_OPT_DETAIL = 2 , # [doc = "< Change engine's mode at run-time"] CS_OPT_MODE = 3 , # [doc = "< User-defined dynamic memory related functions"] CS_OPT_MEM = 4 , # [doc = "< Skip data when disassembling. Then engine is in SKIPDATA mode."] CS_OPT_SKIPDATA = 5 , # [doc = "< Setup user-defined function for SKIPDATA option"] CS_OPT_SKIPDATA_SETUP = 6 , # [doc = "< Customize instruction mnemonic"] CS_OPT_MNEMONIC = 7 , # [doc = "< print immediate operands in unsigned form"] CS_OPT_UNSIGNED = 8 , # [doc = "< ARM, prints branch immediates without offset."] CS_OPT_NO_BRANCH_OFFSET = 9 , } impl cs_opt_value { pub const CS_OPT_SYNTAX_DEFAULT : cs_opt_value = cs_opt_value :: CS_OPT_OFF ; } impl cs_opt_value { pub const CS_OPT_SYNTAX_NOREGNAME : cs_opt_value = cs_opt_value :: CS_OPT_ON ; } # [repr (u32)] # [doc = " Runtime option value (associated with option type above)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_opt_value { # [doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."] CS_OPT_OFF = 0 , # [doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."] CS_OPT_ON = 3 , # [doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_INTEL = 1 , # [doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_ATT = 2 , # [doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."] CS_OPT_SYNTAX_MASM = 4 , # [doc = "< MOS65XX use $ as hex prefix"] CS_OPT_SYNTAX_MOTOROLA = 5 , } # [repr (u32)] # [doc = " Common instruction operand types - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_op_type { # [doc = "< uninitialized/invalid operand."] CS_OP_INVALID = 0 , # [doc = "< Register operand."] CS_OP_REG = 1 , # [doc = "< Immediate operand."] CS_OP_IMM = 2 , # [doc = "< Memory operand. Can be ORed with another operand type."] CS_OP_MEM = 3 , # [doc = "< Floating-Point operand."] CS_OP_FP = 4 , } # [repr (u32)] # [doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_ac_type { # [doc = "< Uninitialized/invalid access type."] CS_AC_INVALID = 0 , # [doc = "< Operand read from memory or register."] CS_AC_READ = 1 , # [doc = "< Operand write to memory or register."] CS_AC_WRITE = 2 , } # [repr (u32)] # [doc = " Common instruction groups - to be consistent across all architectures."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_group_type { # [doc = "< uninitialized/invalid group."] CS_GRP_INVALID = 0 , # [doc = "< all jump instructions (conditional+direct+indirect jumps)"] CS_GRP_JUMP = 1 , # [doc = "< all call instructions"] CS_GRP_CALL = 2 , # [doc = "< all return instructions"] CS_GRP_RET = 3 , # [doc = "< all interrupt instructions (int+syscall)"] CS_GRP_INT = 4 , # [doc = "< all interrupt return instructions"] CS_GRP_IRET = 5 , # [doc = "< all privileged instructions"] CS_GRP_PRIVILEGE = 6 , # [doc = "< all relative branching instructions"] CS_GRP_BRANCH_RELATIVE = 7 , } # [doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."] pub type cs_skipdata_cb_t = :: std :: option :: Option < unsafe extern "C" fn (code : * const u8 , code_size : usize , offset : usize , user_data : * mut :: std :: os :: raw :: c_void) -> usize > ; # [doc = " User-customized setup for SKIPDATA option"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_opt_skipdata { # [doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."] pub mnemonic : * const :: std :: os :: raw :: c_char , # [doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes.\n TriCore: 2 bytes."] pub callback : cs_skipdata_cb_t , # [doc = " User-defined data to be passed to @callback function pointer."] pub user_data : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_opt_skipdata"] [:: std :: mem :: size_of :: < cs_opt_skipdata > () - 24usize] ; ["Alignment of cs_opt_skipdata"] [:: std :: mem :: align_of :: < cs_opt_skipdata > () - 8usize] ; ["Offset of field: cs_opt_skipdata::mnemonic"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , mnemonic) - 0usize] ; ["Offset of field: cs_opt_skipdata::callback"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , callback) - 8usize] ; ["Offset of field: cs_opt_skipdata::user_data"] [:: std :: mem :: offset_of ! (cs_opt_skipdata , user_data) - 16usize] ; } ; # [repr (u32)] # [doc = " ARM shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_shifter { ARM_SFT_INVALID = 0 , # [doc = "< shift with immediate const"] ARM_SFT_ASR = 1 , # [doc = "< shift with immediate const"] ARM_SFT_LSL = 2 , # [doc = "< shift with immediate const"] ARM_SFT_LSR = 3 , # [doc = "< shift with immediate const"] ARM_SFT_ROR = 4 , # [doc = "< shift with immediate const"] ARM_SFT_RRX = 5 , # [doc = "< shift with register"] ARM_SFT_ASR_REG = 6 , # [doc = "< shift with register"] ARM_SFT_LSL_REG = 7 , # [doc = "< shift with register"] ARM_SFT_LSR_REG = 8 , # [doc = "< shift with register"] ARM_SFT_ROR_REG = 9 , # [doc = "< shift with register"] ARM_SFT_RRX_REG = 10 , } # [repr (u32)] # [doc = " ARM condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cc { ARM_CC_INVALID = 0 , # [doc = "< Equal                      Equal"] ARM_CC_EQ = 1 , # [doc = "< Not equal                  Not equal, or unordered"] ARM_CC_NE = 2 , # [doc = "< Carry set                  >, ==, or unordered"] ARM_CC_HS = 3 , # [doc = "< Carry clear                Less than"] ARM_CC_LO = 4 , # [doc = "< Minus, negative            Less than"] ARM_CC_MI = 5 , # [doc = "< Plus, positive or zero     >, ==, or unordered"] ARM_CC_PL = 6 , # [doc = "< Overflow                   Unordered"] ARM_CC_VS = 7 , # [doc = "< No overflow                Not unordered"] ARM_CC_VC = 8 , # [doc = "< Unsigned higher            Greater than, or unordered"] ARM_CC_HI = 9 , # [doc = "< Unsigned lower or same     Less than or equal"] ARM_CC_LS = 10 , # [doc = "< Greater than or equal      Greater than or equal"] ARM_CC_GE = 11 , # [doc = "< Less than                  Less than, or unordered"] ARM_CC_LT = 12 , # [doc = "< Greater than               Greater than"] ARM_CC_GT = 13 , # [doc = "< Less than or equal         <, ==, or unordered"] ARM_CC_LE = 14 , # [doc = "< Always (unconditional)     Always (unconditional)"] ARM_CC_AL = 15 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_sysreg { # [doc = " Special registers for MSR"] ARM_SYSREG_INVALID = 0 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_C = 1 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_X = 2 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_S = 4 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_F = 8 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_C = 16 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_X = 32 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_S = 64 , # [doc = " Special registers for MSR"] ARM_SYSREG_CPSR_F = 128 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR = 256 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_G = 257 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQ = 258 , # [doc = " Special registers for MSR"] ARM_SYSREG_APSR_NZCVQG = 259 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR = 260 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_G = 261 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQG = 262 , # [doc = " Special registers for MSR"] ARM_SYSREG_IAPSR_NZCVQ = 263 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR = 264 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_G = 265 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQG = 266 , # [doc = " Special registers for MSR"] ARM_SYSREG_EAPSR_NZCVQ = 267 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR = 268 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_G = 269 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQG = 270 , # [doc = " Special registers for MSR"] ARM_SYSREG_XPSR_NZCVQ = 271 , # [doc = " Special registers for MSR"] ARM_SYSREG_IPSR = 272 , # [doc = " Special registers for MSR"] ARM_SYSREG_EPSR = 273 , # [doc = " Special registers for MSR"] ARM_SYSREG_IEPSR = 274 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP = 275 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP = 276 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK = 277 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI = 278 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_MAX = 279 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK = 280 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL = 281 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM = 282 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM = 283 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSP_NS = 284 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSP_NS = 285 , # [doc = " Special registers for MSR"] ARM_SYSREG_MSPLIM_NS = 286 , # [doc = " Special registers for MSR"] ARM_SYSREG_PSPLIM_NS = 287 , # [doc = " Special registers for MSR"] ARM_SYSREG_PRIMASK_NS = 288 , # [doc = " Special registers for MSR"] ARM_SYSREG_BASEPRI_NS = 289 , # [doc = " Special registers for MSR"] ARM_SYSREG_FAULTMASK_NS = 290 , # [doc = " Special registers for MSR"] ARM_SYSREG_CONTROL_NS = 291 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_NS = 292 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_USR = 293 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_USR = 294 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_USR = 295 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_USR = 296 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_USR = 297 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_USR = 298 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_USR = 299 , # [doc = " Special registers for MSR"] ARM_SYSREG_R8_FIQ = 300 , # [doc = " Special registers for MSR"] ARM_SYSREG_R9_FIQ = 301 , # [doc = " Special registers for MSR"] ARM_SYSREG_R10_FIQ = 302 , # [doc = " Special registers for MSR"] ARM_SYSREG_R11_FIQ = 303 , # [doc = " Special registers for MSR"] ARM_SYSREG_R12_FIQ = 304 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_FIQ = 305 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_FIQ = 306 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_IRQ = 307 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_IRQ = 308 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_SVC = 309 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_SVC = 310 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_ABT = 311 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_ABT = 312 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_UND = 313 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_UND = 314 , # [doc = " Special registers for MSR"] ARM_SYSREG_LR_MON = 315 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_MON = 316 , # [doc = " Special registers for MSR"] ARM_SYSREG_ELR_HYP = 317 , # [doc = " Special registers for MSR"] ARM_SYSREG_SP_HYP = 318 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_FIQ = 319 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_IRQ = 320 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_SVC = 321 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_ABT = 322 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_UND = 323 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_MON = 324 , # [doc = " Special registers for MSR"] ARM_SYSREG_SPSR_HYP = 325 , } # [repr (u32)] # [doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_mem_barrier { ARM_MB_INVALID = 0 , ARM_MB_RESERVED_0 = 1 , ARM_MB_OSHLD = 2 , ARM_MB_OSHST = 3 , ARM_MB_OSH = 4 , ARM_MB_RESERVED_4 = 5 , ARM_MB_NSHLD = 6 , ARM_MB_NSHST = 7 , ARM_MB_NSH = 8 , ARM_MB_RESERVED_8 = 9 , ARM_MB_ISHLD = 10 , ARM_MB_ISHST = 11 , ARM_MB_ISH = 12 , ARM_MB_RESERVED_12 = 13 , ARM_MB_LD = 14 , ARM_MB_ST = 15 , ARM_MB_SY = 16 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM_OP_FP = 4 , # [doc = "< C-Immediate (coprocessor registers)"] ARM_OP_CIMM = 64 , # [doc = "< P-Immediate (coprocessor registers)"] ARM_OP_PIMM = 65 , # [doc = "< operand for SETEND instruction"] ARM_OP_SETEND = 66 , # [doc = "< MSR/MRS special register operand"] ARM_OP_SYSREG = 67 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_setend_type { # [doc = "< Uninitialized."] ARM_SETEND_INVALID = 0 , # [doc = "< BE operand."] ARM_SETEND_BE = 1 , # [doc = "< LE operand"] ARM_SETEND_LE = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0 , ARM_CPSMODE_IE = 2 , ARM_CPSMODE_ID = 3 , } # [repr (u32)] # [doc = " Operand type for SETEND instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0 , ARM_CPSFLAG_F = 1 , ARM_CPSFLAG_I = 2 , ARM_CPSFLAG_A = 4 , # [doc = "< no flag"] ARM_CPSFLAG_NONE = 16 , } # [repr (u32)] # [doc = " Data type for elements of vector instructions."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0 , ARM_VECTORDATA_I8 = 1 , ARM_VECTORDATA_I16 = 2 , ARM_VECTORDATA_I32 = 3 , ARM_VECTORDATA_I64 = 4 , ARM_VECTORDATA_S8 = 5 , ARM_VECTORDATA_S16 = 6 , ARM_VECTORDATA_S32 = 7 , ARM_VECTORDATA_S64 = 8 , ARM_VECTORDATA_U8 = 9 , ARM_VECTORDATA_U16 = 10 , ARM_VECTORDATA_U32 = 11 , ARM_VECTORDATA_U64 = 12 , ARM_VECTORDATA_P8 = 13 , ARM_VECTORDATA_F16 = 14 , ARM_VECTORDATA_F32 = 15 , ARM_VECTORDATA_F64 = 16 , ARM_VECTORDATA_F16F64 = 17 , ARM_VECTORDATA_F64F16 = 18 , ARM_VECTORDATA_F32F16 = 19 , ARM_VECTORDATA_F16F32 = 20 , ARM_VECTORDATA_F64F32 = 21 , ARM_VECTORDATA_F32F64 = 22 , ARM_VECTORDATA_S32F32 = 23 , ARM_VECTORDATA_U32F32 = 24 , ARM_VECTORDATA_F32S32 = 25 , ARM_VECTORDATA_F32U32 = 26 , ARM_VECTORDATA_F64S16 = 27 , ARM_VECTORDATA_F32S16 = 28 , ARM_VECTORDATA_F64S32 = 29 , ARM_VECTORDATA_S16F64 = 30 , ARM_VECTORDATA_S16F32 = 31 , ARM_VECTORDATA_S32F64 = 32 , ARM_VECTORDATA_U16F64 = 33 , ARM_VECTORDATA_U16F32 = 34 , ARM_VECTORDATA_U32F64 = 35 , ARM_VECTORDATA_F64U16 = 36 , ARM_VECTORDATA_F32U16 = 37 , ARM_VECTORDATA_F64U32 = 38 , ARM_VECTORDATA_F16U16 = 39 , ARM_VECTORDATA_U16F16 = 40 , ARM_VECTORDATA_F16U32 = 41 , ARM_VECTORDATA_U32F16 = 42 , } impl arm_reg { pub const ARM_REG_R13 : arm_reg = arm_reg :: ARM_REG_SP ; } impl arm_reg { pub const ARM_REG_R14 : arm_reg = arm_reg :: ARM_REG_LR ; } impl arm_reg { pub const ARM_REG_R15 : arm_reg = arm_reg :: ARM_REG_PC ; } impl arm_reg { pub const ARM_REG_SB : arm_reg = arm_reg :: ARM_REG_R9 ; } impl arm_reg { pub const ARM_REG_SL : arm_reg = arm_reg :: ARM_REG_R10 ; } impl arm_reg { pub const ARM_REG_FP : arm_reg = arm_reg :: ARM_REG_R11 ; } impl arm_reg { pub const ARM_REG_IP : arm_reg = arm_reg :: ARM_REG_R12 ; } # [repr (u32)] # [doc = " ARM registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_reg { ARM_REG_INVALID = 0 , ARM_REG_APSR = 1 , ARM_REG_APSR_NZCV = 2 , ARM_REG_CPSR = 3 , ARM_REG_FPEXC = 4 , ARM_REG_FPINST = 5 , ARM_REG_FPSCR = 6 , ARM_REG_FPSCR_NZCV = 7 , ARM_REG_FPSID = 8 , ARM_REG_ITSTATE = 9 , ARM_REG_LR = 10 , ARM_REG_PC = 11 , ARM_REG_SP = 12 , ARM_REG_SPSR = 13 , ARM_REG_D0 = 14 , ARM_REG_D1 = 15 , ARM_REG_D2 = 16 , ARM_REG_D3 = 17 , ARM_REG_D4 = 18 , ARM_REG_D5 = 19 , ARM_REG_D6 = 20 , ARM_REG_D7 = 21 , ARM_REG_D8 = 22 , ARM_REG_D9 = 23 , ARM_REG_D10 = 24 , ARM_REG_D11 = 25 , ARM_REG_D12 = 26 , ARM_REG_D13 = 27 , ARM_REG_D14 = 28 , ARM_REG_D15 = 29 , ARM_REG_D16 = 30 , ARM_REG_D17 = 31 , ARM_REG_D18 = 32 , ARM_REG_D19 = 33 , ARM_REG_D20 = 34 , ARM_REG_D21 = 35 , ARM_REG_D22 = 36 , ARM_REG_D23 = 37 , ARM_REG_D24 = 38 , ARM_REG_D25 = 39 , ARM_REG_D26 = 40 , ARM_REG_D27 = 41 , ARM_REG_D28 = 42 , ARM_REG_D29 = 43 , ARM_REG_D30 = 44 , ARM_REG_D31 = 45 , ARM_REG_FPINST2 = 46 , ARM_REG_MVFR0 = 47 , ARM_REG_MVFR1 = 48 , ARM_REG_MVFR2 = 49 , ARM_REG_Q0 = 50 , ARM_REG_Q1 = 51 , ARM_REG_Q2 = 52 , ARM_REG_Q3 = 53 , ARM_REG_Q4 = 54 , ARM_REG_Q5 = 55 , ARM_REG_Q6 = 56 , ARM_REG_Q7 = 57 , ARM_REG_Q8 = 58 , ARM_REG_Q9 = 59 , ARM_REG_Q10 = 60 , ARM_REG_Q11 = 61 , ARM_REG_Q12 = 62 , ARM_REG_Q13 = 63 , ARM_REG_Q14 = 64 , ARM_REG_Q15 = 65 , ARM_REG_R0 = 66 , ARM_REG_R1 = 67 , ARM_REG_R2 = 68 , ARM_REG_R3 = 69 , ARM_REG_R4 = 70 , ARM_REG_R5 = 71 , ARM_REG_R6 = 72 , ARM_REG_R7 = 73 , ARM_REG_R8 = 74 , ARM_REG_R9 = 75 , ARM_REG_R10 = 76 , ARM_REG_R11 = 77 , ARM_REG_R12 = 78 , ARM_REG_S0 = 79 , ARM_REG_S1 = 80 , ARM_REG_S2 = 81 , ARM_REG_S3 = 82 , ARM_REG_S4 = 83 , ARM_REG_S5 = 84 , ARM_REG_S6 = 85 , ARM_REG_S7 = 86 , ARM_REG_S8 = 87 , ARM_REG_S9 = 88 , ARM_REG_S10 = 89 , ARM_REG_S11 = 90 , ARM_REG_S12 = 91 , ARM_REG_S13 = 92 , ARM_REG_S14 = 93 , ARM_REG_S15 = 94 , ARM_REG_S16 = 95 , ARM_REG_S17 = 96 , ARM_REG_S18 = 97 , ARM_REG_S19 = 98 , ARM_REG_S20 = 99 , ARM_REG_S21 = 100 , ARM_REG_S22 = 101 , ARM_REG_S23 = 102 , ARM_REG_S24 = 103 , ARM_REG_S25 = 104 , ARM_REG_S26 = 105 , ARM_REG_S27 = 106 , ARM_REG_S28 = 107 , ARM_REG_S29 = 108 , ARM_REG_S30 = 109 , ARM_REG_S31 = 110 , ARM_REG_ENDING = 111 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm_op_mem { # [doc = "< base register"] pub base : arm_reg , # [doc = "< index register"] pub index : arm_reg , # [doc = "< scale for index register (can be 1, or -1)"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_int , # [doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"] pub lshift : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm_op_mem"] [:: std :: mem :: size_of :: < arm_op_mem > () - 20usize] ; ["Alignment of arm_op_mem"] [:: std :: mem :: align_of :: < arm_op_mem > () - 4usize] ; ["Offset of field: arm_op_mem::base"] [:: std :: mem :: offset_of ! (arm_op_mem , base) - 0usize] ; ["Offset of field: arm_op_mem::index"] [:: std :: mem :: offset_of ! (arm_op_mem , index) - 4usize] ; ["Offset of field: arm_op_mem::scale"] [:: std :: mem :: offset_of ! (arm_op_mem , scale) - 8usize] ; ["Offset of field: arm_op_mem::disp"] [:: std :: mem :: offset_of ! (arm_op_mem , disp) - 12usize] ; ["Offset of field: arm_op_mem::lshift"] [:: std :: mem :: offset_of ! (arm_op_mem , lshift) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm_op { # [doc = "< Vector Index for some vector operands (or -1 if irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , pub shift : cs_arm_op__bindgen_ty_1 , # [doc = "< operand type"] pub type_ : arm_op_type , pub __bindgen_anon_1 : cs_arm_op__bindgen_ty_2 , # [doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."] pub subtracted : bool , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"] pub neon_lane : i8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm_op__bindgen_ty_1 { pub type_ : arm_shifter , pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm_op__bindgen_ty_2 { # [doc = "< register value for REG/SYSREG operand"] pub reg : :: std :: os :: raw :: c_int , # [doc = "< immediate value for C-IMM, P-IMM or IMM operand"] pub imm : i32 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm_op_mem , # [doc = "< SETEND instruction's operand type"] pub setend : arm_setend_type , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm_op__bindgen_ty_2 > () - 24usize] ; ["Alignment of cs_arm_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm_op__bindgen_ty_2::setend"] [:: std :: mem :: offset_of ! (cs_arm_op__bindgen_ty_2 , setend) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm_op"] [:: std :: mem :: size_of :: < cs_arm_op > () - 48usize] ; ["Alignment of cs_arm_op"] [:: std :: mem :: align_of :: < cs_arm_op > () - 8usize] ; ["Offset of field: cs_arm_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm_op , vector_index) - 0usize] ; ["Offset of field: cs_arm_op::shift"] [:: std :: mem :: offset_of ! (cs_arm_op , shift) - 4usize] ; ["Offset of field: cs_arm_op::type_"] [:: std :: mem :: offset_of ! (cs_arm_op , type_) - 12usize] ; ["Offset of field: cs_arm_op::subtracted"] [:: std :: mem :: offset_of ! (cs_arm_op , subtracted) - 40usize] ; ["Offset of field: cs_arm_op::access"] [:: std :: mem :: offset_of ! (cs_arm_op , access) - 41usize] ; ["Offset of field: cs_arm_op::neon_lane"] [:: std :: mem :: offset_of ! (cs_arm_op , neon_lane) - 42usize] ; } ; impl :: std :: fmt :: Debug for cs_arm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm { # [doc = "< User-mode registers to be loaded (for LDM/STM instructions)"] pub usermode : bool , # [doc = "< Scalar size for vector instructions"] pub vector_size : :: std :: os :: raw :: c_int , # [doc = "< Data type for elements of vector instructions"] pub vector_data : arm_vectordata_type , # [doc = "< CPS mode for CPS instruction"] pub cps_mode : arm_cpsmode_type , # [doc = "< CPS mode for CPS instruction"] pub cps_flag : arm_cpsflag_type , # [doc = "< conditional code for this insn"] pub cc : arm_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn write-back?"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = "< Option for some memory barrier instructions"] pub mem_barrier : arm_mem_barrier , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm_op ; 36usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm"] [:: std :: mem :: size_of :: < cs_arm > () - 1768usize] ; ["Alignment of cs_arm"] [:: std :: mem :: align_of :: < cs_arm > () - 8usize] ; ["Offset of field: cs_arm::usermode"] [:: std :: mem :: offset_of ! (cs_arm , usermode) - 0usize] ; ["Offset of field: cs_arm::vector_size"] [:: std :: mem :: offset_of ! (cs_arm , vector_size) - 4usize] ; ["Offset of field: cs_arm::vector_data"] [:: std :: mem :: offset_of ! (cs_arm , vector_data) - 8usize] ; ["Offset of field: cs_arm::cps_mode"] [:: std :: mem :: offset_of ! (cs_arm , cps_mode) - 12usize] ; ["Offset of field: cs_arm::cps_flag"] [:: std :: mem :: offset_of ! (cs_arm , cps_flag) - 16usize] ; ["Offset of field: cs_arm::cc"] [:: std :: mem :: offset_of ! (cs_arm , cc) - 20usize] ; ["Offset of field: cs_arm::update_flags"] [:: std :: mem :: offset_of ! (cs_arm , update_flags) - 24usize] ; ["Offset of field: cs_arm::writeback"] [:: std :: mem :: offset_of ! (cs_arm , writeback) - 25usize] ; ["Offset of field: cs_arm::post_index"] [:: std :: mem :: offset_of ! (cs_arm , post_index) - 26usize] ; ["Offset of field: cs_arm::mem_barrier"] [:: std :: mem :: offset_of ! (cs_arm , mem_barrier) - 28usize] ; ["Offset of field: cs_arm::op_count"] [:: std :: mem :: offset_of ! (cs_arm , op_count) - 32usize] ; ["Offset of field: cs_arm::operands"] [:: std :: mem :: offset_of ! (cs_arm , operands) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_arm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . post_index , self . mem_barrier , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn { ARM_INS_INVALID = 0 , ARM_INS_ADC = 1 , ARM_INS_ADD = 2 , ARM_INS_ADDW = 3 , ARM_INS_ADR = 4 , ARM_INS_AESD = 5 , ARM_INS_AESE = 6 , ARM_INS_AESIMC = 7 , ARM_INS_AESMC = 8 , ARM_INS_AND = 9 , ARM_INS_ASR = 10 , ARM_INS_B = 11 , ARM_INS_BFC = 12 , ARM_INS_BFI = 13 , ARM_INS_BIC = 14 , ARM_INS_BKPT = 15 , ARM_INS_BL = 16 , ARM_INS_BLX = 17 , ARM_INS_BLXNS = 18 , ARM_INS_BX = 19 , ARM_INS_BXJ = 20 , ARM_INS_BXNS = 21 , ARM_INS_CBNZ = 22 , ARM_INS_CBZ = 23 , ARM_INS_CDP = 24 , ARM_INS_CDP2 = 25 , ARM_INS_CLREX = 26 , ARM_INS_CLZ = 27 , ARM_INS_CMN = 28 , ARM_INS_CMP = 29 , ARM_INS_CPS = 30 , ARM_INS_CRC32B = 31 , ARM_INS_CRC32CB = 32 , ARM_INS_CRC32CH = 33 , ARM_INS_CRC32CW = 34 , ARM_INS_CRC32H = 35 , ARM_INS_CRC32W = 36 , ARM_INS_CSDB = 37 , ARM_INS_DBG = 38 , ARM_INS_DCPS1 = 39 , ARM_INS_DCPS2 = 40 , ARM_INS_DCPS3 = 41 , ARM_INS_DFB = 42 , ARM_INS_DMB = 43 , ARM_INS_DSB = 44 , ARM_INS_EOR = 45 , ARM_INS_ERET = 46 , ARM_INS_ESB = 47 , ARM_INS_FADDD = 48 , ARM_INS_FADDS = 49 , ARM_INS_FCMPZD = 50 , ARM_INS_FCMPZS = 51 , ARM_INS_FCONSTD = 52 , ARM_INS_FCONSTS = 53 , ARM_INS_FLDMDBX = 54 , ARM_INS_FLDMIAX = 55 , ARM_INS_FMDHR = 56 , ARM_INS_FMDLR = 57 , ARM_INS_FMSTAT = 58 , ARM_INS_FSTMDBX = 59 , ARM_INS_FSTMIAX = 60 , ARM_INS_FSUBD = 61 , ARM_INS_FSUBS = 62 , ARM_INS_HINT = 63 , ARM_INS_HLT = 64 , ARM_INS_HVC = 65 , ARM_INS_ISB = 66 , ARM_INS_IT = 67 , ARM_INS_LDA = 68 , ARM_INS_LDAB = 69 , ARM_INS_LDAEX = 70 , ARM_INS_LDAEXB = 71 , ARM_INS_LDAEXD = 72 , ARM_INS_LDAEXH = 73 , ARM_INS_LDAH = 74 , ARM_INS_LDC = 75 , ARM_INS_LDC2 = 76 , ARM_INS_LDC2L = 77 , ARM_INS_LDCL = 78 , ARM_INS_LDM = 79 , ARM_INS_LDMDA = 80 , ARM_INS_LDMDB = 81 , ARM_INS_LDMIB = 82 , ARM_INS_LDR = 83 , ARM_INS_LDRB = 84 , ARM_INS_LDRBT = 85 , ARM_INS_LDRD = 86 , ARM_INS_LDREX = 87 , ARM_INS_LDREXB = 88 , ARM_INS_LDREXD = 89 , ARM_INS_LDREXH = 90 , ARM_INS_LDRH = 91 , ARM_INS_LDRHT = 92 , ARM_INS_LDRSB = 93 , ARM_INS_LDRSBT = 94 , ARM_INS_LDRSH = 95 , ARM_INS_LDRSHT = 96 , ARM_INS_LDRT = 97 , ARM_INS_LSL = 98 , ARM_INS_LSR = 99 , ARM_INS_MCR = 100 , ARM_INS_MCR2 = 101 , ARM_INS_MCRR = 102 , ARM_INS_MCRR2 = 103 , ARM_INS_MLA = 104 , ARM_INS_MLS = 105 , ARM_INS_MOV = 106 , ARM_INS_MOVS = 107 , ARM_INS_MOVT = 108 , ARM_INS_MOVW = 109 , ARM_INS_MRC = 110 , ARM_INS_MRC2 = 111 , ARM_INS_MRRC = 112 , ARM_INS_MRRC2 = 113 , ARM_INS_MRS = 114 , ARM_INS_MSR = 115 , ARM_INS_MUL = 116 , ARM_INS_MVN = 117 , ARM_INS_NEG = 118 , ARM_INS_NOP = 119 , ARM_INS_ORN = 120 , ARM_INS_ORR = 121 , ARM_INS_PKHBT = 122 , ARM_INS_PKHTB = 123 , ARM_INS_PLD = 124 , ARM_INS_PLDW = 125 , ARM_INS_PLI = 126 , ARM_INS_POP = 127 , ARM_INS_PUSH = 128 , ARM_INS_QADD = 129 , ARM_INS_QADD16 = 130 , ARM_INS_QADD8 = 131 , ARM_INS_QASX = 132 , ARM_INS_QDADD = 133 , ARM_INS_QDSUB = 134 , ARM_INS_QSAX = 135 , ARM_INS_QSUB = 136 , ARM_INS_QSUB16 = 137 , ARM_INS_QSUB8 = 138 , ARM_INS_RBIT = 139 , ARM_INS_REV = 140 , ARM_INS_REV16 = 141 , ARM_INS_REVSH = 142 , ARM_INS_RFEDA = 143 , ARM_INS_RFEDB = 144 , ARM_INS_RFEIA = 145 , ARM_INS_RFEIB = 146 , ARM_INS_ROR = 147 , ARM_INS_RRX = 148 , ARM_INS_RSB = 149 , ARM_INS_RSC = 150 , ARM_INS_SADD16 = 151 , ARM_INS_SADD8 = 152 , ARM_INS_SASX = 153 , ARM_INS_SBC = 154 , ARM_INS_SBFX = 155 , ARM_INS_SDIV = 156 , ARM_INS_SEL = 157 , ARM_INS_SETEND = 158 , ARM_INS_SETPAN = 159 , ARM_INS_SEV = 160 , ARM_INS_SEVL = 161 , ARM_INS_SG = 162 , ARM_INS_SHA1C = 163 , ARM_INS_SHA1H = 164 , ARM_INS_SHA1M = 165 , ARM_INS_SHA1P = 166 , ARM_INS_SHA1SU0 = 167 , ARM_INS_SHA1SU1 = 168 , ARM_INS_SHA256H = 169 , ARM_INS_SHA256H2 = 170 , ARM_INS_SHA256SU0 = 171 , ARM_INS_SHA256SU1 = 172 , ARM_INS_SHADD16 = 173 , ARM_INS_SHADD8 = 174 , ARM_INS_SHASX = 175 , ARM_INS_SHSAX = 176 , ARM_INS_SHSUB16 = 177 , ARM_INS_SHSUB8 = 178 , ARM_INS_SMC = 179 , ARM_INS_SMLABB = 180 , ARM_INS_SMLABT = 181 , ARM_INS_SMLAD = 182 , ARM_INS_SMLADX = 183 , ARM_INS_SMLAL = 184 , ARM_INS_SMLALBB = 185 , ARM_INS_SMLALBT = 186 , ARM_INS_SMLALD = 187 , ARM_INS_SMLALDX = 188 , ARM_INS_SMLALTB = 189 , ARM_INS_SMLALTT = 190 , ARM_INS_SMLATB = 191 , ARM_INS_SMLATT = 192 , ARM_INS_SMLAWB = 193 , ARM_INS_SMLAWT = 194 , ARM_INS_SMLSD = 195 , ARM_INS_SMLSDX = 196 , ARM_INS_SMLSLD = 197 , ARM_INS_SMLSLDX = 198 , ARM_INS_SMMLA = 199 , ARM_INS_SMMLAR = 200 , ARM_INS_SMMLS = 201 , ARM_INS_SMMLSR = 202 , ARM_INS_SMMUL = 203 , ARM_INS_SMMULR = 204 , ARM_INS_SMUAD = 205 , ARM_INS_SMUADX = 206 , ARM_INS_SMULBB = 207 , ARM_INS_SMULBT = 208 , ARM_INS_SMULL = 209 , ARM_INS_SMULTB = 210 , ARM_INS_SMULTT = 211 , ARM_INS_SMULWB = 212 , ARM_INS_SMULWT = 213 , ARM_INS_SMUSD = 214 , ARM_INS_SMUSDX = 215 , ARM_INS_SRSDA = 216 , ARM_INS_SRSDB = 217 , ARM_INS_SRSIA = 218 , ARM_INS_SRSIB = 219 , ARM_INS_SSAT = 220 , ARM_INS_SSAT16 = 221 , ARM_INS_SSAX = 222 , ARM_INS_SSUB16 = 223 , ARM_INS_SSUB8 = 224 , ARM_INS_STC = 225 , ARM_INS_STC2 = 226 , ARM_INS_STC2L = 227 , ARM_INS_STCL = 228 , ARM_INS_STL = 229 , ARM_INS_STLB = 230 , ARM_INS_STLEX = 231 , ARM_INS_STLEXB = 232 , ARM_INS_STLEXD = 233 , ARM_INS_STLEXH = 234 , ARM_INS_STLH = 235 , ARM_INS_STM = 236 , ARM_INS_STMDA = 237 , ARM_INS_STMDB = 238 , ARM_INS_STMIB = 239 , ARM_INS_STR = 240 , ARM_INS_STRB = 241 , ARM_INS_STRBT = 242 , ARM_INS_STRD = 243 , ARM_INS_STREX = 244 , ARM_INS_STREXB = 245 , ARM_INS_STREXD = 246 , ARM_INS_STREXH = 247 , ARM_INS_STRH = 248 , ARM_INS_STRHT = 249 , ARM_INS_STRT = 250 , ARM_INS_SUB = 251 , ARM_INS_SUBS = 252 , ARM_INS_SUBW = 253 , ARM_INS_SVC = 254 , ARM_INS_SWP = 255 , ARM_INS_SWPB = 256 , ARM_INS_SXTAB = 257 , ARM_INS_SXTAB16 = 258 , ARM_INS_SXTAH = 259 , ARM_INS_SXTB = 260 , ARM_INS_SXTB16 = 261 , ARM_INS_SXTH = 262 , ARM_INS_TBB = 263 , ARM_INS_TBH = 264 , ARM_INS_TEQ = 265 , ARM_INS_TRAP = 266 , ARM_INS_TSB = 267 , ARM_INS_TST = 268 , ARM_INS_TT = 269 , ARM_INS_TTA = 270 , ARM_INS_TTAT = 271 , ARM_INS_TTT = 272 , ARM_INS_UADD16 = 273 , ARM_INS_UADD8 = 274 , ARM_INS_UASX = 275 , ARM_INS_UBFX = 276 , ARM_INS_UDF = 277 , ARM_INS_UDIV = 278 , ARM_INS_UHADD16 = 279 , ARM_INS_UHADD8 = 280 , ARM_INS_UHASX = 281 , ARM_INS_UHSAX = 282 , ARM_INS_UHSUB16 = 283 , ARM_INS_UHSUB8 = 284 , ARM_INS_UMAAL = 285 , ARM_INS_UMLAL = 286 , ARM_INS_UMULL = 287 , ARM_INS_UQADD16 = 288 , ARM_INS_UQADD8 = 289 , ARM_INS_UQASX = 290 , ARM_INS_UQSAX = 291 , ARM_INS_UQSUB16 = 292 , ARM_INS_UQSUB8 = 293 , ARM_INS_USAD8 = 294 , ARM_INS_USADA8 = 295 , ARM_INS_USAT = 296 , ARM_INS_USAT16 = 297 , ARM_INS_USAX = 298 , ARM_INS_USUB16 = 299 , ARM_INS_USUB8 = 300 , ARM_INS_UXTAB = 301 , ARM_INS_UXTAB16 = 302 , ARM_INS_UXTAH = 303 , ARM_INS_UXTB = 304 , ARM_INS_UXTB16 = 305 , ARM_INS_UXTH = 306 , ARM_INS_VABA = 307 , ARM_INS_VABAL = 308 , ARM_INS_VABD = 309 , ARM_INS_VABDL = 310 , ARM_INS_VABS = 311 , ARM_INS_VACGE = 312 , ARM_INS_VACGT = 313 , ARM_INS_VACLE = 314 , ARM_INS_VACLT = 315 , ARM_INS_VADD = 316 , ARM_INS_VADDHN = 317 , ARM_INS_VADDL = 318 , ARM_INS_VADDW = 319 , ARM_INS_VAND = 320 , ARM_INS_VBIC = 321 , ARM_INS_VBIF = 322 , ARM_INS_VBIT = 323 , ARM_INS_VBSL = 324 , ARM_INS_VCADD = 325 , ARM_INS_VCEQ = 326 , ARM_INS_VCGE = 327 , ARM_INS_VCGT = 328 , ARM_INS_VCLE = 329 , ARM_INS_VCLS = 330 , ARM_INS_VCLT = 331 , ARM_INS_VCLZ = 332 , ARM_INS_VCMLA = 333 , ARM_INS_VCMP = 334 , ARM_INS_VCMPE = 335 , ARM_INS_VCNT = 336 , ARM_INS_VCVT = 337 , ARM_INS_VCVTA = 338 , ARM_INS_VCVTB = 339 , ARM_INS_VCVTM = 340 , ARM_INS_VCVTN = 341 , ARM_INS_VCVTP = 342 , ARM_INS_VCVTR = 343 , ARM_INS_VCVTT = 344 , ARM_INS_VDIV = 345 , ARM_INS_VDUP = 346 , ARM_INS_VEOR = 347 , ARM_INS_VEXT = 348 , ARM_INS_VFMA = 349 , ARM_INS_VFMS = 350 , ARM_INS_VFNMA = 351 , ARM_INS_VFNMS = 352 , ARM_INS_VHADD = 353 , ARM_INS_VHSUB = 354 , ARM_INS_VINS = 355 , ARM_INS_VJCVT = 356 , ARM_INS_VLD1 = 357 , ARM_INS_VLD2 = 358 , ARM_INS_VLD3 = 359 , ARM_INS_VLD4 = 360 , ARM_INS_VLDMDB = 361 , ARM_INS_VLDMIA = 362 , ARM_INS_VLDR = 363 , ARM_INS_VLLDM = 364 , ARM_INS_VLSTM = 365 , ARM_INS_VMAX = 366 , ARM_INS_VMAXNM = 367 , ARM_INS_VMIN = 368 , ARM_INS_VMINNM = 369 , ARM_INS_VMLA = 370 , ARM_INS_VMLAL = 371 , ARM_INS_VMLS = 372 , ARM_INS_VMLSL = 373 , ARM_INS_VMOV = 374 , ARM_INS_VMOVL = 375 , ARM_INS_VMOVN = 376 , ARM_INS_VMOVX = 377 , ARM_INS_VMRS = 378 , ARM_INS_VMSR = 379 , ARM_INS_VMUL = 380 , ARM_INS_VMULL = 381 , ARM_INS_VMVN = 382 , ARM_INS_VNEG = 383 , ARM_INS_VNMLA = 384 , ARM_INS_VNMLS = 385 , ARM_INS_VNMUL = 386 , ARM_INS_VORN = 387 , ARM_INS_VORR = 388 , ARM_INS_VPADAL = 389 , ARM_INS_VPADD = 390 , ARM_INS_VPADDL = 391 , ARM_INS_VPMAX = 392 , ARM_INS_VPMIN = 393 , ARM_INS_VPOP = 394 , ARM_INS_VPUSH = 395 , ARM_INS_VQABS = 396 , ARM_INS_VQADD = 397 , ARM_INS_VQDMLAL = 398 , ARM_INS_VQDMLSL = 399 , ARM_INS_VQDMULH = 400 , ARM_INS_VQDMULL = 401 , ARM_INS_VQMOVN = 402 , ARM_INS_VQMOVUN = 403 , ARM_INS_VQNEG = 404 , ARM_INS_VQRDMLAH = 405 , ARM_INS_VQRDMLSH = 406 , ARM_INS_VQRDMULH = 407 , ARM_INS_VQRSHL = 408 , ARM_INS_VQRSHRN = 409 , ARM_INS_VQRSHRUN = 410 , ARM_INS_VQSHL = 411 , ARM_INS_VQSHLU = 412 , ARM_INS_VQSHRN = 413 , ARM_INS_VQSHRUN = 414 , ARM_INS_VQSUB = 415 , ARM_INS_VRADDHN = 416 , ARM_INS_VRECPE = 417 , ARM_INS_VRECPS = 418 , ARM_INS_VREV16 = 419 , ARM_INS_VREV32 = 420 , ARM_INS_VREV64 = 421 , ARM_INS_VRHADD = 422 , ARM_INS_VRINTA = 423 , ARM_INS_VRINTM = 424 , ARM_INS_VRINTN = 425 , ARM_INS_VRINTP = 426 , ARM_INS_VRINTR = 427 , ARM_INS_VRINTX = 428 , ARM_INS_VRINTZ = 429 , ARM_INS_VRSHL = 430 , ARM_INS_VRSHR = 431 , ARM_INS_VRSHRN = 432 , ARM_INS_VRSQRTE = 433 , ARM_INS_VRSQRTS = 434 , ARM_INS_VRSRA = 435 , ARM_INS_VRSUBHN = 436 , ARM_INS_VSDOT = 437 , ARM_INS_VSELEQ = 438 , ARM_INS_VSELGE = 439 , ARM_INS_VSELGT = 440 , ARM_INS_VSELVS = 441 , ARM_INS_VSHL = 442 , ARM_INS_VSHLL = 443 , ARM_INS_VSHR = 444 , ARM_INS_VSHRN = 445 , ARM_INS_VSLI = 446 , ARM_INS_VSQRT = 447 , ARM_INS_VSRA = 448 , ARM_INS_VSRI = 449 , ARM_INS_VST1 = 450 , ARM_INS_VST2 = 451 , ARM_INS_VST3 = 452 , ARM_INS_VST4 = 453 , ARM_INS_VSTMDB = 454 , ARM_INS_VSTMIA = 455 , ARM_INS_VSTR = 456 , ARM_INS_VSUB = 457 , ARM_INS_VSUBHN = 458 , ARM_INS_VSUBL = 459 , ARM_INS_VSUBW = 460 , ARM_INS_VSWP = 461 , ARM_INS_VTBL = 462 , ARM_INS_VTBX = 463 , ARM_INS_VTRN = 464 , ARM_INS_VTST = 465 , ARM_INS_VUDOT = 466 , ARM_INS_VUZP = 467 , ARM_INS_VZIP = 468 , ARM_INS_WFE = 469 , ARM_INS_WFI = 470 , ARM_INS_YIELD = 471 , ARM_INS_ENDING = 472 , } # [repr (u32)] # [doc = " Group of ARM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] ARM_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] ARM_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM_GRP_BRANCH_RELATIVE = 7 , ARM_GRP_CRYPTO = 128 , ARM_GRP_DATABARRIER = 129 , ARM_GRP_DIVIDE = 130 , ARM_GRP_FPARMV8 = 131 , ARM_GRP_MULTPRO = 132 , ARM_GRP_NEON = 133 , ARM_GRP_T2EXTRACTPACK = 134 , ARM_GRP_THUMB2DSP = 135 , ARM_GRP_TRUSTZONE = 136 , ARM_GRP_V4T = 137 , ARM_GRP_V5T = 138 , ARM_GRP_V5TE = 139 , ARM_GRP_V6 = 140 , ARM_GRP_V6T2 = 141 , ARM_GRP_V7 = 142 , ARM_GRP_V8 = 143 , ARM_GRP_VFP2 = 144 , ARM_GRP_VFP3 = 145 , ARM_GRP_VFP4 = 146 , ARM_GRP_ARM = 147 , ARM_GRP_MCLASS = 148 , ARM_GRP_NOTMCLASS = 149 , ARM_GRP_THUMB = 150 , ARM_GRP_THUMB1ONLY = 151 , ARM_GRP_THUMB2 = 152 , ARM_GRP_PREV8 = 153 , ARM_GRP_FPVMLX = 154 , ARM_GRP_MULOPS = 155 , ARM_GRP_CRC = 156 , ARM_GRP_DPVFP = 157 , ARM_GRP_V6M = 158 , ARM_GRP_VIRTUALIZATION = 159 , ARM_GRP_ENDING = 160 , } # [repr (u32)] # [doc = " ARM64 shift type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_shifter { ARM64_SFT_INVALID = 0 , ARM64_SFT_LSL = 1 , ARM64_SFT_MSL = 2 , ARM64_SFT_LSR = 3 , ARM64_SFT_ASR = 4 , ARM64_SFT_ROR = 5 , } # [repr (u32)] # [doc = " ARM64 extender type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_extender { ARM64_EXT_INVALID = 0 , ARM64_EXT_UXTB = 1 , ARM64_EXT_UXTH = 2 , ARM64_EXT_UXTW = 3 , ARM64_EXT_UXTX = 4 , ARM64_EXT_SXTB = 5 , ARM64_EXT_SXTH = 6 , ARM64_EXT_SXTW = 7 , ARM64_EXT_SXTX = 8 , } # [repr (u32)] # [doc = " ARM64 condition code"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_cc { ARM64_CC_INVALID = 0 , # [doc = "< Equal"] ARM64_CC_EQ = 1 , # [doc = "< Not equal:                 Not equal, or unordered"] ARM64_CC_NE = 2 , # [doc = "< Unsigned higher or same:   >, ==, or unordered"] ARM64_CC_HS = 3 , # [doc = "< Unsigned lower or same:    Less than"] ARM64_CC_LO = 4 , # [doc = "< Minus, negative:           Less than"] ARM64_CC_MI = 5 , # [doc = "< Plus, positive or zero:    >, ==, or unordered"] ARM64_CC_PL = 6 , # [doc = "< Overflow:                  Unordered"] ARM64_CC_VS = 7 , # [doc = "< No overflow:               Ordered"] ARM64_CC_VC = 8 , # [doc = "< Unsigned higher:           Greater than, or unordered"] ARM64_CC_HI = 9 , # [doc = "< Unsigned lower or same:    Less than or equal"] ARM64_CC_LS = 10 , # [doc = "< Greater than or equal:     Greater than or equal"] ARM64_CC_GE = 11 , # [doc = "< Less than:                 Less than, or unordered"] ARM64_CC_LT = 12 , # [doc = "< Signed greater than:       Greater than"] ARM64_CC_GT = 13 , # [doc = "< Signed less than or equal: <, ==, or unordered"] ARM64_CC_LE = 14 , # [doc = "< Always (unconditional):    Always (unconditional)"] ARM64_CC_AL = 15 , # [doc = "< Always (unconditional):   Always (unconditional)"] ARM64_CC_NV = 16 , } impl arm64_sysreg { pub const ARM64_SYSREG_DBGDTRTX_EL0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_DBGDTRRX_EL0 ; } impl arm64_sysreg { pub const ARM64_SYSREG_TRCEXTINSELR0 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TRCEXTINSELR ; } impl arm64_sysreg { pub const ARM64_SYSREG_VSCTLR_EL2 : arm64_sysreg = arm64_sysreg :: ARM64_SYSREG_TTBR0_EL2 ; } # [repr (u32)] # [doc = " System registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sysreg { ARM64_SYSREG_INVALID = 0 , ARM64_SYSREG_ACCDATA_EL1 = 50821 , ARM64_SYSREG_ACTLR_EL1 = 49281 , ARM64_SYSREG_ACTLR_EL2 = 57473 , ARM64_SYSREG_ACTLR_EL3 = 61569 , ARM64_SYSREG_AFSR0_EL1 = 49800 , ARM64_SYSREG_AFSR0_EL12 = 60040 , ARM64_SYSREG_AFSR0_EL2 = 57992 , ARM64_SYSREG_AFSR0_EL3 = 62088 , ARM64_SYSREG_AFSR1_EL1 = 49801 , ARM64_SYSREG_AFSR1_EL12 = 60041 , ARM64_SYSREG_AFSR1_EL2 = 57993 , ARM64_SYSREG_AFSR1_EL3 = 62089 , ARM64_SYSREG_AIDR_EL1 = 51207 , ARM64_SYSREG_AMAIR_EL1 = 50456 , ARM64_SYSREG_AMAIR_EL12 = 60696 , ARM64_SYSREG_AMAIR_EL2 = 58648 , ARM64_SYSREG_AMAIR_EL3 = 62744 , ARM64_SYSREG_AMCFGR_EL0 = 56977 , ARM64_SYSREG_AMCGCR_EL0 = 56978 , ARM64_SYSREG_AMCNTENCLR0_EL0 = 56980 , ARM64_SYSREG_AMCNTENCLR1_EL0 = 56984 , ARM64_SYSREG_AMCNTENSET0_EL0 = 56981 , ARM64_SYSREG_AMCNTENSET1_EL0 = 56985 , ARM64_SYSREG_AMCR_EL0 = 56976 , ARM64_SYSREG_AMEVCNTR00_EL0 = 56992 , ARM64_SYSREG_AMEVCNTR01_EL0 = 56993 , ARM64_SYSREG_AMEVCNTR02_EL0 = 56994 , ARM64_SYSREG_AMEVCNTR03_EL0 = 56995 , ARM64_SYSREG_AMEVCNTR10_EL0 = 57056 , ARM64_SYSREG_AMEVCNTR110_EL0 = 57066 , ARM64_SYSREG_AMEVCNTR111_EL0 = 57067 , ARM64_SYSREG_AMEVCNTR112_EL0 = 57068 , ARM64_SYSREG_AMEVCNTR113_EL0 = 57069 , ARM64_SYSREG_AMEVCNTR114_EL0 = 57070 , ARM64_SYSREG_AMEVCNTR115_EL0 = 57071 , ARM64_SYSREG_AMEVCNTR11_EL0 = 57057 , ARM64_SYSREG_AMEVCNTR12_EL0 = 57058 , ARM64_SYSREG_AMEVCNTR13_EL0 = 57059 , ARM64_SYSREG_AMEVCNTR14_EL0 = 57060 , ARM64_SYSREG_AMEVCNTR15_EL0 = 57061 , ARM64_SYSREG_AMEVCNTR16_EL0 = 57062 , ARM64_SYSREG_AMEVCNTR17_EL0 = 57063 , ARM64_SYSREG_AMEVCNTR18_EL0 = 57064 , ARM64_SYSREG_AMEVCNTR19_EL0 = 57065 , ARM64_SYSREG_AMEVCNTVOFF00_EL2 = 59072 , ARM64_SYSREG_AMEVCNTVOFF010_EL2 = 59082 , ARM64_SYSREG_AMEVCNTVOFF011_EL2 = 59083 , ARM64_SYSREG_AMEVCNTVOFF012_EL2 = 59084 , ARM64_SYSREG_AMEVCNTVOFF013_EL2 = 59085 , ARM64_SYSREG_AMEVCNTVOFF014_EL2 = 59086 , ARM64_SYSREG_AMEVCNTVOFF015_EL2 = 59087 , ARM64_SYSREG_AMEVCNTVOFF01_EL2 = 59073 , ARM64_SYSREG_AMEVCNTVOFF02_EL2 = 59074 , ARM64_SYSREG_AMEVCNTVOFF03_EL2 = 59075 , ARM64_SYSREG_AMEVCNTVOFF04_EL2 = 59076 , ARM64_SYSREG_AMEVCNTVOFF05_EL2 = 59077 , ARM64_SYSREG_AMEVCNTVOFF06_EL2 = 59078 , ARM64_SYSREG_AMEVCNTVOFF07_EL2 = 59079 , ARM64_SYSREG_AMEVCNTVOFF08_EL2 = 59080 , ARM64_SYSREG_AMEVCNTVOFF09_EL2 = 59081 , ARM64_SYSREG_AMEVCNTVOFF10_EL2 = 59088 , ARM64_SYSREG_AMEVCNTVOFF110_EL2 = 59098 , ARM64_SYSREG_AMEVCNTVOFF111_EL2 = 59099 , ARM64_SYSREG_AMEVCNTVOFF112_EL2 = 59100 , ARM64_SYSREG_AMEVCNTVOFF113_EL2 = 59101 , ARM64_SYSREG_AMEVCNTVOFF114_EL2 = 59102 , ARM64_SYSREG_AMEVCNTVOFF115_EL2 = 59103 , ARM64_SYSREG_AMEVCNTVOFF11_EL2 = 59089 , ARM64_SYSREG_AMEVCNTVOFF12_EL2 = 59090 , ARM64_SYSREG_AMEVCNTVOFF13_EL2 = 59091 , ARM64_SYSREG_AMEVCNTVOFF14_EL2 = 59092 , ARM64_SYSREG_AMEVCNTVOFF15_EL2 = 59093 , ARM64_SYSREG_AMEVCNTVOFF16_EL2 = 59094 , ARM64_SYSREG_AMEVCNTVOFF17_EL2 = 59095 , ARM64_SYSREG_AMEVCNTVOFF18_EL2 = 59096 , ARM64_SYSREG_AMEVCNTVOFF19_EL2 = 59097 , ARM64_SYSREG_AMEVTYPER00_EL0 = 57008 , ARM64_SYSREG_AMEVTYPER01_EL0 = 57009 , ARM64_SYSREG_AMEVTYPER02_EL0 = 57010 , ARM64_SYSREG_AMEVTYPER03_EL0 = 57011 , ARM64_SYSREG_AMEVTYPER10_EL0 = 57072 , ARM64_SYSREG_AMEVTYPER110_EL0 = 57082 , ARM64_SYSREG_AMEVTYPER111_EL0 = 57083 , ARM64_SYSREG_AMEVTYPER112_EL0 = 57084 , ARM64_SYSREG_AMEVTYPER113_EL0 = 57085 , ARM64_SYSREG_AMEVTYPER114_EL0 = 57086 , ARM64_SYSREG_AMEVTYPER115_EL0 = 57087 , ARM64_SYSREG_AMEVTYPER11_EL0 = 57073 , ARM64_SYSREG_AMEVTYPER12_EL0 = 57074 , ARM64_SYSREG_AMEVTYPER13_EL0 = 57075 , ARM64_SYSREG_AMEVTYPER14_EL0 = 57076 , ARM64_SYSREG_AMEVTYPER15_EL0 = 57077 , ARM64_SYSREG_AMEVTYPER16_EL0 = 57078 , ARM64_SYSREG_AMEVTYPER17_EL0 = 57079 , ARM64_SYSREG_AMEVTYPER18_EL0 = 57080 , ARM64_SYSREG_AMEVTYPER19_EL0 = 57081 , ARM64_SYSREG_AMUSERENR_EL0 = 56979 , ARM64_SYSREG_APDAKEYHI_EL1 = 49425 , ARM64_SYSREG_APDAKEYLO_EL1 = 49424 , ARM64_SYSREG_APDBKEYHI_EL1 = 49427 , ARM64_SYSREG_APDBKEYLO_EL1 = 49426 , ARM64_SYSREG_APGAKEYHI_EL1 = 49433 , ARM64_SYSREG_APGAKEYLO_EL1 = 49432 , ARM64_SYSREG_APIAKEYHI_EL1 = 49417 , ARM64_SYSREG_APIAKEYLO_EL1 = 49416 , ARM64_SYSREG_APIBKEYHI_EL1 = 49419 , ARM64_SYSREG_APIBKEYLO_EL1 = 49418 , ARM64_SYSREG_BRBCR_EL1 = 35968 , ARM64_SYSREG_BRBCR_EL12 = 44160 , ARM64_SYSREG_BRBCR_EL2 = 42112 , ARM64_SYSREG_BRBFCR_EL1 = 35969 , ARM64_SYSREG_BRBIDR0_EL1 = 35984 , ARM64_SYSREG_BRBINF0_EL1 = 35840 , ARM64_SYSREG_BRBINF10_EL1 = 35920 , ARM64_SYSREG_BRBINF11_EL1 = 35928 , ARM64_SYSREG_BRBINF12_EL1 = 35936 , ARM64_SYSREG_BRBINF13_EL1 = 35944 , ARM64_SYSREG_BRBINF14_EL1 = 35952 , ARM64_SYSREG_BRBINF15_EL1 = 35960 , ARM64_SYSREG_BRBINF16_EL1 = 35844 , ARM64_SYSREG_BRBINF17_EL1 = 35852 , ARM64_SYSREG_BRBINF18_EL1 = 35860 , ARM64_SYSREG_BRBINF19_EL1 = 35868 , ARM64_SYSREG_BRBINF1_EL1 = 35848 , ARM64_SYSREG_BRBINF20_EL1 = 35876 , ARM64_SYSREG_BRBINF21_EL1 = 35884 , ARM64_SYSREG_BRBINF22_EL1 = 35892 , ARM64_SYSREG_BRBINF23_EL1 = 35900 , ARM64_SYSREG_BRBINF24_EL1 = 35908 , ARM64_SYSREG_BRBINF25_EL1 = 35916 , ARM64_SYSREG_BRBINF26_EL1 = 35924 , ARM64_SYSREG_BRBINF27_EL1 = 35932 , ARM64_SYSREG_BRBINF28_EL1 = 35940 , ARM64_SYSREG_BRBINF29_EL1 = 35948 , ARM64_SYSREG_BRBINF2_EL1 = 35856 , ARM64_SYSREG_BRBINF30_EL1 = 35956 , ARM64_SYSREG_BRBINF31_EL1 = 35964 , ARM64_SYSREG_BRBINF3_EL1 = 35864 , ARM64_SYSREG_BRBINF4_EL1 = 35872 , ARM64_SYSREG_BRBINF5_EL1 = 35880 , ARM64_SYSREG_BRBINF6_EL1 = 35888 , ARM64_SYSREG_BRBINF7_EL1 = 35896 , ARM64_SYSREG_BRBINF8_EL1 = 35904 , ARM64_SYSREG_BRBINF9_EL1 = 35912 , ARM64_SYSREG_BRBINFINJ_EL1 = 35976 , ARM64_SYSREG_BRBSRC0_EL1 = 35841 , ARM64_SYSREG_BRBSRC10_EL1 = 35921 , ARM64_SYSREG_BRBSRC11_EL1 = 35929 , ARM64_SYSREG_BRBSRC12_EL1 = 35937 , ARM64_SYSREG_BRBSRC13_EL1 = 35945 , ARM64_SYSREG_BRBSRC14_EL1 = 35953 , ARM64_SYSREG_BRBSRC15_EL1 = 35961 , ARM64_SYSREG_BRBSRC16_EL1 = 35845 , ARM64_SYSREG_BRBSRC17_EL1 = 35853 , ARM64_SYSREG_BRBSRC18_EL1 = 35861 , ARM64_SYSREG_BRBSRC19_EL1 = 35869 , ARM64_SYSREG_BRBSRC1_EL1 = 35849 , ARM64_SYSREG_BRBSRC20_EL1 = 35877 , ARM64_SYSREG_BRBSRC21_EL1 = 35885 , ARM64_SYSREG_BRBSRC22_EL1 = 35893 , ARM64_SYSREG_BRBSRC23_EL1 = 35901 , ARM64_SYSREG_BRBSRC24_EL1 = 35909 , ARM64_SYSREG_BRBSRC25_EL1 = 35917 , ARM64_SYSREG_BRBSRC26_EL1 = 35925 , ARM64_SYSREG_BRBSRC27_EL1 = 35933 , ARM64_SYSREG_BRBSRC28_EL1 = 35941 , ARM64_SYSREG_BRBSRC29_EL1 = 35949 , ARM64_SYSREG_BRBSRC2_EL1 = 35857 , ARM64_SYSREG_BRBSRC30_EL1 = 35957 , ARM64_SYSREG_BRBSRC31_EL1 = 35965 , ARM64_SYSREG_BRBSRC3_EL1 = 35865 , ARM64_SYSREG_BRBSRC4_EL1 = 35873 , ARM64_SYSREG_BRBSRC5_EL1 = 35881 , ARM64_SYSREG_BRBSRC6_EL1 = 35889 , ARM64_SYSREG_BRBSRC7_EL1 = 35897 , ARM64_SYSREG_BRBSRC8_EL1 = 35905 , ARM64_SYSREG_BRBSRC9_EL1 = 35913 , ARM64_SYSREG_BRBSRCINJ_EL1 = 35977 , ARM64_SYSREG_BRBTGT0_EL1 = 35842 , ARM64_SYSREG_BRBTGT10_EL1 = 35922 , ARM64_SYSREG_BRBTGT11_EL1 = 35930 , ARM64_SYSREG_BRBTGT12_EL1 = 35938 , ARM64_SYSREG_BRBTGT13_EL1 = 35946 , ARM64_SYSREG_BRBTGT14_EL1 = 35954 , ARM64_SYSREG_BRBTGT15_EL1 = 35962 , ARM64_SYSREG_BRBTGT16_EL1 = 35846 , ARM64_SYSREG_BRBTGT17_EL1 = 35854 , ARM64_SYSREG_BRBTGT18_EL1 = 35862 , ARM64_SYSREG_BRBTGT19_EL1 = 35870 , ARM64_SYSREG_BRBTGT1_EL1 = 35850 , ARM64_SYSREG_BRBTGT20_EL1 = 35878 , ARM64_SYSREG_BRBTGT21_EL1 = 35886 , ARM64_SYSREG_BRBTGT22_EL1 = 35894 , ARM64_SYSREG_BRBTGT23_EL1 = 35902 , ARM64_SYSREG_BRBTGT24_EL1 = 35910 , ARM64_SYSREG_BRBTGT25_EL1 = 35918 , ARM64_SYSREG_BRBTGT26_EL1 = 35926 , ARM64_SYSREG_BRBTGT27_EL1 = 35934 , ARM64_SYSREG_BRBTGT28_EL1 = 35942 , ARM64_SYSREG_BRBTGT29_EL1 = 35950 , ARM64_SYSREG_BRBTGT2_EL1 = 35858 , ARM64_SYSREG_BRBTGT30_EL1 = 35958 , ARM64_SYSREG_BRBTGT31_EL1 = 35966 , ARM64_SYSREG_BRBTGT3_EL1 = 35866 , ARM64_SYSREG_BRBTGT4_EL1 = 35874 , ARM64_SYSREG_BRBTGT5_EL1 = 35882 , ARM64_SYSREG_BRBTGT6_EL1 = 35890 , ARM64_SYSREG_BRBTGT7_EL1 = 35898 , ARM64_SYSREG_BRBTGT8_EL1 = 35906 , ARM64_SYSREG_BRBTGT9_EL1 = 35914 , ARM64_SYSREG_BRBTGTINJ_EL1 = 35978 , ARM64_SYSREG_BRBTS_EL1 = 35970 , ARM64_SYSREG_CCSIDR2_EL1 = 51202 , ARM64_SYSREG_CCSIDR_EL1 = 51200 , ARM64_SYSREG_CLIDR_EL1 = 51201 , ARM64_SYSREG_CNTFRQ_EL0 = 57088 , ARM64_SYSREG_CNTHCTL_EL2 = 59144 , ARM64_SYSREG_CNTHPS_CTL_EL2 = 59177 , ARM64_SYSREG_CNTHPS_CVAL_EL2 = 59178 , ARM64_SYSREG_CNTHPS_TVAL_EL2 = 59176 , ARM64_SYSREG_CNTHP_CTL_EL2 = 59153 , ARM64_SYSREG_CNTHP_CVAL_EL2 = 59154 , ARM64_SYSREG_CNTHP_TVAL_EL2 = 59152 , ARM64_SYSREG_CNTHVS_CTL_EL2 = 59169 , ARM64_SYSREG_CNTHVS_CVAL_EL2 = 59170 , ARM64_SYSREG_CNTHVS_TVAL_EL2 = 59168 , ARM64_SYSREG_CNTHV_CTL_EL2 = 59161 , ARM64_SYSREG_CNTHV_CVAL_EL2 = 59162 , ARM64_SYSREG_CNTHV_TVAL_EL2 = 59160 , ARM64_SYSREG_CNTISCALE_EL2 = 59141 , ARM64_SYSREG_CNTKCTL_EL1 = 50952 , ARM64_SYSREG_CNTKCTL_EL12 = 61192 , ARM64_SYSREG_CNTPCTSS_EL0 = 57093 , ARM64_SYSREG_CNTPCT_EL0 = 57089 , ARM64_SYSREG_CNTPOFF_EL2 = 59142 , ARM64_SYSREG_CNTPS_CTL_EL1 = 65297 , ARM64_SYSREG_CNTPS_CVAL_EL1 = 65298 , ARM64_SYSREG_CNTPS_TVAL_EL1 = 65296 , ARM64_SYSREG_CNTP_CTL_EL0 = 57105 , ARM64_SYSREG_CNTP_CTL_EL02 = 61201 , ARM64_SYSREG_CNTP_CVAL_EL0 = 57106 , ARM64_SYSREG_CNTP_CVAL_EL02 = 61202 , ARM64_SYSREG_CNTP_TVAL_EL0 = 57104 , ARM64_SYSREG_CNTP_TVAL_EL02 = 61200 , ARM64_SYSREG_CNTSCALE_EL2 = 59140 , ARM64_SYSREG_CNTVCTSS_EL0 = 57094 , ARM64_SYSREG_CNTVCT_EL0 = 57090 , ARM64_SYSREG_CNTVFRQ_EL2 = 59143 , ARM64_SYSREG_CNTVOFF_EL2 = 59139 , ARM64_SYSREG_CNTV_CTL_EL0 = 57113 , ARM64_SYSREG_CNTV_CTL_EL02 = 61209 , ARM64_SYSREG_CNTV_CVAL_EL0 = 57114 , ARM64_SYSREG_CNTV_CVAL_EL02 = 61210 , ARM64_SYSREG_CNTV_TVAL_EL0 = 57112 , ARM64_SYSREG_CNTV_TVAL_EL02 = 61208 , ARM64_SYSREG_CONTEXTIDR_EL1 = 50817 , ARM64_SYSREG_CONTEXTIDR_EL12 = 61057 , ARM64_SYSREG_CONTEXTIDR_EL2 = 59009 , ARM64_SYSREG_CPACR_EL1 = 49282 , ARM64_SYSREG_CPACR_EL12 = 59522 , ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 65424 , ARM64_SYSREG_CPTR_EL2 = 57482 , ARM64_SYSREG_CPTR_EL3 = 61578 , ARM64_SYSREG_CSSELR_EL1 = 53248 , ARM64_SYSREG_CTR_EL0 = 55297 , ARM64_SYSREG_CURRENTEL = 49682 , ARM64_SYSREG_DACR32_EL2 = 57728 , ARM64_SYSREG_DAIF = 55825 , ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 33782 , ARM64_SYSREG_DBGBCR0_EL1 = 32773 , ARM64_SYSREG_DBGBCR10_EL1 = 32853 , ARM64_SYSREG_DBGBCR11_EL1 = 32861 , ARM64_SYSREG_DBGBCR12_EL1 = 32869 , ARM64_SYSREG_DBGBCR13_EL1 = 32877 , ARM64_SYSREG_DBGBCR14_EL1 = 32885 , ARM64_SYSREG_DBGBCR15_EL1 = 32893 , ARM64_SYSREG_DBGBCR1_EL1 = 32781 , ARM64_SYSREG_DBGBCR2_EL1 = 32789 , ARM64_SYSREG_DBGBCR3_EL1 = 32797 , ARM64_SYSREG_DBGBCR4_EL1 = 32805 , ARM64_SYSREG_DBGBCR5_EL1 = 32813 , ARM64_SYSREG_DBGBCR6_EL1 = 32821 , ARM64_SYSREG_DBGBCR7_EL1 = 32829 , ARM64_SYSREG_DBGBCR8_EL1 = 32837 , ARM64_SYSREG_DBGBCR9_EL1 = 32845 , ARM64_SYSREG_DBGBVR0_EL1 = 32772 , ARM64_SYSREG_DBGBVR10_EL1 = 32852 , ARM64_SYSREG_DBGBVR11_EL1 = 32860 , ARM64_SYSREG_DBGBVR12_EL1 = 32868 , ARM64_SYSREG_DBGBVR13_EL1 = 32876 , ARM64_SYSREG_DBGBVR14_EL1 = 32884 , ARM64_SYSREG_DBGBVR15_EL1 = 32892 , ARM64_SYSREG_DBGBVR1_EL1 = 32780 , ARM64_SYSREG_DBGBVR2_EL1 = 32788 , ARM64_SYSREG_DBGBVR3_EL1 = 32796 , ARM64_SYSREG_DBGBVR4_EL1 = 32804 , ARM64_SYSREG_DBGBVR5_EL1 = 32812 , ARM64_SYSREG_DBGBVR6_EL1 = 32820 , ARM64_SYSREG_DBGBVR7_EL1 = 32828 , ARM64_SYSREG_DBGBVR8_EL1 = 32836 , ARM64_SYSREG_DBGBVR9_EL1 = 32844 , ARM64_SYSREG_DBGCLAIMCLR_EL1 = 33742 , ARM64_SYSREG_DBGCLAIMSET_EL1 = 33734 , ARM64_SYSREG_DBGDTRRX_EL0 = 38952 , ARM64_SYSREG_DBGDTR_EL0 = 38944 , ARM64_SYSREG_DBGPRCR_EL1 = 32932 , ARM64_SYSREG_DBGVCR32_EL2 = 41016 , ARM64_SYSREG_DBGWCR0_EL1 = 32775 , ARM64_SYSREG_DBGWCR10_EL1 = 32855 , ARM64_SYSREG_DBGWCR11_EL1 = 32863 , ARM64_SYSREG_DBGWCR12_EL1 = 32871 , ARM64_SYSREG_DBGWCR13_EL1 = 32879 , ARM64_SYSREG_DBGWCR14_EL1 = 32887 , ARM64_SYSREG_DBGWCR15_EL1 = 32895 , ARM64_SYSREG_DBGWCR1_EL1 = 32783 , ARM64_SYSREG_DBGWCR2_EL1 = 32791 , ARM64_SYSREG_DBGWCR3_EL1 = 32799 , ARM64_SYSREG_DBGWCR4_EL1 = 32807 , ARM64_SYSREG_DBGWCR5_EL1 = 32815 , ARM64_SYSREG_DBGWCR6_EL1 = 32823 , ARM64_SYSREG_DBGWCR7_EL1 = 32831 , ARM64_SYSREG_DBGWCR8_EL1 = 32839 , ARM64_SYSREG_DBGWCR9_EL1 = 32847 , ARM64_SYSREG_DBGWVR0_EL1 = 32774 , ARM64_SYSREG_DBGWVR10_EL1 = 32854 , ARM64_SYSREG_DBGWVR11_EL1 = 32862 , ARM64_SYSREG_DBGWVR12_EL1 = 32870 , ARM64_SYSREG_DBGWVR13_EL1 = 32878 , ARM64_SYSREG_DBGWVR14_EL1 = 32886 , ARM64_SYSREG_DBGWVR15_EL1 = 32894 , ARM64_SYSREG_DBGWVR1_EL1 = 32782 , ARM64_SYSREG_DBGWVR2_EL1 = 32790 , ARM64_SYSREG_DBGWVR3_EL1 = 32798 , ARM64_SYSREG_DBGWVR4_EL1 = 32806 , ARM64_SYSREG_DBGWVR5_EL1 = 32814 , ARM64_SYSREG_DBGWVR6_EL1 = 32822 , ARM64_SYSREG_DBGWVR7_EL1 = 32830 , ARM64_SYSREG_DBGWVR8_EL1 = 32838 , ARM64_SYSREG_DBGWVR9_EL1 = 32846 , ARM64_SYSREG_DCZID_EL0 = 55303 , ARM64_SYSREG_DISR_EL1 = 50697 , ARM64_SYSREG_DIT = 55829 , ARM64_SYSREG_DLR_EL0 = 55849 , ARM64_SYSREG_DSPSR_EL0 = 55848 , ARM64_SYSREG_ELR_EL1 = 49665 , ARM64_SYSREG_ELR_EL12 = 59905 , ARM64_SYSREG_ELR_EL2 = 57857 , ARM64_SYSREG_ELR_EL3 = 61953 , ARM64_SYSREG_ERRIDR_EL1 = 49816 , ARM64_SYSREG_ERRSELR_EL1 = 49817 , ARM64_SYSREG_ERXADDR_EL1 = 49827 , ARM64_SYSREG_ERXCTLR_EL1 = 49825 , ARM64_SYSREG_ERXFR_EL1 = 49824 , ARM64_SYSREG_ERXMISC0_EL1 = 49832 , ARM64_SYSREG_ERXMISC1_EL1 = 49833 , ARM64_SYSREG_ERXMISC2_EL1 = 49834 , ARM64_SYSREG_ERXMISC3_EL1 = 49835 , ARM64_SYSREG_ERXPFGCDN_EL1 = 49830 , ARM64_SYSREG_ERXPFGCTL_EL1 = 49829 , ARM64_SYSREG_ERXPFGF_EL1 = 49828 , ARM64_SYSREG_ERXSTATUS_EL1 = 49826 , ARM64_SYSREG_ESR_EL1 = 49808 , ARM64_SYSREG_ESR_EL12 = 60048 , ARM64_SYSREG_ESR_EL2 = 58000 , ARM64_SYSREG_ESR_EL3 = 62096 , ARM64_SYSREG_FAR_EL1 = 49920 , ARM64_SYSREG_FAR_EL12 = 60160 , ARM64_SYSREG_FAR_EL2 = 58112 , ARM64_SYSREG_FAR_EL3 = 62208 , ARM64_SYSREG_FPCR = 55840 , ARM64_SYSREG_FPEXC32_EL2 = 58008 , ARM64_SYSREG_FPSR = 55841 , ARM64_SYSREG_GCR_EL1 = 49286 , ARM64_SYSREG_GMID_EL1 = 51204 , ARM64_SYSREG_GPCCR_EL3 = 61710 , ARM64_SYSREG_GPTBR_EL3 = 61708 , ARM64_SYSREG_HACR_EL2 = 57487 , ARM64_SYSREG_HCRX_EL2 = 57490 , ARM64_SYSREG_HCR_EL2 = 57480 , ARM64_SYSREG_HDFGRTR_EL2 = 57740 , ARM64_SYSREG_HDFGWTR_EL2 = 57741 , ARM64_SYSREG_HFGITR_EL2 = 57486 , ARM64_SYSREG_HFGRTR_EL2 = 57484 , ARM64_SYSREG_HFGWTR_EL2 = 57485 , ARM64_SYSREG_HPFAR_EL2 = 58116 , ARM64_SYSREG_HSTR_EL2 = 57483 , ARM64_SYSREG_ICC_AP0R0_EL1 = 50756 , ARM64_SYSREG_ICC_AP0R1_EL1 = 50757 , ARM64_SYSREG_ICC_AP0R2_EL1 = 50758 , ARM64_SYSREG_ICC_AP0R3_EL1 = 50759 , ARM64_SYSREG_ICC_AP1R0_EL1 = 50760 , ARM64_SYSREG_ICC_AP1R1_EL1 = 50761 , ARM64_SYSREG_ICC_AP1R2_EL1 = 50762 , ARM64_SYSREG_ICC_AP1R3_EL1 = 50763 , ARM64_SYSREG_ICC_ASGI1R_EL1 = 50782 , ARM64_SYSREG_ICC_BPR0_EL1 = 50755 , ARM64_SYSREG_ICC_BPR1_EL1 = 50787 , ARM64_SYSREG_ICC_CTLR_EL1 = 50788 , ARM64_SYSREG_ICC_CTLR_EL3 = 63076 , ARM64_SYSREG_ICC_DIR_EL1 = 50777 , ARM64_SYSREG_ICC_EOIR0_EL1 = 50753 , ARM64_SYSREG_ICC_EOIR1_EL1 = 50785 , ARM64_SYSREG_ICC_HPPIR0_EL1 = 50754 , ARM64_SYSREG_ICC_HPPIR1_EL1 = 50786 , ARM64_SYSREG_ICC_IAR0_EL1 = 50752 , ARM64_SYSREG_ICC_IAR1_EL1 = 50784 , ARM64_SYSREG_ICC_IGRPEN0_EL1 = 50790 , ARM64_SYSREG_ICC_IGRPEN1_EL1 = 50791 , ARM64_SYSREG_ICC_IGRPEN1_EL3 = 63079 , ARM64_SYSREG_ICC_PMR_EL1 = 49712 , ARM64_SYSREG_ICC_RPR_EL1 = 50779 , ARM64_SYSREG_ICC_SGI0R_EL1 = 50783 , ARM64_SYSREG_ICC_SGI1R_EL1 = 50781 , ARM64_SYSREG_ICC_SRE_EL1 = 50789 , ARM64_SYSREG_ICC_SRE_EL2 = 58957 , ARM64_SYSREG_ICC_SRE_EL3 = 63077 , ARM64_SYSREG_ICH_AP0R0_EL2 = 58944 , ARM64_SYSREG_ICH_AP0R1_EL2 = 58945 , ARM64_SYSREG_ICH_AP0R2_EL2 = 58946 , ARM64_SYSREG_ICH_AP0R3_EL2 = 58947 , ARM64_SYSREG_ICH_AP1R0_EL2 = 58952 , ARM64_SYSREG_ICH_AP1R1_EL2 = 58953 , ARM64_SYSREG_ICH_AP1R2_EL2 = 58954 , ARM64_SYSREG_ICH_AP1R3_EL2 = 58955 , ARM64_SYSREG_ICH_EISR_EL2 = 58971 , ARM64_SYSREG_ICH_ELRSR_EL2 = 58973 , ARM64_SYSREG_ICH_HCR_EL2 = 58968 , ARM64_SYSREG_ICH_LR0_EL2 = 58976 , ARM64_SYSREG_ICH_LR10_EL2 = 58986 , ARM64_SYSREG_ICH_LR11_EL2 = 58987 , ARM64_SYSREG_ICH_LR12_EL2 = 58988 , ARM64_SYSREG_ICH_LR13_EL2 = 58989 , ARM64_SYSREG_ICH_LR14_EL2 = 58990 , ARM64_SYSREG_ICH_LR15_EL2 = 58991 , ARM64_SYSREG_ICH_LR1_EL2 = 58977 , ARM64_SYSREG_ICH_LR2_EL2 = 58978 , ARM64_SYSREG_ICH_LR3_EL2 = 58979 , ARM64_SYSREG_ICH_LR4_EL2 = 58980 , ARM64_SYSREG_ICH_LR5_EL2 = 58981 , ARM64_SYSREG_ICH_LR6_EL2 = 58982 , ARM64_SYSREG_ICH_LR7_EL2 = 58983 , ARM64_SYSREG_ICH_LR8_EL2 = 58984 , ARM64_SYSREG_ICH_LR9_EL2 = 58985 , ARM64_SYSREG_ICH_MISR_EL2 = 58970 , ARM64_SYSREG_ICH_VMCR_EL2 = 58975 , ARM64_SYSREG_ICH_VTR_EL2 = 58969 , ARM64_SYSREG_ID_AA64AFR0_EL1 = 49196 , ARM64_SYSREG_ID_AA64AFR1_EL1 = 49197 , ARM64_SYSREG_ID_AA64DFR0_EL1 = 49192 , ARM64_SYSREG_ID_AA64DFR1_EL1 = 49193 , ARM64_SYSREG_ID_AA64ISAR0_EL1 = 49200 , ARM64_SYSREG_ID_AA64ISAR1_EL1 = 49201 , ARM64_SYSREG_ID_AA64ISAR2_EL1 = 49202 , ARM64_SYSREG_ID_AA64MMFR0_EL1 = 49208 , ARM64_SYSREG_ID_AA64MMFR1_EL1 = 49209 , ARM64_SYSREG_ID_AA64MMFR2_EL1 = 49210 , ARM64_SYSREG_ID_AA64PFR0_EL1 = 49184 , ARM64_SYSREG_ID_AA64PFR1_EL1 = 49185 , ARM64_SYSREG_ID_AA64SMFR0_EL1 = 49189 , ARM64_SYSREG_ID_AA64ZFR0_EL1 = 49188 , ARM64_SYSREG_ID_AFR0_EL1 = 49163 , ARM64_SYSREG_ID_DFR0_EL1 = 49162 , ARM64_SYSREG_ID_ISAR0_EL1 = 49168 , ARM64_SYSREG_ID_ISAR1_EL1 = 49169 , ARM64_SYSREG_ID_ISAR2_EL1 = 49170 , ARM64_SYSREG_ID_ISAR3_EL1 = 49171 , ARM64_SYSREG_ID_ISAR4_EL1 = 49172 , ARM64_SYSREG_ID_ISAR5_EL1 = 49173 , ARM64_SYSREG_ID_ISAR6_EL1 = 49175 , ARM64_SYSREG_ID_MMFR0_EL1 = 49164 , ARM64_SYSREG_ID_MMFR1_EL1 = 49165 , ARM64_SYSREG_ID_MMFR2_EL1 = 49166 , ARM64_SYSREG_ID_MMFR3_EL1 = 49167 , ARM64_SYSREG_ID_MMFR4_EL1 = 49174 , ARM64_SYSREG_ID_MMFR5_EL1 = 49182 , ARM64_SYSREG_ID_PFR0_EL1 = 49160 , ARM64_SYSREG_ID_PFR1_EL1 = 49161 , ARM64_SYSREG_ID_PFR2_EL1 = 49180 , ARM64_SYSREG_IFSR32_EL2 = 57985 , ARM64_SYSREG_ISR_EL1 = 50696 , ARM64_SYSREG_LORC_EL1 = 50467 , ARM64_SYSREG_LOREA_EL1 = 50465 , ARM64_SYSREG_LORID_EL1 = 50471 , ARM64_SYSREG_LORN_EL1 = 50466 , ARM64_SYSREG_LORSA_EL1 = 50464 , ARM64_SYSREG_MAIR_EL1 = 50448 , ARM64_SYSREG_MAIR_EL12 = 60688 , ARM64_SYSREG_MAIR_EL2 = 58640 , ARM64_SYSREG_MAIR_EL3 = 62736 , ARM64_SYSREG_MDCCINT_EL1 = 32784 , ARM64_SYSREG_MDCCSR_EL0 = 38920 , ARM64_SYSREG_MDCR_EL2 = 57481 , ARM64_SYSREG_MDCR_EL3 = 61593 , ARM64_SYSREG_MDRAR_EL1 = 32896 , ARM64_SYSREG_MDSCR_EL1 = 32786 , ARM64_SYSREG_MFAR_EL3 = 62213 , ARM64_SYSREG_MIDR_EL1 = 49152 , ARM64_SYSREG_MPAM0_EL1 = 50473 , ARM64_SYSREG_MPAM1_EL1 = 50472 , ARM64_SYSREG_MPAM1_EL12 = 60712 , ARM64_SYSREG_MPAM2_EL2 = 58664 , ARM64_SYSREG_MPAM3_EL3 = 62760 , ARM64_SYSREG_MPAMHCR_EL2 = 58656 , ARM64_SYSREG_MPAMIDR_EL1 = 50468 , ARM64_SYSREG_MPAMSM_EL1 = 50475 , ARM64_SYSREG_MPAMVPM0_EL2 = 58672 , ARM64_SYSREG_MPAMVPM1_EL2 = 58673 , ARM64_SYSREG_MPAMVPM2_EL2 = 58674 , ARM64_SYSREG_MPAMVPM3_EL2 = 58675 , ARM64_SYSREG_MPAMVPM4_EL2 = 58676 , ARM64_SYSREG_MPAMVPM5_EL2 = 58677 , ARM64_SYSREG_MPAMVPM6_EL2 = 58678 , ARM64_SYSREG_MPAMVPM7_EL2 = 58679 , ARM64_SYSREG_MPAMVPMV_EL2 = 58657 , ARM64_SYSREG_MPIDR_EL1 = 49157 , ARM64_SYSREG_MPUIR_EL1 = 49156 , ARM64_SYSREG_MPUIR_EL2 = 57348 , ARM64_SYSREG_MVFR0_EL1 = 49176 , ARM64_SYSREG_MVFR1_EL1 = 49177 , ARM64_SYSREG_MVFR2_EL1 = 49178 , ARM64_SYSREG_NZCV = 55824 , ARM64_SYSREG_OSDLR_EL1 = 32924 , ARM64_SYSREG_OSDTRRX_EL1 = 32770 , ARM64_SYSREG_OSDTRTX_EL1 = 32794 , ARM64_SYSREG_OSECCR_EL1 = 32818 , ARM64_SYSREG_OSLAR_EL1 = 32900 , ARM64_SYSREG_OSLSR_EL1 = 32908 , ARM64_SYSREG_PAN = 49683 , ARM64_SYSREG_PAR_EL1 = 50080 , ARM64_SYSREG_PMBIDR_EL1 = 50391 , ARM64_SYSREG_PMBLIMITR_EL1 = 50384 , ARM64_SYSREG_PMBPTR_EL1 = 50385 , ARM64_SYSREG_PMBSR_EL1 = 50387 , ARM64_SYSREG_PMCCFILTR_EL0 = 57215 , ARM64_SYSREG_PMCCNTR_EL0 = 56552 , ARM64_SYSREG_PMCEID0_EL0 = 56550 , ARM64_SYSREG_PMCEID1_EL0 = 56551 , ARM64_SYSREG_PMCNTENCLR_EL0 = 56546 , ARM64_SYSREG_PMCNTENSET_EL0 = 56545 , ARM64_SYSREG_PMCR_EL0 = 56544 , ARM64_SYSREG_PMEVCNTR0_EL0 = 57152 , ARM64_SYSREG_PMEVCNTR10_EL0 = 57162 , ARM64_SYSREG_PMEVCNTR11_EL0 = 57163 , ARM64_SYSREG_PMEVCNTR12_EL0 = 57164 , ARM64_SYSREG_PMEVCNTR13_EL0 = 57165 , ARM64_SYSREG_PMEVCNTR14_EL0 = 57166 , ARM64_SYSREG_PMEVCNTR15_EL0 = 57167 , ARM64_SYSREG_PMEVCNTR16_EL0 = 57168 , ARM64_SYSREG_PMEVCNTR17_EL0 = 57169 , ARM64_SYSREG_PMEVCNTR18_EL0 = 57170 , ARM64_SYSREG_PMEVCNTR19_EL0 = 57171 , ARM64_SYSREG_PMEVCNTR1_EL0 = 57153 , ARM64_SYSREG_PMEVCNTR20_EL0 = 57172 , ARM64_SYSREG_PMEVCNTR21_EL0 = 57173 , ARM64_SYSREG_PMEVCNTR22_EL0 = 57174 , ARM64_SYSREG_PMEVCNTR23_EL0 = 57175 , ARM64_SYSREG_PMEVCNTR24_EL0 = 57176 , ARM64_SYSREG_PMEVCNTR25_EL0 = 57177 , ARM64_SYSREG_PMEVCNTR26_EL0 = 57178 , ARM64_SYSREG_PMEVCNTR27_EL0 = 57179 , ARM64_SYSREG_PMEVCNTR28_EL0 = 57180 , ARM64_SYSREG_PMEVCNTR29_EL0 = 57181 , ARM64_SYSREG_PMEVCNTR2_EL0 = 57154 , ARM64_SYSREG_PMEVCNTR30_EL0 = 57182 , ARM64_SYSREG_PMEVCNTR3_EL0 = 57155 , ARM64_SYSREG_PMEVCNTR4_EL0 = 57156 , ARM64_SYSREG_PMEVCNTR5_EL0 = 57157 , ARM64_SYSREG_PMEVCNTR6_EL0 = 57158 , ARM64_SYSREG_PMEVCNTR7_EL0 = 57159 , ARM64_SYSREG_PMEVCNTR8_EL0 = 57160 , ARM64_SYSREG_PMEVCNTR9_EL0 = 57161 , ARM64_SYSREG_PMEVTYPER0_EL0 = 57184 , ARM64_SYSREG_PMEVTYPER10_EL0 = 57194 , ARM64_SYSREG_PMEVTYPER11_EL0 = 57195 , ARM64_SYSREG_PMEVTYPER12_EL0 = 57196 , ARM64_SYSREG_PMEVTYPER13_EL0 = 57197 , ARM64_SYSREG_PMEVTYPER14_EL0 = 57198 , ARM64_SYSREG_PMEVTYPER15_EL0 = 57199 , ARM64_SYSREG_PMEVTYPER16_EL0 = 57200 , ARM64_SYSREG_PMEVTYPER17_EL0 = 57201 , ARM64_SYSREG_PMEVTYPER18_EL0 = 57202 , ARM64_SYSREG_PMEVTYPER19_EL0 = 57203 , ARM64_SYSREG_PMEVTYPER1_EL0 = 57185 , ARM64_SYSREG_PMEVTYPER20_EL0 = 57204 , ARM64_SYSREG_PMEVTYPER21_EL0 = 57205 , ARM64_SYSREG_PMEVTYPER22_EL0 = 57206 , ARM64_SYSREG_PMEVTYPER23_EL0 = 57207 , ARM64_SYSREG_PMEVTYPER24_EL0 = 57208 , ARM64_SYSREG_PMEVTYPER25_EL0 = 57209 , ARM64_SYSREG_PMEVTYPER26_EL0 = 57210 , ARM64_SYSREG_PMEVTYPER27_EL0 = 57211 , ARM64_SYSREG_PMEVTYPER28_EL0 = 57212 , ARM64_SYSREG_PMEVTYPER29_EL0 = 57213 , ARM64_SYSREG_PMEVTYPER2_EL0 = 57186 , ARM64_SYSREG_PMEVTYPER30_EL0 = 57214 , ARM64_SYSREG_PMEVTYPER3_EL0 = 57187 , ARM64_SYSREG_PMEVTYPER4_EL0 = 57188 , ARM64_SYSREG_PMEVTYPER5_EL0 = 57189 , ARM64_SYSREG_PMEVTYPER6_EL0 = 57190 , ARM64_SYSREG_PMEVTYPER7_EL0 = 57191 , ARM64_SYSREG_PMEVTYPER8_EL0 = 57192 , ARM64_SYSREG_PMEVTYPER9_EL0 = 57193 , ARM64_SYSREG_PMINTENCLR_EL1 = 50418 , ARM64_SYSREG_PMINTENSET_EL1 = 50417 , ARM64_SYSREG_PMMIR_EL1 = 50422 , ARM64_SYSREG_PMOVSCLR_EL0 = 56547 , ARM64_SYSREG_PMOVSSET_EL0 = 56563 , ARM64_SYSREG_PMSCR_EL1 = 50376 , ARM64_SYSREG_PMSCR_EL12 = 60616 , ARM64_SYSREG_PMSCR_EL2 = 58568 , ARM64_SYSREG_PMSELR_EL0 = 56549 , ARM64_SYSREG_PMSEVFR_EL1 = 50381 , ARM64_SYSREG_PMSFCR_EL1 = 50380 , ARM64_SYSREG_PMSICR_EL1 = 50378 , ARM64_SYSREG_PMSIDR_EL1 = 50383 , ARM64_SYSREG_PMSIRR_EL1 = 50379 , ARM64_SYSREG_PMSLATFR_EL1 = 50382 , ARM64_SYSREG_PMSNEVFR_EL1 = 50377 , ARM64_SYSREG_PMSWINC_EL0 = 56548 , ARM64_SYSREG_PMUSERENR_EL0 = 56560 , ARM64_SYSREG_PMXEVCNTR_EL0 = 56554 , ARM64_SYSREG_PMXEVTYPER_EL0 = 56553 , ARM64_SYSREG_PRBAR10_EL1 = 50024 , ARM64_SYSREG_PRBAR10_EL2 = 58216 , ARM64_SYSREG_PRBAR11_EL1 = 50028 , ARM64_SYSREG_PRBAR11_EL2 = 58220 , ARM64_SYSREG_PRBAR12_EL1 = 50032 , ARM64_SYSREG_PRBAR12_EL2 = 58224 , ARM64_SYSREG_PRBAR13_EL1 = 50036 , ARM64_SYSREG_PRBAR13_EL2 = 58228 , ARM64_SYSREG_PRBAR14_EL1 = 50040 , ARM64_SYSREG_PRBAR14_EL2 = 58232 , ARM64_SYSREG_PRBAR15_EL1 = 50044 , ARM64_SYSREG_PRBAR15_EL2 = 58236 , ARM64_SYSREG_PRBAR1_EL1 = 49988 , ARM64_SYSREG_PRBAR1_EL2 = 58180 , ARM64_SYSREG_PRBAR2_EL1 = 49992 , ARM64_SYSREG_PRBAR2_EL2 = 58184 , ARM64_SYSREG_PRBAR3_EL1 = 49996 , ARM64_SYSREG_PRBAR3_EL2 = 58188 , ARM64_SYSREG_PRBAR4_EL1 = 50000 , ARM64_SYSREG_PRBAR4_EL2 = 58192 , ARM64_SYSREG_PRBAR5_EL1 = 50004 , ARM64_SYSREG_PRBAR5_EL2 = 58196 , ARM64_SYSREG_PRBAR6_EL1 = 50008 , ARM64_SYSREG_PRBAR6_EL2 = 58200 , ARM64_SYSREG_PRBAR7_EL1 = 50012 , ARM64_SYSREG_PRBAR7_EL2 = 58204 , ARM64_SYSREG_PRBAR8_EL1 = 50016 , ARM64_SYSREG_PRBAR8_EL2 = 58208 , ARM64_SYSREG_PRBAR9_EL1 = 50020 , ARM64_SYSREG_PRBAR9_EL2 = 58212 , ARM64_SYSREG_PRBAR_EL1 = 49984 , ARM64_SYSREG_PRBAR_EL2 = 58176 , ARM64_SYSREG_PRENR_EL1 = 49929 , ARM64_SYSREG_PRENR_EL2 = 58121 , ARM64_SYSREG_PRLAR10_EL1 = 50025 , ARM64_SYSREG_PRLAR10_EL2 = 58217 , ARM64_SYSREG_PRLAR11_EL1 = 50029 , ARM64_SYSREG_PRLAR11_EL2 = 58221 , ARM64_SYSREG_PRLAR12_EL1 = 50033 , ARM64_SYSREG_PRLAR12_EL2 = 58225 , ARM64_SYSREG_PRLAR13_EL1 = 50037 , ARM64_SYSREG_PRLAR13_EL2 = 58229 , ARM64_SYSREG_PRLAR14_EL1 = 50041 , ARM64_SYSREG_PRLAR14_EL2 = 58233 , ARM64_SYSREG_PRLAR15_EL1 = 50045 , ARM64_SYSREG_PRLAR15_EL2 = 58237 , ARM64_SYSREG_PRLAR1_EL1 = 49989 , ARM64_SYSREG_PRLAR1_EL2 = 58181 , ARM64_SYSREG_PRLAR2_EL1 = 49993 , ARM64_SYSREG_PRLAR2_EL2 = 58185 , ARM64_SYSREG_PRLAR3_EL1 = 49997 , ARM64_SYSREG_PRLAR3_EL2 = 58189 , ARM64_SYSREG_PRLAR4_EL1 = 50001 , ARM64_SYSREG_PRLAR4_EL2 = 58193 , ARM64_SYSREG_PRLAR5_EL1 = 50005 , ARM64_SYSREG_PRLAR5_EL2 = 58197 , ARM64_SYSREG_PRLAR6_EL1 = 50009 , ARM64_SYSREG_PRLAR6_EL2 = 58201 , ARM64_SYSREG_PRLAR7_EL1 = 50013 , ARM64_SYSREG_PRLAR7_EL2 = 58205 , ARM64_SYSREG_PRLAR8_EL1 = 50017 , ARM64_SYSREG_PRLAR8_EL2 = 58209 , ARM64_SYSREG_PRLAR9_EL1 = 50021 , ARM64_SYSREG_PRLAR9_EL2 = 58213 , ARM64_SYSREG_PRLAR_EL1 = 49985 , ARM64_SYSREG_PRLAR_EL2 = 58177 , ARM64_SYSREG_PRSELR_EL1 = 49937 , ARM64_SYSREG_PRSELR_EL2 = 58129 , ARM64_SYSREG_REVIDR_EL1 = 49158 , ARM64_SYSREG_RGSR_EL1 = 49285 , ARM64_SYSREG_RMR_EL1 = 50690 , ARM64_SYSREG_RMR_EL2 = 58882 , ARM64_SYSREG_RMR_EL3 = 62978 , ARM64_SYSREG_RNDR = 55584 , ARM64_SYSREG_RNDRRS = 55585 , ARM64_SYSREG_RVBAR_EL1 = 50689 , ARM64_SYSREG_RVBAR_EL2 = 58881 , ARM64_SYSREG_RVBAR_EL3 = 62977 , ARM64_SYSREG_SCR_EL3 = 61576 , ARM64_SYSREG_SCTLR_EL1 = 49280 , ARM64_SYSREG_SCTLR_EL12 = 59520 , ARM64_SYSREG_SCTLR_EL2 = 57472 , ARM64_SYSREG_SCTLR_EL3 = 61568 , ARM64_SYSREG_SCXTNUM_EL0 = 56967 , ARM64_SYSREG_SCXTNUM_EL1 = 50823 , ARM64_SYSREG_SCXTNUM_EL12 = 61063 , ARM64_SYSREG_SCXTNUM_EL2 = 59015 , ARM64_SYSREG_SCXTNUM_EL3 = 63111 , ARM64_SYSREG_SDER32_EL2 = 57497 , ARM64_SYSREG_SDER32_EL3 = 61577 , ARM64_SYSREG_SMCR_EL1 = 49302 , ARM64_SYSREG_SMCR_EL12 = 59542 , ARM64_SYSREG_SMCR_EL2 = 57494 , ARM64_SYSREG_SMCR_EL3 = 61590 , ARM64_SYSREG_SMIDR_EL1 = 51206 , ARM64_SYSREG_SMPRIMAP_EL2 = 57493 , ARM64_SYSREG_SMPRI_EL1 = 49300 , ARM64_SYSREG_SPSEL = 49680 , ARM64_SYSREG_SPSR_ABT = 57881 , ARM64_SYSREG_SPSR_EL1 = 49664 , ARM64_SYSREG_SPSR_EL12 = 59904 , ARM64_SYSREG_SPSR_EL2 = 57856 , ARM64_SYSREG_SPSR_EL3 = 61952 , ARM64_SYSREG_SPSR_FIQ = 57883 , ARM64_SYSREG_SPSR_IRQ = 57880 , ARM64_SYSREG_SPSR_UND = 57882 , ARM64_SYSREG_SP_EL0 = 49672 , ARM64_SYSREG_SP_EL1 = 57864 , ARM64_SYSREG_SP_EL2 = 61960 , ARM64_SYSREG_SSBS = 55830 , ARM64_SYSREG_SVCR = 55826 , ARM64_SYSREG_TCO = 55831 , ARM64_SYSREG_TCR_EL1 = 49410 , ARM64_SYSREG_TCR_EL12 = 59650 , ARM64_SYSREG_TCR_EL2 = 57602 , ARM64_SYSREG_TCR_EL3 = 61698 , ARM64_SYSREG_TEECR32_EL1 = 36864 , ARM64_SYSREG_TEEHBR32_EL1 = 36992 , ARM64_SYSREG_TFSRE0_EL1 = 49841 , ARM64_SYSREG_TFSR_EL1 = 49840 , ARM64_SYSREG_TFSR_EL12 = 60080 , ARM64_SYSREG_TFSR_EL2 = 58032 , ARM64_SYSREG_TFSR_EL3 = 62128 , ARM64_SYSREG_TPIDR2_EL0 = 56965 , ARM64_SYSREG_TPIDRRO_EL0 = 56963 , ARM64_SYSREG_TPIDR_EL0 = 56962 , ARM64_SYSREG_TPIDR_EL1 = 50820 , ARM64_SYSREG_TPIDR_EL2 = 59010 , ARM64_SYSREG_TPIDR_EL3 = 63106 , ARM64_SYSREG_TRBBASER_EL1 = 50394 , ARM64_SYSREG_TRBIDR_EL1 = 50399 , ARM64_SYSREG_TRBLIMITR_EL1 = 50392 , ARM64_SYSREG_TRBMAR_EL1 = 50396 , ARM64_SYSREG_TRBPTR_EL1 = 50393 , ARM64_SYSREG_TRBSR_EL1 = 50395 , ARM64_SYSREG_TRBTRG_EL1 = 50398 , ARM64_SYSREG_TRCACATR0 = 35074 , ARM64_SYSREG_TRCACATR1 = 35090 , ARM64_SYSREG_TRCACATR10 = 35107 , ARM64_SYSREG_TRCACATR11 = 35123 , ARM64_SYSREG_TRCACATR12 = 35139 , ARM64_SYSREG_TRCACATR13 = 35155 , ARM64_SYSREG_TRCACATR14 = 35171 , ARM64_SYSREG_TRCACATR15 = 35187 , ARM64_SYSREG_TRCACATR2 = 35106 , ARM64_SYSREG_TRCACATR3 = 35122 , ARM64_SYSREG_TRCACATR4 = 35138 , ARM64_SYSREG_TRCACATR5 = 35154 , ARM64_SYSREG_TRCACATR6 = 35170 , ARM64_SYSREG_TRCACATR7 = 35186 , ARM64_SYSREG_TRCACATR8 = 35075 , ARM64_SYSREG_TRCACATR9 = 35091 , ARM64_SYSREG_TRCACVR0 = 35072 , ARM64_SYSREG_TRCACVR1 = 35088 , ARM64_SYSREG_TRCACVR10 = 35105 , ARM64_SYSREG_TRCACVR11 = 35121 , ARM64_SYSREG_TRCACVR12 = 35137 , ARM64_SYSREG_TRCACVR13 = 35153 , ARM64_SYSREG_TRCACVR14 = 35169 , ARM64_SYSREG_TRCACVR15 = 35185 , ARM64_SYSREG_TRCACVR2 = 35104 , ARM64_SYSREG_TRCACVR3 = 35120 , ARM64_SYSREG_TRCACVR4 = 35136 , ARM64_SYSREG_TRCACVR5 = 35152 , ARM64_SYSREG_TRCACVR6 = 35168 , ARM64_SYSREG_TRCACVR7 = 35184 , ARM64_SYSREG_TRCACVR8 = 35073 , ARM64_SYSREG_TRCACVR9 = 35089 , ARM64_SYSREG_TRCAUTHSTATUS = 35830 , ARM64_SYSREG_TRCAUXCTLR = 34864 , ARM64_SYSREG_TRCBBCTLR = 34936 , ARM64_SYSREG_TRCCCCTLR = 34928 , ARM64_SYSREG_TRCCIDCCTLR0 = 35202 , ARM64_SYSREG_TRCCIDCCTLR1 = 35210 , ARM64_SYSREG_TRCCIDCVR0 = 35200 , ARM64_SYSREG_TRCCIDCVR1 = 35216 , ARM64_SYSREG_TRCCIDCVR2 = 35232 , ARM64_SYSREG_TRCCIDCVR3 = 35248 , ARM64_SYSREG_TRCCIDCVR4 = 35264 , ARM64_SYSREG_TRCCIDCVR5 = 35280 , ARM64_SYSREG_TRCCIDCVR6 = 35296 , ARM64_SYSREG_TRCCIDCVR7 = 35312 , ARM64_SYSREG_TRCCIDR0 = 35815 , ARM64_SYSREG_TRCCIDR1 = 35823 , ARM64_SYSREG_TRCCIDR2 = 35831 , ARM64_SYSREG_TRCCIDR3 = 35839 , ARM64_SYSREG_TRCCLAIMCLR = 35790 , ARM64_SYSREG_TRCCLAIMSET = 35782 , ARM64_SYSREG_TRCCNTCTLR0 = 34853 , ARM64_SYSREG_TRCCNTCTLR1 = 34861 , ARM64_SYSREG_TRCCNTCTLR2 = 34869 , ARM64_SYSREG_TRCCNTCTLR3 = 34877 , ARM64_SYSREG_TRCCNTRLDVR0 = 34821 , ARM64_SYSREG_TRCCNTRLDVR1 = 34829 , ARM64_SYSREG_TRCCNTRLDVR2 = 34837 , ARM64_SYSREG_TRCCNTRLDVR3 = 34845 , ARM64_SYSREG_TRCCNTVR0 = 34885 , ARM64_SYSREG_TRCCNTVR1 = 34893 , ARM64_SYSREG_TRCCNTVR2 = 34901 , ARM64_SYSREG_TRCCNTVR3 = 34909 , ARM64_SYSREG_TRCCONFIGR = 34848 , ARM64_SYSREG_TRCDEVAFF0 = 35798 , ARM64_SYSREG_TRCDEVAFF1 = 35806 , ARM64_SYSREG_TRCDEVARCH = 35838 , ARM64_SYSREG_TRCDEVID = 35735 , ARM64_SYSREG_TRCDEVTYPE = 35743 , ARM64_SYSREG_TRCDVCMR0 = 35078 , ARM64_SYSREG_TRCDVCMR1 = 35110 , ARM64_SYSREG_TRCDVCMR2 = 35142 , ARM64_SYSREG_TRCDVCMR3 = 35174 , ARM64_SYSREG_TRCDVCMR4 = 35079 , ARM64_SYSREG_TRCDVCMR5 = 35111 , ARM64_SYSREG_TRCDVCMR6 = 35143 , ARM64_SYSREG_TRCDVCMR7 = 35175 , ARM64_SYSREG_TRCDVCVR0 = 35076 , ARM64_SYSREG_TRCDVCVR1 = 35108 , ARM64_SYSREG_TRCDVCVR2 = 35140 , ARM64_SYSREG_TRCDVCVR3 = 35172 , ARM64_SYSREG_TRCDVCVR4 = 35077 , ARM64_SYSREG_TRCDVCVR5 = 35109 , ARM64_SYSREG_TRCDVCVR6 = 35141 , ARM64_SYSREG_TRCDVCVR7 = 35173 , ARM64_SYSREG_TRCEVENTCTL0R = 34880 , ARM64_SYSREG_TRCEVENTCTL1R = 34888 , ARM64_SYSREG_TRCEXTINSELR = 34884 , ARM64_SYSREG_TRCEXTINSELR1 = 34892 , ARM64_SYSREG_TRCEXTINSELR2 = 34900 , ARM64_SYSREG_TRCEXTINSELR3 = 34908 , ARM64_SYSREG_TRCIDR0 = 34887 , ARM64_SYSREG_TRCIDR1 = 34895 , ARM64_SYSREG_TRCIDR10 = 34838 , ARM64_SYSREG_TRCIDR11 = 34846 , ARM64_SYSREG_TRCIDR12 = 34854 , ARM64_SYSREG_TRCIDR13 = 34862 , ARM64_SYSREG_TRCIDR2 = 34903 , ARM64_SYSREG_TRCIDR3 = 34911 , ARM64_SYSREG_TRCIDR4 = 34919 , ARM64_SYSREG_TRCIDR5 = 34927 , ARM64_SYSREG_TRCIDR6 = 34935 , ARM64_SYSREG_TRCIDR7 = 34943 , ARM64_SYSREG_TRCIDR8 = 34822 , ARM64_SYSREG_TRCIDR9 = 34830 , ARM64_SYSREG_TRCIMSPEC0 = 34823 , ARM64_SYSREG_TRCIMSPEC1 = 34831 , ARM64_SYSREG_TRCIMSPEC2 = 34839 , ARM64_SYSREG_TRCIMSPEC3 = 34847 , ARM64_SYSREG_TRCIMSPEC4 = 34855 , ARM64_SYSREG_TRCIMSPEC5 = 34863 , ARM64_SYSREG_TRCIMSPEC6 = 34871 , ARM64_SYSREG_TRCIMSPEC7 = 34879 , ARM64_SYSREG_TRCITCTRL = 35716 , ARM64_SYSREG_TRCLAR = 35814 , ARM64_SYSREG_TRCLSR = 35822 , ARM64_SYSREG_TRCOSLAR = 34948 , ARM64_SYSREG_TRCOSLSR = 34956 , ARM64_SYSREG_TRCPDCR = 34980 , ARM64_SYSREG_TRCPDSR = 34988 , ARM64_SYSREG_TRCPIDR0 = 35783 , ARM64_SYSREG_TRCPIDR1 = 35791 , ARM64_SYSREG_TRCPIDR2 = 35799 , ARM64_SYSREG_TRCPIDR3 = 35807 , ARM64_SYSREG_TRCPIDR4 = 35751 , ARM64_SYSREG_TRCPIDR5 = 35759 , ARM64_SYSREG_TRCPIDR6 = 35767 , ARM64_SYSREG_TRCPIDR7 = 35775 , ARM64_SYSREG_TRCPRGCTLR = 34824 , ARM64_SYSREG_TRCPROCSELR = 34832 , ARM64_SYSREG_TRCQCTLR = 34825 , ARM64_SYSREG_TRCRSCTLR10 = 35024 , ARM64_SYSREG_TRCRSCTLR11 = 35032 , ARM64_SYSREG_TRCRSCTLR12 = 35040 , ARM64_SYSREG_TRCRSCTLR13 = 35048 , ARM64_SYSREG_TRCRSCTLR14 = 35056 , ARM64_SYSREG_TRCRSCTLR15 = 35064 , ARM64_SYSREG_TRCRSCTLR16 = 34945 , ARM64_SYSREG_TRCRSCTLR17 = 34953 , ARM64_SYSREG_TRCRSCTLR18 = 34961 , ARM64_SYSREG_TRCRSCTLR19 = 34969 , ARM64_SYSREG_TRCRSCTLR2 = 34960 , ARM64_SYSREG_TRCRSCTLR20 = 34977 , ARM64_SYSREG_TRCRSCTLR21 = 34985 , ARM64_SYSREG_TRCRSCTLR22 = 34993 , ARM64_SYSREG_TRCRSCTLR23 = 35001 , ARM64_SYSREG_TRCRSCTLR24 = 35009 , ARM64_SYSREG_TRCRSCTLR25 = 35017 , ARM64_SYSREG_TRCRSCTLR26 = 35025 , ARM64_SYSREG_TRCRSCTLR27 = 35033 , ARM64_SYSREG_TRCRSCTLR28 = 35041 , ARM64_SYSREG_TRCRSCTLR29 = 35049 , ARM64_SYSREG_TRCRSCTLR3 = 34968 , ARM64_SYSREG_TRCRSCTLR30 = 35057 , ARM64_SYSREG_TRCRSCTLR31 = 35065 , ARM64_SYSREG_TRCRSCTLR4 = 34976 , ARM64_SYSREG_TRCRSCTLR5 = 34984 , ARM64_SYSREG_TRCRSCTLR6 = 34992 , ARM64_SYSREG_TRCRSCTLR7 = 35000 , ARM64_SYSREG_TRCRSCTLR8 = 35008 , ARM64_SYSREG_TRCRSCTLR9 = 35016 , ARM64_SYSREG_TRCRSR = 34896 , ARM64_SYSREG_TRCSEQEVR0 = 34820 , ARM64_SYSREG_TRCSEQEVR1 = 34828 , ARM64_SYSREG_TRCSEQEVR2 = 34836 , ARM64_SYSREG_TRCSEQRSTEVR = 34868 , ARM64_SYSREG_TRCSEQSTR = 34876 , ARM64_SYSREG_TRCSSCCR0 = 34946 , ARM64_SYSREG_TRCSSCCR1 = 34954 , ARM64_SYSREG_TRCSSCCR2 = 34962 , ARM64_SYSREG_TRCSSCCR3 = 34970 , ARM64_SYSREG_TRCSSCCR4 = 34978 , ARM64_SYSREG_TRCSSCCR5 = 34986 , ARM64_SYSREG_TRCSSCCR6 = 34994 , ARM64_SYSREG_TRCSSCCR7 = 35002 , ARM64_SYSREG_TRCSSCSR0 = 35010 , ARM64_SYSREG_TRCSSCSR1 = 35018 , ARM64_SYSREG_TRCSSCSR2 = 35026 , ARM64_SYSREG_TRCSSCSR3 = 35034 , ARM64_SYSREG_TRCSSCSR4 = 35042 , ARM64_SYSREG_TRCSSCSR5 = 35050 , ARM64_SYSREG_TRCSSCSR6 = 35058 , ARM64_SYSREG_TRCSSCSR7 = 35066 , ARM64_SYSREG_TRCSSPCICR0 = 34947 , ARM64_SYSREG_TRCSSPCICR1 = 34955 , ARM64_SYSREG_TRCSSPCICR2 = 34963 , ARM64_SYSREG_TRCSSPCICR3 = 34971 , ARM64_SYSREG_TRCSSPCICR4 = 34979 , ARM64_SYSREG_TRCSSPCICR5 = 34987 , ARM64_SYSREG_TRCSSPCICR6 = 34995 , ARM64_SYSREG_TRCSSPCICR7 = 35003 , ARM64_SYSREG_TRCSTALLCTLR = 34904 , ARM64_SYSREG_TRCSTATR = 34840 , ARM64_SYSREG_TRCSYNCPR = 34920 , ARM64_SYSREG_TRCTRACEIDR = 34817 , ARM64_SYSREG_TRCTSCTLR = 34912 , ARM64_SYSREG_TRCVDARCCTLR = 34898 , ARM64_SYSREG_TRCVDCTLR = 34882 , ARM64_SYSREG_TRCVDSACCTLR = 34890 , ARM64_SYSREG_TRCVICTLR = 34818 , ARM64_SYSREG_TRCVIIECTLR = 34826 , ARM64_SYSREG_TRCVIPCSSCTLR = 34842 , ARM64_SYSREG_TRCVISSCTLR = 34834 , ARM64_SYSREG_TRCVMIDCCTLR0 = 35218 , ARM64_SYSREG_TRCVMIDCCTLR1 = 35226 , ARM64_SYSREG_TRCVMIDCVR0 = 35201 , ARM64_SYSREG_TRCVMIDCVR1 = 35217 , ARM64_SYSREG_TRCVMIDCVR2 = 35233 , ARM64_SYSREG_TRCVMIDCVR3 = 35249 , ARM64_SYSREG_TRCVMIDCVR4 = 35265 , ARM64_SYSREG_TRCVMIDCVR5 = 35281 , ARM64_SYSREG_TRCVMIDCVR6 = 35297 , ARM64_SYSREG_TRCVMIDCVR7 = 35313 , ARM64_SYSREG_TRFCR_EL1 = 49297 , ARM64_SYSREG_TRFCR_EL12 = 59537 , ARM64_SYSREG_TRFCR_EL2 = 57489 , ARM64_SYSREG_TTBR0_EL1 = 49408 , ARM64_SYSREG_TTBR0_EL12 = 59648 , ARM64_SYSREG_TTBR0_EL2 = 57600 , ARM64_SYSREG_TTBR0_EL3 = 61696 , ARM64_SYSREG_TTBR1_EL1 = 49409 , ARM64_SYSREG_TTBR1_EL12 = 59649 , ARM64_SYSREG_TTBR1_EL2 = 57601 , ARM64_SYSREG_UAO = 49684 , ARM64_SYSREG_VBAR_EL1 = 50688 , ARM64_SYSREG_VBAR_EL12 = 60928 , ARM64_SYSREG_VBAR_EL2 = 58880 , ARM64_SYSREG_VBAR_EL3 = 62976 , ARM64_SYSREG_VDISR_EL2 = 58889 , ARM64_SYSREG_VMPIDR_EL2 = 57349 , ARM64_SYSREG_VNCR_EL2 = 57616 , ARM64_SYSREG_VPIDR_EL2 = 57344 , ARM64_SYSREG_VSESR_EL2 = 58003 , ARM64_SYSREG_VSTCR_EL2 = 57650 , ARM64_SYSREG_VSTTBR_EL2 = 57648 , ARM64_SYSREG_VTCR_EL2 = 57610 , ARM64_SYSREG_VTTBR_EL2 = 57608 , ARM64_SYSREG_ZCR_EL1 = 49296 , ARM64_SYSREG_ZCR_EL12 = 59536 , ARM64_SYSREG_ZCR_EL2 = 57488 , ARM64_SYSREG_ZCR_EL3 = 61584 , } # [repr (u32)] # [doc = " System PState Field (MSR instruction)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_pstate { ARM64_PSTATE_INVALID = 0 , ARM64_PSTATE_SPSEL = 5 , ARM64_PSTATE_DAIFSET = 30 , ARM64_PSTATE_DAIFCLR = 31 , ARM64_PSTATE_PAN = 4 , ARM64_PSTATE_UAO = 3 , ARM64_PSTATE_DIT = 26 , } # [repr (u32)] # [doc = " Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_vas { ARM64_VAS_INVALID = 0 , ARM64_VAS_16B = 1 , ARM64_VAS_8B = 2 , ARM64_VAS_4B = 3 , ARM64_VAS_1B = 4 , ARM64_VAS_8H = 5 , ARM64_VAS_4H = 6 , ARM64_VAS_2H = 7 , ARM64_VAS_1H = 8 , ARM64_VAS_4S = 9 , ARM64_VAS_2S = 10 , ARM64_VAS_1S = 11 , ARM64_VAS_2D = 12 , ARM64_VAS_1D = 13 , ARM64_VAS_1Q = 14 , } # [repr (u32)] # [doc = " Memory barrier operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0 , ARM64_BARRIER_OSHLD = 1 , ARM64_BARRIER_OSHST = 2 , ARM64_BARRIER_OSH = 3 , ARM64_BARRIER_NSHLD = 5 , ARM64_BARRIER_NSHST = 6 , ARM64_BARRIER_NSH = 7 , ARM64_BARRIER_ISHLD = 9 , ARM64_BARRIER_ISHST = 10 , ARM64_BARRIER_ISH = 11 , ARM64_BARRIER_LD = 13 , ARM64_BARRIER_ST = 14 , ARM64_BARRIER_SY = 15 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] ARM64_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] ARM64_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] ARM64_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] ARM64_OP_MEM = 3 , # [doc = "< = CS_OP_FP (Floating-Point operand)."] ARM64_OP_FP = 4 , # [doc = "< C-Immediate"] ARM64_OP_CIMM = 64 , # [doc = "< MRS register operand."] ARM64_OP_REG_MRS = 65 , # [doc = "< MSR register operand."] ARM64_OP_REG_MSR = 66 , # [doc = "< PState operand."] ARM64_OP_PSTATE = 67 , # [doc = "< SYS operand for IC/DC/AT/TLBI instructions."] ARM64_OP_SYS = 68 , # [doc = "< SVCR operand for MSR SVCR instructions."] ARM64_OP_SVCR = 69 , # [doc = "< Prefetch operand (PRFM)."] ARM64_OP_PREFETCH = 70 , # [doc = "< Memory barrier operand (ISB/DMB/DSB instructions)."] ARM64_OP_BARRIER = 71 , # [doc = "< SME instruction operand with with index."] ARM64_OP_SME_INDEX = 72 , } # [repr (u32)] # [doc = " SYS operands (IC/DC/AC/TLBI)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_sys_op { ARM64_SYS_INVALID = 0 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1 = 1 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1IS = 2 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1ISNXS = 3 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1NXS = 4 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OS = 5 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE1OSNXS = 6 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2 = 7 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2IS = 8 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2ISNXS = 9 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2NXS = 10 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OS = 11 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE2OSNXS = 12 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3 = 13 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3IS = 14 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3ISNXS = 15 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3NXS = 16 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OS = 17 , # [doc = " TLBI operations"] ARM64_TLBI_ALLE3OSNXS = 18 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1 = 19 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1IS = 20 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1ISNXS = 21 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1NXS = 22 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OS = 23 , # [doc = " TLBI operations"] ARM64_TLBI_ASIDE1OSNXS = 24 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1 = 25 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1IS = 26 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1ISNXS = 27 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1NXS = 28 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OS = 29 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2E1OSNXS = 30 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1 = 31 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1IS = 32 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1ISNXS = 33 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1NXS = 34 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OS = 35 , # [doc = " TLBI operations"] ARM64_TLBI_IPAS2LE1OSNXS = 36 , # [doc = " TLBI operations"] ARM64_TLBI_PAALL = 37 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLNXS = 38 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOS = 39 , # [doc = " TLBI operations"] ARM64_TLBI_PAALLOSNXS = 40 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1 = 41 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1IS = 42 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1ISNXS = 43 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1NXS = 44 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OS = 45 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2E1OSNXS = 46 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1 = 47 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1IS = 48 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1ISNXS = 49 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1NXS = 50 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OS = 51 , # [doc = " TLBI operations"] ARM64_TLBI_RIPAS2LE1OSNXS = 52 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOS = 53 , # [doc = " TLBI operations"] ARM64_TLBI_RPALOSNXS = 54 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOS = 55 , # [doc = " TLBI operations"] ARM64_TLBI_RPAOSNXS = 56 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1 = 57 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1IS = 58 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1ISNXS = 59 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1NXS = 60 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OS = 61 , # [doc = " TLBI operations"] ARM64_TLBI_RVAAE1OSNXS = 62 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1 = 63 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1IS = 64 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1ISNXS = 65 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1NXS = 66 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OS = 67 , # [doc = " TLBI operations"] ARM64_TLBI_RVAALE1OSNXS = 68 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1 = 69 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1IS = 70 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1ISNXS = 71 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1NXS = 72 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OS = 73 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE1OSNXS = 74 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2 = 75 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2IS = 76 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2ISNXS = 77 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2NXS = 78 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OS = 79 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE2OSNXS = 80 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3 = 81 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3IS = 82 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3ISNXS = 83 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3NXS = 84 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OS = 85 , # [doc = " TLBI operations"] ARM64_TLBI_RVAE3OSNXS = 86 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1 = 87 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1IS = 88 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1ISNXS = 89 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1NXS = 90 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OS = 91 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE1OSNXS = 92 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2 = 93 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2IS = 94 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2ISNXS = 95 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2NXS = 96 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OS = 97 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE2OSNXS = 98 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3 = 99 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3IS = 100 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3ISNXS = 101 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3NXS = 102 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OS = 103 , # [doc = " TLBI operations"] ARM64_TLBI_RVALE3OSNXS = 104 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1 = 105 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1IS = 106 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1ISNXS = 107 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1NXS = 108 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OS = 109 , # [doc = " TLBI operations"] ARM64_TLBI_VAAE1OSNXS = 110 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1 = 111 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1IS = 112 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1ISNXS = 113 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1NXS = 114 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OS = 115 , # [doc = " TLBI operations"] ARM64_TLBI_VAALE1OSNXS = 116 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1 = 117 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1IS = 118 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1ISNXS = 119 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1NXS = 120 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OS = 121 , # [doc = " TLBI operations"] ARM64_TLBI_VAE1OSNXS = 122 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2 = 123 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2IS = 124 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2ISNXS = 125 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2NXS = 126 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OS = 127 , # [doc = " TLBI operations"] ARM64_TLBI_VAE2OSNXS = 128 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3 = 129 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3IS = 130 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3ISNXS = 131 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3NXS = 132 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OS = 133 , # [doc = " TLBI operations"] ARM64_TLBI_VAE3OSNXS = 134 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1 = 135 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1IS = 136 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1ISNXS = 137 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1NXS = 138 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OS = 139 , # [doc = " TLBI operations"] ARM64_TLBI_VALE1OSNXS = 140 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2 = 141 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2IS = 142 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2ISNXS = 143 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2NXS = 144 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OS = 145 , # [doc = " TLBI operations"] ARM64_TLBI_VALE2OSNXS = 146 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3 = 147 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3IS = 148 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3ISNXS = 149 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3NXS = 150 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OS = 151 , # [doc = " TLBI operations"] ARM64_TLBI_VALE3OSNXS = 152 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1 = 153 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1IS = 154 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1ISNXS = 155 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1NXS = 156 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OS = 157 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLE1OSNXS = 158 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1 = 159 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1IS = 160 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1ISNXS = 161 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1NXS = 162 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OS = 163 , # [doc = " TLBI operations"] ARM64_TLBI_VMALLS12E1OSNXS = 164 , # [doc = " AT operations"] ARM64_AT_S1E1R = 165 , # [doc = " AT operations"] ARM64_AT_S1E2R = 166 , # [doc = " AT operations"] ARM64_AT_S1E3R = 167 , # [doc = " AT operations"] ARM64_AT_S1E1W = 168 , # [doc = " AT operations"] ARM64_AT_S1E2W = 169 , # [doc = " AT operations"] ARM64_AT_S1E3W = 170 , # [doc = " AT operations"] ARM64_AT_S1E0R = 171 , # [doc = " AT operations"] ARM64_AT_S1E0W = 172 , # [doc = " AT operations"] ARM64_AT_S12E1R = 173 , # [doc = " AT operations"] ARM64_AT_S12E1W = 174 , # [doc = " AT operations"] ARM64_AT_S12E0R = 175 , # [doc = " AT operations"] ARM64_AT_S12E0W = 176 , # [doc = " AT operations"] ARM64_AT_S1E1RP = 177 , # [doc = " AT operations"] ARM64_AT_S1E1WP = 178 , # [doc = " DC operations"] ARM64_DC_CGDSW = 179 , # [doc = " DC operations"] ARM64_DC_CGDVAC = 180 , # [doc = " DC operations"] ARM64_DC_CGDVADP = 181 , # [doc = " DC operations"] ARM64_DC_CGDVAP = 182 , # [doc = " DC operations"] ARM64_DC_CGSW = 183 , # [doc = " DC operations"] ARM64_DC_CGVAC = 184 , # [doc = " DC operations"] ARM64_DC_CGVADP = 185 , # [doc = " DC operations"] ARM64_DC_CGVAP = 186 , # [doc = " DC operations"] ARM64_DC_CIGDSW = 187 , # [doc = " DC operations"] ARM64_DC_CIGDVAC = 188 , # [doc = " DC operations"] ARM64_DC_CIGSW = 189 , # [doc = " DC operations"] ARM64_DC_CIGVAC = 190 , # [doc = " DC operations"] ARM64_DC_CISW = 191 , # [doc = " DC operations"] ARM64_DC_CIVAC = 192 , # [doc = " DC operations"] ARM64_DC_CSW = 193 , # [doc = " DC operations"] ARM64_DC_CVAC = 194 , # [doc = " DC operations"] ARM64_DC_CVADP = 195 , # [doc = " DC operations"] ARM64_DC_CVAP = 196 , # [doc = " DC operations"] ARM64_DC_CVAU = 197 , # [doc = " DC operations"] ARM64_DC_GVA = 198 , # [doc = " DC operations"] ARM64_DC_GZVA = 199 , # [doc = " DC operations"] ARM64_DC_IGDSW = 200 , # [doc = " DC operations"] ARM64_DC_IGDVAC = 201 , # [doc = " DC operations"] ARM64_DC_IGSW = 202 , # [doc = " DC operations"] ARM64_DC_IGVAC = 203 , # [doc = " DC operations"] ARM64_DC_ISW = 204 , # [doc = " DC operations"] ARM64_DC_IVAC = 205 , # [doc = " DC operations"] ARM64_DC_ZVA = 206 , # [doc = " IC operations"] ARM64_IC_IALLUIS = 207 , # [doc = " IC operations"] ARM64_IC_IALLU = 208 , # [doc = " IC operations"] ARM64_IC_IVAU = 209 , } # [repr (u32)] # [doc = " SVCR operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_svcr_op { ARM64_SVCR_INVALID = 0 , ARM64_SVCR_SVCRSM = 1 , ARM64_SVCR_SVCRSMZA = 3 , ARM64_SVCR_SVCRZA = 2 , } # [repr (u32)] # [doc = " Prefetch operations (PRFM)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0 , ARM64_PRFM_PLDL1KEEP = 1 , ARM64_PRFM_PLDL1STRM = 2 , ARM64_PRFM_PLDL2KEEP = 3 , ARM64_PRFM_PLDL2STRM = 4 , ARM64_PRFM_PLDL3KEEP = 5 , ARM64_PRFM_PLDL3STRM = 6 , ARM64_PRFM_PLIL1KEEP = 9 , ARM64_PRFM_PLIL1STRM = 10 , ARM64_PRFM_PLIL2KEEP = 11 , ARM64_PRFM_PLIL2STRM = 12 , ARM64_PRFM_PLIL3KEEP = 13 , ARM64_PRFM_PLIL3STRM = 14 , ARM64_PRFM_PSTL1KEEP = 17 , ARM64_PRFM_PSTL1STRM = 18 , ARM64_PRFM_PSTL2KEEP = 19 , ARM64_PRFM_PSTL2STRM = 20 , ARM64_PRFM_PSTL3KEEP = 21 , ARM64_PRFM_PSTL3STRM = 22 , } impl arm64_reg { pub const ARM64_REG_IP0 : arm64_reg = arm64_reg :: ARM64_REG_X16 ; } impl arm64_reg { pub const ARM64_REG_IP1 : arm64_reg = arm64_reg :: ARM64_REG_X17 ; } impl arm64_reg { pub const ARM64_REG_X29 : arm64_reg = arm64_reg :: ARM64_REG_FP ; } impl arm64_reg { pub const ARM64_REG_X30 : arm64_reg = arm64_reg :: ARM64_REG_LR ; } # [repr (u32)] # [doc = " ARM64 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_reg { ARM64_REG_INVALID = 0 , ARM64_REG_FFR = 1 , ARM64_REG_FP = 2 , ARM64_REG_LR = 3 , ARM64_REG_NZCV = 4 , ARM64_REG_SP = 5 , ARM64_REG_VG = 6 , ARM64_REG_WSP = 7 , ARM64_REG_WZR = 8 , ARM64_REG_XZR = 9 , ARM64_REG_ZA = 10 , ARM64_REG_B0 = 11 , ARM64_REG_B1 = 12 , ARM64_REG_B2 = 13 , ARM64_REG_B3 = 14 , ARM64_REG_B4 = 15 , ARM64_REG_B5 = 16 , ARM64_REG_B6 = 17 , ARM64_REG_B7 = 18 , ARM64_REG_B8 = 19 , ARM64_REG_B9 = 20 , ARM64_REG_B10 = 21 , ARM64_REG_B11 = 22 , ARM64_REG_B12 = 23 , ARM64_REG_B13 = 24 , ARM64_REG_B14 = 25 , ARM64_REG_B15 = 26 , ARM64_REG_B16 = 27 , ARM64_REG_B17 = 28 , ARM64_REG_B18 = 29 , ARM64_REG_B19 = 30 , ARM64_REG_B20 = 31 , ARM64_REG_B21 = 32 , ARM64_REG_B22 = 33 , ARM64_REG_B23 = 34 , ARM64_REG_B24 = 35 , ARM64_REG_B25 = 36 , ARM64_REG_B26 = 37 , ARM64_REG_B27 = 38 , ARM64_REG_B28 = 39 , ARM64_REG_B29 = 40 , ARM64_REG_B30 = 41 , ARM64_REG_B31 = 42 , ARM64_REG_D0 = 43 , ARM64_REG_D1 = 44 , ARM64_REG_D2 = 45 , ARM64_REG_D3 = 46 , ARM64_REG_D4 = 47 , ARM64_REG_D5 = 48 , ARM64_REG_D6 = 49 , ARM64_REG_D7 = 50 , ARM64_REG_D8 = 51 , ARM64_REG_D9 = 52 , ARM64_REG_D10 = 53 , ARM64_REG_D11 = 54 , ARM64_REG_D12 = 55 , ARM64_REG_D13 = 56 , ARM64_REG_D14 = 57 , ARM64_REG_D15 = 58 , ARM64_REG_D16 = 59 , ARM64_REG_D17 = 60 , ARM64_REG_D18 = 61 , ARM64_REG_D19 = 62 , ARM64_REG_D20 = 63 , ARM64_REG_D21 = 64 , ARM64_REG_D22 = 65 , ARM64_REG_D23 = 66 , ARM64_REG_D24 = 67 , ARM64_REG_D25 = 68 , ARM64_REG_D26 = 69 , ARM64_REG_D27 = 70 , ARM64_REG_D28 = 71 , ARM64_REG_D29 = 72 , ARM64_REG_D30 = 73 , ARM64_REG_D31 = 74 , ARM64_REG_H0 = 75 , ARM64_REG_H1 = 76 , ARM64_REG_H2 = 77 , ARM64_REG_H3 = 78 , ARM64_REG_H4 = 79 , ARM64_REG_H5 = 80 , ARM64_REG_H6 = 81 , ARM64_REG_H7 = 82 , ARM64_REG_H8 = 83 , ARM64_REG_H9 = 84 , ARM64_REG_H10 = 85 , ARM64_REG_H11 = 86 , ARM64_REG_H12 = 87 , ARM64_REG_H13 = 88 , ARM64_REG_H14 = 89 , ARM64_REG_H15 = 90 , ARM64_REG_H16 = 91 , ARM64_REG_H17 = 92 , ARM64_REG_H18 = 93 , ARM64_REG_H19 = 94 , ARM64_REG_H20 = 95 , ARM64_REG_H21 = 96 , ARM64_REG_H22 = 97 , ARM64_REG_H23 = 98 , ARM64_REG_H24 = 99 , ARM64_REG_H25 = 100 , ARM64_REG_H26 = 101 , ARM64_REG_H27 = 102 , ARM64_REG_H28 = 103 , ARM64_REG_H29 = 104 , ARM64_REG_H30 = 105 , ARM64_REG_H31 = 106 , ARM64_REG_P0 = 107 , ARM64_REG_P1 = 108 , ARM64_REG_P2 = 109 , ARM64_REG_P3 = 110 , ARM64_REG_P4 = 111 , ARM64_REG_P5 = 112 , ARM64_REG_P6 = 113 , ARM64_REG_P7 = 114 , ARM64_REG_P8 = 115 , ARM64_REG_P9 = 116 , ARM64_REG_P10 = 117 , ARM64_REG_P11 = 118 , ARM64_REG_P12 = 119 , ARM64_REG_P13 = 120 , ARM64_REG_P14 = 121 , ARM64_REG_P15 = 122 , ARM64_REG_Q0 = 123 , ARM64_REG_Q1 = 124 , ARM64_REG_Q2 = 125 , ARM64_REG_Q3 = 126 , ARM64_REG_Q4 = 127 , ARM64_REG_Q5 = 128 , ARM64_REG_Q6 = 129 , ARM64_REG_Q7 = 130 , ARM64_REG_Q8 = 131 , ARM64_REG_Q9 = 132 , ARM64_REG_Q10 = 133 , ARM64_REG_Q11 = 134 , ARM64_REG_Q12 = 135 , ARM64_REG_Q13 = 136 , ARM64_REG_Q14 = 137 , ARM64_REG_Q15 = 138 , ARM64_REG_Q16 = 139 , ARM64_REG_Q17 = 140 , ARM64_REG_Q18 = 141 , ARM64_REG_Q19 = 142 , ARM64_REG_Q20 = 143 , ARM64_REG_Q21 = 144 , ARM64_REG_Q22 = 145 , ARM64_REG_Q23 = 146 , ARM64_REG_Q24 = 147 , ARM64_REG_Q25 = 148 , ARM64_REG_Q26 = 149 , ARM64_REG_Q27 = 150 , ARM64_REG_Q28 = 151 , ARM64_REG_Q29 = 152 , ARM64_REG_Q30 = 153 , ARM64_REG_Q31 = 154 , ARM64_REG_S0 = 155 , ARM64_REG_S1 = 156 , ARM64_REG_S2 = 157 , ARM64_REG_S3 = 158 , ARM64_REG_S4 = 159 , ARM64_REG_S5 = 160 , ARM64_REG_S6 = 161 , ARM64_REG_S7 = 162 , ARM64_REG_S8 = 163 , ARM64_REG_S9 = 164 , ARM64_REG_S10 = 165 , ARM64_REG_S11 = 166 , ARM64_REG_S12 = 167 , ARM64_REG_S13 = 168 , ARM64_REG_S14 = 169 , ARM64_REG_S15 = 170 , ARM64_REG_S16 = 171 , ARM64_REG_S17 = 172 , ARM64_REG_S18 = 173 , ARM64_REG_S19 = 174 , ARM64_REG_S20 = 175 , ARM64_REG_S21 = 176 , ARM64_REG_S22 = 177 , ARM64_REG_S23 = 178 , ARM64_REG_S24 = 179 , ARM64_REG_S25 = 180 , ARM64_REG_S26 = 181 , ARM64_REG_S27 = 182 , ARM64_REG_S28 = 183 , ARM64_REG_S29 = 184 , ARM64_REG_S30 = 185 , ARM64_REG_S31 = 186 , ARM64_REG_W0 = 187 , ARM64_REG_W1 = 188 , ARM64_REG_W2 = 189 , ARM64_REG_W3 = 190 , ARM64_REG_W4 = 191 , ARM64_REG_W5 = 192 , ARM64_REG_W6 = 193 , ARM64_REG_W7 = 194 , ARM64_REG_W8 = 195 , ARM64_REG_W9 = 196 , ARM64_REG_W10 = 197 , ARM64_REG_W11 = 198 , ARM64_REG_W12 = 199 , ARM64_REG_W13 = 200 , ARM64_REG_W14 = 201 , ARM64_REG_W15 = 202 , ARM64_REG_W16 = 203 , ARM64_REG_W17 = 204 , ARM64_REG_W18 = 205 , ARM64_REG_W19 = 206 , ARM64_REG_W20 = 207 , ARM64_REG_W21 = 208 , ARM64_REG_W22 = 209 , ARM64_REG_W23 = 210 , ARM64_REG_W24 = 211 , ARM64_REG_W25 = 212 , ARM64_REG_W26 = 213 , ARM64_REG_W27 = 214 , ARM64_REG_W28 = 215 , ARM64_REG_W29 = 216 , ARM64_REG_W30 = 217 , ARM64_REG_X0 = 218 , ARM64_REG_X1 = 219 , ARM64_REG_X2 = 220 , ARM64_REG_X3 = 221 , ARM64_REG_X4 = 222 , ARM64_REG_X5 = 223 , ARM64_REG_X6 = 224 , ARM64_REG_X7 = 225 , ARM64_REG_X8 = 226 , ARM64_REG_X9 = 227 , ARM64_REG_X10 = 228 , ARM64_REG_X11 = 229 , ARM64_REG_X12 = 230 , ARM64_REG_X13 = 231 , ARM64_REG_X14 = 232 , ARM64_REG_X15 = 233 , ARM64_REG_X16 = 234 , ARM64_REG_X17 = 235 , ARM64_REG_X18 = 236 , ARM64_REG_X19 = 237 , ARM64_REG_X20 = 238 , ARM64_REG_X21 = 239 , ARM64_REG_X22 = 240 , ARM64_REG_X23 = 241 , ARM64_REG_X24 = 242 , ARM64_REG_X25 = 243 , ARM64_REG_X26 = 244 , ARM64_REG_X27 = 245 , ARM64_REG_X28 = 246 , ARM64_REG_Z0 = 247 , ARM64_REG_Z1 = 248 , ARM64_REG_Z2 = 249 , ARM64_REG_Z3 = 250 , ARM64_REG_Z4 = 251 , ARM64_REG_Z5 = 252 , ARM64_REG_Z6 = 253 , ARM64_REG_Z7 = 254 , ARM64_REG_Z8 = 255 , ARM64_REG_Z9 = 256 , ARM64_REG_Z10 = 257 , ARM64_REG_Z11 = 258 , ARM64_REG_Z12 = 259 , ARM64_REG_Z13 = 260 , ARM64_REG_Z14 = 261 , ARM64_REG_Z15 = 262 , ARM64_REG_Z16 = 263 , ARM64_REG_Z17 = 264 , ARM64_REG_Z18 = 265 , ARM64_REG_Z19 = 266 , ARM64_REG_Z20 = 267 , ARM64_REG_Z21 = 268 , ARM64_REG_Z22 = 269 , ARM64_REG_Z23 = 270 , ARM64_REG_Z24 = 271 , ARM64_REG_Z25 = 272 , ARM64_REG_Z26 = 273 , ARM64_REG_Z27 = 274 , ARM64_REG_Z28 = 275 , ARM64_REG_Z29 = 276 , ARM64_REG_Z30 = 277 , ARM64_REG_Z31 = 278 , ARM64_REG_ZAB0 = 279 , ARM64_REG_ZAD0 = 280 , ARM64_REG_ZAD1 = 281 , ARM64_REG_ZAD2 = 282 , ARM64_REG_ZAD3 = 283 , ARM64_REG_ZAD4 = 284 , ARM64_REG_ZAD5 = 285 , ARM64_REG_ZAD6 = 286 , ARM64_REG_ZAD7 = 287 , ARM64_REG_ZAH0 = 288 , ARM64_REG_ZAH1 = 289 , ARM64_REG_ZAQ0 = 290 , ARM64_REG_ZAQ1 = 291 , ARM64_REG_ZAQ2 = 292 , ARM64_REG_ZAQ3 = 293 , ARM64_REG_ZAQ4 = 294 , ARM64_REG_ZAQ5 = 295 , ARM64_REG_ZAQ6 = 296 , ARM64_REG_ZAQ7 = 297 , ARM64_REG_ZAQ8 = 298 , ARM64_REG_ZAQ9 = 299 , ARM64_REG_ZAQ10 = 300 , ARM64_REG_ZAQ11 = 301 , ARM64_REG_ZAQ12 = 302 , ARM64_REG_ZAQ13 = 303 , ARM64_REG_ZAQ14 = 304 , ARM64_REG_ZAQ15 = 305 , ARM64_REG_ZAS0 = 306 , ARM64_REG_ZAS1 = 307 , ARM64_REG_ZAS2 = 308 , ARM64_REG_ZAS3 = 309 , ARM64_REG_V0 = 310 , ARM64_REG_V1 = 311 , ARM64_REG_V2 = 312 , ARM64_REG_V3 = 313 , ARM64_REG_V4 = 314 , ARM64_REG_V5 = 315 , ARM64_REG_V6 = 316 , ARM64_REG_V7 = 317 , ARM64_REG_V8 = 318 , ARM64_REG_V9 = 319 , ARM64_REG_V10 = 320 , ARM64_REG_V11 = 321 , ARM64_REG_V12 = 322 , ARM64_REG_V13 = 323 , ARM64_REG_V14 = 324 , ARM64_REG_V15 = 325 , ARM64_REG_V16 = 326 , ARM64_REG_V17 = 327 , ARM64_REG_V18 = 328 , ARM64_REG_V19 = 329 , ARM64_REG_V20 = 330 , ARM64_REG_V21 = 331 , ARM64_REG_V22 = 332 , ARM64_REG_V23 = 333 , ARM64_REG_V24 = 334 , ARM64_REG_V25 = 335 , ARM64_REG_V26 = 336 , ARM64_REG_V27 = 337 , ARM64_REG_V28 = 338 , ARM64_REG_V29 = 339 , ARM64_REG_V30 = 340 , ARM64_REG_V31 = 341 , ARM64_REG_ENDING = 342 , } # [doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_mem { # [doc = "< base register"] pub base : arm64_reg , # [doc = "< index register"] pub index : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_mem"] [:: std :: mem :: size_of :: < arm64_op_mem > () - 12usize] ; ["Alignment of arm64_op_mem"] [:: std :: mem :: align_of :: < arm64_op_mem > () - 4usize] ; ["Offset of field: arm64_op_mem::base"] [:: std :: mem :: offset_of ! (arm64_op_mem , base) - 0usize] ; ["Offset of field: arm64_op_mem::index"] [:: std :: mem :: offset_of ! (arm64_op_mem , index) - 4usize] ; ["Offset of field: arm64_op_mem::disp"] [:: std :: mem :: offset_of ! (arm64_op_mem , disp) - 8usize] ; } ; # [doc = " SME Instruction's operand has index\n This is associated with ARM64_OP_SME_INDEX operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct arm64_op_sme_index { # [doc = "< register being indexed"] pub reg : arm64_reg , # [doc = "< base register"] pub base : arm64_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of arm64_op_sme_index"] [:: std :: mem :: size_of :: < arm64_op_sme_index > () - 12usize] ; ["Alignment of arm64_op_sme_index"] [:: std :: mem :: align_of :: < arm64_op_sme_index > () - 4usize] ; ["Offset of field: arm64_op_sme_index::reg"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , reg) - 0usize] ; ["Offset of field: arm64_op_sme_index::base"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , base) - 4usize] ; ["Offset of field: arm64_op_sme_index::disp"] [:: std :: mem :: offset_of ! (arm64_op_sme_index , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64_op { # [doc = "< Vector Index for some vector operands (or -1 if\n< irrelevant)"] pub vector_index : :: std :: os :: raw :: c_int , # [doc = "< Vector Arrangement Specifier"] pub vas : arm64_vas , pub shift : cs_arm64_op__bindgen_ty_1 , # [doc = "< extender type of this operand"] pub ext : arm64_extender , # [doc = "< operand type"] pub type_ : arm64_op_type , # [doc = "< MSR/MRS SVCR instruction variant."] pub svcr : arm64_svcr_op , pub __bindgen_anon_1 : cs_arm64_op__bindgen_ty_2 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_arm64_op__bindgen_ty_1 { # [doc = "< shifter type of this operand"] pub type_ : arm64_shifter , # [doc = "< shifter value of this operand"] pub value : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_arm64_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , type_) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_1::value"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_1 , value) - 4usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub union cs_arm64_op__bindgen_ty_2 { # [doc = "< register value for REG operand"] pub reg : arm64_reg , # [doc = "< immediate value, or index for C-IMM or IMM operand"] pub imm : i64 , # [doc = "< floating point value for FP operand"] pub fp : f64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : arm64_op_mem , # [doc = "< PState field of MSR instruction."] pub pstate : arm64_pstate , # [doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op,\n< arm64_dc_op, arm64_at_op, arm64_tlbi_op)"] pub sys : arm64_sys_op , # [doc = "< PRFM operation."] pub prefetch : arm64_prefetch_op , # [doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."] pub barrier : arm64_barrier_op , # [doc = "< base/disp value for matrix tile slice\n< instructions."] pub sme_index : arm64_op_sme_index , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_arm64_op__bindgen_ty_2 > () - 16usize] ; ["Alignment of cs_arm64_op__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_arm64_op__bindgen_ty_2 > () - 8usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::reg"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , reg) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::imm"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , imm) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::fp"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , fp) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::mem"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , mem) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::pstate"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , pstate) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sys"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sys) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::prefetch"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , prefetch) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::barrier"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , barrier) - 0usize] ; ["Offset of field: cs_arm64_op__bindgen_ty_2::sme_index"] [:: std :: mem :: offset_of ! (cs_arm64_op__bindgen_ty_2 , sme_index) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op__bindgen_ty_2 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op__bindgen_ty_2 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64_op"] [:: std :: mem :: size_of :: < cs_arm64_op > () - 56usize] ; ["Alignment of cs_arm64_op"] [:: std :: mem :: align_of :: < cs_arm64_op > () - 8usize] ; ["Offset of field: cs_arm64_op::vector_index"] [:: std :: mem :: offset_of ! (cs_arm64_op , vector_index) - 0usize] ; ["Offset of field: cs_arm64_op::vas"] [:: std :: mem :: offset_of ! (cs_arm64_op , vas) - 4usize] ; ["Offset of field: cs_arm64_op::shift"] [:: std :: mem :: offset_of ! (cs_arm64_op , shift) - 8usize] ; ["Offset of field: cs_arm64_op::ext"] [:: std :: mem :: offset_of ! (cs_arm64_op , ext) - 16usize] ; ["Offset of field: cs_arm64_op::type_"] [:: std :: mem :: offset_of ! (cs_arm64_op , type_) - 20usize] ; ["Offset of field: cs_arm64_op::svcr"] [:: std :: mem :: offset_of ! (cs_arm64_op , svcr) - 24usize] ; ["Offset of field: cs_arm64_op::access"] [:: std :: mem :: offset_of ! (cs_arm64_op , access) - 48usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, svcr: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . svcr , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_arm64 { # [doc = "< conditional code for this insn"] pub cc : arm64_cc , # [doc = "< does this insn update flags?"] pub update_flags : bool , # [doc = "< does this insn request writeback? 'True' means 'yes'"] pub writeback : bool , # [doc = "< only set if writeback is 'True', if 'False' pre-index, otherwise post."] pub post_index : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_arm64_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_arm64"] [:: std :: mem :: size_of :: < cs_arm64 > () - 456usize] ; ["Alignment of cs_arm64"] [:: std :: mem :: align_of :: < cs_arm64 > () - 8usize] ; ["Offset of field: cs_arm64::cc"] [:: std :: mem :: offset_of ! (cs_arm64 , cc) - 0usize] ; ["Offset of field: cs_arm64::update_flags"] [:: std :: mem :: offset_of ! (cs_arm64 , update_flags) - 4usize] ; ["Offset of field: cs_arm64::writeback"] [:: std :: mem :: offset_of ! (cs_arm64 , writeback) - 5usize] ; ["Offset of field: cs_arm64::post_index"] [:: std :: mem :: offset_of ! (cs_arm64 , post_index) - 6usize] ; ["Offset of field: cs_arm64::op_count"] [:: std :: mem :: offset_of ! (cs_arm64 , op_count) - 7usize] ; ["Offset of field: cs_arm64::operands"] [:: std :: mem :: offset_of ! (cs_arm64 , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_arm64 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, post_index: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . post_index , self . op_count , self . operands) } } # [repr (u32)] # [doc = " ARM64 instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn { ARM64_INS_INVALID = 0 , ARM64_INS_ABS = 1 , ARM64_INS_ADC = 2 , ARM64_INS_ADCLB = 3 , ARM64_INS_ADCLT = 4 , ARM64_INS_ADCS = 5 , ARM64_INS_ADD = 6 , ARM64_INS_ADDG = 7 , ARM64_INS_ADDHA = 8 , ARM64_INS_ADDHN = 9 , ARM64_INS_ADDHN2 = 10 , ARM64_INS_ADDHNB = 11 , ARM64_INS_ADDHNT = 12 , ARM64_INS_ADDP = 13 , ARM64_INS_ADDPL = 14 , ARM64_INS_ADDS = 15 , ARM64_INS_ADDV = 16 , ARM64_INS_ADDVA = 17 , ARM64_INS_ADDVL = 18 , ARM64_INS_ADR = 19 , ARM64_INS_ADRP = 20 , ARM64_INS_AESD = 21 , ARM64_INS_AESE = 22 , ARM64_INS_AESIMC = 23 , ARM64_INS_AESMC = 24 , ARM64_INS_AND = 25 , ARM64_INS_ANDS = 26 , ARM64_INS_ANDV = 27 , ARM64_INS_ASR = 28 , ARM64_INS_ASRD = 29 , ARM64_INS_ASRR = 30 , ARM64_INS_ASRV = 31 , ARM64_INS_AUTDA = 32 , ARM64_INS_AUTDB = 33 , ARM64_INS_AUTDZA = 34 , ARM64_INS_AUTDZB = 35 , ARM64_INS_AUTIA = 36 , ARM64_INS_AUTIA1716 = 37 , ARM64_INS_AUTIASP = 38 , ARM64_INS_AUTIAZ = 39 , ARM64_INS_AUTIB = 40 , ARM64_INS_AUTIB1716 = 41 , ARM64_INS_AUTIBSP = 42 , ARM64_INS_AUTIBZ = 43 , ARM64_INS_AUTIZA = 44 , ARM64_INS_AUTIZB = 45 , ARM64_INS_AXFLAG = 46 , ARM64_INS_B = 47 , ARM64_INS_BC = 48 , ARM64_INS_BCAX = 49 , ARM64_INS_BDEP = 50 , ARM64_INS_BEXT = 51 , ARM64_INS_BFCVT = 52 , ARM64_INS_BFCVTN = 53 , ARM64_INS_BFCVTN2 = 54 , ARM64_INS_BFCVTNT = 55 , ARM64_INS_BFDOT = 56 , ARM64_INS_BFM = 57 , ARM64_INS_BFMLALB = 58 , ARM64_INS_BFMLALT = 59 , ARM64_INS_BFMMLA = 60 , ARM64_INS_BFMOPA = 61 , ARM64_INS_BFMOPS = 62 , ARM64_INS_BGRP = 63 , ARM64_INS_BIC = 64 , ARM64_INS_BICS = 65 , ARM64_INS_BIF = 66 , ARM64_INS_BIT = 67 , ARM64_INS_BL = 68 , ARM64_INS_BLR = 69 , ARM64_INS_BLRAA = 70 , ARM64_INS_BLRAAZ = 71 , ARM64_INS_BLRAB = 72 , ARM64_INS_BLRABZ = 73 , ARM64_INS_BR = 74 , ARM64_INS_BRAA = 75 , ARM64_INS_BRAAZ = 76 , ARM64_INS_BRAB = 77 , ARM64_INS_BRABZ = 78 , ARM64_INS_BRB = 79 , ARM64_INS_BRK = 80 , ARM64_INS_BRKA = 81 , ARM64_INS_BRKAS = 82 , ARM64_INS_BRKB = 83 , ARM64_INS_BRKBS = 84 , ARM64_INS_BRKN = 85 , ARM64_INS_BRKNS = 86 , ARM64_INS_BRKPA = 87 , ARM64_INS_BRKPAS = 88 , ARM64_INS_BRKPB = 89 , ARM64_INS_BRKPBS = 90 , ARM64_INS_BSL = 91 , ARM64_INS_BSL1N = 92 , ARM64_INS_BSL2N = 93 , ARM64_INS_BTI = 94 , ARM64_INS_CADD = 95 , ARM64_INS_CAS = 96 , ARM64_INS_CASA = 97 , ARM64_INS_CASAB = 98 , ARM64_INS_CASAH = 99 , ARM64_INS_CASAL = 100 , ARM64_INS_CASALB = 101 , ARM64_INS_CASALH = 102 , ARM64_INS_CASB = 103 , ARM64_INS_CASH = 104 , ARM64_INS_CASL = 105 , ARM64_INS_CASLB = 106 , ARM64_INS_CASLH = 107 , ARM64_INS_CASP = 108 , ARM64_INS_CASPA = 109 , ARM64_INS_CASPAL = 110 , ARM64_INS_CASPL = 111 , ARM64_INS_CBNZ = 112 , ARM64_INS_CBZ = 113 , ARM64_INS_CCMN = 114 , ARM64_INS_CCMP = 115 , ARM64_INS_CDOT = 116 , ARM64_INS_CFINV = 117 , ARM64_INS_CINC = 118 , ARM64_INS_CINV = 119 , ARM64_INS_CLASTA = 120 , ARM64_INS_CLASTB = 121 , ARM64_INS_CLREX = 122 , ARM64_INS_CLS = 123 , ARM64_INS_CLZ = 124 , ARM64_INS_CMEQ = 125 , ARM64_INS_CMGE = 126 , ARM64_INS_CMGT = 127 , ARM64_INS_CMHI = 128 , ARM64_INS_CMHS = 129 , ARM64_INS_CMLA = 130 , ARM64_INS_CMLE = 131 , ARM64_INS_CMLO = 132 , ARM64_INS_CMLS = 133 , ARM64_INS_CMLT = 134 , ARM64_INS_CMN = 135 , ARM64_INS_CMP = 136 , ARM64_INS_CMPEQ = 137 , ARM64_INS_CMPGE = 138 , ARM64_INS_CMPGT = 139 , ARM64_INS_CMPHI = 140 , ARM64_INS_CMPHS = 141 , ARM64_INS_CMPLE = 142 , ARM64_INS_CMPLO = 143 , ARM64_INS_CMPLS = 144 , ARM64_INS_CMPLT = 145 , ARM64_INS_CMPNE = 146 , ARM64_INS_CMPP = 147 , ARM64_INS_CMTST = 148 , ARM64_INS_CNEG = 149 , ARM64_INS_CNOT = 150 , ARM64_INS_CNT = 151 , ARM64_INS_CNTB = 152 , ARM64_INS_CNTD = 153 , ARM64_INS_CNTH = 154 , ARM64_INS_CNTP = 155 , ARM64_INS_CNTW = 156 , ARM64_INS_COMPACT = 157 , ARM64_INS_CPY = 158 , ARM64_INS_CPYE = 159 , ARM64_INS_CPYEN = 160 , ARM64_INS_CPYERN = 161 , ARM64_INS_CPYERT = 162 , ARM64_INS_CPYERTN = 163 , ARM64_INS_CPYERTRN = 164 , ARM64_INS_CPYERTWN = 165 , ARM64_INS_CPYET = 166 , ARM64_INS_CPYETN = 167 , ARM64_INS_CPYETRN = 168 , ARM64_INS_CPYETWN = 169 , ARM64_INS_CPYEWN = 170 , ARM64_INS_CPYEWT = 171 , ARM64_INS_CPYEWTN = 172 , ARM64_INS_CPYEWTRN = 173 , ARM64_INS_CPYEWTWN = 174 , ARM64_INS_CPYFE = 175 , ARM64_INS_CPYFEN = 176 , ARM64_INS_CPYFERN = 177 , ARM64_INS_CPYFERT = 178 , ARM64_INS_CPYFERTN = 179 , ARM64_INS_CPYFERTRN = 180 , ARM64_INS_CPYFERTWN = 181 , ARM64_INS_CPYFET = 182 , ARM64_INS_CPYFETN = 183 , ARM64_INS_CPYFETRN = 184 , ARM64_INS_CPYFETWN = 185 , ARM64_INS_CPYFEWN = 186 , ARM64_INS_CPYFEWT = 187 , ARM64_INS_CPYFEWTN = 188 , ARM64_INS_CPYFEWTRN = 189 , ARM64_INS_CPYFEWTWN = 190 , ARM64_INS_CPYFM = 191 , ARM64_INS_CPYFMN = 192 , ARM64_INS_CPYFMRN = 193 , ARM64_INS_CPYFMRT = 194 , ARM64_INS_CPYFMRTN = 195 , ARM64_INS_CPYFMRTRN = 196 , ARM64_INS_CPYFMRTWN = 197 , ARM64_INS_CPYFMT = 198 , ARM64_INS_CPYFMTN = 199 , ARM64_INS_CPYFMTRN = 200 , ARM64_INS_CPYFMTWN = 201 , ARM64_INS_CPYFMWN = 202 , ARM64_INS_CPYFMWT = 203 , ARM64_INS_CPYFMWTN = 204 , ARM64_INS_CPYFMWTRN = 205 , ARM64_INS_CPYFMWTWN = 206 , ARM64_INS_CPYFP = 207 , ARM64_INS_CPYFPN = 208 , ARM64_INS_CPYFPRN = 209 , ARM64_INS_CPYFPRT = 210 , ARM64_INS_CPYFPRTN = 211 , ARM64_INS_CPYFPRTRN = 212 , ARM64_INS_CPYFPRTWN = 213 , ARM64_INS_CPYFPT = 214 , ARM64_INS_CPYFPTN = 215 , ARM64_INS_CPYFPTRN = 216 , ARM64_INS_CPYFPTWN = 217 , ARM64_INS_CPYFPWN = 218 , ARM64_INS_CPYFPWT = 219 , ARM64_INS_CPYFPWTN = 220 , ARM64_INS_CPYFPWTRN = 221 , ARM64_INS_CPYFPWTWN = 222 , ARM64_INS_CPYM = 223 , ARM64_INS_CPYMN = 224 , ARM64_INS_CPYMRN = 225 , ARM64_INS_CPYMRT = 226 , ARM64_INS_CPYMRTN = 227 , ARM64_INS_CPYMRTRN = 228 , ARM64_INS_CPYMRTWN = 229 , ARM64_INS_CPYMT = 230 , ARM64_INS_CPYMTN = 231 , ARM64_INS_CPYMTRN = 232 , ARM64_INS_CPYMTWN = 233 , ARM64_INS_CPYMWN = 234 , ARM64_INS_CPYMWT = 235 , ARM64_INS_CPYMWTN = 236 , ARM64_INS_CPYMWTRN = 237 , ARM64_INS_CPYMWTWN = 238 , ARM64_INS_CPYP = 239 , ARM64_INS_CPYPN = 240 , ARM64_INS_CPYPRN = 241 , ARM64_INS_CPYPRT = 242 , ARM64_INS_CPYPRTN = 243 , ARM64_INS_CPYPRTRN = 244 , ARM64_INS_CPYPRTWN = 245 , ARM64_INS_CPYPT = 246 , ARM64_INS_CPYPTN = 247 , ARM64_INS_CPYPTRN = 248 , ARM64_INS_CPYPTWN = 249 , ARM64_INS_CPYPWN = 250 , ARM64_INS_CPYPWT = 251 , ARM64_INS_CPYPWTN = 252 , ARM64_INS_CPYPWTRN = 253 , ARM64_INS_CPYPWTWN = 254 , ARM64_INS_CRC32B = 255 , ARM64_INS_CRC32CB = 256 , ARM64_INS_CRC32CH = 257 , ARM64_INS_CRC32CW = 258 , ARM64_INS_CRC32CX = 259 , ARM64_INS_CRC32H = 260 , ARM64_INS_CRC32W = 261 , ARM64_INS_CRC32X = 262 , ARM64_INS_CSDB = 263 , ARM64_INS_CSEL = 264 , ARM64_INS_CSET = 265 , ARM64_INS_CSETM = 266 , ARM64_INS_CSINC = 267 , ARM64_INS_CSINV = 268 , ARM64_INS_CSNEG = 269 , ARM64_INS_CTERMEQ = 270 , ARM64_INS_CTERMNE = 271 , ARM64_INS_DCPS1 = 272 , ARM64_INS_DCPS2 = 273 , ARM64_INS_DCPS3 = 274 , ARM64_INS_DECB = 275 , ARM64_INS_DECD = 276 , ARM64_INS_DECH = 277 , ARM64_INS_DECP = 278 , ARM64_INS_DECW = 279 , ARM64_INS_DFB = 280 , ARM64_INS_DGH = 281 , ARM64_INS_DMB = 282 , ARM64_INS_DRPS = 283 , ARM64_INS_DSB = 284 , ARM64_INS_DUP = 285 , ARM64_INS_DUPM = 286 , ARM64_INS_EON = 287 , ARM64_INS_EOR = 288 , ARM64_INS_EOR3 = 289 , ARM64_INS_EORBT = 290 , ARM64_INS_EORS = 291 , ARM64_INS_EORTB = 292 , ARM64_INS_EORV = 293 , ARM64_INS_ERET = 294 , ARM64_INS_ERETAA = 295 , ARM64_INS_ERETAB = 296 , ARM64_INS_ESB = 297 , ARM64_INS_EXT = 298 , ARM64_INS_EXTR = 299 , ARM64_INS_FABD = 300 , ARM64_INS_FABS = 301 , ARM64_INS_FACGE = 302 , ARM64_INS_FACGT = 303 , ARM64_INS_FACLE = 304 , ARM64_INS_FACLT = 305 , ARM64_INS_FADD = 306 , ARM64_INS_FADDA = 307 , ARM64_INS_FADDP = 308 , ARM64_INS_FADDV = 309 , ARM64_INS_FCADD = 310 , ARM64_INS_FCCMP = 311 , ARM64_INS_FCCMPE = 312 , ARM64_INS_FCMEQ = 313 , ARM64_INS_FCMGE = 314 , ARM64_INS_FCMGT = 315 , ARM64_INS_FCMLA = 316 , ARM64_INS_FCMLE = 317 , ARM64_INS_FCMLT = 318 , ARM64_INS_FCMNE = 319 , ARM64_INS_FCMP = 320 , ARM64_INS_FCMPE = 321 , ARM64_INS_FCMUO = 322 , ARM64_INS_FCPY = 323 , ARM64_INS_FCSEL = 324 , ARM64_INS_FCVT = 325 , ARM64_INS_FCVTAS = 326 , ARM64_INS_FCVTAU = 327 , ARM64_INS_FCVTL = 328 , ARM64_INS_FCVTL2 = 329 , ARM64_INS_FCVTLT = 330 , ARM64_INS_FCVTMS = 331 , ARM64_INS_FCVTMU = 332 , ARM64_INS_FCVTN = 333 , ARM64_INS_FCVTN2 = 334 , ARM64_INS_FCVTNS = 335 , ARM64_INS_FCVTNT = 336 , ARM64_INS_FCVTNU = 337 , ARM64_INS_FCVTPS = 338 , ARM64_INS_FCVTPU = 339 , ARM64_INS_FCVTX = 340 , ARM64_INS_FCVTXN = 341 , ARM64_INS_FCVTXN2 = 342 , ARM64_INS_FCVTXNT = 343 , ARM64_INS_FCVTZS = 344 , ARM64_INS_FCVTZU = 345 , ARM64_INS_FDIV = 346 , ARM64_INS_FDIVR = 347 , ARM64_INS_FDUP = 348 , ARM64_INS_FEXPA = 349 , ARM64_INS_FJCVTZS = 350 , ARM64_INS_FLOGB = 351 , ARM64_INS_FMAD = 352 , ARM64_INS_FMADD = 353 , ARM64_INS_FMAX = 354 , ARM64_INS_FMAXNM = 355 , ARM64_INS_FMAXNMP = 356 , ARM64_INS_FMAXNMV = 357 , ARM64_INS_FMAXP = 358 , ARM64_INS_FMAXV = 359 , ARM64_INS_FMIN = 360 , ARM64_INS_FMINNM = 361 , ARM64_INS_FMINNMP = 362 , ARM64_INS_FMINNMV = 363 , ARM64_INS_FMINP = 364 , ARM64_INS_FMINV = 365 , ARM64_INS_FMLA = 366 , ARM64_INS_FMLAL = 367 , ARM64_INS_FMLAL2 = 368 , ARM64_INS_FMLALB = 369 , ARM64_INS_FMLALT = 370 , ARM64_INS_FMLS = 371 , ARM64_INS_FMLSL = 372 , ARM64_INS_FMLSL2 = 373 , ARM64_INS_FMLSLB = 374 , ARM64_INS_FMLSLT = 375 , ARM64_INS_FMMLA = 376 , ARM64_INS_FMOPA = 377 , ARM64_INS_FMOPS = 378 , ARM64_INS_FMOV = 379 , ARM64_INS_FMSB = 380 , ARM64_INS_FMSUB = 381 , ARM64_INS_FMUL = 382 , ARM64_INS_FMULX = 383 , ARM64_INS_FNEG = 384 , ARM64_INS_FNMAD = 385 , ARM64_INS_FNMADD = 386 , ARM64_INS_FNMLA = 387 , ARM64_INS_FNMLS = 388 , ARM64_INS_FNMSB = 389 , ARM64_INS_FNMSUB = 390 , ARM64_INS_FNMUL = 391 , ARM64_INS_FRECPE = 392 , ARM64_INS_FRECPS = 393 , ARM64_INS_FRECPX = 394 , ARM64_INS_FRINT32X = 395 , ARM64_INS_FRINT32Z = 396 , ARM64_INS_FRINT64X = 397 , ARM64_INS_FRINT64Z = 398 , ARM64_INS_FRINTA = 399 , ARM64_INS_FRINTI = 400 , ARM64_INS_FRINTM = 401 , ARM64_INS_FRINTN = 402 , ARM64_INS_FRINTP = 403 , ARM64_INS_FRINTX = 404 , ARM64_INS_FRINTZ = 405 , ARM64_INS_FRSQRTE = 406 , ARM64_INS_FRSQRTS = 407 , ARM64_INS_FSCALE = 408 , ARM64_INS_FSQRT = 409 , ARM64_INS_FSUB = 410 , ARM64_INS_FSUBR = 411 , ARM64_INS_FTMAD = 412 , ARM64_INS_FTSMUL = 413 , ARM64_INS_FTSSEL = 414 , ARM64_INS_GMI = 415 , ARM64_INS_HINT = 416 , ARM64_INS_HISTCNT = 417 , ARM64_INS_HISTSEG = 418 , ARM64_INS_HLT = 419 , ARM64_INS_HVC = 420 , ARM64_INS_INCB = 421 , ARM64_INS_INCD = 422 , ARM64_INS_INCH = 423 , ARM64_INS_INCP = 424 , ARM64_INS_INCW = 425 , ARM64_INS_INDEX = 426 , ARM64_INS_INS = 427 , ARM64_INS_INSR = 428 , ARM64_INS_IRG = 429 , ARM64_INS_ISB = 430 , ARM64_INS_LASTA = 431 , ARM64_INS_LASTB = 432 , ARM64_INS_LD1 = 433 , ARM64_INS_LD1B = 434 , ARM64_INS_LD1D = 435 , ARM64_INS_LD1H = 436 , ARM64_INS_LD1Q = 437 , ARM64_INS_LD1R = 438 , ARM64_INS_LD1RB = 439 , ARM64_INS_LD1RD = 440 , ARM64_INS_LD1RH = 441 , ARM64_INS_LD1ROB = 442 , ARM64_INS_LD1ROD = 443 , ARM64_INS_LD1ROH = 444 , ARM64_INS_LD1ROW = 445 , ARM64_INS_LD1RQB = 446 , ARM64_INS_LD1RQD = 447 , ARM64_INS_LD1RQH = 448 , ARM64_INS_LD1RQW = 449 , ARM64_INS_LD1RSB = 450 , ARM64_INS_LD1RSH = 451 , ARM64_INS_LD1RSW = 452 , ARM64_INS_LD1RW = 453 , ARM64_INS_LD1SB = 454 , ARM64_INS_LD1SH = 455 , ARM64_INS_LD1SW = 456 , ARM64_INS_LD1W = 457 , ARM64_INS_LD2 = 458 , ARM64_INS_LD2B = 459 , ARM64_INS_LD2D = 460 , ARM64_INS_LD2H = 461 , ARM64_INS_LD2R = 462 , ARM64_INS_LD2W = 463 , ARM64_INS_LD3 = 464 , ARM64_INS_LD3B = 465 , ARM64_INS_LD3D = 466 , ARM64_INS_LD3H = 467 , ARM64_INS_LD3R = 468 , ARM64_INS_LD3W = 469 , ARM64_INS_LD4 = 470 , ARM64_INS_LD4B = 471 , ARM64_INS_LD4D = 472 , ARM64_INS_LD4H = 473 , ARM64_INS_LD4R = 474 , ARM64_INS_LD4W = 475 , ARM64_INS_LD64B = 476 , ARM64_INS_LDADD = 477 , ARM64_INS_LDADDA = 478 , ARM64_INS_LDADDAB = 479 , ARM64_INS_LDADDAH = 480 , ARM64_INS_LDADDAL = 481 , ARM64_INS_LDADDALB = 482 , ARM64_INS_LDADDALH = 483 , ARM64_INS_LDADDB = 484 , ARM64_INS_LDADDH = 485 , ARM64_INS_LDADDL = 486 , ARM64_INS_LDADDLB = 487 , ARM64_INS_LDADDLH = 488 , ARM64_INS_LDAPR = 489 , ARM64_INS_LDAPRB = 490 , ARM64_INS_LDAPRH = 491 , ARM64_INS_LDAPUR = 492 , ARM64_INS_LDAPURB = 493 , ARM64_INS_LDAPURH = 494 , ARM64_INS_LDAPURSB = 495 , ARM64_INS_LDAPURSH = 496 , ARM64_INS_LDAPURSW = 497 , ARM64_INS_LDAR = 498 , ARM64_INS_LDARB = 499 , ARM64_INS_LDARH = 500 , ARM64_INS_LDAXP = 501 , ARM64_INS_LDAXR = 502 , ARM64_INS_LDAXRB = 503 , ARM64_INS_LDAXRH = 504 , ARM64_INS_LDCLR = 505 , ARM64_INS_LDCLRA = 506 , ARM64_INS_LDCLRAB = 507 , ARM64_INS_LDCLRAH = 508 , ARM64_INS_LDCLRAL = 509 , ARM64_INS_LDCLRALB = 510 , ARM64_INS_LDCLRALH = 511 , ARM64_INS_LDCLRB = 512 , ARM64_INS_LDCLRH = 513 , ARM64_INS_LDCLRL = 514 , ARM64_INS_LDCLRLB = 515 , ARM64_INS_LDCLRLH = 516 , ARM64_INS_LDEOR = 517 , ARM64_INS_LDEORA = 518 , ARM64_INS_LDEORAB = 519 , ARM64_INS_LDEORAH = 520 , ARM64_INS_LDEORAL = 521 , ARM64_INS_LDEORALB = 522 , ARM64_INS_LDEORALH = 523 , ARM64_INS_LDEORB = 524 , ARM64_INS_LDEORH = 525 , ARM64_INS_LDEORL = 526 , ARM64_INS_LDEORLB = 527 , ARM64_INS_LDEORLH = 528 , ARM64_INS_LDFF1B = 529 , ARM64_INS_LDFF1D = 530 , ARM64_INS_LDFF1H = 531 , ARM64_INS_LDFF1SB = 532 , ARM64_INS_LDFF1SH = 533 , ARM64_INS_LDFF1SW = 534 , ARM64_INS_LDFF1W = 535 , ARM64_INS_LDG = 536 , ARM64_INS_LDGM = 537 , ARM64_INS_LDLAR = 538 , ARM64_INS_LDLARB = 539 , ARM64_INS_LDLARH = 540 , ARM64_INS_LDNF1B = 541 , ARM64_INS_LDNF1D = 542 , ARM64_INS_LDNF1H = 543 , ARM64_INS_LDNF1SB = 544 , ARM64_INS_LDNF1SH = 545 , ARM64_INS_LDNF1SW = 546 , ARM64_INS_LDNF1W = 547 , ARM64_INS_LDNP = 548 , ARM64_INS_LDNT1B = 549 , ARM64_INS_LDNT1D = 550 , ARM64_INS_LDNT1H = 551 , ARM64_INS_LDNT1SB = 552 , ARM64_INS_LDNT1SH = 553 , ARM64_INS_LDNT1SW = 554 , ARM64_INS_LDNT1W = 555 , ARM64_INS_LDP = 556 , ARM64_INS_LDPSW = 557 , ARM64_INS_LDR = 558 , ARM64_INS_LDRAA = 559 , ARM64_INS_LDRAB = 560 , ARM64_INS_LDRB = 561 , ARM64_INS_LDRH = 562 , ARM64_INS_LDRSB = 563 , ARM64_INS_LDRSH = 564 , ARM64_INS_LDRSW = 565 , ARM64_INS_LDSET = 566 , ARM64_INS_LDSETA = 567 , ARM64_INS_LDSETAB = 568 , ARM64_INS_LDSETAH = 569 , ARM64_INS_LDSETAL = 570 , ARM64_INS_LDSETALB = 571 , ARM64_INS_LDSETALH = 572 , ARM64_INS_LDSETB = 573 , ARM64_INS_LDSETH = 574 , ARM64_INS_LDSETL = 575 , ARM64_INS_LDSETLB = 576 , ARM64_INS_LDSETLH = 577 , ARM64_INS_LDSMAX = 578 , ARM64_INS_LDSMAXA = 579 , ARM64_INS_LDSMAXAB = 580 , ARM64_INS_LDSMAXAH = 581 , ARM64_INS_LDSMAXAL = 582 , ARM64_INS_LDSMAXALB = 583 , ARM64_INS_LDSMAXALH = 584 , ARM64_INS_LDSMAXB = 585 , ARM64_INS_LDSMAXH = 586 , ARM64_INS_LDSMAXL = 587 , ARM64_INS_LDSMAXLB = 588 , ARM64_INS_LDSMAXLH = 589 , ARM64_INS_LDSMIN = 590 , ARM64_INS_LDSMINA = 591 , ARM64_INS_LDSMINAB = 592 , ARM64_INS_LDSMINAH = 593 , ARM64_INS_LDSMINAL = 594 , ARM64_INS_LDSMINALB = 595 , ARM64_INS_LDSMINALH = 596 , ARM64_INS_LDSMINB = 597 , ARM64_INS_LDSMINH = 598 , ARM64_INS_LDSMINL = 599 , ARM64_INS_LDSMINLB = 600 , ARM64_INS_LDSMINLH = 601 , ARM64_INS_LDTR = 602 , ARM64_INS_LDTRB = 603 , ARM64_INS_LDTRH = 604 , ARM64_INS_LDTRSB = 605 , ARM64_INS_LDTRSH = 606 , ARM64_INS_LDTRSW = 607 , ARM64_INS_LDUMAX = 608 , ARM64_INS_LDUMAXA = 609 , ARM64_INS_LDUMAXAB = 610 , ARM64_INS_LDUMAXAH = 611 , ARM64_INS_LDUMAXAL = 612 , ARM64_INS_LDUMAXALB = 613 , ARM64_INS_LDUMAXALH = 614 , ARM64_INS_LDUMAXB = 615 , ARM64_INS_LDUMAXH = 616 , ARM64_INS_LDUMAXL = 617 , ARM64_INS_LDUMAXLB = 618 , ARM64_INS_LDUMAXLH = 619 , ARM64_INS_LDUMIN = 620 , ARM64_INS_LDUMINA = 621 , ARM64_INS_LDUMINAB = 622 , ARM64_INS_LDUMINAH = 623 , ARM64_INS_LDUMINAL = 624 , ARM64_INS_LDUMINALB = 625 , ARM64_INS_LDUMINALH = 626 , ARM64_INS_LDUMINB = 627 , ARM64_INS_LDUMINH = 628 , ARM64_INS_LDUMINL = 629 , ARM64_INS_LDUMINLB = 630 , ARM64_INS_LDUMINLH = 631 , ARM64_INS_LDUR = 632 , ARM64_INS_LDURB = 633 , ARM64_INS_LDURH = 634 , ARM64_INS_LDURSB = 635 , ARM64_INS_LDURSH = 636 , ARM64_INS_LDURSW = 637 , ARM64_INS_LDXP = 638 , ARM64_INS_LDXR = 639 , ARM64_INS_LDXRB = 640 , ARM64_INS_LDXRH = 641 , ARM64_INS_LSL = 642 , ARM64_INS_LSLR = 643 , ARM64_INS_LSLV = 644 , ARM64_INS_LSR = 645 , ARM64_INS_LSRR = 646 , ARM64_INS_LSRV = 647 , ARM64_INS_MAD = 648 , ARM64_INS_MADD = 649 , ARM64_INS_MATCH = 650 , ARM64_INS_MLA = 651 , ARM64_INS_MLS = 652 , ARM64_INS_MNEG = 653 , ARM64_INS_MOV = 654 , ARM64_INS_MOVA = 655 , ARM64_INS_MOVI = 656 , ARM64_INS_MOVK = 657 , ARM64_INS_MOVN = 658 , ARM64_INS_MOVPRFX = 659 , ARM64_INS_MOVS = 660 , ARM64_INS_MOVZ = 661 , ARM64_INS_MRS = 662 , ARM64_INS_MSB = 663 , ARM64_INS_MSR = 664 , ARM64_INS_MSUB = 665 , ARM64_INS_MUL = 666 , ARM64_INS_MVN = 667 , ARM64_INS_MVNI = 668 , ARM64_INS_NAND = 669 , ARM64_INS_NANDS = 670 , ARM64_INS_NBSL = 671 , ARM64_INS_NEG = 672 , ARM64_INS_NEGS = 673 , ARM64_INS_NGC = 674 , ARM64_INS_NGCS = 675 , ARM64_INS_NMATCH = 676 , ARM64_INS_NOP = 677 , ARM64_INS_NOR = 678 , ARM64_INS_NORS = 679 , ARM64_INS_NOT = 680 , ARM64_INS_NOTS = 681 , ARM64_INS_ORN = 682 , ARM64_INS_ORNS = 683 , ARM64_INS_ORR = 684 , ARM64_INS_ORRS = 685 , ARM64_INS_ORV = 686 , ARM64_INS_PACDA = 687 , ARM64_INS_PACDB = 688 , ARM64_INS_PACDZA = 689 , ARM64_INS_PACDZB = 690 , ARM64_INS_PACGA = 691 , ARM64_INS_PACIA = 692 , ARM64_INS_PACIA1716 = 693 , ARM64_INS_PACIASP = 694 , ARM64_INS_PACIAZ = 695 , ARM64_INS_PACIB = 696 , ARM64_INS_PACIB1716 = 697 , ARM64_INS_PACIBSP = 698 , ARM64_INS_PACIBZ = 699 , ARM64_INS_PACIZA = 700 , ARM64_INS_PACIZB = 701 , ARM64_INS_PFALSE = 702 , ARM64_INS_PFIRST = 703 , ARM64_INS_PMUL = 704 , ARM64_INS_PMULL = 705 , ARM64_INS_PMULL2 = 706 , ARM64_INS_PMULLB = 707 , ARM64_INS_PMULLT = 708 , ARM64_INS_PNEXT = 709 , ARM64_INS_PRFB = 710 , ARM64_INS_PRFD = 711 , ARM64_INS_PRFH = 712 , ARM64_INS_PRFM = 713 , ARM64_INS_PRFUM = 714 , ARM64_INS_PRFW = 715 , ARM64_INS_PSB = 716 , ARM64_INS_PSEL = 717 , ARM64_INS_PSSBB = 718 , ARM64_INS_PTEST = 719 , ARM64_INS_PTRUE = 720 , ARM64_INS_PTRUES = 721 , ARM64_INS_PUNPKHI = 722 , ARM64_INS_PUNPKLO = 723 , ARM64_INS_RADDHN = 724 , ARM64_INS_RADDHN2 = 725 , ARM64_INS_RADDHNB = 726 , ARM64_INS_RADDHNT = 727 , ARM64_INS_RAX1 = 728 , ARM64_INS_RBIT = 729 , ARM64_INS_RDFFR = 730 , ARM64_INS_RDFFRS = 731 , ARM64_INS_RDVL = 732 , ARM64_INS_RET = 733 , ARM64_INS_RETAA = 734 , ARM64_INS_RETAB = 735 , ARM64_INS_REV = 736 , ARM64_INS_REV16 = 737 , ARM64_INS_REV32 = 738 , ARM64_INS_REV64 = 739 , ARM64_INS_REVB = 740 , ARM64_INS_REVD = 741 , ARM64_INS_REVH = 742 , ARM64_INS_REVW = 743 , ARM64_INS_RMIF = 744 , ARM64_INS_ROR = 745 , ARM64_INS_RORV = 746 , ARM64_INS_RSHRN = 747 , ARM64_INS_RSHRN2 = 748 , ARM64_INS_RSHRNB = 749 , ARM64_INS_RSHRNT = 750 , ARM64_INS_RSUBHN = 751 , ARM64_INS_RSUBHN2 = 752 , ARM64_INS_RSUBHNB = 753 , ARM64_INS_RSUBHNT = 754 , ARM64_INS_SABA = 755 , ARM64_INS_SABAL = 756 , ARM64_INS_SABAL2 = 757 , ARM64_INS_SABALB = 758 , ARM64_INS_SABALT = 759 , ARM64_INS_SABD = 760 , ARM64_INS_SABDL = 761 , ARM64_INS_SABDL2 = 762 , ARM64_INS_SABDLB = 763 , ARM64_INS_SABDLT = 764 , ARM64_INS_SADALP = 765 , ARM64_INS_SADDL = 766 , ARM64_INS_SADDL2 = 767 , ARM64_INS_SADDLB = 768 , ARM64_INS_SADDLBT = 769 , ARM64_INS_SADDLP = 770 , ARM64_INS_SADDLT = 771 , ARM64_INS_SADDLV = 772 , ARM64_INS_SADDV = 773 , ARM64_INS_SADDW = 774 , ARM64_INS_SADDW2 = 775 , ARM64_INS_SADDWB = 776 , ARM64_INS_SADDWT = 777 , ARM64_INS_SB = 778 , ARM64_INS_SBC = 779 , ARM64_INS_SBCLB = 780 , ARM64_INS_SBCLT = 781 , ARM64_INS_SBCS = 782 , ARM64_INS_SBFM = 783 , ARM64_INS_SCLAMP = 784 , ARM64_INS_SCVTF = 785 , ARM64_INS_SDIV = 786 , ARM64_INS_SDIVR = 787 , ARM64_INS_SDOT = 788 , ARM64_INS_SEL = 789 , ARM64_INS_SETE = 790 , ARM64_INS_SETEN = 791 , ARM64_INS_SETET = 792 , ARM64_INS_SETETN = 793 , ARM64_INS_SETF16 = 794 , ARM64_INS_SETF8 = 795 , ARM64_INS_SETFFR = 796 , ARM64_INS_SETGE = 797 , ARM64_INS_SETGEN = 798 , ARM64_INS_SETGET = 799 , ARM64_INS_SETGETN = 800 , ARM64_INS_SETGM = 801 , ARM64_INS_SETGMN = 802 , ARM64_INS_SETGMT = 803 , ARM64_INS_SETGMTN = 804 , ARM64_INS_SETGP = 805 , ARM64_INS_SETGPN = 806 , ARM64_INS_SETGPT = 807 , ARM64_INS_SETGPTN = 808 , ARM64_INS_SETM = 809 , ARM64_INS_SETMN = 810 , ARM64_INS_SETMT = 811 , ARM64_INS_SETMTN = 812 , ARM64_INS_SETP = 813 , ARM64_INS_SETPN = 814 , ARM64_INS_SETPT = 815 , ARM64_INS_SETPTN = 816 , ARM64_INS_SEV = 817 , ARM64_INS_SEVL = 818 , ARM64_INS_SHA1C = 819 , ARM64_INS_SHA1H = 820 , ARM64_INS_SHA1M = 821 , ARM64_INS_SHA1P = 822 , ARM64_INS_SHA1SU0 = 823 , ARM64_INS_SHA1SU1 = 824 , ARM64_INS_SHA256H = 825 , ARM64_INS_SHA256H2 = 826 , ARM64_INS_SHA256SU0 = 827 , ARM64_INS_SHA256SU1 = 828 , ARM64_INS_SHA512H = 829 , ARM64_INS_SHA512H2 = 830 , ARM64_INS_SHA512SU0 = 831 , ARM64_INS_SHA512SU1 = 832 , ARM64_INS_SHADD = 833 , ARM64_INS_SHL = 834 , ARM64_INS_SHLL = 835 , ARM64_INS_SHLL2 = 836 , ARM64_INS_SHRN = 837 , ARM64_INS_SHRN2 = 838 , ARM64_INS_SHRNB = 839 , ARM64_INS_SHRNT = 840 , ARM64_INS_SHSUB = 841 , ARM64_INS_SHSUBR = 842 , ARM64_INS_SLI = 843 , ARM64_INS_SM3PARTW1 = 844 , ARM64_INS_SM3PARTW2 = 845 , ARM64_INS_SM3SS1 = 846 , ARM64_INS_SM3TT1A = 847 , ARM64_INS_SM3TT1B = 848 , ARM64_INS_SM3TT2A = 849 , ARM64_INS_SM3TT2B = 850 , ARM64_INS_SM4E = 851 , ARM64_INS_SM4EKEY = 852 , ARM64_INS_SMADDL = 853 , ARM64_INS_SMAX = 854 , ARM64_INS_SMAXP = 855 , ARM64_INS_SMAXV = 856 , ARM64_INS_SMC = 857 , ARM64_INS_SMIN = 858 , ARM64_INS_SMINP = 859 , ARM64_INS_SMINV = 860 , ARM64_INS_SMLAL = 861 , ARM64_INS_SMLAL2 = 862 , ARM64_INS_SMLALB = 863 , ARM64_INS_SMLALT = 864 , ARM64_INS_SMLSL = 865 , ARM64_INS_SMLSL2 = 866 , ARM64_INS_SMLSLB = 867 , ARM64_INS_SMLSLT = 868 , ARM64_INS_SMMLA = 869 , ARM64_INS_SMNEGL = 870 , ARM64_INS_SMOPA = 871 , ARM64_INS_SMOPS = 872 , ARM64_INS_SMOV = 873 , ARM64_INS_SMSTART = 874 , ARM64_INS_SMSTOP = 875 , ARM64_INS_SMSUBL = 876 , ARM64_INS_SMULH = 877 , ARM64_INS_SMULL = 878 , ARM64_INS_SMULL2 = 879 , ARM64_INS_SMULLB = 880 , ARM64_INS_SMULLT = 881 , ARM64_INS_SPLICE = 882 , ARM64_INS_SQABS = 883 , ARM64_INS_SQADD = 884 , ARM64_INS_SQCADD = 885 , ARM64_INS_SQDECB = 886 , ARM64_INS_SQDECD = 887 , ARM64_INS_SQDECH = 888 , ARM64_INS_SQDECP = 889 , ARM64_INS_SQDECW = 890 , ARM64_INS_SQDMLAL = 891 , ARM64_INS_SQDMLAL2 = 892 , ARM64_INS_SQDMLALB = 893 , ARM64_INS_SQDMLALBT = 894 , ARM64_INS_SQDMLALT = 895 , ARM64_INS_SQDMLSL = 896 , ARM64_INS_SQDMLSL2 = 897 , ARM64_INS_SQDMLSLB = 898 , ARM64_INS_SQDMLSLBT = 899 , ARM64_INS_SQDMLSLT = 900 , ARM64_INS_SQDMULH = 901 , ARM64_INS_SQDMULL = 902 , ARM64_INS_SQDMULL2 = 903 , ARM64_INS_SQDMULLB = 904 , ARM64_INS_SQDMULLT = 905 , ARM64_INS_SQINCB = 906 , ARM64_INS_SQINCD = 907 , ARM64_INS_SQINCH = 908 , ARM64_INS_SQINCP = 909 , ARM64_INS_SQINCW = 910 , ARM64_INS_SQNEG = 911 , ARM64_INS_SQRDCMLAH = 912 , ARM64_INS_SQRDMLAH = 913 , ARM64_INS_SQRDMLSH = 914 , ARM64_INS_SQRDMULH = 915 , ARM64_INS_SQRSHL = 916 , ARM64_INS_SQRSHLR = 917 , ARM64_INS_SQRSHRN = 918 , ARM64_INS_SQRSHRN2 = 919 , ARM64_INS_SQRSHRNB = 920 , ARM64_INS_SQRSHRNT = 921 , ARM64_INS_SQRSHRUN = 922 , ARM64_INS_SQRSHRUN2 = 923 , ARM64_INS_SQRSHRUNB = 924 , ARM64_INS_SQRSHRUNT = 925 , ARM64_INS_SQSHL = 926 , ARM64_INS_SQSHLR = 927 , ARM64_INS_SQSHLU = 928 , ARM64_INS_SQSHRN = 929 , ARM64_INS_SQSHRN2 = 930 , ARM64_INS_SQSHRNB = 931 , ARM64_INS_SQSHRNT = 932 , ARM64_INS_SQSHRUN = 933 , ARM64_INS_SQSHRUN2 = 934 , ARM64_INS_SQSHRUNB = 935 , ARM64_INS_SQSHRUNT = 936 , ARM64_INS_SQSUB = 937 , ARM64_INS_SQSUBR = 938 , ARM64_INS_SQXTN = 939 , ARM64_INS_SQXTN2 = 940 , ARM64_INS_SQXTNB = 941 , ARM64_INS_SQXTNT = 942 , ARM64_INS_SQXTUN = 943 , ARM64_INS_SQXTUN2 = 944 , ARM64_INS_SQXTUNB = 945 , ARM64_INS_SQXTUNT = 946 , ARM64_INS_SRHADD = 947 , ARM64_INS_SRI = 948 , ARM64_INS_SRSHL = 949 , ARM64_INS_SRSHLR = 950 , ARM64_INS_SRSHR = 951 , ARM64_INS_SRSRA = 952 , ARM64_INS_SSBB = 953 , ARM64_INS_SSHL = 954 , ARM64_INS_SSHLL = 955 , ARM64_INS_SSHLL2 = 956 , ARM64_INS_SSHLLB = 957 , ARM64_INS_SSHLLT = 958 , ARM64_INS_SSHR = 959 , ARM64_INS_SSRA = 960 , ARM64_INS_SSUBL = 961 , ARM64_INS_SSUBL2 = 962 , ARM64_INS_SSUBLB = 963 , ARM64_INS_SSUBLBT = 964 , ARM64_INS_SSUBLT = 965 , ARM64_INS_SSUBLTB = 966 , ARM64_INS_SSUBW = 967 , ARM64_INS_SSUBW2 = 968 , ARM64_INS_SSUBWB = 969 , ARM64_INS_SSUBWT = 970 , ARM64_INS_ST1 = 971 , ARM64_INS_ST1B = 972 , ARM64_INS_ST1D = 973 , ARM64_INS_ST1H = 974 , ARM64_INS_ST1Q = 975 , ARM64_INS_ST1W = 976 , ARM64_INS_ST2 = 977 , ARM64_INS_ST2B = 978 , ARM64_INS_ST2D = 979 , ARM64_INS_ST2G = 980 , ARM64_INS_ST2H = 981 , ARM64_INS_ST2W = 982 , ARM64_INS_ST3 = 983 , ARM64_INS_ST3B = 984 , ARM64_INS_ST3D = 985 , ARM64_INS_ST3H = 986 , ARM64_INS_ST3W = 987 , ARM64_INS_ST4 = 988 , ARM64_INS_ST4B = 989 , ARM64_INS_ST4D = 990 , ARM64_INS_ST4H = 991 , ARM64_INS_ST4W = 992 , ARM64_INS_ST64B = 993 , ARM64_INS_ST64BV = 994 , ARM64_INS_ST64BV0 = 995 , ARM64_INS_STADD = 996 , ARM64_INS_STADDB = 997 , ARM64_INS_STADDH = 998 , ARM64_INS_STADDL = 999 , ARM64_INS_STADDLB = 1000 , ARM64_INS_STADDLH = 1001 , ARM64_INS_STCLR = 1002 , ARM64_INS_STCLRB = 1003 , ARM64_INS_STCLRH = 1004 , ARM64_INS_STCLRL = 1005 , ARM64_INS_STCLRLB = 1006 , ARM64_INS_STCLRLH = 1007 , ARM64_INS_STEOR = 1008 , ARM64_INS_STEORB = 1009 , ARM64_INS_STEORH = 1010 , ARM64_INS_STEORL = 1011 , ARM64_INS_STEORLB = 1012 , ARM64_INS_STEORLH = 1013 , ARM64_INS_STG = 1014 , ARM64_INS_STGM = 1015 , ARM64_INS_STGP = 1016 , ARM64_INS_STLLR = 1017 , ARM64_INS_STLLRB = 1018 , ARM64_INS_STLLRH = 1019 , ARM64_INS_STLR = 1020 , ARM64_INS_STLRB = 1021 , ARM64_INS_STLRH = 1022 , ARM64_INS_STLUR = 1023 , ARM64_INS_STLURB = 1024 , ARM64_INS_STLURH = 1025 , ARM64_INS_STLXP = 1026 , ARM64_INS_STLXR = 1027 , ARM64_INS_STLXRB = 1028 , ARM64_INS_STLXRH = 1029 , ARM64_INS_STNP = 1030 , ARM64_INS_STNT1B = 1031 , ARM64_INS_STNT1D = 1032 , ARM64_INS_STNT1H = 1033 , ARM64_INS_STNT1W = 1034 , ARM64_INS_STP = 1035 , ARM64_INS_STR = 1036 , ARM64_INS_STRB = 1037 , ARM64_INS_STRH = 1038 , ARM64_INS_STSET = 1039 , ARM64_INS_STSETB = 1040 , ARM64_INS_STSETH = 1041 , ARM64_INS_STSETL = 1042 , ARM64_INS_STSETLB = 1043 , ARM64_INS_STSETLH = 1044 , ARM64_INS_STSMAX = 1045 , ARM64_INS_STSMAXB = 1046 , ARM64_INS_STSMAXH = 1047 , ARM64_INS_STSMAXL = 1048 , ARM64_INS_STSMAXLB = 1049 , ARM64_INS_STSMAXLH = 1050 , ARM64_INS_STSMIN = 1051 , ARM64_INS_STSMINB = 1052 , ARM64_INS_STSMINH = 1053 , ARM64_INS_STSMINL = 1054 , ARM64_INS_STSMINLB = 1055 , ARM64_INS_STSMINLH = 1056 , ARM64_INS_STTR = 1057 , ARM64_INS_STTRB = 1058 , ARM64_INS_STTRH = 1059 , ARM64_INS_STUMAX = 1060 , ARM64_INS_STUMAXB = 1061 , ARM64_INS_STUMAXH = 1062 , ARM64_INS_STUMAXL = 1063 , ARM64_INS_STUMAXLB = 1064 , ARM64_INS_STUMAXLH = 1065 , ARM64_INS_STUMIN = 1066 , ARM64_INS_STUMINB = 1067 , ARM64_INS_STUMINH = 1068 , ARM64_INS_STUMINL = 1069 , ARM64_INS_STUMINLB = 1070 , ARM64_INS_STUMINLH = 1071 , ARM64_INS_STUR = 1072 , ARM64_INS_STURB = 1073 , ARM64_INS_STURH = 1074 , ARM64_INS_STXP = 1075 , ARM64_INS_STXR = 1076 , ARM64_INS_STXRB = 1077 , ARM64_INS_STXRH = 1078 , ARM64_INS_STZ2G = 1079 , ARM64_INS_STZG = 1080 , ARM64_INS_STZGM = 1081 , ARM64_INS_SUB = 1082 , ARM64_INS_SUBG = 1083 , ARM64_INS_SUBHN = 1084 , ARM64_INS_SUBHN2 = 1085 , ARM64_INS_SUBHNB = 1086 , ARM64_INS_SUBHNT = 1087 , ARM64_INS_SUBP = 1088 , ARM64_INS_SUBPS = 1089 , ARM64_INS_SUBR = 1090 , ARM64_INS_SUBS = 1091 , ARM64_INS_SUDOT = 1092 , ARM64_INS_SUMOPA = 1093 , ARM64_INS_SUMOPS = 1094 , ARM64_INS_SUNPKHI = 1095 , ARM64_INS_SUNPKLO = 1096 , ARM64_INS_SUQADD = 1097 , ARM64_INS_SVC = 1098 , ARM64_INS_SWP = 1099 , ARM64_INS_SWPA = 1100 , ARM64_INS_SWPAB = 1101 , ARM64_INS_SWPAH = 1102 , ARM64_INS_SWPAL = 1103 , ARM64_INS_SWPALB = 1104 , ARM64_INS_SWPALH = 1105 , ARM64_INS_SWPB = 1106 , ARM64_INS_SWPH = 1107 , ARM64_INS_SWPL = 1108 , ARM64_INS_SWPLB = 1109 , ARM64_INS_SWPLH = 1110 , ARM64_INS_SXTB = 1111 , ARM64_INS_SXTH = 1112 , ARM64_INS_SXTL = 1113 , ARM64_INS_SXTL2 = 1114 , ARM64_INS_SXTW = 1115 , ARM64_INS_SYS = 1116 , ARM64_INS_SYSL = 1117 , ARM64_INS_TBL = 1118 , ARM64_INS_TBNZ = 1119 , ARM64_INS_TBX = 1120 , ARM64_INS_TBZ = 1121 , ARM64_INS_TCANCEL = 1122 , ARM64_INS_TCOMMIT = 1123 , ARM64_INS_TRN1 = 1124 , ARM64_INS_TRN2 = 1125 , ARM64_INS_TSB = 1126 , ARM64_INS_TST = 1127 , ARM64_INS_TSTART = 1128 , ARM64_INS_TTEST = 1129 , ARM64_INS_UABA = 1130 , ARM64_INS_UABAL = 1131 , ARM64_INS_UABAL2 = 1132 , ARM64_INS_UABALB = 1133 , ARM64_INS_UABALT = 1134 , ARM64_INS_UABD = 1135 , ARM64_INS_UABDL = 1136 , ARM64_INS_UABDL2 = 1137 , ARM64_INS_UABDLB = 1138 , ARM64_INS_UABDLT = 1139 , ARM64_INS_UADALP = 1140 , ARM64_INS_UADDL = 1141 , ARM64_INS_UADDL2 = 1142 , ARM64_INS_UADDLB = 1143 , ARM64_INS_UADDLP = 1144 , ARM64_INS_UADDLT = 1145 , ARM64_INS_UADDLV = 1146 , ARM64_INS_UADDV = 1147 , ARM64_INS_UADDW = 1148 , ARM64_INS_UADDW2 = 1149 , ARM64_INS_UADDWB = 1150 , ARM64_INS_UADDWT = 1151 , ARM64_INS_UBFM = 1152 , ARM64_INS_UCLAMP = 1153 , ARM64_INS_UCVTF = 1154 , ARM64_INS_UDF = 1155 , ARM64_INS_UDIV = 1156 , ARM64_INS_UDIVR = 1157 , ARM64_INS_UDOT = 1158 , ARM64_INS_UHADD = 1159 , ARM64_INS_UHSUB = 1160 , ARM64_INS_UHSUBR = 1161 , ARM64_INS_UMADDL = 1162 , ARM64_INS_UMAX = 1163 , ARM64_INS_UMAXP = 1164 , ARM64_INS_UMAXV = 1165 , ARM64_INS_UMIN = 1166 , ARM64_INS_UMINP = 1167 , ARM64_INS_UMINV = 1168 , ARM64_INS_UMLAL = 1169 , ARM64_INS_UMLAL2 = 1170 , ARM64_INS_UMLALB = 1171 , ARM64_INS_UMLALT = 1172 , ARM64_INS_UMLSL = 1173 , ARM64_INS_UMLSL2 = 1174 , ARM64_INS_UMLSLB = 1175 , ARM64_INS_UMLSLT = 1176 , ARM64_INS_UMMLA = 1177 , ARM64_INS_UMNEGL = 1178 , ARM64_INS_UMOPA = 1179 , ARM64_INS_UMOPS = 1180 , ARM64_INS_UMOV = 1181 , ARM64_INS_UMSUBL = 1182 , ARM64_INS_UMULH = 1183 , ARM64_INS_UMULL = 1184 , ARM64_INS_UMULL2 = 1185 , ARM64_INS_UMULLB = 1186 , ARM64_INS_UMULLT = 1187 , ARM64_INS_UQADD = 1188 , ARM64_INS_UQDECB = 1189 , ARM64_INS_UQDECD = 1190 , ARM64_INS_UQDECH = 1191 , ARM64_INS_UQDECP = 1192 , ARM64_INS_UQDECW = 1193 , ARM64_INS_UQINCB = 1194 , ARM64_INS_UQINCD = 1195 , ARM64_INS_UQINCH = 1196 , ARM64_INS_UQINCP = 1197 , ARM64_INS_UQINCW = 1198 , ARM64_INS_UQRSHL = 1199 , ARM64_INS_UQRSHLR = 1200 , ARM64_INS_UQRSHRN = 1201 , ARM64_INS_UQRSHRN2 = 1202 , ARM64_INS_UQRSHRNB = 1203 , ARM64_INS_UQRSHRNT = 1204 , ARM64_INS_UQSHL = 1205 , ARM64_INS_UQSHLR = 1206 , ARM64_INS_UQSHRN = 1207 , ARM64_INS_UQSHRN2 = 1208 , ARM64_INS_UQSHRNB = 1209 , ARM64_INS_UQSHRNT = 1210 , ARM64_INS_UQSUB = 1211 , ARM64_INS_UQSUBR = 1212 , ARM64_INS_UQXTN = 1213 , ARM64_INS_UQXTN2 = 1214 , ARM64_INS_UQXTNB = 1215 , ARM64_INS_UQXTNT = 1216 , ARM64_INS_URECPE = 1217 , ARM64_INS_URHADD = 1218 , ARM64_INS_URSHL = 1219 , ARM64_INS_URSHLR = 1220 , ARM64_INS_URSHR = 1221 , ARM64_INS_URSQRTE = 1222 , ARM64_INS_URSRA = 1223 , ARM64_INS_USDOT = 1224 , ARM64_INS_USHL = 1225 , ARM64_INS_USHLL = 1226 , ARM64_INS_USHLL2 = 1227 , ARM64_INS_USHLLB = 1228 , ARM64_INS_USHLLT = 1229 , ARM64_INS_USHR = 1230 , ARM64_INS_USMMLA = 1231 , ARM64_INS_USMOPA = 1232 , ARM64_INS_USMOPS = 1233 , ARM64_INS_USQADD = 1234 , ARM64_INS_USRA = 1235 , ARM64_INS_USUBL = 1236 , ARM64_INS_USUBL2 = 1237 , ARM64_INS_USUBLB = 1238 , ARM64_INS_USUBLT = 1239 , ARM64_INS_USUBW = 1240 , ARM64_INS_USUBW2 = 1241 , ARM64_INS_USUBWB = 1242 , ARM64_INS_USUBWT = 1243 , ARM64_INS_UUNPKHI = 1244 , ARM64_INS_UUNPKLO = 1245 , ARM64_INS_UXTB = 1246 , ARM64_INS_UXTH = 1247 , ARM64_INS_UXTL = 1248 , ARM64_INS_UXTL2 = 1249 , ARM64_INS_UXTW = 1250 , ARM64_INS_UZP1 = 1251 , ARM64_INS_UZP2 = 1252 , ARM64_INS_WFE = 1253 , ARM64_INS_WFET = 1254 , ARM64_INS_WFI = 1255 , ARM64_INS_WFIT = 1256 , ARM64_INS_WHILEGE = 1257 , ARM64_INS_WHILEGT = 1258 , ARM64_INS_WHILEHI = 1259 , ARM64_INS_WHILEHS = 1260 , ARM64_INS_WHILELE = 1261 , ARM64_INS_WHILELO = 1262 , ARM64_INS_WHILELS = 1263 , ARM64_INS_WHILELT = 1264 , ARM64_INS_WHILERW = 1265 , ARM64_INS_WHILEWR = 1266 , ARM64_INS_WRFFR = 1267 , ARM64_INS_XAFLAG = 1268 , ARM64_INS_XAR = 1269 , ARM64_INS_XPACD = 1270 , ARM64_INS_XPACI = 1271 , ARM64_INS_XPACLRI = 1272 , ARM64_INS_XTN = 1273 , ARM64_INS_XTN2 = 1274 , ARM64_INS_YIELD = 1275 , ARM64_INS_ZERO = 1276 , ARM64_INS_ZIP1 = 1277 , ARM64_INS_ZIP2 = 1278 , ARM64_INS_SBFIZ = 1279 , ARM64_INS_UBFIZ = 1280 , ARM64_INS_SBFX = 1281 , ARM64_INS_UBFX = 1282 , ARM64_INS_BFI = 1283 , ARM64_INS_BFXIL = 1284 , ARM64_INS_IC = 1285 , ARM64_INS_DC = 1286 , ARM64_INS_AT = 1287 , ARM64_INS_TLBI = 1288 , ARM64_INS_ENDING = 1289 , } # [repr (u32)] # [doc = " Group of ARM64 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum arm64_insn_group { # [doc = "< = CS_GRP_INVALID"] ARM64_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] ARM64_GRP_JUMP = 1 , ARM64_GRP_CALL = 2 , ARM64_GRP_RET = 3 , ARM64_GRP_INT = 4 , # [doc = "< = CS_GRP_PRIVILEGE"] ARM64_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] ARM64_GRP_BRANCH_RELATIVE = 7 , ARM64_GRP_PAC = 8 , ARM64_GRP_CRYPTO = 128 , ARM64_GRP_FPARMV8 = 129 , ARM64_GRP_NEON = 130 , ARM64_GRP_CRC = 131 , ARM64_GRP_AES = 132 , ARM64_GRP_DOTPROD = 133 , ARM64_GRP_FULLFP16 = 134 , ARM64_GRP_LSE = 135 , ARM64_GRP_RCPC = 136 , ARM64_GRP_RDM = 137 , ARM64_GRP_SHA2 = 138 , ARM64_GRP_SHA3 = 139 , ARM64_GRP_SM4 = 140 , ARM64_GRP_SVE = 141 , ARM64_GRP_SVE2 = 142 , ARM64_GRP_SVE2AES = 143 , ARM64_GRP_SVE2BitPerm = 144 , ARM64_GRP_SVE2SHA3 = 145 , ARM64_GRP_SVE2SM4 = 146 , ARM64_GRP_SME = 147 , ARM64_GRP_SMEF64 = 148 , ARM64_GRP_SMEI64 = 149 , ARM64_GRP_MatMulFP32 = 150 , ARM64_GRP_MatMulFP64 = 151 , ARM64_GRP_MatMulInt8 = 152 , ARM64_GRP_V8_1A = 153 , ARM64_GRP_V8_3A = 154 , ARM64_GRP_V8_4A = 155 , ARM64_GRP_ENDING = 156 , } # [repr (u32)] # [doc = " M68K registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_reg { M68K_REG_INVALID = 0 , M68K_REG_D0 = 1 , M68K_REG_D1 = 2 , M68K_REG_D2 = 3 , M68K_REG_D3 = 4 , M68K_REG_D4 = 5 , M68K_REG_D5 = 6 , M68K_REG_D6 = 7 , M68K_REG_D7 = 8 , M68K_REG_A0 = 9 , M68K_REG_A1 = 10 , M68K_REG_A2 = 11 , M68K_REG_A3 = 12 , M68K_REG_A4 = 13 , M68K_REG_A5 = 14 , M68K_REG_A6 = 15 , M68K_REG_A7 = 16 , M68K_REG_FP0 = 17 , M68K_REG_FP1 = 18 , M68K_REG_FP2 = 19 , M68K_REG_FP3 = 20 , M68K_REG_FP4 = 21 , M68K_REG_FP5 = 22 , M68K_REG_FP6 = 23 , M68K_REG_FP7 = 24 , M68K_REG_PC = 25 , M68K_REG_SR = 26 , M68K_REG_CCR = 27 , M68K_REG_SFC = 28 , M68K_REG_DFC = 29 , M68K_REG_USP = 30 , M68K_REG_VBR = 31 , M68K_REG_CACR = 32 , M68K_REG_CAAR = 33 , M68K_REG_MSP = 34 , M68K_REG_ISP = 35 , M68K_REG_TC = 36 , M68K_REG_ITT0 = 37 , M68K_REG_ITT1 = 38 , M68K_REG_DTT0 = 39 , M68K_REG_DTT1 = 40 , M68K_REG_MMUSR = 41 , M68K_REG_URP = 42 , M68K_REG_SRP = 43 , M68K_REG_FPCR = 44 , M68K_REG_FPSR = 45 , M68K_REG_FPIAR = 46 , M68K_REG_ENDING = 47 , } # [repr (u32)] # [doc = " M68K Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_address_mode { # [doc = "< No address mode."] M68K_AM_NONE = 0 , # [doc = "< Register Direct - Data"] M68K_AM_REG_DIRECT_DATA = 1 , # [doc = "< Register Direct - Address"] M68K_AM_REG_DIRECT_ADDR = 2 , # [doc = "< Register Indirect - Address"] M68K_AM_REGI_ADDR = 3 , # [doc = "< Register Indirect - Address with Postincrement"] M68K_AM_REGI_ADDR_POST_INC = 4 , # [doc = "< Register Indirect - Address with Predecrement"] M68K_AM_REGI_ADDR_PRE_DEC = 5 , # [doc = "< Register Indirect - Address with Displacement"] M68K_AM_REGI_ADDR_DISP = 6 , # [doc = "< Address Register Indirect With Index- 8-bit displacement"] M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 , # [doc = "< Address Register Indirect With Index- Base displacement"] M68K_AM_AREGI_INDEX_BASE_DISP = 8 , # [doc = "< Memory indirect - Postindex"] M68K_AM_MEMI_POST_INDEX = 9 , # [doc = "< Memory indirect - Preindex"] M68K_AM_MEMI_PRE_INDEX = 10 , # [doc = "< Program Counter Indirect - with Displacement"] M68K_AM_PCI_DISP = 11 , # [doc = "< Program Counter Indirect with Index - with 8-Bit Displacement"] M68K_AM_PCI_INDEX_8_BIT_DISP = 12 , # [doc = "< Program Counter Indirect with Index - with Base Displacement"] M68K_AM_PCI_INDEX_BASE_DISP = 13 , # [doc = "< Program Counter Memory Indirect - Postindexed"] M68K_AM_PC_MEMI_POST_INDEX = 14 , # [doc = "< Program Counter Memory Indirect - Preindexed"] M68K_AM_PC_MEMI_PRE_INDEX = 15 , # [doc = "< Absolute Data Addressing  - Short"] M68K_AM_ABSOLUTE_DATA_SHORT = 16 , # [doc = "< Absolute Data Addressing  - Long"] M68K_AM_ABSOLUTE_DATA_LONG = 17 , # [doc = "< Immediate value"] M68K_AM_IMMEDIATE = 18 , # [doc = "< Address as displacement from (PC+2) used by branches"] M68K_AM_BRANCH_DISPLACEMENT = 19 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] M68K_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] M68K_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] M68K_OP_MEM = 3 , # [doc = "< single precision Floating-Point operand"] M68K_OP_FP_SINGLE = 4 , # [doc = "< double precision Floating-Point operand"] M68K_OP_FP_DOUBLE = 5 , # [doc = "< Register bits move"] M68K_OP_REG_BITS = 6 , # [doc = "< Register pair in the same op (upper 4 bits for first reg, lower for second)"] M68K_OP_REG_PAIR = 7 , # [doc = "< Branch displacement"] M68K_OP_BR_DISP = 8 , } # [doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_mem { # [doc = "< base register (or M68K_REG_INVALID if irrelevant)"] pub base_reg : m68k_reg , # [doc = "< index register (or M68K_REG_INVALID if irrelevant)"] pub index_reg : m68k_reg , # [doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"] pub in_base_reg : m68k_reg , # [doc = "< indirect displacement"] pub in_disp : u32 , # [doc = "< other displacement"] pub out_disp : u32 , # [doc = "< displacement value"] pub disp : i16 , # [doc = "< scale for index register"] pub scale : u8 , # [doc = "< set to true if the two values below should be used"] pub bitfield : u8 , # [doc = "< used for bf* instructions"] pub width : u8 , # [doc = "< used for bf* instructions"] pub offset : u8 , # [doc = "< 0 = w, 1 = l"] pub index_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_mem"] [:: std :: mem :: size_of :: < m68k_op_mem > () - 28usize] ; ["Alignment of m68k_op_mem"] [:: std :: mem :: align_of :: < m68k_op_mem > () - 4usize] ; ["Offset of field: m68k_op_mem::base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , base_reg) - 0usize] ; ["Offset of field: m68k_op_mem::index_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_reg) - 4usize] ; ["Offset of field: m68k_op_mem::in_base_reg"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_base_reg) - 8usize] ; ["Offset of field: m68k_op_mem::in_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , in_disp) - 12usize] ; ["Offset of field: m68k_op_mem::out_disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , out_disp) - 16usize] ; ["Offset of field: m68k_op_mem::disp"] [:: std :: mem :: offset_of ! (m68k_op_mem , disp) - 20usize] ; ["Offset of field: m68k_op_mem::scale"] [:: std :: mem :: offset_of ! (m68k_op_mem , scale) - 22usize] ; ["Offset of field: m68k_op_mem::bitfield"] [:: std :: mem :: offset_of ! (m68k_op_mem , bitfield) - 23usize] ; ["Offset of field: m68k_op_mem::width"] [:: std :: mem :: offset_of ! (m68k_op_mem , width) - 24usize] ; ["Offset of field: m68k_op_mem::offset"] [:: std :: mem :: offset_of ! (m68k_op_mem , offset) - 25usize] ; ["Offset of field: m68k_op_mem::index_size"] [:: std :: mem :: offset_of ! (m68k_op_mem , index_size) - 26usize] ; } ; # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_op_br_disp_size { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M68K_OP_BR_DISP_SIZE_INVALID = 0 , # [doc = "< signed 8-bit displacement"] M68K_OP_BR_DISP_SIZE_BYTE = 1 , # [doc = "< signed 16-bit displacement"] M68K_OP_BR_DISP_SIZE_WORD = 2 , # [doc = "< signed 32-bit displacement"] M68K_OP_BR_DISP_SIZE_LONG = 4 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m68k_op_br_disp { # [doc = "< displacement value"] pub disp : i32 , # [doc = "< Size from m68k_op_br_disp_size type above"] pub disp_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_br_disp"] [:: std :: mem :: size_of :: < m68k_op_br_disp > () - 8usize] ; ["Alignment of m68k_op_br_disp"] [:: std :: mem :: align_of :: < m68k_op_br_disp > () - 4usize] ; ["Offset of field: m68k_op_br_disp::disp"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp) - 0usize] ; ["Offset of field: m68k_op_br_disp::disp_size"] [:: std :: mem :: offset_of ! (m68k_op_br_disp , disp_size) - 4usize] ; } ; # [doc = " Register pair in one operand."] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_m68k_op_reg_pair { pub reg_0 : m68k_reg , pub reg_1 : m68k_reg , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op_reg_pair"] [:: std :: mem :: size_of :: < cs_m68k_op_reg_pair > () - 8usize] ; ["Alignment of cs_m68k_op_reg_pair"] [:: std :: mem :: align_of :: < cs_m68k_op_reg_pair > () - 4usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_0"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_0) - 0usize] ; ["Offset of field: cs_m68k_op_reg_pair::reg_1"] [:: std :: mem :: offset_of ! (cs_m68k_op_reg_pair , reg_1) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k_op { pub __bindgen_anon_1 : cs_m68k_op__bindgen_ty_1 , # [doc = "< data when operand is targeting memory"] pub mem : m68k_op_mem , # [doc = "< data when operand is a branch displacement"] pub br_disp : m68k_op_br_disp , # [doc = "< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)"] pub register_bits : u32 , pub type_ : m68k_op_type , # [doc = "< M68K addressing mode for this op"] pub address_mode : m68k_address_mode , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m68k_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< double imm"] pub dimm : f64 , # [doc = "< float imm"] pub simm : f32 , # [doc = "< register value for REG operand"] pub reg : m68k_reg , # [doc = "< register pair in one operand"] pub reg_pair : cs_m68k_op_reg_pair , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_m68k_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m68k_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::dimm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , dimm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::simm"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , simm) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m68k_op__bindgen_ty_1::reg_pair"] [:: std :: mem :: offset_of ! (cs_m68k_op__bindgen_ty_1 , reg_pair) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k_op"] [:: std :: mem :: size_of :: < cs_m68k_op > () - 56usize] ; ["Alignment of cs_m68k_op"] [:: std :: mem :: align_of :: < cs_m68k_op > () - 8usize] ; ["Offset of field: cs_m68k_op::mem"] [:: std :: mem :: offset_of ! (cs_m68k_op , mem) - 8usize] ; ["Offset of field: cs_m68k_op::br_disp"] [:: std :: mem :: offset_of ! (cs_m68k_op , br_disp) - 36usize] ; ["Offset of field: cs_m68k_op::register_bits"] [:: std :: mem :: offset_of ! (cs_m68k_op , register_bits) - 44usize] ; ["Offset of field: cs_m68k_op::type_"] [:: std :: mem :: offset_of ! (cs_m68k_op , type_) - 48usize] ; ["Offset of field: cs_m68k_op::address_mode"] [:: std :: mem :: offset_of ! (cs_m68k_op , address_mode) - 52usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode) } } # [repr (u32)] # [doc = " Operation size of the CPU instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_cpu_size { # [doc = "< unsized or unspecified"] M68K_CPU_SIZE_NONE = 0 , # [doc = "< 1 byte in size"] M68K_CPU_SIZE_BYTE = 1 , # [doc = "< 2 bytes in size"] M68K_CPU_SIZE_WORD = 2 , # [doc = "< 4 bytes in size"] M68K_CPU_SIZE_LONG = 4 , } # [repr (u32)] # [doc = " Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_fpu_size { # [doc = "< unsized like fsave/frestore"] M68K_FPU_SIZE_NONE = 0 , # [doc = "< 4 byte in size (single float)"] M68K_FPU_SIZE_SINGLE = 4 , # [doc = "< 8 byte in size (double)"] M68K_FPU_SIZE_DOUBLE = 8 , # [doc = "< 12 byte in size (extended real format)"] M68K_FPU_SIZE_EXTENDED = 12 , } # [repr (u32)] # [doc = " Type of size that is being used for the current instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0 , M68K_SIZE_TYPE_CPU = 1 , M68K_SIZE_TYPE_FPU = 2 , } # [doc = " Operation size of the current instruction (NOT the actually size of instruction)"] # [repr (C)] # [derive (Copy , Clone)] pub struct m68k_op_size { pub type_ : m68k_size_type , pub __bindgen_anon_1 : m68k_op_size__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union m68k_op_size__bindgen_ty_1 { pub cpu_size : m68k_cpu_size , pub fpu_size : m68k_fpu_size , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: size_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Alignment of m68k_op_size__bindgen_ty_1"] [:: std :: mem :: align_of :: < m68k_op_size__bindgen_ty_1 > () - 4usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::cpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , cpu_size) - 0usize] ; ["Offset of field: m68k_op_size__bindgen_ty_1::fpu_size"] [:: std :: mem :: offset_of ! (m68k_op_size__bindgen_ty_1 , fpu_size) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m68k_op_size"] [:: std :: mem :: size_of :: < m68k_op_size > () - 8usize] ; ["Alignment of m68k_op_size"] [:: std :: mem :: align_of :: < m68k_op_size > () - 4usize] ; ["Offset of field: m68k_op_size::type_"] [:: std :: mem :: offset_of ! (m68k_op_size , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for m68k_op_size { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "m68k_op_size {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The M68K instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m68k { # [doc = "< operands for this instruction."] pub operands : [cs_m68k_op ; 4usize] , # [doc = "< size of data operand works on in bytes (.b, .w, .l, etc)"] pub op_size : m68k_op_size , # [doc = "< number of operands for the instruction"] pub op_count : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m68k"] [:: std :: mem :: size_of :: < cs_m68k > () - 240usize] ; ["Alignment of cs_m68k"] [:: std :: mem :: align_of :: < cs_m68k > () - 8usize] ; ["Offset of field: cs_m68k::operands"] [:: std :: mem :: offset_of ! (cs_m68k , operands) - 0usize] ; ["Offset of field: cs_m68k::op_size"] [:: std :: mem :: offset_of ! (cs_m68k , op_size) - 224usize] ; ["Offset of field: cs_m68k::op_count"] [:: std :: mem :: offset_of ! (cs_m68k , op_count) - 232usize] ; } ; impl :: std :: fmt :: Debug for cs_m68k { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}" , self . operands , self . op_size , self . op_count) } } # [repr (u32)] # [doc = " M68K instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_insn { M68K_INS_INVALID = 0 , M68K_INS_ABCD = 1 , M68K_INS_ADD = 2 , M68K_INS_ADDA = 3 , M68K_INS_ADDI = 4 , M68K_INS_ADDQ = 5 , M68K_INS_ADDX = 6 , M68K_INS_AND = 7 , M68K_INS_ANDI = 8 , M68K_INS_ASL = 9 , M68K_INS_ASR = 10 , M68K_INS_BHS = 11 , M68K_INS_BLO = 12 , M68K_INS_BHI = 13 , M68K_INS_BLS = 14 , M68K_INS_BCC = 15 , M68K_INS_BCS = 16 , M68K_INS_BNE = 17 , M68K_INS_BEQ = 18 , M68K_INS_BVC = 19 , M68K_INS_BVS = 20 , M68K_INS_BPL = 21 , M68K_INS_BMI = 22 , M68K_INS_BGE = 23 , M68K_INS_BLT = 24 , M68K_INS_BGT = 25 , M68K_INS_BLE = 26 , M68K_INS_BRA = 27 , M68K_INS_BSR = 28 , M68K_INS_BCHG = 29 , M68K_INS_BCLR = 30 , M68K_INS_BSET = 31 , M68K_INS_BTST = 32 , M68K_INS_BFCHG = 33 , M68K_INS_BFCLR = 34 , M68K_INS_BFEXTS = 35 , M68K_INS_BFEXTU = 36 , M68K_INS_BFFFO = 37 , M68K_INS_BFINS = 38 , M68K_INS_BFSET = 39 , M68K_INS_BFTST = 40 , M68K_INS_BKPT = 41 , M68K_INS_CALLM = 42 , M68K_INS_CAS = 43 , M68K_INS_CAS2 = 44 , M68K_INS_CHK = 45 , M68K_INS_CHK2 = 46 , M68K_INS_CLR = 47 , M68K_INS_CMP = 48 , M68K_INS_CMPA = 49 , M68K_INS_CMPI = 50 , M68K_INS_CMPM = 51 , M68K_INS_CMP2 = 52 , M68K_INS_CINVL = 53 , M68K_INS_CINVP = 54 , M68K_INS_CINVA = 55 , M68K_INS_CPUSHL = 56 , M68K_INS_CPUSHP = 57 , M68K_INS_CPUSHA = 58 , M68K_INS_DBT = 59 , M68K_INS_DBF = 60 , M68K_INS_DBHI = 61 , M68K_INS_DBLS = 62 , M68K_INS_DBCC = 63 , M68K_INS_DBCS = 64 , M68K_INS_DBNE = 65 , M68K_INS_DBEQ = 66 , M68K_INS_DBVC = 67 , M68K_INS_DBVS = 68 , M68K_INS_DBPL = 69 , M68K_INS_DBMI = 70 , M68K_INS_DBGE = 71 , M68K_INS_DBLT = 72 , M68K_INS_DBGT = 73 , M68K_INS_DBLE = 74 , M68K_INS_DBRA = 75 , M68K_INS_DIVS = 76 , M68K_INS_DIVSL = 77 , M68K_INS_DIVU = 78 , M68K_INS_DIVUL = 79 , M68K_INS_EOR = 80 , M68K_INS_EORI = 81 , M68K_INS_EXG = 82 , M68K_INS_EXT = 83 , M68K_INS_EXTB = 84 , M68K_INS_FABS = 85 , M68K_INS_FSABS = 86 , M68K_INS_FDABS = 87 , M68K_INS_FACOS = 88 , M68K_INS_FADD = 89 , M68K_INS_FSADD = 90 , M68K_INS_FDADD = 91 , M68K_INS_FASIN = 92 , M68K_INS_FATAN = 93 , M68K_INS_FATANH = 94 , M68K_INS_FBF = 95 , M68K_INS_FBEQ = 96 , M68K_INS_FBOGT = 97 , M68K_INS_FBOGE = 98 , M68K_INS_FBOLT = 99 , M68K_INS_FBOLE = 100 , M68K_INS_FBOGL = 101 , M68K_INS_FBOR = 102 , M68K_INS_FBUN = 103 , M68K_INS_FBUEQ = 104 , M68K_INS_FBUGT = 105 , M68K_INS_FBUGE = 106 , M68K_INS_FBULT = 107 , M68K_INS_FBULE = 108 , M68K_INS_FBNE = 109 , M68K_INS_FBT = 110 , M68K_INS_FBSF = 111 , M68K_INS_FBSEQ = 112 , M68K_INS_FBGT = 113 , M68K_INS_FBGE = 114 , M68K_INS_FBLT = 115 , M68K_INS_FBLE = 116 , M68K_INS_FBGL = 117 , M68K_INS_FBGLE = 118 , M68K_INS_FBNGLE = 119 , M68K_INS_FBNGL = 120 , M68K_INS_FBNLE = 121 , M68K_INS_FBNLT = 122 , M68K_INS_FBNGE = 123 , M68K_INS_FBNGT = 124 , M68K_INS_FBSNE = 125 , M68K_INS_FBST = 126 , M68K_INS_FCMP = 127 , M68K_INS_FCOS = 128 , M68K_INS_FCOSH = 129 , M68K_INS_FDBF = 130 , M68K_INS_FDBEQ = 131 , M68K_INS_FDBOGT = 132 , M68K_INS_FDBOGE = 133 , M68K_INS_FDBOLT = 134 , M68K_INS_FDBOLE = 135 , M68K_INS_FDBOGL = 136 , M68K_INS_FDBOR = 137 , M68K_INS_FDBUN = 138 , M68K_INS_FDBUEQ = 139 , M68K_INS_FDBUGT = 140 , M68K_INS_FDBUGE = 141 , M68K_INS_FDBULT = 142 , M68K_INS_FDBULE = 143 , M68K_INS_FDBNE = 144 , M68K_INS_FDBT = 145 , M68K_INS_FDBSF = 146 , M68K_INS_FDBSEQ = 147 , M68K_INS_FDBGT = 148 , M68K_INS_FDBGE = 149 , M68K_INS_FDBLT = 150 , M68K_INS_FDBLE = 151 , M68K_INS_FDBGL = 152 , M68K_INS_FDBGLE = 153 , M68K_INS_FDBNGLE = 154 , M68K_INS_FDBNGL = 155 , M68K_INS_FDBNLE = 156 , M68K_INS_FDBNLT = 157 , M68K_INS_FDBNGE = 158 , M68K_INS_FDBNGT = 159 , M68K_INS_FDBSNE = 160 , M68K_INS_FDBST = 161 , M68K_INS_FDIV = 162 , M68K_INS_FSDIV = 163 , M68K_INS_FDDIV = 164 , M68K_INS_FETOX = 165 , M68K_INS_FETOXM1 = 166 , M68K_INS_FGETEXP = 167 , M68K_INS_FGETMAN = 168 , M68K_INS_FINT = 169 , M68K_INS_FINTRZ = 170 , M68K_INS_FLOG10 = 171 , M68K_INS_FLOG2 = 172 , M68K_INS_FLOGN = 173 , M68K_INS_FLOGNP1 = 174 , M68K_INS_FMOD = 175 , M68K_INS_FMOVE = 176 , M68K_INS_FSMOVE = 177 , M68K_INS_FDMOVE = 178 , M68K_INS_FMOVECR = 179 , M68K_INS_FMOVEM = 180 , M68K_INS_FMUL = 181 , M68K_INS_FSMUL = 182 , M68K_INS_FDMUL = 183 , M68K_INS_FNEG = 184 , M68K_INS_FSNEG = 185 , M68K_INS_FDNEG = 186 , M68K_INS_FNOP = 187 , M68K_INS_FREM = 188 , M68K_INS_FRESTORE = 189 , M68K_INS_FSAVE = 190 , M68K_INS_FSCALE = 191 , M68K_INS_FSGLDIV = 192 , M68K_INS_FSGLMUL = 193 , M68K_INS_FSIN = 194 , M68K_INS_FSINCOS = 195 , M68K_INS_FSINH = 196 , M68K_INS_FSQRT = 197 , M68K_INS_FSSQRT = 198 , M68K_INS_FDSQRT = 199 , M68K_INS_FSF = 200 , M68K_INS_FSBEQ = 201 , M68K_INS_FSOGT = 202 , M68K_INS_FSOGE = 203 , M68K_INS_FSOLT = 204 , M68K_INS_FSOLE = 205 , M68K_INS_FSOGL = 206 , M68K_INS_FSOR = 207 , M68K_INS_FSUN = 208 , M68K_INS_FSUEQ = 209 , M68K_INS_FSUGT = 210 , M68K_INS_FSUGE = 211 , M68K_INS_FSULT = 212 , M68K_INS_FSULE = 213 , M68K_INS_FSNE = 214 , M68K_INS_FST = 215 , M68K_INS_FSSF = 216 , M68K_INS_FSSEQ = 217 , M68K_INS_FSGT = 218 , M68K_INS_FSGE = 219 , M68K_INS_FSLT = 220 , M68K_INS_FSLE = 221 , M68K_INS_FSGL = 222 , M68K_INS_FSGLE = 223 , M68K_INS_FSNGLE = 224 , M68K_INS_FSNGL = 225 , M68K_INS_FSNLE = 226 , M68K_INS_FSNLT = 227 , M68K_INS_FSNGE = 228 , M68K_INS_FSNGT = 229 , M68K_INS_FSSNE = 230 , M68K_INS_FSST = 231 , M68K_INS_FSUB = 232 , M68K_INS_FSSUB = 233 , M68K_INS_FDSUB = 234 , M68K_INS_FTAN = 235 , M68K_INS_FTANH = 236 , M68K_INS_FTENTOX = 237 , M68K_INS_FTRAPF = 238 , M68K_INS_FTRAPEQ = 239 , M68K_INS_FTRAPOGT = 240 , M68K_INS_FTRAPOGE = 241 , M68K_INS_FTRAPOLT = 242 , M68K_INS_FTRAPOLE = 243 , M68K_INS_FTRAPOGL = 244 , M68K_INS_FTRAPOR = 245 , M68K_INS_FTRAPUN = 246 , M68K_INS_FTRAPUEQ = 247 , M68K_INS_FTRAPUGT = 248 , M68K_INS_FTRAPUGE = 249 , M68K_INS_FTRAPULT = 250 , M68K_INS_FTRAPULE = 251 , M68K_INS_FTRAPNE = 252 , M68K_INS_FTRAPT = 253 , M68K_INS_FTRAPSF = 254 , M68K_INS_FTRAPSEQ = 255 , M68K_INS_FTRAPGT = 256 , M68K_INS_FTRAPGE = 257 , M68K_INS_FTRAPLT = 258 , M68K_INS_FTRAPLE = 259 , M68K_INS_FTRAPGL = 260 , M68K_INS_FTRAPGLE = 261 , M68K_INS_FTRAPNGLE = 262 , M68K_INS_FTRAPNGL = 263 , M68K_INS_FTRAPNLE = 264 , M68K_INS_FTRAPNLT = 265 , M68K_INS_FTRAPNGE = 266 , M68K_INS_FTRAPNGT = 267 , M68K_INS_FTRAPSNE = 268 , M68K_INS_FTRAPST = 269 , M68K_INS_FTST = 270 , M68K_INS_FTWOTOX = 271 , M68K_INS_HALT = 272 , M68K_INS_ILLEGAL = 273 , M68K_INS_JMP = 274 , M68K_INS_JSR = 275 , M68K_INS_LEA = 276 , M68K_INS_LINK = 277 , M68K_INS_LPSTOP = 278 , M68K_INS_LSL = 279 , M68K_INS_LSR = 280 , M68K_INS_MOVE = 281 , M68K_INS_MOVEA = 282 , M68K_INS_MOVEC = 283 , M68K_INS_MOVEM = 284 , M68K_INS_MOVEP = 285 , M68K_INS_MOVEQ = 286 , M68K_INS_MOVES = 287 , M68K_INS_MOVE16 = 288 , M68K_INS_MULS = 289 , M68K_INS_MULU = 290 , M68K_INS_NBCD = 291 , M68K_INS_NEG = 292 , M68K_INS_NEGX = 293 , M68K_INS_NOP = 294 , M68K_INS_NOT = 295 , M68K_INS_OR = 296 , M68K_INS_ORI = 297 , M68K_INS_PACK = 298 , M68K_INS_PEA = 299 , M68K_INS_PFLUSH = 300 , M68K_INS_PFLUSHA = 301 , M68K_INS_PFLUSHAN = 302 , M68K_INS_PFLUSHN = 303 , M68K_INS_PLOADR = 304 , M68K_INS_PLOADW = 305 , M68K_INS_PLPAR = 306 , M68K_INS_PLPAW = 307 , M68K_INS_PMOVE = 308 , M68K_INS_PMOVEFD = 309 , M68K_INS_PTESTR = 310 , M68K_INS_PTESTW = 311 , M68K_INS_PULSE = 312 , M68K_INS_REMS = 313 , M68K_INS_REMU = 314 , M68K_INS_RESET = 315 , M68K_INS_ROL = 316 , M68K_INS_ROR = 317 , M68K_INS_ROXL = 318 , M68K_INS_ROXR = 319 , M68K_INS_RTD = 320 , M68K_INS_RTE = 321 , M68K_INS_RTM = 322 , M68K_INS_RTR = 323 , M68K_INS_RTS = 324 , M68K_INS_SBCD = 325 , M68K_INS_ST = 326 , M68K_INS_SF = 327 , M68K_INS_SHI = 328 , M68K_INS_SLS = 329 , M68K_INS_SCC = 330 , M68K_INS_SHS = 331 , M68K_INS_SCS = 332 , M68K_INS_SLO = 333 , M68K_INS_SNE = 334 , M68K_INS_SEQ = 335 , M68K_INS_SVC = 336 , M68K_INS_SVS = 337 , M68K_INS_SPL = 338 , M68K_INS_SMI = 339 , M68K_INS_SGE = 340 , M68K_INS_SLT = 341 , M68K_INS_SGT = 342 , M68K_INS_SLE = 343 , M68K_INS_STOP = 344 , M68K_INS_SUB = 345 , M68K_INS_SUBA = 346 , M68K_INS_SUBI = 347 , M68K_INS_SUBQ = 348 , M68K_INS_SUBX = 349 , M68K_INS_SWAP = 350 , M68K_INS_TAS = 351 , M68K_INS_TRAP = 352 , M68K_INS_TRAPV = 353 , M68K_INS_TRAPT = 354 , M68K_INS_TRAPF = 355 , M68K_INS_TRAPHI = 356 , M68K_INS_TRAPLS = 357 , M68K_INS_TRAPCC = 358 , M68K_INS_TRAPHS = 359 , M68K_INS_TRAPCS = 360 , M68K_INS_TRAPLO = 361 , M68K_INS_TRAPNE = 362 , M68K_INS_TRAPEQ = 363 , M68K_INS_TRAPVC = 364 , M68K_INS_TRAPVS = 365 , M68K_INS_TRAPPL = 366 , M68K_INS_TRAPMI = 367 , M68K_INS_TRAPGE = 368 , M68K_INS_TRAPLT = 369 , M68K_INS_TRAPGT = 370 , M68K_INS_TRAPLE = 371 , M68K_INS_TST = 372 , M68K_INS_UNLK = 373 , M68K_INS_UNPK = 374 , M68K_INS_ENDING = 375 , } # [repr (u32)] # [doc = " Group of M68K instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m68k_group_type { # [doc = "< CS_GRUP_INVALID"] M68K_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M68K_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] M68K_GRP_RET = 3 , # [doc = "< = CS_GRP_IRET"] M68K_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M68K_GRP_BRANCH_RELATIVE = 7 , M68K_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MIPS_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MIPS_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MIPS_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MIPS_OP_MEM = 3 , } impl mips_reg { pub const MIPS_REG_ZERO : mips_reg = mips_reg :: MIPS_REG_0 ; } impl mips_reg { pub const MIPS_REG_AT : mips_reg = mips_reg :: MIPS_REG_1 ; } impl mips_reg { pub const MIPS_REG_V0 : mips_reg = mips_reg :: MIPS_REG_2 ; } impl mips_reg { pub const MIPS_REG_V1 : mips_reg = mips_reg :: MIPS_REG_3 ; } impl mips_reg { pub const MIPS_REG_A0 : mips_reg = mips_reg :: MIPS_REG_4 ; } impl mips_reg { pub const MIPS_REG_A1 : mips_reg = mips_reg :: MIPS_REG_5 ; } impl mips_reg { pub const MIPS_REG_A2 : mips_reg = mips_reg :: MIPS_REG_6 ; } impl mips_reg { pub const MIPS_REG_A3 : mips_reg = mips_reg :: MIPS_REG_7 ; } impl mips_reg { pub const MIPS_REG_T0 : mips_reg = mips_reg :: MIPS_REG_8 ; } impl mips_reg { pub const MIPS_REG_T1 : mips_reg = mips_reg :: MIPS_REG_9 ; } impl mips_reg { pub const MIPS_REG_T2 : mips_reg = mips_reg :: MIPS_REG_10 ; } impl mips_reg { pub const MIPS_REG_T3 : mips_reg = mips_reg :: MIPS_REG_11 ; } impl mips_reg { pub const MIPS_REG_T4 : mips_reg = mips_reg :: MIPS_REG_12 ; } impl mips_reg { pub const MIPS_REG_T5 : mips_reg = mips_reg :: MIPS_REG_13 ; } impl mips_reg { pub const MIPS_REG_T6 : mips_reg = mips_reg :: MIPS_REG_14 ; } impl mips_reg { pub const MIPS_REG_T7 : mips_reg = mips_reg :: MIPS_REG_15 ; } impl mips_reg { pub const MIPS_REG_S0 : mips_reg = mips_reg :: MIPS_REG_16 ; } impl mips_reg { pub const MIPS_REG_S1 : mips_reg = mips_reg :: MIPS_REG_17 ; } impl mips_reg { pub const MIPS_REG_S2 : mips_reg = mips_reg :: MIPS_REG_18 ; } impl mips_reg { pub const MIPS_REG_S3 : mips_reg = mips_reg :: MIPS_REG_19 ; } impl mips_reg { pub const MIPS_REG_S4 : mips_reg = mips_reg :: MIPS_REG_20 ; } impl mips_reg { pub const MIPS_REG_S5 : mips_reg = mips_reg :: MIPS_REG_21 ; } impl mips_reg { pub const MIPS_REG_S6 : mips_reg = mips_reg :: MIPS_REG_22 ; } impl mips_reg { pub const MIPS_REG_S7 : mips_reg = mips_reg :: MIPS_REG_23 ; } impl mips_reg { pub const MIPS_REG_T8 : mips_reg = mips_reg :: MIPS_REG_24 ; } impl mips_reg { pub const MIPS_REG_T9 : mips_reg = mips_reg :: MIPS_REG_25 ; } impl mips_reg { pub const MIPS_REG_K0 : mips_reg = mips_reg :: MIPS_REG_26 ; } impl mips_reg { pub const MIPS_REG_K1 : mips_reg = mips_reg :: MIPS_REG_27 ; } impl mips_reg { pub const MIPS_REG_GP : mips_reg = mips_reg :: MIPS_REG_28 ; } impl mips_reg { pub const MIPS_REG_SP : mips_reg = mips_reg :: MIPS_REG_29 ; } impl mips_reg { pub const MIPS_REG_FP : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_S8 : mips_reg = mips_reg :: MIPS_REG_30 ; } impl mips_reg { pub const MIPS_REG_RA : mips_reg = mips_reg :: MIPS_REG_31 ; } impl mips_reg { pub const MIPS_REG_HI0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_HI1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_HI2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_HI3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } impl mips_reg { pub const MIPS_REG_LO0 : mips_reg = mips_reg :: MIPS_REG_AC0 ; } impl mips_reg { pub const MIPS_REG_LO1 : mips_reg = mips_reg :: MIPS_REG_AC1 ; } impl mips_reg { pub const MIPS_REG_LO2 : mips_reg = mips_reg :: MIPS_REG_AC2 ; } impl mips_reg { pub const MIPS_REG_LO3 : mips_reg = mips_reg :: MIPS_REG_AC3 ; } # [repr (u32)] # [doc = " MIPS registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_reg { MIPS_REG_INVALID = 0 , MIPS_REG_PC = 1 , MIPS_REG_0 = 2 , MIPS_REG_1 = 3 , MIPS_REG_2 = 4 , MIPS_REG_3 = 5 , MIPS_REG_4 = 6 , MIPS_REG_5 = 7 , MIPS_REG_6 = 8 , MIPS_REG_7 = 9 , MIPS_REG_8 = 10 , MIPS_REG_9 = 11 , MIPS_REG_10 = 12 , MIPS_REG_11 = 13 , MIPS_REG_12 = 14 , MIPS_REG_13 = 15 , MIPS_REG_14 = 16 , MIPS_REG_15 = 17 , MIPS_REG_16 = 18 , MIPS_REG_17 = 19 , MIPS_REG_18 = 20 , MIPS_REG_19 = 21 , MIPS_REG_20 = 22 , MIPS_REG_21 = 23 , MIPS_REG_22 = 24 , MIPS_REG_23 = 25 , MIPS_REG_24 = 26 , MIPS_REG_25 = 27 , MIPS_REG_26 = 28 , MIPS_REG_27 = 29 , MIPS_REG_28 = 30 , MIPS_REG_29 = 31 , MIPS_REG_30 = 32 , MIPS_REG_31 = 33 , MIPS_REG_DSPCCOND = 34 , MIPS_REG_DSPCARRY = 35 , MIPS_REG_DSPEFI = 36 , MIPS_REG_DSPOUTFLAG = 37 , MIPS_REG_DSPOUTFLAG16_19 = 38 , MIPS_REG_DSPOUTFLAG20 = 39 , MIPS_REG_DSPOUTFLAG21 = 40 , MIPS_REG_DSPOUTFLAG22 = 41 , MIPS_REG_DSPOUTFLAG23 = 42 , MIPS_REG_DSPPOS = 43 , MIPS_REG_DSPSCOUNT = 44 , MIPS_REG_AC0 = 45 , MIPS_REG_AC1 = 46 , MIPS_REG_AC2 = 47 , MIPS_REG_AC3 = 48 , MIPS_REG_CC0 = 49 , MIPS_REG_CC1 = 50 , MIPS_REG_CC2 = 51 , MIPS_REG_CC3 = 52 , MIPS_REG_CC4 = 53 , MIPS_REG_CC5 = 54 , MIPS_REG_CC6 = 55 , MIPS_REG_CC7 = 56 , MIPS_REG_F0 = 57 , MIPS_REG_F1 = 58 , MIPS_REG_F2 = 59 , MIPS_REG_F3 = 60 , MIPS_REG_F4 = 61 , MIPS_REG_F5 = 62 , MIPS_REG_F6 = 63 , MIPS_REG_F7 = 64 , MIPS_REG_F8 = 65 , MIPS_REG_F9 = 66 , MIPS_REG_F10 = 67 , MIPS_REG_F11 = 68 , MIPS_REG_F12 = 69 , MIPS_REG_F13 = 70 , MIPS_REG_F14 = 71 , MIPS_REG_F15 = 72 , MIPS_REG_F16 = 73 , MIPS_REG_F17 = 74 , MIPS_REG_F18 = 75 , MIPS_REG_F19 = 76 , MIPS_REG_F20 = 77 , MIPS_REG_F21 = 78 , MIPS_REG_F22 = 79 , MIPS_REG_F23 = 80 , MIPS_REG_F24 = 81 , MIPS_REG_F25 = 82 , MIPS_REG_F26 = 83 , MIPS_REG_F27 = 84 , MIPS_REG_F28 = 85 , MIPS_REG_F29 = 86 , MIPS_REG_F30 = 87 , MIPS_REG_F31 = 88 , MIPS_REG_FCC0 = 89 , MIPS_REG_FCC1 = 90 , MIPS_REG_FCC2 = 91 , MIPS_REG_FCC3 = 92 , MIPS_REG_FCC4 = 93 , MIPS_REG_FCC5 = 94 , MIPS_REG_FCC6 = 95 , MIPS_REG_FCC7 = 96 , MIPS_REG_W0 = 97 , MIPS_REG_W1 = 98 , MIPS_REG_W2 = 99 , MIPS_REG_W3 = 100 , MIPS_REG_W4 = 101 , MIPS_REG_W5 = 102 , MIPS_REG_W6 = 103 , MIPS_REG_W7 = 104 , MIPS_REG_W8 = 105 , MIPS_REG_W9 = 106 , MIPS_REG_W10 = 107 , MIPS_REG_W11 = 108 , MIPS_REG_W12 = 109 , MIPS_REG_W13 = 110 , MIPS_REG_W14 = 111 , MIPS_REG_W15 = 112 , MIPS_REG_W16 = 113 , MIPS_REG_W17 = 114 , MIPS_REG_W18 = 115 , MIPS_REG_W19 = 116 , MIPS_REG_W20 = 117 , MIPS_REG_W21 = 118 , MIPS_REG_W22 = 119 , MIPS_REG_W23 = 120 , MIPS_REG_W24 = 121 , MIPS_REG_W25 = 122 , MIPS_REG_W26 = 123 , MIPS_REG_W27 = 124 , MIPS_REG_W28 = 125 , MIPS_REG_W29 = 126 , MIPS_REG_W30 = 127 , MIPS_REG_W31 = 128 , MIPS_REG_HI = 129 , MIPS_REG_LO = 130 , MIPS_REG_P0 = 131 , MIPS_REG_P1 = 132 , MIPS_REG_P2 = 133 , MIPS_REG_MPL0 = 134 , MIPS_REG_MPL1 = 135 , MIPS_REG_MPL2 = 136 , MIPS_REG_ENDING = 137 , } # [doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct mips_op_mem { # [doc = "< base register"] pub base : mips_reg , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of mips_op_mem"] [:: std :: mem :: size_of :: < mips_op_mem > () - 16usize] ; ["Alignment of mips_op_mem"] [:: std :: mem :: align_of :: < mips_op_mem > () - 8usize] ; ["Offset of field: mips_op_mem::base"] [:: std :: mem :: offset_of ! (mips_op_mem , base) - 0usize] ; ["Offset of field: mips_op_mem::disp"] [:: std :: mem :: offset_of ! (mips_op_mem , disp) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips_op { # [doc = "< operand type"] pub type_ : mips_op_type , pub __bindgen_anon_1 : cs_mips_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mips_op__bindgen_ty_1 { # [doc = "< register id for REG operand"] pub reg : mips_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : mips_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mips_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_mips_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mips_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mips_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mips_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips_op"] [:: std :: mem :: size_of :: < cs_mips_op > () - 24usize] ; ["Alignment of cs_mips_op"] [:: std :: mem :: align_of :: < cs_mips_op > () - 8usize] ; ["Offset of field: cs_mips_op::type_"] [:: std :: mem :: offset_of ! (cs_mips_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mips_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mips { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mips_op ; 10usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mips"] [:: std :: mem :: size_of :: < cs_mips > () - 248usize] ; ["Alignment of cs_mips"] [:: std :: mem :: align_of :: < cs_mips > () - 8usize] ; ["Offset of field: cs_mips::op_count"] [:: std :: mem :: offset_of ! (cs_mips , op_count) - 0usize] ; ["Offset of field: cs_mips::operands"] [:: std :: mem :: offset_of ! (cs_mips , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mips { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mips {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " MIPS instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn { MIPS_INS_INVALID = 0 , MIPS_INS_ABSQ_S = 1 , MIPS_INS_ADD = 2 , MIPS_INS_ADDIUPC = 3 , MIPS_INS_ADDIUR1SP = 4 , MIPS_INS_ADDIUR2 = 5 , MIPS_INS_ADDIUS5 = 6 , MIPS_INS_ADDIUSP = 7 , MIPS_INS_ADDQH = 8 , MIPS_INS_ADDQH_R = 9 , MIPS_INS_ADDQ = 10 , MIPS_INS_ADDQ_S = 11 , MIPS_INS_ADDSC = 12 , MIPS_INS_ADDS_A = 13 , MIPS_INS_ADDS_S = 14 , MIPS_INS_ADDS_U = 15 , MIPS_INS_ADDU16 = 16 , MIPS_INS_ADDUH = 17 , MIPS_INS_ADDUH_R = 18 , MIPS_INS_ADDU = 19 , MIPS_INS_ADDU_S = 20 , MIPS_INS_ADDVI = 21 , MIPS_INS_ADDV = 22 , MIPS_INS_ADDWC = 23 , MIPS_INS_ADD_A = 24 , MIPS_INS_ADDI = 25 , MIPS_INS_ADDIU = 26 , MIPS_INS_ALIGN = 27 , MIPS_INS_ALUIPC = 28 , MIPS_INS_AND = 29 , MIPS_INS_AND16 = 30 , MIPS_INS_ANDI16 = 31 , MIPS_INS_ANDI = 32 , MIPS_INS_APPEND = 33 , MIPS_INS_ASUB_S = 34 , MIPS_INS_ASUB_U = 35 , MIPS_INS_AUI = 36 , MIPS_INS_AUIPC = 37 , MIPS_INS_AVER_S = 38 , MIPS_INS_AVER_U = 39 , MIPS_INS_AVE_S = 40 , MIPS_INS_AVE_U = 41 , MIPS_INS_B16 = 42 , MIPS_INS_BADDU = 43 , MIPS_INS_BAL = 44 , MIPS_INS_BALC = 45 , MIPS_INS_BALIGN = 46 , MIPS_INS_BBIT0 = 47 , MIPS_INS_BBIT032 = 48 , MIPS_INS_BBIT1 = 49 , MIPS_INS_BBIT132 = 50 , MIPS_INS_BC = 51 , MIPS_INS_BC0F = 52 , MIPS_INS_BC0FL = 53 , MIPS_INS_BC0T = 54 , MIPS_INS_BC0TL = 55 , MIPS_INS_BC1EQZ = 56 , MIPS_INS_BC1F = 57 , MIPS_INS_BC1FL = 58 , MIPS_INS_BC1NEZ = 59 , MIPS_INS_BC1T = 60 , MIPS_INS_BC1TL = 61 , MIPS_INS_BC2EQZ = 62 , MIPS_INS_BC2F = 63 , MIPS_INS_BC2FL = 64 , MIPS_INS_BC2NEZ = 65 , MIPS_INS_BC2T = 66 , MIPS_INS_BC2TL = 67 , MIPS_INS_BC3F = 68 , MIPS_INS_BC3FL = 69 , MIPS_INS_BC3T = 70 , MIPS_INS_BC3TL = 71 , MIPS_INS_BCLRI = 72 , MIPS_INS_BCLR = 73 , MIPS_INS_BEQ = 74 , MIPS_INS_BEQC = 75 , MIPS_INS_BEQL = 76 , MIPS_INS_BEQZ16 = 77 , MIPS_INS_BEQZALC = 78 , MIPS_INS_BEQZC = 79 , MIPS_INS_BGEC = 80 , MIPS_INS_BGEUC = 81 , MIPS_INS_BGEZ = 82 , MIPS_INS_BGEZAL = 83 , MIPS_INS_BGEZALC = 84 , MIPS_INS_BGEZALL = 85 , MIPS_INS_BGEZALS = 86 , MIPS_INS_BGEZC = 87 , MIPS_INS_BGEZL = 88 , MIPS_INS_BGTZ = 89 , MIPS_INS_BGTZALC = 90 , MIPS_INS_BGTZC = 91 , MIPS_INS_BGTZL = 92 , MIPS_INS_BINSLI = 93 , MIPS_INS_BINSL = 94 , MIPS_INS_BINSRI = 95 , MIPS_INS_BINSR = 96 , MIPS_INS_BITREV = 97 , MIPS_INS_BITSWAP = 98 , MIPS_INS_BLEZ = 99 , MIPS_INS_BLEZALC = 100 , MIPS_INS_BLEZC = 101 , MIPS_INS_BLEZL = 102 , MIPS_INS_BLTC = 103 , MIPS_INS_BLTUC = 104 , MIPS_INS_BLTZ = 105 , MIPS_INS_BLTZAL = 106 , MIPS_INS_BLTZALC = 107 , MIPS_INS_BLTZALL = 108 , MIPS_INS_BLTZALS = 109 , MIPS_INS_BLTZC = 110 , MIPS_INS_BLTZL = 111 , MIPS_INS_BMNZI = 112 , MIPS_INS_BMNZ = 113 , MIPS_INS_BMZI = 114 , MIPS_INS_BMZ = 115 , MIPS_INS_BNE = 116 , MIPS_INS_BNEC = 117 , MIPS_INS_BNEGI = 118 , MIPS_INS_BNEG = 119 , MIPS_INS_BNEL = 120 , MIPS_INS_BNEZ16 = 121 , MIPS_INS_BNEZALC = 122 , MIPS_INS_BNEZC = 123 , MIPS_INS_BNVC = 124 , MIPS_INS_BNZ = 125 , MIPS_INS_BOVC = 126 , MIPS_INS_BPOSGE32 = 127 , MIPS_INS_BREAK = 128 , MIPS_INS_BREAK16 = 129 , MIPS_INS_BSELI = 130 , MIPS_INS_BSEL = 131 , MIPS_INS_BSETI = 132 , MIPS_INS_BSET = 133 , MIPS_INS_BZ = 134 , MIPS_INS_BEQZ = 135 , MIPS_INS_B = 136 , MIPS_INS_BNEZ = 137 , MIPS_INS_BTEQZ = 138 , MIPS_INS_BTNEZ = 139 , MIPS_INS_CACHE = 140 , MIPS_INS_CEIL = 141 , MIPS_INS_CEQI = 142 , MIPS_INS_CEQ = 143 , MIPS_INS_CFC1 = 144 , MIPS_INS_CFCMSA = 145 , MIPS_INS_CINS = 146 , MIPS_INS_CINS32 = 147 , MIPS_INS_CLASS = 148 , MIPS_INS_CLEI_S = 149 , MIPS_INS_CLEI_U = 150 , MIPS_INS_CLE_S = 151 , MIPS_INS_CLE_U = 152 , MIPS_INS_CLO = 153 , MIPS_INS_CLTI_S = 154 , MIPS_INS_CLTI_U = 155 , MIPS_INS_CLT_S = 156 , MIPS_INS_CLT_U = 157 , MIPS_INS_CLZ = 158 , MIPS_INS_CMPGDU = 159 , MIPS_INS_CMPGU = 160 , MIPS_INS_CMPU = 161 , MIPS_INS_CMP = 162 , MIPS_INS_COPY_S = 163 , MIPS_INS_COPY_U = 164 , MIPS_INS_CTC1 = 165 , MIPS_INS_CTCMSA = 166 , MIPS_INS_CVT = 167 , MIPS_INS_C = 168 , MIPS_INS_CMPI = 169 , MIPS_INS_DADD = 170 , MIPS_INS_DADDI = 171 , MIPS_INS_DADDIU = 172 , MIPS_INS_DADDU = 173 , MIPS_INS_DAHI = 174 , MIPS_INS_DALIGN = 175 , MIPS_INS_DATI = 176 , MIPS_INS_DAUI = 177 , MIPS_INS_DBITSWAP = 178 , MIPS_INS_DCLO = 179 , MIPS_INS_DCLZ = 180 , MIPS_INS_DDIV = 181 , MIPS_INS_DDIVU = 182 , MIPS_INS_DERET = 183 , MIPS_INS_DEXT = 184 , MIPS_INS_DEXTM = 185 , MIPS_INS_DEXTU = 186 , MIPS_INS_DI = 187 , MIPS_INS_DINS = 188 , MIPS_INS_DINSM = 189 , MIPS_INS_DINSU = 190 , MIPS_INS_DIV = 191 , MIPS_INS_DIVU = 192 , MIPS_INS_DIV_S = 193 , MIPS_INS_DIV_U = 194 , MIPS_INS_DLSA = 195 , MIPS_INS_DMFC0 = 196 , MIPS_INS_DMFC1 = 197 , MIPS_INS_DMFC2 = 198 , MIPS_INS_DMOD = 199 , MIPS_INS_DMODU = 200 , MIPS_INS_DMTC0 = 201 , MIPS_INS_DMTC1 = 202 , MIPS_INS_DMTC2 = 203 , MIPS_INS_DMUH = 204 , MIPS_INS_DMUHU = 205 , MIPS_INS_DMUL = 206 , MIPS_INS_DMULT = 207 , MIPS_INS_DMULTU = 208 , MIPS_INS_DMULU = 209 , MIPS_INS_DOTP_S = 210 , MIPS_INS_DOTP_U = 211 , MIPS_INS_DPADD_S = 212 , MIPS_INS_DPADD_U = 213 , MIPS_INS_DPAQX_SA = 214 , MIPS_INS_DPAQX_S = 215 , MIPS_INS_DPAQ_SA = 216 , MIPS_INS_DPAQ_S = 217 , MIPS_INS_DPAU = 218 , MIPS_INS_DPAX = 219 , MIPS_INS_DPA = 220 , MIPS_INS_DPOP = 221 , MIPS_INS_DPSQX_SA = 222 , MIPS_INS_DPSQX_S = 223 , MIPS_INS_DPSQ_SA = 224 , MIPS_INS_DPSQ_S = 225 , MIPS_INS_DPSUB_S = 226 , MIPS_INS_DPSUB_U = 227 , MIPS_INS_DPSU = 228 , MIPS_INS_DPSX = 229 , MIPS_INS_DPS = 230 , MIPS_INS_DROTR = 231 , MIPS_INS_DROTR32 = 232 , MIPS_INS_DROTRV = 233 , MIPS_INS_DSBH = 234 , MIPS_INS_DSHD = 235 , MIPS_INS_DSLL = 236 , MIPS_INS_DSLL32 = 237 , MIPS_INS_DSLLV = 238 , MIPS_INS_DSRA = 239 , MIPS_INS_DSRA32 = 240 , MIPS_INS_DSRAV = 241 , MIPS_INS_DSRL = 242 , MIPS_INS_DSRL32 = 243 , MIPS_INS_DSRLV = 244 , MIPS_INS_DSUB = 245 , MIPS_INS_DSUBU = 246 , MIPS_INS_EHB = 247 , MIPS_INS_EI = 248 , MIPS_INS_ERET = 249 , MIPS_INS_EXT = 250 , MIPS_INS_EXTP = 251 , MIPS_INS_EXTPDP = 252 , MIPS_INS_EXTPDPV = 253 , MIPS_INS_EXTPV = 254 , MIPS_INS_EXTRV_RS = 255 , MIPS_INS_EXTRV_R = 256 , MIPS_INS_EXTRV_S = 257 , MIPS_INS_EXTRV = 258 , MIPS_INS_EXTR_RS = 259 , MIPS_INS_EXTR_R = 260 , MIPS_INS_EXTR_S = 261 , MIPS_INS_EXTR = 262 , MIPS_INS_EXTS = 263 , MIPS_INS_EXTS32 = 264 , MIPS_INS_ABS = 265 , MIPS_INS_FADD = 266 , MIPS_INS_FCAF = 267 , MIPS_INS_FCEQ = 268 , MIPS_INS_FCLASS = 269 , MIPS_INS_FCLE = 270 , MIPS_INS_FCLT = 271 , MIPS_INS_FCNE = 272 , MIPS_INS_FCOR = 273 , MIPS_INS_FCUEQ = 274 , MIPS_INS_FCULE = 275 , MIPS_INS_FCULT = 276 , MIPS_INS_FCUNE = 277 , MIPS_INS_FCUN = 278 , MIPS_INS_FDIV = 279 , MIPS_INS_FEXDO = 280 , MIPS_INS_FEXP2 = 281 , MIPS_INS_FEXUPL = 282 , MIPS_INS_FEXUPR = 283 , MIPS_INS_FFINT_S = 284 , MIPS_INS_FFINT_U = 285 , MIPS_INS_FFQL = 286 , MIPS_INS_FFQR = 287 , MIPS_INS_FILL = 288 , MIPS_INS_FLOG2 = 289 , MIPS_INS_FLOOR = 290 , MIPS_INS_FMADD = 291 , MIPS_INS_FMAX_A = 292 , MIPS_INS_FMAX = 293 , MIPS_INS_FMIN_A = 294 , MIPS_INS_FMIN = 295 , MIPS_INS_MOV = 296 , MIPS_INS_FMSUB = 297 , MIPS_INS_FMUL = 298 , MIPS_INS_MUL = 299 , MIPS_INS_NEG = 300 , MIPS_INS_FRCP = 301 , MIPS_INS_FRINT = 302 , MIPS_INS_FRSQRT = 303 , MIPS_INS_FSAF = 304 , MIPS_INS_FSEQ = 305 , MIPS_INS_FSLE = 306 , MIPS_INS_FSLT = 307 , MIPS_INS_FSNE = 308 , MIPS_INS_FSOR = 309 , MIPS_INS_FSQRT = 310 , MIPS_INS_SQRT = 311 , MIPS_INS_FSUB = 312 , MIPS_INS_SUB = 313 , MIPS_INS_FSUEQ = 314 , MIPS_INS_FSULE = 315 , MIPS_INS_FSULT = 316 , MIPS_INS_FSUNE = 317 , MIPS_INS_FSUN = 318 , MIPS_INS_FTINT_S = 319 , MIPS_INS_FTINT_U = 320 , MIPS_INS_FTQ = 321 , MIPS_INS_FTRUNC_S = 322 , MIPS_INS_FTRUNC_U = 323 , MIPS_INS_HADD_S = 324 , MIPS_INS_HADD_U = 325 , MIPS_INS_HSUB_S = 326 , MIPS_INS_HSUB_U = 327 , MIPS_INS_ILVEV = 328 , MIPS_INS_ILVL = 329 , MIPS_INS_ILVOD = 330 , MIPS_INS_ILVR = 331 , MIPS_INS_INS = 332 , MIPS_INS_INSERT = 333 , MIPS_INS_INSV = 334 , MIPS_INS_INSVE = 335 , MIPS_INS_J = 336 , MIPS_INS_JAL = 337 , MIPS_INS_JALR = 338 , MIPS_INS_JALRS16 = 339 , MIPS_INS_JALRS = 340 , MIPS_INS_JALS = 341 , MIPS_INS_JALX = 342 , MIPS_INS_JIALC = 343 , MIPS_INS_JIC = 344 , MIPS_INS_JR = 345 , MIPS_INS_JR16 = 346 , MIPS_INS_JRADDIUSP = 347 , MIPS_INS_JRC = 348 , MIPS_INS_JALRC = 349 , MIPS_INS_LB = 350 , MIPS_INS_LBU16 = 351 , MIPS_INS_LBUX = 352 , MIPS_INS_LBU = 353 , MIPS_INS_LD = 354 , MIPS_INS_LDC1 = 355 , MIPS_INS_LDC2 = 356 , MIPS_INS_LDC3 = 357 , MIPS_INS_LDI = 358 , MIPS_INS_LDL = 359 , MIPS_INS_LDPC = 360 , MIPS_INS_LDR = 361 , MIPS_INS_LDXC1 = 362 , MIPS_INS_LH = 363 , MIPS_INS_LHU16 = 364 , MIPS_INS_LHX = 365 , MIPS_INS_LHU = 366 , MIPS_INS_LI16 = 367 , MIPS_INS_LL = 368 , MIPS_INS_LLD = 369 , MIPS_INS_LSA = 370 , MIPS_INS_LUXC1 = 371 , MIPS_INS_LUI = 372 , MIPS_INS_LW = 373 , MIPS_INS_LW16 = 374 , MIPS_INS_LWC1 = 375 , MIPS_INS_LWC2 = 376 , MIPS_INS_LWC3 = 377 , MIPS_INS_LWL = 378 , MIPS_INS_LWM16 = 379 , MIPS_INS_LWM32 = 380 , MIPS_INS_LWPC = 381 , MIPS_INS_LWP = 382 , MIPS_INS_LWR = 383 , MIPS_INS_LWUPC = 384 , MIPS_INS_LWU = 385 , MIPS_INS_LWX = 386 , MIPS_INS_LWXC1 = 387 , MIPS_INS_LWXS = 388 , MIPS_INS_LI = 389 , MIPS_INS_MADD = 390 , MIPS_INS_MADDF = 391 , MIPS_INS_MADDR_Q = 392 , MIPS_INS_MADDU = 393 , MIPS_INS_MADDV = 394 , MIPS_INS_MADD_Q = 395 , MIPS_INS_MAQ_SA = 396 , MIPS_INS_MAQ_S = 397 , MIPS_INS_MAXA = 398 , MIPS_INS_MAXI_S = 399 , MIPS_INS_MAXI_U = 400 , MIPS_INS_MAX_A = 401 , MIPS_INS_MAX = 402 , MIPS_INS_MAX_S = 403 , MIPS_INS_MAX_U = 404 , MIPS_INS_MFC0 = 405 , MIPS_INS_MFC1 = 406 , MIPS_INS_MFC2 = 407 , MIPS_INS_MFHC1 = 408 , MIPS_INS_MFHI = 409 , MIPS_INS_MFLO = 410 , MIPS_INS_MINA = 411 , MIPS_INS_MINI_S = 412 , MIPS_INS_MINI_U = 413 , MIPS_INS_MIN_A = 414 , MIPS_INS_MIN = 415 , MIPS_INS_MIN_S = 416 , MIPS_INS_MIN_U = 417 , MIPS_INS_MOD = 418 , MIPS_INS_MODSUB = 419 , MIPS_INS_MODU = 420 , MIPS_INS_MOD_S = 421 , MIPS_INS_MOD_U = 422 , MIPS_INS_MOVE = 423 , MIPS_INS_MOVEP = 424 , MIPS_INS_MOVF = 425 , MIPS_INS_MOVN = 426 , MIPS_INS_MOVT = 427 , MIPS_INS_MOVZ = 428 , MIPS_INS_MSUB = 429 , MIPS_INS_MSUBF = 430 , MIPS_INS_MSUBR_Q = 431 , MIPS_INS_MSUBU = 432 , MIPS_INS_MSUBV = 433 , MIPS_INS_MSUB_Q = 434 , MIPS_INS_MTC0 = 435 , MIPS_INS_MTC1 = 436 , MIPS_INS_MTC2 = 437 , MIPS_INS_MTHC1 = 438 , MIPS_INS_MTHI = 439 , MIPS_INS_MTHLIP = 440 , MIPS_INS_MTLO = 441 , MIPS_INS_MTM0 = 442 , MIPS_INS_MTM1 = 443 , MIPS_INS_MTM2 = 444 , MIPS_INS_MTP0 = 445 , MIPS_INS_MTP1 = 446 , MIPS_INS_MTP2 = 447 , MIPS_INS_MUH = 448 , MIPS_INS_MUHU = 449 , MIPS_INS_MULEQ_S = 450 , MIPS_INS_MULEU_S = 451 , MIPS_INS_MULQ_RS = 452 , MIPS_INS_MULQ_S = 453 , MIPS_INS_MULR_Q = 454 , MIPS_INS_MULSAQ_S = 455 , MIPS_INS_MULSA = 456 , MIPS_INS_MULT = 457 , MIPS_INS_MULTU = 458 , MIPS_INS_MULU = 459 , MIPS_INS_MULV = 460 , MIPS_INS_MUL_Q = 461 , MIPS_INS_MUL_S = 462 , MIPS_INS_NLOC = 463 , MIPS_INS_NLZC = 464 , MIPS_INS_NMADD = 465 , MIPS_INS_NMSUB = 466 , MIPS_INS_NOR = 467 , MIPS_INS_NORI = 468 , MIPS_INS_NOT16 = 469 , MIPS_INS_NOT = 470 , MIPS_INS_OR = 471 , MIPS_INS_OR16 = 472 , MIPS_INS_ORI = 473 , MIPS_INS_PACKRL = 474 , MIPS_INS_PAUSE = 475 , MIPS_INS_PCKEV = 476 , MIPS_INS_PCKOD = 477 , MIPS_INS_PCNT = 478 , MIPS_INS_PICK = 479 , MIPS_INS_POP = 480 , MIPS_INS_PRECEQU = 481 , MIPS_INS_PRECEQ = 482 , MIPS_INS_PRECEU = 483 , MIPS_INS_PRECRQU_S = 484 , MIPS_INS_PRECRQ = 485 , MIPS_INS_PRECRQ_RS = 486 , MIPS_INS_PRECR = 487 , MIPS_INS_PRECR_SRA = 488 , MIPS_INS_PRECR_SRA_R = 489 , MIPS_INS_PREF = 490 , MIPS_INS_PREPEND = 491 , MIPS_INS_RADDU = 492 , MIPS_INS_RDDSP = 493 , MIPS_INS_RDHWR = 494 , MIPS_INS_REPLV = 495 , MIPS_INS_REPL = 496 , MIPS_INS_RINT = 497 , MIPS_INS_ROTR = 498 , MIPS_INS_ROTRV = 499 , MIPS_INS_ROUND = 500 , MIPS_INS_SAT_S = 501 , MIPS_INS_SAT_U = 502 , MIPS_INS_SB = 503 , MIPS_INS_SB16 = 504 , MIPS_INS_SC = 505 , MIPS_INS_SCD = 506 , MIPS_INS_SD = 507 , MIPS_INS_SDBBP = 508 , MIPS_INS_SDBBP16 = 509 , MIPS_INS_SDC1 = 510 , MIPS_INS_SDC2 = 511 , MIPS_INS_SDC3 = 512 , MIPS_INS_SDL = 513 , MIPS_INS_SDR = 514 , MIPS_INS_SDXC1 = 515 , MIPS_INS_SEB = 516 , MIPS_INS_SEH = 517 , MIPS_INS_SELEQZ = 518 , MIPS_INS_SELNEZ = 519 , MIPS_INS_SEL = 520 , MIPS_INS_SEQ = 521 , MIPS_INS_SEQI = 522 , MIPS_INS_SH = 523 , MIPS_INS_SH16 = 524 , MIPS_INS_SHF = 525 , MIPS_INS_SHILO = 526 , MIPS_INS_SHILOV = 527 , MIPS_INS_SHLLV = 528 , MIPS_INS_SHLLV_S = 529 , MIPS_INS_SHLL = 530 , MIPS_INS_SHLL_S = 531 , MIPS_INS_SHRAV = 532 , MIPS_INS_SHRAV_R = 533 , MIPS_INS_SHRA = 534 , MIPS_INS_SHRA_R = 535 , MIPS_INS_SHRLV = 536 , MIPS_INS_SHRL = 537 , MIPS_INS_SLDI = 538 , MIPS_INS_SLD = 539 , MIPS_INS_SLL = 540 , MIPS_INS_SLL16 = 541 , MIPS_INS_SLLI = 542 , MIPS_INS_SLLV = 543 , MIPS_INS_SLT = 544 , MIPS_INS_SLTI = 545 , MIPS_INS_SLTIU = 546 , MIPS_INS_SLTU = 547 , MIPS_INS_SNE = 548 , MIPS_INS_SNEI = 549 , MIPS_INS_SPLATI = 550 , MIPS_INS_SPLAT = 551 , MIPS_INS_SRA = 552 , MIPS_INS_SRAI = 553 , MIPS_INS_SRARI = 554 , MIPS_INS_SRAR = 555 , MIPS_INS_SRAV = 556 , MIPS_INS_SRL = 557 , MIPS_INS_SRL16 = 558 , MIPS_INS_SRLI = 559 , MIPS_INS_SRLRI = 560 , MIPS_INS_SRLR = 561 , MIPS_INS_SRLV = 562 , MIPS_INS_SSNOP = 563 , MIPS_INS_ST = 564 , MIPS_INS_SUBQH = 565 , MIPS_INS_SUBQH_R = 566 , MIPS_INS_SUBQ = 567 , MIPS_INS_SUBQ_S = 568 , MIPS_INS_SUBSUS_U = 569 , MIPS_INS_SUBSUU_S = 570 , MIPS_INS_SUBS_S = 571 , MIPS_INS_SUBS_U = 572 , MIPS_INS_SUBU16 = 573 , MIPS_INS_SUBUH = 574 , MIPS_INS_SUBUH_R = 575 , MIPS_INS_SUBU = 576 , MIPS_INS_SUBU_S = 577 , MIPS_INS_SUBVI = 578 , MIPS_INS_SUBV = 579 , MIPS_INS_SUXC1 = 580 , MIPS_INS_SW = 581 , MIPS_INS_SW16 = 582 , MIPS_INS_SWC1 = 583 , MIPS_INS_SWC2 = 584 , MIPS_INS_SWC3 = 585 , MIPS_INS_SWL = 586 , MIPS_INS_SWM16 = 587 , MIPS_INS_SWM32 = 588 , MIPS_INS_SWP = 589 , MIPS_INS_SWR = 590 , MIPS_INS_SWXC1 = 591 , MIPS_INS_SYNC = 592 , MIPS_INS_SYNCI = 593 , MIPS_INS_SYSCALL = 594 , MIPS_INS_TEQ = 595 , MIPS_INS_TEQI = 596 , MIPS_INS_TGE = 597 , MIPS_INS_TGEI = 598 , MIPS_INS_TGEIU = 599 , MIPS_INS_TGEU = 600 , MIPS_INS_TLBP = 601 , MIPS_INS_TLBR = 602 , MIPS_INS_TLBWI = 603 , MIPS_INS_TLBWR = 604 , MIPS_INS_TLT = 605 , MIPS_INS_TLTI = 606 , MIPS_INS_TLTIU = 607 , MIPS_INS_TLTU = 608 , MIPS_INS_TNE = 609 , MIPS_INS_TNEI = 610 , MIPS_INS_TRUNC = 611 , MIPS_INS_V3MULU = 612 , MIPS_INS_VMM0 = 613 , MIPS_INS_VMULU = 614 , MIPS_INS_VSHF = 615 , MIPS_INS_WAIT = 616 , MIPS_INS_WRDSP = 617 , MIPS_INS_WSBH = 618 , MIPS_INS_XOR = 619 , MIPS_INS_XOR16 = 620 , MIPS_INS_XORI = 621 , MIPS_INS_NOP = 622 , MIPS_INS_NEGU = 623 , MIPS_INS_JALR_HB = 624 , MIPS_INS_JR_HB = 625 , MIPS_INS_ENDING = 626 , } # [repr (u32)] # [doc = " Group of MIPS instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mips_insn_group { # [doc = "< = CS_GRP_INVALID"] MIPS_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MIPS_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] MIPS_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MIPS_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MIPS_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MIPS_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] MIPS_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MIPS_GRP_BRANCH_RELATIVE = 7 , MIPS_GRP_BITCOUNT = 128 , MIPS_GRP_DSP = 129 , MIPS_GRP_DSPR2 = 130 , MIPS_GRP_FPIDX = 131 , MIPS_GRP_MSA = 132 , MIPS_GRP_MIPS32R2 = 133 , MIPS_GRP_MIPS64 = 134 , MIPS_GRP_MIPS64R2 = 135 , MIPS_GRP_SEINREG = 136 , MIPS_GRP_STDENC = 137 , MIPS_GRP_SWAP = 138 , MIPS_GRP_MICROMIPS = 139 , MIPS_GRP_MIPS16MODE = 140 , MIPS_GRP_FP64BIT = 141 , MIPS_GRP_NONANSFPMATH = 142 , MIPS_GRP_NOTFP64BIT = 143 , MIPS_GRP_NOTINMICROMIPS = 144 , MIPS_GRP_NOTNACL = 145 , MIPS_GRP_NOTMIPS32R6 = 146 , MIPS_GRP_NOTMIPS64R6 = 147 , MIPS_GRP_CNMIPS = 148 , MIPS_GRP_MIPS32 = 149 , MIPS_GRP_MIPS32R6 = 150 , MIPS_GRP_MIPS64R6 = 151 , MIPS_GRP_MIPS2 = 152 , MIPS_GRP_MIPS3 = 153 , MIPS_GRP_MIPS3_32 = 154 , MIPS_GRP_MIPS3_32R2 = 155 , MIPS_GRP_MIPS4_32 = 156 , MIPS_GRP_MIPS4_32R2 = 157 , MIPS_GRP_MIPS5_32R2 = 158 , MIPS_GRP_GP32BIT = 159 , MIPS_GRP_GP64BIT = 160 , MIPS_GRP_ENDING = 161 , } # [repr (u32)] # [doc = " PPC branch codes for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bc { PPC_BC_INVALID = 0 , PPC_BC_LT = 12 , PPC_BC_LE = 36 , PPC_BC_EQ = 76 , PPC_BC_GE = 4 , PPC_BC_GT = 44 , PPC_BC_NE = 68 , PPC_BC_UN = 108 , PPC_BC_NU = 100 , # [doc = "< summary overflow"] PPC_BC_SO = 140 , # [doc = "< not summary overflow"] PPC_BC_NS = 132 , } # [repr (u32)] # [doc = " PPC branch hint for some branch instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_bh { # [doc = "< no hint"] PPC_BH_INVALID = 0 , # [doc = "< PLUS hint"] PPC_BH_PLUS = 1 , # [doc = "< MINUS hint"] PPC_BH_MINUS = 2 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] PPC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] PPC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] PPC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] PPC_OP_MEM = 3 , # [doc = "< Condition Register field"] PPC_OP_CRX = 64 , } # [repr (u32)] # [doc = " PPC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_reg { PPC_REG_INVALID = 0 , PPC_REG_CARRY = 2 , PPC_REG_CTR = 3 , PPC_REG_LR = 5 , PPC_REG_RM = 6 , PPC_REG_VRSAVE = 8 , PPC_REG_XER = 9 , PPC_REG_ZERO = 10 , PPC_REG_CR0 = 12 , PPC_REG_CR1 = 13 , PPC_REG_CR2 = 14 , PPC_REG_CR3 = 15 , PPC_REG_CR4 = 16 , PPC_REG_CR5 = 17 , PPC_REG_CR6 = 18 , PPC_REG_CR7 = 19 , PPC_REG_CTR8 = 20 , PPC_REG_F0 = 21 , PPC_REG_F1 = 22 , PPC_REG_F2 = 23 , PPC_REG_F3 = 24 , PPC_REG_F4 = 25 , PPC_REG_F5 = 26 , PPC_REG_F6 = 27 , PPC_REG_F7 = 28 , PPC_REG_F8 = 29 , PPC_REG_F9 = 30 , PPC_REG_F10 = 31 , PPC_REG_F11 = 32 , PPC_REG_F12 = 33 , PPC_REG_F13 = 34 , PPC_REG_F14 = 35 , PPC_REG_F15 = 36 , PPC_REG_F16 = 37 , PPC_REG_F17 = 38 , PPC_REG_F18 = 39 , PPC_REG_F19 = 40 , PPC_REG_F20 = 41 , PPC_REG_F21 = 42 , PPC_REG_F22 = 43 , PPC_REG_F23 = 44 , PPC_REG_F24 = 45 , PPC_REG_F25 = 46 , PPC_REG_F26 = 47 , PPC_REG_F27 = 48 , PPC_REG_F28 = 49 , PPC_REG_F29 = 50 , PPC_REG_F30 = 51 , PPC_REG_F31 = 52 , PPC_REG_LR8 = 54 , PPC_REG_Q0 = 55 , PPC_REG_Q1 = 56 , PPC_REG_Q2 = 57 , PPC_REG_Q3 = 58 , PPC_REG_Q4 = 59 , PPC_REG_Q5 = 60 , PPC_REG_Q6 = 61 , PPC_REG_Q7 = 62 , PPC_REG_Q8 = 63 , PPC_REG_Q9 = 64 , PPC_REG_Q10 = 65 , PPC_REG_Q11 = 66 , PPC_REG_Q12 = 67 , PPC_REG_Q13 = 68 , PPC_REG_Q14 = 69 , PPC_REG_Q15 = 70 , PPC_REG_Q16 = 71 , PPC_REG_Q17 = 72 , PPC_REG_Q18 = 73 , PPC_REG_Q19 = 74 , PPC_REG_Q20 = 75 , PPC_REG_Q21 = 76 , PPC_REG_Q22 = 77 , PPC_REG_Q23 = 78 , PPC_REG_Q24 = 79 , PPC_REG_Q25 = 80 , PPC_REG_Q26 = 81 , PPC_REG_Q27 = 82 , PPC_REG_Q28 = 83 , PPC_REG_Q29 = 84 , PPC_REG_Q30 = 85 , PPC_REG_Q31 = 86 , PPC_REG_R0 = 87 , PPC_REG_R1 = 88 , PPC_REG_R2 = 89 , PPC_REG_R3 = 90 , PPC_REG_R4 = 91 , PPC_REG_R5 = 92 , PPC_REG_R6 = 93 , PPC_REG_R7 = 94 , PPC_REG_R8 = 95 , PPC_REG_R9 = 96 , PPC_REG_R10 = 97 , PPC_REG_R11 = 98 , PPC_REG_R12 = 99 , PPC_REG_R13 = 100 , PPC_REG_R14 = 101 , PPC_REG_R15 = 102 , PPC_REG_R16 = 103 , PPC_REG_R17 = 104 , PPC_REG_R18 = 105 , PPC_REG_R19 = 106 , PPC_REG_R20 = 107 , PPC_REG_R21 = 108 , PPC_REG_R22 = 109 , PPC_REG_R23 = 110 , PPC_REG_R24 = 111 , PPC_REG_R25 = 112 , PPC_REG_R26 = 113 , PPC_REG_R27 = 114 , PPC_REG_R28 = 115 , PPC_REG_R29 = 116 , PPC_REG_R30 = 117 , PPC_REG_R31 = 118 , PPC_REG_V0 = 151 , PPC_REG_V1 = 152 , PPC_REG_V2 = 153 , PPC_REG_V3 = 154 , PPC_REG_V4 = 155 , PPC_REG_V5 = 156 , PPC_REG_V6 = 157 , PPC_REG_V7 = 158 , PPC_REG_V8 = 159 , PPC_REG_V9 = 160 , PPC_REG_V10 = 161 , PPC_REG_V11 = 162 , PPC_REG_V12 = 163 , PPC_REG_V13 = 164 , PPC_REG_V14 = 165 , PPC_REG_V15 = 166 , PPC_REG_V16 = 167 , PPC_REG_V17 = 168 , PPC_REG_V18 = 169 , PPC_REG_V19 = 170 , PPC_REG_V20 = 171 , PPC_REG_V21 = 172 , PPC_REG_V22 = 173 , PPC_REG_V23 = 174 , PPC_REG_V24 = 175 , PPC_REG_V25 = 176 , PPC_REG_V26 = 177 , PPC_REG_V27 = 178 , PPC_REG_V28 = 179 , PPC_REG_V29 = 180 , PPC_REG_V30 = 181 , PPC_REG_V31 = 182 , PPC_REG_VS0 = 215 , PPC_REG_VS1 = 216 , PPC_REG_VS2 = 217 , PPC_REG_VS3 = 218 , PPC_REG_VS4 = 219 , PPC_REG_VS5 = 220 , PPC_REG_VS6 = 221 , PPC_REG_VS7 = 222 , PPC_REG_VS8 = 223 , PPC_REG_VS9 = 224 , PPC_REG_VS10 = 225 , PPC_REG_VS11 = 226 , PPC_REG_VS12 = 227 , PPC_REG_VS13 = 228 , PPC_REG_VS14 = 229 , PPC_REG_VS15 = 230 , PPC_REG_VS16 = 231 , PPC_REG_VS17 = 232 , PPC_REG_VS18 = 233 , PPC_REG_VS19 = 234 , PPC_REG_VS20 = 235 , PPC_REG_VS21 = 236 , PPC_REG_VS22 = 237 , PPC_REG_VS23 = 238 , PPC_REG_VS24 = 239 , PPC_REG_VS25 = 240 , PPC_REG_VS26 = 241 , PPC_REG_VS27 = 242 , PPC_REG_VS28 = 243 , PPC_REG_VS29 = 244 , PPC_REG_VS30 = 245 , PPC_REG_VS31 = 246 , PPC_REG_VS32 = 247 , PPC_REG_VS33 = 248 , PPC_REG_VS34 = 249 , PPC_REG_VS35 = 250 , PPC_REG_VS36 = 251 , PPC_REG_VS37 = 252 , PPC_REG_VS38 = 253 , PPC_REG_VS39 = 254 , PPC_REG_VS40 = 255 , PPC_REG_VS41 = 256 , PPC_REG_VS42 = 257 , PPC_REG_VS43 = 258 , PPC_REG_VS44 = 259 , PPC_REG_VS45 = 260 , PPC_REG_VS46 = 261 , PPC_REG_VS47 = 262 , PPC_REG_VS48 = 263 , PPC_REG_VS49 = 264 , PPC_REG_VS50 = 265 , PPC_REG_VS51 = 266 , PPC_REG_VS52 = 267 , PPC_REG_VS53 = 268 , PPC_REG_VS54 = 269 , PPC_REG_VS55 = 270 , PPC_REG_VS56 = 271 , PPC_REG_VS57 = 272 , PPC_REG_VS58 = 273 , PPC_REG_VS59 = 274 , PPC_REG_VS60 = 275 , PPC_REG_VS61 = 276 , PPC_REG_VS62 = 277 , PPC_REG_VS63 = 278 , PPC_REG_CR0EQ = 312 , PPC_REG_CR1EQ = 313 , PPC_REG_CR2EQ = 314 , PPC_REG_CR3EQ = 315 , PPC_REG_CR4EQ = 316 , PPC_REG_CR5EQ = 317 , PPC_REG_CR6EQ = 318 , PPC_REG_CR7EQ = 319 , PPC_REG_CR0GT = 320 , PPC_REG_CR1GT = 321 , PPC_REG_CR2GT = 322 , PPC_REG_CR3GT = 323 , PPC_REG_CR4GT = 324 , PPC_REG_CR5GT = 325 , PPC_REG_CR6GT = 326 , PPC_REG_CR7GT = 327 , PPC_REG_CR0LT = 328 , PPC_REG_CR1LT = 329 , PPC_REG_CR2LT = 330 , PPC_REG_CR3LT = 331 , PPC_REG_CR4LT = 332 , PPC_REG_CR5LT = 333 , PPC_REG_CR6LT = 334 , PPC_REG_CR7LT = 335 , PPC_REG_CR0UN = 336 , PPC_REG_CR1UN = 337 , PPC_REG_CR2UN = 338 , PPC_REG_CR3UN = 339 , PPC_REG_CR4UN = 340 , PPC_REG_CR5UN = 341 , PPC_REG_CR6UN = 342 , PPC_REG_CR7UN = 343 , PPC_REG_ENDING = 344 , } # [doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_mem { # [doc = "< base register"] pub base : ppc_reg , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_mem"] [:: std :: mem :: size_of :: < ppc_op_mem > () - 8usize] ; ["Alignment of ppc_op_mem"] [:: std :: mem :: align_of :: < ppc_op_mem > () - 4usize] ; ["Offset of field: ppc_op_mem::base"] [:: std :: mem :: offset_of ! (ppc_op_mem , base) - 0usize] ; ["Offset of field: ppc_op_mem::disp"] [:: std :: mem :: offset_of ! (ppc_op_mem , disp) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct ppc_op_crx { pub scale : :: std :: os :: raw :: c_uint , pub reg : ppc_reg , pub cond : ppc_bc , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of ppc_op_crx"] [:: std :: mem :: size_of :: < ppc_op_crx > () - 12usize] ; ["Alignment of ppc_op_crx"] [:: std :: mem :: align_of :: < ppc_op_crx > () - 4usize] ; ["Offset of field: ppc_op_crx::scale"] [:: std :: mem :: offset_of ! (ppc_op_crx , scale) - 0usize] ; ["Offset of field: ppc_op_crx::reg"] [:: std :: mem :: offset_of ! (ppc_op_crx , reg) - 4usize] ; ["Offset of field: ppc_op_crx::cond"] [:: std :: mem :: offset_of ! (ppc_op_crx , cond) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc_op { # [doc = "< operand type"] pub type_ : ppc_op_type , pub __bindgen_anon_1 : cs_ppc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_ppc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : ppc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : ppc_op_mem , # [doc = "< operand with condition register"] pub crx : ppc_op_crx , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_ppc_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_ppc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_ppc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_ppc_op__bindgen_ty_1::crx"] [:: std :: mem :: offset_of ! (cs_ppc_op__bindgen_ty_1 , crx) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc_op"] [:: std :: mem :: size_of :: < cs_ppc_op > () - 24usize] ; ["Alignment of cs_ppc_op"] [:: std :: mem :: align_of :: < cs_ppc_op > () - 8usize] ; ["Offset of field: cs_ppc_op::type_"] [:: std :: mem :: offset_of ! (cs_ppc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_ppc { # [doc = " branch code for branch instructions"] pub bc : ppc_bc , # [doc = " branch hint for branch instructions"] pub bh : ppc_bh , # [doc = " if update_cr0 = True, then this 'dot' insn updates CR0"] pub update_cr0 : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_ppc_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_ppc"] [:: std :: mem :: size_of :: < cs_ppc > () - 208usize] ; ["Alignment of cs_ppc"] [:: std :: mem :: align_of :: < cs_ppc > () - 8usize] ; ["Offset of field: cs_ppc::bc"] [:: std :: mem :: offset_of ! (cs_ppc , bc) - 0usize] ; ["Offset of field: cs_ppc::bh"] [:: std :: mem :: offset_of ! (cs_ppc , bh) - 4usize] ; ["Offset of field: cs_ppc::update_cr0"] [:: std :: mem :: offset_of ! (cs_ppc , update_cr0) - 8usize] ; ["Offset of field: cs_ppc::op_count"] [:: std :: mem :: offset_of ! (cs_ppc , op_count) - 9usize] ; ["Offset of field: cs_ppc::operands"] [:: std :: mem :: offset_of ! (cs_ppc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_ppc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}" , self . bc , self . bh , self . update_cr0 , self . op_count , self . operands) } } # [repr (u32)] # [doc = " PPC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn { PPC_INS_INVALID = 0 , PPC_INS_ADD = 1 , PPC_INS_ADDC = 2 , PPC_INS_ADDE = 3 , PPC_INS_ADDI = 4 , PPC_INS_ADDIC = 5 , PPC_INS_ADDIS = 6 , PPC_INS_ADDME = 7 , PPC_INS_ADDPCIS = 8 , PPC_INS_ADDZE = 9 , PPC_INS_AND = 10 , PPC_INS_ANDC = 11 , PPC_INS_ANDI = 12 , PPC_INS_ANDIS = 13 , PPC_INS_ATTN = 14 , PPC_INS_B = 15 , PPC_INS_BA = 16 , PPC_INS_BC = 17 , PPC_INS_BCA = 18 , PPC_INS_BCCTR = 19 , PPC_INS_BCCTRL = 20 , PPC_INS_BCDCFN = 21 , PPC_INS_BCDCFSQ = 22 , PPC_INS_BCDCFZ = 23 , PPC_INS_BCDCPSGN = 24 , PPC_INS_BCDCTN = 25 , PPC_INS_BCDCTSQ = 26 , PPC_INS_BCDCTZ = 27 , PPC_INS_BCDS = 28 , PPC_INS_BCDSETSGN = 29 , PPC_INS_BCDSR = 30 , PPC_INS_BCDTRUNC = 31 , PPC_INS_BCDUS = 32 , PPC_INS_BCDUTRUNC = 33 , PPC_INS_BCL = 34 , PPC_INS_BCLA = 35 , PPC_INS_BCLR = 36 , PPC_INS_BCLRL = 37 , PPC_INS_BCTR = 38 , PPC_INS_BCTRL = 39 , PPC_INS_BDNZ = 40 , PPC_INS_BDNZA = 41 , PPC_INS_BDNZF = 42 , PPC_INS_BDNZFA = 43 , PPC_INS_BDNZFL = 44 , PPC_INS_BDNZFLA = 45 , PPC_INS_BDNZFLR = 46 , PPC_INS_BDNZFLRL = 47 , PPC_INS_BDNZL = 48 , PPC_INS_BDNZLA = 49 , PPC_INS_BDNZLR = 50 , PPC_INS_BDNZLRL = 51 , PPC_INS_BDNZT = 52 , PPC_INS_BDNZTA = 53 , PPC_INS_BDNZTL = 54 , PPC_INS_BDNZTLA = 55 , PPC_INS_BDNZTLR = 56 , PPC_INS_BDNZTLRL = 57 , PPC_INS_BDZ = 58 , PPC_INS_BDZA = 59 , PPC_INS_BDZF = 60 , PPC_INS_BDZFA = 61 , PPC_INS_BDZFL = 62 , PPC_INS_BDZFLA = 63 , PPC_INS_BDZFLR = 64 , PPC_INS_BDZFLRL = 65 , PPC_INS_BDZL = 66 , PPC_INS_BDZLA = 67 , PPC_INS_BDZLR = 68 , PPC_INS_BDZLRL = 69 , PPC_INS_BDZT = 70 , PPC_INS_BDZTA = 71 , PPC_INS_BDZTL = 72 , PPC_INS_BDZTLA = 73 , PPC_INS_BDZTLR = 74 , PPC_INS_BDZTLRL = 75 , PPC_INS_BEQ = 76 , PPC_INS_BEQA = 77 , PPC_INS_BEQCTR = 78 , PPC_INS_BEQCTRL = 79 , PPC_INS_BEQL = 80 , PPC_INS_BEQLA = 81 , PPC_INS_BEQLR = 82 , PPC_INS_BEQLRL = 83 , PPC_INS_BF = 84 , PPC_INS_BFA = 85 , PPC_INS_BFCTR = 86 , PPC_INS_BFCTRL = 87 , PPC_INS_BFL = 88 , PPC_INS_BFLA = 89 , PPC_INS_BFLR = 90 , PPC_INS_BFLRL = 91 , PPC_INS_BGE = 92 , PPC_INS_BGEA = 93 , PPC_INS_BGECTR = 94 , PPC_INS_BGECTRL = 95 , PPC_INS_BGEL = 96 , PPC_INS_BGELA = 97 , PPC_INS_BGELR = 98 , PPC_INS_BGELRL = 99 , PPC_INS_BGT = 100 , PPC_INS_BGTA = 101 , PPC_INS_BGTCTR = 102 , PPC_INS_BGTCTRL = 103 , PPC_INS_BGTL = 104 , PPC_INS_BGTLA = 105 , PPC_INS_BGTLR = 106 , PPC_INS_BGTLRL = 107 , PPC_INS_BL = 108 , PPC_INS_BLA = 109 , PPC_INS_BLE = 110 , PPC_INS_BLEA = 111 , PPC_INS_BLECTR = 112 , PPC_INS_BLECTRL = 113 , PPC_INS_BLEL = 114 , PPC_INS_BLELA = 115 , PPC_INS_BLELR = 116 , PPC_INS_BLELRL = 117 , PPC_INS_BLR = 118 , PPC_INS_BLRL = 119 , PPC_INS_BLT = 120 , PPC_INS_BLTA = 121 , PPC_INS_BLTCTR = 122 , PPC_INS_BLTCTRL = 123 , PPC_INS_BLTL = 124 , PPC_INS_BLTLA = 125 , PPC_INS_BLTLR = 126 , PPC_INS_BLTLRL = 127 , PPC_INS_BNE = 128 , PPC_INS_BNEA = 129 , PPC_INS_BNECTR = 130 , PPC_INS_BNECTRL = 131 , PPC_INS_BNEL = 132 , PPC_INS_BNELA = 133 , PPC_INS_BNELR = 134 , PPC_INS_BNELRL = 135 , PPC_INS_BNG = 136 , PPC_INS_BNGA = 137 , PPC_INS_BNGCTR = 138 , PPC_INS_BNGCTRL = 139 , PPC_INS_BNGL = 140 , PPC_INS_BNGLA = 141 , PPC_INS_BNGLR = 142 , PPC_INS_BNGLRL = 143 , PPC_INS_BNL = 144 , PPC_INS_BNLA = 145 , PPC_INS_BNLCTR = 146 , PPC_INS_BNLCTRL = 147 , PPC_INS_BNLL = 148 , PPC_INS_BNLLA = 149 , PPC_INS_BNLLR = 150 , PPC_INS_BNLLRL = 151 , PPC_INS_BNS = 152 , PPC_INS_BNSA = 153 , PPC_INS_BNSCTR = 154 , PPC_INS_BNSCTRL = 155 , PPC_INS_BNSL = 156 , PPC_INS_BNSLA = 157 , PPC_INS_BNSLR = 158 , PPC_INS_BNSLRL = 159 , PPC_INS_BNU = 160 , PPC_INS_BNUA = 161 , PPC_INS_BNUCTR = 162 , PPC_INS_BNUCTRL = 163 , PPC_INS_BNUL = 164 , PPC_INS_BNULA = 165 , PPC_INS_BNULR = 166 , PPC_INS_BNULRL = 167 , PPC_INS_BPERMD = 168 , PPC_INS_BRINC = 169 , PPC_INS_BSO = 170 , PPC_INS_BSOA = 171 , PPC_INS_BSOCTR = 172 , PPC_INS_BSOCTRL = 173 , PPC_INS_BSOL = 174 , PPC_INS_BSOLA = 175 , PPC_INS_BSOLR = 176 , PPC_INS_BSOLRL = 177 , PPC_INS_BT = 178 , PPC_INS_BTA = 179 , PPC_INS_BTCTR = 180 , PPC_INS_BTCTRL = 181 , PPC_INS_BTL = 182 , PPC_INS_BTLA = 183 , PPC_INS_BTLR = 184 , PPC_INS_BTLRL = 185 , PPC_INS_BUN = 186 , PPC_INS_BUNA = 187 , PPC_INS_BUNCTR = 188 , PPC_INS_BUNCTRL = 189 , PPC_INS_BUNL = 190 , PPC_INS_BUNLA = 191 , PPC_INS_BUNLR = 192 , PPC_INS_BUNLRL = 193 , PPC_INS_CLRBHRB = 194 , PPC_INS_CLRLDI = 195 , PPC_INS_CLRLSLDI = 196 , PPC_INS_CLRLSLWI = 197 , PPC_INS_CLRLWI = 198 , PPC_INS_CLRRDI = 199 , PPC_INS_CLRRWI = 200 , PPC_INS_CMP = 201 , PPC_INS_CMPB = 202 , PPC_INS_CMPD = 203 , PPC_INS_CMPDI = 204 , PPC_INS_CMPEQB = 205 , PPC_INS_CMPI = 206 , PPC_INS_CMPL = 207 , PPC_INS_CMPLD = 208 , PPC_INS_CMPLDI = 209 , PPC_INS_CMPLI = 210 , PPC_INS_CMPLW = 211 , PPC_INS_CMPLWI = 212 , PPC_INS_CMPRB = 213 , PPC_INS_CMPW = 214 , PPC_INS_CMPWI = 215 , PPC_INS_CNTLZD = 216 , PPC_INS_CNTLZW = 217 , PPC_INS_CNTTZD = 218 , PPC_INS_CNTTZW = 219 , PPC_INS_COPY = 220 , PPC_INS_COPY_FIRST = 221 , PPC_INS_CP_ABORT = 222 , PPC_INS_CRAND = 223 , PPC_INS_CRANDC = 224 , PPC_INS_CRCLR = 225 , PPC_INS_CREQV = 226 , PPC_INS_CRMOVE = 227 , PPC_INS_CRNAND = 228 , PPC_INS_CRNOR = 229 , PPC_INS_CRNOT = 230 , PPC_INS_CROR = 231 , PPC_INS_CRORC = 232 , PPC_INS_CRSET = 233 , PPC_INS_CRXOR = 234 , PPC_INS_DARN = 235 , PPC_INS_DCBA = 236 , PPC_INS_DCBF = 237 , PPC_INS_DCBFEP = 238 , PPC_INS_DCBFL = 239 , PPC_INS_DCBFLP = 240 , PPC_INS_DCBI = 241 , PPC_INS_DCBST = 242 , PPC_INS_DCBSTEP = 243 , PPC_INS_DCBT = 244 , PPC_INS_DCBTCT = 245 , PPC_INS_DCBTDS = 246 , PPC_INS_DCBTEP = 247 , PPC_INS_DCBTST = 248 , PPC_INS_DCBTSTCT = 249 , PPC_INS_DCBTSTDS = 250 , PPC_INS_DCBTSTEP = 251 , PPC_INS_DCBTSTT = 252 , PPC_INS_DCBTT = 253 , PPC_INS_DCBZ = 254 , PPC_INS_DCBZEP = 255 , PPC_INS_DCBZL = 256 , PPC_INS_DCBZLEP = 257 , PPC_INS_DCCCI = 258 , PPC_INS_DCI = 259 , PPC_INS_DIVD = 260 , PPC_INS_DIVDE = 261 , PPC_INS_DIVDEU = 262 , PPC_INS_DIVDU = 263 , PPC_INS_DIVW = 264 , PPC_INS_DIVWE = 265 , PPC_INS_DIVWEU = 266 , PPC_INS_DIVWU = 267 , PPC_INS_DSS = 268 , PPC_INS_DSSALL = 269 , PPC_INS_DST = 270 , PPC_INS_DSTST = 271 , PPC_INS_DSTSTT = 272 , PPC_INS_DSTT = 273 , PPC_INS_EFDABS = 274 , PPC_INS_EFDADD = 275 , PPC_INS_EFDCFS = 276 , PPC_INS_EFDCFSF = 277 , PPC_INS_EFDCFSI = 278 , PPC_INS_EFDCFSID = 279 , PPC_INS_EFDCFUF = 280 , PPC_INS_EFDCFUI = 281 , PPC_INS_EFDCFUID = 282 , PPC_INS_EFDCMPEQ = 283 , PPC_INS_EFDCMPGT = 284 , PPC_INS_EFDCMPLT = 285 , PPC_INS_EFDCTSF = 286 , PPC_INS_EFDCTSI = 287 , PPC_INS_EFDCTSIDZ = 288 , PPC_INS_EFDCTSIZ = 289 , PPC_INS_EFDCTUF = 290 , PPC_INS_EFDCTUI = 291 , PPC_INS_EFDCTUIDZ = 292 , PPC_INS_EFDCTUIZ = 293 , PPC_INS_EFDDIV = 294 , PPC_INS_EFDMUL = 295 , PPC_INS_EFDNABS = 296 , PPC_INS_EFDNEG = 297 , PPC_INS_EFDSUB = 298 , PPC_INS_EFDTSTEQ = 299 , PPC_INS_EFDTSTGT = 300 , PPC_INS_EFDTSTLT = 301 , PPC_INS_EFSABS = 302 , PPC_INS_EFSADD = 303 , PPC_INS_EFSCFD = 304 , PPC_INS_EFSCFSF = 305 , PPC_INS_EFSCFSI = 306 , PPC_INS_EFSCFUF = 307 , PPC_INS_EFSCFUI = 308 , PPC_INS_EFSCMPEQ = 309 , PPC_INS_EFSCMPGT = 310 , PPC_INS_EFSCMPLT = 311 , PPC_INS_EFSCTSF = 312 , PPC_INS_EFSCTSI = 313 , PPC_INS_EFSCTSIZ = 314 , PPC_INS_EFSCTUF = 315 , PPC_INS_EFSCTUI = 316 , PPC_INS_EFSCTUIZ = 317 , PPC_INS_EFSDIV = 318 , PPC_INS_EFSMUL = 319 , PPC_INS_EFSNABS = 320 , PPC_INS_EFSNEG = 321 , PPC_INS_EFSSUB = 322 , PPC_INS_EFSTSTEQ = 323 , PPC_INS_EFSTSTGT = 324 , PPC_INS_EFSTSTLT = 325 , PPC_INS_EIEIO = 326 , PPC_INS_EQV = 327 , PPC_INS_EVABS = 328 , PPC_INS_EVADDIW = 329 , PPC_INS_EVADDSMIAAW = 330 , PPC_INS_EVADDSSIAAW = 331 , PPC_INS_EVADDUMIAAW = 332 , PPC_INS_EVADDUSIAAW = 333 , PPC_INS_EVADDW = 334 , PPC_INS_EVAND = 335 , PPC_INS_EVANDC = 336 , PPC_INS_EVCMPEQ = 337 , PPC_INS_EVCMPGTS = 338 , PPC_INS_EVCMPGTU = 339 , PPC_INS_EVCMPLTS = 340 , PPC_INS_EVCMPLTU = 341 , PPC_INS_EVCNTLSW = 342 , PPC_INS_EVCNTLZW = 343 , PPC_INS_EVDIVWS = 344 , PPC_INS_EVDIVWU = 345 , PPC_INS_EVEQV = 346 , PPC_INS_EVEXTSB = 347 , PPC_INS_EVEXTSH = 348 , PPC_INS_EVFSABS = 349 , PPC_INS_EVFSADD = 350 , PPC_INS_EVFSCFSF = 351 , PPC_INS_EVFSCFSI = 352 , PPC_INS_EVFSCFUF = 353 , PPC_INS_EVFSCFUI = 354 , PPC_INS_EVFSCMPEQ = 355 , PPC_INS_EVFSCMPGT = 356 , PPC_INS_EVFSCMPLT = 357 , PPC_INS_EVFSCTSF = 358 , PPC_INS_EVFSCTSI = 359 , PPC_INS_EVFSCTSIZ = 360 , PPC_INS_EVFSCTUI = 361 , PPC_INS_EVFSDIV = 362 , PPC_INS_EVFSMUL = 363 , PPC_INS_EVFSNABS = 364 , PPC_INS_EVFSNEG = 365 , PPC_INS_EVFSSUB = 366 , PPC_INS_EVFSTSTEQ = 367 , PPC_INS_EVFSTSTGT = 368 , PPC_INS_EVFSTSTLT = 369 , PPC_INS_EVLDD = 370 , PPC_INS_EVLDDX = 371 , PPC_INS_EVLDH = 372 , PPC_INS_EVLDHX = 373 , PPC_INS_EVLDW = 374 , PPC_INS_EVLDWX = 375 , PPC_INS_EVLHHESPLAT = 376 , PPC_INS_EVLHHESPLATX = 377 , PPC_INS_EVLHHOSSPLAT = 378 , PPC_INS_EVLHHOSSPLATX = 379 , PPC_INS_EVLHHOUSPLAT = 380 , PPC_INS_EVLHHOUSPLATX = 381 , PPC_INS_EVLWHE = 382 , PPC_INS_EVLWHEX = 383 , PPC_INS_EVLWHOS = 384 , PPC_INS_EVLWHOSX = 385 , PPC_INS_EVLWHOU = 386 , PPC_INS_EVLWHOUX = 387 , PPC_INS_EVLWHSPLAT = 388 , PPC_INS_EVLWHSPLATX = 389 , PPC_INS_EVLWWSPLAT = 390 , PPC_INS_EVLWWSPLATX = 391 , PPC_INS_EVMERGEHI = 392 , PPC_INS_EVMERGEHILO = 393 , PPC_INS_EVMERGELO = 394 , PPC_INS_EVMERGELOHI = 395 , PPC_INS_EVMHEGSMFAA = 396 , PPC_INS_EVMHEGSMFAN = 397 , PPC_INS_EVMHEGSMIAA = 398 , PPC_INS_EVMHEGSMIAN = 399 , PPC_INS_EVMHEGUMIAA = 400 , PPC_INS_EVMHEGUMIAN = 401 , PPC_INS_EVMHESMF = 402 , PPC_INS_EVMHESMFA = 403 , PPC_INS_EVMHESMFAAW = 404 , PPC_INS_EVMHESMFANW = 405 , PPC_INS_EVMHESMI = 406 , PPC_INS_EVMHESMIA = 407 , PPC_INS_EVMHESMIAAW = 408 , PPC_INS_EVMHESMIANW = 409 , PPC_INS_EVMHESSF = 410 , PPC_INS_EVMHESSFA = 411 , PPC_INS_EVMHESSFAAW = 412 , PPC_INS_EVMHESSFANW = 413 , PPC_INS_EVMHESSIAAW = 414 , PPC_INS_EVMHESSIANW = 415 , PPC_INS_EVMHEUMI = 416 , PPC_INS_EVMHEUMIA = 417 , PPC_INS_EVMHEUMIAAW = 418 , PPC_INS_EVMHEUMIANW = 419 , PPC_INS_EVMHEUSIAAW = 420 , PPC_INS_EVMHEUSIANW = 421 , PPC_INS_EVMHOGSMFAA = 422 , PPC_INS_EVMHOGSMFAN = 423 , PPC_INS_EVMHOGSMIAA = 424 , PPC_INS_EVMHOGSMIAN = 425 , PPC_INS_EVMHOGUMIAA = 426 , PPC_INS_EVMHOGUMIAN = 427 , PPC_INS_EVMHOSMF = 428 , PPC_INS_EVMHOSMFA = 429 , PPC_INS_EVMHOSMFAAW = 430 , PPC_INS_EVMHOSMFANW = 431 , PPC_INS_EVMHOSMI = 432 , PPC_INS_EVMHOSMIA = 433 , PPC_INS_EVMHOSMIAAW = 434 , PPC_INS_EVMHOSMIANW = 435 , PPC_INS_EVMHOSSF = 436 , PPC_INS_EVMHOSSFA = 437 , PPC_INS_EVMHOSSFAAW = 438 , PPC_INS_EVMHOSSFANW = 439 , PPC_INS_EVMHOSSIAAW = 440 , PPC_INS_EVMHOSSIANW = 441 , PPC_INS_EVMHOUMI = 442 , PPC_INS_EVMHOUMIA = 443 , PPC_INS_EVMHOUMIAAW = 444 , PPC_INS_EVMHOUMIANW = 445 , PPC_INS_EVMHOUSIAAW = 446 , PPC_INS_EVMHOUSIANW = 447 , PPC_INS_EVMRA = 448 , PPC_INS_EVMWHSMF = 449 , PPC_INS_EVMWHSMFA = 450 , PPC_INS_EVMWHSMI = 451 , PPC_INS_EVMWHSMIA = 452 , PPC_INS_EVMWHSSF = 453 , PPC_INS_EVMWHSSFA = 454 , PPC_INS_EVMWHUMI = 455 , PPC_INS_EVMWHUMIA = 456 , PPC_INS_EVMWLSMIAAW = 457 , PPC_INS_EVMWLSMIANW = 458 , PPC_INS_EVMWLSSIAAW = 459 , PPC_INS_EVMWLSSIANW = 460 , PPC_INS_EVMWLUMI = 461 , PPC_INS_EVMWLUMIA = 462 , PPC_INS_EVMWLUMIAAW = 463 , PPC_INS_EVMWLUMIANW = 464 , PPC_INS_EVMWLUSIAAW = 465 , PPC_INS_EVMWLUSIANW = 466 , PPC_INS_EVMWSMF = 467 , PPC_INS_EVMWSMFA = 468 , PPC_INS_EVMWSMFAA = 469 , PPC_INS_EVMWSMFAN = 470 , PPC_INS_EVMWSMI = 471 , PPC_INS_EVMWSMIA = 472 , PPC_INS_EVMWSMIAA = 473 , PPC_INS_EVMWSMIAN = 474 , PPC_INS_EVMWSSF = 475 , PPC_INS_EVMWSSFA = 476 , PPC_INS_EVMWSSFAA = 477 , PPC_INS_EVMWSSFAN = 478 , PPC_INS_EVMWUMI = 479 , PPC_INS_EVMWUMIA = 480 , PPC_INS_EVMWUMIAA = 481 , PPC_INS_EVMWUMIAN = 482 , PPC_INS_EVNAND = 483 , PPC_INS_EVNEG = 484 , PPC_INS_EVNOR = 485 , PPC_INS_EVOR = 486 , PPC_INS_EVORC = 487 , PPC_INS_EVRLW = 488 , PPC_INS_EVRLWI = 489 , PPC_INS_EVRNDW = 490 , PPC_INS_EVSEL = 491 , PPC_INS_EVSLW = 492 , PPC_INS_EVSLWI = 493 , PPC_INS_EVSPLATFI = 494 , PPC_INS_EVSPLATI = 495 , PPC_INS_EVSRWIS = 496 , PPC_INS_EVSRWIU = 497 , PPC_INS_EVSRWS = 498 , PPC_INS_EVSRWU = 499 , PPC_INS_EVSTDD = 500 , PPC_INS_EVSTDDX = 501 , PPC_INS_EVSTDH = 502 , PPC_INS_EVSTDHX = 503 , PPC_INS_EVSTDW = 504 , PPC_INS_EVSTDWX = 505 , PPC_INS_EVSTWHE = 506 , PPC_INS_EVSTWHEX = 507 , PPC_INS_EVSTWHO = 508 , PPC_INS_EVSTWHOX = 509 , PPC_INS_EVSTWWE = 510 , PPC_INS_EVSTWWEX = 511 , PPC_INS_EVSTWWO = 512 , PPC_INS_EVSTWWOX = 513 , PPC_INS_EVSUBFSMIAAW = 514 , PPC_INS_EVSUBFSSIAAW = 515 , PPC_INS_EVSUBFUMIAAW = 516 , PPC_INS_EVSUBFUSIAAW = 517 , PPC_INS_EVSUBFW = 518 , PPC_INS_EVSUBIFW = 519 , PPC_INS_EVXOR = 520 , PPC_INS_EXTLDI = 521 , PPC_INS_EXTLWI = 522 , PPC_INS_EXTRDI = 523 , PPC_INS_EXTRWI = 524 , PPC_INS_EXTSB = 525 , PPC_INS_EXTSH = 526 , PPC_INS_EXTSW = 527 , PPC_INS_EXTSWSLI = 528 , PPC_INS_FABS = 529 , PPC_INS_FADD = 530 , PPC_INS_FADDS = 531 , PPC_INS_FCFID = 532 , PPC_INS_FCFIDS = 533 , PPC_INS_FCFIDU = 534 , PPC_INS_FCFIDUS = 535 , PPC_INS_FCMPU = 536 , PPC_INS_FCPSGN = 537 , PPC_INS_FCTID = 538 , PPC_INS_FCTIDU = 539 , PPC_INS_FCTIDUZ = 540 , PPC_INS_FCTIDZ = 541 , PPC_INS_FCTIW = 542 , PPC_INS_FCTIWU = 543 , PPC_INS_FCTIWUZ = 544 , PPC_INS_FCTIWZ = 545 , PPC_INS_FDIV = 546 , PPC_INS_FDIVS = 547 , PPC_INS_FMADD = 548 , PPC_INS_FMADDS = 549 , PPC_INS_FMR = 550 , PPC_INS_FMSUB = 551 , PPC_INS_FMSUBS = 552 , PPC_INS_FMUL = 553 , PPC_INS_FMULS = 554 , PPC_INS_FNABS = 555 , PPC_INS_FNEG = 556 , PPC_INS_FNMADD = 557 , PPC_INS_FNMADDS = 558 , PPC_INS_FNMSUB = 559 , PPC_INS_FNMSUBS = 560 , PPC_INS_FRE = 561 , PPC_INS_FRES = 562 , PPC_INS_FRIM = 563 , PPC_INS_FRIN = 564 , PPC_INS_FRIP = 565 , PPC_INS_FRIZ = 566 , PPC_INS_FRSP = 567 , PPC_INS_FRSQRTE = 568 , PPC_INS_FRSQRTES = 569 , PPC_INS_FSEL = 570 , PPC_INS_FSQRT = 571 , PPC_INS_FSQRTS = 572 , PPC_INS_FSUB = 573 , PPC_INS_FSUBS = 574 , PPC_INS_FTDIV = 575 , PPC_INS_FTSQRT = 576 , PPC_INS_HRFID = 577 , PPC_INS_ICBI = 578 , PPC_INS_ICBIEP = 579 , PPC_INS_ICBLC = 580 , PPC_INS_ICBLQ = 581 , PPC_INS_ICBT = 582 , PPC_INS_ICBTLS = 583 , PPC_INS_ICCCI = 584 , PPC_INS_ICI = 585 , PPC_INS_INSLWI = 586 , PPC_INS_INSRDI = 587 , PPC_INS_INSRWI = 588 , PPC_INS_ISEL = 589 , PPC_INS_ISYNC = 590 , PPC_INS_LA = 591 , PPC_INS_LBARX = 592 , PPC_INS_LBEPX = 593 , PPC_INS_LBZ = 594 , PPC_INS_LBZCIX = 595 , PPC_INS_LBZU = 596 , PPC_INS_LBZUX = 597 , PPC_INS_LBZX = 598 , PPC_INS_LD = 599 , PPC_INS_LDARX = 600 , PPC_INS_LDAT = 601 , PPC_INS_LDBRX = 602 , PPC_INS_LDCIX = 603 , PPC_INS_LDMX = 604 , PPC_INS_LDU = 605 , PPC_INS_LDUX = 606 , PPC_INS_LDX = 607 , PPC_INS_LFD = 608 , PPC_INS_LFDEPX = 609 , PPC_INS_LFDU = 610 , PPC_INS_LFDUX = 611 , PPC_INS_LFDX = 612 , PPC_INS_LFIWAX = 613 , PPC_INS_LFIWZX = 614 , PPC_INS_LFS = 615 , PPC_INS_LFSU = 616 , PPC_INS_LFSUX = 617 , PPC_INS_LFSX = 618 , PPC_INS_LHA = 619 , PPC_INS_LHARX = 620 , PPC_INS_LHAU = 621 , PPC_INS_LHAUX = 622 , PPC_INS_LHAX = 623 , PPC_INS_LHBRX = 624 , PPC_INS_LHEPX = 625 , PPC_INS_LHZ = 626 , PPC_INS_LHZCIX = 627 , PPC_INS_LHZU = 628 , PPC_INS_LHZUX = 629 , PPC_INS_LHZX = 630 , PPC_INS_LI = 631 , PPC_INS_LIS = 632 , PPC_INS_LMW = 633 , PPC_INS_LNIA = 634 , PPC_INS_LSWI = 635 , PPC_INS_LVEBX = 636 , PPC_INS_LVEHX = 637 , PPC_INS_LVEWX = 638 , PPC_INS_LVSL = 639 , PPC_INS_LVSR = 640 , PPC_INS_LVX = 641 , PPC_INS_LVXL = 642 , PPC_INS_LWA = 643 , PPC_INS_LWARX = 644 , PPC_INS_LWAT = 645 , PPC_INS_LWAUX = 646 , PPC_INS_LWAX = 647 , PPC_INS_LWBRX = 648 , PPC_INS_LWEPX = 649 , PPC_INS_LWSYNC = 650 , PPC_INS_LWZ = 651 , PPC_INS_LWZCIX = 652 , PPC_INS_LWZU = 653 , PPC_INS_LWZUX = 654 , PPC_INS_LWZX = 655 , PPC_INS_LXSD = 656 , PPC_INS_LXSDX = 657 , PPC_INS_LXSIBZX = 658 , PPC_INS_LXSIHZX = 659 , PPC_INS_LXSIWAX = 660 , PPC_INS_LXSIWZX = 661 , PPC_INS_LXSSP = 662 , PPC_INS_LXSSPX = 663 , PPC_INS_LXV = 664 , PPC_INS_LXVB16X = 665 , PPC_INS_LXVD2X = 666 , PPC_INS_LXVDSX = 667 , PPC_INS_LXVH8X = 668 , PPC_INS_LXVL = 669 , PPC_INS_LXVLL = 670 , PPC_INS_LXVW4X = 671 , PPC_INS_LXVWSX = 672 , PPC_INS_LXVX = 673 , PPC_INS_MADDHD = 674 , PPC_INS_MADDHDU = 675 , PPC_INS_MADDLD = 676 , PPC_INS_MBAR = 677 , PPC_INS_MCRF = 678 , PPC_INS_MCRFS = 679 , PPC_INS_MCRXRX = 680 , PPC_INS_MFAMR = 681 , PPC_INS_MFASR = 682 , PPC_INS_MFBHRBE = 683 , PPC_INS_MFBR0 = 684 , PPC_INS_MFBR1 = 685 , PPC_INS_MFBR2 = 686 , PPC_INS_MFBR3 = 687 , PPC_INS_MFBR4 = 688 , PPC_INS_MFBR5 = 689 , PPC_INS_MFBR6 = 690 , PPC_INS_MFBR7 = 691 , PPC_INS_MFCFAR = 692 , PPC_INS_MFCR = 693 , PPC_INS_MFCTR = 694 , PPC_INS_MFDAR = 695 , PPC_INS_MFDBATL = 696 , PPC_INS_MFDBATU = 697 , PPC_INS_MFDCCR = 698 , PPC_INS_MFDCR = 699 , PPC_INS_MFDEAR = 700 , PPC_INS_MFDEC = 701 , PPC_INS_MFDSCR = 702 , PPC_INS_MFDSISR = 703 , PPC_INS_MFESR = 704 , PPC_INS_MFFPRD = 705 , PPC_INS_MFFS = 706 , PPC_INS_MFFSCDRN = 707 , PPC_INS_MFFSCDRNI = 708 , PPC_INS_MFFSCE = 709 , PPC_INS_MFFSCRN = 710 , PPC_INS_MFFSCRNI = 711 , PPC_INS_MFFSL = 712 , PPC_INS_MFIBATL = 713 , PPC_INS_MFIBATU = 714 , PPC_INS_MFICCR = 715 , PPC_INS_MFLR = 716 , PPC_INS_MFMSR = 717 , PPC_INS_MFOCRF = 718 , PPC_INS_MFPID = 719 , PPC_INS_MFPMR = 720 , PPC_INS_MFPVR = 721 , PPC_INS_MFRTCL = 722 , PPC_INS_MFRTCU = 723 , PPC_INS_MFSDR1 = 724 , PPC_INS_MFSPEFSCR = 725 , PPC_INS_MFSPR = 726 , PPC_INS_MFSPRG = 727 , PPC_INS_MFSPRG0 = 728 , PPC_INS_MFSPRG1 = 729 , PPC_INS_MFSPRG2 = 730 , PPC_INS_MFSPRG3 = 731 , PPC_INS_MFSPRG4 = 732 , PPC_INS_MFSPRG5 = 733 , PPC_INS_MFSPRG6 = 734 , PPC_INS_MFSPRG7 = 735 , PPC_INS_MFSR = 736 , PPC_INS_MFSRIN = 737 , PPC_INS_MFSRR0 = 738 , PPC_INS_MFSRR1 = 739 , PPC_INS_MFSRR2 = 740 , PPC_INS_MFSRR3 = 741 , PPC_INS_MFTB = 742 , PPC_INS_MFTBHI = 743 , PPC_INS_MFTBL = 744 , PPC_INS_MFTBLO = 745 , PPC_INS_MFTBU = 746 , PPC_INS_MFTCR = 747 , PPC_INS_MFVRD = 748 , PPC_INS_MFVRSAVE = 749 , PPC_INS_MFVSCR = 750 , PPC_INS_MFVSRD = 751 , PPC_INS_MFVSRLD = 752 , PPC_INS_MFVSRWZ = 753 , PPC_INS_MFXER = 754 , PPC_INS_MODSD = 755 , PPC_INS_MODSW = 756 , PPC_INS_MODUD = 757 , PPC_INS_MODUW = 758 , PPC_INS_MR = 759 , PPC_INS_MSGSYNC = 760 , PPC_INS_MSYNC = 761 , PPC_INS_MTAMR = 762 , PPC_INS_MTASR = 763 , PPC_INS_MTBR0 = 764 , PPC_INS_MTBR1 = 765 , PPC_INS_MTBR2 = 766 , PPC_INS_MTBR3 = 767 , PPC_INS_MTBR4 = 768 , PPC_INS_MTBR5 = 769 , PPC_INS_MTBR6 = 770 , PPC_INS_MTBR7 = 771 , PPC_INS_MTCFAR = 772 , PPC_INS_MTCR = 773 , PPC_INS_MTCRF = 774 , PPC_INS_MTCTR = 775 , PPC_INS_MTDAR = 776 , PPC_INS_MTDBATL = 777 , PPC_INS_MTDBATU = 778 , PPC_INS_MTDCCR = 779 , PPC_INS_MTDCR = 780 , PPC_INS_MTDEAR = 781 , PPC_INS_MTDEC = 782 , PPC_INS_MTDSCR = 783 , PPC_INS_MTDSISR = 784 , PPC_INS_MTESR = 785 , PPC_INS_MTFSB0 = 786 , PPC_INS_MTFSB1 = 787 , PPC_INS_MTFSF = 788 , PPC_INS_MTFSFI = 789 , PPC_INS_MTIBATL = 790 , PPC_INS_MTIBATU = 791 , PPC_INS_MTICCR = 792 , PPC_INS_MTLR = 793 , PPC_INS_MTMSR = 794 , PPC_INS_MTMSRD = 795 , PPC_INS_MTOCRF = 796 , PPC_INS_MTPID = 797 , PPC_INS_MTPMR = 798 , PPC_INS_MTSDR1 = 799 , PPC_INS_MTSPEFSCR = 800 , PPC_INS_MTSPR = 801 , PPC_INS_MTSPRG = 802 , PPC_INS_MTSPRG0 = 803 , PPC_INS_MTSPRG1 = 804 , PPC_INS_MTSPRG2 = 805 , PPC_INS_MTSPRG3 = 806 , PPC_INS_MTSPRG4 = 807 , PPC_INS_MTSPRG5 = 808 , PPC_INS_MTSPRG6 = 809 , PPC_INS_MTSPRG7 = 810 , PPC_INS_MTSR = 811 , PPC_INS_MTSRIN = 812 , PPC_INS_MTSRR0 = 813 , PPC_INS_MTSRR1 = 814 , PPC_INS_MTSRR2 = 815 , PPC_INS_MTSRR3 = 816 , PPC_INS_MTTBHI = 817 , PPC_INS_MTTBL = 818 , PPC_INS_MTTBLO = 819 , PPC_INS_MTTBU = 820 , PPC_INS_MTTCR = 821 , PPC_INS_MTVRSAVE = 822 , PPC_INS_MTVSCR = 823 , PPC_INS_MTVSRD = 824 , PPC_INS_MTVSRDD = 825 , PPC_INS_MTVSRWA = 826 , PPC_INS_MTVSRWS = 827 , PPC_INS_MTVSRWZ = 828 , PPC_INS_MTXER = 829 , PPC_INS_MULHD = 830 , PPC_INS_MULHDU = 831 , PPC_INS_MULHW = 832 , PPC_INS_MULHWU = 833 , PPC_INS_MULLD = 834 , PPC_INS_MULLI = 835 , PPC_INS_MULLW = 836 , PPC_INS_NAND = 837 , PPC_INS_NAP = 838 , PPC_INS_NEG = 839 , PPC_INS_NOP = 840 , PPC_INS_NOR = 841 , PPC_INS_NOT = 842 , PPC_INS_OR = 843 , PPC_INS_ORC = 844 , PPC_INS_ORI = 845 , PPC_INS_ORIS = 846 , PPC_INS_PASTE = 847 , PPC_INS_PASTE_LAST = 848 , PPC_INS_POPCNTB = 849 , PPC_INS_POPCNTD = 850 , PPC_INS_POPCNTW = 851 , PPC_INS_PTESYNC = 852 , PPC_INS_QVALIGNI = 853 , PPC_INS_QVESPLATI = 854 , PPC_INS_QVFABS = 855 , PPC_INS_QVFADD = 856 , PPC_INS_QVFADDS = 857 , PPC_INS_QVFAND = 858 , PPC_INS_QVFANDC = 859 , PPC_INS_QVFCFID = 860 , PPC_INS_QVFCFIDS = 861 , PPC_INS_QVFCFIDU = 862 , PPC_INS_QVFCFIDUS = 863 , PPC_INS_QVFCLR = 864 , PPC_INS_QVFCMPEQ = 865 , PPC_INS_QVFCMPGT = 866 , PPC_INS_QVFCMPLT = 867 , PPC_INS_QVFCPSGN = 868 , PPC_INS_QVFCTFB = 869 , PPC_INS_QVFCTID = 870 , PPC_INS_QVFCTIDU = 871 , PPC_INS_QVFCTIDUZ = 872 , PPC_INS_QVFCTIDZ = 873 , PPC_INS_QVFCTIW = 874 , PPC_INS_QVFCTIWU = 875 , PPC_INS_QVFCTIWUZ = 876 , PPC_INS_QVFCTIWZ = 877 , PPC_INS_QVFEQU = 878 , PPC_INS_QVFLOGICAL = 879 , PPC_INS_QVFMADD = 880 , PPC_INS_QVFMADDS = 881 , PPC_INS_QVFMR = 882 , PPC_INS_QVFMSUB = 883 , PPC_INS_QVFMSUBS = 884 , PPC_INS_QVFMUL = 885 , PPC_INS_QVFMULS = 886 , PPC_INS_QVFNABS = 887 , PPC_INS_QVFNAND = 888 , PPC_INS_QVFNEG = 889 , PPC_INS_QVFNMADD = 890 , PPC_INS_QVFNMADDS = 891 , PPC_INS_QVFNMSUB = 892 , PPC_INS_QVFNMSUBS = 893 , PPC_INS_QVFNOR = 894 , PPC_INS_QVFNOT = 895 , PPC_INS_QVFOR = 896 , PPC_INS_QVFORC = 897 , PPC_INS_QVFPERM = 898 , PPC_INS_QVFRE = 899 , PPC_INS_QVFRES = 900 , PPC_INS_QVFRIM = 901 , PPC_INS_QVFRIN = 902 , PPC_INS_QVFRIP = 903 , PPC_INS_QVFRIZ = 904 , PPC_INS_QVFRSP = 905 , PPC_INS_QVFRSQRTE = 906 , PPC_INS_QVFRSQRTES = 907 , PPC_INS_QVFSEL = 908 , PPC_INS_QVFSET = 909 , PPC_INS_QVFSUB = 910 , PPC_INS_QVFSUBS = 911 , PPC_INS_QVFTSTNAN = 912 , PPC_INS_QVFXMADD = 913 , PPC_INS_QVFXMADDS = 914 , PPC_INS_QVFXMUL = 915 , PPC_INS_QVFXMULS = 916 , PPC_INS_QVFXOR = 917 , PPC_INS_QVFXXCPNMADD = 918 , PPC_INS_QVFXXCPNMADDS = 919 , PPC_INS_QVFXXMADD = 920 , PPC_INS_QVFXXMADDS = 921 , PPC_INS_QVFXXNPMADD = 922 , PPC_INS_QVFXXNPMADDS = 923 , PPC_INS_QVGPCI = 924 , PPC_INS_QVLFCDUX = 925 , PPC_INS_QVLFCDUXA = 926 , PPC_INS_QVLFCDX = 927 , PPC_INS_QVLFCDXA = 928 , PPC_INS_QVLFCSUX = 929 , PPC_INS_QVLFCSUXA = 930 , PPC_INS_QVLFCSX = 931 , PPC_INS_QVLFCSXA = 932 , PPC_INS_QVLFDUX = 933 , PPC_INS_QVLFDUXA = 934 , PPC_INS_QVLFDX = 935 , PPC_INS_QVLFDXA = 936 , PPC_INS_QVLFIWAX = 937 , PPC_INS_QVLFIWAXA = 938 , PPC_INS_QVLFIWZX = 939 , PPC_INS_QVLFIWZXA = 940 , PPC_INS_QVLFSUX = 941 , PPC_INS_QVLFSUXA = 942 , PPC_INS_QVLFSX = 943 , PPC_INS_QVLFSXA = 944 , PPC_INS_QVLPCLDX = 945 , PPC_INS_QVLPCLSX = 946 , PPC_INS_QVLPCRDX = 947 , PPC_INS_QVLPCRSX = 948 , PPC_INS_QVSTFCDUX = 949 , PPC_INS_QVSTFCDUXA = 950 , PPC_INS_QVSTFCDUXI = 951 , PPC_INS_QVSTFCDUXIA = 952 , PPC_INS_QVSTFCDX = 953 , PPC_INS_QVSTFCDXA = 954 , PPC_INS_QVSTFCDXI = 955 , PPC_INS_QVSTFCDXIA = 956 , PPC_INS_QVSTFCSUX = 957 , PPC_INS_QVSTFCSUXA = 958 , PPC_INS_QVSTFCSUXI = 959 , PPC_INS_QVSTFCSUXIA = 960 , PPC_INS_QVSTFCSX = 961 , PPC_INS_QVSTFCSXA = 962 , PPC_INS_QVSTFCSXI = 963 , PPC_INS_QVSTFCSXIA = 964 , PPC_INS_QVSTFDUX = 965 , PPC_INS_QVSTFDUXA = 966 , PPC_INS_QVSTFDUXI = 967 , PPC_INS_QVSTFDUXIA = 968 , PPC_INS_QVSTFDX = 969 , PPC_INS_QVSTFDXA = 970 , PPC_INS_QVSTFDXI = 971 , PPC_INS_QVSTFDXIA = 972 , PPC_INS_QVSTFIWX = 973 , PPC_INS_QVSTFIWXA = 974 , PPC_INS_QVSTFSUX = 975 , PPC_INS_QVSTFSUXA = 976 , PPC_INS_QVSTFSUXI = 977 , PPC_INS_QVSTFSUXIA = 978 , PPC_INS_QVSTFSX = 979 , PPC_INS_QVSTFSXA = 980 , PPC_INS_QVSTFSXI = 981 , PPC_INS_QVSTFSXIA = 982 , PPC_INS_RFCI = 983 , PPC_INS_RFDI = 984 , PPC_INS_RFEBB = 985 , PPC_INS_RFI = 986 , PPC_INS_RFID = 987 , PPC_INS_RFMCI = 988 , PPC_INS_RLDCL = 989 , PPC_INS_RLDCR = 990 , PPC_INS_RLDIC = 991 , PPC_INS_RLDICL = 992 , PPC_INS_RLDICR = 993 , PPC_INS_RLDIMI = 994 , PPC_INS_RLWIMI = 995 , PPC_INS_RLWINM = 996 , PPC_INS_RLWNM = 997 , PPC_INS_ROTLD = 998 , PPC_INS_ROTLDI = 999 , PPC_INS_ROTLW = 1000 , PPC_INS_ROTLWI = 1001 , PPC_INS_ROTRDI = 1002 , PPC_INS_ROTRWI = 1003 , PPC_INS_SC = 1004 , PPC_INS_SETB = 1005 , PPC_INS_SLBIA = 1006 , PPC_INS_SLBIE = 1007 , PPC_INS_SLBIEG = 1008 , PPC_INS_SLBMFEE = 1009 , PPC_INS_SLBMFEV = 1010 , PPC_INS_SLBMTE = 1011 , PPC_INS_SLBSYNC = 1012 , PPC_INS_SLD = 1013 , PPC_INS_SLDI = 1014 , PPC_INS_SLW = 1015 , PPC_INS_SLWI = 1016 , PPC_INS_SRAD = 1017 , PPC_INS_SRADI = 1018 , PPC_INS_SRAW = 1019 , PPC_INS_SRAWI = 1020 , PPC_INS_SRD = 1021 , PPC_INS_SRDI = 1022 , PPC_INS_SRW = 1023 , PPC_INS_SRWI = 1024 , PPC_INS_STB = 1025 , PPC_INS_STBCIX = 1026 , PPC_INS_STBCX = 1027 , PPC_INS_STBEPX = 1028 , PPC_INS_STBU = 1029 , PPC_INS_STBUX = 1030 , PPC_INS_STBX = 1031 , PPC_INS_STD = 1032 , PPC_INS_STDAT = 1033 , PPC_INS_STDBRX = 1034 , PPC_INS_STDCIX = 1035 , PPC_INS_STDCX = 1036 , PPC_INS_STDU = 1037 , PPC_INS_STDUX = 1038 , PPC_INS_STDX = 1039 , PPC_INS_STFD = 1040 , PPC_INS_STFDEPX = 1041 , PPC_INS_STFDU = 1042 , PPC_INS_STFDUX = 1043 , PPC_INS_STFDX = 1044 , PPC_INS_STFIWX = 1045 , PPC_INS_STFS = 1046 , PPC_INS_STFSU = 1047 , PPC_INS_STFSUX = 1048 , PPC_INS_STFSX = 1049 , PPC_INS_STH = 1050 , PPC_INS_STHBRX = 1051 , PPC_INS_STHCIX = 1052 , PPC_INS_STHCX = 1053 , PPC_INS_STHEPX = 1054 , PPC_INS_STHU = 1055 , PPC_INS_STHUX = 1056 , PPC_INS_STHX = 1057 , PPC_INS_STMW = 1058 , PPC_INS_STOP = 1059 , PPC_INS_STSWI = 1060 , PPC_INS_STVEBX = 1061 , PPC_INS_STVEHX = 1062 , PPC_INS_STVEWX = 1063 , PPC_INS_STVX = 1064 , PPC_INS_STVXL = 1065 , PPC_INS_STW = 1066 , PPC_INS_STWAT = 1067 , PPC_INS_STWBRX = 1068 , PPC_INS_STWCIX = 1069 , PPC_INS_STWCX = 1070 , PPC_INS_STWEPX = 1071 , PPC_INS_STWU = 1072 , PPC_INS_STWUX = 1073 , PPC_INS_STWX = 1074 , PPC_INS_STXSD = 1075 , PPC_INS_STXSDX = 1076 , PPC_INS_STXSIBX = 1077 , PPC_INS_STXSIHX = 1078 , PPC_INS_STXSIWX = 1079 , PPC_INS_STXSSP = 1080 , PPC_INS_STXSSPX = 1081 , PPC_INS_STXV = 1082 , PPC_INS_STXVB16X = 1083 , PPC_INS_STXVD2X = 1084 , PPC_INS_STXVH8X = 1085 , PPC_INS_STXVL = 1086 , PPC_INS_STXVLL = 1087 , PPC_INS_STXVW4X = 1088 , PPC_INS_STXVX = 1089 , PPC_INS_SUB = 1090 , PPC_INS_SUBC = 1091 , PPC_INS_SUBF = 1092 , PPC_INS_SUBFC = 1093 , PPC_INS_SUBFE = 1094 , PPC_INS_SUBFIC = 1095 , PPC_INS_SUBFME = 1096 , PPC_INS_SUBFZE = 1097 , PPC_INS_SUBI = 1098 , PPC_INS_SUBIC = 1099 , PPC_INS_SUBIS = 1100 , PPC_INS_SUBPCIS = 1101 , PPC_INS_SYNC = 1102 , PPC_INS_TABORT = 1103 , PPC_INS_TABORTDC = 1104 , PPC_INS_TABORTDCI = 1105 , PPC_INS_TABORTWC = 1106 , PPC_INS_TABORTWCI = 1107 , PPC_INS_TBEGIN = 1108 , PPC_INS_TCHECK = 1109 , PPC_INS_TD = 1110 , PPC_INS_TDEQ = 1111 , PPC_INS_TDEQI = 1112 , PPC_INS_TDGE = 1113 , PPC_INS_TDGEI = 1114 , PPC_INS_TDGT = 1115 , PPC_INS_TDGTI = 1116 , PPC_INS_TDI = 1117 , PPC_INS_TDLE = 1118 , PPC_INS_TDLEI = 1119 , PPC_INS_TDLGE = 1120 , PPC_INS_TDLGEI = 1121 , PPC_INS_TDLGT = 1122 , PPC_INS_TDLGTI = 1123 , PPC_INS_TDLLE = 1124 , PPC_INS_TDLLEI = 1125 , PPC_INS_TDLLT = 1126 , PPC_INS_TDLLTI = 1127 , PPC_INS_TDLNG = 1128 , PPC_INS_TDLNGI = 1129 , PPC_INS_TDLNL = 1130 , PPC_INS_TDLNLI = 1131 , PPC_INS_TDLT = 1132 , PPC_INS_TDLTI = 1133 , PPC_INS_TDNE = 1134 , PPC_INS_TDNEI = 1135 , PPC_INS_TDNG = 1136 , PPC_INS_TDNGI = 1137 , PPC_INS_TDNL = 1138 , PPC_INS_TDNLI = 1139 , PPC_INS_TDU = 1140 , PPC_INS_TDUI = 1141 , PPC_INS_TEND = 1142 , PPC_INS_TLBIA = 1143 , PPC_INS_TLBIE = 1144 , PPC_INS_TLBIEL = 1145 , PPC_INS_TLBIVAX = 1146 , PPC_INS_TLBLD = 1147 , PPC_INS_TLBLI = 1148 , PPC_INS_TLBRE = 1149 , PPC_INS_TLBREHI = 1150 , PPC_INS_TLBRELO = 1151 , PPC_INS_TLBSX = 1152 , PPC_INS_TLBSYNC = 1153 , PPC_INS_TLBWE = 1154 , PPC_INS_TLBWEHI = 1155 , PPC_INS_TLBWELO = 1156 , PPC_INS_TRAP = 1157 , PPC_INS_TRECHKPT = 1158 , PPC_INS_TRECLAIM = 1159 , PPC_INS_TSR = 1160 , PPC_INS_TW = 1161 , PPC_INS_TWEQ = 1162 , PPC_INS_TWEQI = 1163 , PPC_INS_TWGE = 1164 , PPC_INS_TWGEI = 1165 , PPC_INS_TWGT = 1166 , PPC_INS_TWGTI = 1167 , PPC_INS_TWI = 1168 , PPC_INS_TWLE = 1169 , PPC_INS_TWLEI = 1170 , PPC_INS_TWLGE = 1171 , PPC_INS_TWLGEI = 1172 , PPC_INS_TWLGT = 1173 , PPC_INS_TWLGTI = 1174 , PPC_INS_TWLLE = 1175 , PPC_INS_TWLLEI = 1176 , PPC_INS_TWLLT = 1177 , PPC_INS_TWLLTI = 1178 , PPC_INS_TWLNG = 1179 , PPC_INS_TWLNGI = 1180 , PPC_INS_TWLNL = 1181 , PPC_INS_TWLNLI = 1182 , PPC_INS_TWLT = 1183 , PPC_INS_TWLTI = 1184 , PPC_INS_TWNE = 1185 , PPC_INS_TWNEI = 1186 , PPC_INS_TWNG = 1187 , PPC_INS_TWNGI = 1188 , PPC_INS_TWNL = 1189 , PPC_INS_TWNLI = 1190 , PPC_INS_TWU = 1191 , PPC_INS_TWUI = 1192 , PPC_INS_VABSDUB = 1193 , PPC_INS_VABSDUH = 1194 , PPC_INS_VABSDUW = 1195 , PPC_INS_VADDCUQ = 1196 , PPC_INS_VADDCUW = 1197 , PPC_INS_VADDECUQ = 1198 , PPC_INS_VADDEUQM = 1199 , PPC_INS_VADDFP = 1200 , PPC_INS_VADDSBS = 1201 , PPC_INS_VADDSHS = 1202 , PPC_INS_VADDSWS = 1203 , PPC_INS_VADDUBM = 1204 , PPC_INS_VADDUBS = 1205 , PPC_INS_VADDUDM = 1206 , PPC_INS_VADDUHM = 1207 , PPC_INS_VADDUHS = 1208 , PPC_INS_VADDUQM = 1209 , PPC_INS_VADDUWM = 1210 , PPC_INS_VADDUWS = 1211 , PPC_INS_VAND = 1212 , PPC_INS_VANDC = 1213 , PPC_INS_VAVGSB = 1214 , PPC_INS_VAVGSH = 1215 , PPC_INS_VAVGSW = 1216 , PPC_INS_VAVGUB = 1217 , PPC_INS_VAVGUH = 1218 , PPC_INS_VAVGUW = 1219 , PPC_INS_VBPERMD = 1220 , PPC_INS_VBPERMQ = 1221 , PPC_INS_VCFSX = 1222 , PPC_INS_VCFUX = 1223 , PPC_INS_VCIPHER = 1224 , PPC_INS_VCIPHERLAST = 1225 , PPC_INS_VCLZB = 1226 , PPC_INS_VCLZD = 1227 , PPC_INS_VCLZH = 1228 , PPC_INS_VCLZLSBB = 1229 , PPC_INS_VCLZW = 1230 , PPC_INS_VCMPBFP = 1231 , PPC_INS_VCMPEQFP = 1232 , PPC_INS_VCMPEQUB = 1233 , PPC_INS_VCMPEQUD = 1234 , PPC_INS_VCMPEQUH = 1235 , PPC_INS_VCMPEQUW = 1236 , PPC_INS_VCMPGEFP = 1237 , PPC_INS_VCMPGTFP = 1238 , PPC_INS_VCMPGTSB = 1239 , PPC_INS_VCMPGTSD = 1240 , PPC_INS_VCMPGTSH = 1241 , PPC_INS_VCMPGTSW = 1242 , PPC_INS_VCMPGTUB = 1243 , PPC_INS_VCMPGTUD = 1244 , PPC_INS_VCMPGTUH = 1245 , PPC_INS_VCMPGTUW = 1246 , PPC_INS_VCMPNEB = 1247 , PPC_INS_VCMPNEH = 1248 , PPC_INS_VCMPNEW = 1249 , PPC_INS_VCMPNEZB = 1250 , PPC_INS_VCMPNEZH = 1251 , PPC_INS_VCMPNEZW = 1252 , PPC_INS_VCTSXS = 1253 , PPC_INS_VCTUXS = 1254 , PPC_INS_VCTZB = 1255 , PPC_INS_VCTZD = 1256 , PPC_INS_VCTZH = 1257 , PPC_INS_VCTZLSBB = 1258 , PPC_INS_VCTZW = 1259 , PPC_INS_VEQV = 1260 , PPC_INS_VEXPTEFP = 1261 , PPC_INS_VEXTRACTD = 1262 , PPC_INS_VEXTRACTUB = 1263 , PPC_INS_VEXTRACTUH = 1264 , PPC_INS_VEXTRACTUW = 1265 , PPC_INS_VEXTSB2D = 1266 , PPC_INS_VEXTSB2W = 1267 , PPC_INS_VEXTSH2D = 1268 , PPC_INS_VEXTSH2W = 1269 , PPC_INS_VEXTSW2D = 1270 , PPC_INS_VEXTUBLX = 1271 , PPC_INS_VEXTUBRX = 1272 , PPC_INS_VEXTUHLX = 1273 , PPC_INS_VEXTUHRX = 1274 , PPC_INS_VEXTUWLX = 1275 , PPC_INS_VEXTUWRX = 1276 , PPC_INS_VGBBD = 1277 , PPC_INS_VINSERTB = 1278 , PPC_INS_VINSERTD = 1279 , PPC_INS_VINSERTH = 1280 , PPC_INS_VINSERTW = 1281 , PPC_INS_VLOGEFP = 1282 , PPC_INS_VMADDFP = 1283 , PPC_INS_VMAXFP = 1284 , PPC_INS_VMAXSB = 1285 , PPC_INS_VMAXSD = 1286 , PPC_INS_VMAXSH = 1287 , PPC_INS_VMAXSW = 1288 , PPC_INS_VMAXUB = 1289 , PPC_INS_VMAXUD = 1290 , PPC_INS_VMAXUH = 1291 , PPC_INS_VMAXUW = 1292 , PPC_INS_VMHADDSHS = 1293 , PPC_INS_VMHRADDSHS = 1294 , PPC_INS_VMINFP = 1295 , PPC_INS_VMINSB = 1296 , PPC_INS_VMINSD = 1297 , PPC_INS_VMINSH = 1298 , PPC_INS_VMINSW = 1299 , PPC_INS_VMINUB = 1300 , PPC_INS_VMINUD = 1301 , PPC_INS_VMINUH = 1302 , PPC_INS_VMINUW = 1303 , PPC_INS_VMLADDUHM = 1304 , PPC_INS_VMR = 1305 , PPC_INS_VMRGEW = 1306 , PPC_INS_VMRGHB = 1307 , PPC_INS_VMRGHH = 1308 , PPC_INS_VMRGHW = 1309 , PPC_INS_VMRGLB = 1310 , PPC_INS_VMRGLH = 1311 , PPC_INS_VMRGLW = 1312 , PPC_INS_VMRGOW = 1313 , PPC_INS_VMSUMMBM = 1314 , PPC_INS_VMSUMSHM = 1315 , PPC_INS_VMSUMSHS = 1316 , PPC_INS_VMSUMUBM = 1317 , PPC_INS_VMSUMUHM = 1318 , PPC_INS_VMSUMUHS = 1319 , PPC_INS_VMUL10CUQ = 1320 , PPC_INS_VMUL10ECUQ = 1321 , PPC_INS_VMUL10EUQ = 1322 , PPC_INS_VMUL10UQ = 1323 , PPC_INS_VMULESB = 1324 , PPC_INS_VMULESH = 1325 , PPC_INS_VMULESW = 1326 , PPC_INS_VMULEUB = 1327 , PPC_INS_VMULEUH = 1328 , PPC_INS_VMULEUW = 1329 , PPC_INS_VMULOSB = 1330 , PPC_INS_VMULOSH = 1331 , PPC_INS_VMULOSW = 1332 , PPC_INS_VMULOUB = 1333 , PPC_INS_VMULOUH = 1334 , PPC_INS_VMULOUW = 1335 , PPC_INS_VMULUWM = 1336 , PPC_INS_VNAND = 1337 , PPC_INS_VNCIPHER = 1338 , PPC_INS_VNCIPHERLAST = 1339 , PPC_INS_VNEGD = 1340 , PPC_INS_VNEGW = 1341 , PPC_INS_VNMSUBFP = 1342 , PPC_INS_VNOR = 1343 , PPC_INS_VNOT = 1344 , PPC_INS_VOR = 1345 , PPC_INS_VORC = 1346 , PPC_INS_VPERM = 1347 , PPC_INS_VPERMR = 1348 , PPC_INS_VPERMXOR = 1349 , PPC_INS_VPKPX = 1350 , PPC_INS_VPKSDSS = 1351 , PPC_INS_VPKSDUS = 1352 , PPC_INS_VPKSHSS = 1353 , PPC_INS_VPKSHUS = 1354 , PPC_INS_VPKSWSS = 1355 , PPC_INS_VPKSWUS = 1356 , PPC_INS_VPKUDUM = 1357 , PPC_INS_VPKUDUS = 1358 , PPC_INS_VPKUHUM = 1359 , PPC_INS_VPKUHUS = 1360 , PPC_INS_VPKUWUM = 1361 , PPC_INS_VPKUWUS = 1362 , PPC_INS_VPMSUMB = 1363 , PPC_INS_VPMSUMD = 1364 , PPC_INS_VPMSUMH = 1365 , PPC_INS_VPMSUMW = 1366 , PPC_INS_VPOPCNTB = 1367 , PPC_INS_VPOPCNTD = 1368 , PPC_INS_VPOPCNTH = 1369 , PPC_INS_VPOPCNTW = 1370 , PPC_INS_VPRTYBD = 1371 , PPC_INS_VPRTYBQ = 1372 , PPC_INS_VPRTYBW = 1373 , PPC_INS_VREFP = 1374 , PPC_INS_VRFIM = 1375 , PPC_INS_VRFIN = 1376 , PPC_INS_VRFIP = 1377 , PPC_INS_VRFIZ = 1378 , PPC_INS_VRLB = 1379 , PPC_INS_VRLD = 1380 , PPC_INS_VRLDMI = 1381 , PPC_INS_VRLDNM = 1382 , PPC_INS_VRLH = 1383 , PPC_INS_VRLW = 1384 , PPC_INS_VRLWMI = 1385 , PPC_INS_VRLWNM = 1386 , PPC_INS_VRSQRTEFP = 1387 , PPC_INS_VSBOX = 1388 , PPC_INS_VSEL = 1389 , PPC_INS_VSHASIGMAD = 1390 , PPC_INS_VSHASIGMAW = 1391 , PPC_INS_VSL = 1392 , PPC_INS_VSLB = 1393 , PPC_INS_VSLD = 1394 , PPC_INS_VSLDOI = 1395 , PPC_INS_VSLH = 1396 , PPC_INS_VSLO = 1397 , PPC_INS_VSLV = 1398 , PPC_INS_VSLW = 1399 , PPC_INS_VSPLTB = 1400 , PPC_INS_VSPLTH = 1401 , PPC_INS_VSPLTISB = 1402 , PPC_INS_VSPLTISH = 1403 , PPC_INS_VSPLTISW = 1404 , PPC_INS_VSPLTW = 1405 , PPC_INS_VSR = 1406 , PPC_INS_VSRAB = 1407 , PPC_INS_VSRAD = 1408 , PPC_INS_VSRAH = 1409 , PPC_INS_VSRAW = 1410 , PPC_INS_VSRB = 1411 , PPC_INS_VSRD = 1412 , PPC_INS_VSRH = 1413 , PPC_INS_VSRO = 1414 , PPC_INS_VSRV = 1415 , PPC_INS_VSRW = 1416 , PPC_INS_VSUBCUQ = 1417 , PPC_INS_VSUBCUW = 1418 , PPC_INS_VSUBECUQ = 1419 , PPC_INS_VSUBEUQM = 1420 , PPC_INS_VSUBFP = 1421 , PPC_INS_VSUBSBS = 1422 , PPC_INS_VSUBSHS = 1423 , PPC_INS_VSUBSWS = 1424 , PPC_INS_VSUBUBM = 1425 , PPC_INS_VSUBUBS = 1426 , PPC_INS_VSUBUDM = 1427 , PPC_INS_VSUBUHM = 1428 , PPC_INS_VSUBUHS = 1429 , PPC_INS_VSUBUQM = 1430 , PPC_INS_VSUBUWM = 1431 , PPC_INS_VSUBUWS = 1432 , PPC_INS_VSUM2SWS = 1433 , PPC_INS_VSUM4SBS = 1434 , PPC_INS_VSUM4SHS = 1435 , PPC_INS_VSUM4UBS = 1436 , PPC_INS_VSUMSWS = 1437 , PPC_INS_VUPKHPX = 1438 , PPC_INS_VUPKHSB = 1439 , PPC_INS_VUPKHSH = 1440 , PPC_INS_VUPKHSW = 1441 , PPC_INS_VUPKLPX = 1442 , PPC_INS_VUPKLSB = 1443 , PPC_INS_VUPKLSH = 1444 , PPC_INS_VUPKLSW = 1445 , PPC_INS_VXOR = 1446 , PPC_INS_WAIT = 1447 , PPC_INS_WAITIMPL = 1448 , PPC_INS_WAITRSV = 1449 , PPC_INS_WRTEE = 1450 , PPC_INS_WRTEEI = 1451 , PPC_INS_XNOP = 1452 , PPC_INS_XOR = 1453 , PPC_INS_XORI = 1454 , PPC_INS_XORIS = 1455 , PPC_INS_XSABSDP = 1456 , PPC_INS_XSABSQP = 1457 , PPC_INS_XSADDDP = 1458 , PPC_INS_XSADDQP = 1459 , PPC_INS_XSADDQPO = 1460 , PPC_INS_XSADDSP = 1461 , PPC_INS_XSCMPEQDP = 1462 , PPC_INS_XSCMPEXPDP = 1463 , PPC_INS_XSCMPEXPQP = 1464 , PPC_INS_XSCMPGEDP = 1465 , PPC_INS_XSCMPGTDP = 1466 , PPC_INS_XSCMPODP = 1467 , PPC_INS_XSCMPOQP = 1468 , PPC_INS_XSCMPUDP = 1469 , PPC_INS_XSCMPUQP = 1470 , PPC_INS_XSCPSGNDP = 1471 , PPC_INS_XSCPSGNQP = 1472 , PPC_INS_XSCVDPHP = 1473 , PPC_INS_XSCVDPQP = 1474 , PPC_INS_XSCVDPSP = 1475 , PPC_INS_XSCVDPSPN = 1476 , PPC_INS_XSCVDPSXDS = 1477 , PPC_INS_XSCVDPSXWS = 1478 , PPC_INS_XSCVDPUXDS = 1479 , PPC_INS_XSCVDPUXWS = 1480 , PPC_INS_XSCVHPDP = 1481 , PPC_INS_XSCVQPDP = 1482 , PPC_INS_XSCVQPDPO = 1483 , PPC_INS_XSCVQPSDZ = 1484 , PPC_INS_XSCVQPSWZ = 1485 , PPC_INS_XSCVQPUDZ = 1486 , PPC_INS_XSCVQPUWZ = 1487 , PPC_INS_XSCVSDQP = 1488 , PPC_INS_XSCVSPDP = 1489 , PPC_INS_XSCVSPDPN = 1490 , PPC_INS_XSCVSXDDP = 1491 , PPC_INS_XSCVSXDSP = 1492 , PPC_INS_XSCVUDQP = 1493 , PPC_INS_XSCVUXDDP = 1494 , PPC_INS_XSCVUXDSP = 1495 , PPC_INS_XSDIVDP = 1496 , PPC_INS_XSDIVQP = 1497 , PPC_INS_XSDIVQPO = 1498 , PPC_INS_XSDIVSP = 1499 , PPC_INS_XSIEXPDP = 1500 , PPC_INS_XSIEXPQP = 1501 , PPC_INS_XSMADDADP = 1502 , PPC_INS_XSMADDASP = 1503 , PPC_INS_XSMADDMDP = 1504 , PPC_INS_XSMADDMSP = 1505 , PPC_INS_XSMADDQP = 1506 , PPC_INS_XSMADDQPO = 1507 , PPC_INS_XSMAXCDP = 1508 , PPC_INS_XSMAXDP = 1509 , PPC_INS_XSMAXJDP = 1510 , PPC_INS_XSMINCDP = 1511 , PPC_INS_XSMINDP = 1512 , PPC_INS_XSMINJDP = 1513 , PPC_INS_XSMSUBADP = 1514 , PPC_INS_XSMSUBASP = 1515 , PPC_INS_XSMSUBMDP = 1516 , PPC_INS_XSMSUBMSP = 1517 , PPC_INS_XSMSUBQP = 1518 , PPC_INS_XSMSUBQPO = 1519 , PPC_INS_XSMULDP = 1520 , PPC_INS_XSMULQP = 1521 , PPC_INS_XSMULQPO = 1522 , PPC_INS_XSMULSP = 1523 , PPC_INS_XSNABSDP = 1524 , PPC_INS_XSNABSQP = 1525 , PPC_INS_XSNEGDP = 1526 , PPC_INS_XSNEGQP = 1527 , PPC_INS_XSNMADDADP = 1528 , PPC_INS_XSNMADDASP = 1529 , PPC_INS_XSNMADDMDP = 1530 , PPC_INS_XSNMADDMSP = 1531 , PPC_INS_XSNMADDQP = 1532 , PPC_INS_XSNMADDQPO = 1533 , PPC_INS_XSNMSUBADP = 1534 , PPC_INS_XSNMSUBASP = 1535 , PPC_INS_XSNMSUBMDP = 1536 , PPC_INS_XSNMSUBMSP = 1537 , PPC_INS_XSNMSUBQP = 1538 , PPC_INS_XSNMSUBQPO = 1539 , PPC_INS_XSRDPI = 1540 , PPC_INS_XSRDPIC = 1541 , PPC_INS_XSRDPIM = 1542 , PPC_INS_XSRDPIP = 1543 , PPC_INS_XSRDPIZ = 1544 , PPC_INS_XSREDP = 1545 , PPC_INS_XSRESP = 1546 , PPC_INS_XSRQPI = 1547 , PPC_INS_XSRQPIX = 1548 , PPC_INS_XSRQPXP = 1549 , PPC_INS_XSRSP = 1550 , PPC_INS_XSRSQRTEDP = 1551 , PPC_INS_XSRSQRTESP = 1552 , PPC_INS_XSSQRTDP = 1553 , PPC_INS_XSSQRTQP = 1554 , PPC_INS_XSSQRTQPO = 1555 , PPC_INS_XSSQRTSP = 1556 , PPC_INS_XSSUBDP = 1557 , PPC_INS_XSSUBQP = 1558 , PPC_INS_XSSUBQPO = 1559 , PPC_INS_XSSUBSP = 1560 , PPC_INS_XSTDIVDP = 1561 , PPC_INS_XSTSQRTDP = 1562 , PPC_INS_XSTSTDCDP = 1563 , PPC_INS_XSTSTDCQP = 1564 , PPC_INS_XSTSTDCSP = 1565 , PPC_INS_XSXEXPDP = 1566 , PPC_INS_XSXEXPQP = 1567 , PPC_INS_XSXSIGDP = 1568 , PPC_INS_XSXSIGQP = 1569 , PPC_INS_XVABSDP = 1570 , PPC_INS_XVABSSP = 1571 , PPC_INS_XVADDDP = 1572 , PPC_INS_XVADDSP = 1573 , PPC_INS_XVCMPEQDP = 1574 , PPC_INS_XVCMPEQSP = 1575 , PPC_INS_XVCMPGEDP = 1576 , PPC_INS_XVCMPGESP = 1577 , PPC_INS_XVCMPGTDP = 1578 , PPC_INS_XVCMPGTSP = 1579 , PPC_INS_XVCPSGNDP = 1580 , PPC_INS_XVCPSGNSP = 1581 , PPC_INS_XVCVDPSP = 1582 , PPC_INS_XVCVDPSXDS = 1583 , PPC_INS_XVCVDPSXWS = 1584 , PPC_INS_XVCVDPUXDS = 1585 , PPC_INS_XVCVDPUXWS = 1586 , PPC_INS_XVCVHPSP = 1587 , PPC_INS_XVCVSPDP = 1588 , PPC_INS_XVCVSPHP = 1589 , PPC_INS_XVCVSPSXDS = 1590 , PPC_INS_XVCVSPSXWS = 1591 , PPC_INS_XVCVSPUXDS = 1592 , PPC_INS_XVCVSPUXWS = 1593 , PPC_INS_XVCVSXDDP = 1594 , PPC_INS_XVCVSXDSP = 1595 , PPC_INS_XVCVSXWDP = 1596 , PPC_INS_XVCVSXWSP = 1597 , PPC_INS_XVCVUXDDP = 1598 , PPC_INS_XVCVUXDSP = 1599 , PPC_INS_XVCVUXWDP = 1600 , PPC_INS_XVCVUXWSP = 1601 , PPC_INS_XVDIVDP = 1602 , PPC_INS_XVDIVSP = 1603 , PPC_INS_XVIEXPDP = 1604 , PPC_INS_XVIEXPSP = 1605 , PPC_INS_XVMADDADP = 1606 , PPC_INS_XVMADDASP = 1607 , PPC_INS_XVMADDMDP = 1608 , PPC_INS_XVMADDMSP = 1609 , PPC_INS_XVMAXDP = 1610 , PPC_INS_XVMAXSP = 1611 , PPC_INS_XVMINDP = 1612 , PPC_INS_XVMINSP = 1613 , PPC_INS_XVMOVDP = 1614 , PPC_INS_XVMOVSP = 1615 , PPC_INS_XVMSUBADP = 1616 , PPC_INS_XVMSUBASP = 1617 , PPC_INS_XVMSUBMDP = 1618 , PPC_INS_XVMSUBMSP = 1619 , PPC_INS_XVMULDP = 1620 , PPC_INS_XVMULSP = 1621 , PPC_INS_XVNABSDP = 1622 , PPC_INS_XVNABSSP = 1623 , PPC_INS_XVNEGDP = 1624 , PPC_INS_XVNEGSP = 1625 , PPC_INS_XVNMADDADP = 1626 , PPC_INS_XVNMADDASP = 1627 , PPC_INS_XVNMADDMDP = 1628 , PPC_INS_XVNMADDMSP = 1629 , PPC_INS_XVNMSUBADP = 1630 , PPC_INS_XVNMSUBASP = 1631 , PPC_INS_XVNMSUBMDP = 1632 , PPC_INS_XVNMSUBMSP = 1633 , PPC_INS_XVRDPI = 1634 , PPC_INS_XVRDPIC = 1635 , PPC_INS_XVRDPIM = 1636 , PPC_INS_XVRDPIP = 1637 , PPC_INS_XVRDPIZ = 1638 , PPC_INS_XVREDP = 1639 , PPC_INS_XVRESP = 1640 , PPC_INS_XVRSPI = 1641 , PPC_INS_XVRSPIC = 1642 , PPC_INS_XVRSPIM = 1643 , PPC_INS_XVRSPIP = 1644 , PPC_INS_XVRSPIZ = 1645 , PPC_INS_XVRSQRTEDP = 1646 , PPC_INS_XVRSQRTESP = 1647 , PPC_INS_XVSQRTDP = 1648 , PPC_INS_XVSQRTSP = 1649 , PPC_INS_XVSUBDP = 1650 , PPC_INS_XVSUBSP = 1651 , PPC_INS_XVTDIVDP = 1652 , PPC_INS_XVTDIVSP = 1653 , PPC_INS_XVTSQRTDP = 1654 , PPC_INS_XVTSQRTSP = 1655 , PPC_INS_XVTSTDCDP = 1656 , PPC_INS_XVTSTDCSP = 1657 , PPC_INS_XVXEXPDP = 1658 , PPC_INS_XVXEXPSP = 1659 , PPC_INS_XVXSIGDP = 1660 , PPC_INS_XVXSIGSP = 1661 , PPC_INS_XXBRD = 1662 , PPC_INS_XXBRH = 1663 , PPC_INS_XXBRQ = 1664 , PPC_INS_XXBRW = 1665 , PPC_INS_XXEXTRACTUW = 1666 , PPC_INS_XXINSERTW = 1667 , PPC_INS_XXLAND = 1668 , PPC_INS_XXLANDC = 1669 , PPC_INS_XXLEQV = 1670 , PPC_INS_XXLNAND = 1671 , PPC_INS_XXLNOR = 1672 , PPC_INS_XXLOR = 1673 , PPC_INS_XXLORC = 1674 , PPC_INS_XXLXOR = 1675 , PPC_INS_XXMRGHD = 1676 , PPC_INS_XXMRGHW = 1677 , PPC_INS_XXMRGLD = 1678 , PPC_INS_XXMRGLW = 1679 , PPC_INS_XXPERM = 1680 , PPC_INS_XXPERMDI = 1681 , PPC_INS_XXPERMR = 1682 , PPC_INS_XXSEL = 1683 , PPC_INS_XXSLDWI = 1684 , PPC_INS_XXSPLTD = 1685 , PPC_INS_XXSPLTIB = 1686 , PPC_INS_XXSPLTW = 1687 , PPC_INS_XXSWAPD = 1688 , PPC_INS_DCBZ_L = 1689 , PPC_INS_PSQ_L = 1690 , PPC_INS_PSQ_LU = 1691 , PPC_INS_PSQ_LUX = 1692 , PPC_INS_PSQ_LX = 1693 , PPC_INS_PSQ_ST = 1694 , PPC_INS_PSQ_STU = 1695 , PPC_INS_PSQ_STUX = 1696 , PPC_INS_PSQ_STX = 1697 , PPC_INS_PS_ABS = 1698 , PPC_INS_PS_ADD = 1699 , PPC_INS_PS_CMPO0 = 1700 , PPC_INS_PS_CMPO1 = 1701 , PPC_INS_PS_CMPU0 = 1702 , PPC_INS_PS_CMPU1 = 1703 , PPC_INS_PS_DIV = 1704 , PPC_INS_PS_MADD = 1705 , PPC_INS_PS_MADDS0 = 1706 , PPC_INS_PS_MADDS1 = 1707 , PPC_INS_PS_MERGE00 = 1708 , PPC_INS_PS_MERGE01 = 1709 , PPC_INS_PS_MERGE10 = 1710 , PPC_INS_PS_MERGE11 = 1711 , PPC_INS_PS_MR = 1712 , PPC_INS_PS_MSUB = 1713 , PPC_INS_PS_MUL = 1714 , PPC_INS_PS_MULS0 = 1715 , PPC_INS_PS_MULS1 = 1716 , PPC_INS_PS_NABS = 1717 , PPC_INS_PS_NEG = 1718 , PPC_INS_PS_NMADD = 1719 , PPC_INS_PS_NMSUB = 1720 , PPC_INS_PS_RES = 1721 , PPC_INS_PS_RSQRTE = 1722 , PPC_INS_PS_SEL = 1723 , PPC_INS_PS_SUB = 1724 , PPC_INS_PS_SUM0 = 1725 , PPC_INS_PS_SUM1 = 1726 , PPC_INS_ENDING = 1727 , } # [repr (u32)] # [doc = " Group of PPC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum ppc_insn_group { # [doc = "< = CS_GRP_INVALID"] PPC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] PPC_GRP_JUMP = 1 , PPC_GRP_ALTIVEC = 128 , PPC_GRP_MODE32 = 129 , PPC_GRP_MODE64 = 130 , PPC_GRP_BOOKE = 131 , PPC_GRP_NOTBOOKE = 132 , PPC_GRP_SPE = 133 , PPC_GRP_VSX = 134 , PPC_GRP_E500 = 135 , PPC_GRP_PPC4XX = 136 , PPC_GRP_PPC6XX = 137 , PPC_GRP_ICBT = 138 , PPC_GRP_P8ALTIVEC = 139 , PPC_GRP_P8VECTOR = 140 , PPC_GRP_QPX = 141 , PPC_GRP_PS = 142 , PPC_GRP_ENDING = 143 , } # [repr (u32)] # [doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_cc { # [doc = "< invalid CC (default)"] SPARC_CC_INVALID = 0 , # [doc = "< Always"] SPARC_CC_ICC_A = 264 , # [doc = "< Never"] SPARC_CC_ICC_N = 256 , # [doc = "< Not Equal"] SPARC_CC_ICC_NE = 265 , # [doc = "< Equal"] SPARC_CC_ICC_E = 257 , # [doc = "< Greater"] SPARC_CC_ICC_G = 266 , # [doc = "< Less or Equal"] SPARC_CC_ICC_LE = 258 , # [doc = "< Greater or Equal"] SPARC_CC_ICC_GE = 267 , # [doc = "< Less"] SPARC_CC_ICC_L = 259 , # [doc = "< Greater Unsigned"] SPARC_CC_ICC_GU = 268 , # [doc = "< Less or Equal Unsigned"] SPARC_CC_ICC_LEU = 260 , # [doc = "< Carry Clear/Great or Equal Unsigned"] SPARC_CC_ICC_CC = 269 , # [doc = "< Carry Set/Less Unsigned"] SPARC_CC_ICC_CS = 261 , # [doc = "< Positive"] SPARC_CC_ICC_POS = 270 , # [doc = "< Negative"] SPARC_CC_ICC_NEG = 262 , # [doc = "< Overflow Clear"] SPARC_CC_ICC_VC = 271 , # [doc = "< Overflow Set"] SPARC_CC_ICC_VS = 263 , # [doc = "< Always"] SPARC_CC_FCC_A = 280 , # [doc = "< Never"] SPARC_CC_FCC_N = 272 , # [doc = "< Unordered"] SPARC_CC_FCC_U = 279 , # [doc = "< Greater"] SPARC_CC_FCC_G = 278 , # [doc = "< Unordered or Greater"] SPARC_CC_FCC_UG = 277 , # [doc = "< Less"] SPARC_CC_FCC_L = 276 , # [doc = "< Unordered or Less"] SPARC_CC_FCC_UL = 275 , # [doc = "< Less or Greater"] SPARC_CC_FCC_LG = 274 , # [doc = "< Not Equal"] SPARC_CC_FCC_NE = 273 , # [doc = "< Equal"] SPARC_CC_FCC_E = 281 , # [doc = "< Unordered or Equal"] SPARC_CC_FCC_UE = 282 , # [doc = "< Greater or Equal"] SPARC_CC_FCC_GE = 283 , # [doc = "< Unordered or Greater or Equal"] SPARC_CC_FCC_UGE = 284 , # [doc = "< Less or Equal"] SPARC_CC_FCC_LE = 285 , # [doc = "< Unordered or Less or Equal"] SPARC_CC_FCC_ULE = 286 , # [doc = "< Ordered"] SPARC_CC_FCC_O = 287 , } # [repr (u32)] # [doc = " Branch hint"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_hint { # [doc = "< no hint"] SPARC_HINT_INVALID = 0 , # [doc = "< annul delay slot instruction"] SPARC_HINT_A = 1 , # [doc = "< branch taken"] SPARC_HINT_PT = 2 , # [doc = "< branch NOT taken"] SPARC_HINT_PN = 4 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SPARC_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SPARC_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SPARC_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SPARC_OP_MEM = 3 , } impl sparc_reg { pub const SPARC_REG_O6 : sparc_reg = sparc_reg :: SPARC_REG_SP ; } impl sparc_reg { pub const SPARC_REG_I6 : sparc_reg = sparc_reg :: SPARC_REG_FP ; } # [repr (u32)] # [doc = " SPARC registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_reg { SPARC_REG_INVALID = 0 , SPARC_REG_F0 = 1 , SPARC_REG_F1 = 2 , SPARC_REG_F2 = 3 , SPARC_REG_F3 = 4 , SPARC_REG_F4 = 5 , SPARC_REG_F5 = 6 , SPARC_REG_F6 = 7 , SPARC_REG_F7 = 8 , SPARC_REG_F8 = 9 , SPARC_REG_F9 = 10 , SPARC_REG_F10 = 11 , SPARC_REG_F11 = 12 , SPARC_REG_F12 = 13 , SPARC_REG_F13 = 14 , SPARC_REG_F14 = 15 , SPARC_REG_F15 = 16 , SPARC_REG_F16 = 17 , SPARC_REG_F17 = 18 , SPARC_REG_F18 = 19 , SPARC_REG_F19 = 20 , SPARC_REG_F20 = 21 , SPARC_REG_F21 = 22 , SPARC_REG_F22 = 23 , SPARC_REG_F23 = 24 , SPARC_REG_F24 = 25 , SPARC_REG_F25 = 26 , SPARC_REG_F26 = 27 , SPARC_REG_F27 = 28 , SPARC_REG_F28 = 29 , SPARC_REG_F29 = 30 , SPARC_REG_F30 = 31 , SPARC_REG_F31 = 32 , SPARC_REG_F32 = 33 , SPARC_REG_F34 = 34 , SPARC_REG_F36 = 35 , SPARC_REG_F38 = 36 , SPARC_REG_F40 = 37 , SPARC_REG_F42 = 38 , SPARC_REG_F44 = 39 , SPARC_REG_F46 = 40 , SPARC_REG_F48 = 41 , SPARC_REG_F50 = 42 , SPARC_REG_F52 = 43 , SPARC_REG_F54 = 44 , SPARC_REG_F56 = 45 , SPARC_REG_F58 = 46 , SPARC_REG_F60 = 47 , SPARC_REG_F62 = 48 , SPARC_REG_FCC0 = 49 , SPARC_REG_FCC1 = 50 , SPARC_REG_FCC2 = 51 , SPARC_REG_FCC3 = 52 , SPARC_REG_FP = 53 , SPARC_REG_G0 = 54 , SPARC_REG_G1 = 55 , SPARC_REG_G2 = 56 , SPARC_REG_G3 = 57 , SPARC_REG_G4 = 58 , SPARC_REG_G5 = 59 , SPARC_REG_G6 = 60 , SPARC_REG_G7 = 61 , SPARC_REG_I0 = 62 , SPARC_REG_I1 = 63 , SPARC_REG_I2 = 64 , SPARC_REG_I3 = 65 , SPARC_REG_I4 = 66 , SPARC_REG_I5 = 67 , SPARC_REG_I7 = 68 , SPARC_REG_ICC = 69 , SPARC_REG_L0 = 70 , SPARC_REG_L1 = 71 , SPARC_REG_L2 = 72 , SPARC_REG_L3 = 73 , SPARC_REG_L4 = 74 , SPARC_REG_L5 = 75 , SPARC_REG_L6 = 76 , SPARC_REG_L7 = 77 , SPARC_REG_O0 = 78 , SPARC_REG_O1 = 79 , SPARC_REG_O2 = 80 , SPARC_REG_O3 = 81 , SPARC_REG_O4 = 82 , SPARC_REG_O5 = 83 , SPARC_REG_O7 = 84 , SPARC_REG_SP = 85 , SPARC_REG_Y = 86 , SPARC_REG_XCC = 87 , SPARC_REG_ENDING = 88 , } # [doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sparc_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sparc_op_mem"] [:: std :: mem :: size_of :: < sparc_op_mem > () - 8usize] ; ["Alignment of sparc_op_mem"] [:: std :: mem :: align_of :: < sparc_op_mem > () - 4usize] ; ["Offset of field: sparc_op_mem::base"] [:: std :: mem :: offset_of ! (sparc_op_mem , base) - 0usize] ; ["Offset of field: sparc_op_mem::index"] [:: std :: mem :: offset_of ! (sparc_op_mem , index) - 1usize] ; ["Offset of field: sparc_op_mem::disp"] [:: std :: mem :: offset_of ! (sparc_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc_op { # [doc = "< operand type"] pub type_ : sparc_op_type , pub __bindgen_anon_1 : cs_sparc_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sparc_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sparc_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sparc_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_sparc_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sparc_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sparc_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sparc_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc_op"] [:: std :: mem :: size_of :: < cs_sparc_op > () - 16usize] ; ["Alignment of cs_sparc_op"] [:: std :: mem :: align_of :: < cs_sparc_op > () - 8usize] ; ["Offset of field: cs_sparc_op::type_"] [:: std :: mem :: offset_of ! (cs_sparc_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sparc { # [doc = "< code condition for this insn"] pub cc : sparc_cc , # [doc = "< branch hint: encoding as bitwise OR of sparc_hint."] pub hint : sparc_hint , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sparc_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sparc"] [:: std :: mem :: size_of :: < cs_sparc > () - 80usize] ; ["Alignment of cs_sparc"] [:: std :: mem :: align_of :: < cs_sparc > () - 8usize] ; ["Offset of field: cs_sparc::cc"] [:: std :: mem :: offset_of ! (cs_sparc , cc) - 0usize] ; ["Offset of field: cs_sparc::hint"] [:: std :: mem :: offset_of ! (cs_sparc , hint) - 4usize] ; ["Offset of field: cs_sparc::op_count"] [:: std :: mem :: offset_of ! (cs_sparc , op_count) - 8usize] ; ["Offset of field: cs_sparc::operands"] [:: std :: mem :: offset_of ! (cs_sparc , operands) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_sparc { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . hint , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SPARC instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn { SPARC_INS_INVALID = 0 , SPARC_INS_ADDCC = 1 , SPARC_INS_ADDX = 2 , SPARC_INS_ADDXCC = 3 , SPARC_INS_ADDXC = 4 , SPARC_INS_ADDXCCC = 5 , SPARC_INS_ADD = 6 , SPARC_INS_ALIGNADDR = 7 , SPARC_INS_ALIGNADDRL = 8 , SPARC_INS_ANDCC = 9 , SPARC_INS_ANDNCC = 10 , SPARC_INS_ANDN = 11 , SPARC_INS_AND = 12 , SPARC_INS_ARRAY16 = 13 , SPARC_INS_ARRAY32 = 14 , SPARC_INS_ARRAY8 = 15 , SPARC_INS_B = 16 , SPARC_INS_JMP = 17 , SPARC_INS_BMASK = 18 , SPARC_INS_FB = 19 , SPARC_INS_BRGEZ = 20 , SPARC_INS_BRGZ = 21 , SPARC_INS_BRLEZ = 22 , SPARC_INS_BRLZ = 23 , SPARC_INS_BRNZ = 24 , SPARC_INS_BRZ = 25 , SPARC_INS_BSHUFFLE = 26 , SPARC_INS_CALL = 27 , SPARC_INS_CASX = 28 , SPARC_INS_CAS = 29 , SPARC_INS_CMASK16 = 30 , SPARC_INS_CMASK32 = 31 , SPARC_INS_CMASK8 = 32 , SPARC_INS_CMP = 33 , SPARC_INS_EDGE16 = 34 , SPARC_INS_EDGE16L = 35 , SPARC_INS_EDGE16LN = 36 , SPARC_INS_EDGE16N = 37 , SPARC_INS_EDGE32 = 38 , SPARC_INS_EDGE32L = 39 , SPARC_INS_EDGE32LN = 40 , SPARC_INS_EDGE32N = 41 , SPARC_INS_EDGE8 = 42 , SPARC_INS_EDGE8L = 43 , SPARC_INS_EDGE8LN = 44 , SPARC_INS_EDGE8N = 45 , SPARC_INS_FABSD = 46 , SPARC_INS_FABSQ = 47 , SPARC_INS_FABSS = 48 , SPARC_INS_FADDD = 49 , SPARC_INS_FADDQ = 50 , SPARC_INS_FADDS = 51 , SPARC_INS_FALIGNDATA = 52 , SPARC_INS_FAND = 53 , SPARC_INS_FANDNOT1 = 54 , SPARC_INS_FANDNOT1S = 55 , SPARC_INS_FANDNOT2 = 56 , SPARC_INS_FANDNOT2S = 57 , SPARC_INS_FANDS = 58 , SPARC_INS_FCHKSM16 = 59 , SPARC_INS_FCMPD = 60 , SPARC_INS_FCMPEQ16 = 61 , SPARC_INS_FCMPEQ32 = 62 , SPARC_INS_FCMPGT16 = 63 , SPARC_INS_FCMPGT32 = 64 , SPARC_INS_FCMPLE16 = 65 , SPARC_INS_FCMPLE32 = 66 , SPARC_INS_FCMPNE16 = 67 , SPARC_INS_FCMPNE32 = 68 , SPARC_INS_FCMPQ = 69 , SPARC_INS_FCMPS = 70 , SPARC_INS_FDIVD = 71 , SPARC_INS_FDIVQ = 72 , SPARC_INS_FDIVS = 73 , SPARC_INS_FDMULQ = 74 , SPARC_INS_FDTOI = 75 , SPARC_INS_FDTOQ = 76 , SPARC_INS_FDTOS = 77 , SPARC_INS_FDTOX = 78 , SPARC_INS_FEXPAND = 79 , SPARC_INS_FHADDD = 80 , SPARC_INS_FHADDS = 81 , SPARC_INS_FHSUBD = 82 , SPARC_INS_FHSUBS = 83 , SPARC_INS_FITOD = 84 , SPARC_INS_FITOQ = 85 , SPARC_INS_FITOS = 86 , SPARC_INS_FLCMPD = 87 , SPARC_INS_FLCMPS = 88 , SPARC_INS_FLUSHW = 89 , SPARC_INS_FMEAN16 = 90 , SPARC_INS_FMOVD = 91 , SPARC_INS_FMOVQ = 92 , SPARC_INS_FMOVRDGEZ = 93 , SPARC_INS_FMOVRQGEZ = 94 , SPARC_INS_FMOVRSGEZ = 95 , SPARC_INS_FMOVRDGZ = 96 , SPARC_INS_FMOVRQGZ = 97 , SPARC_INS_FMOVRSGZ = 98 , SPARC_INS_FMOVRDLEZ = 99 , SPARC_INS_FMOVRQLEZ = 100 , SPARC_INS_FMOVRSLEZ = 101 , SPARC_INS_FMOVRDLZ = 102 , SPARC_INS_FMOVRQLZ = 103 , SPARC_INS_FMOVRSLZ = 104 , SPARC_INS_FMOVRDNZ = 105 , SPARC_INS_FMOVRQNZ = 106 , SPARC_INS_FMOVRSNZ = 107 , SPARC_INS_FMOVRDZ = 108 , SPARC_INS_FMOVRQZ = 109 , SPARC_INS_FMOVRSZ = 110 , SPARC_INS_FMOVS = 111 , SPARC_INS_FMUL8SUX16 = 112 , SPARC_INS_FMUL8ULX16 = 113 , SPARC_INS_FMUL8X16 = 114 , SPARC_INS_FMUL8X16AL = 115 , SPARC_INS_FMUL8X16AU = 116 , SPARC_INS_FMULD = 117 , SPARC_INS_FMULD8SUX16 = 118 , SPARC_INS_FMULD8ULX16 = 119 , SPARC_INS_FMULQ = 120 , SPARC_INS_FMULS = 121 , SPARC_INS_FNADDD = 122 , SPARC_INS_FNADDS = 123 , SPARC_INS_FNAND = 124 , SPARC_INS_FNANDS = 125 , SPARC_INS_FNEGD = 126 , SPARC_INS_FNEGQ = 127 , SPARC_INS_FNEGS = 128 , SPARC_INS_FNHADDD = 129 , SPARC_INS_FNHADDS = 130 , SPARC_INS_FNOR = 131 , SPARC_INS_FNORS = 132 , SPARC_INS_FNOT1 = 133 , SPARC_INS_FNOT1S = 134 , SPARC_INS_FNOT2 = 135 , SPARC_INS_FNOT2S = 136 , SPARC_INS_FONE = 137 , SPARC_INS_FONES = 138 , SPARC_INS_FOR = 139 , SPARC_INS_FORNOT1 = 140 , SPARC_INS_FORNOT1S = 141 , SPARC_INS_FORNOT2 = 142 , SPARC_INS_FORNOT2S = 143 , SPARC_INS_FORS = 144 , SPARC_INS_FPACK16 = 145 , SPARC_INS_FPACK32 = 146 , SPARC_INS_FPACKFIX = 147 , SPARC_INS_FPADD16 = 148 , SPARC_INS_FPADD16S = 149 , SPARC_INS_FPADD32 = 150 , SPARC_INS_FPADD32S = 151 , SPARC_INS_FPADD64 = 152 , SPARC_INS_FPMERGE = 153 , SPARC_INS_FPSUB16 = 154 , SPARC_INS_FPSUB16S = 155 , SPARC_INS_FPSUB32 = 156 , SPARC_INS_FPSUB32S = 157 , SPARC_INS_FQTOD = 158 , SPARC_INS_FQTOI = 159 , SPARC_INS_FQTOS = 160 , SPARC_INS_FQTOX = 161 , SPARC_INS_FSLAS16 = 162 , SPARC_INS_FSLAS32 = 163 , SPARC_INS_FSLL16 = 164 , SPARC_INS_FSLL32 = 165 , SPARC_INS_FSMULD = 166 , SPARC_INS_FSQRTD = 167 , SPARC_INS_FSQRTQ = 168 , SPARC_INS_FSQRTS = 169 , SPARC_INS_FSRA16 = 170 , SPARC_INS_FSRA32 = 171 , SPARC_INS_FSRC1 = 172 , SPARC_INS_FSRC1S = 173 , SPARC_INS_FSRC2 = 174 , SPARC_INS_FSRC2S = 175 , SPARC_INS_FSRL16 = 176 , SPARC_INS_FSRL32 = 177 , SPARC_INS_FSTOD = 178 , SPARC_INS_FSTOI = 179 , SPARC_INS_FSTOQ = 180 , SPARC_INS_FSTOX = 181 , SPARC_INS_FSUBD = 182 , SPARC_INS_FSUBQ = 183 , SPARC_INS_FSUBS = 184 , SPARC_INS_FXNOR = 185 , SPARC_INS_FXNORS = 186 , SPARC_INS_FXOR = 187 , SPARC_INS_FXORS = 188 , SPARC_INS_FXTOD = 189 , SPARC_INS_FXTOQ = 190 , SPARC_INS_FXTOS = 191 , SPARC_INS_FZERO = 192 , SPARC_INS_FZEROS = 193 , SPARC_INS_JMPL = 194 , SPARC_INS_LDD = 195 , SPARC_INS_LD = 196 , SPARC_INS_LDQ = 197 , SPARC_INS_LDSB = 198 , SPARC_INS_LDSH = 199 , SPARC_INS_LDSW = 200 , SPARC_INS_LDUB = 201 , SPARC_INS_LDUH = 202 , SPARC_INS_LDX = 203 , SPARC_INS_LZCNT = 204 , SPARC_INS_MEMBAR = 205 , SPARC_INS_MOVDTOX = 206 , SPARC_INS_MOV = 207 , SPARC_INS_MOVRGEZ = 208 , SPARC_INS_MOVRGZ = 209 , SPARC_INS_MOVRLEZ = 210 , SPARC_INS_MOVRLZ = 211 , SPARC_INS_MOVRNZ = 212 , SPARC_INS_MOVRZ = 213 , SPARC_INS_MOVSTOSW = 214 , SPARC_INS_MOVSTOUW = 215 , SPARC_INS_MULX = 216 , SPARC_INS_NOP = 217 , SPARC_INS_ORCC = 218 , SPARC_INS_ORNCC = 219 , SPARC_INS_ORN = 220 , SPARC_INS_OR = 221 , SPARC_INS_PDIST = 222 , SPARC_INS_PDISTN = 223 , SPARC_INS_POPC = 224 , SPARC_INS_RD = 225 , SPARC_INS_RESTORE = 226 , SPARC_INS_RETT = 227 , SPARC_INS_SAVE = 228 , SPARC_INS_SDIVCC = 229 , SPARC_INS_SDIVX = 230 , SPARC_INS_SDIV = 231 , SPARC_INS_SETHI = 232 , SPARC_INS_SHUTDOWN = 233 , SPARC_INS_SIAM = 234 , SPARC_INS_SLLX = 235 , SPARC_INS_SLL = 236 , SPARC_INS_SMULCC = 237 , SPARC_INS_SMUL = 238 , SPARC_INS_SRAX = 239 , SPARC_INS_SRA = 240 , SPARC_INS_SRLX = 241 , SPARC_INS_SRL = 242 , SPARC_INS_STBAR = 243 , SPARC_INS_STB = 244 , SPARC_INS_STD = 245 , SPARC_INS_ST = 246 , SPARC_INS_STH = 247 , SPARC_INS_STQ = 248 , SPARC_INS_STX = 249 , SPARC_INS_SUBCC = 250 , SPARC_INS_SUBX = 251 , SPARC_INS_SUBXCC = 252 , SPARC_INS_SUB = 253 , SPARC_INS_SWAP = 254 , SPARC_INS_TADDCCTV = 255 , SPARC_INS_TADDCC = 256 , SPARC_INS_T = 257 , SPARC_INS_TSUBCCTV = 258 , SPARC_INS_TSUBCC = 259 , SPARC_INS_UDIVCC = 260 , SPARC_INS_UDIVX = 261 , SPARC_INS_UDIV = 262 , SPARC_INS_UMULCC = 263 , SPARC_INS_UMULXHI = 264 , SPARC_INS_UMUL = 265 , SPARC_INS_UNIMP = 266 , SPARC_INS_FCMPED = 267 , SPARC_INS_FCMPEQ = 268 , SPARC_INS_FCMPES = 269 , SPARC_INS_WR = 270 , SPARC_INS_XMULX = 271 , SPARC_INS_XMULXHI = 272 , SPARC_INS_XNORCC = 273 , SPARC_INS_XNOR = 274 , SPARC_INS_XORCC = 275 , SPARC_INS_XOR = 276 , SPARC_INS_RET = 277 , SPARC_INS_RETL = 278 , SPARC_INS_ENDING = 279 , } # [repr (u32)] # [doc = " Group of SPARC instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sparc_insn_group { # [doc = "< = CS_GRP_INVALID"] SPARC_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SPARC_GRP_JUMP = 1 , SPARC_GRP_HARDQUAD = 128 , SPARC_GRP_V9 = 129 , SPARC_GRP_VIS = 130 , SPARC_GRP_VIS2 = 131 , SPARC_GRP_VIS3 = 132 , SPARC_GRP_32BIT = 133 , SPARC_GRP_64BIT = 134 , SPARC_GRP_ENDING = 135 , } # [repr (u32)] # [doc = " Enums corresponding to SystemZ condition codes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_cc { # [doc = "< invalid CC (default)"] SYSZ_CC_INVALID = 0 , SYSZ_CC_O = 1 , SYSZ_CC_H = 2 , SYSZ_CC_NLE = 3 , SYSZ_CC_L = 4 , SYSZ_CC_NHE = 5 , SYSZ_CC_LH = 6 , SYSZ_CC_NE = 7 , SYSZ_CC_E = 8 , SYSZ_CC_NLH = 9 , SYSZ_CC_HE = 10 , SYSZ_CC_NL = 11 , SYSZ_CC_LE = 12 , SYSZ_CC_NH = 13 , SYSZ_CC_NO = 14 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SYSZ_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SYSZ_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SYSZ_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SYSZ_OP_MEM = 3 , # [doc = "< Access register operand."] SYSZ_OP_ACREG = 64 , } # [repr (u32)] # [doc = " SystemZ registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_reg { SYSZ_REG_INVALID = 0 , SYSZ_REG_0 = 1 , SYSZ_REG_1 = 2 , SYSZ_REG_2 = 3 , SYSZ_REG_3 = 4 , SYSZ_REG_4 = 5 , SYSZ_REG_5 = 6 , SYSZ_REG_6 = 7 , SYSZ_REG_7 = 8 , SYSZ_REG_8 = 9 , SYSZ_REG_9 = 10 , SYSZ_REG_10 = 11 , SYSZ_REG_11 = 12 , SYSZ_REG_12 = 13 , SYSZ_REG_13 = 14 , SYSZ_REG_14 = 15 , SYSZ_REG_15 = 16 , SYSZ_REG_CC = 17 , SYSZ_REG_F0 = 18 , SYSZ_REG_F1 = 19 , SYSZ_REG_F2 = 20 , SYSZ_REG_F3 = 21 , SYSZ_REG_F4 = 22 , SYSZ_REG_F5 = 23 , SYSZ_REG_F6 = 24 , SYSZ_REG_F7 = 25 , SYSZ_REG_F8 = 26 , SYSZ_REG_F9 = 27 , SYSZ_REG_F10 = 28 , SYSZ_REG_F11 = 29 , SYSZ_REG_F12 = 30 , SYSZ_REG_F13 = 31 , SYSZ_REG_F14 = 32 , SYSZ_REG_F15 = 33 , SYSZ_REG_R0L = 34 , SYSZ_REG_A0 = 35 , SYSZ_REG_A1 = 36 , SYSZ_REG_A2 = 37 , SYSZ_REG_A3 = 38 , SYSZ_REG_A4 = 39 , SYSZ_REG_A5 = 40 , SYSZ_REG_A6 = 41 , SYSZ_REG_A7 = 42 , SYSZ_REG_A8 = 43 , SYSZ_REG_A9 = 44 , SYSZ_REG_A10 = 45 , SYSZ_REG_A11 = 46 , SYSZ_REG_A12 = 47 , SYSZ_REG_A13 = 48 , SYSZ_REG_A14 = 49 , SYSZ_REG_A15 = 50 , SYSZ_REG_C0 = 51 , SYSZ_REG_C1 = 52 , SYSZ_REG_C2 = 53 , SYSZ_REG_C3 = 54 , SYSZ_REG_C4 = 55 , SYSZ_REG_C5 = 56 , SYSZ_REG_C6 = 57 , SYSZ_REG_C7 = 58 , SYSZ_REG_C8 = 59 , SYSZ_REG_C9 = 60 , SYSZ_REG_C10 = 61 , SYSZ_REG_C11 = 62 , SYSZ_REG_C12 = 63 , SYSZ_REG_C13 = 64 , SYSZ_REG_C14 = 65 , SYSZ_REG_C15 = 66 , SYSZ_REG_V0 = 67 , SYSZ_REG_V1 = 68 , SYSZ_REG_V2 = 69 , SYSZ_REG_V3 = 70 , SYSZ_REG_V4 = 71 , SYSZ_REG_V5 = 72 , SYSZ_REG_V6 = 73 , SYSZ_REG_V7 = 74 , SYSZ_REG_V8 = 75 , SYSZ_REG_V9 = 76 , SYSZ_REG_V10 = 77 , SYSZ_REG_V11 = 78 , SYSZ_REG_V12 = 79 , SYSZ_REG_V13 = 80 , SYSZ_REG_V14 = 81 , SYSZ_REG_V15 = 82 , SYSZ_REG_V16 = 83 , SYSZ_REG_V17 = 84 , SYSZ_REG_V18 = 85 , SYSZ_REG_V19 = 86 , SYSZ_REG_V20 = 87 , SYSZ_REG_V21 = 88 , SYSZ_REG_V22 = 89 , SYSZ_REG_V23 = 90 , SYSZ_REG_V24 = 91 , SYSZ_REG_V25 = 92 , SYSZ_REG_V26 = 93 , SYSZ_REG_V27 = 94 , SYSZ_REG_V28 = 95 , SYSZ_REG_V29 = 96 , SYSZ_REG_V30 = 97 , SYSZ_REG_V31 = 98 , SYSZ_REG_F16 = 99 , SYSZ_REG_F17 = 100 , SYSZ_REG_F18 = 101 , SYSZ_REG_F19 = 102 , SYSZ_REG_F20 = 103 , SYSZ_REG_F21 = 104 , SYSZ_REG_F22 = 105 , SYSZ_REG_F23 = 106 , SYSZ_REG_F24 = 107 , SYSZ_REG_F25 = 108 , SYSZ_REG_F26 = 109 , SYSZ_REG_F27 = 110 , SYSZ_REG_F28 = 111 , SYSZ_REG_F29 = 112 , SYSZ_REG_F30 = 113 , SYSZ_REG_F31 = 114 , SYSZ_REG_F0Q = 115 , SYSZ_REG_F4Q = 116 , SYSZ_REG_ENDING = 117 , } # [doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sysz_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< BDLAddr operand"] pub length : u64 , # [doc = "< displacement/offset value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sysz_op_mem"] [:: std :: mem :: size_of :: < sysz_op_mem > () - 24usize] ; ["Alignment of sysz_op_mem"] [:: std :: mem :: align_of :: < sysz_op_mem > () - 8usize] ; ["Offset of field: sysz_op_mem::base"] [:: std :: mem :: offset_of ! (sysz_op_mem , base) - 0usize] ; ["Offset of field: sysz_op_mem::index"] [:: std :: mem :: offset_of ! (sysz_op_mem , index) - 1usize] ; ["Offset of field: sysz_op_mem::length"] [:: std :: mem :: offset_of ! (sysz_op_mem , length) - 8usize] ; ["Offset of field: sysz_op_mem::disp"] [:: std :: mem :: offset_of ! (sysz_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz_op { # [doc = "< operand type"] pub type_ : sysz_op_type , pub __bindgen_anon_1 : cs_sysz_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sysz_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : sysz_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/disp value for MEM operand"] pub mem : sysz_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sysz_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_sysz_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sysz_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sysz_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sysz_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz_op"] [:: std :: mem :: size_of :: < cs_sysz_op > () - 32usize] ; ["Alignment of cs_sysz_op"] [:: std :: mem :: align_of :: < cs_sysz_op > () - 8usize] ; ["Offset of field: cs_sysz_op::type_"] [:: std :: mem :: offset_of ! (cs_sysz_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sysz { # [doc = "< Code condition"] pub cc : sysz_cc , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_sysz_op ; 6usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sysz"] [:: std :: mem :: size_of :: < cs_sysz > () - 200usize] ; ["Alignment of cs_sysz"] [:: std :: mem :: align_of :: < cs_sysz > () - 8usize] ; ["Offset of field: cs_sysz::cc"] [:: std :: mem :: offset_of ! (cs_sysz , cc) - 0usize] ; ["Offset of field: cs_sysz::op_count"] [:: std :: mem :: offset_of ! (cs_sysz , op_count) - 4usize] ; ["Offset of field: cs_sysz::operands"] [:: std :: mem :: offset_of ! (cs_sysz , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sysz { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . op_count , self . operands) } } # [repr (u32)] # [doc = " SystemZ instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn { SYSZ_INS_INVALID = 0 , SYSZ_INS_A = 1 , SYSZ_INS_ADB = 2 , SYSZ_INS_ADBR = 3 , SYSZ_INS_AEB = 4 , SYSZ_INS_AEBR = 5 , SYSZ_INS_AFI = 6 , SYSZ_INS_AG = 7 , SYSZ_INS_AGF = 8 , SYSZ_INS_AGFI = 9 , SYSZ_INS_AGFR = 10 , SYSZ_INS_AGHI = 11 , SYSZ_INS_AGHIK = 12 , SYSZ_INS_AGR = 13 , SYSZ_INS_AGRK = 14 , SYSZ_INS_AGSI = 15 , SYSZ_INS_AH = 16 , SYSZ_INS_AHI = 17 , SYSZ_INS_AHIK = 18 , SYSZ_INS_AHY = 19 , SYSZ_INS_AIH = 20 , SYSZ_INS_AL = 21 , SYSZ_INS_ALC = 22 , SYSZ_INS_ALCG = 23 , SYSZ_INS_ALCGR = 24 , SYSZ_INS_ALCR = 25 , SYSZ_INS_ALFI = 26 , SYSZ_INS_ALG = 27 , SYSZ_INS_ALGF = 28 , SYSZ_INS_ALGFI = 29 , SYSZ_INS_ALGFR = 30 , SYSZ_INS_ALGHSIK = 31 , SYSZ_INS_ALGR = 32 , SYSZ_INS_ALGRK = 33 , SYSZ_INS_ALHSIK = 34 , SYSZ_INS_ALR = 35 , SYSZ_INS_ALRK = 36 , SYSZ_INS_ALY = 37 , SYSZ_INS_AR = 38 , SYSZ_INS_ARK = 39 , SYSZ_INS_ASI = 40 , SYSZ_INS_AXBR = 41 , SYSZ_INS_AY = 42 , SYSZ_INS_BCR = 43 , SYSZ_INS_BRC = 44 , SYSZ_INS_BRCL = 45 , SYSZ_INS_CGIJ = 46 , SYSZ_INS_CGRJ = 47 , SYSZ_INS_CIJ = 48 , SYSZ_INS_CLGIJ = 49 , SYSZ_INS_CLGRJ = 50 , SYSZ_INS_CLIJ = 51 , SYSZ_INS_CLRJ = 52 , SYSZ_INS_CRJ = 53 , SYSZ_INS_BER = 54 , SYSZ_INS_JE = 55 , SYSZ_INS_JGE = 56 , SYSZ_INS_LOCE = 57 , SYSZ_INS_LOCGE = 58 , SYSZ_INS_LOCGRE = 59 , SYSZ_INS_LOCRE = 60 , SYSZ_INS_STOCE = 61 , SYSZ_INS_STOCGE = 62 , SYSZ_INS_BHR = 63 , SYSZ_INS_BHER = 64 , SYSZ_INS_JHE = 65 , SYSZ_INS_JGHE = 66 , SYSZ_INS_LOCHE = 67 , SYSZ_INS_LOCGHE = 68 , SYSZ_INS_LOCGRHE = 69 , SYSZ_INS_LOCRHE = 70 , SYSZ_INS_STOCHE = 71 , SYSZ_INS_STOCGHE = 72 , SYSZ_INS_JH = 73 , SYSZ_INS_JGH = 74 , SYSZ_INS_LOCH = 75 , SYSZ_INS_LOCGH = 76 , SYSZ_INS_LOCGRH = 77 , SYSZ_INS_LOCRH = 78 , SYSZ_INS_STOCH = 79 , SYSZ_INS_STOCGH = 80 , SYSZ_INS_CGIJNLH = 81 , SYSZ_INS_CGRJNLH = 82 , SYSZ_INS_CIJNLH = 83 , SYSZ_INS_CLGIJNLH = 84 , SYSZ_INS_CLGRJNLH = 85 , SYSZ_INS_CLIJNLH = 86 , SYSZ_INS_CLRJNLH = 87 , SYSZ_INS_CRJNLH = 88 , SYSZ_INS_CGIJE = 89 , SYSZ_INS_CGRJE = 90 , SYSZ_INS_CIJE = 91 , SYSZ_INS_CLGIJE = 92 , SYSZ_INS_CLGRJE = 93 , SYSZ_INS_CLIJE = 94 , SYSZ_INS_CLRJE = 95 , SYSZ_INS_CRJE = 96 , SYSZ_INS_CGIJNLE = 97 , SYSZ_INS_CGRJNLE = 98 , SYSZ_INS_CIJNLE = 99 , SYSZ_INS_CLGIJNLE = 100 , SYSZ_INS_CLGRJNLE = 101 , SYSZ_INS_CLIJNLE = 102 , SYSZ_INS_CLRJNLE = 103 , SYSZ_INS_CRJNLE = 104 , SYSZ_INS_CGIJH = 105 , SYSZ_INS_CGRJH = 106 , SYSZ_INS_CIJH = 107 , SYSZ_INS_CLGIJH = 108 , SYSZ_INS_CLGRJH = 109 , SYSZ_INS_CLIJH = 110 , SYSZ_INS_CLRJH = 111 , SYSZ_INS_CRJH = 112 , SYSZ_INS_CGIJNL = 113 , SYSZ_INS_CGRJNL = 114 , SYSZ_INS_CIJNL = 115 , SYSZ_INS_CLGIJNL = 116 , SYSZ_INS_CLGRJNL = 117 , SYSZ_INS_CLIJNL = 118 , SYSZ_INS_CLRJNL = 119 , SYSZ_INS_CRJNL = 120 , SYSZ_INS_CGIJHE = 121 , SYSZ_INS_CGRJHE = 122 , SYSZ_INS_CIJHE = 123 , SYSZ_INS_CLGIJHE = 124 , SYSZ_INS_CLGRJHE = 125 , SYSZ_INS_CLIJHE = 126 , SYSZ_INS_CLRJHE = 127 , SYSZ_INS_CRJHE = 128 , SYSZ_INS_CGIJNHE = 129 , SYSZ_INS_CGRJNHE = 130 , SYSZ_INS_CIJNHE = 131 , SYSZ_INS_CLGIJNHE = 132 , SYSZ_INS_CLGRJNHE = 133 , SYSZ_INS_CLIJNHE = 134 , SYSZ_INS_CLRJNHE = 135 , SYSZ_INS_CRJNHE = 136 , SYSZ_INS_CGIJL = 137 , SYSZ_INS_CGRJL = 138 , SYSZ_INS_CIJL = 139 , SYSZ_INS_CLGIJL = 140 , SYSZ_INS_CLGRJL = 141 , SYSZ_INS_CLIJL = 142 , SYSZ_INS_CLRJL = 143 , SYSZ_INS_CRJL = 144 , SYSZ_INS_CGIJNH = 145 , SYSZ_INS_CGRJNH = 146 , SYSZ_INS_CIJNH = 147 , SYSZ_INS_CLGIJNH = 148 , SYSZ_INS_CLGRJNH = 149 , SYSZ_INS_CLIJNH = 150 , SYSZ_INS_CLRJNH = 151 , SYSZ_INS_CRJNH = 152 , SYSZ_INS_CGIJLE = 153 , SYSZ_INS_CGRJLE = 154 , SYSZ_INS_CIJLE = 155 , SYSZ_INS_CLGIJLE = 156 , SYSZ_INS_CLGRJLE = 157 , SYSZ_INS_CLIJLE = 158 , SYSZ_INS_CLRJLE = 159 , SYSZ_INS_CRJLE = 160 , SYSZ_INS_CGIJNE = 161 , SYSZ_INS_CGRJNE = 162 , SYSZ_INS_CIJNE = 163 , SYSZ_INS_CLGIJNE = 164 , SYSZ_INS_CLGRJNE = 165 , SYSZ_INS_CLIJNE = 166 , SYSZ_INS_CLRJNE = 167 , SYSZ_INS_CRJNE = 168 , SYSZ_INS_CGIJLH = 169 , SYSZ_INS_CGRJLH = 170 , SYSZ_INS_CIJLH = 171 , SYSZ_INS_CLGIJLH = 172 , SYSZ_INS_CLGRJLH = 173 , SYSZ_INS_CLIJLH = 174 , SYSZ_INS_CLRJLH = 175 , SYSZ_INS_CRJLH = 176 , SYSZ_INS_BLR = 177 , SYSZ_INS_BLER = 178 , SYSZ_INS_JLE = 179 , SYSZ_INS_JGLE = 180 , SYSZ_INS_LOCLE = 181 , SYSZ_INS_LOCGLE = 182 , SYSZ_INS_LOCGRLE = 183 , SYSZ_INS_LOCRLE = 184 , SYSZ_INS_STOCLE = 185 , SYSZ_INS_STOCGLE = 186 , SYSZ_INS_BLHR = 187 , SYSZ_INS_JLH = 188 , SYSZ_INS_JGLH = 189 , SYSZ_INS_LOCLH = 190 , SYSZ_INS_LOCGLH = 191 , SYSZ_INS_LOCGRLH = 192 , SYSZ_INS_LOCRLH = 193 , SYSZ_INS_STOCLH = 194 , SYSZ_INS_STOCGLH = 195 , SYSZ_INS_JL = 196 , SYSZ_INS_JGL = 197 , SYSZ_INS_LOCL = 198 , SYSZ_INS_LOCGL = 199 , SYSZ_INS_LOCGRL = 200 , SYSZ_INS_LOCRL = 201 , SYSZ_INS_LOC = 202 , SYSZ_INS_LOCG = 203 , SYSZ_INS_LOCGR = 204 , SYSZ_INS_LOCR = 205 , SYSZ_INS_STOCL = 206 , SYSZ_INS_STOCGL = 207 , SYSZ_INS_BNER = 208 , SYSZ_INS_JNE = 209 , SYSZ_INS_JGNE = 210 , SYSZ_INS_LOCNE = 211 , SYSZ_INS_LOCGNE = 212 , SYSZ_INS_LOCGRNE = 213 , SYSZ_INS_LOCRNE = 214 , SYSZ_INS_STOCNE = 215 , SYSZ_INS_STOCGNE = 216 , SYSZ_INS_BNHR = 217 , SYSZ_INS_BNHER = 218 , SYSZ_INS_JNHE = 219 , SYSZ_INS_JGNHE = 220 , SYSZ_INS_LOCNHE = 221 , SYSZ_INS_LOCGNHE = 222 , SYSZ_INS_LOCGRNHE = 223 , SYSZ_INS_LOCRNHE = 224 , SYSZ_INS_STOCNHE = 225 , SYSZ_INS_STOCGNHE = 226 , SYSZ_INS_JNH = 227 , SYSZ_INS_JGNH = 228 , SYSZ_INS_LOCNH = 229 , SYSZ_INS_LOCGNH = 230 , SYSZ_INS_LOCGRNH = 231 , SYSZ_INS_LOCRNH = 232 , SYSZ_INS_STOCNH = 233 , SYSZ_INS_STOCGNH = 234 , SYSZ_INS_BNLR = 235 , SYSZ_INS_BNLER = 236 , SYSZ_INS_JNLE = 237 , SYSZ_INS_JGNLE = 238 , SYSZ_INS_LOCNLE = 239 , SYSZ_INS_LOCGNLE = 240 , SYSZ_INS_LOCGRNLE = 241 , SYSZ_INS_LOCRNLE = 242 , SYSZ_INS_STOCNLE = 243 , SYSZ_INS_STOCGNLE = 244 , SYSZ_INS_BNLHR = 245 , SYSZ_INS_JNLH = 246 , SYSZ_INS_JGNLH = 247 , SYSZ_INS_LOCNLH = 248 , SYSZ_INS_LOCGNLH = 249 , SYSZ_INS_LOCGRNLH = 250 , SYSZ_INS_LOCRNLH = 251 , SYSZ_INS_STOCNLH = 252 , SYSZ_INS_STOCGNLH = 253 , SYSZ_INS_JNL = 254 , SYSZ_INS_JGNL = 255 , SYSZ_INS_LOCNL = 256 , SYSZ_INS_LOCGNL = 257 , SYSZ_INS_LOCGRNL = 258 , SYSZ_INS_LOCRNL = 259 , SYSZ_INS_STOCNL = 260 , SYSZ_INS_STOCGNL = 261 , SYSZ_INS_BNOR = 262 , SYSZ_INS_JNO = 263 , SYSZ_INS_JGNO = 264 , SYSZ_INS_LOCNO = 265 , SYSZ_INS_LOCGNO = 266 , SYSZ_INS_LOCGRNO = 267 , SYSZ_INS_LOCRNO = 268 , SYSZ_INS_STOCNO = 269 , SYSZ_INS_STOCGNO = 270 , SYSZ_INS_BOR = 271 , SYSZ_INS_JO = 272 , SYSZ_INS_JGO = 273 , SYSZ_INS_LOCO = 274 , SYSZ_INS_LOCGO = 275 , SYSZ_INS_LOCGRO = 276 , SYSZ_INS_LOCRO = 277 , SYSZ_INS_STOCO = 278 , SYSZ_INS_STOCGO = 279 , SYSZ_INS_STOC = 280 , SYSZ_INS_STOCG = 281 , SYSZ_INS_BASR = 282 , SYSZ_INS_BR = 283 , SYSZ_INS_BRAS = 284 , SYSZ_INS_BRASL = 285 , SYSZ_INS_J = 286 , SYSZ_INS_JG = 287 , SYSZ_INS_BRCT = 288 , SYSZ_INS_BRCTG = 289 , SYSZ_INS_C = 290 , SYSZ_INS_CDB = 291 , SYSZ_INS_CDBR = 292 , SYSZ_INS_CDFBR = 293 , SYSZ_INS_CDGBR = 294 , SYSZ_INS_CDLFBR = 295 , SYSZ_INS_CDLGBR = 296 , SYSZ_INS_CEB = 297 , SYSZ_INS_CEBR = 298 , SYSZ_INS_CEFBR = 299 , SYSZ_INS_CEGBR = 300 , SYSZ_INS_CELFBR = 301 , SYSZ_INS_CELGBR = 302 , SYSZ_INS_CFDBR = 303 , SYSZ_INS_CFEBR = 304 , SYSZ_INS_CFI = 305 , SYSZ_INS_CFXBR = 306 , SYSZ_INS_CG = 307 , SYSZ_INS_CGDBR = 308 , SYSZ_INS_CGEBR = 309 , SYSZ_INS_CGF = 310 , SYSZ_INS_CGFI = 311 , SYSZ_INS_CGFR = 312 , SYSZ_INS_CGFRL = 313 , SYSZ_INS_CGH = 314 , SYSZ_INS_CGHI = 315 , SYSZ_INS_CGHRL = 316 , SYSZ_INS_CGHSI = 317 , SYSZ_INS_CGR = 318 , SYSZ_INS_CGRL = 319 , SYSZ_INS_CGXBR = 320 , SYSZ_INS_CH = 321 , SYSZ_INS_CHF = 322 , SYSZ_INS_CHHSI = 323 , SYSZ_INS_CHI = 324 , SYSZ_INS_CHRL = 325 , SYSZ_INS_CHSI = 326 , SYSZ_INS_CHY = 327 , SYSZ_INS_CIH = 328 , SYSZ_INS_CL = 329 , SYSZ_INS_CLC = 330 , SYSZ_INS_CLFDBR = 331 , SYSZ_INS_CLFEBR = 332 , SYSZ_INS_CLFHSI = 333 , SYSZ_INS_CLFI = 334 , SYSZ_INS_CLFXBR = 335 , SYSZ_INS_CLG = 336 , SYSZ_INS_CLGDBR = 337 , SYSZ_INS_CLGEBR = 338 , SYSZ_INS_CLGF = 339 , SYSZ_INS_CLGFI = 340 , SYSZ_INS_CLGFR = 341 , SYSZ_INS_CLGFRL = 342 , SYSZ_INS_CLGHRL = 343 , SYSZ_INS_CLGHSI = 344 , SYSZ_INS_CLGR = 345 , SYSZ_INS_CLGRL = 346 , SYSZ_INS_CLGXBR = 347 , SYSZ_INS_CLHF = 348 , SYSZ_INS_CLHHSI = 349 , SYSZ_INS_CLHRL = 350 , SYSZ_INS_CLI = 351 , SYSZ_INS_CLIH = 352 , SYSZ_INS_CLIY = 353 , SYSZ_INS_CLR = 354 , SYSZ_INS_CLRL = 355 , SYSZ_INS_CLST = 356 , SYSZ_INS_CLY = 357 , SYSZ_INS_CPSDR = 358 , SYSZ_INS_CR = 359 , SYSZ_INS_CRL = 360 , SYSZ_INS_CS = 361 , SYSZ_INS_CSG = 362 , SYSZ_INS_CSY = 363 , SYSZ_INS_CXBR = 364 , SYSZ_INS_CXFBR = 365 , SYSZ_INS_CXGBR = 366 , SYSZ_INS_CXLFBR = 367 , SYSZ_INS_CXLGBR = 368 , SYSZ_INS_CY = 369 , SYSZ_INS_DDB = 370 , SYSZ_INS_DDBR = 371 , SYSZ_INS_DEB = 372 , SYSZ_INS_DEBR = 373 , SYSZ_INS_DL = 374 , SYSZ_INS_DLG = 375 , SYSZ_INS_DLGR = 376 , SYSZ_INS_DLR = 377 , SYSZ_INS_DSG = 378 , SYSZ_INS_DSGF = 379 , SYSZ_INS_DSGFR = 380 , SYSZ_INS_DSGR = 381 , SYSZ_INS_DXBR = 382 , SYSZ_INS_EAR = 383 , SYSZ_INS_FIDBR = 384 , SYSZ_INS_FIDBRA = 385 , SYSZ_INS_FIEBR = 386 , SYSZ_INS_FIEBRA = 387 , SYSZ_INS_FIXBR = 388 , SYSZ_INS_FIXBRA = 389 , SYSZ_INS_FLOGR = 390 , SYSZ_INS_IC = 391 , SYSZ_INS_ICY = 392 , SYSZ_INS_IIHF = 393 , SYSZ_INS_IIHH = 394 , SYSZ_INS_IIHL = 395 , SYSZ_INS_IILF = 396 , SYSZ_INS_IILH = 397 , SYSZ_INS_IILL = 398 , SYSZ_INS_IPM = 399 , SYSZ_INS_L = 400 , SYSZ_INS_LA = 401 , SYSZ_INS_LAA = 402 , SYSZ_INS_LAAG = 403 , SYSZ_INS_LAAL = 404 , SYSZ_INS_LAALG = 405 , SYSZ_INS_LAN = 406 , SYSZ_INS_LANG = 407 , SYSZ_INS_LAO = 408 , SYSZ_INS_LAOG = 409 , SYSZ_INS_LARL = 410 , SYSZ_INS_LAX = 411 , SYSZ_INS_LAXG = 412 , SYSZ_INS_LAY = 413 , SYSZ_INS_LB = 414 , SYSZ_INS_LBH = 415 , SYSZ_INS_LBR = 416 , SYSZ_INS_LCDBR = 417 , SYSZ_INS_LCEBR = 418 , SYSZ_INS_LCGFR = 419 , SYSZ_INS_LCGR = 420 , SYSZ_INS_LCR = 421 , SYSZ_INS_LCXBR = 422 , SYSZ_INS_LD = 423 , SYSZ_INS_LDEB = 424 , SYSZ_INS_LDEBR = 425 , SYSZ_INS_LDGR = 426 , SYSZ_INS_LDR = 427 , SYSZ_INS_LDXBR = 428 , SYSZ_INS_LDXBRA = 429 , SYSZ_INS_LDY = 430 , SYSZ_INS_LE = 431 , SYSZ_INS_LEDBR = 432 , SYSZ_INS_LEDBRA = 433 , SYSZ_INS_LER = 434 , SYSZ_INS_LEXBR = 435 , SYSZ_INS_LEXBRA = 436 , SYSZ_INS_LEY = 437 , SYSZ_INS_LFH = 438 , SYSZ_INS_LG = 439 , SYSZ_INS_LGB = 440 , SYSZ_INS_LGBR = 441 , SYSZ_INS_LGDR = 442 , SYSZ_INS_LGF = 443 , SYSZ_INS_LGFI = 444 , SYSZ_INS_LGFR = 445 , SYSZ_INS_LGFRL = 446 , SYSZ_INS_LGH = 447 , SYSZ_INS_LGHI = 448 , SYSZ_INS_LGHR = 449 , SYSZ_INS_LGHRL = 450 , SYSZ_INS_LGR = 451 , SYSZ_INS_LGRL = 452 , SYSZ_INS_LH = 453 , SYSZ_INS_LHH = 454 , SYSZ_INS_LHI = 455 , SYSZ_INS_LHR = 456 , SYSZ_INS_LHRL = 457 , SYSZ_INS_LHY = 458 , SYSZ_INS_LLC = 459 , SYSZ_INS_LLCH = 460 , SYSZ_INS_LLCR = 461 , SYSZ_INS_LLGC = 462 , SYSZ_INS_LLGCR = 463 , SYSZ_INS_LLGF = 464 , SYSZ_INS_LLGFR = 465 , SYSZ_INS_LLGFRL = 466 , SYSZ_INS_LLGH = 467 , SYSZ_INS_LLGHR = 468 , SYSZ_INS_LLGHRL = 469 , SYSZ_INS_LLH = 470 , SYSZ_INS_LLHH = 471 , SYSZ_INS_LLHR = 472 , SYSZ_INS_LLHRL = 473 , SYSZ_INS_LLIHF = 474 , SYSZ_INS_LLIHH = 475 , SYSZ_INS_LLIHL = 476 , SYSZ_INS_LLILF = 477 , SYSZ_INS_LLILH = 478 , SYSZ_INS_LLILL = 479 , SYSZ_INS_LMG = 480 , SYSZ_INS_LNDBR = 481 , SYSZ_INS_LNEBR = 482 , SYSZ_INS_LNGFR = 483 , SYSZ_INS_LNGR = 484 , SYSZ_INS_LNR = 485 , SYSZ_INS_LNXBR = 486 , SYSZ_INS_LPDBR = 487 , SYSZ_INS_LPEBR = 488 , SYSZ_INS_LPGFR = 489 , SYSZ_INS_LPGR = 490 , SYSZ_INS_LPR = 491 , SYSZ_INS_LPXBR = 492 , SYSZ_INS_LR = 493 , SYSZ_INS_LRL = 494 , SYSZ_INS_LRV = 495 , SYSZ_INS_LRVG = 496 , SYSZ_INS_LRVGR = 497 , SYSZ_INS_LRVR = 498 , SYSZ_INS_LT = 499 , SYSZ_INS_LTDBR = 500 , SYSZ_INS_LTEBR = 501 , SYSZ_INS_LTG = 502 , SYSZ_INS_LTGF = 503 , SYSZ_INS_LTGFR = 504 , SYSZ_INS_LTGR = 505 , SYSZ_INS_LTR = 506 , SYSZ_INS_LTXBR = 507 , SYSZ_INS_LXDB = 508 , SYSZ_INS_LXDBR = 509 , SYSZ_INS_LXEB = 510 , SYSZ_INS_LXEBR = 511 , SYSZ_INS_LXR = 512 , SYSZ_INS_LY = 513 , SYSZ_INS_LZDR = 514 , SYSZ_INS_LZER = 515 , SYSZ_INS_LZXR = 516 , SYSZ_INS_MADB = 517 , SYSZ_INS_MADBR = 518 , SYSZ_INS_MAEB = 519 , SYSZ_INS_MAEBR = 520 , SYSZ_INS_MDB = 521 , SYSZ_INS_MDBR = 522 , SYSZ_INS_MDEB = 523 , SYSZ_INS_MDEBR = 524 , SYSZ_INS_MEEB = 525 , SYSZ_INS_MEEBR = 526 , SYSZ_INS_MGHI = 527 , SYSZ_INS_MH = 528 , SYSZ_INS_MHI = 529 , SYSZ_INS_MHY = 530 , SYSZ_INS_MLG = 531 , SYSZ_INS_MLGR = 532 , SYSZ_INS_MS = 533 , SYSZ_INS_MSDB = 534 , SYSZ_INS_MSDBR = 535 , SYSZ_INS_MSEB = 536 , SYSZ_INS_MSEBR = 537 , SYSZ_INS_MSFI = 538 , SYSZ_INS_MSG = 539 , SYSZ_INS_MSGF = 540 , SYSZ_INS_MSGFI = 541 , SYSZ_INS_MSGFR = 542 , SYSZ_INS_MSGR = 543 , SYSZ_INS_MSR = 544 , SYSZ_INS_MSY = 545 , SYSZ_INS_MVC = 546 , SYSZ_INS_MVGHI = 547 , SYSZ_INS_MVHHI = 548 , SYSZ_INS_MVHI = 549 , SYSZ_INS_MVI = 550 , SYSZ_INS_MVIY = 551 , SYSZ_INS_MVST = 552 , SYSZ_INS_MXBR = 553 , SYSZ_INS_MXDB = 554 , SYSZ_INS_MXDBR = 555 , SYSZ_INS_N = 556 , SYSZ_INS_NC = 557 , SYSZ_INS_NG = 558 , SYSZ_INS_NGR = 559 , SYSZ_INS_NGRK = 560 , SYSZ_INS_NI = 561 , SYSZ_INS_NIHF = 562 , SYSZ_INS_NIHH = 563 , SYSZ_INS_NIHL = 564 , SYSZ_INS_NILF = 565 , SYSZ_INS_NILH = 566 , SYSZ_INS_NILL = 567 , SYSZ_INS_NIY = 568 , SYSZ_INS_NR = 569 , SYSZ_INS_NRK = 570 , SYSZ_INS_NY = 571 , SYSZ_INS_O = 572 , SYSZ_INS_OC = 573 , SYSZ_INS_OG = 574 , SYSZ_INS_OGR = 575 , SYSZ_INS_OGRK = 576 , SYSZ_INS_OI = 577 , SYSZ_INS_OIHF = 578 , SYSZ_INS_OIHH = 579 , SYSZ_INS_OIHL = 580 , SYSZ_INS_OILF = 581 , SYSZ_INS_OILH = 582 , SYSZ_INS_OILL = 583 , SYSZ_INS_OIY = 584 , SYSZ_INS_OR = 585 , SYSZ_INS_ORK = 586 , SYSZ_INS_OY = 587 , SYSZ_INS_PFD = 588 , SYSZ_INS_PFDRL = 589 , SYSZ_INS_RISBG = 590 , SYSZ_INS_RISBHG = 591 , SYSZ_INS_RISBLG = 592 , SYSZ_INS_RLL = 593 , SYSZ_INS_RLLG = 594 , SYSZ_INS_RNSBG = 595 , SYSZ_INS_ROSBG = 596 , SYSZ_INS_RXSBG = 597 , SYSZ_INS_S = 598 , SYSZ_INS_SDB = 599 , SYSZ_INS_SDBR = 600 , SYSZ_INS_SEB = 601 , SYSZ_INS_SEBR = 602 , SYSZ_INS_SG = 603 , SYSZ_INS_SGF = 604 , SYSZ_INS_SGFR = 605 , SYSZ_INS_SGR = 606 , SYSZ_INS_SGRK = 607 , SYSZ_INS_SH = 608 , SYSZ_INS_SHY = 609 , SYSZ_INS_SL = 610 , SYSZ_INS_SLB = 611 , SYSZ_INS_SLBG = 612 , SYSZ_INS_SLBR = 613 , SYSZ_INS_SLFI = 614 , SYSZ_INS_SLG = 615 , SYSZ_INS_SLBGR = 616 , SYSZ_INS_SLGF = 617 , SYSZ_INS_SLGFI = 618 , SYSZ_INS_SLGFR = 619 , SYSZ_INS_SLGR = 620 , SYSZ_INS_SLGRK = 621 , SYSZ_INS_SLL = 622 , SYSZ_INS_SLLG = 623 , SYSZ_INS_SLLK = 624 , SYSZ_INS_SLR = 625 , SYSZ_INS_SLRK = 626 , SYSZ_INS_SLY = 627 , SYSZ_INS_SQDB = 628 , SYSZ_INS_SQDBR = 629 , SYSZ_INS_SQEB = 630 , SYSZ_INS_SQEBR = 631 , SYSZ_INS_SQXBR = 632 , SYSZ_INS_SR = 633 , SYSZ_INS_SRA = 634 , SYSZ_INS_SRAG = 635 , SYSZ_INS_SRAK = 636 , SYSZ_INS_SRK = 637 , SYSZ_INS_SRL = 638 , SYSZ_INS_SRLG = 639 , SYSZ_INS_SRLK = 640 , SYSZ_INS_SRST = 641 , SYSZ_INS_ST = 642 , SYSZ_INS_STC = 643 , SYSZ_INS_STCH = 644 , SYSZ_INS_STCY = 645 , SYSZ_INS_STD = 646 , SYSZ_INS_STDY = 647 , SYSZ_INS_STE = 648 , SYSZ_INS_STEY = 649 , SYSZ_INS_STFH = 650 , SYSZ_INS_STG = 651 , SYSZ_INS_STGRL = 652 , SYSZ_INS_STH = 653 , SYSZ_INS_STHH = 654 , SYSZ_INS_STHRL = 655 , SYSZ_INS_STHY = 656 , SYSZ_INS_STMG = 657 , SYSZ_INS_STRL = 658 , SYSZ_INS_STRV = 659 , SYSZ_INS_STRVG = 660 , SYSZ_INS_STY = 661 , SYSZ_INS_SXBR = 662 , SYSZ_INS_SY = 663 , SYSZ_INS_TM = 664 , SYSZ_INS_TMHH = 665 , SYSZ_INS_TMHL = 666 , SYSZ_INS_TMLH = 667 , SYSZ_INS_TMLL = 668 , SYSZ_INS_TMY = 669 , SYSZ_INS_X = 670 , SYSZ_INS_XC = 671 , SYSZ_INS_XG = 672 , SYSZ_INS_XGR = 673 , SYSZ_INS_XGRK = 674 , SYSZ_INS_XI = 675 , SYSZ_INS_XIHF = 676 , SYSZ_INS_XILF = 677 , SYSZ_INS_XIY = 678 , SYSZ_INS_XR = 679 , SYSZ_INS_XRK = 680 , SYSZ_INS_XY = 681 , SYSZ_INS_AD = 682 , SYSZ_INS_ADR = 683 , SYSZ_INS_ADTR = 684 , SYSZ_INS_ADTRA = 685 , SYSZ_INS_AE = 686 , SYSZ_INS_AER = 687 , SYSZ_INS_AGH = 688 , SYSZ_INS_AHHHR = 689 , SYSZ_INS_AHHLR = 690 , SYSZ_INS_ALGSI = 691 , SYSZ_INS_ALHHHR = 692 , SYSZ_INS_ALHHLR = 693 , SYSZ_INS_ALSI = 694 , SYSZ_INS_ALSIH = 695 , SYSZ_INS_ALSIHN = 696 , SYSZ_INS_AP = 697 , SYSZ_INS_AU = 698 , SYSZ_INS_AUR = 699 , SYSZ_INS_AW = 700 , SYSZ_INS_AWR = 701 , SYSZ_INS_AXR = 702 , SYSZ_INS_AXTR = 703 , SYSZ_INS_AXTRA = 704 , SYSZ_INS_B = 705 , SYSZ_INS_BAKR = 706 , SYSZ_INS_BAL = 707 , SYSZ_INS_BALR = 708 , SYSZ_INS_BAS = 709 , SYSZ_INS_BASSM = 710 , SYSZ_INS_BC = 711 , SYSZ_INS_BCT = 712 , SYSZ_INS_BCTG = 713 , SYSZ_INS_BCTGR = 714 , SYSZ_INS_BCTR = 715 , SYSZ_INS_BE = 716 , SYSZ_INS_BH = 717 , SYSZ_INS_BHE = 718 , SYSZ_INS_BI = 719 , SYSZ_INS_BIC = 720 , SYSZ_INS_BIE = 721 , SYSZ_INS_BIH = 722 , SYSZ_INS_BIHE = 723 , SYSZ_INS_BIL = 724 , SYSZ_INS_BILE = 725 , SYSZ_INS_BILH = 726 , SYSZ_INS_BIM = 727 , SYSZ_INS_BINE = 728 , SYSZ_INS_BINH = 729 , SYSZ_INS_BINHE = 730 , SYSZ_INS_BINL = 731 , SYSZ_INS_BINLE = 732 , SYSZ_INS_BINLH = 733 , SYSZ_INS_BINM = 734 , SYSZ_INS_BINO = 735 , SYSZ_INS_BINP = 736 , SYSZ_INS_BINZ = 737 , SYSZ_INS_BIO = 738 , SYSZ_INS_BIP = 739 , SYSZ_INS_BIZ = 740 , SYSZ_INS_BL = 741 , SYSZ_INS_BLE = 742 , SYSZ_INS_BLH = 743 , SYSZ_INS_BM = 744 , SYSZ_INS_BMR = 745 , SYSZ_INS_BNE = 746 , SYSZ_INS_BNH = 747 , SYSZ_INS_BNHE = 748 , SYSZ_INS_BNL = 749 , SYSZ_INS_BNLE = 750 , SYSZ_INS_BNLH = 751 , SYSZ_INS_BNM = 752 , SYSZ_INS_BNMR = 753 , SYSZ_INS_BNO = 754 , SYSZ_INS_BNP = 755 , SYSZ_INS_BNPR = 756 , SYSZ_INS_BNZ = 757 , SYSZ_INS_BNZR = 758 , SYSZ_INS_BO = 759 , SYSZ_INS_BP = 760 , SYSZ_INS_BPP = 761 , SYSZ_INS_BPR = 762 , SYSZ_INS_BPRP = 763 , SYSZ_INS_BRCTH = 764 , SYSZ_INS_BRXH = 765 , SYSZ_INS_BRXHG = 766 , SYSZ_INS_BRXLE = 767 , SYSZ_INS_BRXLG = 768 , SYSZ_INS_BSA = 769 , SYSZ_INS_BSG = 770 , SYSZ_INS_BSM = 771 , SYSZ_INS_BXH = 772 , SYSZ_INS_BXHG = 773 , SYSZ_INS_BXLE = 774 , SYSZ_INS_BXLEG = 775 , SYSZ_INS_BZ = 776 , SYSZ_INS_BZR = 777 , SYSZ_INS_CD = 778 , SYSZ_INS_CDFBRA = 779 , SYSZ_INS_CDFR = 780 , SYSZ_INS_CDFTR = 781 , SYSZ_INS_CDGBRA = 782 , SYSZ_INS_CDGR = 783 , SYSZ_INS_CDGTR = 784 , SYSZ_INS_CDGTRA = 785 , SYSZ_INS_CDLFTR = 786 , SYSZ_INS_CDLGTR = 787 , SYSZ_INS_CDPT = 788 , SYSZ_INS_CDR = 789 , SYSZ_INS_CDS = 790 , SYSZ_INS_CDSG = 791 , SYSZ_INS_CDSTR = 792 , SYSZ_INS_CDSY = 793 , SYSZ_INS_CDTR = 794 , SYSZ_INS_CDUTR = 795 , SYSZ_INS_CDZT = 796 , SYSZ_INS_CE = 797 , SYSZ_INS_CEDTR = 798 , SYSZ_INS_CEFBRA = 799 , SYSZ_INS_CEFR = 800 , SYSZ_INS_CEGBRA = 801 , SYSZ_INS_CEGR = 802 , SYSZ_INS_CER = 803 , SYSZ_INS_CEXTR = 804 , SYSZ_INS_CFC = 805 , SYSZ_INS_CFDBRA = 806 , SYSZ_INS_CFDR = 807 , SYSZ_INS_CFDTR = 808 , SYSZ_INS_CFEBRA = 809 , SYSZ_INS_CFER = 810 , SYSZ_INS_CFXBRA = 811 , SYSZ_INS_CFXR = 812 , SYSZ_INS_CFXTR = 813 , SYSZ_INS_CGDBRA = 814 , SYSZ_INS_CGDR = 815 , SYSZ_INS_CGDTR = 816 , SYSZ_INS_CGDTRA = 817 , SYSZ_INS_CGEBRA = 818 , SYSZ_INS_CGER = 819 , SYSZ_INS_CGIB = 820 , SYSZ_INS_CGIBE = 821 , SYSZ_INS_CGIBH = 822 , SYSZ_INS_CGIBHE = 823 , SYSZ_INS_CGIBL = 824 , SYSZ_INS_CGIBLE = 825 , SYSZ_INS_CGIBLH = 826 , SYSZ_INS_CGIBNE = 827 , SYSZ_INS_CGIBNH = 828 , SYSZ_INS_CGIBNHE = 829 , SYSZ_INS_CGIBNL = 830 , SYSZ_INS_CGIBNLE = 831 , SYSZ_INS_CGIBNLH = 832 , SYSZ_INS_CGIT = 833 , SYSZ_INS_CGITE = 834 , SYSZ_INS_CGITH = 835 , SYSZ_INS_CGITHE = 836 , SYSZ_INS_CGITL = 837 , SYSZ_INS_CGITLE = 838 , SYSZ_INS_CGITLH = 839 , SYSZ_INS_CGITNE = 840 , SYSZ_INS_CGITNH = 841 , SYSZ_INS_CGITNHE = 842 , SYSZ_INS_CGITNL = 843 , SYSZ_INS_CGITNLE = 844 , SYSZ_INS_CGITNLH = 845 , SYSZ_INS_CGRB = 846 , SYSZ_INS_CGRBE = 847 , SYSZ_INS_CGRBH = 848 , SYSZ_INS_CGRBHE = 849 , SYSZ_INS_CGRBL = 850 , SYSZ_INS_CGRBLE = 851 , SYSZ_INS_CGRBLH = 852 , SYSZ_INS_CGRBNE = 853 , SYSZ_INS_CGRBNH = 854 , SYSZ_INS_CGRBNHE = 855 , SYSZ_INS_CGRBNL = 856 , SYSZ_INS_CGRBNLE = 857 , SYSZ_INS_CGRBNLH = 858 , SYSZ_INS_CGRT = 859 , SYSZ_INS_CGRTE = 860 , SYSZ_INS_CGRTH = 861 , SYSZ_INS_CGRTHE = 862 , SYSZ_INS_CGRTL = 863 , SYSZ_INS_CGRTLE = 864 , SYSZ_INS_CGRTLH = 865 , SYSZ_INS_CGRTNE = 866 , SYSZ_INS_CGRTNH = 867 , SYSZ_INS_CGRTNHE = 868 , SYSZ_INS_CGRTNL = 869 , SYSZ_INS_CGRTNLE = 870 , SYSZ_INS_CGRTNLH = 871 , SYSZ_INS_CGXBRA = 872 , SYSZ_INS_CGXR = 873 , SYSZ_INS_CGXTR = 874 , SYSZ_INS_CGXTRA = 875 , SYSZ_INS_CHHR = 876 , SYSZ_INS_CHLR = 877 , SYSZ_INS_CIB = 878 , SYSZ_INS_CIBE = 879 , SYSZ_INS_CIBH = 880 , SYSZ_INS_CIBHE = 881 , SYSZ_INS_CIBL = 882 , SYSZ_INS_CIBLE = 883 , SYSZ_INS_CIBLH = 884 , SYSZ_INS_CIBNE = 885 , SYSZ_INS_CIBNH = 886 , SYSZ_INS_CIBNHE = 887 , SYSZ_INS_CIBNL = 888 , SYSZ_INS_CIBNLE = 889 , SYSZ_INS_CIBNLH = 890 , SYSZ_INS_CIT = 891 , SYSZ_INS_CITE = 892 , SYSZ_INS_CITH = 893 , SYSZ_INS_CITHE = 894 , SYSZ_INS_CITL = 895 , SYSZ_INS_CITLE = 896 , SYSZ_INS_CITLH = 897 , SYSZ_INS_CITNE = 898 , SYSZ_INS_CITNH = 899 , SYSZ_INS_CITNHE = 900 , SYSZ_INS_CITNL = 901 , SYSZ_INS_CITNLE = 902 , SYSZ_INS_CITNLH = 903 , SYSZ_INS_CKSM = 904 , SYSZ_INS_CLCL = 905 , SYSZ_INS_CLCLE = 906 , SYSZ_INS_CLCLU = 907 , SYSZ_INS_CLFDTR = 908 , SYSZ_INS_CLFIT = 909 , SYSZ_INS_CLFITE = 910 , SYSZ_INS_CLFITH = 911 , SYSZ_INS_CLFITHE = 912 , SYSZ_INS_CLFITL = 913 , SYSZ_INS_CLFITLE = 914 , SYSZ_INS_CLFITLH = 915 , SYSZ_INS_CLFITNE = 916 , SYSZ_INS_CLFITNH = 917 , SYSZ_INS_CLFITNHE = 918 , SYSZ_INS_CLFITNL = 919 , SYSZ_INS_CLFITNLE = 920 , SYSZ_INS_CLFITNLH = 921 , SYSZ_INS_CLFXTR = 922 , SYSZ_INS_CLGDTR = 923 , SYSZ_INS_CLGIB = 924 , SYSZ_INS_CLGIBE = 925 , SYSZ_INS_CLGIBH = 926 , SYSZ_INS_CLGIBHE = 927 , SYSZ_INS_CLGIBL = 928 , SYSZ_INS_CLGIBLE = 929 , SYSZ_INS_CLGIBLH = 930 , SYSZ_INS_CLGIBNE = 931 , SYSZ_INS_CLGIBNH = 932 , SYSZ_INS_CLGIBNHE = 933 , SYSZ_INS_CLGIBNL = 934 , SYSZ_INS_CLGIBNLE = 935 , SYSZ_INS_CLGIBNLH = 936 , SYSZ_INS_CLGIT = 937 , SYSZ_INS_CLGITE = 938 , SYSZ_INS_CLGITH = 939 , SYSZ_INS_CLGITHE = 940 , SYSZ_INS_CLGITL = 941 , SYSZ_INS_CLGITLE = 942 , SYSZ_INS_CLGITLH = 943 , SYSZ_INS_CLGITNE = 944 , SYSZ_INS_CLGITNH = 945 , SYSZ_INS_CLGITNHE = 946 , SYSZ_INS_CLGITNL = 947 , SYSZ_INS_CLGITNLE = 948 , SYSZ_INS_CLGITNLH = 949 , SYSZ_INS_CLGRB = 950 , SYSZ_INS_CLGRBE = 951 , SYSZ_INS_CLGRBH = 952 , SYSZ_INS_CLGRBHE = 953 , SYSZ_INS_CLGRBL = 954 , SYSZ_INS_CLGRBLE = 955 , SYSZ_INS_CLGRBLH = 956 , SYSZ_INS_CLGRBNE = 957 , SYSZ_INS_CLGRBNH = 958 , SYSZ_INS_CLGRBNHE = 959 , SYSZ_INS_CLGRBNL = 960 , SYSZ_INS_CLGRBNLE = 961 , SYSZ_INS_CLGRBNLH = 962 , SYSZ_INS_CLGRT = 963 , SYSZ_INS_CLGRTE = 964 , SYSZ_INS_CLGRTH = 965 , SYSZ_INS_CLGRTHE = 966 , SYSZ_INS_CLGRTL = 967 , SYSZ_INS_CLGRTLE = 968 , SYSZ_INS_CLGRTLH = 969 , SYSZ_INS_CLGRTNE = 970 , SYSZ_INS_CLGRTNH = 971 , SYSZ_INS_CLGRTNHE = 972 , SYSZ_INS_CLGRTNL = 973 , SYSZ_INS_CLGRTNLE = 974 , SYSZ_INS_CLGRTNLH = 975 , SYSZ_INS_CLGT = 976 , SYSZ_INS_CLGTE = 977 , SYSZ_INS_CLGTH = 978 , SYSZ_INS_CLGTHE = 979 , SYSZ_INS_CLGTL = 980 , SYSZ_INS_CLGTLE = 981 , SYSZ_INS_CLGTLH = 982 , SYSZ_INS_CLGTNE = 983 , SYSZ_INS_CLGTNH = 984 , SYSZ_INS_CLGTNHE = 985 , SYSZ_INS_CLGTNL = 986 , SYSZ_INS_CLGTNLE = 987 , SYSZ_INS_CLGTNLH = 988 , SYSZ_INS_CLGXTR = 989 , SYSZ_INS_CLHHR = 990 , SYSZ_INS_CLHLR = 991 , SYSZ_INS_CLIB = 992 , SYSZ_INS_CLIBE = 993 , SYSZ_INS_CLIBH = 994 , SYSZ_INS_CLIBHE = 995 , SYSZ_INS_CLIBL = 996 , SYSZ_INS_CLIBLE = 997 , SYSZ_INS_CLIBLH = 998 , SYSZ_INS_CLIBNE = 999 , SYSZ_INS_CLIBNH = 1000 , SYSZ_INS_CLIBNHE = 1001 , SYSZ_INS_CLIBNL = 1002 , SYSZ_INS_CLIBNLE = 1003 , SYSZ_INS_CLIBNLH = 1004 , SYSZ_INS_CLM = 1005 , SYSZ_INS_CLMH = 1006 , SYSZ_INS_CLMY = 1007 , SYSZ_INS_CLRB = 1008 , SYSZ_INS_CLRBE = 1009 , SYSZ_INS_CLRBH = 1010 , SYSZ_INS_CLRBHE = 1011 , SYSZ_INS_CLRBL = 1012 , SYSZ_INS_CLRBLE = 1013 , SYSZ_INS_CLRBLH = 1014 , SYSZ_INS_CLRBNE = 1015 , SYSZ_INS_CLRBNH = 1016 , SYSZ_INS_CLRBNHE = 1017 , SYSZ_INS_CLRBNL = 1018 , SYSZ_INS_CLRBNLE = 1019 , SYSZ_INS_CLRBNLH = 1020 , SYSZ_INS_CLRT = 1021 , SYSZ_INS_CLRTE = 1022 , SYSZ_INS_CLRTH = 1023 , SYSZ_INS_CLRTHE = 1024 , SYSZ_INS_CLRTL = 1025 , SYSZ_INS_CLRTLE = 1026 , SYSZ_INS_CLRTLH = 1027 , SYSZ_INS_CLRTNE = 1028 , SYSZ_INS_CLRTNH = 1029 , SYSZ_INS_CLRTNHE = 1030 , SYSZ_INS_CLRTNL = 1031 , SYSZ_INS_CLRTNLE = 1032 , SYSZ_INS_CLRTNLH = 1033 , SYSZ_INS_CLT = 1034 , SYSZ_INS_CLTE = 1035 , SYSZ_INS_CLTH = 1036 , SYSZ_INS_CLTHE = 1037 , SYSZ_INS_CLTL = 1038 , SYSZ_INS_CLTLE = 1039 , SYSZ_INS_CLTLH = 1040 , SYSZ_INS_CLTNE = 1041 , SYSZ_INS_CLTNH = 1042 , SYSZ_INS_CLTNHE = 1043 , SYSZ_INS_CLTNL = 1044 , SYSZ_INS_CLTNLE = 1045 , SYSZ_INS_CLTNLH = 1046 , SYSZ_INS_CMPSC = 1047 , SYSZ_INS_CP = 1048 , SYSZ_INS_CPDT = 1049 , SYSZ_INS_CPXT = 1050 , SYSZ_INS_CPYA = 1051 , SYSZ_INS_CRB = 1052 , SYSZ_INS_CRBE = 1053 , SYSZ_INS_CRBH = 1054 , SYSZ_INS_CRBHE = 1055 , SYSZ_INS_CRBL = 1056 , SYSZ_INS_CRBLE = 1057 , SYSZ_INS_CRBLH = 1058 , SYSZ_INS_CRBNE = 1059 , SYSZ_INS_CRBNH = 1060 , SYSZ_INS_CRBNHE = 1061 , SYSZ_INS_CRBNL = 1062 , SYSZ_INS_CRBNLE = 1063 , SYSZ_INS_CRBNLH = 1064 , SYSZ_INS_CRDTE = 1065 , SYSZ_INS_CRT = 1066 , SYSZ_INS_CRTE = 1067 , SYSZ_INS_CRTH = 1068 , SYSZ_INS_CRTHE = 1069 , SYSZ_INS_CRTL = 1070 , SYSZ_INS_CRTLE = 1071 , SYSZ_INS_CRTLH = 1072 , SYSZ_INS_CRTNE = 1073 , SYSZ_INS_CRTNH = 1074 , SYSZ_INS_CRTNHE = 1075 , SYSZ_INS_CRTNL = 1076 , SYSZ_INS_CRTNLE = 1077 , SYSZ_INS_CRTNLH = 1078 , SYSZ_INS_CSCH = 1079 , SYSZ_INS_CSDTR = 1080 , SYSZ_INS_CSP = 1081 , SYSZ_INS_CSPG = 1082 , SYSZ_INS_CSST = 1083 , SYSZ_INS_CSXTR = 1084 , SYSZ_INS_CU12 = 1085 , SYSZ_INS_CU14 = 1086 , SYSZ_INS_CU21 = 1087 , SYSZ_INS_CU24 = 1088 , SYSZ_INS_CU41 = 1089 , SYSZ_INS_CU42 = 1090 , SYSZ_INS_CUDTR = 1091 , SYSZ_INS_CUSE = 1092 , SYSZ_INS_CUTFU = 1093 , SYSZ_INS_CUUTF = 1094 , SYSZ_INS_CUXTR = 1095 , SYSZ_INS_CVB = 1096 , SYSZ_INS_CVBG = 1097 , SYSZ_INS_CVBY = 1098 , SYSZ_INS_CVD = 1099 , SYSZ_INS_CVDG = 1100 , SYSZ_INS_CVDY = 1101 , SYSZ_INS_CXFBRA = 1102 , SYSZ_INS_CXFR = 1103 , SYSZ_INS_CXFTR = 1104 , SYSZ_INS_CXGBRA = 1105 , SYSZ_INS_CXGR = 1106 , SYSZ_INS_CXGTR = 1107 , SYSZ_INS_CXGTRA = 1108 , SYSZ_INS_CXLFTR = 1109 , SYSZ_INS_CXLGTR = 1110 , SYSZ_INS_CXPT = 1111 , SYSZ_INS_CXR = 1112 , SYSZ_INS_CXSTR = 1113 , SYSZ_INS_CXTR = 1114 , SYSZ_INS_CXUTR = 1115 , SYSZ_INS_CXZT = 1116 , SYSZ_INS_CZDT = 1117 , SYSZ_INS_CZXT = 1118 , SYSZ_INS_D = 1119 , SYSZ_INS_DD = 1120 , SYSZ_INS_DDR = 1121 , SYSZ_INS_DDTR = 1122 , SYSZ_INS_DDTRA = 1123 , SYSZ_INS_DE = 1124 , SYSZ_INS_DER = 1125 , SYSZ_INS_DIAG = 1126 , SYSZ_INS_DIDBR = 1127 , SYSZ_INS_DIEBR = 1128 , SYSZ_INS_DP = 1129 , SYSZ_INS_DR = 1130 , SYSZ_INS_DXR = 1131 , SYSZ_INS_DXTR = 1132 , SYSZ_INS_DXTRA = 1133 , SYSZ_INS_ECAG = 1134 , SYSZ_INS_ECCTR = 1135 , SYSZ_INS_ECPGA = 1136 , SYSZ_INS_ECTG = 1137 , SYSZ_INS_ED = 1138 , SYSZ_INS_EDMK = 1139 , SYSZ_INS_EEDTR = 1140 , SYSZ_INS_EEXTR = 1141 , SYSZ_INS_EFPC = 1142 , SYSZ_INS_EPAIR = 1143 , SYSZ_INS_EPAR = 1144 , SYSZ_INS_EPCTR = 1145 , SYSZ_INS_EPSW = 1146 , SYSZ_INS_EREG = 1147 , SYSZ_INS_EREGG = 1148 , SYSZ_INS_ESAIR = 1149 , SYSZ_INS_ESAR = 1150 , SYSZ_INS_ESDTR = 1151 , SYSZ_INS_ESEA = 1152 , SYSZ_INS_ESTA = 1153 , SYSZ_INS_ESXTR = 1154 , SYSZ_INS_ETND = 1155 , SYSZ_INS_EX = 1156 , SYSZ_INS_EXRL = 1157 , SYSZ_INS_FIDR = 1158 , SYSZ_INS_FIDTR = 1159 , SYSZ_INS_FIER = 1160 , SYSZ_INS_FIXR = 1161 , SYSZ_INS_FIXTR = 1162 , SYSZ_INS_HDR = 1163 , SYSZ_INS_HER = 1164 , SYSZ_INS_HSCH = 1165 , SYSZ_INS_IAC = 1166 , SYSZ_INS_ICM = 1167 , SYSZ_INS_ICMH = 1168 , SYSZ_INS_ICMY = 1169 , SYSZ_INS_IDTE = 1170 , SYSZ_INS_IEDTR = 1171 , SYSZ_INS_IEXTR = 1172 , SYSZ_INS_IPK = 1173 , SYSZ_INS_IPTE = 1174 , SYSZ_INS_IRBM = 1175 , SYSZ_INS_ISKE = 1176 , SYSZ_INS_IVSK = 1177 , SYSZ_INS_JGM = 1178 , SYSZ_INS_JGNM = 1179 , SYSZ_INS_JGNP = 1180 , SYSZ_INS_JGNZ = 1181 , SYSZ_INS_JGP = 1182 , SYSZ_INS_JGZ = 1183 , SYSZ_INS_JM = 1184 , SYSZ_INS_JNM = 1185 , SYSZ_INS_JNP = 1186 , SYSZ_INS_JNZ = 1187 , SYSZ_INS_JP = 1188 , SYSZ_INS_JZ = 1189 , SYSZ_INS_KDB = 1190 , SYSZ_INS_KDBR = 1191 , SYSZ_INS_KDTR = 1192 , SYSZ_INS_KEB = 1193 , SYSZ_INS_KEBR = 1194 , SYSZ_INS_KIMD = 1195 , SYSZ_INS_KLMD = 1196 , SYSZ_INS_KM = 1197 , SYSZ_INS_KMA = 1198 , SYSZ_INS_KMAC = 1199 , SYSZ_INS_KMC = 1200 , SYSZ_INS_KMCTR = 1201 , SYSZ_INS_KMF = 1202 , SYSZ_INS_KMO = 1203 , SYSZ_INS_KXBR = 1204 , SYSZ_INS_KXTR = 1205 , SYSZ_INS_LAE = 1206 , SYSZ_INS_LAEY = 1207 , SYSZ_INS_LAM = 1208 , SYSZ_INS_LAMY = 1209 , SYSZ_INS_LASP = 1210 , SYSZ_INS_LAT = 1211 , SYSZ_INS_LCBB = 1212 , SYSZ_INS_LCCTL = 1213 , SYSZ_INS_LCDFR = 1214 , SYSZ_INS_LCDR = 1215 , SYSZ_INS_LCER = 1216 , SYSZ_INS_LCTL = 1217 , SYSZ_INS_LCTLG = 1218 , SYSZ_INS_LCXR = 1219 , SYSZ_INS_LDE = 1220 , SYSZ_INS_LDER = 1221 , SYSZ_INS_LDETR = 1222 , SYSZ_INS_LDXR = 1223 , SYSZ_INS_LDXTR = 1224 , SYSZ_INS_LEDR = 1225 , SYSZ_INS_LEDTR = 1226 , SYSZ_INS_LEXR = 1227 , SYSZ_INS_LFAS = 1228 , SYSZ_INS_LFHAT = 1229 , SYSZ_INS_LFPC = 1230 , SYSZ_INS_LGAT = 1231 , SYSZ_INS_LGG = 1232 , SYSZ_INS_LGSC = 1233 , SYSZ_INS_LLGFAT = 1234 , SYSZ_INS_LLGFSG = 1235 , SYSZ_INS_LLGT = 1236 , SYSZ_INS_LLGTAT = 1237 , SYSZ_INS_LLGTR = 1238 , SYSZ_INS_LLZRGF = 1239 , SYSZ_INS_LM = 1240 , SYSZ_INS_LMD = 1241 , SYSZ_INS_LMH = 1242 , SYSZ_INS_LMY = 1243 , SYSZ_INS_LNDFR = 1244 , SYSZ_INS_LNDR = 1245 , SYSZ_INS_LNER = 1246 , SYSZ_INS_LNXR = 1247 , SYSZ_INS_LOCFH = 1248 , SYSZ_INS_LOCFHE = 1249 , SYSZ_INS_LOCFHH = 1250 , SYSZ_INS_LOCFHHE = 1251 , SYSZ_INS_LOCFHL = 1252 , SYSZ_INS_LOCFHLE = 1253 , SYSZ_INS_LOCFHLH = 1254 , SYSZ_INS_LOCFHM = 1255 , SYSZ_INS_LOCFHNE = 1256 , SYSZ_INS_LOCFHNH = 1257 , SYSZ_INS_LOCFHNHE = 1258 , SYSZ_INS_LOCFHNL = 1259 , SYSZ_INS_LOCFHNLE = 1260 , SYSZ_INS_LOCFHNLH = 1261 , SYSZ_INS_LOCFHNM = 1262 , SYSZ_INS_LOCFHNO = 1263 , SYSZ_INS_LOCFHNP = 1264 , SYSZ_INS_LOCFHNZ = 1265 , SYSZ_INS_LOCFHO = 1266 , SYSZ_INS_LOCFHP = 1267 , SYSZ_INS_LOCFHR = 1268 , SYSZ_INS_LOCFHRE = 1269 , SYSZ_INS_LOCFHRH = 1270 , SYSZ_INS_LOCFHRHE = 1271 , SYSZ_INS_LOCFHRL = 1272 , SYSZ_INS_LOCFHRLE = 1273 , SYSZ_INS_LOCFHRLH = 1274 , SYSZ_INS_LOCFHRM = 1275 , SYSZ_INS_LOCFHRNE = 1276 , SYSZ_INS_LOCFHRNH = 1277 , SYSZ_INS_LOCFHRNHE = 1278 , SYSZ_INS_LOCFHRNL = 1279 , SYSZ_INS_LOCFHRNLE = 1280 , SYSZ_INS_LOCFHRNLH = 1281 , SYSZ_INS_LOCFHRNM = 1282 , SYSZ_INS_LOCFHRNO = 1283 , SYSZ_INS_LOCFHRNP = 1284 , SYSZ_INS_LOCFHRNZ = 1285 , SYSZ_INS_LOCFHRO = 1286 , SYSZ_INS_LOCFHRP = 1287 , SYSZ_INS_LOCFHRZ = 1288 , SYSZ_INS_LOCFHZ = 1289 , SYSZ_INS_LOCGHI = 1290 , SYSZ_INS_LOCGHIE = 1291 , SYSZ_INS_LOCGHIH = 1292 , SYSZ_INS_LOCGHIHE = 1293 , SYSZ_INS_LOCGHIL = 1294 , SYSZ_INS_LOCGHILE = 1295 , SYSZ_INS_LOCGHILH = 1296 , SYSZ_INS_LOCGHIM = 1297 , SYSZ_INS_LOCGHINE = 1298 , SYSZ_INS_LOCGHINH = 1299 , SYSZ_INS_LOCGHINHE = 1300 , SYSZ_INS_LOCGHINL = 1301 , SYSZ_INS_LOCGHINLE = 1302 , SYSZ_INS_LOCGHINLH = 1303 , SYSZ_INS_LOCGHINM = 1304 , SYSZ_INS_LOCGHINO = 1305 , SYSZ_INS_LOCGHINP = 1306 , SYSZ_INS_LOCGHINZ = 1307 , SYSZ_INS_LOCGHIO = 1308 , SYSZ_INS_LOCGHIP = 1309 , SYSZ_INS_LOCGHIZ = 1310 , SYSZ_INS_LOCGM = 1311 , SYSZ_INS_LOCGNM = 1312 , SYSZ_INS_LOCGNP = 1313 , SYSZ_INS_LOCGNZ = 1314 , SYSZ_INS_LOCGP = 1315 , SYSZ_INS_LOCGRM = 1316 , SYSZ_INS_LOCGRNM = 1317 , SYSZ_INS_LOCGRNP = 1318 , SYSZ_INS_LOCGRNZ = 1319 , SYSZ_INS_LOCGRP = 1320 , SYSZ_INS_LOCGRZ = 1321 , SYSZ_INS_LOCGZ = 1322 , SYSZ_INS_LOCHHI = 1323 , SYSZ_INS_LOCHHIE = 1324 , SYSZ_INS_LOCHHIH = 1325 , SYSZ_INS_LOCHHIHE = 1326 , SYSZ_INS_LOCHHIL = 1327 , SYSZ_INS_LOCHHILE = 1328 , SYSZ_INS_LOCHHILH = 1329 , SYSZ_INS_LOCHHIM = 1330 , SYSZ_INS_LOCHHINE = 1331 , SYSZ_INS_LOCHHINH = 1332 , SYSZ_INS_LOCHHINHE = 1333 , SYSZ_INS_LOCHHINL = 1334 , SYSZ_INS_LOCHHINLE = 1335 , SYSZ_INS_LOCHHINLH = 1336 , SYSZ_INS_LOCHHINM = 1337 , SYSZ_INS_LOCHHINO = 1338 , SYSZ_INS_LOCHHINP = 1339 , SYSZ_INS_LOCHHINZ = 1340 , SYSZ_INS_LOCHHIO = 1341 , SYSZ_INS_LOCHHIP = 1342 , SYSZ_INS_LOCHHIZ = 1343 , SYSZ_INS_LOCHI = 1344 , SYSZ_INS_LOCHIE = 1345 , SYSZ_INS_LOCHIH = 1346 , SYSZ_INS_LOCHIHE = 1347 , SYSZ_INS_LOCHIL = 1348 , SYSZ_INS_LOCHILE = 1349 , SYSZ_INS_LOCHILH = 1350 , SYSZ_INS_LOCHIM = 1351 , SYSZ_INS_LOCHINE = 1352 , SYSZ_INS_LOCHINH = 1353 , SYSZ_INS_LOCHINHE = 1354 , SYSZ_INS_LOCHINL = 1355 , SYSZ_INS_LOCHINLE = 1356 , SYSZ_INS_LOCHINLH = 1357 , SYSZ_INS_LOCHINM = 1358 , SYSZ_INS_LOCHINO = 1359 , SYSZ_INS_LOCHINP = 1360 , SYSZ_INS_LOCHINZ = 1361 , SYSZ_INS_LOCHIO = 1362 , SYSZ_INS_LOCHIP = 1363 , SYSZ_INS_LOCHIZ = 1364 , SYSZ_INS_LOCM = 1365 , SYSZ_INS_LOCNM = 1366 , SYSZ_INS_LOCNP = 1367 , SYSZ_INS_LOCNZ = 1368 , SYSZ_INS_LOCP = 1369 , SYSZ_INS_LOCRM = 1370 , SYSZ_INS_LOCRNM = 1371 , SYSZ_INS_LOCRNP = 1372 , SYSZ_INS_LOCRNZ = 1373 , SYSZ_INS_LOCRP = 1374 , SYSZ_INS_LOCRZ = 1375 , SYSZ_INS_LOCZ = 1376 , SYSZ_INS_LPCTL = 1377 , SYSZ_INS_LPD = 1378 , SYSZ_INS_LPDFR = 1379 , SYSZ_INS_LPDG = 1380 , SYSZ_INS_LPDR = 1381 , SYSZ_INS_LPER = 1382 , SYSZ_INS_LPP = 1383 , SYSZ_INS_LPQ = 1384 , SYSZ_INS_LPSW = 1385 , SYSZ_INS_LPSWE = 1386 , SYSZ_INS_LPTEA = 1387 , SYSZ_INS_LPXR = 1388 , SYSZ_INS_LRA = 1389 , SYSZ_INS_LRAG = 1390 , SYSZ_INS_LRAY = 1391 , SYSZ_INS_LRDR = 1392 , SYSZ_INS_LRER = 1393 , SYSZ_INS_LRVH = 1394 , SYSZ_INS_LSCTL = 1395 , SYSZ_INS_LTDR = 1396 , SYSZ_INS_LTDTR = 1397 , SYSZ_INS_LTER = 1398 , SYSZ_INS_LTXR = 1399 , SYSZ_INS_LTXTR = 1400 , SYSZ_INS_LURA = 1401 , SYSZ_INS_LURAG = 1402 , SYSZ_INS_LXD = 1403 , SYSZ_INS_LXDR = 1404 , SYSZ_INS_LXDTR = 1405 , SYSZ_INS_LXE = 1406 , SYSZ_INS_LXER = 1407 , SYSZ_INS_LZRF = 1408 , SYSZ_INS_LZRG = 1409 , SYSZ_INS_M = 1410 , SYSZ_INS_MAD = 1411 , SYSZ_INS_MADR = 1412 , SYSZ_INS_MAE = 1413 , SYSZ_INS_MAER = 1414 , SYSZ_INS_MAY = 1415 , SYSZ_INS_MAYH = 1416 , SYSZ_INS_MAYHR = 1417 , SYSZ_INS_MAYL = 1418 , SYSZ_INS_MAYLR = 1419 , SYSZ_INS_MAYR = 1420 , SYSZ_INS_MC = 1421 , SYSZ_INS_MD = 1422 , SYSZ_INS_MDE = 1423 , SYSZ_INS_MDER = 1424 , SYSZ_INS_MDR = 1425 , SYSZ_INS_MDTR = 1426 , SYSZ_INS_MDTRA = 1427 , SYSZ_INS_ME = 1428 , SYSZ_INS_MEE = 1429 , SYSZ_INS_MEER = 1430 , SYSZ_INS_MER = 1431 , SYSZ_INS_MFY = 1432 , SYSZ_INS_MG = 1433 , SYSZ_INS_MGH = 1434 , SYSZ_INS_MGRK = 1435 , SYSZ_INS_ML = 1436 , SYSZ_INS_MLR = 1437 , SYSZ_INS_MP = 1438 , SYSZ_INS_MR = 1439 , SYSZ_INS_MSC = 1440 , SYSZ_INS_MSCH = 1441 , SYSZ_INS_MSD = 1442 , SYSZ_INS_MSDR = 1443 , SYSZ_INS_MSE = 1444 , SYSZ_INS_MSER = 1445 , SYSZ_INS_MSGC = 1446 , SYSZ_INS_MSGRKC = 1447 , SYSZ_INS_MSRKC = 1448 , SYSZ_INS_MSTA = 1449 , SYSZ_INS_MVCDK = 1450 , SYSZ_INS_MVCIN = 1451 , SYSZ_INS_MVCK = 1452 , SYSZ_INS_MVCL = 1453 , SYSZ_INS_MVCLE = 1454 , SYSZ_INS_MVCLU = 1455 , SYSZ_INS_MVCOS = 1456 , SYSZ_INS_MVCP = 1457 , SYSZ_INS_MVCS = 1458 , SYSZ_INS_MVCSK = 1459 , SYSZ_INS_MVN = 1460 , SYSZ_INS_MVO = 1461 , SYSZ_INS_MVPG = 1462 , SYSZ_INS_MVZ = 1463 , SYSZ_INS_MXD = 1464 , SYSZ_INS_MXDR = 1465 , SYSZ_INS_MXR = 1466 , SYSZ_INS_MXTR = 1467 , SYSZ_INS_MXTRA = 1468 , SYSZ_INS_MY = 1469 , SYSZ_INS_MYH = 1470 , SYSZ_INS_MYHR = 1471 , SYSZ_INS_MYL = 1472 , SYSZ_INS_MYLR = 1473 , SYSZ_INS_MYR = 1474 , SYSZ_INS_NIAI = 1475 , SYSZ_INS_NTSTG = 1476 , SYSZ_INS_PACK = 1477 , SYSZ_INS_PALB = 1478 , SYSZ_INS_PC = 1479 , SYSZ_INS_PCC = 1480 , SYSZ_INS_PCKMO = 1481 , SYSZ_INS_PFMF = 1482 , SYSZ_INS_PFPO = 1483 , SYSZ_INS_PGIN = 1484 , SYSZ_INS_PGOUT = 1485 , SYSZ_INS_PKA = 1486 , SYSZ_INS_PKU = 1487 , SYSZ_INS_PLO = 1488 , SYSZ_INS_POPCNT = 1489 , SYSZ_INS_PPA = 1490 , SYSZ_INS_PPNO = 1491 , SYSZ_INS_PR = 1492 , SYSZ_INS_PRNO = 1493 , SYSZ_INS_PT = 1494 , SYSZ_INS_PTF = 1495 , SYSZ_INS_PTFF = 1496 , SYSZ_INS_PTI = 1497 , SYSZ_INS_PTLB = 1498 , SYSZ_INS_QADTR = 1499 , SYSZ_INS_QAXTR = 1500 , SYSZ_INS_QCTRI = 1501 , SYSZ_INS_QSI = 1502 , SYSZ_INS_RCHP = 1503 , SYSZ_INS_RISBGN = 1504 , SYSZ_INS_RP = 1505 , SYSZ_INS_RRBE = 1506 , SYSZ_INS_RRBM = 1507 , SYSZ_INS_RRDTR = 1508 , SYSZ_INS_RRXTR = 1509 , SYSZ_INS_RSCH = 1510 , SYSZ_INS_SAC = 1511 , SYSZ_INS_SACF = 1512 , SYSZ_INS_SAL = 1513 , SYSZ_INS_SAM24 = 1514 , SYSZ_INS_SAM31 = 1515 , SYSZ_INS_SAM64 = 1516 , SYSZ_INS_SAR = 1517 , SYSZ_INS_SCCTR = 1518 , SYSZ_INS_SCHM = 1519 , SYSZ_INS_SCK = 1520 , SYSZ_INS_SCKC = 1521 , SYSZ_INS_SCKPF = 1522 , SYSZ_INS_SD = 1523 , SYSZ_INS_SDR = 1524 , SYSZ_INS_SDTR = 1525 , SYSZ_INS_SDTRA = 1526 , SYSZ_INS_SE = 1527 , SYSZ_INS_SER = 1528 , SYSZ_INS_SFASR = 1529 , SYSZ_INS_SFPC = 1530 , SYSZ_INS_SGH = 1531 , SYSZ_INS_SHHHR = 1532 , SYSZ_INS_SHHLR = 1533 , SYSZ_INS_SIE = 1534 , SYSZ_INS_SIGA = 1535 , SYSZ_INS_SIGP = 1536 , SYSZ_INS_SLA = 1537 , SYSZ_INS_SLAG = 1538 , SYSZ_INS_SLAK = 1539 , SYSZ_INS_SLDA = 1540 , SYSZ_INS_SLDL = 1541 , SYSZ_INS_SLDT = 1542 , SYSZ_INS_SLHHHR = 1543 , SYSZ_INS_SLHHLR = 1544 , SYSZ_INS_SLXT = 1545 , SYSZ_INS_SP = 1546 , SYSZ_INS_SPCTR = 1547 , SYSZ_INS_SPKA = 1548 , SYSZ_INS_SPM = 1549 , SYSZ_INS_SPT = 1550 , SYSZ_INS_SPX = 1551 , SYSZ_INS_SQD = 1552 , SYSZ_INS_SQDR = 1553 , SYSZ_INS_SQE = 1554 , SYSZ_INS_SQER = 1555 , SYSZ_INS_SQXR = 1556 , SYSZ_INS_SRDA = 1557 , SYSZ_INS_SRDL = 1558 , SYSZ_INS_SRDT = 1559 , SYSZ_INS_SRNM = 1560 , SYSZ_INS_SRNMB = 1561 , SYSZ_INS_SRNMT = 1562 , SYSZ_INS_SRP = 1563 , SYSZ_INS_SRSTU = 1564 , SYSZ_INS_SRXT = 1565 , SYSZ_INS_SSAIR = 1566 , SYSZ_INS_SSAR = 1567 , SYSZ_INS_SSCH = 1568 , SYSZ_INS_SSKE = 1569 , SYSZ_INS_SSM = 1570 , SYSZ_INS_STAM = 1571 , SYSZ_INS_STAMY = 1572 , SYSZ_INS_STAP = 1573 , SYSZ_INS_STCK = 1574 , SYSZ_INS_STCKC = 1575 , SYSZ_INS_STCKE = 1576 , SYSZ_INS_STCKF = 1577 , SYSZ_INS_STCM = 1578 , SYSZ_INS_STCMH = 1579 , SYSZ_INS_STCMY = 1580 , SYSZ_INS_STCPS = 1581 , SYSZ_INS_STCRW = 1582 , SYSZ_INS_STCTG = 1583 , SYSZ_INS_STCTL = 1584 , SYSZ_INS_STFL = 1585 , SYSZ_INS_STFLE = 1586 , SYSZ_INS_STFPC = 1587 , SYSZ_INS_STGSC = 1588 , SYSZ_INS_STIDP = 1589 , SYSZ_INS_STM = 1590 , SYSZ_INS_STMH = 1591 , SYSZ_INS_STMY = 1592 , SYSZ_INS_STNSM = 1593 , SYSZ_INS_STOCFH = 1594 , SYSZ_INS_STOCFHE = 1595 , SYSZ_INS_STOCFHH = 1596 , SYSZ_INS_STOCFHHE = 1597 , SYSZ_INS_STOCFHL = 1598 , SYSZ_INS_STOCFHLE = 1599 , SYSZ_INS_STOCFHLH = 1600 , SYSZ_INS_STOCFHM = 1601 , SYSZ_INS_STOCFHNE = 1602 , SYSZ_INS_STOCFHNH = 1603 , SYSZ_INS_STOCFHNHE = 1604 , SYSZ_INS_STOCFHNL = 1605 , SYSZ_INS_STOCFHNLE = 1606 , SYSZ_INS_STOCFHNLH = 1607 , SYSZ_INS_STOCFHNM = 1608 , SYSZ_INS_STOCFHNO = 1609 , SYSZ_INS_STOCFHNP = 1610 , SYSZ_INS_STOCFHNZ = 1611 , SYSZ_INS_STOCFHO = 1612 , SYSZ_INS_STOCFHP = 1613 , SYSZ_INS_STOCFHZ = 1614 , SYSZ_INS_STOCGM = 1615 , SYSZ_INS_STOCGNM = 1616 , SYSZ_INS_STOCGNP = 1617 , SYSZ_INS_STOCGNZ = 1618 , SYSZ_INS_STOCGP = 1619 , SYSZ_INS_STOCGZ = 1620 , SYSZ_INS_STOCM = 1621 , SYSZ_INS_STOCNM = 1622 , SYSZ_INS_STOCNP = 1623 , SYSZ_INS_STOCNZ = 1624 , SYSZ_INS_STOCP = 1625 , SYSZ_INS_STOCZ = 1626 , SYSZ_INS_STOSM = 1627 , SYSZ_INS_STPQ = 1628 , SYSZ_INS_STPT = 1629 , SYSZ_INS_STPX = 1630 , SYSZ_INS_STRAG = 1631 , SYSZ_INS_STRVH = 1632 , SYSZ_INS_STSCH = 1633 , SYSZ_INS_STSI = 1634 , SYSZ_INS_STURA = 1635 , SYSZ_INS_STURG = 1636 , SYSZ_INS_SU = 1637 , SYSZ_INS_SUR = 1638 , SYSZ_INS_SVC = 1639 , SYSZ_INS_SW = 1640 , SYSZ_INS_SWR = 1641 , SYSZ_INS_SXR = 1642 , SYSZ_INS_SXTR = 1643 , SYSZ_INS_SXTRA = 1644 , SYSZ_INS_TABORT = 1645 , SYSZ_INS_TAM = 1646 , SYSZ_INS_TAR = 1647 , SYSZ_INS_TB = 1648 , SYSZ_INS_TBDR = 1649 , SYSZ_INS_TBEDR = 1650 , SYSZ_INS_TBEGIN = 1651 , SYSZ_INS_TBEGINC = 1652 , SYSZ_INS_TCDB = 1653 , SYSZ_INS_TCEB = 1654 , SYSZ_INS_TCXB = 1655 , SYSZ_INS_TDCDT = 1656 , SYSZ_INS_TDCET = 1657 , SYSZ_INS_TDCXT = 1658 , SYSZ_INS_TDGDT = 1659 , SYSZ_INS_TDGET = 1660 , SYSZ_INS_TDGXT = 1661 , SYSZ_INS_TEND = 1662 , SYSZ_INS_THDER = 1663 , SYSZ_INS_THDR = 1664 , SYSZ_INS_TP = 1665 , SYSZ_INS_TPI = 1666 , SYSZ_INS_TPROT = 1667 , SYSZ_INS_TR = 1668 , SYSZ_INS_TRACE = 1669 , SYSZ_INS_TRACG = 1670 , SYSZ_INS_TRAP2 = 1671 , SYSZ_INS_TRAP4 = 1672 , SYSZ_INS_TRE = 1673 , SYSZ_INS_TROO = 1674 , SYSZ_INS_TROT = 1675 , SYSZ_INS_TRT = 1676 , SYSZ_INS_TRTE = 1677 , SYSZ_INS_TRTO = 1678 , SYSZ_INS_TRTR = 1679 , SYSZ_INS_TRTRE = 1680 , SYSZ_INS_TRTT = 1681 , SYSZ_INS_TS = 1682 , SYSZ_INS_TSCH = 1683 , SYSZ_INS_UNPK = 1684 , SYSZ_INS_UNPKA = 1685 , SYSZ_INS_UNPKU = 1686 , SYSZ_INS_UPT = 1687 , SYSZ_INS_VA = 1688 , SYSZ_INS_VAB = 1689 , SYSZ_INS_VAC = 1690 , SYSZ_INS_VACC = 1691 , SYSZ_INS_VACCB = 1692 , SYSZ_INS_VACCC = 1693 , SYSZ_INS_VACCCQ = 1694 , SYSZ_INS_VACCF = 1695 , SYSZ_INS_VACCG = 1696 , SYSZ_INS_VACCH = 1697 , SYSZ_INS_VACCQ = 1698 , SYSZ_INS_VACQ = 1699 , SYSZ_INS_VAF = 1700 , SYSZ_INS_VAG = 1701 , SYSZ_INS_VAH = 1702 , SYSZ_INS_VAP = 1703 , SYSZ_INS_VAQ = 1704 , SYSZ_INS_VAVG = 1705 , SYSZ_INS_VAVGB = 1706 , SYSZ_INS_VAVGF = 1707 , SYSZ_INS_VAVGG = 1708 , SYSZ_INS_VAVGH = 1709 , SYSZ_INS_VAVGL = 1710 , SYSZ_INS_VAVGLB = 1711 , SYSZ_INS_VAVGLF = 1712 , SYSZ_INS_VAVGLG = 1713 , SYSZ_INS_VAVGLH = 1714 , SYSZ_INS_VBPERM = 1715 , SYSZ_INS_VCDG = 1716 , SYSZ_INS_VCDGB = 1717 , SYSZ_INS_VCDLG = 1718 , SYSZ_INS_VCDLGB = 1719 , SYSZ_INS_VCEQ = 1720 , SYSZ_INS_VCEQB = 1721 , SYSZ_INS_VCEQBS = 1722 , SYSZ_INS_VCEQF = 1723 , SYSZ_INS_VCEQFS = 1724 , SYSZ_INS_VCEQG = 1725 , SYSZ_INS_VCEQGS = 1726 , SYSZ_INS_VCEQH = 1727 , SYSZ_INS_VCEQHS = 1728 , SYSZ_INS_VCGD = 1729 , SYSZ_INS_VCGDB = 1730 , SYSZ_INS_VCH = 1731 , SYSZ_INS_VCHB = 1732 , SYSZ_INS_VCHBS = 1733 , SYSZ_INS_VCHF = 1734 , SYSZ_INS_VCHFS = 1735 , SYSZ_INS_VCHG = 1736 , SYSZ_INS_VCHGS = 1737 , SYSZ_INS_VCHH = 1738 , SYSZ_INS_VCHHS = 1739 , SYSZ_INS_VCHL = 1740 , SYSZ_INS_VCHLB = 1741 , SYSZ_INS_VCHLBS = 1742 , SYSZ_INS_VCHLF = 1743 , SYSZ_INS_VCHLFS = 1744 , SYSZ_INS_VCHLG = 1745 , SYSZ_INS_VCHLGS = 1746 , SYSZ_INS_VCHLH = 1747 , SYSZ_INS_VCHLHS = 1748 , SYSZ_INS_VCKSM = 1749 , SYSZ_INS_VCLGD = 1750 , SYSZ_INS_VCLGDB = 1751 , SYSZ_INS_VCLZ = 1752 , SYSZ_INS_VCLZB = 1753 , SYSZ_INS_VCLZF = 1754 , SYSZ_INS_VCLZG = 1755 , SYSZ_INS_VCLZH = 1756 , SYSZ_INS_VCP = 1757 , SYSZ_INS_VCTZ = 1758 , SYSZ_INS_VCTZB = 1759 , SYSZ_INS_VCTZF = 1760 , SYSZ_INS_VCTZG = 1761 , SYSZ_INS_VCTZH = 1762 , SYSZ_INS_VCVB = 1763 , SYSZ_INS_VCVBG = 1764 , SYSZ_INS_VCVD = 1765 , SYSZ_INS_VCVDG = 1766 , SYSZ_INS_VDP = 1767 , SYSZ_INS_VEC = 1768 , SYSZ_INS_VECB = 1769 , SYSZ_INS_VECF = 1770 , SYSZ_INS_VECG = 1771 , SYSZ_INS_VECH = 1772 , SYSZ_INS_VECL = 1773 , SYSZ_INS_VECLB = 1774 , SYSZ_INS_VECLF = 1775 , SYSZ_INS_VECLG = 1776 , SYSZ_INS_VECLH = 1777 , SYSZ_INS_VERIM = 1778 , SYSZ_INS_VERIMB = 1779 , SYSZ_INS_VERIMF = 1780 , SYSZ_INS_VERIMG = 1781 , SYSZ_INS_VERIMH = 1782 , SYSZ_INS_VERLL = 1783 , SYSZ_INS_VERLLB = 1784 , SYSZ_INS_VERLLF = 1785 , SYSZ_INS_VERLLG = 1786 , SYSZ_INS_VERLLH = 1787 , SYSZ_INS_VERLLV = 1788 , SYSZ_INS_VERLLVB = 1789 , SYSZ_INS_VERLLVF = 1790 , SYSZ_INS_VERLLVG = 1791 , SYSZ_INS_VERLLVH = 1792 , SYSZ_INS_VESL = 1793 , SYSZ_INS_VESLB = 1794 , SYSZ_INS_VESLF = 1795 , SYSZ_INS_VESLG = 1796 , SYSZ_INS_VESLH = 1797 , SYSZ_INS_VESLV = 1798 , SYSZ_INS_VESLVB = 1799 , SYSZ_INS_VESLVF = 1800 , SYSZ_INS_VESLVG = 1801 , SYSZ_INS_VESLVH = 1802 , SYSZ_INS_VESRA = 1803 , SYSZ_INS_VESRAB = 1804 , SYSZ_INS_VESRAF = 1805 , SYSZ_INS_VESRAG = 1806 , SYSZ_INS_VESRAH = 1807 , SYSZ_INS_VESRAV = 1808 , SYSZ_INS_VESRAVB = 1809 , SYSZ_INS_VESRAVF = 1810 , SYSZ_INS_VESRAVG = 1811 , SYSZ_INS_VESRAVH = 1812 , SYSZ_INS_VESRL = 1813 , SYSZ_INS_VESRLB = 1814 , SYSZ_INS_VESRLF = 1815 , SYSZ_INS_VESRLG = 1816 , SYSZ_INS_VESRLH = 1817 , SYSZ_INS_VESRLV = 1818 , SYSZ_INS_VESRLVB = 1819 , SYSZ_INS_VESRLVF = 1820 , SYSZ_INS_VESRLVG = 1821 , SYSZ_INS_VESRLVH = 1822 , SYSZ_INS_VFA = 1823 , SYSZ_INS_VFADB = 1824 , SYSZ_INS_VFAE = 1825 , SYSZ_INS_VFAEB = 1826 , SYSZ_INS_VFAEBS = 1827 , SYSZ_INS_VFAEF = 1828 , SYSZ_INS_VFAEFS = 1829 , SYSZ_INS_VFAEH = 1830 , SYSZ_INS_VFAEHS = 1831 , SYSZ_INS_VFAEZB = 1832 , SYSZ_INS_VFAEZBS = 1833 , SYSZ_INS_VFAEZF = 1834 , SYSZ_INS_VFAEZFS = 1835 , SYSZ_INS_VFAEZH = 1836 , SYSZ_INS_VFAEZHS = 1837 , SYSZ_INS_VFASB = 1838 , SYSZ_INS_VFCE = 1839 , SYSZ_INS_VFCEDB = 1840 , SYSZ_INS_VFCEDBS = 1841 , SYSZ_INS_VFCESB = 1842 , SYSZ_INS_VFCESBS = 1843 , SYSZ_INS_VFCH = 1844 , SYSZ_INS_VFCHDB = 1845 , SYSZ_INS_VFCHDBS = 1846 , SYSZ_INS_VFCHE = 1847 , SYSZ_INS_VFCHEDB = 1848 , SYSZ_INS_VFCHEDBS = 1849 , SYSZ_INS_VFCHESB = 1850 , SYSZ_INS_VFCHESBS = 1851 , SYSZ_INS_VFCHSB = 1852 , SYSZ_INS_VFCHSBS = 1853 , SYSZ_INS_VFD = 1854 , SYSZ_INS_VFDDB = 1855 , SYSZ_INS_VFDSB = 1856 , SYSZ_INS_VFEE = 1857 , SYSZ_INS_VFEEB = 1858 , SYSZ_INS_VFEEBS = 1859 , SYSZ_INS_VFEEF = 1860 , SYSZ_INS_VFEEFS = 1861 , SYSZ_INS_VFEEH = 1862 , SYSZ_INS_VFEEHS = 1863 , SYSZ_INS_VFEEZB = 1864 , SYSZ_INS_VFEEZBS = 1865 , SYSZ_INS_VFEEZF = 1866 , SYSZ_INS_VFEEZFS = 1867 , SYSZ_INS_VFEEZH = 1868 , SYSZ_INS_VFEEZHS = 1869 , SYSZ_INS_VFENE = 1870 , SYSZ_INS_VFENEB = 1871 , SYSZ_INS_VFENEBS = 1872 , SYSZ_INS_VFENEF = 1873 , SYSZ_INS_VFENEFS = 1874 , SYSZ_INS_VFENEH = 1875 , SYSZ_INS_VFENEHS = 1876 , SYSZ_INS_VFENEZB = 1877 , SYSZ_INS_VFENEZBS = 1878 , SYSZ_INS_VFENEZF = 1879 , SYSZ_INS_VFENEZFS = 1880 , SYSZ_INS_VFENEZH = 1881 , SYSZ_INS_VFENEZHS = 1882 , SYSZ_INS_VFI = 1883 , SYSZ_INS_VFIDB = 1884 , SYSZ_INS_VFISB = 1885 , SYSZ_INS_VFKEDB = 1886 , SYSZ_INS_VFKEDBS = 1887 , SYSZ_INS_VFKESB = 1888 , SYSZ_INS_VFKESBS = 1889 , SYSZ_INS_VFKHDB = 1890 , SYSZ_INS_VFKHDBS = 1891 , SYSZ_INS_VFKHEDB = 1892 , SYSZ_INS_VFKHEDBS = 1893 , SYSZ_INS_VFKHESB = 1894 , SYSZ_INS_VFKHESBS = 1895 , SYSZ_INS_VFKHSB = 1896 , SYSZ_INS_VFKHSBS = 1897 , SYSZ_INS_VFLCDB = 1898 , SYSZ_INS_VFLCSB = 1899 , SYSZ_INS_VFLL = 1900 , SYSZ_INS_VFLLS = 1901 , SYSZ_INS_VFLNDB = 1902 , SYSZ_INS_VFLNSB = 1903 , SYSZ_INS_VFLPDB = 1904 , SYSZ_INS_VFLPSB = 1905 , SYSZ_INS_VFLR = 1906 , SYSZ_INS_VFLRD = 1907 , SYSZ_INS_VFM = 1908 , SYSZ_INS_VFMA = 1909 , SYSZ_INS_VFMADB = 1910 , SYSZ_INS_VFMASB = 1911 , SYSZ_INS_VFMAX = 1912 , SYSZ_INS_VFMAXDB = 1913 , SYSZ_INS_VFMAXSB = 1914 , SYSZ_INS_VFMDB = 1915 , SYSZ_INS_VFMIN = 1916 , SYSZ_INS_VFMINDB = 1917 , SYSZ_INS_VFMINSB = 1918 , SYSZ_INS_VFMS = 1919 , SYSZ_INS_VFMSB = 1920 , SYSZ_INS_VFMSDB = 1921 , SYSZ_INS_VFMSSB = 1922 , SYSZ_INS_VFNMA = 1923 , SYSZ_INS_VFNMADB = 1924 , SYSZ_INS_VFNMASB = 1925 , SYSZ_INS_VFNMS = 1926 , SYSZ_INS_VFNMSDB = 1927 , SYSZ_INS_VFNMSSB = 1928 , SYSZ_INS_VFPSO = 1929 , SYSZ_INS_VFPSODB = 1930 , SYSZ_INS_VFPSOSB = 1931 , SYSZ_INS_VFS = 1932 , SYSZ_INS_VFSDB = 1933 , SYSZ_INS_VFSQ = 1934 , SYSZ_INS_VFSQDB = 1935 , SYSZ_INS_VFSQSB = 1936 , SYSZ_INS_VFSSB = 1937 , SYSZ_INS_VFTCI = 1938 , SYSZ_INS_VFTCIDB = 1939 , SYSZ_INS_VFTCISB = 1940 , SYSZ_INS_VGBM = 1941 , SYSZ_INS_VGEF = 1942 , SYSZ_INS_VGEG = 1943 , SYSZ_INS_VGFM = 1944 , SYSZ_INS_VGFMA = 1945 , SYSZ_INS_VGFMAB = 1946 , SYSZ_INS_VGFMAF = 1947 , SYSZ_INS_VGFMAG = 1948 , SYSZ_INS_VGFMAH = 1949 , SYSZ_INS_VGFMB = 1950 , SYSZ_INS_VGFMF = 1951 , SYSZ_INS_VGFMG = 1952 , SYSZ_INS_VGFMH = 1953 , SYSZ_INS_VGM = 1954 , SYSZ_INS_VGMB = 1955 , SYSZ_INS_VGMF = 1956 , SYSZ_INS_VGMG = 1957 , SYSZ_INS_VGMH = 1958 , SYSZ_INS_VISTR = 1959 , SYSZ_INS_VISTRB = 1960 , SYSZ_INS_VISTRBS = 1961 , SYSZ_INS_VISTRF = 1962 , SYSZ_INS_VISTRFS = 1963 , SYSZ_INS_VISTRH = 1964 , SYSZ_INS_VISTRHS = 1965 , SYSZ_INS_VL = 1966 , SYSZ_INS_VLBB = 1967 , SYSZ_INS_VLC = 1968 , SYSZ_INS_VLCB = 1969 , SYSZ_INS_VLCF = 1970 , SYSZ_INS_VLCG = 1971 , SYSZ_INS_VLCH = 1972 , SYSZ_INS_VLDE = 1973 , SYSZ_INS_VLDEB = 1974 , SYSZ_INS_VLEB = 1975 , SYSZ_INS_VLED = 1976 , SYSZ_INS_VLEDB = 1977 , SYSZ_INS_VLEF = 1978 , SYSZ_INS_VLEG = 1979 , SYSZ_INS_VLEH = 1980 , SYSZ_INS_VLEIB = 1981 , SYSZ_INS_VLEIF = 1982 , SYSZ_INS_VLEIG = 1983 , SYSZ_INS_VLEIH = 1984 , SYSZ_INS_VLGV = 1985 , SYSZ_INS_VLGVB = 1986 , SYSZ_INS_VLGVF = 1987 , SYSZ_INS_VLGVG = 1988 , SYSZ_INS_VLGVH = 1989 , SYSZ_INS_VLIP = 1990 , SYSZ_INS_VLL = 1991 , SYSZ_INS_VLLEZ = 1992 , SYSZ_INS_VLLEZB = 1993 , SYSZ_INS_VLLEZF = 1994 , SYSZ_INS_VLLEZG = 1995 , SYSZ_INS_VLLEZH = 1996 , SYSZ_INS_VLLEZLF = 1997 , SYSZ_INS_VLM = 1998 , SYSZ_INS_VLP = 1999 , SYSZ_INS_VLPB = 2000 , SYSZ_INS_VLPF = 2001 , SYSZ_INS_VLPG = 2002 , SYSZ_INS_VLPH = 2003 , SYSZ_INS_VLR = 2004 , SYSZ_INS_VLREP = 2005 , SYSZ_INS_VLREPB = 2006 , SYSZ_INS_VLREPF = 2007 , SYSZ_INS_VLREPG = 2008 , SYSZ_INS_VLREPH = 2009 , SYSZ_INS_VLRL = 2010 , SYSZ_INS_VLRLR = 2011 , SYSZ_INS_VLVG = 2012 , SYSZ_INS_VLVGB = 2013 , SYSZ_INS_VLVGF = 2014 , SYSZ_INS_VLVGG = 2015 , SYSZ_INS_VLVGH = 2016 , SYSZ_INS_VLVGP = 2017 , SYSZ_INS_VMAE = 2018 , SYSZ_INS_VMAEB = 2019 , SYSZ_INS_VMAEF = 2020 , SYSZ_INS_VMAEH = 2021 , SYSZ_INS_VMAH = 2022 , SYSZ_INS_VMAHB = 2023 , SYSZ_INS_VMAHF = 2024 , SYSZ_INS_VMAHH = 2025 , SYSZ_INS_VMAL = 2026 , SYSZ_INS_VMALB = 2027 , SYSZ_INS_VMALE = 2028 , SYSZ_INS_VMALEB = 2029 , SYSZ_INS_VMALEF = 2030 , SYSZ_INS_VMALEH = 2031 , SYSZ_INS_VMALF = 2032 , SYSZ_INS_VMALH = 2033 , SYSZ_INS_VMALHB = 2034 , SYSZ_INS_VMALHF = 2035 , SYSZ_INS_VMALHH = 2036 , SYSZ_INS_VMALHW = 2037 , SYSZ_INS_VMALO = 2038 , SYSZ_INS_VMALOB = 2039 , SYSZ_INS_VMALOF = 2040 , SYSZ_INS_VMALOH = 2041 , SYSZ_INS_VMAO = 2042 , SYSZ_INS_VMAOB = 2043 , SYSZ_INS_VMAOF = 2044 , SYSZ_INS_VMAOH = 2045 , SYSZ_INS_VME = 2046 , SYSZ_INS_VMEB = 2047 , SYSZ_INS_VMEF = 2048 , SYSZ_INS_VMEH = 2049 , SYSZ_INS_VMH = 2050 , SYSZ_INS_VMHB = 2051 , SYSZ_INS_VMHF = 2052 , SYSZ_INS_VMHH = 2053 , SYSZ_INS_VML = 2054 , SYSZ_INS_VMLB = 2055 , SYSZ_INS_VMLE = 2056 , SYSZ_INS_VMLEB = 2057 , SYSZ_INS_VMLEF = 2058 , SYSZ_INS_VMLEH = 2059 , SYSZ_INS_VMLF = 2060 , SYSZ_INS_VMLH = 2061 , SYSZ_INS_VMLHB = 2062 , SYSZ_INS_VMLHF = 2063 , SYSZ_INS_VMLHH = 2064 , SYSZ_INS_VMLHW = 2065 , SYSZ_INS_VMLO = 2066 , SYSZ_INS_VMLOB = 2067 , SYSZ_INS_VMLOF = 2068 , SYSZ_INS_VMLOH = 2069 , SYSZ_INS_VMN = 2070 , SYSZ_INS_VMNB = 2071 , SYSZ_INS_VMNF = 2072 , SYSZ_INS_VMNG = 2073 , SYSZ_INS_VMNH = 2074 , SYSZ_INS_VMNL = 2075 , SYSZ_INS_VMNLB = 2076 , SYSZ_INS_VMNLF = 2077 , SYSZ_INS_VMNLG = 2078 , SYSZ_INS_VMNLH = 2079 , SYSZ_INS_VMO = 2080 , SYSZ_INS_VMOB = 2081 , SYSZ_INS_VMOF = 2082 , SYSZ_INS_VMOH = 2083 , SYSZ_INS_VMP = 2084 , SYSZ_INS_VMRH = 2085 , SYSZ_INS_VMRHB = 2086 , SYSZ_INS_VMRHF = 2087 , SYSZ_INS_VMRHG = 2088 , SYSZ_INS_VMRHH = 2089 , SYSZ_INS_VMRL = 2090 , SYSZ_INS_VMRLB = 2091 , SYSZ_INS_VMRLF = 2092 , SYSZ_INS_VMRLG = 2093 , SYSZ_INS_VMRLH = 2094 , SYSZ_INS_VMSL = 2095 , SYSZ_INS_VMSLG = 2096 , SYSZ_INS_VMSP = 2097 , SYSZ_INS_VMX = 2098 , SYSZ_INS_VMXB = 2099 , SYSZ_INS_VMXF = 2100 , SYSZ_INS_VMXG = 2101 , SYSZ_INS_VMXH = 2102 , SYSZ_INS_VMXL = 2103 , SYSZ_INS_VMXLB = 2104 , SYSZ_INS_VMXLF = 2105 , SYSZ_INS_VMXLG = 2106 , SYSZ_INS_VMXLH = 2107 , SYSZ_INS_VN = 2108 , SYSZ_INS_VNC = 2109 , SYSZ_INS_VNN = 2110 , SYSZ_INS_VNO = 2111 , SYSZ_INS_VNX = 2112 , SYSZ_INS_VO = 2113 , SYSZ_INS_VOC = 2114 , SYSZ_INS_VONE = 2115 , SYSZ_INS_VPDI = 2116 , SYSZ_INS_VPERM = 2117 , SYSZ_INS_VPK = 2118 , SYSZ_INS_VPKF = 2119 , SYSZ_INS_VPKG = 2120 , SYSZ_INS_VPKH = 2121 , SYSZ_INS_VPKLS = 2122 , SYSZ_INS_VPKLSF = 2123 , SYSZ_INS_VPKLSFS = 2124 , SYSZ_INS_VPKLSG = 2125 , SYSZ_INS_VPKLSGS = 2126 , SYSZ_INS_VPKLSH = 2127 , SYSZ_INS_VPKLSHS = 2128 , SYSZ_INS_VPKS = 2129 , SYSZ_INS_VPKSF = 2130 , SYSZ_INS_VPKSFS = 2131 , SYSZ_INS_VPKSG = 2132 , SYSZ_INS_VPKSGS = 2133 , SYSZ_INS_VPKSH = 2134 , SYSZ_INS_VPKSHS = 2135 , SYSZ_INS_VPKZ = 2136 , SYSZ_INS_VPOPCT = 2137 , SYSZ_INS_VPOPCTB = 2138 , SYSZ_INS_VPOPCTF = 2139 , SYSZ_INS_VPOPCTG = 2140 , SYSZ_INS_VPOPCTH = 2141 , SYSZ_INS_VPSOP = 2142 , SYSZ_INS_VREP = 2143 , SYSZ_INS_VREPB = 2144 , SYSZ_INS_VREPF = 2145 , SYSZ_INS_VREPG = 2146 , SYSZ_INS_VREPH = 2147 , SYSZ_INS_VREPI = 2148 , SYSZ_INS_VREPIB = 2149 , SYSZ_INS_VREPIF = 2150 , SYSZ_INS_VREPIG = 2151 , SYSZ_INS_VREPIH = 2152 , SYSZ_INS_VRP = 2153 , SYSZ_INS_VS = 2154 , SYSZ_INS_VSB = 2155 , SYSZ_INS_VSBCBI = 2156 , SYSZ_INS_VSBCBIQ = 2157 , SYSZ_INS_VSBI = 2158 , SYSZ_INS_VSBIQ = 2159 , SYSZ_INS_VSCBI = 2160 , SYSZ_INS_VSCBIB = 2161 , SYSZ_INS_VSCBIF = 2162 , SYSZ_INS_VSCBIG = 2163 , SYSZ_INS_VSCBIH = 2164 , SYSZ_INS_VSCBIQ = 2165 , SYSZ_INS_VSCEF = 2166 , SYSZ_INS_VSCEG = 2167 , SYSZ_INS_VSDP = 2168 , SYSZ_INS_VSEG = 2169 , SYSZ_INS_VSEGB = 2170 , SYSZ_INS_VSEGF = 2171 , SYSZ_INS_VSEGH = 2172 , SYSZ_INS_VSEL = 2173 , SYSZ_INS_VSF = 2174 , SYSZ_INS_VSG = 2175 , SYSZ_INS_VSH = 2176 , SYSZ_INS_VSL = 2177 , SYSZ_INS_VSLB = 2178 , SYSZ_INS_VSLDB = 2179 , SYSZ_INS_VSP = 2180 , SYSZ_INS_VSQ = 2181 , SYSZ_INS_VSRA = 2182 , SYSZ_INS_VSRAB = 2183 , SYSZ_INS_VSRL = 2184 , SYSZ_INS_VSRLB = 2185 , SYSZ_INS_VSRP = 2186 , SYSZ_INS_VST = 2187 , SYSZ_INS_VSTEB = 2188 , SYSZ_INS_VSTEF = 2189 , SYSZ_INS_VSTEG = 2190 , SYSZ_INS_VSTEH = 2191 , SYSZ_INS_VSTL = 2192 , SYSZ_INS_VSTM = 2193 , SYSZ_INS_VSTRC = 2194 , SYSZ_INS_VSTRCB = 2195 , SYSZ_INS_VSTRCBS = 2196 , SYSZ_INS_VSTRCF = 2197 , SYSZ_INS_VSTRCFS = 2198 , SYSZ_INS_VSTRCH = 2199 , SYSZ_INS_VSTRCHS = 2200 , SYSZ_INS_VSTRCZB = 2201 , SYSZ_INS_VSTRCZBS = 2202 , SYSZ_INS_VSTRCZF = 2203 , SYSZ_INS_VSTRCZFS = 2204 , SYSZ_INS_VSTRCZH = 2205 , SYSZ_INS_VSTRCZHS = 2206 , SYSZ_INS_VSTRL = 2207 , SYSZ_INS_VSTRLR = 2208 , SYSZ_INS_VSUM = 2209 , SYSZ_INS_VSUMB = 2210 , SYSZ_INS_VSUMG = 2211 , SYSZ_INS_VSUMGF = 2212 , SYSZ_INS_VSUMGH = 2213 , SYSZ_INS_VSUMH = 2214 , SYSZ_INS_VSUMQ = 2215 , SYSZ_INS_VSUMQF = 2216 , SYSZ_INS_VSUMQG = 2217 , SYSZ_INS_VTM = 2218 , SYSZ_INS_VTP = 2219 , SYSZ_INS_VUPH = 2220 , SYSZ_INS_VUPHB = 2221 , SYSZ_INS_VUPHF = 2222 , SYSZ_INS_VUPHH = 2223 , SYSZ_INS_VUPKZ = 2224 , SYSZ_INS_VUPL = 2225 , SYSZ_INS_VUPLB = 2226 , SYSZ_INS_VUPLF = 2227 , SYSZ_INS_VUPLH = 2228 , SYSZ_INS_VUPLHB = 2229 , SYSZ_INS_VUPLHF = 2230 , SYSZ_INS_VUPLHH = 2231 , SYSZ_INS_VUPLHW = 2232 , SYSZ_INS_VUPLL = 2233 , SYSZ_INS_VUPLLB = 2234 , SYSZ_INS_VUPLLF = 2235 , SYSZ_INS_VUPLLH = 2236 , SYSZ_INS_VX = 2237 , SYSZ_INS_VZERO = 2238 , SYSZ_INS_WCDGB = 2239 , SYSZ_INS_WCDLGB = 2240 , SYSZ_INS_WCGDB = 2241 , SYSZ_INS_WCLGDB = 2242 , SYSZ_INS_WFADB = 2243 , SYSZ_INS_WFASB = 2244 , SYSZ_INS_WFAXB = 2245 , SYSZ_INS_WFC = 2246 , SYSZ_INS_WFCDB = 2247 , SYSZ_INS_WFCEDB = 2248 , SYSZ_INS_WFCEDBS = 2249 , SYSZ_INS_WFCESB = 2250 , SYSZ_INS_WFCESBS = 2251 , SYSZ_INS_WFCEXB = 2252 , SYSZ_INS_WFCEXBS = 2253 , SYSZ_INS_WFCHDB = 2254 , SYSZ_INS_WFCHDBS = 2255 , SYSZ_INS_WFCHEDB = 2256 , SYSZ_INS_WFCHEDBS = 2257 , SYSZ_INS_WFCHESB = 2258 , SYSZ_INS_WFCHESBS = 2259 , SYSZ_INS_WFCHEXB = 2260 , SYSZ_INS_WFCHEXBS = 2261 , SYSZ_INS_WFCHSB = 2262 , SYSZ_INS_WFCHSBS = 2263 , SYSZ_INS_WFCHXB = 2264 , SYSZ_INS_WFCHXBS = 2265 , SYSZ_INS_WFCSB = 2266 , SYSZ_INS_WFCXB = 2267 , SYSZ_INS_WFDDB = 2268 , SYSZ_INS_WFDSB = 2269 , SYSZ_INS_WFDXB = 2270 , SYSZ_INS_WFIDB = 2271 , SYSZ_INS_WFISB = 2272 , SYSZ_INS_WFIXB = 2273 , SYSZ_INS_WFK = 2274 , SYSZ_INS_WFKDB = 2275 , SYSZ_INS_WFKEDB = 2276 , SYSZ_INS_WFKEDBS = 2277 , SYSZ_INS_WFKESB = 2278 , SYSZ_INS_WFKESBS = 2279 , SYSZ_INS_WFKEXB = 2280 , SYSZ_INS_WFKEXBS = 2281 , SYSZ_INS_WFKHDB = 2282 , SYSZ_INS_WFKHDBS = 2283 , SYSZ_INS_WFKHEDB = 2284 , SYSZ_INS_WFKHEDBS = 2285 , SYSZ_INS_WFKHESB = 2286 , SYSZ_INS_WFKHESBS = 2287 , SYSZ_INS_WFKHEXB = 2288 , SYSZ_INS_WFKHEXBS = 2289 , SYSZ_INS_WFKHSB = 2290 , SYSZ_INS_WFKHSBS = 2291 , SYSZ_INS_WFKHXB = 2292 , SYSZ_INS_WFKHXBS = 2293 , SYSZ_INS_WFKSB = 2294 , SYSZ_INS_WFKXB = 2295 , SYSZ_INS_WFLCDB = 2296 , SYSZ_INS_WFLCSB = 2297 , SYSZ_INS_WFLCXB = 2298 , SYSZ_INS_WFLLD = 2299 , SYSZ_INS_WFLLS = 2300 , SYSZ_INS_WFLNDB = 2301 , SYSZ_INS_WFLNSB = 2302 , SYSZ_INS_WFLNXB = 2303 , SYSZ_INS_WFLPDB = 2304 , SYSZ_INS_WFLPSB = 2305 , SYSZ_INS_WFLPXB = 2306 , SYSZ_INS_WFLRD = 2307 , SYSZ_INS_WFLRX = 2308 , SYSZ_INS_WFMADB = 2309 , SYSZ_INS_WFMASB = 2310 , SYSZ_INS_WFMAXB = 2311 , SYSZ_INS_WFMAXDB = 2312 , SYSZ_INS_WFMAXSB = 2313 , SYSZ_INS_WFMAXXB = 2314 , SYSZ_INS_WFMDB = 2315 , SYSZ_INS_WFMINDB = 2316 , SYSZ_INS_WFMINSB = 2317 , SYSZ_INS_WFMINXB = 2318 , SYSZ_INS_WFMSB = 2319 , SYSZ_INS_WFMSDB = 2320 , SYSZ_INS_WFMSSB = 2321 , SYSZ_INS_WFMSXB = 2322 , SYSZ_INS_WFMXB = 2323 , SYSZ_INS_WFNMADB = 2324 , SYSZ_INS_WFNMASB = 2325 , SYSZ_INS_WFNMAXB = 2326 , SYSZ_INS_WFNMSDB = 2327 , SYSZ_INS_WFNMSSB = 2328 , SYSZ_INS_WFNMSXB = 2329 , SYSZ_INS_WFPSODB = 2330 , SYSZ_INS_WFPSOSB = 2331 , SYSZ_INS_WFPSOXB = 2332 , SYSZ_INS_WFSDB = 2333 , SYSZ_INS_WFSQDB = 2334 , SYSZ_INS_WFSQSB = 2335 , SYSZ_INS_WFSQXB = 2336 , SYSZ_INS_WFSSB = 2337 , SYSZ_INS_WFSXB = 2338 , SYSZ_INS_WFTCIDB = 2339 , SYSZ_INS_WFTCISB = 2340 , SYSZ_INS_WFTCIXB = 2341 , SYSZ_INS_WLDEB = 2342 , SYSZ_INS_WLEDB = 2343 , SYSZ_INS_XSCH = 2344 , SYSZ_INS_ZAP = 2345 , SYSZ_INS_ENDING = 2346 , } # [repr (u32)] # [doc = " Group of SystemZ instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sysz_insn_group { # [doc = "< = CS_GRP_INVALID"] SYSZ_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SYSZ_GRP_JUMP = 1 , SYSZ_GRP_DISTINCTOPS = 128 , SYSZ_GRP_FPEXTENSION = 129 , SYSZ_GRP_HIGHWORD = 130 , SYSZ_GRP_INTERLOCKEDACCESS1 = 131 , SYSZ_GRP_LOADSTOREONCOND = 132 , SYSZ_GRP_DFPPACKEDCONVERSION = 133 , SYSZ_GRP_DFPZONEDCONVERSION = 134 , SYSZ_GRP_ENHANCEDDAT2 = 135 , SYSZ_GRP_EXECUTIONHINT = 136 , SYSZ_GRP_GUARDEDSTORAGE = 137 , SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 , SYSZ_GRP_LOADANDTRAP = 139 , SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 , SYSZ_GRP_LOADSTOREONCOND2 = 141 , SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 , SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 , SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 , SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 , SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 , SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 , SYSZ_GRP_NOVECTOR = 149 , SYSZ_GRP_POPULATIONCOUNT = 150 , SYSZ_GRP_PROCESSORASSIST = 151 , SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 , SYSZ_GRP_TRANSACTIONALEXECUTION = 153 , SYSZ_GRP_VECTOR = 154 , SYSZ_GRP_VECTORENHANCEMENTS1 = 155 , SYSZ_GRP_VECTORPACKEDDECIMAL = 156 , SYSZ_GRP_ENDING = 157 , } # [repr (u32)] # [doc = " X86 registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_reg { X86_REG_INVALID = 0 , X86_REG_AH = 1 , X86_REG_AL = 2 , X86_REG_AX = 3 , X86_REG_BH = 4 , X86_REG_BL = 5 , X86_REG_BP = 6 , X86_REG_BPL = 7 , X86_REG_BX = 8 , X86_REG_CH = 9 , X86_REG_CL = 10 , X86_REG_CS = 11 , X86_REG_CX = 12 , X86_REG_DH = 13 , X86_REG_DI = 14 , X86_REG_DIL = 15 , X86_REG_DL = 16 , X86_REG_DS = 17 , X86_REG_DX = 18 , X86_REG_EAX = 19 , X86_REG_EBP = 20 , X86_REG_EBX = 21 , X86_REG_ECX = 22 , X86_REG_EDI = 23 , X86_REG_EDX = 24 , X86_REG_EFLAGS = 25 , X86_REG_EIP = 26 , X86_REG_EIZ = 27 , X86_REG_ES = 28 , X86_REG_ESI = 29 , X86_REG_ESP = 30 , X86_REG_FPSW = 31 , X86_REG_FS = 32 , X86_REG_GS = 33 , X86_REG_IP = 34 , X86_REG_RAX = 35 , X86_REG_RBP = 36 , X86_REG_RBX = 37 , X86_REG_RCX = 38 , X86_REG_RDI = 39 , X86_REG_RDX = 40 , X86_REG_RIP = 41 , X86_REG_RIZ = 42 , X86_REG_RSI = 43 , X86_REG_RSP = 44 , X86_REG_SI = 45 , X86_REG_SIL = 46 , X86_REG_SP = 47 , X86_REG_SPL = 48 , X86_REG_SS = 49 , X86_REG_CR0 = 50 , X86_REG_CR1 = 51 , X86_REG_CR2 = 52 , X86_REG_CR3 = 53 , X86_REG_CR4 = 54 , X86_REG_CR5 = 55 , X86_REG_CR6 = 56 , X86_REG_CR7 = 57 , X86_REG_CR8 = 58 , X86_REG_CR9 = 59 , X86_REG_CR10 = 60 , X86_REG_CR11 = 61 , X86_REG_CR12 = 62 , X86_REG_CR13 = 63 , X86_REG_CR14 = 64 , X86_REG_CR15 = 65 , X86_REG_DR0 = 66 , X86_REG_DR1 = 67 , X86_REG_DR2 = 68 , X86_REG_DR3 = 69 , X86_REG_DR4 = 70 , X86_REG_DR5 = 71 , X86_REG_DR6 = 72 , X86_REG_DR7 = 73 , X86_REG_DR8 = 74 , X86_REG_DR9 = 75 , X86_REG_DR10 = 76 , X86_REG_DR11 = 77 , X86_REG_DR12 = 78 , X86_REG_DR13 = 79 , X86_REG_DR14 = 80 , X86_REG_DR15 = 81 , X86_REG_FP0 = 82 , X86_REG_FP1 = 83 , X86_REG_FP2 = 84 , X86_REG_FP3 = 85 , X86_REG_FP4 = 86 , X86_REG_FP5 = 87 , X86_REG_FP6 = 88 , X86_REG_FP7 = 89 , X86_REG_K0 = 90 , X86_REG_K1 = 91 , X86_REG_K2 = 92 , X86_REG_K3 = 93 , X86_REG_K4 = 94 , X86_REG_K5 = 95 , X86_REG_K6 = 96 , X86_REG_K7 = 97 , X86_REG_MM0 = 98 , X86_REG_MM1 = 99 , X86_REG_MM2 = 100 , X86_REG_MM3 = 101 , X86_REG_MM4 = 102 , X86_REG_MM5 = 103 , X86_REG_MM6 = 104 , X86_REG_MM7 = 105 , X86_REG_R8 = 106 , X86_REG_R9 = 107 , X86_REG_R10 = 108 , X86_REG_R11 = 109 , X86_REG_R12 = 110 , X86_REG_R13 = 111 , X86_REG_R14 = 112 , X86_REG_R15 = 113 , X86_REG_ST0 = 114 , X86_REG_ST1 = 115 , X86_REG_ST2 = 116 , X86_REG_ST3 = 117 , X86_REG_ST4 = 118 , X86_REG_ST5 = 119 , X86_REG_ST6 = 120 , X86_REG_ST7 = 121 , X86_REG_XMM0 = 122 , X86_REG_XMM1 = 123 , X86_REG_XMM2 = 124 , X86_REG_XMM3 = 125 , X86_REG_XMM4 = 126 , X86_REG_XMM5 = 127 , X86_REG_XMM6 = 128 , X86_REG_XMM7 = 129 , X86_REG_XMM8 = 130 , X86_REG_XMM9 = 131 , X86_REG_XMM10 = 132 , X86_REG_XMM11 = 133 , X86_REG_XMM12 = 134 , X86_REG_XMM13 = 135 , X86_REG_XMM14 = 136 , X86_REG_XMM15 = 137 , X86_REG_XMM16 = 138 , X86_REG_XMM17 = 139 , X86_REG_XMM18 = 140 , X86_REG_XMM19 = 141 , X86_REG_XMM20 = 142 , X86_REG_XMM21 = 143 , X86_REG_XMM22 = 144 , X86_REG_XMM23 = 145 , X86_REG_XMM24 = 146 , X86_REG_XMM25 = 147 , X86_REG_XMM26 = 148 , X86_REG_XMM27 = 149 , X86_REG_XMM28 = 150 , X86_REG_XMM29 = 151 , X86_REG_XMM30 = 152 , X86_REG_XMM31 = 153 , X86_REG_YMM0 = 154 , X86_REG_YMM1 = 155 , X86_REG_YMM2 = 156 , X86_REG_YMM3 = 157 , X86_REG_YMM4 = 158 , X86_REG_YMM5 = 159 , X86_REG_YMM6 = 160 , X86_REG_YMM7 = 161 , X86_REG_YMM8 = 162 , X86_REG_YMM9 = 163 , X86_REG_YMM10 = 164 , X86_REG_YMM11 = 165 , X86_REG_YMM12 = 166 , X86_REG_YMM13 = 167 , X86_REG_YMM14 = 168 , X86_REG_YMM15 = 169 , X86_REG_YMM16 = 170 , X86_REG_YMM17 = 171 , X86_REG_YMM18 = 172 , X86_REG_YMM19 = 173 , X86_REG_YMM20 = 174 , X86_REG_YMM21 = 175 , X86_REG_YMM22 = 176 , X86_REG_YMM23 = 177 , X86_REG_YMM24 = 178 , X86_REG_YMM25 = 179 , X86_REG_YMM26 = 180 , X86_REG_YMM27 = 181 , X86_REG_YMM28 = 182 , X86_REG_YMM29 = 183 , X86_REG_YMM30 = 184 , X86_REG_YMM31 = 185 , X86_REG_ZMM0 = 186 , X86_REG_ZMM1 = 187 , X86_REG_ZMM2 = 188 , X86_REG_ZMM3 = 189 , X86_REG_ZMM4 = 190 , X86_REG_ZMM5 = 191 , X86_REG_ZMM6 = 192 , X86_REG_ZMM7 = 193 , X86_REG_ZMM8 = 194 , X86_REG_ZMM9 = 195 , X86_REG_ZMM10 = 196 , X86_REG_ZMM11 = 197 , X86_REG_ZMM12 = 198 , X86_REG_ZMM13 = 199 , X86_REG_ZMM14 = 200 , X86_REG_ZMM15 = 201 , X86_REG_ZMM16 = 202 , X86_REG_ZMM17 = 203 , X86_REG_ZMM18 = 204 , X86_REG_ZMM19 = 205 , X86_REG_ZMM20 = 206 , X86_REG_ZMM21 = 207 , X86_REG_ZMM22 = 208 , X86_REG_ZMM23 = 209 , X86_REG_ZMM24 = 210 , X86_REG_ZMM25 = 211 , X86_REG_ZMM26 = 212 , X86_REG_ZMM27 = 213 , X86_REG_ZMM28 = 214 , X86_REG_ZMM29 = 215 , X86_REG_ZMM30 = 216 , X86_REG_ZMM31 = 217 , X86_REG_R8B = 218 , X86_REG_R9B = 219 , X86_REG_R10B = 220 , X86_REG_R11B = 221 , X86_REG_R12B = 222 , X86_REG_R13B = 223 , X86_REG_R14B = 224 , X86_REG_R15B = 225 , X86_REG_R8D = 226 , X86_REG_R9D = 227 , X86_REG_R10D = 228 , X86_REG_R11D = 229 , X86_REG_R12D = 230 , X86_REG_R13D = 231 , X86_REG_R14D = 232 , X86_REG_R15D = 233 , X86_REG_R8W = 234 , X86_REG_R9W = 235 , X86_REG_R10W = 236 , X86_REG_R11W = 237 , X86_REG_R12W = 238 , X86_REG_R13W = 239 , X86_REG_R14W = 240 , X86_REG_R15W = 241 , X86_REG_BND0 = 242 , X86_REG_BND1 = 243 , X86_REG_BND2 = 244 , X86_REG_BND3 = 245 , X86_REG_ENDING = 246 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] X86_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] X86_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] X86_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] X86_OP_MEM = 3 , } # [repr (u32)] # [doc = " XOP Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_xop_cc { # [doc = "< Uninitialized."] X86_XOP_CC_INVALID = 0 , X86_XOP_CC_LT = 1 , X86_XOP_CC_LE = 2 , X86_XOP_CC_GT = 3 , X86_XOP_CC_GE = 4 , X86_XOP_CC_EQ = 5 , X86_XOP_CC_NEQ = 6 , X86_XOP_CC_FALSE = 7 , X86_XOP_CC_TRUE = 8 , } # [repr (u32)] # [doc = " AVX broadcast type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_bcast { # [doc = "< Uninitialized."] X86_AVX_BCAST_INVALID = 0 , # [doc = "< AVX512 broadcast type {1to2}"] X86_AVX_BCAST_2 = 1 , # [doc = "< AVX512 broadcast type {1to4}"] X86_AVX_BCAST_4 = 2 , # [doc = "< AVX512 broadcast type {1to8}"] X86_AVX_BCAST_8 = 3 , # [doc = "< AVX512 broadcast type {1to16}"] X86_AVX_BCAST_16 = 4 , } # [repr (u32)] # [doc = " SSE Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_sse_cc { # [doc = "< Uninitialized."] X86_SSE_CC_INVALID = 0 , X86_SSE_CC_EQ = 1 , X86_SSE_CC_LT = 2 , X86_SSE_CC_LE = 3 , X86_SSE_CC_UNORD = 4 , X86_SSE_CC_NEQ = 5 , X86_SSE_CC_NLT = 6 , X86_SSE_CC_NLE = 7 , X86_SSE_CC_ORD = 8 , } # [repr (u32)] # [doc = " AVX Code Condition type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_cc { # [doc = "< Uninitialized."] X86_AVX_CC_INVALID = 0 , X86_AVX_CC_EQ = 1 , X86_AVX_CC_LT = 2 , X86_AVX_CC_LE = 3 , X86_AVX_CC_UNORD = 4 , X86_AVX_CC_NEQ = 5 , X86_AVX_CC_NLT = 6 , X86_AVX_CC_NLE = 7 , X86_AVX_CC_ORD = 8 , X86_AVX_CC_EQ_UQ = 9 , X86_AVX_CC_NGE = 10 , X86_AVX_CC_NGT = 11 , X86_AVX_CC_FALSE = 12 , X86_AVX_CC_NEQ_OQ = 13 , X86_AVX_CC_GE = 14 , X86_AVX_CC_GT = 15 , X86_AVX_CC_TRUE = 16 , X86_AVX_CC_EQ_OS = 17 , X86_AVX_CC_LT_OQ = 18 , X86_AVX_CC_LE_OQ = 19 , X86_AVX_CC_UNORD_S = 20 , X86_AVX_CC_NEQ_US = 21 , X86_AVX_CC_NLT_UQ = 22 , X86_AVX_CC_NLE_UQ = 23 , X86_AVX_CC_ORD_S = 24 , X86_AVX_CC_EQ_US = 25 , X86_AVX_CC_NGE_UQ = 26 , X86_AVX_CC_NGT_UQ = 27 , X86_AVX_CC_FALSE_OS = 28 , X86_AVX_CC_NEQ_OS = 29 , X86_AVX_CC_GE_OQ = 30 , X86_AVX_CC_GT_OQ = 31 , X86_AVX_CC_TRUE_US = 32 , } # [repr (u32)] # [doc = " AVX static rounding mode type"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_avx_rm { # [doc = "< Uninitialized."] X86_AVX_RM_INVALID = 0 , # [doc = "< Round to nearest"] X86_AVX_RM_RN = 1 , # [doc = "< Round down"] X86_AVX_RM_RD = 2 , # [doc = "< Round up"] X86_AVX_RM_RU = 3 , # [doc = "< Round toward zero"] X86_AVX_RM_RZ = 4 , } impl x86_prefix { pub const X86_PREFIX_REPE : x86_prefix = x86_prefix :: X86_PREFIX_REP ; } # [repr (u32)] # [doc = " Instruction prefixes - to be used in cs_x86.prefix[]"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_prefix { # [doc = "< lock (cs_x86.prefix[0]"] X86_PREFIX_LOCK = 240 , # [doc = "< rep (cs_x86.prefix[0]"] X86_PREFIX_REP = 243 , # [doc = "< repne/repnz (cs_x86.prefix[0]"] X86_PREFIX_REPNE = 242 , # [doc = "< segment override CS (cs_x86.prefix[1]"] X86_PREFIX_CS = 46 , # [doc = "< segment override SS (cs_x86.prefix[1]"] X86_PREFIX_SS = 54 , # [doc = "< segment override DS (cs_x86.prefix[1]"] X86_PREFIX_DS = 62 , # [doc = "< segment override ES (cs_x86.prefix[1]"] X86_PREFIX_ES = 38 , # [doc = "< segment override FS (cs_x86.prefix[1]"] X86_PREFIX_FS = 100 , # [doc = "< segment override GS (cs_x86.prefix[1]"] X86_PREFIX_GS = 101 , # [doc = "< operand-size override (cs_x86.prefix[2]"] X86_PREFIX_OPSIZE = 102 , # [doc = "< address-size override (cs_x86.prefix[3]"] X86_PREFIX_ADDRSIZE = 103 , } # [doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct x86_op_mem { # [doc = "< segment register (or X86_REG_INVALID if irrelevant)"] pub segment : x86_reg , # [doc = "< base register (or X86_REG_INVALID if irrelevant)"] pub base : x86_reg , # [doc = "< index register (or X86_REG_INVALID if irrelevant)"] pub index : x86_reg , # [doc = "< scale for index register"] pub scale : :: std :: os :: raw :: c_int , # [doc = "< displacement value"] pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of x86_op_mem"] [:: std :: mem :: size_of :: < x86_op_mem > () - 24usize] ; ["Alignment of x86_op_mem"] [:: std :: mem :: align_of :: < x86_op_mem > () - 8usize] ; ["Offset of field: x86_op_mem::segment"] [:: std :: mem :: offset_of ! (x86_op_mem , segment) - 0usize] ; ["Offset of field: x86_op_mem::base"] [:: std :: mem :: offset_of ! (x86_op_mem , base) - 4usize] ; ["Offset of field: x86_op_mem::index"] [:: std :: mem :: offset_of ! (x86_op_mem , index) - 8usize] ; ["Offset of field: x86_op_mem::scale"] [:: std :: mem :: offset_of ! (x86_op_mem , scale) - 12usize] ; ["Offset of field: x86_op_mem::disp"] [:: std :: mem :: offset_of ! (x86_op_mem , disp) - 16usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86_op { # [doc = "< operand type"] pub type_ : x86_op_type , pub __bindgen_anon_1 : cs_x86_op__bindgen_ty_1 , # [doc = " size of this operand (in bytes)."] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , # [doc = " AVX broadcast type, or 0 if irrelevant"] pub avx_bcast : x86_avx_bcast , # [doc = " AVX zero opmask {z}"] pub avx_zero_opmask : bool , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : x86_reg , # [doc = "< immediate value for IMM operand"] pub imm : i64 , # [doc = "< base/index/scale/disp value for MEM operand"] pub mem : x86_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_x86_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_x86_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_x86_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_op"] [:: std :: mem :: size_of :: < cs_x86_op > () - 48usize] ; ["Alignment of cs_x86_op"] [:: std :: mem :: align_of :: < cs_x86_op > () - 8usize] ; ["Offset of field: cs_x86_op::type_"] [:: std :: mem :: offset_of ! (cs_x86_op , type_) - 0usize] ; ["Offset of field: cs_x86_op::size"] [:: std :: mem :: offset_of ! (cs_x86_op , size) - 32usize] ; ["Offset of field: cs_x86_op::access"] [:: std :: mem :: offset_of ! (cs_x86_op , access) - 33usize] ; ["Offset of field: cs_x86_op::avx_bcast"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_bcast) - 36usize] ; ["Offset of field: cs_x86_op::avx_zero_opmask"] [:: std :: mem :: offset_of ! (cs_x86_op , avx_zero_opmask) - 40usize] ; } ; impl :: std :: fmt :: Debug for cs_x86_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask) } } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_x86_encoding { # [doc = " ModR/M offset, or 0 when irrelevant"] pub modrm_offset : u8 , # [doc = " Displacement offset, or 0 when irrelevant."] pub disp_offset : u8 , pub disp_size : u8 , # [doc = " Immediate offset, or 0 when irrelevant."] pub imm_offset : u8 , pub imm_size : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86_encoding"] [:: std :: mem :: size_of :: < cs_x86_encoding > () - 5usize] ; ["Alignment of cs_x86_encoding"] [:: std :: mem :: align_of :: < cs_x86_encoding > () - 1usize] ; ["Offset of field: cs_x86_encoding::modrm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , modrm_offset) - 0usize] ; ["Offset of field: cs_x86_encoding::disp_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_offset) - 1usize] ; ["Offset of field: cs_x86_encoding::disp_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , disp_size) - 2usize] ; ["Offset of field: cs_x86_encoding::imm_offset"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_offset) - 3usize] ; ["Offset of field: cs_x86_encoding::imm_size"] [:: std :: mem :: offset_of ! (cs_x86_encoding , imm_size) - 4usize] ; } ; # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_x86 { # [doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"] pub prefix : [u8 ; 4usize] , # [doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."] pub opcode : [u8 ; 4usize] , # [doc = " REX prefix: only a non-zero value is relevant for x86_64"] pub rex : u8 , # [doc = " Address size, which can be overridden with above prefix[5]."] pub addr_size : u8 , # [doc = " ModR/M byte"] pub modrm : u8 , # [doc = " SIB value, or 0 when irrelevant."] pub sib : u8 , # [doc = " Displacement value, valid if encoding.disp_offset != 0"] pub disp : i64 , # [doc = " SIB index register, or X86_REG_INVALID when irrelevant."] pub sib_index : x86_reg , # [doc = " SIB scale, only applicable if sib_index is valid."] pub sib_scale : i8 , # [doc = " SIB base register, or X86_REG_INVALID when irrelevant."] pub sib_base : x86_reg , # [doc = " XOP Code Condition"] pub xop_cc : x86_xop_cc , # [doc = " SSE Code Condition"] pub sse_cc : x86_sse_cc , # [doc = " AVX Code Condition"] pub avx_cc : x86_avx_cc , # [doc = " AVX Suppress all Exception"] pub avx_sae : bool , # [doc = " AVX static rounding mode"] pub avx_rm : x86_avx_rm , pub __bindgen_anon_1 : cs_x86__bindgen_ty_1 , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_x86_op ; 8usize] , # [doc = "< encoding information"] pub encoding : cs_x86_encoding , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_x86__bindgen_ty_1 { # [doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"] pub eflags : u64 , # [doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"] pub fpu_flags : u64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_x86__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_x86__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_x86__bindgen_ty_1::eflags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , eflags) - 0usize] ; ["Offset of field: cs_x86__bindgen_ty_1::fpu_flags"] [:: std :: mem :: offset_of ! (cs_x86__bindgen_ty_1 , fpu_flags) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_x86__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_x86"] [:: std :: mem :: size_of :: < cs_x86 > () - 464usize] ; ["Alignment of cs_x86"] [:: std :: mem :: align_of :: < cs_x86 > () - 8usize] ; ["Offset of field: cs_x86::prefix"] [:: std :: mem :: offset_of ! (cs_x86 , prefix) - 0usize] ; ["Offset of field: cs_x86::opcode"] [:: std :: mem :: offset_of ! (cs_x86 , opcode) - 4usize] ; ["Offset of field: cs_x86::rex"] [:: std :: mem :: offset_of ! (cs_x86 , rex) - 8usize] ; ["Offset of field: cs_x86::addr_size"] [:: std :: mem :: offset_of ! (cs_x86 , addr_size) - 9usize] ; ["Offset of field: cs_x86::modrm"] [:: std :: mem :: offset_of ! (cs_x86 , modrm) - 10usize] ; ["Offset of field: cs_x86::sib"] [:: std :: mem :: offset_of ! (cs_x86 , sib) - 11usize] ; ["Offset of field: cs_x86::disp"] [:: std :: mem :: offset_of ! (cs_x86 , disp) - 16usize] ; ["Offset of field: cs_x86::sib_index"] [:: std :: mem :: offset_of ! (cs_x86 , sib_index) - 24usize] ; ["Offset of field: cs_x86::sib_scale"] [:: std :: mem :: offset_of ! (cs_x86 , sib_scale) - 28usize] ; ["Offset of field: cs_x86::sib_base"] [:: std :: mem :: offset_of ! (cs_x86 , sib_base) - 32usize] ; ["Offset of field: cs_x86::xop_cc"] [:: std :: mem :: offset_of ! (cs_x86 , xop_cc) - 36usize] ; ["Offset of field: cs_x86::sse_cc"] [:: std :: mem :: offset_of ! (cs_x86 , sse_cc) - 40usize] ; ["Offset of field: cs_x86::avx_cc"] [:: std :: mem :: offset_of ! (cs_x86 , avx_cc) - 44usize] ; ["Offset of field: cs_x86::avx_sae"] [:: std :: mem :: offset_of ! (cs_x86 , avx_sae) - 48usize] ; ["Offset of field: cs_x86::avx_rm"] [:: std :: mem :: offset_of ! (cs_x86 , avx_rm) - 52usize] ; ["Offset of field: cs_x86::op_count"] [:: std :: mem :: offset_of ! (cs_x86 , op_count) - 64usize] ; ["Offset of field: cs_x86::operands"] [:: std :: mem :: offset_of ! (cs_x86 , operands) - 72usize] ; ["Offset of field: cs_x86::encoding"] [:: std :: mem :: offset_of ! (cs_x86 , encoding) - 456usize] ; } ; impl :: std :: fmt :: Debug for cs_x86 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding) } } # [repr (u32)] # [doc = " X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn { X86_INS_INVALID = 0 , X86_INS_AAA = 1 , X86_INS_AAD = 2 , X86_INS_AAM = 3 , X86_INS_AAS = 4 , X86_INS_FABS = 5 , X86_INS_ADC = 6 , X86_INS_ADCX = 7 , X86_INS_ADD = 8 , X86_INS_ADDPD = 9 , X86_INS_ADDPS = 10 , X86_INS_ADDSD = 11 , X86_INS_ADDSS = 12 , X86_INS_ADDSUBPD = 13 , X86_INS_ADDSUBPS = 14 , X86_INS_FADD = 15 , X86_INS_FIADD = 16 , X86_INS_ADOX = 17 , X86_INS_AESDECLAST = 18 , X86_INS_AESDEC = 19 , X86_INS_AESENCLAST = 20 , X86_INS_AESENC = 21 , X86_INS_AESIMC = 22 , X86_INS_AESKEYGENASSIST = 23 , X86_INS_AND = 24 , X86_INS_ANDN = 25 , X86_INS_ANDNPD = 26 , X86_INS_ANDNPS = 27 , X86_INS_ANDPD = 28 , X86_INS_ANDPS = 29 , X86_INS_ARPL = 30 , X86_INS_BEXTR = 31 , X86_INS_BLCFILL = 32 , X86_INS_BLCI = 33 , X86_INS_BLCIC = 34 , X86_INS_BLCMSK = 35 , X86_INS_BLCS = 36 , X86_INS_BLENDPD = 37 , X86_INS_BLENDPS = 38 , X86_INS_BLENDVPD = 39 , X86_INS_BLENDVPS = 40 , X86_INS_BLSFILL = 41 , X86_INS_BLSI = 42 , X86_INS_BLSIC = 43 , X86_INS_BLSMSK = 44 , X86_INS_BLSR = 45 , X86_INS_BNDCL = 46 , X86_INS_BNDCN = 47 , X86_INS_BNDCU = 48 , X86_INS_BNDLDX = 49 , X86_INS_BNDMK = 50 , X86_INS_BNDMOV = 51 , X86_INS_BNDSTX = 52 , X86_INS_BOUND = 53 , X86_INS_BSF = 54 , X86_INS_BSR = 55 , X86_INS_BSWAP = 56 , X86_INS_BT = 57 , X86_INS_BTC = 58 , X86_INS_BTR = 59 , X86_INS_BTS = 60 , X86_INS_BZHI = 61 , X86_INS_CALL = 62 , X86_INS_CBW = 63 , X86_INS_CDQ = 64 , X86_INS_CDQE = 65 , X86_INS_FCHS = 66 , X86_INS_CLAC = 67 , X86_INS_CLC = 68 , X86_INS_CLD = 69 , X86_INS_CLDEMOTE = 70 , X86_INS_CLFLUSH = 71 , X86_INS_CLFLUSHOPT = 72 , X86_INS_CLGI = 73 , X86_INS_CLI = 74 , X86_INS_CLRSSBSY = 75 , X86_INS_CLTS = 76 , X86_INS_CLWB = 77 , X86_INS_CLZERO = 78 , X86_INS_CMC = 79 , X86_INS_CMOVA = 80 , X86_INS_CMOVAE = 81 , X86_INS_CMOVB = 82 , X86_INS_CMOVBE = 83 , X86_INS_FCMOVBE = 84 , X86_INS_FCMOVB = 85 , X86_INS_CMOVE = 86 , X86_INS_FCMOVE = 87 , X86_INS_CMOVG = 88 , X86_INS_CMOVGE = 89 , X86_INS_CMOVL = 90 , X86_INS_CMOVLE = 91 , X86_INS_FCMOVNBE = 92 , X86_INS_FCMOVNB = 93 , X86_INS_CMOVNE = 94 , X86_INS_FCMOVNE = 95 , X86_INS_CMOVNO = 96 , X86_INS_CMOVNP = 97 , X86_INS_FCMOVNU = 98 , X86_INS_FCMOVNP = 99 , X86_INS_CMOVNS = 100 , X86_INS_CMOVO = 101 , X86_INS_CMOVP = 102 , X86_INS_FCMOVU = 103 , X86_INS_CMOVS = 104 , X86_INS_CMP = 105 , X86_INS_CMPPD = 106 , X86_INS_CMPPS = 107 , X86_INS_CMPSB = 108 , X86_INS_CMPSD = 109 , X86_INS_CMPSQ = 110 , X86_INS_CMPSS = 111 , X86_INS_CMPSW = 112 , X86_INS_CMPXCHG16B = 113 , X86_INS_CMPXCHG = 114 , X86_INS_CMPXCHG8B = 115 , X86_INS_COMISD = 116 , X86_INS_COMISS = 117 , X86_INS_FCOMP = 118 , X86_INS_FCOMPI = 119 , X86_INS_FCOMI = 120 , X86_INS_FCOM = 121 , X86_INS_FCOS = 122 , X86_INS_CPUID = 123 , X86_INS_CQO = 124 , X86_INS_CRC32 = 125 , X86_INS_CVTDQ2PD = 126 , X86_INS_CVTDQ2PS = 127 , X86_INS_CVTPD2DQ = 128 , X86_INS_CVTPD2PS = 129 , X86_INS_CVTPS2DQ = 130 , X86_INS_CVTPS2PD = 131 , X86_INS_CVTSD2SI = 132 , X86_INS_CVTSD2SS = 133 , X86_INS_CVTSI2SD = 134 , X86_INS_CVTSI2SS = 135 , X86_INS_CVTSS2SD = 136 , X86_INS_CVTSS2SI = 137 , X86_INS_CVTTPD2DQ = 138 , X86_INS_CVTTPS2DQ = 139 , X86_INS_CVTTSD2SI = 140 , X86_INS_CVTTSS2SI = 141 , X86_INS_CWD = 142 , X86_INS_CWDE = 143 , X86_INS_DAA = 144 , X86_INS_DAS = 145 , X86_INS_DATA16 = 146 , X86_INS_DEC = 147 , X86_INS_DIV = 148 , X86_INS_DIVPD = 149 , X86_INS_DIVPS = 150 , X86_INS_FDIVR = 151 , X86_INS_FIDIVR = 152 , X86_INS_FDIVRP = 153 , X86_INS_DIVSD = 154 , X86_INS_DIVSS = 155 , X86_INS_FDIV = 156 , X86_INS_FIDIV = 157 , X86_INS_FDIVP = 158 , X86_INS_DPPD = 159 , X86_INS_DPPS = 160 , X86_INS_ENCLS = 161 , X86_INS_ENCLU = 162 , X86_INS_ENCLV = 163 , X86_INS_ENDBR32 = 164 , X86_INS_ENDBR64 = 165 , X86_INS_ENTER = 166 , X86_INS_EXTRACTPS = 167 , X86_INS_EXTRQ = 168 , X86_INS_F2XM1 = 169 , X86_INS_LCALL = 170 , X86_INS_LJMP = 171 , X86_INS_JMP = 172 , X86_INS_FBLD = 173 , X86_INS_FBSTP = 174 , X86_INS_FCOMPP = 175 , X86_INS_FDECSTP = 176 , X86_INS_FDISI8087_NOP = 177 , X86_INS_FEMMS = 178 , X86_INS_FENI8087_NOP = 179 , X86_INS_FFREE = 180 , X86_INS_FFREEP = 181 , X86_INS_FICOM = 182 , X86_INS_FICOMP = 183 , X86_INS_FINCSTP = 184 , X86_INS_FLDCW = 185 , X86_INS_FLDENV = 186 , X86_INS_FLDL2E = 187 , X86_INS_FLDL2T = 188 , X86_INS_FLDLG2 = 189 , X86_INS_FLDLN2 = 190 , X86_INS_FLDPI = 191 , X86_INS_FNCLEX = 192 , X86_INS_FNINIT = 193 , X86_INS_FNOP = 194 , X86_INS_FNSTCW = 195 , X86_INS_FNSTSW = 196 , X86_INS_FPATAN = 197 , X86_INS_FSTPNCE = 198 , X86_INS_FPREM = 199 , X86_INS_FPREM1 = 200 , X86_INS_FPTAN = 201 , X86_INS_FRNDINT = 202 , X86_INS_FRSTOR = 203 , X86_INS_FNSAVE = 204 , X86_INS_FSCALE = 205 , X86_INS_FSETPM = 206 , X86_INS_FSINCOS = 207 , X86_INS_FNSTENV = 208 , X86_INS_FXAM = 209 , X86_INS_FXRSTOR = 210 , X86_INS_FXRSTOR64 = 211 , X86_INS_FXSAVE = 212 , X86_INS_FXSAVE64 = 213 , X86_INS_FXTRACT = 214 , X86_INS_FYL2X = 215 , X86_INS_FYL2XP1 = 216 , X86_INS_GETSEC = 217 , X86_INS_GF2P8AFFINEINVQB = 218 , X86_INS_GF2P8AFFINEQB = 219 , X86_INS_GF2P8MULB = 220 , X86_INS_HADDPD = 221 , X86_INS_HADDPS = 222 , X86_INS_HLT = 223 , X86_INS_HSUBPD = 224 , X86_INS_HSUBPS = 225 , X86_INS_IDIV = 226 , X86_INS_FILD = 227 , X86_INS_IMUL = 228 , X86_INS_IN = 229 , X86_INS_INC = 230 , X86_INS_INCSSPD = 231 , X86_INS_INCSSPQ = 232 , X86_INS_INSB = 233 , X86_INS_INSERTPS = 234 , X86_INS_INSERTQ = 235 , X86_INS_INSD = 236 , X86_INS_INSW = 237 , X86_INS_INT = 238 , X86_INS_INT1 = 239 , X86_INS_INT3 = 240 , X86_INS_INTO = 241 , X86_INS_INVD = 242 , X86_INS_INVEPT = 243 , X86_INS_INVLPG = 244 , X86_INS_INVLPGA = 245 , X86_INS_INVPCID = 246 , X86_INS_INVVPID = 247 , X86_INS_IRET = 248 , X86_INS_IRETD = 249 , X86_INS_IRETQ = 250 , X86_INS_FISTTP = 251 , X86_INS_FIST = 252 , X86_INS_FISTP = 253 , X86_INS_JAE = 254 , X86_INS_JA = 255 , X86_INS_JBE = 256 , X86_INS_JB = 257 , X86_INS_JCXZ = 258 , X86_INS_JECXZ = 259 , X86_INS_JE = 260 , X86_INS_JGE = 261 , X86_INS_JG = 262 , X86_INS_JLE = 263 , X86_INS_JL = 264 , X86_INS_JNE = 265 , X86_INS_JNO = 266 , X86_INS_JNP = 267 , X86_INS_JNS = 268 , X86_INS_JO = 269 , X86_INS_JP = 270 , X86_INS_JRCXZ = 271 , X86_INS_JS = 272 , X86_INS_KADDB = 273 , X86_INS_KADDD = 274 , X86_INS_KADDQ = 275 , X86_INS_KADDW = 276 , X86_INS_KANDB = 277 , X86_INS_KANDD = 278 , X86_INS_KANDNB = 279 , X86_INS_KANDND = 280 , X86_INS_KANDNQ = 281 , X86_INS_KANDNW = 282 , X86_INS_KANDQ = 283 , X86_INS_KANDW = 284 , X86_INS_KMOVB = 285 , X86_INS_KMOVD = 286 , X86_INS_KMOVQ = 287 , X86_INS_KMOVW = 288 , X86_INS_KNOTB = 289 , X86_INS_KNOTD = 290 , X86_INS_KNOTQ = 291 , X86_INS_KNOTW = 292 , X86_INS_KORB = 293 , X86_INS_KORD = 294 , X86_INS_KORQ = 295 , X86_INS_KORTESTB = 296 , X86_INS_KORTESTD = 297 , X86_INS_KORTESTQ = 298 , X86_INS_KORTESTW = 299 , X86_INS_KORW = 300 , X86_INS_KSHIFTLB = 301 , X86_INS_KSHIFTLD = 302 , X86_INS_KSHIFTLQ = 303 , X86_INS_KSHIFTLW = 304 , X86_INS_KSHIFTRB = 305 , X86_INS_KSHIFTRD = 306 , X86_INS_KSHIFTRQ = 307 , X86_INS_KSHIFTRW = 308 , X86_INS_KTESTB = 309 , X86_INS_KTESTD = 310 , X86_INS_KTESTQ = 311 , X86_INS_KTESTW = 312 , X86_INS_KUNPCKBW = 313 , X86_INS_KUNPCKDQ = 314 , X86_INS_KUNPCKWD = 315 , X86_INS_KXNORB = 316 , X86_INS_KXNORD = 317 , X86_INS_KXNORQ = 318 , X86_INS_KXNORW = 319 , X86_INS_KXORB = 320 , X86_INS_KXORD = 321 , X86_INS_KXORQ = 322 , X86_INS_KXORW = 323 , X86_INS_LAHF = 324 , X86_INS_LAR = 325 , X86_INS_LDDQU = 326 , X86_INS_LDMXCSR = 327 , X86_INS_LDS = 328 , X86_INS_FLDZ = 329 , X86_INS_FLD1 = 330 , X86_INS_FLD = 331 , X86_INS_LEA = 332 , X86_INS_LEAVE = 333 , X86_INS_LES = 334 , X86_INS_LFENCE = 335 , X86_INS_LFS = 336 , X86_INS_LGDT = 337 , X86_INS_LGS = 338 , X86_INS_LIDT = 339 , X86_INS_LLDT = 340 , X86_INS_LLWPCB = 341 , X86_INS_LMSW = 342 , X86_INS_LOCK = 343 , X86_INS_LODSB = 344 , X86_INS_LODSD = 345 , X86_INS_LODSQ = 346 , X86_INS_LODSW = 347 , X86_INS_LOOP = 348 , X86_INS_LOOPE = 349 , X86_INS_LOOPNE = 350 , X86_INS_RETF = 351 , X86_INS_RETFQ = 352 , X86_INS_LSL = 353 , X86_INS_LSS = 354 , X86_INS_LTR = 355 , X86_INS_LWPINS = 356 , X86_INS_LWPVAL = 357 , X86_INS_LZCNT = 358 , X86_INS_MASKMOVDQU = 359 , X86_INS_MAXPD = 360 , X86_INS_MAXPS = 361 , X86_INS_MAXSD = 362 , X86_INS_MAXSS = 363 , X86_INS_MFENCE = 364 , X86_INS_MINPD = 365 , X86_INS_MINPS = 366 , X86_INS_MINSD = 367 , X86_INS_MINSS = 368 , X86_INS_CVTPD2PI = 369 , X86_INS_CVTPI2PD = 370 , X86_INS_CVTPI2PS = 371 , X86_INS_CVTPS2PI = 372 , X86_INS_CVTTPD2PI = 373 , X86_INS_CVTTPS2PI = 374 , X86_INS_EMMS = 375 , X86_INS_MASKMOVQ = 376 , X86_INS_MOVD = 377 , X86_INS_MOVQ = 378 , X86_INS_MOVDQ2Q = 379 , X86_INS_MOVNTQ = 380 , X86_INS_MOVQ2DQ = 381 , X86_INS_PABSB = 382 , X86_INS_PABSD = 383 , X86_INS_PABSW = 384 , X86_INS_PACKSSDW = 385 , X86_INS_PACKSSWB = 386 , X86_INS_PACKUSWB = 387 , X86_INS_PADDB = 388 , X86_INS_PADDD = 389 , X86_INS_PADDQ = 390 , X86_INS_PADDSB = 391 , X86_INS_PADDSW = 392 , X86_INS_PADDUSB = 393 , X86_INS_PADDUSW = 394 , X86_INS_PADDW = 395 , X86_INS_PALIGNR = 396 , X86_INS_PANDN = 397 , X86_INS_PAND = 398 , X86_INS_PAVGB = 399 , X86_INS_PAVGW = 400 , X86_INS_PCMPEQB = 401 , X86_INS_PCMPEQD = 402 , X86_INS_PCMPEQW = 403 , X86_INS_PCMPGTB = 404 , X86_INS_PCMPGTD = 405 , X86_INS_PCMPGTW = 406 , X86_INS_PEXTRW = 407 , X86_INS_PHADDD = 408 , X86_INS_PHADDSW = 409 , X86_INS_PHADDW = 410 , X86_INS_PHSUBD = 411 , X86_INS_PHSUBSW = 412 , X86_INS_PHSUBW = 413 , X86_INS_PINSRW = 414 , X86_INS_PMADDUBSW = 415 , X86_INS_PMADDWD = 416 , X86_INS_PMAXSW = 417 , X86_INS_PMAXUB = 418 , X86_INS_PMINSW = 419 , X86_INS_PMINUB = 420 , X86_INS_PMOVMSKB = 421 , X86_INS_PMULHRSW = 422 , X86_INS_PMULHUW = 423 , X86_INS_PMULHW = 424 , X86_INS_PMULLW = 425 , X86_INS_PMULUDQ = 426 , X86_INS_POR = 427 , X86_INS_PSADBW = 428 , X86_INS_PSHUFB = 429 , X86_INS_PSHUFW = 430 , X86_INS_PSIGNB = 431 , X86_INS_PSIGND = 432 , X86_INS_PSIGNW = 433 , X86_INS_PSLLD = 434 , X86_INS_PSLLQ = 435 , X86_INS_PSLLW = 436 , X86_INS_PSRAD = 437 , X86_INS_PSRAW = 438 , X86_INS_PSRLD = 439 , X86_INS_PSRLQ = 440 , X86_INS_PSRLW = 441 , X86_INS_PSUBB = 442 , X86_INS_PSUBD = 443 , X86_INS_PSUBQ = 444 , X86_INS_PSUBSB = 445 , X86_INS_PSUBSW = 446 , X86_INS_PSUBUSB = 447 , X86_INS_PSUBUSW = 448 , X86_INS_PSUBW = 449 , X86_INS_PUNPCKHBW = 450 , X86_INS_PUNPCKHDQ = 451 , X86_INS_PUNPCKHWD = 452 , X86_INS_PUNPCKLBW = 453 , X86_INS_PUNPCKLDQ = 454 , X86_INS_PUNPCKLWD = 455 , X86_INS_PXOR = 456 , X86_INS_MONITORX = 457 , X86_INS_MONITOR = 458 , X86_INS_MONTMUL = 459 , X86_INS_MOV = 460 , X86_INS_MOVABS = 461 , X86_INS_MOVAPD = 462 , X86_INS_MOVAPS = 463 , X86_INS_MOVBE = 464 , X86_INS_MOVDDUP = 465 , X86_INS_MOVDIR64B = 466 , X86_INS_MOVDIRI = 467 , X86_INS_MOVDQA = 468 , X86_INS_MOVDQU = 469 , X86_INS_MOVHLPS = 470 , X86_INS_MOVHPD = 471 , X86_INS_MOVHPS = 472 , X86_INS_MOVLHPS = 473 , X86_INS_MOVLPD = 474 , X86_INS_MOVLPS = 475 , X86_INS_MOVMSKPD = 476 , X86_INS_MOVMSKPS = 477 , X86_INS_MOVNTDQA = 478 , X86_INS_MOVNTDQ = 479 , X86_INS_MOVNTI = 480 , X86_INS_MOVNTPD = 481 , X86_INS_MOVNTPS = 482 , X86_INS_MOVNTSD = 483 , X86_INS_MOVNTSS = 484 , X86_INS_MOVSB = 485 , X86_INS_MOVSD = 486 , X86_INS_MOVSHDUP = 487 , X86_INS_MOVSLDUP = 488 , X86_INS_MOVSQ = 489 , X86_INS_MOVSS = 490 , X86_INS_MOVSW = 491 , X86_INS_MOVSX = 492 , X86_INS_MOVSXD = 493 , X86_INS_MOVUPD = 494 , X86_INS_MOVUPS = 495 , X86_INS_MOVZX = 496 , X86_INS_MPSADBW = 497 , X86_INS_MUL = 498 , X86_INS_MULPD = 499 , X86_INS_MULPS = 500 , X86_INS_MULSD = 501 , X86_INS_MULSS = 502 , X86_INS_MULX = 503 , X86_INS_FMUL = 504 , X86_INS_FIMUL = 505 , X86_INS_FMULP = 506 , X86_INS_MWAITX = 507 , X86_INS_MWAIT = 508 , X86_INS_NEG = 509 , X86_INS_NOP = 510 , X86_INS_NOT = 511 , X86_INS_OR = 512 , X86_INS_ORPD = 513 , X86_INS_ORPS = 514 , X86_INS_OUT = 515 , X86_INS_OUTSB = 516 , X86_INS_OUTSD = 517 , X86_INS_OUTSW = 518 , X86_INS_PACKUSDW = 519 , X86_INS_PAUSE = 520 , X86_INS_PAVGUSB = 521 , X86_INS_PBLENDVB = 522 , X86_INS_PBLENDW = 523 , X86_INS_PCLMULQDQ = 524 , X86_INS_PCMPEQQ = 525 , X86_INS_PCMPESTRI = 526 , X86_INS_PCMPESTRM = 527 , X86_INS_PCMPGTQ = 528 , X86_INS_PCMPISTRI = 529 , X86_INS_PCMPISTRM = 530 , X86_INS_PCONFIG = 531 , X86_INS_PDEP = 532 , X86_INS_PEXT = 533 , X86_INS_PEXTRB = 534 , X86_INS_PEXTRD = 535 , X86_INS_PEXTRQ = 536 , X86_INS_PF2ID = 537 , X86_INS_PF2IW = 538 , X86_INS_PFACC = 539 , X86_INS_PFADD = 540 , X86_INS_PFCMPEQ = 541 , X86_INS_PFCMPGE = 542 , X86_INS_PFCMPGT = 543 , X86_INS_PFMAX = 544 , X86_INS_PFMIN = 545 , X86_INS_PFMUL = 546 , X86_INS_PFNACC = 547 , X86_INS_PFPNACC = 548 , X86_INS_PFRCPIT1 = 549 , X86_INS_PFRCPIT2 = 550 , X86_INS_PFRCP = 551 , X86_INS_PFRSQIT1 = 552 , X86_INS_PFRSQRT = 553 , X86_INS_PFSUBR = 554 , X86_INS_PFSUB = 555 , X86_INS_PHMINPOSUW = 556 , X86_INS_PI2FD = 557 , X86_INS_PI2FW = 558 , X86_INS_PINSRB = 559 , X86_INS_PINSRD = 560 , X86_INS_PINSRQ = 561 , X86_INS_PMAXSB = 562 , X86_INS_PMAXSD = 563 , X86_INS_PMAXUD = 564 , X86_INS_PMAXUW = 565 , X86_INS_PMINSB = 566 , X86_INS_PMINSD = 567 , X86_INS_PMINUD = 568 , X86_INS_PMINUW = 569 , X86_INS_PMOVSXBD = 570 , X86_INS_PMOVSXBQ = 571 , X86_INS_PMOVSXBW = 572 , X86_INS_PMOVSXDQ = 573 , X86_INS_PMOVSXWD = 574 , X86_INS_PMOVSXWQ = 575 , X86_INS_PMOVZXBD = 576 , X86_INS_PMOVZXBQ = 577 , X86_INS_PMOVZXBW = 578 , X86_INS_PMOVZXDQ = 579 , X86_INS_PMOVZXWD = 580 , X86_INS_PMOVZXWQ = 581 , X86_INS_PMULDQ = 582 , X86_INS_PMULHRW = 583 , X86_INS_PMULLD = 584 , X86_INS_POP = 585 , X86_INS_POPAW = 586 , X86_INS_POPAL = 587 , X86_INS_POPCNT = 588 , X86_INS_POPF = 589 , X86_INS_POPFD = 590 , X86_INS_POPFQ = 591 , X86_INS_PREFETCH = 592 , X86_INS_PREFETCHNTA = 593 , X86_INS_PREFETCHT0 = 594 , X86_INS_PREFETCHT1 = 595 , X86_INS_PREFETCHT2 = 596 , X86_INS_PREFETCHW = 597 , X86_INS_PREFETCHWT1 = 598 , X86_INS_PSHUFD = 599 , X86_INS_PSHUFHW = 600 , X86_INS_PSHUFLW = 601 , X86_INS_PSLLDQ = 602 , X86_INS_PSRLDQ = 603 , X86_INS_PSWAPD = 604 , X86_INS_PTEST = 605 , X86_INS_PTWRITE = 606 , X86_INS_PUNPCKHQDQ = 607 , X86_INS_PUNPCKLQDQ = 608 , X86_INS_PUSH = 609 , X86_INS_PUSHAW = 610 , X86_INS_PUSHAL = 611 , X86_INS_PUSHF = 612 , X86_INS_PUSHFD = 613 , X86_INS_PUSHFQ = 614 , X86_INS_RCL = 615 , X86_INS_RCPPS = 616 , X86_INS_RCPSS = 617 , X86_INS_RCR = 618 , X86_INS_RDFSBASE = 619 , X86_INS_RDGSBASE = 620 , X86_INS_RDMSR = 621 , X86_INS_RDPID = 622 , X86_INS_RDPKRU = 623 , X86_INS_RDPMC = 624 , X86_INS_RDRAND = 625 , X86_INS_RDSEED = 626 , X86_INS_RDSSPD = 627 , X86_INS_RDSSPQ = 628 , X86_INS_RDTSC = 629 , X86_INS_RDTSCP = 630 , X86_INS_REPNE = 631 , X86_INS_REP = 632 , X86_INS_RET = 633 , X86_INS_REX64 = 634 , X86_INS_ROL = 635 , X86_INS_ROR = 636 , X86_INS_RORX = 637 , X86_INS_ROUNDPD = 638 , X86_INS_ROUNDPS = 639 , X86_INS_ROUNDSD = 640 , X86_INS_ROUNDSS = 641 , X86_INS_RSM = 642 , X86_INS_RSQRTPS = 643 , X86_INS_RSQRTSS = 644 , X86_INS_RSTORSSP = 645 , X86_INS_SAHF = 646 , X86_INS_SAL = 647 , X86_INS_SALC = 648 , X86_INS_SAR = 649 , X86_INS_SARX = 650 , X86_INS_SAVEPREVSSP = 651 , X86_INS_SBB = 652 , X86_INS_SCASB = 653 , X86_INS_SCASD = 654 , X86_INS_SCASQ = 655 , X86_INS_SCASW = 656 , X86_INS_SETAE = 657 , X86_INS_SETA = 658 , X86_INS_SETBE = 659 , X86_INS_SETB = 660 , X86_INS_SETE = 661 , X86_INS_SETGE = 662 , X86_INS_SETG = 663 , X86_INS_SETLE = 664 , X86_INS_SETL = 665 , X86_INS_SETNE = 666 , X86_INS_SETNO = 667 , X86_INS_SETNP = 668 , X86_INS_SETNS = 669 , X86_INS_SETO = 670 , X86_INS_SETP = 671 , X86_INS_SETSSBSY = 672 , X86_INS_SETS = 673 , X86_INS_SFENCE = 674 , X86_INS_SGDT = 675 , X86_INS_SHA1MSG1 = 676 , X86_INS_SHA1MSG2 = 677 , X86_INS_SHA1NEXTE = 678 , X86_INS_SHA1RNDS4 = 679 , X86_INS_SHA256MSG1 = 680 , X86_INS_SHA256MSG2 = 681 , X86_INS_SHA256RNDS2 = 682 , X86_INS_SHL = 683 , X86_INS_SHLD = 684 , X86_INS_SHLX = 685 , X86_INS_SHR = 686 , X86_INS_SHRD = 687 , X86_INS_SHRX = 688 , X86_INS_SHUFPD = 689 , X86_INS_SHUFPS = 690 , X86_INS_SIDT = 691 , X86_INS_FSIN = 692 , X86_INS_SKINIT = 693 , X86_INS_SLDT = 694 , X86_INS_SLWPCB = 695 , X86_INS_SMSW = 696 , X86_INS_SQRTPD = 697 , X86_INS_SQRTPS = 698 , X86_INS_SQRTSD = 699 , X86_INS_SQRTSS = 700 , X86_INS_FSQRT = 701 , X86_INS_STAC = 702 , X86_INS_STC = 703 , X86_INS_STD = 704 , X86_INS_STGI = 705 , X86_INS_STI = 706 , X86_INS_STMXCSR = 707 , X86_INS_STOSB = 708 , X86_INS_STOSD = 709 , X86_INS_STOSQ = 710 , X86_INS_STOSW = 711 , X86_INS_STR = 712 , X86_INS_FST = 713 , X86_INS_FSTP = 714 , X86_INS_SUB = 715 , X86_INS_SUBPD = 716 , X86_INS_SUBPS = 717 , X86_INS_FSUBR = 718 , X86_INS_FISUBR = 719 , X86_INS_FSUBRP = 720 , X86_INS_SUBSD = 721 , X86_INS_SUBSS = 722 , X86_INS_FSUB = 723 , X86_INS_FISUB = 724 , X86_INS_FSUBP = 725 , X86_INS_SWAPGS = 726 , X86_INS_SYSCALL = 727 , X86_INS_SYSENTER = 728 , X86_INS_SYSEXIT = 729 , X86_INS_SYSEXITQ = 730 , X86_INS_SYSRET = 731 , X86_INS_SYSRETQ = 732 , X86_INS_T1MSKC = 733 , X86_INS_TEST = 734 , X86_INS_TPAUSE = 735 , X86_INS_FTST = 736 , X86_INS_TZCNT = 737 , X86_INS_TZMSK = 738 , X86_INS_UCOMISD = 739 , X86_INS_UCOMISS = 740 , X86_INS_FUCOMPI = 741 , X86_INS_FUCOMI = 742 , X86_INS_FUCOMPP = 743 , X86_INS_FUCOMP = 744 , X86_INS_FUCOM = 745 , X86_INS_UD0 = 746 , X86_INS_UD1 = 747 , X86_INS_UD2 = 748 , X86_INS_UMONITOR = 749 , X86_INS_UMWAIT = 750 , X86_INS_UNPCKHPD = 751 , X86_INS_UNPCKHPS = 752 , X86_INS_UNPCKLPD = 753 , X86_INS_UNPCKLPS = 754 , X86_INS_V4FMADDPS = 755 , X86_INS_V4FMADDSS = 756 , X86_INS_V4FNMADDPS = 757 , X86_INS_V4FNMADDSS = 758 , X86_INS_VADDPD = 759 , X86_INS_VADDPS = 760 , X86_INS_VADDSD = 761 , X86_INS_VADDSS = 762 , X86_INS_VADDSUBPD = 763 , X86_INS_VADDSUBPS = 764 , X86_INS_VAESDECLAST = 765 , X86_INS_VAESDEC = 766 , X86_INS_VAESENCLAST = 767 , X86_INS_VAESENC = 768 , X86_INS_VAESIMC = 769 , X86_INS_VAESKEYGENASSIST = 770 , X86_INS_VALIGND = 771 , X86_INS_VALIGNQ = 772 , X86_INS_VANDNPD = 773 , X86_INS_VANDNPS = 774 , X86_INS_VANDPD = 775 , X86_INS_VANDPS = 776 , X86_INS_VBLENDMPD = 777 , X86_INS_VBLENDMPS = 778 , X86_INS_VBLENDPD = 779 , X86_INS_VBLENDPS = 780 , X86_INS_VBLENDVPD = 781 , X86_INS_VBLENDVPS = 782 , X86_INS_VBROADCASTF128 = 783 , X86_INS_VBROADCASTF32X2 = 784 , X86_INS_VBROADCASTF32X4 = 785 , X86_INS_VBROADCASTF32X8 = 786 , X86_INS_VBROADCASTF64X2 = 787 , X86_INS_VBROADCASTF64X4 = 788 , X86_INS_VBROADCASTI128 = 789 , X86_INS_VBROADCASTI32X2 = 790 , X86_INS_VBROADCASTI32X4 = 791 , X86_INS_VBROADCASTI32X8 = 792 , X86_INS_VBROADCASTI64X2 = 793 , X86_INS_VBROADCASTI64X4 = 794 , X86_INS_VBROADCASTSD = 795 , X86_INS_VBROADCASTSS = 796 , X86_INS_VCMP = 797 , X86_INS_VCMPPD = 798 , X86_INS_VCMPPS = 799 , X86_INS_VCMPSD = 800 , X86_INS_VCMPSS = 801 , X86_INS_VCOMISD = 802 , X86_INS_VCOMISS = 803 , X86_INS_VCOMPRESSPD = 804 , X86_INS_VCOMPRESSPS = 805 , X86_INS_VCVTDQ2PD = 806 , X86_INS_VCVTDQ2PS = 807 , X86_INS_VCVTPD2DQ = 808 , X86_INS_VCVTPD2PS = 809 , X86_INS_VCVTPD2QQ = 810 , X86_INS_VCVTPD2UDQ = 811 , X86_INS_VCVTPD2UQQ = 812 , X86_INS_VCVTPH2PS = 813 , X86_INS_VCVTPS2DQ = 814 , X86_INS_VCVTPS2PD = 815 , X86_INS_VCVTPS2PH = 816 , X86_INS_VCVTPS2QQ = 817 , X86_INS_VCVTPS2UDQ = 818 , X86_INS_VCVTPS2UQQ = 819 , X86_INS_VCVTQQ2PD = 820 , X86_INS_VCVTQQ2PS = 821 , X86_INS_VCVTSD2SI = 822 , X86_INS_VCVTSD2SS = 823 , X86_INS_VCVTSD2USI = 824 , X86_INS_VCVTSI2SD = 825 , X86_INS_VCVTSI2SS = 826 , X86_INS_VCVTSS2SD = 827 , X86_INS_VCVTSS2SI = 828 , X86_INS_VCVTSS2USI = 829 , X86_INS_VCVTTPD2DQ = 830 , X86_INS_VCVTTPD2QQ = 831 , X86_INS_VCVTTPD2UDQ = 832 , X86_INS_VCVTTPD2UQQ = 833 , X86_INS_VCVTTPS2DQ = 834 , X86_INS_VCVTTPS2QQ = 835 , X86_INS_VCVTTPS2UDQ = 836 , X86_INS_VCVTTPS2UQQ = 837 , X86_INS_VCVTTSD2SI = 838 , X86_INS_VCVTTSD2USI = 839 , X86_INS_VCVTTSS2SI = 840 , X86_INS_VCVTTSS2USI = 841 , X86_INS_VCVTUDQ2PD = 842 , X86_INS_VCVTUDQ2PS = 843 , X86_INS_VCVTUQQ2PD = 844 , X86_INS_VCVTUQQ2PS = 845 , X86_INS_VCVTUSI2SD = 846 , X86_INS_VCVTUSI2SS = 847 , X86_INS_VDBPSADBW = 848 , X86_INS_VDIVPD = 849 , X86_INS_VDIVPS = 850 , X86_INS_VDIVSD = 851 , X86_INS_VDIVSS = 852 , X86_INS_VDPPD = 853 , X86_INS_VDPPS = 854 , X86_INS_VERR = 855 , X86_INS_VERW = 856 , X86_INS_VEXP2PD = 857 , X86_INS_VEXP2PS = 858 , X86_INS_VEXPANDPD = 859 , X86_INS_VEXPANDPS = 860 , X86_INS_VEXTRACTF128 = 861 , X86_INS_VEXTRACTF32X4 = 862 , X86_INS_VEXTRACTF32X8 = 863 , X86_INS_VEXTRACTF64X2 = 864 , X86_INS_VEXTRACTF64X4 = 865 , X86_INS_VEXTRACTI128 = 866 , X86_INS_VEXTRACTI32X4 = 867 , X86_INS_VEXTRACTI32X8 = 868 , X86_INS_VEXTRACTI64X2 = 869 , X86_INS_VEXTRACTI64X4 = 870 , X86_INS_VEXTRACTPS = 871 , X86_INS_VFIXUPIMMPD = 872 , X86_INS_VFIXUPIMMPS = 873 , X86_INS_VFIXUPIMMSD = 874 , X86_INS_VFIXUPIMMSS = 875 , X86_INS_VFMADD132PD = 876 , X86_INS_VFMADD132PS = 877 , X86_INS_VFMADD132SD = 878 , X86_INS_VFMADD132SS = 879 , X86_INS_VFMADD213PD = 880 , X86_INS_VFMADD213PS = 881 , X86_INS_VFMADD213SD = 882 , X86_INS_VFMADD213SS = 883 , X86_INS_VFMADD231PD = 884 , X86_INS_VFMADD231PS = 885 , X86_INS_VFMADD231SD = 886 , X86_INS_VFMADD231SS = 887 , X86_INS_VFMADDPD = 888 , X86_INS_VFMADDPS = 889 , X86_INS_VFMADDSD = 890 , X86_INS_VFMADDSS = 891 , X86_INS_VFMADDSUB132PD = 892 , X86_INS_VFMADDSUB132PS = 893 , X86_INS_VFMADDSUB213PD = 894 , X86_INS_VFMADDSUB213PS = 895 , X86_INS_VFMADDSUB231PD = 896 , X86_INS_VFMADDSUB231PS = 897 , X86_INS_VFMADDSUBPD = 898 , X86_INS_VFMADDSUBPS = 899 , X86_INS_VFMSUB132PD = 900 , X86_INS_VFMSUB132PS = 901 , X86_INS_VFMSUB132SD = 902 , X86_INS_VFMSUB132SS = 903 , X86_INS_VFMSUB213PD = 904 , X86_INS_VFMSUB213PS = 905 , X86_INS_VFMSUB213SD = 906 , X86_INS_VFMSUB213SS = 907 , X86_INS_VFMSUB231PD = 908 , X86_INS_VFMSUB231PS = 909 , X86_INS_VFMSUB231SD = 910 , X86_INS_VFMSUB231SS = 911 , X86_INS_VFMSUBADD132PD = 912 , X86_INS_VFMSUBADD132PS = 913 , X86_INS_VFMSUBADD213PD = 914 , X86_INS_VFMSUBADD213PS = 915 , X86_INS_VFMSUBADD231PD = 916 , X86_INS_VFMSUBADD231PS = 917 , X86_INS_VFMSUBADDPD = 918 , X86_INS_VFMSUBADDPS = 919 , X86_INS_VFMSUBPD = 920 , X86_INS_VFMSUBPS = 921 , X86_INS_VFMSUBSD = 922 , X86_INS_VFMSUBSS = 923 , X86_INS_VFNMADD132PD = 924 , X86_INS_VFNMADD132PS = 925 , X86_INS_VFNMADD132SD = 926 , X86_INS_VFNMADD132SS = 927 , X86_INS_VFNMADD213PD = 928 , X86_INS_VFNMADD213PS = 929 , X86_INS_VFNMADD213SD = 930 , X86_INS_VFNMADD213SS = 931 , X86_INS_VFNMADD231PD = 932 , X86_INS_VFNMADD231PS = 933 , X86_INS_VFNMADD231SD = 934 , X86_INS_VFNMADD231SS = 935 , X86_INS_VFNMADDPD = 936 , X86_INS_VFNMADDPS = 937 , X86_INS_VFNMADDSD = 938 , X86_INS_VFNMADDSS = 939 , X86_INS_VFNMSUB132PD = 940 , X86_INS_VFNMSUB132PS = 941 , X86_INS_VFNMSUB132SD = 942 , X86_INS_VFNMSUB132SS = 943 , X86_INS_VFNMSUB213PD = 944 , X86_INS_VFNMSUB213PS = 945 , X86_INS_VFNMSUB213SD = 946 , X86_INS_VFNMSUB213SS = 947 , X86_INS_VFNMSUB231PD = 948 , X86_INS_VFNMSUB231PS = 949 , X86_INS_VFNMSUB231SD = 950 , X86_INS_VFNMSUB231SS = 951 , X86_INS_VFNMSUBPD = 952 , X86_INS_VFNMSUBPS = 953 , X86_INS_VFNMSUBSD = 954 , X86_INS_VFNMSUBSS = 955 , X86_INS_VFPCLASSPD = 956 , X86_INS_VFPCLASSPS = 957 , X86_INS_VFPCLASSSD = 958 , X86_INS_VFPCLASSSS = 959 , X86_INS_VFRCZPD = 960 , X86_INS_VFRCZPS = 961 , X86_INS_VFRCZSD = 962 , X86_INS_VFRCZSS = 963 , X86_INS_VGATHERDPD = 964 , X86_INS_VGATHERDPS = 965 , X86_INS_VGATHERPF0DPD = 966 , X86_INS_VGATHERPF0DPS = 967 , X86_INS_VGATHERPF0QPD = 968 , X86_INS_VGATHERPF0QPS = 969 , X86_INS_VGATHERPF1DPD = 970 , X86_INS_VGATHERPF1DPS = 971 , X86_INS_VGATHERPF1QPD = 972 , X86_INS_VGATHERPF1QPS = 973 , X86_INS_VGATHERQPD = 974 , X86_INS_VGATHERQPS = 975 , X86_INS_VGETEXPPD = 976 , X86_INS_VGETEXPPS = 977 , X86_INS_VGETEXPSD = 978 , X86_INS_VGETEXPSS = 979 , X86_INS_VGETMANTPD = 980 , X86_INS_VGETMANTPS = 981 , X86_INS_VGETMANTSD = 982 , X86_INS_VGETMANTSS = 983 , X86_INS_VGF2P8AFFINEINVQB = 984 , X86_INS_VGF2P8AFFINEQB = 985 , X86_INS_VGF2P8MULB = 986 , X86_INS_VHADDPD = 987 , X86_INS_VHADDPS = 988 , X86_INS_VHSUBPD = 989 , X86_INS_VHSUBPS = 990 , X86_INS_VINSERTF128 = 991 , X86_INS_VINSERTF32X4 = 992 , X86_INS_VINSERTF32X8 = 993 , X86_INS_VINSERTF64X2 = 994 , X86_INS_VINSERTF64X4 = 995 , X86_INS_VINSERTI128 = 996 , X86_INS_VINSERTI32X4 = 997 , X86_INS_VINSERTI32X8 = 998 , X86_INS_VINSERTI64X2 = 999 , X86_INS_VINSERTI64X4 = 1000 , X86_INS_VINSERTPS = 1001 , X86_INS_VLDDQU = 1002 , X86_INS_VLDMXCSR = 1003 , X86_INS_VMASKMOVDQU = 1004 , X86_INS_VMASKMOVPD = 1005 , X86_INS_VMASKMOVPS = 1006 , X86_INS_VMAXPD = 1007 , X86_INS_VMAXPS = 1008 , X86_INS_VMAXSD = 1009 , X86_INS_VMAXSS = 1010 , X86_INS_VMCALL = 1011 , X86_INS_VMCLEAR = 1012 , X86_INS_VMFUNC = 1013 , X86_INS_VMINPD = 1014 , X86_INS_VMINPS = 1015 , X86_INS_VMINSD = 1016 , X86_INS_VMINSS = 1017 , X86_INS_VMLAUNCH = 1018 , X86_INS_VMLOAD = 1019 , X86_INS_VMMCALL = 1020 , X86_INS_VMOVQ = 1021 , X86_INS_VMOVAPD = 1022 , X86_INS_VMOVAPS = 1023 , X86_INS_VMOVDDUP = 1024 , X86_INS_VMOVD = 1025 , X86_INS_VMOVDQA32 = 1026 , X86_INS_VMOVDQA64 = 1027 , X86_INS_VMOVDQA = 1028 , X86_INS_VMOVDQU16 = 1029 , X86_INS_VMOVDQU32 = 1030 , X86_INS_VMOVDQU64 = 1031 , X86_INS_VMOVDQU8 = 1032 , X86_INS_VMOVDQU = 1033 , X86_INS_VMOVHLPS = 1034 , X86_INS_VMOVHPD = 1035 , X86_INS_VMOVHPS = 1036 , X86_INS_VMOVLHPS = 1037 , X86_INS_VMOVLPD = 1038 , X86_INS_VMOVLPS = 1039 , X86_INS_VMOVMSKPD = 1040 , X86_INS_VMOVMSKPS = 1041 , X86_INS_VMOVNTDQA = 1042 , X86_INS_VMOVNTDQ = 1043 , X86_INS_VMOVNTPD = 1044 , X86_INS_VMOVNTPS = 1045 , X86_INS_VMOVSD = 1046 , X86_INS_VMOVSHDUP = 1047 , X86_INS_VMOVSLDUP = 1048 , X86_INS_VMOVSS = 1049 , X86_INS_VMOVUPD = 1050 , X86_INS_VMOVUPS = 1051 , X86_INS_VMPSADBW = 1052 , X86_INS_VMPTRLD = 1053 , X86_INS_VMPTRST = 1054 , X86_INS_VMREAD = 1055 , X86_INS_VMRESUME = 1056 , X86_INS_VMRUN = 1057 , X86_INS_VMSAVE = 1058 , X86_INS_VMULPD = 1059 , X86_INS_VMULPS = 1060 , X86_INS_VMULSD = 1061 , X86_INS_VMULSS = 1062 , X86_INS_VMWRITE = 1063 , X86_INS_VMXOFF = 1064 , X86_INS_VMXON = 1065 , X86_INS_VORPD = 1066 , X86_INS_VORPS = 1067 , X86_INS_VP4DPWSSDS = 1068 , X86_INS_VP4DPWSSD = 1069 , X86_INS_VPABSB = 1070 , X86_INS_VPABSD = 1071 , X86_INS_VPABSQ = 1072 , X86_INS_VPABSW = 1073 , X86_INS_VPACKSSDW = 1074 , X86_INS_VPACKSSWB = 1075 , X86_INS_VPACKUSDW = 1076 , X86_INS_VPACKUSWB = 1077 , X86_INS_VPADDB = 1078 , X86_INS_VPADDD = 1079 , X86_INS_VPADDQ = 1080 , X86_INS_VPADDSB = 1081 , X86_INS_VPADDSW = 1082 , X86_INS_VPADDUSB = 1083 , X86_INS_VPADDUSW = 1084 , X86_INS_VPADDW = 1085 , X86_INS_VPALIGNR = 1086 , X86_INS_VPANDD = 1087 , X86_INS_VPANDND = 1088 , X86_INS_VPANDNQ = 1089 , X86_INS_VPANDN = 1090 , X86_INS_VPANDQ = 1091 , X86_INS_VPAND = 1092 , X86_INS_VPAVGB = 1093 , X86_INS_VPAVGW = 1094 , X86_INS_VPBLENDD = 1095 , X86_INS_VPBLENDMB = 1096 , X86_INS_VPBLENDMD = 1097 , X86_INS_VPBLENDMQ = 1098 , X86_INS_VPBLENDMW = 1099 , X86_INS_VPBLENDVB = 1100 , X86_INS_VPBLENDW = 1101 , X86_INS_VPBROADCASTB = 1102 , X86_INS_VPBROADCASTD = 1103 , X86_INS_VPBROADCASTMB2Q = 1104 , X86_INS_VPBROADCASTMW2D = 1105 , X86_INS_VPBROADCASTQ = 1106 , X86_INS_VPBROADCASTW = 1107 , X86_INS_VPCLMULQDQ = 1108 , X86_INS_VPCMOV = 1109 , X86_INS_VPCMP = 1110 , X86_INS_VPCMPB = 1111 , X86_INS_VPCMPD = 1112 , X86_INS_VPCMPEQB = 1113 , X86_INS_VPCMPEQD = 1114 , X86_INS_VPCMPEQQ = 1115 , X86_INS_VPCMPEQW = 1116 , X86_INS_VPCMPESTRI = 1117 , X86_INS_VPCMPESTRM = 1118 , X86_INS_VPCMPGTB = 1119 , X86_INS_VPCMPGTD = 1120 , X86_INS_VPCMPGTQ = 1121 , X86_INS_VPCMPGTW = 1122 , X86_INS_VPCMPISTRI = 1123 , X86_INS_VPCMPISTRM = 1124 , X86_INS_VPCMPQ = 1125 , X86_INS_VPCMPUB = 1126 , X86_INS_VPCMPUD = 1127 , X86_INS_VPCMPUQ = 1128 , X86_INS_VPCMPUW = 1129 , X86_INS_VPCMPW = 1130 , X86_INS_VPCOM = 1131 , X86_INS_VPCOMB = 1132 , X86_INS_VPCOMD = 1133 , X86_INS_VPCOMPRESSB = 1134 , X86_INS_VPCOMPRESSD = 1135 , X86_INS_VPCOMPRESSQ = 1136 , X86_INS_VPCOMPRESSW = 1137 , X86_INS_VPCOMQ = 1138 , X86_INS_VPCOMUB = 1139 , X86_INS_VPCOMUD = 1140 , X86_INS_VPCOMUQ = 1141 , X86_INS_VPCOMUW = 1142 , X86_INS_VPCOMW = 1143 , X86_INS_VPCONFLICTD = 1144 , X86_INS_VPCONFLICTQ = 1145 , X86_INS_VPDPBUSDS = 1146 , X86_INS_VPDPBUSD = 1147 , X86_INS_VPDPWSSDS = 1148 , X86_INS_VPDPWSSD = 1149 , X86_INS_VPERM2F128 = 1150 , X86_INS_VPERM2I128 = 1151 , X86_INS_VPERMB = 1152 , X86_INS_VPERMD = 1153 , X86_INS_VPERMI2B = 1154 , X86_INS_VPERMI2D = 1155 , X86_INS_VPERMI2PD = 1156 , X86_INS_VPERMI2PS = 1157 , X86_INS_VPERMI2Q = 1158 , X86_INS_VPERMI2W = 1159 , X86_INS_VPERMIL2PD = 1160 , X86_INS_VPERMILPD = 1161 , X86_INS_VPERMIL2PS = 1162 , X86_INS_VPERMILPS = 1163 , X86_INS_VPERMPD = 1164 , X86_INS_VPERMPS = 1165 , X86_INS_VPERMQ = 1166 , X86_INS_VPERMT2B = 1167 , X86_INS_VPERMT2D = 1168 , X86_INS_VPERMT2PD = 1169 , X86_INS_VPERMT2PS = 1170 , X86_INS_VPERMT2Q = 1171 , X86_INS_VPERMT2W = 1172 , X86_INS_VPERMW = 1173 , X86_INS_VPEXPANDB = 1174 , X86_INS_VPEXPANDD = 1175 , X86_INS_VPEXPANDQ = 1176 , X86_INS_VPEXPANDW = 1177 , X86_INS_VPEXTRB = 1178 , X86_INS_VPEXTRD = 1179 , X86_INS_VPEXTRQ = 1180 , X86_INS_VPEXTRW = 1181 , X86_INS_VPGATHERDD = 1182 , X86_INS_VPGATHERDQ = 1183 , X86_INS_VPGATHERQD = 1184 , X86_INS_VPGATHERQQ = 1185 , X86_INS_VPHADDBD = 1186 , X86_INS_VPHADDBQ = 1187 , X86_INS_VPHADDBW = 1188 , X86_INS_VPHADDDQ = 1189 , X86_INS_VPHADDD = 1190 , X86_INS_VPHADDSW = 1191 , X86_INS_VPHADDUBD = 1192 , X86_INS_VPHADDUBQ = 1193 , X86_INS_VPHADDUBW = 1194 , X86_INS_VPHADDUDQ = 1195 , X86_INS_VPHADDUWD = 1196 , X86_INS_VPHADDUWQ = 1197 , X86_INS_VPHADDWD = 1198 , X86_INS_VPHADDWQ = 1199 , X86_INS_VPHADDW = 1200 , X86_INS_VPHMINPOSUW = 1201 , X86_INS_VPHSUBBW = 1202 , X86_INS_VPHSUBDQ = 1203 , X86_INS_VPHSUBD = 1204 , X86_INS_VPHSUBSW = 1205 , X86_INS_VPHSUBWD = 1206 , X86_INS_VPHSUBW = 1207 , X86_INS_VPINSRB = 1208 , X86_INS_VPINSRD = 1209 , X86_INS_VPINSRQ = 1210 , X86_INS_VPINSRW = 1211 , X86_INS_VPLZCNTD = 1212 , X86_INS_VPLZCNTQ = 1213 , X86_INS_VPMACSDD = 1214 , X86_INS_VPMACSDQH = 1215 , X86_INS_VPMACSDQL = 1216 , X86_INS_VPMACSSDD = 1217 , X86_INS_VPMACSSDQH = 1218 , X86_INS_VPMACSSDQL = 1219 , X86_INS_VPMACSSWD = 1220 , X86_INS_VPMACSSWW = 1221 , X86_INS_VPMACSWD = 1222 , X86_INS_VPMACSWW = 1223 , X86_INS_VPMADCSSWD = 1224 , X86_INS_VPMADCSWD = 1225 , X86_INS_VPMADD52HUQ = 1226 , X86_INS_VPMADD52LUQ = 1227 , X86_INS_VPMADDUBSW = 1228 , X86_INS_VPMADDWD = 1229 , X86_INS_VPMASKMOVD = 1230 , X86_INS_VPMASKMOVQ = 1231 , X86_INS_VPMAXSB = 1232 , X86_INS_VPMAXSD = 1233 , X86_INS_VPMAXSQ = 1234 , X86_INS_VPMAXSW = 1235 , X86_INS_VPMAXUB = 1236 , X86_INS_VPMAXUD = 1237 , X86_INS_VPMAXUQ = 1238 , X86_INS_VPMAXUW = 1239 , X86_INS_VPMINSB = 1240 , X86_INS_VPMINSD = 1241 , X86_INS_VPMINSQ = 1242 , X86_INS_VPMINSW = 1243 , X86_INS_VPMINUB = 1244 , X86_INS_VPMINUD = 1245 , X86_INS_VPMINUQ = 1246 , X86_INS_VPMINUW = 1247 , X86_INS_VPMOVB2M = 1248 , X86_INS_VPMOVD2M = 1249 , X86_INS_VPMOVDB = 1250 , X86_INS_VPMOVDW = 1251 , X86_INS_VPMOVM2B = 1252 , X86_INS_VPMOVM2D = 1253 , X86_INS_VPMOVM2Q = 1254 , X86_INS_VPMOVM2W = 1255 , X86_INS_VPMOVMSKB = 1256 , X86_INS_VPMOVQ2M = 1257 , X86_INS_VPMOVQB = 1258 , X86_INS_VPMOVQD = 1259 , X86_INS_VPMOVQW = 1260 , X86_INS_VPMOVSDB = 1261 , X86_INS_VPMOVSDW = 1262 , X86_INS_VPMOVSQB = 1263 , X86_INS_VPMOVSQD = 1264 , X86_INS_VPMOVSQW = 1265 , X86_INS_VPMOVSWB = 1266 , X86_INS_VPMOVSXBD = 1267 , X86_INS_VPMOVSXBQ = 1268 , X86_INS_VPMOVSXBW = 1269 , X86_INS_VPMOVSXDQ = 1270 , X86_INS_VPMOVSXWD = 1271 , X86_INS_VPMOVSXWQ = 1272 , X86_INS_VPMOVUSDB = 1273 , X86_INS_VPMOVUSDW = 1274 , X86_INS_VPMOVUSQB = 1275 , X86_INS_VPMOVUSQD = 1276 , X86_INS_VPMOVUSQW = 1277 , X86_INS_VPMOVUSWB = 1278 , X86_INS_VPMOVW2M = 1279 , X86_INS_VPMOVWB = 1280 , X86_INS_VPMOVZXBD = 1281 , X86_INS_VPMOVZXBQ = 1282 , X86_INS_VPMOVZXBW = 1283 , X86_INS_VPMOVZXDQ = 1284 , X86_INS_VPMOVZXWD = 1285 , X86_INS_VPMOVZXWQ = 1286 , X86_INS_VPMULDQ = 1287 , X86_INS_VPMULHRSW = 1288 , X86_INS_VPMULHUW = 1289 , X86_INS_VPMULHW = 1290 , X86_INS_VPMULLD = 1291 , X86_INS_VPMULLQ = 1292 , X86_INS_VPMULLW = 1293 , X86_INS_VPMULTISHIFTQB = 1294 , X86_INS_VPMULUDQ = 1295 , X86_INS_VPOPCNTB = 1296 , X86_INS_VPOPCNTD = 1297 , X86_INS_VPOPCNTQ = 1298 , X86_INS_VPOPCNTW = 1299 , X86_INS_VPORD = 1300 , X86_INS_VPORQ = 1301 , X86_INS_VPOR = 1302 , X86_INS_VPPERM = 1303 , X86_INS_VPROLD = 1304 , X86_INS_VPROLQ = 1305 , X86_INS_VPROLVD = 1306 , X86_INS_VPROLVQ = 1307 , X86_INS_VPRORD = 1308 , X86_INS_VPRORQ = 1309 , X86_INS_VPRORVD = 1310 , X86_INS_VPRORVQ = 1311 , X86_INS_VPROTB = 1312 , X86_INS_VPROTD = 1313 , X86_INS_VPROTQ = 1314 , X86_INS_VPROTW = 1315 , X86_INS_VPSADBW = 1316 , X86_INS_VPSCATTERDD = 1317 , X86_INS_VPSCATTERDQ = 1318 , X86_INS_VPSCATTERQD = 1319 , X86_INS_VPSCATTERQQ = 1320 , X86_INS_VPSHAB = 1321 , X86_INS_VPSHAD = 1322 , X86_INS_VPSHAQ = 1323 , X86_INS_VPSHAW = 1324 , X86_INS_VPSHLB = 1325 , X86_INS_VPSHLDD = 1326 , X86_INS_VPSHLDQ = 1327 , X86_INS_VPSHLDVD = 1328 , X86_INS_VPSHLDVQ = 1329 , X86_INS_VPSHLDVW = 1330 , X86_INS_VPSHLDW = 1331 , X86_INS_VPSHLD = 1332 , X86_INS_VPSHLQ = 1333 , X86_INS_VPSHLW = 1334 , X86_INS_VPSHRDD = 1335 , X86_INS_VPSHRDQ = 1336 , X86_INS_VPSHRDVD = 1337 , X86_INS_VPSHRDVQ = 1338 , X86_INS_VPSHRDVW = 1339 , X86_INS_VPSHRDW = 1340 , X86_INS_VPSHUFBITQMB = 1341 , X86_INS_VPSHUFB = 1342 , X86_INS_VPSHUFD = 1343 , X86_INS_VPSHUFHW = 1344 , X86_INS_VPSHUFLW = 1345 , X86_INS_VPSIGNB = 1346 , X86_INS_VPSIGND = 1347 , X86_INS_VPSIGNW = 1348 , X86_INS_VPSLLDQ = 1349 , X86_INS_VPSLLD = 1350 , X86_INS_VPSLLQ = 1351 , X86_INS_VPSLLVD = 1352 , X86_INS_VPSLLVQ = 1353 , X86_INS_VPSLLVW = 1354 , X86_INS_VPSLLW = 1355 , X86_INS_VPSRAD = 1356 , X86_INS_VPSRAQ = 1357 , X86_INS_VPSRAVD = 1358 , X86_INS_VPSRAVQ = 1359 , X86_INS_VPSRAVW = 1360 , X86_INS_VPSRAW = 1361 , X86_INS_VPSRLDQ = 1362 , X86_INS_VPSRLD = 1363 , X86_INS_VPSRLQ = 1364 , X86_INS_VPSRLVD = 1365 , X86_INS_VPSRLVQ = 1366 , X86_INS_VPSRLVW = 1367 , X86_INS_VPSRLW = 1368 , X86_INS_VPSUBB = 1369 , X86_INS_VPSUBD = 1370 , X86_INS_VPSUBQ = 1371 , X86_INS_VPSUBSB = 1372 , X86_INS_VPSUBSW = 1373 , X86_INS_VPSUBUSB = 1374 , X86_INS_VPSUBUSW = 1375 , X86_INS_VPSUBW = 1376 , X86_INS_VPTERNLOGD = 1377 , X86_INS_VPTERNLOGQ = 1378 , X86_INS_VPTESTMB = 1379 , X86_INS_VPTESTMD = 1380 , X86_INS_VPTESTMQ = 1381 , X86_INS_VPTESTMW = 1382 , X86_INS_VPTESTNMB = 1383 , X86_INS_VPTESTNMD = 1384 , X86_INS_VPTESTNMQ = 1385 , X86_INS_VPTESTNMW = 1386 , X86_INS_VPTEST = 1387 , X86_INS_VPUNPCKHBW = 1388 , X86_INS_VPUNPCKHDQ = 1389 , X86_INS_VPUNPCKHQDQ = 1390 , X86_INS_VPUNPCKHWD = 1391 , X86_INS_VPUNPCKLBW = 1392 , X86_INS_VPUNPCKLDQ = 1393 , X86_INS_VPUNPCKLQDQ = 1394 , X86_INS_VPUNPCKLWD = 1395 , X86_INS_VPXORD = 1396 , X86_INS_VPXORQ = 1397 , X86_INS_VPXOR = 1398 , X86_INS_VRANGEPD = 1399 , X86_INS_VRANGEPS = 1400 , X86_INS_VRANGESD = 1401 , X86_INS_VRANGESS = 1402 , X86_INS_VRCP14PD = 1403 , X86_INS_VRCP14PS = 1404 , X86_INS_VRCP14SD = 1405 , X86_INS_VRCP14SS = 1406 , X86_INS_VRCP28PD = 1407 , X86_INS_VRCP28PS = 1408 , X86_INS_VRCP28SD = 1409 , X86_INS_VRCP28SS = 1410 , X86_INS_VRCPPS = 1411 , X86_INS_VRCPSS = 1412 , X86_INS_VREDUCEPD = 1413 , X86_INS_VREDUCEPS = 1414 , X86_INS_VREDUCESD = 1415 , X86_INS_VREDUCESS = 1416 , X86_INS_VRNDSCALEPD = 1417 , X86_INS_VRNDSCALEPS = 1418 , X86_INS_VRNDSCALESD = 1419 , X86_INS_VRNDSCALESS = 1420 , X86_INS_VROUNDPD = 1421 , X86_INS_VROUNDPS = 1422 , X86_INS_VROUNDSD = 1423 , X86_INS_VROUNDSS = 1424 , X86_INS_VRSQRT14PD = 1425 , X86_INS_VRSQRT14PS = 1426 , X86_INS_VRSQRT14SD = 1427 , X86_INS_VRSQRT14SS = 1428 , X86_INS_VRSQRT28PD = 1429 , X86_INS_VRSQRT28PS = 1430 , X86_INS_VRSQRT28SD = 1431 , X86_INS_VRSQRT28SS = 1432 , X86_INS_VRSQRTPS = 1433 , X86_INS_VRSQRTSS = 1434 , X86_INS_VSCALEFPD = 1435 , X86_INS_VSCALEFPS = 1436 , X86_INS_VSCALEFSD = 1437 , X86_INS_VSCALEFSS = 1438 , X86_INS_VSCATTERDPD = 1439 , X86_INS_VSCATTERDPS = 1440 , X86_INS_VSCATTERPF0DPD = 1441 , X86_INS_VSCATTERPF0DPS = 1442 , X86_INS_VSCATTERPF0QPD = 1443 , X86_INS_VSCATTERPF0QPS = 1444 , X86_INS_VSCATTERPF1DPD = 1445 , X86_INS_VSCATTERPF1DPS = 1446 , X86_INS_VSCATTERPF1QPD = 1447 , X86_INS_VSCATTERPF1QPS = 1448 , X86_INS_VSCATTERQPD = 1449 , X86_INS_VSCATTERQPS = 1450 , X86_INS_VSHUFF32X4 = 1451 , X86_INS_VSHUFF64X2 = 1452 , X86_INS_VSHUFI32X4 = 1453 , X86_INS_VSHUFI64X2 = 1454 , X86_INS_VSHUFPD = 1455 , X86_INS_VSHUFPS = 1456 , X86_INS_VSQRTPD = 1457 , X86_INS_VSQRTPS = 1458 , X86_INS_VSQRTSD = 1459 , X86_INS_VSQRTSS = 1460 , X86_INS_VSTMXCSR = 1461 , X86_INS_VSUBPD = 1462 , X86_INS_VSUBPS = 1463 , X86_INS_VSUBSD = 1464 , X86_INS_VSUBSS = 1465 , X86_INS_VTESTPD = 1466 , X86_INS_VTESTPS = 1467 , X86_INS_VUCOMISD = 1468 , X86_INS_VUCOMISS = 1469 , X86_INS_VUNPCKHPD = 1470 , X86_INS_VUNPCKHPS = 1471 , X86_INS_VUNPCKLPD = 1472 , X86_INS_VUNPCKLPS = 1473 , X86_INS_VXORPD = 1474 , X86_INS_VXORPS = 1475 , X86_INS_VZEROALL = 1476 , X86_INS_VZEROUPPER = 1477 , X86_INS_WAIT = 1478 , X86_INS_WBINVD = 1479 , X86_INS_WBNOINVD = 1480 , X86_INS_WRFSBASE = 1481 , X86_INS_WRGSBASE = 1482 , X86_INS_WRMSR = 1483 , X86_INS_WRPKRU = 1484 , X86_INS_WRSSD = 1485 , X86_INS_WRSSQ = 1486 , X86_INS_WRUSSD = 1487 , X86_INS_WRUSSQ = 1488 , X86_INS_XABORT = 1489 , X86_INS_XACQUIRE = 1490 , X86_INS_XADD = 1491 , X86_INS_XBEGIN = 1492 , X86_INS_XCHG = 1493 , X86_INS_FXCH = 1494 , X86_INS_XCRYPTCBC = 1495 , X86_INS_XCRYPTCFB = 1496 , X86_INS_XCRYPTCTR = 1497 , X86_INS_XCRYPTECB = 1498 , X86_INS_XCRYPTOFB = 1499 , X86_INS_XEND = 1500 , X86_INS_XGETBV = 1501 , X86_INS_XLATB = 1502 , X86_INS_XOR = 1503 , X86_INS_XORPD = 1504 , X86_INS_XORPS = 1505 , X86_INS_XRELEASE = 1506 , X86_INS_XRSTOR = 1507 , X86_INS_XRSTOR64 = 1508 , X86_INS_XRSTORS = 1509 , X86_INS_XRSTORS64 = 1510 , X86_INS_XSAVE = 1511 , X86_INS_XSAVE64 = 1512 , X86_INS_XSAVEC = 1513 , X86_INS_XSAVEC64 = 1514 , X86_INS_XSAVEOPT = 1515 , X86_INS_XSAVEOPT64 = 1516 , X86_INS_XSAVES = 1517 , X86_INS_XSAVES64 = 1518 , X86_INS_XSETBV = 1519 , X86_INS_XSHA1 = 1520 , X86_INS_XSHA256 = 1521 , X86_INS_XSTORE = 1522 , X86_INS_XTEST = 1523 , X86_INS_ENDING = 1524 , } # [repr (u32)] # [doc = " Group of X86 instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum x86_insn_group { # [doc = "< = CS_GRP_INVALID"] X86_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] X86_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] X86_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] X86_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] X86_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] X86_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] X86_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] X86_GRP_BRANCH_RELATIVE = 7 , # [doc = "< all virtualization instructions (VT-x + AMD-V)"] X86_GRP_VM = 128 , X86_GRP_3DNOW = 129 , X86_GRP_AES = 130 , X86_GRP_ADX = 131 , X86_GRP_AVX = 132 , X86_GRP_AVX2 = 133 , X86_GRP_AVX512 = 134 , X86_GRP_BMI = 135 , X86_GRP_BMI2 = 136 , X86_GRP_CMOV = 137 , X86_GRP_F16C = 138 , X86_GRP_FMA = 139 , X86_GRP_FMA4 = 140 , X86_GRP_FSGSBASE = 141 , X86_GRP_HLE = 142 , X86_GRP_MMX = 143 , X86_GRP_MODE32 = 144 , X86_GRP_MODE64 = 145 , X86_GRP_RTM = 146 , X86_GRP_SHA = 147 , X86_GRP_SSE1 = 148 , X86_GRP_SSE2 = 149 , X86_GRP_SSE3 = 150 , X86_GRP_SSE41 = 151 , X86_GRP_SSE42 = 152 , X86_GRP_SSE4A = 153 , X86_GRP_SSSE3 = 154 , X86_GRP_PCLMUL = 155 , X86_GRP_XOP = 156 , X86_GRP_CDI = 157 , X86_GRP_ERI = 158 , X86_GRP_TBM = 159 , X86_GRP_16BITMODE = 160 , X86_GRP_NOT64BITMODE = 161 , X86_GRP_SGX = 162 , X86_GRP_DQI = 163 , X86_GRP_BWI = 164 , X86_GRP_PFI = 165 , X86_GRP_VLX = 166 , X86_GRP_SMAP = 167 , X86_GRP_NOVLX = 168 , X86_GRP_FPU = 169 , X86_GRP_ENDING = 170 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] XCORE_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] XCORE_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] XCORE_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] XCORE_OP_MEM = 3 , } # [repr (u32)] # [doc = " XCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_reg { XCORE_REG_INVALID = 0 , XCORE_REG_CP = 1 , XCORE_REG_DP = 2 , XCORE_REG_LR = 3 , XCORE_REG_SP = 4 , XCORE_REG_R0 = 5 , XCORE_REG_R1 = 6 , XCORE_REG_R2 = 7 , XCORE_REG_R3 = 8 , XCORE_REG_R4 = 9 , XCORE_REG_R5 = 10 , XCORE_REG_R6 = 11 , XCORE_REG_R7 = 12 , XCORE_REG_R8 = 13 , XCORE_REG_R9 = 14 , XCORE_REG_R10 = 15 , XCORE_REG_R11 = 16 , # [doc = "< pc"] XCORE_REG_PC = 17 , # [doc = "< save pc"] XCORE_REG_SCP = 18 , XCORE_REG_SSR = 19 , XCORE_REG_ET = 20 , XCORE_REG_ED = 21 , XCORE_REG_SED = 22 , XCORE_REG_KEP = 23 , XCORE_REG_KSP = 24 , XCORE_REG_ID = 25 , XCORE_REG_ENDING = 26 , } # [doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct xcore_op_mem { # [doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"] pub base : u8 , # [doc = "< index register, same conditions apply here"] pub index : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , # [doc = "< +1: forward, -1: backward"] pub direct : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of xcore_op_mem"] [:: std :: mem :: size_of :: < xcore_op_mem > () - 12usize] ; ["Alignment of xcore_op_mem"] [:: std :: mem :: align_of :: < xcore_op_mem > () - 4usize] ; ["Offset of field: xcore_op_mem::base"] [:: std :: mem :: offset_of ! (xcore_op_mem , base) - 0usize] ; ["Offset of field: xcore_op_mem::index"] [:: std :: mem :: offset_of ! (xcore_op_mem , index) - 1usize] ; ["Offset of field: xcore_op_mem::disp"] [:: std :: mem :: offset_of ! (xcore_op_mem , disp) - 4usize] ; ["Offset of field: xcore_op_mem::direct"] [:: std :: mem :: offset_of ! (xcore_op_mem , direct) - 8usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore_op { # [doc = "< operand type"] pub type_ : xcore_op_type , pub __bindgen_anon_1 : cs_xcore_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_xcore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : xcore_reg , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : xcore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_xcore_op__bindgen_ty_1 > () - 12usize] ; ["Alignment of cs_xcore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_xcore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_xcore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_xcore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore_op"] [:: std :: mem :: size_of :: < cs_xcore_op > () - 16usize] ; ["Alignment of cs_xcore_op"] [:: std :: mem :: align_of :: < cs_xcore_op > () - 4usize] ; ["Offset of field: cs_xcore_op::type_"] [:: std :: mem :: offset_of ! (cs_xcore_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_xcore { # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_xcore_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_xcore"] [:: std :: mem :: size_of :: < cs_xcore > () - 132usize] ; ["Alignment of cs_xcore"] [:: std :: mem :: align_of :: < cs_xcore > () - 4usize] ; ["Offset of field: cs_xcore::op_count"] [:: std :: mem :: offset_of ! (cs_xcore , op_count) - 0usize] ; ["Offset of field: cs_xcore::operands"] [:: std :: mem :: offset_of ! (cs_xcore , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_xcore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_xcore {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " XCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn { XCORE_INS_INVALID = 0 , XCORE_INS_ADD = 1 , XCORE_INS_ANDNOT = 2 , XCORE_INS_AND = 3 , XCORE_INS_ASHR = 4 , XCORE_INS_BAU = 5 , XCORE_INS_BITREV = 6 , XCORE_INS_BLA = 7 , XCORE_INS_BLAT = 8 , XCORE_INS_BL = 9 , XCORE_INS_BF = 10 , XCORE_INS_BT = 11 , XCORE_INS_BU = 12 , XCORE_INS_BRU = 13 , XCORE_INS_BYTEREV = 14 , XCORE_INS_CHKCT = 15 , XCORE_INS_CLRE = 16 , XCORE_INS_CLRPT = 17 , XCORE_INS_CLRSR = 18 , XCORE_INS_CLZ = 19 , XCORE_INS_CRC8 = 20 , XCORE_INS_CRC32 = 21 , XCORE_INS_DCALL = 22 , XCORE_INS_DENTSP = 23 , XCORE_INS_DGETREG = 24 , XCORE_INS_DIVS = 25 , XCORE_INS_DIVU = 26 , XCORE_INS_DRESTSP = 27 , XCORE_INS_DRET = 28 , XCORE_INS_ECALLF = 29 , XCORE_INS_ECALLT = 30 , XCORE_INS_EDU = 31 , XCORE_INS_EEF = 32 , XCORE_INS_EET = 33 , XCORE_INS_EEU = 34 , XCORE_INS_ENDIN = 35 , XCORE_INS_ENTSP = 36 , XCORE_INS_EQ = 37 , XCORE_INS_EXTDP = 38 , XCORE_INS_EXTSP = 39 , XCORE_INS_FREER = 40 , XCORE_INS_FREET = 41 , XCORE_INS_GETD = 42 , XCORE_INS_GET = 43 , XCORE_INS_GETN = 44 , XCORE_INS_GETR = 45 , XCORE_INS_GETSR = 46 , XCORE_INS_GETST = 47 , XCORE_INS_GETTS = 48 , XCORE_INS_INCT = 49 , XCORE_INS_INIT = 50 , XCORE_INS_INPW = 51 , XCORE_INS_INSHR = 52 , XCORE_INS_INT = 53 , XCORE_INS_IN = 54 , XCORE_INS_KCALL = 55 , XCORE_INS_KENTSP = 56 , XCORE_INS_KRESTSP = 57 , XCORE_INS_KRET = 58 , XCORE_INS_LADD = 59 , XCORE_INS_LD16S = 60 , XCORE_INS_LD8U = 61 , XCORE_INS_LDA16 = 62 , XCORE_INS_LDAP = 63 , XCORE_INS_LDAW = 64 , XCORE_INS_LDC = 65 , XCORE_INS_LDW = 66 , XCORE_INS_LDIVU = 67 , XCORE_INS_LMUL = 68 , XCORE_INS_LSS = 69 , XCORE_INS_LSUB = 70 , XCORE_INS_LSU = 71 , XCORE_INS_MACCS = 72 , XCORE_INS_MACCU = 73 , XCORE_INS_MJOIN = 74 , XCORE_INS_MKMSK = 75 , XCORE_INS_MSYNC = 76 , XCORE_INS_MUL = 77 , XCORE_INS_NEG = 78 , XCORE_INS_NOT = 79 , XCORE_INS_OR = 80 , XCORE_INS_OUTCT = 81 , XCORE_INS_OUTPW = 82 , XCORE_INS_OUTSHR = 83 , XCORE_INS_OUTT = 84 , XCORE_INS_OUT = 85 , XCORE_INS_PEEK = 86 , XCORE_INS_REMS = 87 , XCORE_INS_REMU = 88 , XCORE_INS_RETSP = 89 , XCORE_INS_SETCLK = 90 , XCORE_INS_SET = 91 , XCORE_INS_SETC = 92 , XCORE_INS_SETD = 93 , XCORE_INS_SETEV = 94 , XCORE_INS_SETN = 95 , XCORE_INS_SETPSC = 96 , XCORE_INS_SETPT = 97 , XCORE_INS_SETRDY = 98 , XCORE_INS_SETSR = 99 , XCORE_INS_SETTW = 100 , XCORE_INS_SETV = 101 , XCORE_INS_SEXT = 102 , XCORE_INS_SHL = 103 , XCORE_INS_SHR = 104 , XCORE_INS_SSYNC = 105 , XCORE_INS_ST16 = 106 , XCORE_INS_ST8 = 107 , XCORE_INS_STW = 108 , XCORE_INS_SUB = 109 , XCORE_INS_SYNCR = 110 , XCORE_INS_TESTCT = 111 , XCORE_INS_TESTLCL = 112 , XCORE_INS_TESTWCT = 113 , XCORE_INS_TSETMR = 114 , XCORE_INS_START = 115 , XCORE_INS_WAITEF = 116 , XCORE_INS_WAITET = 117 , XCORE_INS_WAITEU = 118 , XCORE_INS_XOR = 119 , XCORE_INS_ZEXT = 120 , XCORE_INS_ENDING = 121 , } # [repr (u32)] # [doc = " Group of XCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum xcore_insn_group { # [doc = "< = CS_GRP_INVALID"] XCORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] XCORE_GRP_JUMP = 1 , XCORE_GRP_ENDING = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] TMS320C64X_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] TMS320C64X_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] TMS320C64X_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] TMS320C64X_OP_MEM = 3 , # [doc = "< Register pair for double word ops"] TMS320C64X_OP_REGPAIR = 64 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0 , TMS320C64X_MEM_DISP_CONSTANT = 1 , TMS320C64X_MEM_DISP_REGISTER = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0 , TMS320C64X_MEM_DIR_FW = 1 , TMS320C64X_MEM_DIR_BW = 2 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0 , TMS320C64X_MEM_MOD_NO = 1 , TMS320C64X_MEM_MOD_PRE = 2 , TMS320C64X_MEM_MOD_POST = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tms320c64x_op_mem { # [doc = "< base register"] pub base : :: std :: os :: raw :: c_uint , # [doc = "< displacement/offset value"] pub disp : :: std :: os :: raw :: c_uint , # [doc = "< unit of base and offset register"] pub unit : :: std :: os :: raw :: c_uint , # [doc = "< offset scaled"] pub scaled : :: std :: os :: raw :: c_uint , # [doc = "< displacement type"] pub disptype : :: std :: os :: raw :: c_uint , # [doc = "< direction"] pub direction : :: std :: os :: raw :: c_uint , # [doc = "< modification"] pub modify : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tms320c64x_op_mem"] [:: std :: mem :: size_of :: < tms320c64x_op_mem > () - 28usize] ; ["Alignment of tms320c64x_op_mem"] [:: std :: mem :: align_of :: < tms320c64x_op_mem > () - 4usize] ; ["Offset of field: tms320c64x_op_mem::base"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , base) - 0usize] ; ["Offset of field: tms320c64x_op_mem::disp"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disp) - 4usize] ; ["Offset of field: tms320c64x_op_mem::unit"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , unit) - 8usize] ; ["Offset of field: tms320c64x_op_mem::scaled"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , scaled) - 12usize] ; ["Offset of field: tms320c64x_op_mem::disptype"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , disptype) - 16usize] ; ["Offset of field: tms320c64x_op_mem::direction"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , direction) - 20usize] ; ["Offset of field: tms320c64x_op_mem::modify"] [:: std :: mem :: offset_of ! (tms320c64x_op_mem , modify) - 24usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x_op { # [doc = "< operand type"] pub type_ : tms320c64x_op_type , pub __bindgen_anon_1 : cs_tms320c64x_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tms320c64x_op__bindgen_ty_1 { # [doc = "< register value for REG operand or first register for REGPAIR operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tms320c64x_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 28usize] ; ["Alignment of cs_tms320c64x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tms320c64x_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x_op"] [:: std :: mem :: size_of :: < cs_tms320c64x_op > () - 32usize] ; ["Alignment of cs_tms320c64x_op"] [:: std :: mem :: align_of :: < cs_tms320c64x_op > () - 4usize] ; ["Offset of field: cs_tms320c64x_op::type_"] [:: std :: mem :: offset_of ! (cs_tms320c64x_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tms320c64x { pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tms320c64x_op ; 8usize] , pub condition : cs_tms320c64x__bindgen_ty_1 , pub funit : cs_tms320c64x__bindgen_ty_2 , pub parallel : :: std :: os :: raw :: c_uint , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub zero : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_1::zero"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_1 , zero) - 4usize] ; } ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_tms320c64x__bindgen_ty_2 { pub unit : :: std :: os :: raw :: c_uint , pub side : :: std :: os :: raw :: c_uint , pub crosspath : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: size_of :: < cs_tms320c64x__bindgen_ty_2 > () - 12usize] ; ["Alignment of cs_tms320c64x__bindgen_ty_2"] [:: std :: mem :: align_of :: < cs_tms320c64x__bindgen_ty_2 > () - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::unit"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , unit) - 0usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::side"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , side) - 4usize] ; ["Offset of field: cs_tms320c64x__bindgen_ty_2::crosspath"] [:: std :: mem :: offset_of ! (cs_tms320c64x__bindgen_ty_2 , crosspath) - 8usize] ; } ; # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tms320c64x"] [:: std :: mem :: size_of :: < cs_tms320c64x > () - 284usize] ; ["Alignment of cs_tms320c64x"] [:: std :: mem :: align_of :: < cs_tms320c64x > () - 4usize] ; ["Offset of field: cs_tms320c64x::op_count"] [:: std :: mem :: offset_of ! (cs_tms320c64x , op_count) - 0usize] ; ["Offset of field: cs_tms320c64x::operands"] [:: std :: mem :: offset_of ! (cs_tms320c64x , operands) - 4usize] ; ["Offset of field: cs_tms320c64x::condition"] [:: std :: mem :: offset_of ! (cs_tms320c64x , condition) - 260usize] ; ["Offset of field: cs_tms320c64x::funit"] [:: std :: mem :: offset_of ! (cs_tms320c64x , funit) - 268usize] ; ["Offset of field: cs_tms320c64x::parallel"] [:: std :: mem :: offset_of ! (cs_tms320c64x , parallel) - 280usize] ; } ; impl :: std :: fmt :: Debug for cs_tms320c64x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel) } } impl tms320c64x_reg { pub const TMS320C64X_REG_EFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ECR ; } impl tms320c64x_reg { pub const TMS320C64X_REG_IFR : tms320c64x_reg = tms320c64x_reg :: TMS320C64X_REG_ISR ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0 , TMS320C64X_REG_AMR = 1 , TMS320C64X_REG_CSR = 2 , TMS320C64X_REG_DIER = 3 , TMS320C64X_REG_DNUM = 4 , TMS320C64X_REG_ECR = 5 , TMS320C64X_REG_GFPGFR = 6 , TMS320C64X_REG_GPLYA = 7 , TMS320C64X_REG_GPLYB = 8 , TMS320C64X_REG_ICR = 9 , TMS320C64X_REG_IER = 10 , TMS320C64X_REG_IERR = 11 , TMS320C64X_REG_ILC = 12 , TMS320C64X_REG_IRP = 13 , TMS320C64X_REG_ISR = 14 , TMS320C64X_REG_ISTP = 15 , TMS320C64X_REG_ITSR = 16 , TMS320C64X_REG_NRP = 17 , TMS320C64X_REG_NTSR = 18 , TMS320C64X_REG_REP = 19 , TMS320C64X_REG_RILC = 20 , TMS320C64X_REG_SSR = 21 , TMS320C64X_REG_TSCH = 22 , TMS320C64X_REG_TSCL = 23 , TMS320C64X_REG_TSR = 24 , TMS320C64X_REG_A0 = 25 , TMS320C64X_REG_A1 = 26 , TMS320C64X_REG_A2 = 27 , TMS320C64X_REG_A3 = 28 , TMS320C64X_REG_A4 = 29 , TMS320C64X_REG_A5 = 30 , TMS320C64X_REG_A6 = 31 , TMS320C64X_REG_A7 = 32 , TMS320C64X_REG_A8 = 33 , TMS320C64X_REG_A9 = 34 , TMS320C64X_REG_A10 = 35 , TMS320C64X_REG_A11 = 36 , TMS320C64X_REG_A12 = 37 , TMS320C64X_REG_A13 = 38 , TMS320C64X_REG_A14 = 39 , TMS320C64X_REG_A15 = 40 , TMS320C64X_REG_A16 = 41 , TMS320C64X_REG_A17 = 42 , TMS320C64X_REG_A18 = 43 , TMS320C64X_REG_A19 = 44 , TMS320C64X_REG_A20 = 45 , TMS320C64X_REG_A21 = 46 , TMS320C64X_REG_A22 = 47 , TMS320C64X_REG_A23 = 48 , TMS320C64X_REG_A24 = 49 , TMS320C64X_REG_A25 = 50 , TMS320C64X_REG_A26 = 51 , TMS320C64X_REG_A27 = 52 , TMS320C64X_REG_A28 = 53 , TMS320C64X_REG_A29 = 54 , TMS320C64X_REG_A30 = 55 , TMS320C64X_REG_A31 = 56 , TMS320C64X_REG_B0 = 57 , TMS320C64X_REG_B1 = 58 , TMS320C64X_REG_B2 = 59 , TMS320C64X_REG_B3 = 60 , TMS320C64X_REG_B4 = 61 , TMS320C64X_REG_B5 = 62 , TMS320C64X_REG_B6 = 63 , TMS320C64X_REG_B7 = 64 , TMS320C64X_REG_B8 = 65 , TMS320C64X_REG_B9 = 66 , TMS320C64X_REG_B10 = 67 , TMS320C64X_REG_B11 = 68 , TMS320C64X_REG_B12 = 69 , TMS320C64X_REG_B13 = 70 , TMS320C64X_REG_B14 = 71 , TMS320C64X_REG_B15 = 72 , TMS320C64X_REG_B16 = 73 , TMS320C64X_REG_B17 = 74 , TMS320C64X_REG_B18 = 75 , TMS320C64X_REG_B19 = 76 , TMS320C64X_REG_B20 = 77 , TMS320C64X_REG_B21 = 78 , TMS320C64X_REG_B22 = 79 , TMS320C64X_REG_B23 = 80 , TMS320C64X_REG_B24 = 81 , TMS320C64X_REG_B25 = 82 , TMS320C64X_REG_B26 = 83 , TMS320C64X_REG_B27 = 84 , TMS320C64X_REG_B28 = 85 , TMS320C64X_REG_B29 = 86 , TMS320C64X_REG_B30 = 87 , TMS320C64X_REG_B31 = 88 , TMS320C64X_REG_PCE1 = 89 , TMS320C64X_REG_ENDING = 90 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0 , TMS320C64X_INS_ABS = 1 , TMS320C64X_INS_ABS2 = 2 , TMS320C64X_INS_ADD = 3 , TMS320C64X_INS_ADD2 = 4 , TMS320C64X_INS_ADD4 = 5 , TMS320C64X_INS_ADDAB = 6 , TMS320C64X_INS_ADDAD = 7 , TMS320C64X_INS_ADDAH = 8 , TMS320C64X_INS_ADDAW = 9 , TMS320C64X_INS_ADDK = 10 , TMS320C64X_INS_ADDKPC = 11 , TMS320C64X_INS_ADDU = 12 , TMS320C64X_INS_AND = 13 , TMS320C64X_INS_ANDN = 14 , TMS320C64X_INS_AVG2 = 15 , TMS320C64X_INS_AVGU4 = 16 , TMS320C64X_INS_B = 17 , TMS320C64X_INS_BDEC = 18 , TMS320C64X_INS_BITC4 = 19 , TMS320C64X_INS_BNOP = 20 , TMS320C64X_INS_BPOS = 21 , TMS320C64X_INS_CLR = 22 , TMS320C64X_INS_CMPEQ = 23 , TMS320C64X_INS_CMPEQ2 = 24 , TMS320C64X_INS_CMPEQ4 = 25 , TMS320C64X_INS_CMPGT = 26 , TMS320C64X_INS_CMPGT2 = 27 , TMS320C64X_INS_CMPGTU4 = 28 , TMS320C64X_INS_CMPLT = 29 , TMS320C64X_INS_CMPLTU = 30 , TMS320C64X_INS_DEAL = 31 , TMS320C64X_INS_DOTP2 = 32 , TMS320C64X_INS_DOTPN2 = 33 , TMS320C64X_INS_DOTPNRSU2 = 34 , TMS320C64X_INS_DOTPRSU2 = 35 , TMS320C64X_INS_DOTPSU4 = 36 , TMS320C64X_INS_DOTPU4 = 37 , TMS320C64X_INS_EXT = 38 , TMS320C64X_INS_EXTU = 39 , TMS320C64X_INS_GMPGTU = 40 , TMS320C64X_INS_GMPY4 = 41 , TMS320C64X_INS_LDB = 42 , TMS320C64X_INS_LDBU = 43 , TMS320C64X_INS_LDDW = 44 , TMS320C64X_INS_LDH = 45 , TMS320C64X_INS_LDHU = 46 , TMS320C64X_INS_LDNDW = 47 , TMS320C64X_INS_LDNW = 48 , TMS320C64X_INS_LDW = 49 , TMS320C64X_INS_LMBD = 50 , TMS320C64X_INS_MAX2 = 51 , TMS320C64X_INS_MAXU4 = 52 , TMS320C64X_INS_MIN2 = 53 , TMS320C64X_INS_MINU4 = 54 , TMS320C64X_INS_MPY = 55 , TMS320C64X_INS_MPY2 = 56 , TMS320C64X_INS_MPYH = 57 , TMS320C64X_INS_MPYHI = 58 , TMS320C64X_INS_MPYHIR = 59 , TMS320C64X_INS_MPYHL = 60 , TMS320C64X_INS_MPYHLU = 61 , TMS320C64X_INS_MPYHSLU = 62 , TMS320C64X_INS_MPYHSU = 63 , TMS320C64X_INS_MPYHU = 64 , TMS320C64X_INS_MPYHULS = 65 , TMS320C64X_INS_MPYHUS = 66 , TMS320C64X_INS_MPYLH = 67 , TMS320C64X_INS_MPYLHU = 68 , TMS320C64X_INS_MPYLI = 69 , TMS320C64X_INS_MPYLIR = 70 , TMS320C64X_INS_MPYLSHU = 71 , TMS320C64X_INS_MPYLUHS = 72 , TMS320C64X_INS_MPYSU = 73 , TMS320C64X_INS_MPYSU4 = 74 , TMS320C64X_INS_MPYU = 75 , TMS320C64X_INS_MPYU4 = 76 , TMS320C64X_INS_MPYUS = 77 , TMS320C64X_INS_MVC = 78 , TMS320C64X_INS_MVD = 79 , TMS320C64X_INS_MVK = 80 , TMS320C64X_INS_MVKL = 81 , TMS320C64X_INS_MVKLH = 82 , TMS320C64X_INS_NOP = 83 , TMS320C64X_INS_NORM = 84 , TMS320C64X_INS_OR = 85 , TMS320C64X_INS_PACK2 = 86 , TMS320C64X_INS_PACKH2 = 87 , TMS320C64X_INS_PACKH4 = 88 , TMS320C64X_INS_PACKHL2 = 89 , TMS320C64X_INS_PACKL4 = 90 , TMS320C64X_INS_PACKLH2 = 91 , TMS320C64X_INS_ROTL = 92 , TMS320C64X_INS_SADD = 93 , TMS320C64X_INS_SADD2 = 94 , TMS320C64X_INS_SADDU4 = 95 , TMS320C64X_INS_SADDUS2 = 96 , TMS320C64X_INS_SAT = 97 , TMS320C64X_INS_SET = 98 , TMS320C64X_INS_SHFL = 99 , TMS320C64X_INS_SHL = 100 , TMS320C64X_INS_SHLMB = 101 , TMS320C64X_INS_SHR = 102 , TMS320C64X_INS_SHR2 = 103 , TMS320C64X_INS_SHRMB = 104 , TMS320C64X_INS_SHRU = 105 , TMS320C64X_INS_SHRU2 = 106 , TMS320C64X_INS_SMPY = 107 , TMS320C64X_INS_SMPY2 = 108 , TMS320C64X_INS_SMPYH = 109 , TMS320C64X_INS_SMPYHL = 110 , TMS320C64X_INS_SMPYLH = 111 , TMS320C64X_INS_SPACK2 = 112 , TMS320C64X_INS_SPACKU4 = 113 , TMS320C64X_INS_SSHL = 114 , TMS320C64X_INS_SSHVL = 115 , TMS320C64X_INS_SSHVR = 116 , TMS320C64X_INS_SSUB = 117 , TMS320C64X_INS_STB = 118 , TMS320C64X_INS_STDW = 119 , TMS320C64X_INS_STH = 120 , TMS320C64X_INS_STNDW = 121 , TMS320C64X_INS_STNW = 122 , TMS320C64X_INS_STW = 123 , TMS320C64X_INS_SUB = 124 , TMS320C64X_INS_SUB2 = 125 , TMS320C64X_INS_SUB4 = 126 , TMS320C64X_INS_SUBAB = 127 , TMS320C64X_INS_SUBABS4 = 128 , TMS320C64X_INS_SUBAH = 129 , TMS320C64X_INS_SUBAW = 130 , TMS320C64X_INS_SUBC = 131 , TMS320C64X_INS_SUBU = 132 , TMS320C64X_INS_SWAP4 = 133 , TMS320C64X_INS_UNPKHU4 = 134 , TMS320C64X_INS_UNPKLU4 = 135 , TMS320C64X_INS_XOR = 136 , TMS320C64X_INS_XPND2 = 137 , TMS320C64X_INS_XPND4 = 138 , TMS320C64X_INS_IDLE = 139 , TMS320C64X_INS_MV = 140 , TMS320C64X_INS_NEG = 141 , TMS320C64X_INS_NOT = 142 , TMS320C64X_INS_SWAP2 = 143 , TMS320C64X_INS_ZERO = 144 , TMS320C64X_INS_ENDING = 145 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_insn_group { # [doc = "< = CS_GRP_INVALID"] TMS320C64X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] TMS320C64X_GRP_JUMP = 1 , TMS320C64X_GRP_FUNIT_D = 128 , TMS320C64X_GRP_FUNIT_L = 129 , TMS320C64X_GRP_FUNIT_M = 130 , TMS320C64X_GRP_FUNIT_S = 131 , TMS320C64X_GRP_FUNIT_NO = 132 , TMS320C64X_GRP_ENDING = 133 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0 , TMS320C64X_FUNIT_D = 1 , TMS320C64X_FUNIT_L = 2 , TMS320C64X_FUNIT_M = 3 , TMS320C64X_FUNIT_S = 4 , TMS320C64X_FUNIT_NO = 5 , } # [repr (u32)] # [doc = " M680X registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_reg { M680X_REG_INVALID = 0 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_A = 1 , # [doc = "< M6800/1/2/3/9, HD6301/9"] M680X_REG_B = 2 , # [doc = "< HD6309"] M680X_REG_E = 3 , # [doc = "< HD6309"] M680X_REG_F = 4 , # [doc = "< HD6309"] M680X_REG_0 = 5 , # [doc = "< M6801/3/9, HD6301/9"] M680X_REG_D = 6 , # [doc = "< HD6309"] M680X_REG_W = 7 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_CC = 8 , # [doc = "< M6809/M6309"] M680X_REG_DP = 9 , # [doc = "< M6309"] M680X_REG_MD = 10 , # [doc = "< M6808"] M680X_REG_HX = 11 , # [doc = "< M6808"] M680X_REG_H = 12 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_X = 13 , # [doc = "< M6809/M6309"] M680X_REG_Y = 14 , # [doc = "< M6809/M6309"] M680X_REG_S = 15 , # [doc = "< M6809/M6309"] M680X_REG_U = 16 , # [doc = "< M6309"] M680X_REG_V = 17 , # [doc = "< M6309"] M680X_REG_Q = 18 , # [doc = "< M6800/1/2/3/9, M6301/9"] M680X_REG_PC = 19 , # [doc = "< CPU12"] M680X_REG_TMP2 = 20 , # [doc = "< CPU12"] M680X_REG_TMP3 = 21 , # [doc = "< <-- mark the end of the list of registers"] M680X_REG_ENDING = 22 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] M680X_OP_INVALID = 0 , # [doc = "< = Register operand."] M680X_OP_REGISTER = 1 , # [doc = "< = Immediate operand."] M680X_OP_IMMEDIATE = 2 , # [doc = "< = Indexed addressing operand."] M680X_OP_INDEXED = 3 , # [doc = "< = Extended addressing operand."] M680X_OP_EXTENDED = 4 , # [doc = "< = Direct addressing operand."] M680X_OP_DIRECT = 5 , # [doc = "< = Relative addressing operand."] M680X_OP_RELATIVE = 6 , # [doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."] M680X_OP_CONSTANT = 7 , } # [doc = " Instruction's operand referring to indexed addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_idx { # [doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"] pub base_reg : m680x_reg , # [doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"] pub offset_reg : m680x_reg , # [doc = "< 5-,8- or 16-bit offset. See also offset_bits."] pub offset : i16 , # [doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"] pub offset_addr : u16 , # [doc = "< offset width in bits for indexed addressing"] pub offset_bits : u8 , # [doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"] pub inc_dec : i8 , # [doc = "< 8-bit flags (see above)"] pub flags : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_idx"] [:: std :: mem :: size_of :: < m680x_op_idx > () - 16usize] ; ["Alignment of m680x_op_idx"] [:: std :: mem :: align_of :: < m680x_op_idx > () - 4usize] ; ["Offset of field: m680x_op_idx::base_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , base_reg) - 0usize] ; ["Offset of field: m680x_op_idx::offset_reg"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_reg) - 4usize] ; ["Offset of field: m680x_op_idx::offset"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset) - 8usize] ; ["Offset of field: m680x_op_idx::offset_addr"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_addr) - 10usize] ; ["Offset of field: m680x_op_idx::offset_bits"] [:: std :: mem :: offset_of ! (m680x_op_idx , offset_bits) - 12usize] ; ["Offset of field: m680x_op_idx::inc_dec"] [:: std :: mem :: offset_of ! (m680x_op_idx , inc_dec) - 13usize] ; ["Offset of field: m680x_op_idx::flags"] [:: std :: mem :: offset_of ! (m680x_op_idx , flags) - 14usize] ; } ; # [doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_rel { # [doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."] pub address : u16 , # [doc = "< the offset/displacement value"] pub offset : i16 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_rel"] [:: std :: mem :: size_of :: < m680x_op_rel > () - 4usize] ; ["Alignment of m680x_op_rel"] [:: std :: mem :: align_of :: < m680x_op_rel > () - 2usize] ; ["Offset of field: m680x_op_rel::address"] [:: std :: mem :: offset_of ! (m680x_op_rel , address) - 0usize] ; ["Offset of field: m680x_op_rel::offset"] [:: std :: mem :: offset_of ! (m680x_op_rel , offset) - 2usize] ; } ; # [doc = " Instruction's operand referring to extended addressing"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct m680x_op_ext { # [doc = "< The absolute address"] pub address : u16 , # [doc = "< true if extended indirect addressing"] pub indirect : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of m680x_op_ext"] [:: std :: mem :: size_of :: < m680x_op_ext > () - 4usize] ; ["Alignment of m680x_op_ext"] [:: std :: mem :: align_of :: < m680x_op_ext > () - 2usize] ; ["Offset of field: m680x_op_ext::address"] [:: std :: mem :: offset_of ! (m680x_op_ext , address) - 0usize] ; ["Offset of field: m680x_op_ext::indirect"] [:: std :: mem :: offset_of ! (m680x_op_ext , indirect) - 2usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x_op { pub type_ : m680x_op_type , pub __bindgen_anon_1 : cs_m680x_op__bindgen_ty_1 , # [doc = "< size of this operand (in bytes)"] pub size : u8 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_m680x_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< register value for REG operand"] pub reg : m680x_reg , # [doc = "< Indexed addressing operand"] pub idx : m680x_op_idx , # [doc = "< Relative address. operand (Bcc/LBcc)"] pub rel : m680x_op_rel , # [doc = "< Extended address"] pub ext : m680x_op_ext , # [doc = "<</ Direct address (lower 8-bit)"] pub direct_addr : u8 , # [doc = "< constant value (bit index, page nr.)"] pub const_val : u8 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_m680x_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_m680x_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_m680x_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::idx"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , idx) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::rel"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , rel) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , ext) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::direct_addr"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , direct_addr) - 0usize] ; ["Offset of field: cs_m680x_op__bindgen_ty_1::const_val"] [:: std :: mem :: offset_of ! (cs_m680x_op__bindgen_ty_1 , const_val) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x_op"] [:: std :: mem :: size_of :: < cs_m680x_op > () - 24usize] ; ["Alignment of cs_m680x_op"] [:: std :: mem :: align_of :: < cs_m680x_op > () - 4usize] ; ["Offset of field: cs_m680x_op::type_"] [:: std :: mem :: offset_of ! (cs_m680x_op , type_) - 0usize] ; ["Offset of field: cs_m680x_op::size"] [:: std :: mem :: offset_of ! (cs_m680x_op , size) - 20usize] ; ["Offset of field: cs_m680x_op::access"] [:: std :: mem :: offset_of ! (cs_m680x_op , access) - 21usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access) } } # [repr (u32)] # [doc = " Group of M680X instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_group_type { M680X_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] M680X_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] M680X_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] M680X_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] M680X_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] M680X_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEDGE; not used"] M680X_GRP_PRIV = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] M680X_GRP_BRAREL = 7 , M680X_GRP_ENDING = 8 , } # [doc = " The M680X instruction and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_m680x { # [doc = "< See: M680X instruction flags"] pub flags : u8 , # [doc = "< number of operands for the instruction or 0"] pub op_count : u8 , # [doc = "< operands for this insn."] pub operands : [cs_m680x_op ; 9usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_m680x"] [:: std :: mem :: size_of :: < cs_m680x > () - 220usize] ; ["Alignment of cs_m680x"] [:: std :: mem :: align_of :: < cs_m680x > () - 4usize] ; ["Offset of field: cs_m680x::flags"] [:: std :: mem :: offset_of ! (cs_m680x , flags) - 0usize] ; ["Offset of field: cs_m680x::op_count"] [:: std :: mem :: offset_of ! (cs_m680x , op_count) - 1usize] ; ["Offset of field: cs_m680x::operands"] [:: std :: mem :: offset_of ! (cs_m680x , operands) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_m680x { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " M680X instruction IDs"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum m680x_insn { M680X_INS_INVLD = 0 , # [doc = "< M6800/1/2/3"] M680X_INS_ABA = 1 , M680X_INS_ABX = 2 , M680X_INS_ABY = 3 , M680X_INS_ADC = 4 , M680X_INS_ADCA = 5 , M680X_INS_ADCB = 6 , M680X_INS_ADCD = 7 , M680X_INS_ADCR = 8 , M680X_INS_ADD = 9 , M680X_INS_ADDA = 10 , M680X_INS_ADDB = 11 , M680X_INS_ADDD = 12 , M680X_INS_ADDE = 13 , M680X_INS_ADDF = 14 , M680X_INS_ADDR = 15 , M680X_INS_ADDW = 16 , M680X_INS_AIM = 17 , M680X_INS_AIS = 18 , M680X_INS_AIX = 19 , M680X_INS_AND = 20 , M680X_INS_ANDA = 21 , M680X_INS_ANDB = 22 , M680X_INS_ANDCC = 23 , M680X_INS_ANDD = 24 , M680X_INS_ANDR = 25 , M680X_INS_ASL = 26 , M680X_INS_ASLA = 27 , M680X_INS_ASLB = 28 , # [doc = "< or LSLD"] M680X_INS_ASLD = 29 , M680X_INS_ASR = 30 , M680X_INS_ASRA = 31 , M680X_INS_ASRB = 32 , M680X_INS_ASRD = 33 , M680X_INS_ASRX = 34 , M680X_INS_BAND = 35 , # [doc = "< or BHS"] M680X_INS_BCC = 36 , M680X_INS_BCLR = 37 , # [doc = "< or BLO"] M680X_INS_BCS = 38 , M680X_INS_BEOR = 39 , M680X_INS_BEQ = 40 , M680X_INS_BGE = 41 , M680X_INS_BGND = 42 , M680X_INS_BGT = 43 , M680X_INS_BHCC = 44 , M680X_INS_BHCS = 45 , M680X_INS_BHI = 46 , M680X_INS_BIAND = 47 , M680X_INS_BIEOR = 48 , M680X_INS_BIH = 49 , M680X_INS_BIL = 50 , M680X_INS_BIOR = 51 , M680X_INS_BIT = 52 , M680X_INS_BITA = 53 , M680X_INS_BITB = 54 , M680X_INS_BITD = 55 , M680X_INS_BITMD = 56 , M680X_INS_BLE = 57 , M680X_INS_BLS = 58 , M680X_INS_BLT = 59 , M680X_INS_BMC = 60 , M680X_INS_BMI = 61 , M680X_INS_BMS = 62 , M680X_INS_BNE = 63 , M680X_INS_BOR = 64 , M680X_INS_BPL = 65 , M680X_INS_BRCLR = 66 , M680X_INS_BRSET = 67 , M680X_INS_BRA = 68 , M680X_INS_BRN = 69 , M680X_INS_BSET = 70 , M680X_INS_BSR = 71 , M680X_INS_BVC = 72 , M680X_INS_BVS = 73 , M680X_INS_CALL = 74 , # [doc = "< M6800/1/2/3"] M680X_INS_CBA = 75 , M680X_INS_CBEQ = 76 , M680X_INS_CBEQA = 77 , M680X_INS_CBEQX = 78 , # [doc = "< M6800/1/2/3"] M680X_INS_CLC = 79 , # [doc = "< M6800/1/2/3"] M680X_INS_CLI = 80 , M680X_INS_CLR = 81 , M680X_INS_CLRA = 82 , M680X_INS_CLRB = 83 , M680X_INS_CLRD = 84 , M680X_INS_CLRE = 85 , M680X_INS_CLRF = 86 , M680X_INS_CLRH = 87 , M680X_INS_CLRW = 88 , M680X_INS_CLRX = 89 , # [doc = "< M6800/1/2/3"] M680X_INS_CLV = 90 , M680X_INS_CMP = 91 , M680X_INS_CMPA = 92 , M680X_INS_CMPB = 93 , M680X_INS_CMPD = 94 , M680X_INS_CMPE = 95 , M680X_INS_CMPF = 96 , M680X_INS_CMPR = 97 , M680X_INS_CMPS = 98 , M680X_INS_CMPU = 99 , M680X_INS_CMPW = 100 , M680X_INS_CMPX = 101 , M680X_INS_CMPY = 102 , M680X_INS_COM = 103 , M680X_INS_COMA = 104 , M680X_INS_COMB = 105 , M680X_INS_COMD = 106 , M680X_INS_COME = 107 , M680X_INS_COMF = 108 , M680X_INS_COMW = 109 , M680X_INS_COMX = 110 , M680X_INS_CPD = 111 , M680X_INS_CPHX = 112 , M680X_INS_CPS = 113 , # [doc = "< M6800/1/2/3"] M680X_INS_CPX = 114 , M680X_INS_CPY = 115 , M680X_INS_CWAI = 116 , M680X_INS_DAA = 117 , M680X_INS_DBEQ = 118 , M680X_INS_DBNE = 119 , M680X_INS_DBNZ = 120 , M680X_INS_DBNZA = 121 , M680X_INS_DBNZX = 122 , M680X_INS_DEC = 123 , M680X_INS_DECA = 124 , M680X_INS_DECB = 125 , M680X_INS_DECD = 126 , M680X_INS_DECE = 127 , M680X_INS_DECF = 128 , M680X_INS_DECW = 129 , M680X_INS_DECX = 130 , # [doc = "< M6800/1/2/3"] M680X_INS_DES = 131 , # [doc = "< M6800/1/2/3"] M680X_INS_DEX = 132 , M680X_INS_DEY = 133 , M680X_INS_DIV = 134 , M680X_INS_DIVD = 135 , M680X_INS_DIVQ = 136 , M680X_INS_EDIV = 137 , M680X_INS_EDIVS = 138 , M680X_INS_EIM = 139 , M680X_INS_EMACS = 140 , M680X_INS_EMAXD = 141 , M680X_INS_EMAXM = 142 , M680X_INS_EMIND = 143 , M680X_INS_EMINM = 144 , M680X_INS_EMUL = 145 , M680X_INS_EMULS = 146 , M680X_INS_EOR = 147 , M680X_INS_EORA = 148 , M680X_INS_EORB = 149 , M680X_INS_EORD = 150 , M680X_INS_EORR = 151 , M680X_INS_ETBL = 152 , M680X_INS_EXG = 153 , M680X_INS_FDIV = 154 , M680X_INS_IBEQ = 155 , M680X_INS_IBNE = 156 , M680X_INS_IDIV = 157 , M680X_INS_IDIVS = 158 , M680X_INS_ILLGL = 159 , M680X_INS_INC = 160 , M680X_INS_INCA = 161 , M680X_INS_INCB = 162 , M680X_INS_INCD = 163 , M680X_INS_INCE = 164 , M680X_INS_INCF = 165 , M680X_INS_INCW = 166 , M680X_INS_INCX = 167 , # [doc = "< M6800/1/2/3"] M680X_INS_INS = 168 , # [doc = "< M6800/1/2/3"] M680X_INS_INX = 169 , M680X_INS_INY = 170 , M680X_INS_JMP = 171 , M680X_INS_JSR = 172 , # [doc = "< or LBHS"] M680X_INS_LBCC = 173 , # [doc = "< or LBLO"] M680X_INS_LBCS = 174 , M680X_INS_LBEQ = 175 , M680X_INS_LBGE = 176 , M680X_INS_LBGT = 177 , M680X_INS_LBHI = 178 , M680X_INS_LBLE = 179 , M680X_INS_LBLS = 180 , M680X_INS_LBLT = 181 , M680X_INS_LBMI = 182 , M680X_INS_LBNE = 183 , M680X_INS_LBPL = 184 , M680X_INS_LBRA = 185 , M680X_INS_LBRN = 186 , M680X_INS_LBSR = 187 , M680X_INS_LBVC = 188 , M680X_INS_LBVS = 189 , M680X_INS_LDA = 190 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAA = 191 , # [doc = "< M6800/1/2/3"] M680X_INS_LDAB = 192 , M680X_INS_LDB = 193 , M680X_INS_LDBT = 194 , M680X_INS_LDD = 195 , M680X_INS_LDE = 196 , M680X_INS_LDF = 197 , M680X_INS_LDHX = 198 , M680X_INS_LDMD = 199 , M680X_INS_LDQ = 200 , M680X_INS_LDS = 201 , M680X_INS_LDU = 202 , M680X_INS_LDW = 203 , M680X_INS_LDX = 204 , M680X_INS_LDY = 205 , M680X_INS_LEAS = 206 , M680X_INS_LEAU = 207 , M680X_INS_LEAX = 208 , M680X_INS_LEAY = 209 , M680X_INS_LSL = 210 , M680X_INS_LSLA = 211 , M680X_INS_LSLB = 212 , M680X_INS_LSLD = 213 , M680X_INS_LSLX = 214 , M680X_INS_LSR = 215 , M680X_INS_LSRA = 216 , M680X_INS_LSRB = 217 , # [doc = "< or ASRD"] M680X_INS_LSRD = 218 , M680X_INS_LSRW = 219 , M680X_INS_LSRX = 220 , M680X_INS_MAXA = 221 , M680X_INS_MAXM = 222 , M680X_INS_MEM = 223 , M680X_INS_MINA = 224 , M680X_INS_MINM = 225 , M680X_INS_MOV = 226 , M680X_INS_MOVB = 227 , M680X_INS_MOVW = 228 , M680X_INS_MUL = 229 , M680X_INS_MULD = 230 , M680X_INS_NEG = 231 , M680X_INS_NEGA = 232 , M680X_INS_NEGB = 233 , M680X_INS_NEGD = 234 , M680X_INS_NEGX = 235 , M680X_INS_NOP = 236 , M680X_INS_NSA = 237 , M680X_INS_OIM = 238 , M680X_INS_ORA = 239 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAA = 240 , # [doc = "< M6800/1/2/3"] M680X_INS_ORAB = 241 , M680X_INS_ORB = 242 , M680X_INS_ORCC = 243 , M680X_INS_ORD = 244 , M680X_INS_ORR = 245 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHA = 246 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHB = 247 , M680X_INS_PSHC = 248 , M680X_INS_PSHD = 249 , M680X_INS_PSHH = 250 , M680X_INS_PSHS = 251 , M680X_INS_PSHSW = 252 , M680X_INS_PSHU = 253 , M680X_INS_PSHUW = 254 , # [doc = "< M6800/1/2/3"] M680X_INS_PSHX = 255 , M680X_INS_PSHY = 256 , # [doc = "< M6800/1/2/3"] M680X_INS_PULA = 257 , # [doc = "< M6800/1/2/3"] M680X_INS_PULB = 258 , M680X_INS_PULC = 259 , M680X_INS_PULD = 260 , M680X_INS_PULH = 261 , M680X_INS_PULS = 262 , M680X_INS_PULSW = 263 , M680X_INS_PULU = 264 , M680X_INS_PULUW = 265 , # [doc = "< M6800/1/2/3"] M680X_INS_PULX = 266 , M680X_INS_PULY = 267 , M680X_INS_REV = 268 , M680X_INS_REVW = 269 , M680X_INS_ROL = 270 , M680X_INS_ROLA = 271 , M680X_INS_ROLB = 272 , M680X_INS_ROLD = 273 , M680X_INS_ROLW = 274 , M680X_INS_ROLX = 275 , M680X_INS_ROR = 276 , M680X_INS_RORA = 277 , M680X_INS_RORB = 278 , M680X_INS_RORD = 279 , M680X_INS_RORW = 280 , M680X_INS_RORX = 281 , M680X_INS_RSP = 282 , M680X_INS_RTC = 283 , M680X_INS_RTI = 284 , M680X_INS_RTS = 285 , # [doc = "< M6800/1/2/3"] M680X_INS_SBA = 286 , M680X_INS_SBC = 287 , M680X_INS_SBCA = 288 , M680X_INS_SBCB = 289 , M680X_INS_SBCD = 290 , M680X_INS_SBCR = 291 , M680X_INS_SEC = 292 , M680X_INS_SEI = 293 , M680X_INS_SEV = 294 , M680X_INS_SEX = 295 , M680X_INS_SEXW = 296 , M680X_INS_SLP = 297 , M680X_INS_STA = 298 , # [doc = "< M6800/1/2/3"] M680X_INS_STAA = 299 , # [doc = "< M6800/1/2/3"] M680X_INS_STAB = 300 , M680X_INS_STB = 301 , M680X_INS_STBT = 302 , M680X_INS_STD = 303 , M680X_INS_STE = 304 , M680X_INS_STF = 305 , M680X_INS_STOP = 306 , M680X_INS_STHX = 307 , M680X_INS_STQ = 308 , M680X_INS_STS = 309 , M680X_INS_STU = 310 , M680X_INS_STW = 311 , M680X_INS_STX = 312 , M680X_INS_STY = 313 , M680X_INS_SUB = 314 , M680X_INS_SUBA = 315 , M680X_INS_SUBB = 316 , M680X_INS_SUBD = 317 , M680X_INS_SUBE = 318 , M680X_INS_SUBF = 319 , M680X_INS_SUBR = 320 , M680X_INS_SUBW = 321 , M680X_INS_SWI = 322 , M680X_INS_SWI2 = 323 , M680X_INS_SWI3 = 324 , M680X_INS_SYNC = 325 , # [doc = "< M6800/1/2/3"] M680X_INS_TAB = 326 , # [doc = "< M6800/1/2/3"] M680X_INS_TAP = 327 , M680X_INS_TAX = 328 , # [doc = "< M6800/1/2/3"] M680X_INS_TBA = 329 , M680X_INS_TBEQ = 330 , M680X_INS_TBL = 331 , M680X_INS_TBNE = 332 , M680X_INS_TEST = 333 , M680X_INS_TFM = 334 , M680X_INS_TFR = 335 , M680X_INS_TIM = 336 , # [doc = "< M6800/1/2/3"] M680X_INS_TPA = 337 , M680X_INS_TST = 338 , M680X_INS_TSTA = 339 , M680X_INS_TSTB = 340 , M680X_INS_TSTD = 341 , M680X_INS_TSTE = 342 , M680X_INS_TSTF = 343 , M680X_INS_TSTW = 344 , M680X_INS_TSTX = 345 , # [doc = "< M6800/1/2/3"] M680X_INS_TSX = 346 , M680X_INS_TSY = 347 , M680X_INS_TXA = 348 , # [doc = "< M6800/1/2/3"] M680X_INS_TXS = 349 , M680X_INS_TYS = 350 , # [doc = "< M6800/1/2/3"] M680X_INS_WAI = 351 , M680X_INS_WAIT = 352 , M680X_INS_WAV = 353 , M680X_INS_WAVR = 354 , # [doc = "< HD6301"] M680X_INS_XGDX = 355 , M680X_INS_XGDY = 356 , M680X_INS_ENDING = 357 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_evm { # [doc = "< number of items popped from the stack"] pub pop : :: std :: os :: raw :: c_uchar , # [doc = "< number of items pushed into the stack"] pub push : :: std :: os :: raw :: c_uchar , # [doc = "< gas fee for the instruction"] pub fee : :: std :: os :: raw :: c_uint , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_evm"] [:: std :: mem :: size_of :: < cs_evm > () - 8usize] ; ["Alignment of cs_evm"] [:: std :: mem :: align_of :: < cs_evm > () - 4usize] ; ["Offset of field: cs_evm::pop"] [:: std :: mem :: offset_of ! (cs_evm , pop) - 0usize] ; ["Offset of field: cs_evm::push"] [:: std :: mem :: offset_of ! (cs_evm , push) - 1usize] ; ["Offset of field: cs_evm::fee"] [:: std :: mem :: offset_of ! (cs_evm , fee) - 4usize] ; } ; # [repr (u32)] # [doc = " EVM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn { EVM_INS_STOP = 0 , EVM_INS_ADD = 1 , EVM_INS_MUL = 2 , EVM_INS_SUB = 3 , EVM_INS_DIV = 4 , EVM_INS_SDIV = 5 , EVM_INS_MOD = 6 , EVM_INS_SMOD = 7 , EVM_INS_ADDMOD = 8 , EVM_INS_MULMOD = 9 , EVM_INS_EXP = 10 , EVM_INS_SIGNEXTEND = 11 , EVM_INS_LT = 16 , EVM_INS_GT = 17 , EVM_INS_SLT = 18 , EVM_INS_SGT = 19 , EVM_INS_EQ = 20 , EVM_INS_ISZERO = 21 , EVM_INS_AND = 22 , EVM_INS_OR = 23 , EVM_INS_XOR = 24 , EVM_INS_NOT = 25 , EVM_INS_BYTE = 26 , EVM_INS_SHA3 = 32 , EVM_INS_ADDRESS = 48 , EVM_INS_BALANCE = 49 , EVM_INS_ORIGIN = 50 , EVM_INS_CALLER = 51 , EVM_INS_CALLVALUE = 52 , EVM_INS_CALLDATALOAD = 53 , EVM_INS_CALLDATASIZE = 54 , EVM_INS_CALLDATACOPY = 55 , EVM_INS_CODESIZE = 56 , EVM_INS_CODECOPY = 57 , EVM_INS_GASPRICE = 58 , EVM_INS_EXTCODESIZE = 59 , EVM_INS_EXTCODECOPY = 60 , EVM_INS_RETURNDATASIZE = 61 , EVM_INS_RETURNDATACOPY = 62 , EVM_INS_BLOCKHASH = 64 , EVM_INS_COINBASE = 65 , EVM_INS_TIMESTAMP = 66 , EVM_INS_NUMBER = 67 , EVM_INS_DIFFICULTY = 68 , EVM_INS_GASLIMIT = 69 , EVM_INS_POP = 80 , EVM_INS_MLOAD = 81 , EVM_INS_MSTORE = 82 , EVM_INS_MSTORE8 = 83 , EVM_INS_SLOAD = 84 , EVM_INS_SSTORE = 85 , EVM_INS_JUMP = 86 , EVM_INS_JUMPI = 87 , EVM_INS_PC = 88 , EVM_INS_MSIZE = 89 , EVM_INS_GAS = 90 , EVM_INS_JUMPDEST = 91 , EVM_INS_PUSH1 = 96 , EVM_INS_PUSH2 = 97 , EVM_INS_PUSH3 = 98 , EVM_INS_PUSH4 = 99 , EVM_INS_PUSH5 = 100 , EVM_INS_PUSH6 = 101 , EVM_INS_PUSH7 = 102 , EVM_INS_PUSH8 = 103 , EVM_INS_PUSH9 = 104 , EVM_INS_PUSH10 = 105 , EVM_INS_PUSH11 = 106 , EVM_INS_PUSH12 = 107 , EVM_INS_PUSH13 = 108 , EVM_INS_PUSH14 = 109 , EVM_INS_PUSH15 = 110 , EVM_INS_PUSH16 = 111 , EVM_INS_PUSH17 = 112 , EVM_INS_PUSH18 = 113 , EVM_INS_PUSH19 = 114 , EVM_INS_PUSH20 = 115 , EVM_INS_PUSH21 = 116 , EVM_INS_PUSH22 = 117 , EVM_INS_PUSH23 = 118 , EVM_INS_PUSH24 = 119 , EVM_INS_PUSH25 = 120 , EVM_INS_PUSH26 = 121 , EVM_INS_PUSH27 = 122 , EVM_INS_PUSH28 = 123 , EVM_INS_PUSH29 = 124 , EVM_INS_PUSH30 = 125 , EVM_INS_PUSH31 = 126 , EVM_INS_PUSH32 = 127 , EVM_INS_DUP1 = 128 , EVM_INS_DUP2 = 129 , EVM_INS_DUP3 = 130 , EVM_INS_DUP4 = 131 , EVM_INS_DUP5 = 132 , EVM_INS_DUP6 = 133 , EVM_INS_DUP7 = 134 , EVM_INS_DUP8 = 135 , EVM_INS_DUP9 = 136 , EVM_INS_DUP10 = 137 , EVM_INS_DUP11 = 138 , EVM_INS_DUP12 = 139 , EVM_INS_DUP13 = 140 , EVM_INS_DUP14 = 141 , EVM_INS_DUP15 = 142 , EVM_INS_DUP16 = 143 , EVM_INS_SWAP1 = 144 , EVM_INS_SWAP2 = 145 , EVM_INS_SWAP3 = 146 , EVM_INS_SWAP4 = 147 , EVM_INS_SWAP5 = 148 , EVM_INS_SWAP6 = 149 , EVM_INS_SWAP7 = 150 , EVM_INS_SWAP8 = 151 , EVM_INS_SWAP9 = 152 , EVM_INS_SWAP10 = 153 , EVM_INS_SWAP11 = 154 , EVM_INS_SWAP12 = 155 , EVM_INS_SWAP13 = 156 , EVM_INS_SWAP14 = 157 , EVM_INS_SWAP15 = 158 , EVM_INS_SWAP16 = 159 , EVM_INS_LOG0 = 160 , EVM_INS_LOG1 = 161 , EVM_INS_LOG2 = 162 , EVM_INS_LOG3 = 163 , EVM_INS_LOG4 = 164 , EVM_INS_CREATE = 240 , EVM_INS_CALL = 241 , EVM_INS_CALLCODE = 242 , EVM_INS_RETURN = 243 , EVM_INS_DELEGATECALL = 244 , EVM_INS_CALLBLACKBOX = 245 , EVM_INS_STATICCALL = 250 , EVM_INS_REVERT = 253 , EVM_INS_SUICIDE = 255 , EVM_INS_INVALID = 512 , EVM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of EVM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum evm_insn_group { # [doc = "< = CS_GRP_INVALID"] EVM_GRP_INVALID = 0 , # [doc = "< all jump instructions"] EVM_GRP_JUMP = 1 , # [doc = "< math instructions"] EVM_GRP_MATH = 8 , # [doc = "< instructions write to stack"] EVM_GRP_STACK_WRITE = 9 , # [doc = "< instructions read from stack"] EVM_GRP_STACK_READ = 10 , # [doc = "< instructions write to memory"] EVM_GRP_MEM_WRITE = 11 , # [doc = "< instructions read from memory"] EVM_GRP_MEM_READ = 12 , # [doc = "< instructions write to storage"] EVM_GRP_STORE_WRITE = 13 , # [doc = "< instructions read from storage"] EVM_GRP_STORE_READ = 14 , # [doc = "< instructions halt execution"] EVM_GRP_HALT = 15 , # [doc = "< <-- mark the end of the list of groups"] EVM_GRP_ENDING = 16 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_op_type { RISCV_OP_INVALID = 0 , RISCV_OP_REG = 1 , RISCV_OP_IMM = 2 , RISCV_OP_MEM = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct riscv_op_mem { pub base : :: std :: os :: raw :: c_uint , pub disp : i64 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of riscv_op_mem"] [:: std :: mem :: size_of :: < riscv_op_mem > () - 16usize] ; ["Alignment of riscv_op_mem"] [:: std :: mem :: align_of :: < riscv_op_mem > () - 8usize] ; ["Offset of field: riscv_op_mem::base"] [:: std :: mem :: offset_of ! (riscv_op_mem , base) - 0usize] ; ["Offset of field: riscv_op_mem::disp"] [:: std :: mem :: offset_of ! (riscv_op_mem , disp) - 8usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv_op { pub type_ : riscv_op_type , pub __bindgen_anon_1 : cs_riscv_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_riscv_op__bindgen_ty_1 { pub reg : :: std :: os :: raw :: c_uint , pub imm : i64 , pub mem : riscv_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_riscv_op__bindgen_ty_1 > () - 16usize] ; ["Alignment of cs_riscv_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_riscv_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_riscv_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_riscv_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv_op"] [:: std :: mem :: size_of :: < cs_riscv_op > () - 24usize] ; ["Alignment of cs_riscv_op"] [:: std :: mem :: align_of :: < cs_riscv_op > () - 8usize] ; ["Offset of field: cs_riscv_op::type_"] [:: std :: mem :: offset_of ! (cs_riscv_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (C)] # [derive (Copy , Clone)] pub struct cs_riscv { pub need_effective_addr : bool , pub op_count : u8 , pub operands : [cs_riscv_op ; 8usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_riscv"] [:: std :: mem :: size_of :: < cs_riscv > () - 200usize] ; ["Alignment of cs_riscv"] [:: std :: mem :: align_of :: < cs_riscv > () - 8usize] ; ["Offset of field: cs_riscv::need_effective_addr"] [:: std :: mem :: offset_of ! (cs_riscv , need_effective_addr) - 0usize] ; ["Offset of field: cs_riscv::op_count"] [:: std :: mem :: offset_of ! (cs_riscv , op_count) - 1usize] ; ["Offset of field: cs_riscv::operands"] [:: std :: mem :: offset_of ! (cs_riscv , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_riscv { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}" , self . need_effective_addr , self . op_count , self . operands) } } impl riscv_reg { pub const RISCV_REG_ZERO : riscv_reg = riscv_reg :: RISCV_REG_X0 ; } impl riscv_reg { pub const RISCV_REG_RA : riscv_reg = riscv_reg :: RISCV_REG_X1 ; } impl riscv_reg { pub const RISCV_REG_SP : riscv_reg = riscv_reg :: RISCV_REG_X2 ; } impl riscv_reg { pub const RISCV_REG_GP : riscv_reg = riscv_reg :: RISCV_REG_X3 ; } impl riscv_reg { pub const RISCV_REG_TP : riscv_reg = riscv_reg :: RISCV_REG_X4 ; } impl riscv_reg { pub const RISCV_REG_T0 : riscv_reg = riscv_reg :: RISCV_REG_X5 ; } impl riscv_reg { pub const RISCV_REG_T1 : riscv_reg = riscv_reg :: RISCV_REG_X6 ; } impl riscv_reg { pub const RISCV_REG_T2 : riscv_reg = riscv_reg :: RISCV_REG_X7 ; } impl riscv_reg { pub const RISCV_REG_S0 : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_FP : riscv_reg = riscv_reg :: RISCV_REG_X8 ; } impl riscv_reg { pub const RISCV_REG_S1 : riscv_reg = riscv_reg :: RISCV_REG_X9 ; } impl riscv_reg { pub const RISCV_REG_A0 : riscv_reg = riscv_reg :: RISCV_REG_X10 ; } impl riscv_reg { pub const RISCV_REG_A1 : riscv_reg = riscv_reg :: RISCV_REG_X11 ; } impl riscv_reg { pub const RISCV_REG_A2 : riscv_reg = riscv_reg :: RISCV_REG_X12 ; } impl riscv_reg { pub const RISCV_REG_A3 : riscv_reg = riscv_reg :: RISCV_REG_X13 ; } impl riscv_reg { pub const RISCV_REG_A4 : riscv_reg = riscv_reg :: RISCV_REG_X14 ; } impl riscv_reg { pub const RISCV_REG_A5 : riscv_reg = riscv_reg :: RISCV_REG_X15 ; } impl riscv_reg { pub const RISCV_REG_A6 : riscv_reg = riscv_reg :: RISCV_REG_X16 ; } impl riscv_reg { pub const RISCV_REG_A7 : riscv_reg = riscv_reg :: RISCV_REG_X17 ; } impl riscv_reg { pub const RISCV_REG_S2 : riscv_reg = riscv_reg :: RISCV_REG_X18 ; } impl riscv_reg { pub const RISCV_REG_S3 : riscv_reg = riscv_reg :: RISCV_REG_X19 ; } impl riscv_reg { pub const RISCV_REG_S4 : riscv_reg = riscv_reg :: RISCV_REG_X20 ; } impl riscv_reg { pub const RISCV_REG_S5 : riscv_reg = riscv_reg :: RISCV_REG_X21 ; } impl riscv_reg { pub const RISCV_REG_S6 : riscv_reg = riscv_reg :: RISCV_REG_X22 ; } impl riscv_reg { pub const RISCV_REG_S7 : riscv_reg = riscv_reg :: RISCV_REG_X23 ; } impl riscv_reg { pub const RISCV_REG_S8 : riscv_reg = riscv_reg :: RISCV_REG_X24 ; } impl riscv_reg { pub const RISCV_REG_S9 : riscv_reg = riscv_reg :: RISCV_REG_X25 ; } impl riscv_reg { pub const RISCV_REG_S10 : riscv_reg = riscv_reg :: RISCV_REG_X26 ; } impl riscv_reg { pub const RISCV_REG_S11 : riscv_reg = riscv_reg :: RISCV_REG_X27 ; } impl riscv_reg { pub const RISCV_REG_T3 : riscv_reg = riscv_reg :: RISCV_REG_X28 ; } impl riscv_reg { pub const RISCV_REG_T4 : riscv_reg = riscv_reg :: RISCV_REG_X29 ; } impl riscv_reg { pub const RISCV_REG_T5 : riscv_reg = riscv_reg :: RISCV_REG_X30 ; } impl riscv_reg { pub const RISCV_REG_T6 : riscv_reg = riscv_reg :: RISCV_REG_X31 ; } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_reg { RISCV_REG_INVALID = 0 , RISCV_REG_X0 = 1 , RISCV_REG_X1 = 2 , RISCV_REG_X2 = 3 , RISCV_REG_X3 = 4 , RISCV_REG_X4 = 5 , RISCV_REG_X5 = 6 , RISCV_REG_X6 = 7 , RISCV_REG_X7 = 8 , RISCV_REG_X8 = 9 , RISCV_REG_X9 = 10 , RISCV_REG_X10 = 11 , RISCV_REG_X11 = 12 , RISCV_REG_X12 = 13 , RISCV_REG_X13 = 14 , RISCV_REG_X14 = 15 , RISCV_REG_X15 = 16 , RISCV_REG_X16 = 17 , RISCV_REG_X17 = 18 , RISCV_REG_X18 = 19 , RISCV_REG_X19 = 20 , RISCV_REG_X20 = 21 , RISCV_REG_X21 = 22 , RISCV_REG_X22 = 23 , RISCV_REG_X23 = 24 , RISCV_REG_X24 = 25 , RISCV_REG_X25 = 26 , RISCV_REG_X26 = 27 , RISCV_REG_X27 = 28 , RISCV_REG_X28 = 29 , RISCV_REG_X29 = 30 , RISCV_REG_X30 = 31 , RISCV_REG_X31 = 32 , RISCV_REG_F0_32 = 33 , RISCV_REG_F0_64 = 34 , RISCV_REG_F1_32 = 35 , RISCV_REG_F1_64 = 36 , RISCV_REG_F2_32 = 37 , RISCV_REG_F2_64 = 38 , RISCV_REG_F3_32 = 39 , RISCV_REG_F3_64 = 40 , RISCV_REG_F4_32 = 41 , RISCV_REG_F4_64 = 42 , RISCV_REG_F5_32 = 43 , RISCV_REG_F5_64 = 44 , RISCV_REG_F6_32 = 45 , RISCV_REG_F6_64 = 46 , RISCV_REG_F7_32 = 47 , RISCV_REG_F7_64 = 48 , RISCV_REG_F8_32 = 49 , RISCV_REG_F8_64 = 50 , RISCV_REG_F9_32 = 51 , RISCV_REG_F9_64 = 52 , RISCV_REG_F10_32 = 53 , RISCV_REG_F10_64 = 54 , RISCV_REG_F11_32 = 55 , RISCV_REG_F11_64 = 56 , RISCV_REG_F12_32 = 57 , RISCV_REG_F12_64 = 58 , RISCV_REG_F13_32 = 59 , RISCV_REG_F13_64 = 60 , RISCV_REG_F14_32 = 61 , RISCV_REG_F14_64 = 62 , RISCV_REG_F15_32 = 63 , RISCV_REG_F15_64 = 64 , RISCV_REG_F16_32 = 65 , RISCV_REG_F16_64 = 66 , RISCV_REG_F17_32 = 67 , RISCV_REG_F17_64 = 68 , RISCV_REG_F18_32 = 69 , RISCV_REG_F18_64 = 70 , RISCV_REG_F19_32 = 71 , RISCV_REG_F19_64 = 72 , RISCV_REG_F20_32 = 73 , RISCV_REG_F20_64 = 74 , RISCV_REG_F21_32 = 75 , RISCV_REG_F21_64 = 76 , RISCV_REG_F22_32 = 77 , RISCV_REG_F22_64 = 78 , RISCV_REG_F23_32 = 79 , RISCV_REG_F23_64 = 80 , RISCV_REG_F24_32 = 81 , RISCV_REG_F24_64 = 82 , RISCV_REG_F25_32 = 83 , RISCV_REG_F25_64 = 84 , RISCV_REG_F26_32 = 85 , RISCV_REG_F26_64 = 86 , RISCV_REG_F27_32 = 87 , RISCV_REG_F27_64 = 88 , RISCV_REG_F28_32 = 89 , RISCV_REG_F28_64 = 90 , RISCV_REG_F29_32 = 91 , RISCV_REG_F29_64 = 92 , RISCV_REG_F30_32 = 93 , RISCV_REG_F30_64 = 94 , RISCV_REG_F31_32 = 95 , RISCV_REG_F31_64 = 96 , RISCV_REG_ENDING = 97 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn { RISCV_INS_INVALID = 0 , RISCV_INS_ADD = 1 , RISCV_INS_ADDI = 2 , RISCV_INS_ADDIW = 3 , RISCV_INS_ADDW = 4 , RISCV_INS_AMOADD_D = 5 , RISCV_INS_AMOADD_D_AQ = 6 , RISCV_INS_AMOADD_D_AQ_RL = 7 , RISCV_INS_AMOADD_D_RL = 8 , RISCV_INS_AMOADD_W = 9 , RISCV_INS_AMOADD_W_AQ = 10 , RISCV_INS_AMOADD_W_AQ_RL = 11 , RISCV_INS_AMOADD_W_RL = 12 , RISCV_INS_AMOAND_D = 13 , RISCV_INS_AMOAND_D_AQ = 14 , RISCV_INS_AMOAND_D_AQ_RL = 15 , RISCV_INS_AMOAND_D_RL = 16 , RISCV_INS_AMOAND_W = 17 , RISCV_INS_AMOAND_W_AQ = 18 , RISCV_INS_AMOAND_W_AQ_RL = 19 , RISCV_INS_AMOAND_W_RL = 20 , RISCV_INS_AMOMAXU_D = 21 , RISCV_INS_AMOMAXU_D_AQ = 22 , RISCV_INS_AMOMAXU_D_AQ_RL = 23 , RISCV_INS_AMOMAXU_D_RL = 24 , RISCV_INS_AMOMAXU_W = 25 , RISCV_INS_AMOMAXU_W_AQ = 26 , RISCV_INS_AMOMAXU_W_AQ_RL = 27 , RISCV_INS_AMOMAXU_W_RL = 28 , RISCV_INS_AMOMAX_D = 29 , RISCV_INS_AMOMAX_D_AQ = 30 , RISCV_INS_AMOMAX_D_AQ_RL = 31 , RISCV_INS_AMOMAX_D_RL = 32 , RISCV_INS_AMOMAX_W = 33 , RISCV_INS_AMOMAX_W_AQ = 34 , RISCV_INS_AMOMAX_W_AQ_RL = 35 , RISCV_INS_AMOMAX_W_RL = 36 , RISCV_INS_AMOMINU_D = 37 , RISCV_INS_AMOMINU_D_AQ = 38 , RISCV_INS_AMOMINU_D_AQ_RL = 39 , RISCV_INS_AMOMINU_D_RL = 40 , RISCV_INS_AMOMINU_W = 41 , RISCV_INS_AMOMINU_W_AQ = 42 , RISCV_INS_AMOMINU_W_AQ_RL = 43 , RISCV_INS_AMOMINU_W_RL = 44 , RISCV_INS_AMOMIN_D = 45 , RISCV_INS_AMOMIN_D_AQ = 46 , RISCV_INS_AMOMIN_D_AQ_RL = 47 , RISCV_INS_AMOMIN_D_RL = 48 , RISCV_INS_AMOMIN_W = 49 , RISCV_INS_AMOMIN_W_AQ = 50 , RISCV_INS_AMOMIN_W_AQ_RL = 51 , RISCV_INS_AMOMIN_W_RL = 52 , RISCV_INS_AMOOR_D = 53 , RISCV_INS_AMOOR_D_AQ = 54 , RISCV_INS_AMOOR_D_AQ_RL = 55 , RISCV_INS_AMOOR_D_RL = 56 , RISCV_INS_AMOOR_W = 57 , RISCV_INS_AMOOR_W_AQ = 58 , RISCV_INS_AMOOR_W_AQ_RL = 59 , RISCV_INS_AMOOR_W_RL = 60 , RISCV_INS_AMOSWAP_D = 61 , RISCV_INS_AMOSWAP_D_AQ = 62 , RISCV_INS_AMOSWAP_D_AQ_RL = 63 , RISCV_INS_AMOSWAP_D_RL = 64 , RISCV_INS_AMOSWAP_W = 65 , RISCV_INS_AMOSWAP_W_AQ = 66 , RISCV_INS_AMOSWAP_W_AQ_RL = 67 , RISCV_INS_AMOSWAP_W_RL = 68 , RISCV_INS_AMOXOR_D = 69 , RISCV_INS_AMOXOR_D_AQ = 70 , RISCV_INS_AMOXOR_D_AQ_RL = 71 , RISCV_INS_AMOXOR_D_RL = 72 , RISCV_INS_AMOXOR_W = 73 , RISCV_INS_AMOXOR_W_AQ = 74 , RISCV_INS_AMOXOR_W_AQ_RL = 75 , RISCV_INS_AMOXOR_W_RL = 76 , RISCV_INS_AND = 77 , RISCV_INS_ANDI = 78 , RISCV_INS_AUIPC = 79 , RISCV_INS_BEQ = 80 , RISCV_INS_BGE = 81 , RISCV_INS_BGEU = 82 , RISCV_INS_BLT = 83 , RISCV_INS_BLTU = 84 , RISCV_INS_BNE = 85 , RISCV_INS_CSRRC = 86 , RISCV_INS_CSRRCI = 87 , RISCV_INS_CSRRS = 88 , RISCV_INS_CSRRSI = 89 , RISCV_INS_CSRRW = 90 , RISCV_INS_CSRRWI = 91 , RISCV_INS_C_ADD = 92 , RISCV_INS_C_ADDI = 93 , RISCV_INS_C_ADDI16SP = 94 , RISCV_INS_C_ADDI4SPN = 95 , RISCV_INS_C_ADDIW = 96 , RISCV_INS_C_ADDW = 97 , RISCV_INS_C_AND = 98 , RISCV_INS_C_ANDI = 99 , RISCV_INS_C_BEQZ = 100 , RISCV_INS_C_BNEZ = 101 , RISCV_INS_C_EBREAK = 102 , RISCV_INS_C_FLD = 103 , RISCV_INS_C_FLDSP = 104 , RISCV_INS_C_FLW = 105 , RISCV_INS_C_FLWSP = 106 , RISCV_INS_C_FSD = 107 , RISCV_INS_C_FSDSP = 108 , RISCV_INS_C_FSW = 109 , RISCV_INS_C_FSWSP = 110 , RISCV_INS_C_J = 111 , RISCV_INS_C_JAL = 112 , RISCV_INS_C_JALR = 113 , RISCV_INS_C_JR = 114 , RISCV_INS_C_LD = 115 , RISCV_INS_C_LDSP = 116 , RISCV_INS_C_LI = 117 , RISCV_INS_C_LUI = 118 , RISCV_INS_C_LW = 119 , RISCV_INS_C_LWSP = 120 , RISCV_INS_C_MV = 121 , RISCV_INS_C_NOP = 122 , RISCV_INS_C_OR = 123 , RISCV_INS_C_SD = 124 , RISCV_INS_C_SDSP = 125 , RISCV_INS_C_SLLI = 126 , RISCV_INS_C_SRAI = 127 , RISCV_INS_C_SRLI = 128 , RISCV_INS_C_SUB = 129 , RISCV_INS_C_SUBW = 130 , RISCV_INS_C_SW = 131 , RISCV_INS_C_SWSP = 132 , RISCV_INS_C_UNIMP = 133 , RISCV_INS_C_XOR = 134 , RISCV_INS_DIV = 135 , RISCV_INS_DIVU = 136 , RISCV_INS_DIVUW = 137 , RISCV_INS_DIVW = 138 , RISCV_INS_EBREAK = 139 , RISCV_INS_ECALL = 140 , RISCV_INS_FADD_D = 141 , RISCV_INS_FADD_S = 142 , RISCV_INS_FCLASS_D = 143 , RISCV_INS_FCLASS_S = 144 , RISCV_INS_FCVT_D_L = 145 , RISCV_INS_FCVT_D_LU = 146 , RISCV_INS_FCVT_D_S = 147 , RISCV_INS_FCVT_D_W = 148 , RISCV_INS_FCVT_D_WU = 149 , RISCV_INS_FCVT_LU_D = 150 , RISCV_INS_FCVT_LU_S = 151 , RISCV_INS_FCVT_L_D = 152 , RISCV_INS_FCVT_L_S = 153 , RISCV_INS_FCVT_S_D = 154 , RISCV_INS_FCVT_S_L = 155 , RISCV_INS_FCVT_S_LU = 156 , RISCV_INS_FCVT_S_W = 157 , RISCV_INS_FCVT_S_WU = 158 , RISCV_INS_FCVT_WU_D = 159 , RISCV_INS_FCVT_WU_S = 160 , RISCV_INS_FCVT_W_D = 161 , RISCV_INS_FCVT_W_S = 162 , RISCV_INS_FDIV_D = 163 , RISCV_INS_FDIV_S = 164 , RISCV_INS_FENCE = 165 , RISCV_INS_FENCE_I = 166 , RISCV_INS_FENCE_TSO = 167 , RISCV_INS_FEQ_D = 168 , RISCV_INS_FEQ_S = 169 , RISCV_INS_FLD = 170 , RISCV_INS_FLE_D = 171 , RISCV_INS_FLE_S = 172 , RISCV_INS_FLT_D = 173 , RISCV_INS_FLT_S = 174 , RISCV_INS_FLW = 175 , RISCV_INS_FMADD_D = 176 , RISCV_INS_FMADD_S = 177 , RISCV_INS_FMAX_D = 178 , RISCV_INS_FMAX_S = 179 , RISCV_INS_FMIN_D = 180 , RISCV_INS_FMIN_S = 181 , RISCV_INS_FMSUB_D = 182 , RISCV_INS_FMSUB_S = 183 , RISCV_INS_FMUL_D = 184 , RISCV_INS_FMUL_S = 185 , RISCV_INS_FMV_D_X = 186 , RISCV_INS_FMV_W_X = 187 , RISCV_INS_FMV_X_D = 188 , RISCV_INS_FMV_X_W = 189 , RISCV_INS_FNMADD_D = 190 , RISCV_INS_FNMADD_S = 191 , RISCV_INS_FNMSUB_D = 192 , RISCV_INS_FNMSUB_S = 193 , RISCV_INS_FSD = 194 , RISCV_INS_FSGNJN_D = 195 , RISCV_INS_FSGNJN_S = 196 , RISCV_INS_FSGNJX_D = 197 , RISCV_INS_FSGNJX_S = 198 , RISCV_INS_FSGNJ_D = 199 , RISCV_INS_FSGNJ_S = 200 , RISCV_INS_FSQRT_D = 201 , RISCV_INS_FSQRT_S = 202 , RISCV_INS_FSUB_D = 203 , RISCV_INS_FSUB_S = 204 , RISCV_INS_FSW = 205 , RISCV_INS_JAL = 206 , RISCV_INS_JALR = 207 , RISCV_INS_LB = 208 , RISCV_INS_LBU = 209 , RISCV_INS_LD = 210 , RISCV_INS_LH = 211 , RISCV_INS_LHU = 212 , RISCV_INS_LR_D = 213 , RISCV_INS_LR_D_AQ = 214 , RISCV_INS_LR_D_AQ_RL = 215 , RISCV_INS_LR_D_RL = 216 , RISCV_INS_LR_W = 217 , RISCV_INS_LR_W_AQ = 218 , RISCV_INS_LR_W_AQ_RL = 219 , RISCV_INS_LR_W_RL = 220 , RISCV_INS_LUI = 221 , RISCV_INS_LW = 222 , RISCV_INS_LWU = 223 , RISCV_INS_MRET = 224 , RISCV_INS_MUL = 225 , RISCV_INS_MULH = 226 , RISCV_INS_MULHSU = 227 , RISCV_INS_MULHU = 228 , RISCV_INS_MULW = 229 , RISCV_INS_OR = 230 , RISCV_INS_ORI = 231 , RISCV_INS_REM = 232 , RISCV_INS_REMU = 233 , RISCV_INS_REMUW = 234 , RISCV_INS_REMW = 235 , RISCV_INS_SB = 236 , RISCV_INS_SC_D = 237 , RISCV_INS_SC_D_AQ = 238 , RISCV_INS_SC_D_AQ_RL = 239 , RISCV_INS_SC_D_RL = 240 , RISCV_INS_SC_W = 241 , RISCV_INS_SC_W_AQ = 242 , RISCV_INS_SC_W_AQ_RL = 243 , RISCV_INS_SC_W_RL = 244 , RISCV_INS_SD = 245 , RISCV_INS_SFENCE_VMA = 246 , RISCV_INS_SH = 247 , RISCV_INS_SLL = 248 , RISCV_INS_SLLI = 249 , RISCV_INS_SLLIW = 250 , RISCV_INS_SLLW = 251 , RISCV_INS_SLT = 252 , RISCV_INS_SLTI = 253 , RISCV_INS_SLTIU = 254 , RISCV_INS_SLTU = 255 , RISCV_INS_SRA = 256 , RISCV_INS_SRAI = 257 , RISCV_INS_SRAIW = 258 , RISCV_INS_SRAW = 259 , RISCV_INS_SRET = 260 , RISCV_INS_SRL = 261 , RISCV_INS_SRLI = 262 , RISCV_INS_SRLIW = 263 , RISCV_INS_SRLW = 264 , RISCV_INS_SUB = 265 , RISCV_INS_SUBW = 266 , RISCV_INS_SW = 267 , RISCV_INS_UNIMP = 268 , RISCV_INS_URET = 269 , RISCV_INS_WFI = 270 , RISCV_INS_XOR = 271 , RISCV_INS_XORI = 272 , RISCV_INS_ENDING = 273 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum riscv_insn_group { # [doc = "< = CS_GRP_INVALID"] RISCV_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] RISCV_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] RISCV_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] RISCV_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] RISCV_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] RISCV_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] RISCV_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] RISCV_GRP_BRANCH_RELATIVE = 7 , RISCV_GRP_ISRV32 = 128 , RISCV_GRP_ISRV64 = 129 , RISCV_GRP_HASSTDEXTA = 130 , RISCV_GRP_HASSTDEXTC = 131 , RISCV_GRP_HASSTDEXTD = 132 , RISCV_GRP_HASSTDEXTF = 133 , RISCV_GRP_HASSTDEXTM = 134 , RISCV_GRP_ENDING = 135 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_op_type { WASM_OP_INVALID = 0 , WASM_OP_NONE = 1 , WASM_OP_INT7 = 2 , WASM_OP_VARUINT32 = 3 , WASM_OP_VARUINT64 = 4 , WASM_OP_UINT32 = 5 , WASM_OP_UINT64 = 6 , WASM_OP_IMM = 7 , WASM_OP_BRTABLE = 8 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_wasm_brtable { pub length : u32 , pub address : u64 , pub default_target : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_brtable"] [:: std :: mem :: size_of :: < cs_wasm_brtable > () - 24usize] ; ["Alignment of cs_wasm_brtable"] [:: std :: mem :: align_of :: < cs_wasm_brtable > () - 8usize] ; ["Offset of field: cs_wasm_brtable::length"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , length) - 0usize] ; ["Offset of field: cs_wasm_brtable::address"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , address) - 8usize] ; ["Offset of field: cs_wasm_brtable::default_target"] [:: std :: mem :: offset_of ! (cs_wasm_brtable , default_target) - 16usize] ; } ; # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm_op { pub type_ : wasm_op_type , pub size : u32 , pub __bindgen_anon_1 : cs_wasm_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_wasm_op__bindgen_ty_1 { pub int7 : i8 , pub varuint32 : u32 , pub varuint64 : u64 , pub uint32 : u32 , pub uint64 : u64 , pub immediate : [u32 ; 2usize] , pub brtable : cs_wasm_brtable , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_wasm_op__bindgen_ty_1 > () - 24usize] ; ["Alignment of cs_wasm_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_wasm_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::int7"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , int7) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::varuint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , varuint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint32"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint32) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::uint64"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , uint64) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::immediate"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , immediate) - 0usize] ; ["Offset of field: cs_wasm_op__bindgen_ty_1::brtable"] [:: std :: mem :: offset_of ! (cs_wasm_op__bindgen_ty_1 , brtable) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm_op"] [:: std :: mem :: size_of :: < cs_wasm_op > () - 32usize] ; ["Alignment of cs_wasm_op"] [:: std :: mem :: align_of :: < cs_wasm_op > () - 8usize] ; ["Offset of field: cs_wasm_op::type_"] [:: std :: mem :: offset_of ! (cs_wasm_op , type_) - 0usize] ; ["Offset of field: cs_wasm_op::size"] [:: std :: mem :: offset_of ! (cs_wasm_op , size) - 4usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . size , self . __bindgen_anon_1) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_wasm { pub op_count : u8 , pub operands : [cs_wasm_op ; 2usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_wasm"] [:: std :: mem :: size_of :: < cs_wasm > () - 72usize] ; ["Alignment of cs_wasm"] [:: std :: mem :: align_of :: < cs_wasm > () - 8usize] ; ["Offset of field: cs_wasm::op_count"] [:: std :: mem :: offset_of ! (cs_wasm , op_count) - 0usize] ; ["Offset of field: cs_wasm::operands"] [:: std :: mem :: offset_of ! (cs_wasm , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_wasm { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_wasm {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } # [repr (u32)] # [doc = " WASM instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn { WASM_INS_UNREACHABLE = 0 , WASM_INS_NOP = 1 , WASM_INS_BLOCK = 2 , WASM_INS_LOOP = 3 , WASM_INS_IF = 4 , WASM_INS_ELSE = 5 , WASM_INS_END = 11 , WASM_INS_BR = 12 , WASM_INS_BR_IF = 13 , WASM_INS_BR_TABLE = 14 , WASM_INS_RETURN = 15 , WASM_INS_CALL = 16 , WASM_INS_CALL_INDIRECT = 17 , WASM_INS_DROP = 26 , WASM_INS_SELECT = 27 , WASM_INS_GET_LOCAL = 32 , WASM_INS_SET_LOCAL = 33 , WASM_INS_TEE_LOCAL = 34 , WASM_INS_GET_GLOBAL = 35 , WASM_INS_SET_GLOBAL = 36 , WASM_INS_I32_LOAD = 40 , WASM_INS_I64_LOAD = 41 , WASM_INS_F32_LOAD = 42 , WASM_INS_F64_LOAD = 43 , WASM_INS_I32_LOAD8_S = 44 , WASM_INS_I32_LOAD8_U = 45 , WASM_INS_I32_LOAD16_S = 46 , WASM_INS_I32_LOAD16_U = 47 , WASM_INS_I64_LOAD8_S = 48 , WASM_INS_I64_LOAD8_U = 49 , WASM_INS_I64_LOAD16_S = 50 , WASM_INS_I64_LOAD16_U = 51 , WASM_INS_I64_LOAD32_S = 52 , WASM_INS_I64_LOAD32_U = 53 , WASM_INS_I32_STORE = 54 , WASM_INS_I64_STORE = 55 , WASM_INS_F32_STORE = 56 , WASM_INS_F64_STORE = 57 , WASM_INS_I32_STORE8 = 58 , WASM_INS_I32_STORE16 = 59 , WASM_INS_I64_STORE8 = 60 , WASM_INS_I64_STORE16 = 61 , WASM_INS_I64_STORE32 = 62 , WASM_INS_CURRENT_MEMORY = 63 , WASM_INS_GROW_MEMORY = 64 , WASM_INS_I32_CONST = 65 , WASM_INS_I64_CONST = 66 , WASM_INS_F32_CONST = 67 , WASM_INS_F64_CONST = 68 , WASM_INS_I32_EQZ = 69 , WASM_INS_I32_EQ = 70 , WASM_INS_I32_NE = 71 , WASM_INS_I32_LT_S = 72 , WASM_INS_I32_LT_U = 73 , WASM_INS_I32_GT_S = 74 , WASM_INS_I32_GT_U = 75 , WASM_INS_I32_LE_S = 76 , WASM_INS_I32_LE_U = 77 , WASM_INS_I32_GE_S = 78 , WASM_INS_I32_GE_U = 79 , WASM_INS_I64_EQZ = 80 , WASM_INS_I64_EQ = 81 , WASM_INS_I64_NE = 82 , WASM_INS_I64_LT_S = 83 , WASM_INS_I64_LT_U = 84 , WASN_INS_I64_GT_S = 85 , WASM_INS_I64_GT_U = 86 , WASM_INS_I64_LE_S = 87 , WASM_INS_I64_LE_U = 88 , WASM_INS_I64_GE_S = 89 , WASM_INS_I64_GE_U = 90 , WASM_INS_F32_EQ = 91 , WASM_INS_F32_NE = 92 , WASM_INS_F32_LT = 93 , WASM_INS_F32_GT = 94 , WASM_INS_F32_LE = 95 , WASM_INS_F32_GE = 96 , WASM_INS_F64_EQ = 97 , WASM_INS_F64_NE = 98 , WASM_INS_F64_LT = 99 , WASM_INS_F64_GT = 100 , WASM_INS_F64_LE = 101 , WASM_INS_F64_GE = 102 , WASM_INS_I32_CLZ = 103 , WASM_INS_I32_CTZ = 104 , WASM_INS_I32_POPCNT = 105 , WASM_INS_I32_ADD = 106 , WASM_INS_I32_SUB = 107 , WASM_INS_I32_MUL = 108 , WASM_INS_I32_DIV_S = 109 , WASM_INS_I32_DIV_U = 110 , WASM_INS_I32_REM_S = 111 , WASM_INS_I32_REM_U = 112 , WASM_INS_I32_AND = 113 , WASM_INS_I32_OR = 114 , WASM_INS_I32_XOR = 115 , WASM_INS_I32_SHL = 116 , WASM_INS_I32_SHR_S = 117 , WASM_INS_I32_SHR_U = 118 , WASM_INS_I32_ROTL = 119 , WASM_INS_I32_ROTR = 120 , WASM_INS_I64_CLZ = 121 , WASM_INS_I64_CTZ = 122 , WASM_INS_I64_POPCNT = 123 , WASM_INS_I64_ADD = 124 , WASM_INS_I64_SUB = 125 , WASM_INS_I64_MUL = 126 , WASM_INS_I64_DIV_S = 127 , WASM_INS_I64_DIV_U = 128 , WASM_INS_I64_REM_S = 129 , WASM_INS_I64_REM_U = 130 , WASM_INS_I64_AND = 131 , WASM_INS_I64_OR = 132 , WASM_INS_I64_XOR = 133 , WASM_INS_I64_SHL = 134 , WASM_INS_I64_SHR_S = 135 , WASM_INS_I64_SHR_U = 136 , WASM_INS_I64_ROTL = 137 , WASM_INS_I64_ROTR = 138 , WASM_INS_F32_ABS = 139 , WASM_INS_F32_NEG = 140 , WASM_INS_F32_CEIL = 141 , WASM_INS_F32_FLOOR = 142 , WASM_INS_F32_TRUNC = 143 , WASM_INS_F32_NEAREST = 144 , WASM_INS_F32_SQRT = 145 , WASM_INS_F32_ADD = 146 , WASM_INS_F32_SUB = 147 , WASM_INS_F32_MUL = 148 , WASM_INS_F32_DIV = 149 , WASM_INS_F32_MIN = 150 , WASM_INS_F32_MAX = 151 , WASM_INS_F32_COPYSIGN = 152 , WASM_INS_F64_ABS = 153 , WASM_INS_F64_NEG = 154 , WASM_INS_F64_CEIL = 155 , WASM_INS_F64_FLOOR = 156 , WASM_INS_F64_TRUNC = 157 , WASM_INS_F64_NEAREST = 158 , WASM_INS_F64_SQRT = 159 , WASM_INS_F64_ADD = 160 , WASM_INS_F64_SUB = 161 , WASM_INS_F64_MUL = 162 , WASM_INS_F64_DIV = 163 , WASM_INS_F64_MIN = 164 , WASM_INS_F64_MAX = 165 , WASM_INS_F64_COPYSIGN = 166 , WASM_INS_I32_WARP_I64 = 167 , WASP_INS_I32_TRUNC_S_F32 = 168 , WASM_INS_I32_TRUNC_U_F32 = 169 , WASM_INS_I32_TRUNC_S_F64 = 170 , WASM_INS_I32_TRUNC_U_F64 = 171 , WASM_INS_I64_EXTEND_S_I32 = 172 , WASM_INS_I64_EXTEND_U_I32 = 173 , WASM_INS_I64_TRUNC_S_F32 = 174 , WASM_INS_I64_TRUNC_U_F32 = 175 , WASM_INS_I64_TRUNC_S_F64 = 176 , WASM_INS_I64_TRUNC_U_F64 = 177 , WASM_INS_F32_CONVERT_S_I32 = 178 , WASM_INS_F32_CONVERT_U_I32 = 179 , WASM_INS_F32_CONVERT_S_I64 = 180 , WASM_INS_F32_CONVERT_U_I64 = 181 , WASM_INS_F32_DEMOTE_F64 = 182 , WASM_INS_F64_CONVERT_S_I32 = 183 , WASM_INS_F64_CONVERT_U_I32 = 184 , WASM_INS_F64_CONVERT_S_I64 = 185 , WASM_INS_F64_CONVERT_U_I64 = 186 , WASM_INS_F64_PROMOTE_F32 = 187 , WASM_INS_I32_REINTERPRET_F32 = 188 , WASM_INS_I64_REINTERPRET_F64 = 189 , WASM_INS_F32_REINTERPRET_I32 = 190 , WASM_INS_F64_REINTERPRET_I64 = 191 , WASM_INS_INVALID = 512 , WASM_INS_ENDING = 513 , } # [repr (u32)] # [doc = " Group of WASM instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum wasm_insn_group { # [doc = "< = CS_GRP_INVALID"] WASM_GRP_INVALID = 0 , WASM_GRP_NUMBERIC = 8 , WASM_GRP_PARAMETRIC = 9 , WASM_GRP_VARIABLE = 10 , WASM_GRP_MEMORY = 11 , WASM_GRP_CONTROL = 12 , # [doc = "< <-- mark the end of the list of groups"] WASM_GRP_ENDING = 13 , } # [repr (u32)] # [doc = " MOS65XX registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_reg { MOS65XX_REG_INVALID = 0 , # [doc = "< accumulator"] MOS65XX_REG_ACC = 1 , # [doc = "< X index register"] MOS65XX_REG_X = 2 , # [doc = "< Y index register"] MOS65XX_REG_Y = 3 , # [doc = "< status register"] MOS65XX_REG_P = 4 , # [doc = "< stack pointer register"] MOS65XX_REG_SP = 5 , # [doc = "< direct page register"] MOS65XX_REG_DP = 6 , # [doc = "< data bank register"] MOS65XX_REG_B = 7 , # [doc = "< program bank register"] MOS65XX_REG_K = 8 , MOS65XX_REG_ENDING = 9 , } # [repr (u32)] # [doc = " MOS65XX Addressing Modes"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_address_mode { # [doc = "< No address mode."] MOS65XX_AM_NONE = 0 , # [doc = "< implied addressing (no addressing mode)"] MOS65XX_AM_IMP = 1 , # [doc = "< accumulator addressing"] MOS65XX_AM_ACC = 2 , # [doc = "< 8/16 Bit immediate value"] MOS65XX_AM_IMM = 3 , # [doc = "< relative addressing used by branches"] MOS65XX_AM_REL = 4 , # [doc = "< interrupt addressing"] MOS65XX_AM_INT = 5 , # [doc = "< memory block addressing"] MOS65XX_AM_BLOCK = 6 , # [doc = "< zeropage addressing"] MOS65XX_AM_ZP = 7 , # [doc = "< indexed zeropage addressing by the X index register"] MOS65XX_AM_ZP_X = 8 , # [doc = "< indexed zeropage addressing by the Y index register"] MOS65XX_AM_ZP_Y = 9 , # [doc = "< zero page address, branch relative address"] MOS65XX_AM_ZP_REL = 10 , # [doc = "< indirect zeropage addressing"] MOS65XX_AM_ZP_IND = 11 , # [doc = "< indexed zeropage indirect addressing by the X index register"] MOS65XX_AM_ZP_X_IND = 12 , # [doc = "< indirect zeropage indexed addressing by the Y index register"] MOS65XX_AM_ZP_IND_Y = 13 , # [doc = "< zeropage indirect long addressing"] MOS65XX_AM_ZP_IND_LONG = 14 , # [doc = "< zeropage indirect long addressing indexed by Y register"] MOS65XX_AM_ZP_IND_LONG_Y = 15 , # [doc = "< absolute addressing"] MOS65XX_AM_ABS = 16 , # [doc = "< indexed absolute addressing by the X index register"] MOS65XX_AM_ABS_X = 17 , # [doc = "< indexed absolute addressing by the Y index register"] MOS65XX_AM_ABS_Y = 18 , # [doc = "< absolute indirect addressing"] MOS65XX_AM_ABS_IND = 19 , # [doc = "< indexed absolute indirect addressing by the X index register"] MOS65XX_AM_ABS_X_IND = 20 , # [doc = "< absolute indirect long addressing"] MOS65XX_AM_ABS_IND_LONG = 21 , # [doc = "< absolute long address mode"] MOS65XX_AM_ABS_LONG = 22 , # [doc = "< absolute long address mode, indexed by X register"] MOS65XX_AM_ABS_LONG_X = 23 , # [doc = "< stack relative addressing"] MOS65XX_AM_SR = 24 , # [doc = "< indirect stack relative addressing indexed by the Y index register"] MOS65XX_AM_SR_IND_Y = 25 , } # [repr (u32)] # [doc = " MOS65XX instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_insn { MOS65XX_INS_INVALID = 0 , MOS65XX_INS_ADC = 1 , MOS65XX_INS_AND = 2 , MOS65XX_INS_ASL = 3 , MOS65XX_INS_BBR = 4 , MOS65XX_INS_BBS = 5 , MOS65XX_INS_BCC = 6 , MOS65XX_INS_BCS = 7 , MOS65XX_INS_BEQ = 8 , MOS65XX_INS_BIT = 9 , MOS65XX_INS_BMI = 10 , MOS65XX_INS_BNE = 11 , MOS65XX_INS_BPL = 12 , MOS65XX_INS_BRA = 13 , MOS65XX_INS_BRK = 14 , MOS65XX_INS_BRL = 15 , MOS65XX_INS_BVC = 16 , MOS65XX_INS_BVS = 17 , MOS65XX_INS_CLC = 18 , MOS65XX_INS_CLD = 19 , MOS65XX_INS_CLI = 20 , MOS65XX_INS_CLV = 21 , MOS65XX_INS_CMP = 22 , MOS65XX_INS_COP = 23 , MOS65XX_INS_CPX = 24 , MOS65XX_INS_CPY = 25 , MOS65XX_INS_DEC = 26 , MOS65XX_INS_DEX = 27 , MOS65XX_INS_DEY = 28 , MOS65XX_INS_EOR = 29 , MOS65XX_INS_INC = 30 , MOS65XX_INS_INX = 31 , MOS65XX_INS_INY = 32 , MOS65XX_INS_JML = 33 , MOS65XX_INS_JMP = 34 , MOS65XX_INS_JSL = 35 , MOS65XX_INS_JSR = 36 , MOS65XX_INS_LDA = 37 , MOS65XX_INS_LDX = 38 , MOS65XX_INS_LDY = 39 , MOS65XX_INS_LSR = 40 , MOS65XX_INS_MVN = 41 , MOS65XX_INS_MVP = 42 , MOS65XX_INS_NOP = 43 , MOS65XX_INS_ORA = 44 , MOS65XX_INS_PEA = 45 , MOS65XX_INS_PEI = 46 , MOS65XX_INS_PER = 47 , MOS65XX_INS_PHA = 48 , MOS65XX_INS_PHB = 49 , MOS65XX_INS_PHD = 50 , MOS65XX_INS_PHK = 51 , MOS65XX_INS_PHP = 52 , MOS65XX_INS_PHX = 53 , MOS65XX_INS_PHY = 54 , MOS65XX_INS_PLA = 55 , MOS65XX_INS_PLB = 56 , MOS65XX_INS_PLD = 57 , MOS65XX_INS_PLP = 58 , MOS65XX_INS_PLX = 59 , MOS65XX_INS_PLY = 60 , MOS65XX_INS_REP = 61 , MOS65XX_INS_RMB = 62 , MOS65XX_INS_ROL = 63 , MOS65XX_INS_ROR = 64 , MOS65XX_INS_RTI = 65 , MOS65XX_INS_RTL = 66 , MOS65XX_INS_RTS = 67 , MOS65XX_INS_SBC = 68 , MOS65XX_INS_SEC = 69 , MOS65XX_INS_SED = 70 , MOS65XX_INS_SEI = 71 , MOS65XX_INS_SEP = 72 , MOS65XX_INS_SMB = 73 , MOS65XX_INS_STA = 74 , MOS65XX_INS_STP = 75 , MOS65XX_INS_STX = 76 , MOS65XX_INS_STY = 77 , MOS65XX_INS_STZ = 78 , MOS65XX_INS_TAX = 79 , MOS65XX_INS_TAY = 80 , MOS65XX_INS_TCD = 81 , MOS65XX_INS_TCS = 82 , MOS65XX_INS_TDC = 83 , MOS65XX_INS_TRB = 84 , MOS65XX_INS_TSB = 85 , MOS65XX_INS_TSC = 86 , MOS65XX_INS_TSX = 87 , MOS65XX_INS_TXA = 88 , MOS65XX_INS_TXS = 89 , MOS65XX_INS_TXY = 90 , MOS65XX_INS_TYA = 91 , MOS65XX_INS_TYX = 92 , MOS65XX_INS_WAI = 93 , MOS65XX_INS_WDM = 94 , MOS65XX_INS_XBA = 95 , MOS65XX_INS_XCE = 96 , MOS65XX_INS_ENDING = 97 , } # [repr (u32)] # [doc = " Group of MOS65XX instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_group_type { # [doc = "< CS_GRP_INVALID"] MOS65XX_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] MOS65XX_GRP_JUMP = 1 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_CALL = 2 , # [doc = "< = CS_GRP_RET"] MOS65XX_GRP_RET = 3 , # [doc = "< = CS_GRP_INT"] MOS65XX_GRP_INT = 4 , # [doc = "< = CS_GRP_IRET"] MOS65XX_GRP_IRET = 5 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] MOS65XX_GRP_BRANCH_RELATIVE = 6 , MOS65XX_GRP_ENDING = 7 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum mos65xx_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] MOS65XX_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] MOS65XX_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] MOS65XX_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] MOS65XX_OP_MEM = 3 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx_op { # [doc = "< operand type"] pub type_ : mos65xx_op_type , pub __bindgen_anon_1 : cs_mos65xx_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_mos65xx_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : mos65xx_reg , # [doc = "< immediate value for IMM operand"] pub imm : u16 , # [doc = "< address for MEM operand"] pub mem : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Alignment of cs_mos65xx_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_mos65xx_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_mos65xx_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_mos65xx_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx_op"] [:: std :: mem :: size_of :: < cs_mos65xx_op > () - 8usize] ; ["Alignment of cs_mos65xx_op"] [:: std :: mem :: align_of :: < cs_mos65xx_op > () - 4usize] ; ["Offset of field: cs_mos65xx_op::type_"] [:: std :: mem :: offset_of ! (cs_mos65xx_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [doc = " The MOS65XX address mode and it's operands"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_mos65xx { pub am : mos65xx_address_mode , pub modifies_flags : bool , # [doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_mos65xx_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_mos65xx"] [:: std :: mem :: size_of :: < cs_mos65xx > () - 32usize] ; ["Alignment of cs_mos65xx"] [:: std :: mem :: align_of :: < cs_mos65xx > () - 4usize] ; ["Offset of field: cs_mos65xx::am"] [:: std :: mem :: offset_of ! (cs_mos65xx , am) - 0usize] ; ["Offset of field: cs_mos65xx::modifies_flags"] [:: std :: mem :: offset_of ! (cs_mos65xx , modifies_flags) - 4usize] ; ["Offset of field: cs_mos65xx::op_count"] [:: std :: mem :: offset_of ! (cs_mos65xx , op_count) - 5usize] ; ["Offset of field: cs_mos65xx::operands"] [:: std :: mem :: offset_of ! (cs_mos65xx , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_mos65xx { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}" , self . am , self . modifies_flags , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_op_type { BPF_OP_INVALID = 0 , BPF_OP_REG = 1 , BPF_OP_IMM = 2 , BPF_OP_OFF = 3 , BPF_OP_MEM = 4 , # [doc = "< M[k] in cBPF"] BPF_OP_MMEM = 5 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] BPF_OP_MSH = 6 , # [doc = "< cBPF's extension (not eBPF)"] BPF_OP_EXT = 7 , } # [repr (u32)] # [doc = " BPF registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_reg { BPF_REG_INVALID = 0 , BPF_REG_A = 1 , BPF_REG_X = 2 , BPF_REG_R0 = 3 , BPF_REG_R1 = 4 , BPF_REG_R2 = 5 , BPF_REG_R3 = 6 , BPF_REG_R4 = 7 , BPF_REG_R5 = 8 , BPF_REG_R6 = 9 , BPF_REG_R7 = 10 , BPF_REG_R8 = 11 , BPF_REG_R9 = 12 , BPF_REG_R10 = 13 , BPF_REG_ENDING = 14 , } # [doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct bpf_op_mem { # [doc = "< base register"] pub base : bpf_reg , # [doc = "< offset value"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of bpf_op_mem"] [:: std :: mem :: size_of :: < bpf_op_mem > () - 8usize] ; ["Alignment of bpf_op_mem"] [:: std :: mem :: align_of :: < bpf_op_mem > () - 4usize] ; ["Offset of field: bpf_op_mem::base"] [:: std :: mem :: offset_of ! (bpf_op_mem , base) - 0usize] ; ["Offset of field: bpf_op_mem::disp"] [:: std :: mem :: offset_of ! (bpf_op_mem , disp) - 4usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_ext_type { BPF_EXT_INVALID = 0 , BPF_EXT_LEN = 1 , } # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf_op { pub type_ : bpf_op_type , pub __bindgen_anon_1 : cs_bpf_op__bindgen_ty_1 , # [doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_bpf_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : u8 , # [doc = "< immediate value IMM operand"] pub imm : u64 , # [doc = "< offset value, used in jump & call"] pub off : u32 , # [doc = "< base/disp value for MEM operand"] pub mem : bpf_op_mem , # [doc = "< M[k] in cBPF"] pub mmem : u32 , # [doc = "< corresponds to cBPF's BPF_MSH mode"] pub msh : u32 , # [doc = "< cBPF's extension (not eBPF)"] pub ext : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_bpf_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_bpf_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::off"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , off) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::mmem"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , mmem) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::msh"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , msh) - 0usize] ; ["Offset of field: cs_bpf_op__bindgen_ty_1::ext"] [:: std :: mem :: offset_of ! (cs_bpf_op__bindgen_ty_1 , ext) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf_op"] [:: std :: mem :: size_of :: < cs_bpf_op > () - 24usize] ; ["Alignment of cs_bpf_op"] [:: std :: mem :: align_of :: < cs_bpf_op > () - 8usize] ; ["Offset of field: cs_bpf_op::type_"] [:: std :: mem :: offset_of ! (cs_bpf_op , type_) - 0usize] ; ["Offset of field: cs_bpf_op::access"] [:: std :: mem :: offset_of ! (cs_bpf_op , access) - 16usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_bpf { pub op_count : u8 , pub operands : [cs_bpf_op ; 4usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_bpf"] [:: std :: mem :: size_of :: < cs_bpf > () - 104usize] ; ["Alignment of cs_bpf"] [:: std :: mem :: align_of :: < cs_bpf > () - 8usize] ; ["Offset of field: cs_bpf::op_count"] [:: std :: mem :: offset_of ! (cs_bpf , op_count) - 0usize] ; ["Offset of field: cs_bpf::operands"] [:: std :: mem :: offset_of ! (cs_bpf , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_bpf { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_bpf {{ op_count: {:?}, operands: {:?} }}" , self . op_count , self . operands) } } impl bpf_insn { pub const BPF_INS_LD : bpf_insn = bpf_insn :: BPF_INS_LDW ; } impl bpf_insn { pub const BPF_INS_LDX : bpf_insn = bpf_insn :: BPF_INS_LDXW ; } impl bpf_insn { pub const BPF_INS_ST : bpf_insn = bpf_insn :: BPF_INS_STW ; } impl bpf_insn { pub const BPF_INS_STX : bpf_insn = bpf_insn :: BPF_INS_STXW ; } # [repr (u32)] # [doc = " BPF instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn { BPF_INS_INVALID = 0 , BPF_INS_ADD = 1 , BPF_INS_SUB = 2 , BPF_INS_MUL = 3 , BPF_INS_DIV = 4 , BPF_INS_OR = 5 , BPF_INS_AND = 6 , BPF_INS_LSH = 7 , BPF_INS_RSH = 8 , BPF_INS_NEG = 9 , BPF_INS_MOD = 10 , BPF_INS_XOR = 11 , # [doc = "< eBPF only"] BPF_INS_MOV = 12 , # [doc = "< eBPF only"] BPF_INS_ARSH = 13 , BPF_INS_ADD64 = 14 , BPF_INS_SUB64 = 15 , BPF_INS_MUL64 = 16 , BPF_INS_DIV64 = 17 , BPF_INS_OR64 = 18 , BPF_INS_AND64 = 19 , BPF_INS_LSH64 = 20 , BPF_INS_RSH64 = 21 , BPF_INS_NEG64 = 22 , BPF_INS_MOD64 = 23 , BPF_INS_XOR64 = 24 , BPF_INS_MOV64 = 25 , BPF_INS_ARSH64 = 26 , BPF_INS_LE16 = 27 , BPF_INS_LE32 = 28 , BPF_INS_LE64 = 29 , BPF_INS_BE16 = 30 , BPF_INS_BE32 = 31 , BPF_INS_BE64 = 32 , # [doc = "< eBPF only"] BPF_INS_LDW = 33 , BPF_INS_LDH = 34 , BPF_INS_LDB = 35 , # [doc = "< eBPF only: load 64-bit imm"] BPF_INS_LDDW = 36 , # [doc = "< eBPF only"] BPF_INS_LDXW = 37 , # [doc = "< eBPF only"] BPF_INS_LDXH = 38 , # [doc = "< eBPF only"] BPF_INS_LDXB = 39 , # [doc = "< eBPF only"] BPF_INS_LDXDW = 40 , # [doc = "< eBPF only"] BPF_INS_STW = 41 , # [doc = "< eBPF only"] BPF_INS_STH = 42 , # [doc = "< eBPF only"] BPF_INS_STB = 43 , # [doc = "< eBPF only"] BPF_INS_STDW = 44 , # [doc = "< eBPF only"] BPF_INS_STXW = 45 , # [doc = "< eBPF only"] BPF_INS_STXH = 46 , # [doc = "< eBPF only"] BPF_INS_STXB = 47 , # [doc = "< eBPF only"] BPF_INS_STXDW = 48 , # [doc = "< eBPF only"] BPF_INS_XADDW = 49 , # [doc = "< eBPF only"] BPF_INS_XADDDW = 50 , BPF_INS_JMP = 51 , BPF_INS_JEQ = 52 , BPF_INS_JGT = 53 , BPF_INS_JGE = 54 , BPF_INS_JSET = 55 , # [doc = "< eBPF only"] BPF_INS_JNE = 56 , # [doc = "< eBPF only"] BPF_INS_JSGT = 57 , # [doc = "< eBPF only"] BPF_INS_JSGE = 58 , # [doc = "< eBPF only"] BPF_INS_CALL = 59 , # [doc = "< eBPF only"] BPF_INS_CALLX = 60 , # [doc = "< eBPF only"] BPF_INS_EXIT = 61 , # [doc = "< eBPF only"] BPF_INS_JLT = 62 , # [doc = "< eBPF only"] BPF_INS_JLE = 63 , # [doc = "< eBPF only"] BPF_INS_JSLT = 64 , # [doc = "< eBPF only"] BPF_INS_JSLE = 65 , BPF_INS_RET = 66 , BPF_INS_TAX = 67 , BPF_INS_TXA = 68 , BPF_INS_ENDING = 69 , } # [repr (u32)] # [doc = " Group of BPF instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum bpf_insn_group { # [doc = "< = CS_GRP_INVALID"] BPF_GRP_INVALID = 0 , BPF_GRP_LOAD = 1 , BPF_GRP_STORE = 2 , BPF_GRP_ALU = 3 , BPF_GRP_JUMP = 4 , # [doc = "< eBPF only"] BPF_GRP_CALL = 5 , BPF_GRP_RETURN = 6 , # [doc = "< cBPF only"] BPF_GRP_MISC = 7 , BPF_GRP_ENDING = 8 , } # [repr (u32)] # [doc = " SH registers and special registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_reg { SH_REG_INVALID = 0 , SH_REG_R0 = 1 , SH_REG_R1 = 2 , SH_REG_R2 = 3 , SH_REG_R3 = 4 , SH_REG_R4 = 5 , SH_REG_R5 = 6 , SH_REG_R6 = 7 , SH_REG_R7 = 8 , SH_REG_R8 = 9 , SH_REG_R9 = 10 , SH_REG_R10 = 11 , SH_REG_R11 = 12 , SH_REG_R12 = 13 , SH_REG_R13 = 14 , SH_REG_R14 = 15 , SH_REG_R15 = 16 , SH_REG_R0_BANK = 17 , SH_REG_R1_BANK = 18 , SH_REG_R2_BANK = 19 , SH_REG_R3_BANK = 20 , SH_REG_R4_BANK = 21 , SH_REG_R5_BANK = 22 , SH_REG_R6_BANK = 23 , SH_REG_R7_BANK = 24 , SH_REG_FR0 = 25 , SH_REG_FR1 = 26 , SH_REG_FR2 = 27 , SH_REG_FR3 = 28 , SH_REG_FR4 = 29 , SH_REG_FR5 = 30 , SH_REG_FR6 = 31 , SH_REG_FR7 = 32 , SH_REG_FR8 = 33 , SH_REG_FR9 = 34 , SH_REG_FR10 = 35 , SH_REG_FR11 = 36 , SH_REG_FR12 = 37 , SH_REG_FR13 = 38 , SH_REG_FR14 = 39 , SH_REG_FR15 = 40 , SH_REG_DR0 = 41 , SH_REG_DR2 = 42 , SH_REG_DR4 = 43 , SH_REG_DR6 = 44 , SH_REG_DR8 = 45 , SH_REG_DR10 = 46 , SH_REG_DR12 = 47 , SH_REG_DR14 = 48 , SH_REG_XD0 = 49 , SH_REG_XD2 = 50 , SH_REG_XD4 = 51 , SH_REG_XD6 = 52 , SH_REG_XD8 = 53 , SH_REG_XD10 = 54 , SH_REG_XD12 = 55 , SH_REG_XD14 = 56 , SH_REG_XF0 = 57 , SH_REG_XF1 = 58 , SH_REG_XF2 = 59 , SH_REG_XF3 = 60 , SH_REG_XF4 = 61 , SH_REG_XF5 = 62 , SH_REG_XF6 = 63 , SH_REG_XF7 = 64 , SH_REG_XF8 = 65 , SH_REG_XF9 = 66 , SH_REG_XF10 = 67 , SH_REG_XF11 = 68 , SH_REG_XF12 = 69 , SH_REG_XF13 = 70 , SH_REG_XF14 = 71 , SH_REG_XF15 = 72 , SH_REG_FV0 = 73 , SH_REG_FV4 = 74 , SH_REG_FV8 = 75 , SH_REG_FV12 = 76 , SH_REG_XMATRX = 77 , SH_REG_PC = 78 , SH_REG_PR = 79 , SH_REG_MACH = 80 , SH_REG_MACL = 81 , SH_REG_SR = 82 , SH_REG_GBR = 83 , SH_REG_SSR = 84 , SH_REG_SPC = 85 , SH_REG_SGR = 86 , SH_REG_DBR = 87 , SH_REG_VBR = 88 , SH_REG_TBR = 89 , SH_REG_RS = 90 , SH_REG_RE = 91 , SH_REG_MOD = 92 , SH_REG_FPUL = 93 , SH_REG_FPSCR = 94 , SH_REG_DSP_X0 = 95 , SH_REG_DSP_X1 = 96 , SH_REG_DSP_Y0 = 97 , SH_REG_DSP_Y1 = 98 , SH_REG_DSP_A0 = 99 , SH_REG_DSP_A1 = 100 , SH_REG_DSP_A0G = 101 , SH_REG_DSP_A1G = 102 , SH_REG_DSP_M0 = 103 , SH_REG_DSP_M1 = 104 , SH_REG_DSP_DSR = 105 , SH_REG_DSP_RSV0 = 106 , SH_REG_DSP_RSV1 = 107 , SH_REG_DSP_RSV2 = 108 , SH_REG_DSP_RSV3 = 109 , SH_REG_DSP_RSV4 = 110 , SH_REG_DSP_RSV5 = 111 , SH_REG_DSP_RSV6 = 112 , SH_REG_DSP_RSV7 = 113 , SH_REG_DSP_RSV8 = 114 , SH_REG_DSP_RSV9 = 115 , SH_REG_DSP_RSVA = 116 , SH_REG_DSP_RSVB = 117 , SH_REG_DSP_RSVC = 118 , SH_REG_DSP_RSVD = 119 , SH_REG_DSP_RSVE = 120 , SH_REG_DSP_RSVF = 121 , SH_REG_ENDING = 122 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_type { # [doc = "< = CS_OP_INVALID (Uninitialized)."] SH_OP_INVALID = 0 , # [doc = "< = CS_OP_REG (Register operand)."] SH_OP_REG = 1 , # [doc = "< = CS_OP_IMM (Immediate operand)."] SH_OP_IMM = 2 , # [doc = "< = CS_OP_MEM (Memory operand)."] SH_OP_MEM = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_op_mem_type { SH_OP_MEM_INVALID = 0 , # [doc = " <= Invalid"] SH_OP_MEM_REG_IND = 1 , # [doc = " <= Register indirect"] SH_OP_MEM_REG_POST = 2 , # [doc = " <= Register post increment"] SH_OP_MEM_REG_PRE = 3 , # [doc = " <= Register pre decrement"] SH_OP_MEM_REG_DISP = 4 , # [doc = " <= displacement"] SH_OP_MEM_REG_R0 = 5 , # [doc = " <= R0 indexed"] SH_OP_MEM_GBR_DISP = 6 , # [doc = " <= GBR based displacement"] SH_OP_MEM_GBR_R0 = 7 , # [doc = " <= GBR based R0 indexed"] SH_OP_MEM_PCR = 8 , # [doc = " <= PC relative"] SH_OP_MEM_TBR_DISP = 9 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_mem { pub address : sh_op_mem_type , # [doc = " <= memory address"] pub reg : sh_reg , # [doc = " <= base register"] pub disp : u32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_mem"] [:: std :: mem :: size_of :: < sh_op_mem > () - 12usize] ; ["Alignment of sh_op_mem"] [:: std :: mem :: align_of :: < sh_op_mem > () - 4usize] ; ["Offset of field: sh_op_mem::address"] [:: std :: mem :: offset_of ! (sh_op_mem , address) - 0usize] ; ["Offset of field: sh_op_mem::reg"] [:: std :: mem :: offset_of ! (sh_op_mem , reg) - 4usize] ; ["Offset of field: sh_op_mem::disp"] [:: std :: mem :: offset_of ! (sh_op_mem , disp) - 8usize] ; } ; # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn_type { SH_INS_DSP_INVALID = 0 , SH_INS_DSP_DOUBLE = 1 , SH_INS_DSP_SINGLE = 2 , SH_INS_DSP_PARALLEL = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_insn { SH_INS_DSP_NOP = 1 , SH_INS_DSP_MOV = 2 , SH_INS_DSP_PSHL = 3 , SH_INS_DSP_PSHA = 4 , SH_INS_DSP_PMULS = 5 , SH_INS_DSP_PCLR_PMULS = 6 , SH_INS_DSP_PSUB_PMULS = 7 , SH_INS_DSP_PADD_PMULS = 8 , SH_INS_DSP_PSUBC = 9 , SH_INS_DSP_PADDC = 10 , SH_INS_DSP_PCMP = 11 , SH_INS_DSP_PABS = 12 , SH_INS_DSP_PRND = 13 , SH_INS_DSP_PSUB = 14 , SH_INS_DSP_PSUBr = 15 , SH_INS_DSP_PADD = 16 , SH_INS_DSP_PAND = 17 , SH_INS_DSP_PXOR = 18 , SH_INS_DSP_POR = 19 , SH_INS_DSP_PDEC = 20 , SH_INS_DSP_PINC = 21 , SH_INS_DSP_PCLR = 22 , SH_INS_DSP_PDMSB = 23 , SH_INS_DSP_PNEG = 24 , SH_INS_DSP_PCOPY = 25 , SH_INS_DSP_PSTS = 26 , SH_INS_DSP_PLDS = 27 , SH_INS_DSP_PSWAP = 28 , SH_INS_DSP_PWAD = 29 , SH_INS_DSP_PWSB = 30 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_operand { SH_OP_DSP_INVALID = 0 , SH_OP_DSP_REG_PRE = 1 , SH_OP_DSP_REG_IND = 2 , SH_OP_DSP_REG_POST = 3 , SH_OP_DSP_REG_INDEX = 4 , SH_OP_DSP_REG = 5 , SH_OP_DSP_IMM = 6 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_dsp_cc { SH_DSP_CC_INVALID = 0 , SH_DSP_CC_NONE = 1 , SH_DSP_CC_DCT = 2 , SH_DSP_CC_DCF = 3 , } # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct sh_op_dsp { pub insn : sh_dsp_insn , pub operand : [sh_dsp_operand ; 2usize] , pub r : [sh_reg ; 6usize] , pub cc : sh_dsp_cc , pub imm : u8 , pub size : :: std :: os :: raw :: c_int , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of sh_op_dsp"] [:: std :: mem :: size_of :: < sh_op_dsp > () - 48usize] ; ["Alignment of sh_op_dsp"] [:: std :: mem :: align_of :: < sh_op_dsp > () - 4usize] ; ["Offset of field: sh_op_dsp::insn"] [:: std :: mem :: offset_of ! (sh_op_dsp , insn) - 0usize] ; ["Offset of field: sh_op_dsp::operand"] [:: std :: mem :: offset_of ! (sh_op_dsp , operand) - 4usize] ; ["Offset of field: sh_op_dsp::r"] [:: std :: mem :: offset_of ! (sh_op_dsp , r) - 12usize] ; ["Offset of field: sh_op_dsp::cc"] [:: std :: mem :: offset_of ! (sh_op_dsp , cc) - 36usize] ; ["Offset of field: sh_op_dsp::imm"] [:: std :: mem :: offset_of ! (sh_op_dsp , imm) - 40usize] ; ["Offset of field: sh_op_dsp::size"] [:: std :: mem :: offset_of ! (sh_op_dsp , size) - 44usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh_op { pub type_ : sh_op_type , pub __bindgen_anon_1 : cs_sh_op__bindgen_ty_1 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_sh_op__bindgen_ty_1 { # [doc = "< immediate value for IMM operand"] pub imm : u64 , # [doc = "< register value for REG operand"] pub reg : sh_reg , # [doc = "< data when operand is targeting memory"] pub mem : sh_op_mem , # [doc = "< dsp instruction"] pub dsp : sh_op_dsp , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_sh_op__bindgen_ty_1 > () - 48usize] ; ["Alignment of cs_sh_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_sh_op__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , mem) - 0usize] ; ["Offset of field: cs_sh_op__bindgen_ty_1::dsp"] [:: std :: mem :: offset_of ! (cs_sh_op__bindgen_ty_1 , dsp) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh_op"] [:: std :: mem :: size_of :: < cs_sh_op > () - 56usize] ; ["Alignment of cs_sh_op"] [:: std :: mem :: align_of :: < cs_sh_op > () - 8usize] ; ["Offset of field: cs_sh_op::type_"] [:: std :: mem :: offset_of ! (cs_sh_op , type_) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_sh_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh_op {{ type: {:?}, __bindgen_anon_1: {:?} }}" , self . type_ , self . __bindgen_anon_1) } } # [repr (u32)] # [doc = " SH instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn { SH_INS_INVALID = 0 , SH_INS_ADD_r = 1 , SH_INS_ADD = 2 , SH_INS_ADDC = 3 , SH_INS_ADDV = 4 , SH_INS_AND = 5 , SH_INS_BAND = 6 , SH_INS_BANDNOT = 7 , SH_INS_BCLR = 8 , SH_INS_BF = 9 , SH_INS_BF_S = 10 , SH_INS_BLD = 11 , SH_INS_BLDNOT = 12 , SH_INS_BOR = 13 , SH_INS_BORNOT = 14 , SH_INS_BRA = 15 , SH_INS_BRAF = 16 , SH_INS_BSET = 17 , SH_INS_BSR = 18 , SH_INS_BSRF = 19 , SH_INS_BST = 20 , SH_INS_BT = 21 , SH_INS_BT_S = 22 , SH_INS_BXOR = 23 , SH_INS_CLIPS = 24 , SH_INS_CLIPU = 25 , SH_INS_CLRDMXY = 26 , SH_INS_CLRMAC = 27 , SH_INS_CLRS = 28 , SH_INS_CLRT = 29 , SH_INS_CMP_EQ = 30 , SH_INS_CMP_GE = 31 , SH_INS_CMP_GT = 32 , SH_INS_CMP_HI = 33 , SH_INS_CMP_HS = 34 , SH_INS_CMP_PL = 35 , SH_INS_CMP_PZ = 36 , SH_INS_CMP_STR = 37 , SH_INS_DIV0S = 38 , SH_INS_DIV0U = 39 , SH_INS_DIV1 = 40 , SH_INS_DIVS = 41 , SH_INS_DIVU = 42 , SH_INS_DMULS_L = 43 , SH_INS_DMULU_L = 44 , SH_INS_DT = 45 , SH_INS_EXTS_B = 46 , SH_INS_EXTS_W = 47 , SH_INS_EXTU_B = 48 , SH_INS_EXTU_W = 49 , SH_INS_FABS = 50 , SH_INS_FADD = 51 , SH_INS_FCMP_EQ = 52 , SH_INS_FCMP_GT = 53 , SH_INS_FCNVDS = 54 , SH_INS_FCNVSD = 55 , SH_INS_FDIV = 56 , SH_INS_FIPR = 57 , SH_INS_FLDI0 = 58 , SH_INS_FLDI1 = 59 , SH_INS_FLDS = 60 , SH_INS_FLOAT = 61 , SH_INS_FMAC = 62 , SH_INS_FMOV = 63 , SH_INS_FMUL = 64 , SH_INS_FNEG = 65 , SH_INS_FPCHG = 66 , SH_INS_FRCHG = 67 , SH_INS_FSCA = 68 , SH_INS_FSCHG = 69 , SH_INS_FSQRT = 70 , SH_INS_FSRRA = 71 , SH_INS_FSTS = 72 , SH_INS_FSUB = 73 , SH_INS_FTRC = 74 , SH_INS_FTRV = 75 , SH_INS_ICBI = 76 , SH_INS_JMP = 77 , SH_INS_JSR = 78 , SH_INS_JSR_N = 79 , SH_INS_LDBANK = 80 , SH_INS_LDC = 81 , SH_INS_LDRC = 82 , SH_INS_LDRE = 83 , SH_INS_LDRS = 84 , SH_INS_LDS = 85 , SH_INS_LDTLB = 86 , SH_INS_MAC_L = 87 , SH_INS_MAC_W = 88 , SH_INS_MOV = 89 , SH_INS_MOVA = 90 , SH_INS_MOVCA = 91 , SH_INS_MOVCO = 92 , SH_INS_MOVI20 = 93 , SH_INS_MOVI20S = 94 , SH_INS_MOVLI = 95 , SH_INS_MOVML = 96 , SH_INS_MOVMU = 97 , SH_INS_MOVRT = 98 , SH_INS_MOVT = 99 , SH_INS_MOVU = 100 , SH_INS_MOVUA = 101 , SH_INS_MUL_L = 102 , SH_INS_MULR = 103 , SH_INS_MULS_W = 104 , SH_INS_MULU_W = 105 , SH_INS_NEG = 106 , SH_INS_NEGC = 107 , SH_INS_NOP = 108 , SH_INS_NOT = 109 , SH_INS_NOTT = 110 , SH_INS_OCBI = 111 , SH_INS_OCBP = 112 , SH_INS_OCBWB = 113 , SH_INS_OR = 114 , SH_INS_PREF = 115 , SH_INS_PREFI = 116 , SH_INS_RESBANK = 117 , SH_INS_ROTCL = 118 , SH_INS_ROTCR = 119 , SH_INS_ROTL = 120 , SH_INS_ROTR = 121 , SH_INS_RTE = 122 , SH_INS_RTS = 123 , SH_INS_RTS_N = 124 , SH_INS_RTV_N = 125 , SH_INS_SETDMX = 126 , SH_INS_SETDMY = 127 , SH_INS_SETRC = 128 , SH_INS_SETS = 129 , SH_INS_SETT = 130 , SH_INS_SHAD = 131 , SH_INS_SHAL = 132 , SH_INS_SHAR = 133 , SH_INS_SHLD = 134 , SH_INS_SHLL = 135 , SH_INS_SHLL16 = 136 , SH_INS_SHLL2 = 137 , SH_INS_SHLL8 = 138 , SH_INS_SHLR = 139 , SH_INS_SHLR16 = 140 , SH_INS_SHLR2 = 141 , SH_INS_SHLR8 = 142 , SH_INS_SLEEP = 143 , SH_INS_STBANK = 144 , SH_INS_STC = 145 , SH_INS_STS = 146 , SH_INS_SUB = 147 , SH_INS_SUBC = 148 , SH_INS_SUBV = 149 , SH_INS_SWAP_B = 150 , SH_INS_SWAP_W = 151 , SH_INS_SYNCO = 152 , SH_INS_TAS = 153 , SH_INS_TRAPA = 154 , SH_INS_TST = 155 , SH_INS_XOR = 156 , SH_INS_XTRCT = 157 , SH_INS_DSP = 158 , SH_INS_ENDING = 159 , } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_sh { pub insn : sh_insn , pub size : u8 , pub op_count : u8 , pub operands : [cs_sh_op ; 3usize] , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_sh"] [:: std :: mem :: size_of :: < cs_sh > () - 176usize] ; ["Alignment of cs_sh"] [:: std :: mem :: align_of :: < cs_sh > () - 8usize] ; ["Offset of field: cs_sh::insn"] [:: std :: mem :: offset_of ! (cs_sh , insn) - 0usize] ; ["Offset of field: cs_sh::size"] [:: std :: mem :: offset_of ! (cs_sh , size) - 4usize] ; ["Offset of field: cs_sh::op_count"] [:: std :: mem :: offset_of ! (cs_sh , op_count) - 5usize] ; ["Offset of field: cs_sh::operands"] [:: std :: mem :: offset_of ! (cs_sh , operands) - 8usize] ; } ; impl :: std :: fmt :: Debug for cs_sh { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_sh {{ insn: {:?}, size: {:?}, op_count: {:?}, operands: {:?} }}" , self . insn , self . size , self . op_count , self . operands) } } # [repr (u32)] # [doc = " Group of SH instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum sh_insn_group { # [doc = "< CS_GRUP_INVALID"] SH_GRP_INVALID = 0 , # [doc = "< = CS_GRP_JUMP"] SH_GRP_JUMP = 1 , # [doc = "< = CS_GRP_CALL"] SH_GRP_CALL = 2 , # [doc = "< = CS_GRP_INT"] SH_GRP_INT = 3 , # [doc = "< = CS_GRP_RET"] SH_GRP_RET = 4 , # [doc = "< = CS_GRP_IRET"] SH_GRP_IRET = 5 , # [doc = "< = CS_GRP_PRIVILEGE"] SH_GRP_PRIVILEGE = 6 , # [doc = "< = CS_GRP_BRANCH_RELATIVE"] SH_GRP_BRANCH_RELATIVE = 7 , SH_GRP_SH1 = 8 , SH_GRP_SH2 = 9 , SH_GRP_SH2E = 10 , SH_GRP_SH2DSP = 11 , SH_GRP_SH2A = 12 , SH_GRP_SH2AFPU = 13 , SH_GRP_SH3 = 14 , SH_GRP_SH3DSP = 15 , SH_GRP_SH4 = 16 , SH_GRP_SH4A = 17 , SH_GRP_ENDING = 18 , } # [repr (u32)] # [doc = " Operand type for instruction's operands"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_op_type { # [doc = "< CS_OP_INVALID (Uninitialized)."] TRICORE_OP_INVALID = 0 , # [doc = "< CS_OP_REG (Register operand)."] TRICORE_OP_REG = 1 , # [doc = "< CS_OP_IMM (Immediate operand)."] TRICORE_OP_IMM = 2 , # [doc = "< CS_OP_MEM (Memory operand)."] TRICORE_OP_MEM = 3 , } # [doc = " Instruction's operand referring to memory\n This is associated with TRICORE_OP_MEM operand type above"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct tricore_op_mem { # [doc = "< base register"] pub base : u8 , # [doc = "< displacement/offset value"] pub disp : i32 , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of tricore_op_mem"] [:: std :: mem :: size_of :: < tricore_op_mem > () - 8usize] ; ["Alignment of tricore_op_mem"] [:: std :: mem :: align_of :: < tricore_op_mem > () - 4usize] ; ["Offset of field: tricore_op_mem::base"] [:: std :: mem :: offset_of ! (tricore_op_mem , base) - 0usize] ; ["Offset of field: tricore_op_mem::disp"] [:: std :: mem :: offset_of ! (tricore_op_mem , disp) - 4usize] ; } ; # [doc = " Instruction operand"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore_op { # [doc = "< operand type"] pub type_ : tricore_op_type , pub __bindgen_anon_1 : cs_tricore_op__bindgen_ty_1 , # [doc = "< How is this operand accessed? (READ, WRITE or READ|WRITE)"] pub access : u8 , } # [repr (C)] # [derive (Copy , Clone)] pub union cs_tricore_op__bindgen_ty_1 { # [doc = "< register value for REG operand"] pub reg : :: std :: os :: raw :: c_uint , # [doc = "< immediate value for IMM operand"] pub imm : i32 , # [doc = "< base/disp value for MEM operand"] pub mem : tricore_op_mem , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_tricore_op__bindgen_ty_1 > () - 8usize] ; ["Alignment of cs_tricore_op__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_tricore_op__bindgen_ty_1 > () - 4usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::reg"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , reg) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::imm"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , imm) - 0usize] ; ["Offset of field: cs_tricore_op__bindgen_ty_1::mem"] [:: std :: mem :: offset_of ! (cs_tricore_op__bindgen_ty_1 , mem) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore_op"] [:: std :: mem :: size_of :: < cs_tricore_op > () - 16usize] ; ["Alignment of cs_tricore_op"] [:: std :: mem :: align_of :: < cs_tricore_op > () - 4usize] ; ["Offset of field: cs_tricore_op::type_"] [:: std :: mem :: offset_of ! (cs_tricore_op , type_) - 0usize] ; ["Offset of field: cs_tricore_op::access"] [:: std :: mem :: offset_of ! (cs_tricore_op , access) - 12usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore_op { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . access) } } # [doc = " Instruction structure"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_tricore { # [doc = "< number of operands of this instruction."] pub op_count : u8 , # [doc = "< operands for this instruction."] pub operands : [cs_tricore_op ; 8usize] , # [doc = "< whether the flags register is updated."] pub update_flags : bool , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_tricore"] [:: std :: mem :: size_of :: < cs_tricore > () - 136usize] ; ["Alignment of cs_tricore"] [:: std :: mem :: align_of :: < cs_tricore > () - 4usize] ; ["Offset of field: cs_tricore::op_count"] [:: std :: mem :: offset_of ! (cs_tricore , op_count) - 0usize] ; ["Offset of field: cs_tricore::operands"] [:: std :: mem :: offset_of ! (cs_tricore , operands) - 4usize] ; ["Offset of field: cs_tricore::update_flags"] [:: std :: mem :: offset_of ! (cs_tricore , update_flags) - 132usize] ; } ; impl :: std :: fmt :: Debug for cs_tricore { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_tricore {{ op_count: {:?}, operands: {:?}, update_flags: {:?} }}" , self . op_count , self . operands , self . update_flags) } } # [repr (u32)] # [doc = " TriCore registers"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_reg { TRICORE_REG_INVALID = 0 , TRICORE_REG_FCX = 1 , TRICORE_REG_PC = 2 , TRICORE_REG_PCXI = 3 , TRICORE_REG_PSW = 4 , TRICORE_REG_A0 = 5 , TRICORE_REG_A1 = 6 , TRICORE_REG_A2 = 7 , TRICORE_REG_A3 = 8 , TRICORE_REG_A4 = 9 , TRICORE_REG_A5 = 10 , TRICORE_REG_A6 = 11 , TRICORE_REG_A7 = 12 , TRICORE_REG_A8 = 13 , TRICORE_REG_A9 = 14 , TRICORE_REG_A10 = 15 , TRICORE_REG_A11 = 16 , TRICORE_REG_A12 = 17 , TRICORE_REG_A13 = 18 , TRICORE_REG_A14 = 19 , TRICORE_REG_A15 = 20 , TRICORE_REG_D0 = 21 , TRICORE_REG_D1 = 22 , TRICORE_REG_D2 = 23 , TRICORE_REG_D3 = 24 , TRICORE_REG_D4 = 25 , TRICORE_REG_D5 = 26 , TRICORE_REG_D6 = 27 , TRICORE_REG_D7 = 28 , TRICORE_REG_D8 = 29 , TRICORE_REG_D9 = 30 , TRICORE_REG_D10 = 31 , TRICORE_REG_D11 = 32 , TRICORE_REG_D12 = 33 , TRICORE_REG_D13 = 34 , TRICORE_REG_D14 = 35 , TRICORE_REG_D15 = 36 , TRICORE_REG_E0 = 37 , TRICORE_REG_E2 = 38 , TRICORE_REG_E4 = 39 , TRICORE_REG_E6 = 40 , TRICORE_REG_E8 = 41 , TRICORE_REG_E10 = 42 , TRICORE_REG_E12 = 43 , TRICORE_REG_E14 = 44 , TRICORE_REG_P0 = 45 , TRICORE_REG_P2 = 46 , TRICORE_REG_P4 = 47 , TRICORE_REG_P6 = 48 , TRICORE_REG_P8 = 49 , TRICORE_REG_P10 = 50 , TRICORE_REG_P12 = 51 , TRICORE_REG_P14 = 52 , TRICORE_REG_A0_A1 = 53 , TRICORE_REG_A2_A3 = 54 , TRICORE_REG_A4_A5 = 55 , TRICORE_REG_A6_A7 = 56 , TRICORE_REG_A8_A9 = 57 , TRICORE_REG_A10_A11 = 58 , TRICORE_REG_A12_A13 = 59 , TRICORE_REG_A14_A15 = 60 , TRICORE_REG_ENDING = 61 , } # [repr (u32)] # [doc = " TriCore instruction"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn { TRICORE_INS_INVALID = 0 , TRICORE_INS_XOR_T = 1 , TRICORE_INS_ABSDIFS_B = 2 , TRICORE_INS_ABSDIFS_H = 3 , TRICORE_INS_ABSDIFS = 4 , TRICORE_INS_ABSDIF_B = 5 , TRICORE_INS_ABSDIF_H = 6 , TRICORE_INS_ABSDIF = 7 , TRICORE_INS_ABSS_B = 8 , TRICORE_INS_ABSS_H = 9 , TRICORE_INS_ABSS = 10 , TRICORE_INS_ABS_B = 11 , TRICORE_INS_ABS_H = 12 , TRICORE_INS_ABS = 13 , TRICORE_INS_ADDC = 14 , TRICORE_INS_ADDIH_A = 15 , TRICORE_INS_ADDIH = 16 , TRICORE_INS_ADDI = 17 , TRICORE_INS_ADDSC_AT = 18 , TRICORE_INS_ADDSC_A = 19 , TRICORE_INS_ADDS_BU = 20 , TRICORE_INS_ADDS_B = 21 , TRICORE_INS_ADDS_H = 22 , TRICORE_INS_ADDS_HU = 23 , TRICORE_INS_ADDS_U = 24 , TRICORE_INS_ADDS = 25 , TRICORE_INS_ADDX = 26 , TRICORE_INS_ADD_A = 27 , TRICORE_INS_ADD_B = 28 , TRICORE_INS_ADD_F = 29 , TRICORE_INS_ADD_H = 30 , TRICORE_INS_ADD = 31 , TRICORE_INS_ANDN_T = 32 , TRICORE_INS_ANDN = 33 , TRICORE_INS_AND_ANDN_T = 34 , TRICORE_INS_AND_AND_T = 35 , TRICORE_INS_AND_EQ = 36 , TRICORE_INS_AND_GE_U = 37 , TRICORE_INS_AND_GE = 38 , TRICORE_INS_AND_LT_U = 39 , TRICORE_INS_AND_LT = 40 , TRICORE_INS_AND_NE = 41 , TRICORE_INS_AND_NOR_T = 42 , TRICORE_INS_AND_OR_T = 43 , TRICORE_INS_AND_T = 44 , TRICORE_INS_AND = 45 , TRICORE_INS_BISR = 46 , TRICORE_INS_BMERGE = 47 , TRICORE_INS_BSPLIT = 48 , TRICORE_INS_CACHEA_I = 49 , TRICORE_INS_CACHEA_WI = 50 , TRICORE_INS_CACHEA_W = 51 , TRICORE_INS_CACHEI_I = 52 , TRICORE_INS_CACHEI_WI = 53 , TRICORE_INS_CACHEI_W = 54 , TRICORE_INS_CADDN_A = 55 , TRICORE_INS_CADDN = 56 , TRICORE_INS_CADD_A = 57 , TRICORE_INS_CADD = 58 , TRICORE_INS_CALLA = 59 , TRICORE_INS_CALLI = 60 , TRICORE_INS_CALL = 61 , TRICORE_INS_CLO_B = 62 , TRICORE_INS_CLO_H = 63 , TRICORE_INS_CLO = 64 , TRICORE_INS_CLS_B = 65 , TRICORE_INS_CLS_H = 66 , TRICORE_INS_CLS = 67 , TRICORE_INS_CLZ_B = 68 , TRICORE_INS_CLZ_H = 69 , TRICORE_INS_CLZ = 70 , TRICORE_INS_CMOVN = 71 , TRICORE_INS_CMOV = 72 , TRICORE_INS_CMPSWAP_W = 73 , TRICORE_INS_CMP_F = 74 , TRICORE_INS_CRC32B_W = 75 , TRICORE_INS_CRC32L_W = 76 , TRICORE_INS_CRC32_B = 77 , TRICORE_INS_CRCN = 78 , TRICORE_INS_CSUBN_A = 79 , TRICORE_INS_CSUBN = 80 , TRICORE_INS_CSUB_A = 81 , TRICORE_INS_CSUB = 82 , TRICORE_INS_DEBUG = 83 , TRICORE_INS_DEXTR = 84 , TRICORE_INS_DIFSC_A = 85 , TRICORE_INS_DISABLE = 86 , TRICORE_INS_DIV_F = 87 , TRICORE_INS_DIV_U = 88 , TRICORE_INS_DIV = 89 , TRICORE_INS_DSYNC = 90 , TRICORE_INS_DVADJ = 91 , TRICORE_INS_DVINIT_BU = 92 , TRICORE_INS_DVINIT_B = 93 , TRICORE_INS_DVINIT_HU = 94 , TRICORE_INS_DVINIT_H = 95 , TRICORE_INS_DVINIT_U = 96 , TRICORE_INS_DVINIT = 97 , TRICORE_INS_DVSTEP_U = 98 , TRICORE_INS_DVSTEP = 99 , TRICORE_INS_ENABLE = 100 , TRICORE_INS_EQANY_B = 101 , TRICORE_INS_EQANY_H = 102 , TRICORE_INS_EQZ_A = 103 , TRICORE_INS_EQ_A = 104 , TRICORE_INS_EQ_B = 105 , TRICORE_INS_EQ_H = 106 , TRICORE_INS_EQ_W = 107 , TRICORE_INS_EQ = 108 , TRICORE_INS_EXTR_U = 109 , TRICORE_INS_EXTR = 110 , TRICORE_INS_FCALLA = 111 , TRICORE_INS_FCALLI = 112 , TRICORE_INS_FCALL = 113 , TRICORE_INS_FRET = 114 , TRICORE_INS_FTOHP = 115 , TRICORE_INS_FTOIZ = 116 , TRICORE_INS_FTOI = 117 , TRICORE_INS_FTOQ31Z = 118 , TRICORE_INS_FTOQ31 = 119 , TRICORE_INS_FTOUZ = 120 , TRICORE_INS_FTOU = 121 , TRICORE_INS_GE_A = 122 , TRICORE_INS_GE_U = 123 , TRICORE_INS_GE = 124 , TRICORE_INS_HPTOF = 125 , TRICORE_INS_IMASK = 126 , TRICORE_INS_INSERT = 127 , TRICORE_INS_INSN_T = 128 , TRICORE_INS_INS_T = 129 , TRICORE_INS_ISYNC = 130 , TRICORE_INS_ITOF = 131 , TRICORE_INS_IXMAX_U = 132 , TRICORE_INS_IXMAX = 133 , TRICORE_INS_IXMIN_U = 134 , TRICORE_INS_IXMIN = 135 , TRICORE_INS_JA = 136 , TRICORE_INS_JEQ_A = 137 , TRICORE_INS_JEQ = 138 , TRICORE_INS_JGEZ = 139 , TRICORE_INS_JGE_U = 140 , TRICORE_INS_JGE = 141 , TRICORE_INS_JGTZ = 142 , TRICORE_INS_JI = 143 , TRICORE_INS_JLA = 144 , TRICORE_INS_JLEZ = 145 , TRICORE_INS_JLI = 146 , TRICORE_INS_JLTZ = 147 , TRICORE_INS_JLT_U = 148 , TRICORE_INS_JLT = 149 , TRICORE_INS_JL = 150 , TRICORE_INS_JNED = 151 , TRICORE_INS_JNEI = 152 , TRICORE_INS_JNE_A = 153 , TRICORE_INS_JNE = 154 , TRICORE_INS_JNZ_A = 155 , TRICORE_INS_JNZ_T = 156 , TRICORE_INS_JNZ = 157 , TRICORE_INS_JZ_A = 158 , TRICORE_INS_JZ_T = 159 , TRICORE_INS_JZ = 160 , TRICORE_INS_J = 161 , TRICORE_INS_LDLCX = 162 , TRICORE_INS_LDMST = 163 , TRICORE_INS_LDUCX = 164 , TRICORE_INS_LD_A = 165 , TRICORE_INS_LD_BU = 166 , TRICORE_INS_LD_B = 167 , TRICORE_INS_LD_DA = 168 , TRICORE_INS_LD_D = 169 , TRICORE_INS_LD_HU = 170 , TRICORE_INS_LD_H = 171 , TRICORE_INS_LD_Q = 172 , TRICORE_INS_LD_W = 173 , TRICORE_INS_LEA = 174 , TRICORE_INS_LHA = 175 , TRICORE_INS_LOOPU = 176 , TRICORE_INS_LOOP = 177 , TRICORE_INS_LT_A = 178 , TRICORE_INS_LT_B = 179 , TRICORE_INS_LT_BU = 180 , TRICORE_INS_LT_H = 181 , TRICORE_INS_LT_HU = 182 , TRICORE_INS_LT_U = 183 , TRICORE_INS_LT_W = 184 , TRICORE_INS_LT_WU = 185 , TRICORE_INS_LT = 186 , TRICORE_INS_MADDMS_H = 187 , TRICORE_INS_MADDMS_U = 188 , TRICORE_INS_MADDMS = 189 , TRICORE_INS_MADDM_H = 190 , TRICORE_INS_MADDM_Q = 191 , TRICORE_INS_MADDM_U = 192 , TRICORE_INS_MADDM = 193 , TRICORE_INS_MADDRS_H = 194 , TRICORE_INS_MADDRS_Q = 195 , TRICORE_INS_MADDR_H = 196 , TRICORE_INS_MADDR_Q = 197 , TRICORE_INS_MADDSUMS_H = 198 , TRICORE_INS_MADDSUM_H = 199 , TRICORE_INS_MADDSURS_H = 200 , TRICORE_INS_MADDSUR_H = 201 , TRICORE_INS_MADDSUS_H = 202 , TRICORE_INS_MADDSU_H = 203 , TRICORE_INS_MADDS_H = 204 , TRICORE_INS_MADDS_Q = 205 , TRICORE_INS_MADDS_U = 206 , TRICORE_INS_MADDS = 207 , TRICORE_INS_MADD_F = 208 , TRICORE_INS_MADD_H = 209 , TRICORE_INS_MADD_Q = 210 , TRICORE_INS_MADD_U = 211 , TRICORE_INS_MADD = 212 , TRICORE_INS_MAX_B = 213 , TRICORE_INS_MAX_BU = 214 , TRICORE_INS_MAX_H = 215 , TRICORE_INS_MAX_HU = 216 , TRICORE_INS_MAX_U = 217 , TRICORE_INS_MAX = 218 , TRICORE_INS_MFCR = 219 , TRICORE_INS_MIN_B = 220 , TRICORE_INS_MIN_BU = 221 , TRICORE_INS_MIN_H = 222 , TRICORE_INS_MIN_HU = 223 , TRICORE_INS_MIN_U = 224 , TRICORE_INS_MIN = 225 , TRICORE_INS_MOVH_A = 226 , TRICORE_INS_MOVH = 227 , TRICORE_INS_MOVZ_A = 228 , TRICORE_INS_MOV_AA = 229 , TRICORE_INS_MOV_A = 230 , TRICORE_INS_MOV_D = 231 , TRICORE_INS_MOV_U = 232 , TRICORE_INS_MOV = 233 , TRICORE_INS_MSUBADMS_H = 234 , TRICORE_INS_MSUBADM_H = 235 , TRICORE_INS_MSUBADRS_H = 236 , TRICORE_INS_MSUBADR_H = 237 , TRICORE_INS_MSUBADS_H = 238 , TRICORE_INS_MSUBAD_H = 239 , TRICORE_INS_MSUBMS_H = 240 , TRICORE_INS_MSUBMS_U = 241 , TRICORE_INS_MSUBMS = 242 , TRICORE_INS_MSUBM_H = 243 , TRICORE_INS_MSUBM_Q = 244 , TRICORE_INS_MSUBM_U = 245 , TRICORE_INS_MSUBM = 246 , TRICORE_INS_MSUBRS_H = 247 , TRICORE_INS_MSUBRS_Q = 248 , TRICORE_INS_MSUBR_H = 249 , TRICORE_INS_MSUBR_Q = 250 , TRICORE_INS_MSUBS_H = 251 , TRICORE_INS_MSUBS_Q = 252 , TRICORE_INS_MSUBS_U = 253 , TRICORE_INS_MSUBS = 254 , TRICORE_INS_MSUB_F = 255 , TRICORE_INS_MSUB_H = 256 , TRICORE_INS_MSUB_Q = 257 , TRICORE_INS_MSUB_U = 258 , TRICORE_INS_MSUB = 259 , TRICORE_INS_MTCR = 260 , TRICORE_INS_MULMS_H = 261 , TRICORE_INS_MULM_H = 262 , TRICORE_INS_MULM_U = 263 , TRICORE_INS_MULM = 264 , TRICORE_INS_MULR_H = 265 , TRICORE_INS_MULR_Q = 266 , TRICORE_INS_MULS_U = 267 , TRICORE_INS_MULS = 268 , TRICORE_INS_MUL_F = 269 , TRICORE_INS_MUL_H = 270 , TRICORE_INS_MUL_Q = 271 , TRICORE_INS_MUL_U = 272 , TRICORE_INS_MUL = 273 , TRICORE_INS_NAND_T = 274 , TRICORE_INS_NAND = 275 , TRICORE_INS_NEZ_A = 276 , TRICORE_INS_NE_A = 277 , TRICORE_INS_NE = 278 , TRICORE_INS_NOP = 279 , TRICORE_INS_NOR_T = 280 , TRICORE_INS_NOR = 281 , TRICORE_INS_NOT = 282 , TRICORE_INS_ORN_T = 283 , TRICORE_INS_ORN = 284 , TRICORE_INS_OR_ANDN_T = 285 , TRICORE_INS_OR_AND_T = 286 , TRICORE_INS_OR_EQ = 287 , TRICORE_INS_OR_GE_U = 288 , TRICORE_INS_OR_GE = 289 , TRICORE_INS_OR_LT_U = 290 , TRICORE_INS_OR_LT = 291 , TRICORE_INS_OR_NE = 292 , TRICORE_INS_OR_NOR_T = 293 , TRICORE_INS_OR_OR_T = 294 , TRICORE_INS_OR_T = 295 , TRICORE_INS_OR = 296 , TRICORE_INS_PACK = 297 , TRICORE_INS_PARITY = 298 , TRICORE_INS_POPCNT_W = 299 , TRICORE_INS_Q31TOF = 300 , TRICORE_INS_QSEED_F = 301 , TRICORE_INS_RESTORE = 302 , TRICORE_INS_RET = 303 , TRICORE_INS_RFE = 304 , TRICORE_INS_RFM = 305 , TRICORE_INS_RSLCX = 306 , TRICORE_INS_RSTV = 307 , TRICORE_INS_RSUBS_U = 308 , TRICORE_INS_RSUBS = 309 , TRICORE_INS_RSUB = 310 , TRICORE_INS_SAT_BU = 311 , TRICORE_INS_SAT_B = 312 , TRICORE_INS_SAT_HU = 313 , TRICORE_INS_SAT_H = 314 , TRICORE_INS_SELN_A = 315 , TRICORE_INS_SELN = 316 , TRICORE_INS_SEL_A = 317 , TRICORE_INS_SEL = 318 , TRICORE_INS_SHAS = 319 , TRICORE_INS_SHA_B = 320 , TRICORE_INS_SHA_H = 321 , TRICORE_INS_SHA = 322 , TRICORE_INS_SHUFFLE = 323 , TRICORE_INS_SH_ANDN_T = 324 , TRICORE_INS_SH_AND_T = 325 , TRICORE_INS_SH_B = 326 , TRICORE_INS_SH_EQ = 327 , TRICORE_INS_SH_GE_U = 328 , TRICORE_INS_SH_GE = 329 , TRICORE_INS_SH_H = 330 , TRICORE_INS_SH_LT_U = 331 , TRICORE_INS_SH_LT = 332 , TRICORE_INS_SH_NAND_T = 333 , TRICORE_INS_SH_NE = 334 , TRICORE_INS_SH_NOR_T = 335 , TRICORE_INS_SH_ORN_T = 336 , TRICORE_INS_SH_OR_T = 337 , TRICORE_INS_SH_XNOR_T = 338 , TRICORE_INS_SH_XOR_T = 339 , TRICORE_INS_SH = 340 , TRICORE_INS_STLCX = 341 , TRICORE_INS_STUCX = 342 , TRICORE_INS_ST_A = 343 , TRICORE_INS_ST_B = 344 , TRICORE_INS_ST_DA = 345 , TRICORE_INS_ST_D = 346 , TRICORE_INS_ST_H = 347 , TRICORE_INS_ST_Q = 348 , TRICORE_INS_ST_T = 349 , TRICORE_INS_ST_W = 350 , TRICORE_INS_SUBC = 351 , TRICORE_INS_SUBSC_A = 352 , TRICORE_INS_SUBS_BU = 353 , TRICORE_INS_SUBS_B = 354 , TRICORE_INS_SUBS_HU = 355 , TRICORE_INS_SUBS_H = 356 , TRICORE_INS_SUBS_U = 357 , TRICORE_INS_SUBS = 358 , TRICORE_INS_SUBX = 359 , TRICORE_INS_SUB_A = 360 , TRICORE_INS_SUB_B = 361 , TRICORE_INS_SUB_F = 362 , TRICORE_INS_SUB_H = 363 , TRICORE_INS_SUB = 364 , TRICORE_INS_SVLCX = 365 , TRICORE_INS_SWAPMSK_W = 366 , TRICORE_INS_SWAP_A = 367 , TRICORE_INS_SWAP_W = 368 , TRICORE_INS_SYSCALL = 369 , TRICORE_INS_TLBDEMAP = 370 , TRICORE_INS_TLBFLUSH_A = 371 , TRICORE_INS_TLBFLUSH_B = 372 , TRICORE_INS_TLBMAP = 373 , TRICORE_INS_TLBPROBE_A = 374 , TRICORE_INS_TLBPROBE_I = 375 , TRICORE_INS_TRAPSV = 376 , TRICORE_INS_TRAPV = 377 , TRICORE_INS_UNPACK = 378 , TRICORE_INS_UPDFL = 379 , TRICORE_INS_UTOF = 380 , TRICORE_INS_WAIT = 381 , TRICORE_INS_XNOR_T = 382 , TRICORE_INS_XNOR = 383 , TRICORE_INS_XOR_EQ = 384 , TRICORE_INS_XOR_GE_U = 385 , TRICORE_INS_XOR_GE = 386 , TRICORE_INS_XOR_LT_U = 387 , TRICORE_INS_XOR_LT = 388 , TRICORE_INS_XOR_NE = 389 , TRICORE_INS_XOR = 390 , TRICORE_INS_ENDING = 391 , } # [repr (u32)] # [doc = " Group of TriCore instructions"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_insn_group { # [doc = "< = CS_GRP_INVALID"] TRICORE_GRP_INVALID = 0 , # [doc = "< = CS_GRP_CALL"] TRICORE_GRP_CALL = 1 , # [doc = "< = CS_GRP_JUMP"] TRICORE_GRP_JUMP = 2 , # [doc = "< mark the end of the list of groups"] TRICORE_GRP_ENDING = 3 , } # [repr (u32)] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum tricore_feature_t { TRICORE_FEATURE_INVALID = 0 , TRICORE_FEATURE_HasV110 = 128 , TRICORE_FEATURE_HasV120_UP = 129 , TRICORE_FEATURE_HasV130_UP = 130 , TRICORE_FEATURE_HasV161 = 131 , TRICORE_FEATURE_HasV160_UP = 132 , TRICORE_FEATURE_HasV131_UP = 133 , TRICORE_FEATURE_HasV161_UP = 134 , TRICORE_FEATURE_HasV162 = 135 , TRICORE_FEATURE_HasV162_UP = 136 , # [doc = "< mark the end of the list of features"] TRICORE_FEATURE_ENDING = 137 , } pub use self :: tricore_feature_t as tricore_feature ; # [doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"] # [repr (C)] # [derive (Copy , Clone)] pub struct cs_detail { pub regs_read : [u16 ; 20usize] , # [doc = "< number of implicit registers read by this insn"] pub regs_read_count : u8 , pub regs_write : [u16 ; 20usize] , # [doc = "< number of implicit registers modified by this insn"] pub regs_write_count : u8 , # [doc = "< list of group this instruction belong to"] pub groups : [u8 ; 8usize] , # [doc = "< number of groups this insn belongs to"] pub groups_count : u8 , # [doc = "< Instruction has writeback operands."] pub writeback : bool , pub __bindgen_anon_1 : cs_detail__bindgen_ty_1 , } # [doc = " Architecture-specific instruction info"] # [repr (C)] # [derive (Copy , Clone)] pub union cs_detail__bindgen_ty_1 { # [doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"] pub x86 : cs_x86 , # [doc = "< ARM64 architecture (aka AArch64)"] pub arm64 : cs_arm64 , # [doc = "< ARM architecture (including Thumb/Thumb2)"] pub arm : cs_arm , # [doc = "< M68K architecture"] pub m68k : cs_m68k , # [doc = "< MIPS architecture"] pub mips : cs_mips , # [doc = "< PowerPC architecture"] pub ppc : cs_ppc , # [doc = "< Sparc architecture"] pub sparc : cs_sparc , # [doc = "< SystemZ architecture"] pub sysz : cs_sysz , # [doc = "< XCore architecture"] pub xcore : cs_xcore , # [doc = "< TMS320C64x architecture"] pub tms320c64x : cs_tms320c64x , # [doc = "< M680X architecture"] pub m680x : cs_m680x , # [doc = "< Ethereum architecture"] pub evm : cs_evm , # [doc = "< MOS65XX architecture (including MOS6502)"] pub mos65xx : cs_mos65xx , # [doc = "< Web Assembly architecture"] pub wasm : cs_wasm , # [doc = "< Berkeley Packet Filter architecture (including eBPF)"] pub bpf : cs_bpf , # [doc = "< RISCV architecture"] pub riscv : cs_riscv , # [doc = "< SH architecture"] pub sh : cs_sh , # [doc = "< TriCore architecture"] pub tricore : cs_tricore , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail__bindgen_ty_1"] [:: std :: mem :: size_of :: < cs_detail__bindgen_ty_1 > () - 1768usize] ; ["Alignment of cs_detail__bindgen_ty_1"] [:: std :: mem :: align_of :: < cs_detail__bindgen_ty_1 > () - 8usize] ; ["Offset of field: cs_detail__bindgen_ty_1::x86"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , x86) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm64"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm64) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::arm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , arm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m68k"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m68k) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mips"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mips) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::ppc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , ppc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sparc"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sparc) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sysz"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sysz) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::xcore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , xcore) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tms320c64x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tms320c64x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::m680x"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , m680x) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::evm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , evm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::mos65xx"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , mos65xx) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::wasm"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , wasm) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::bpf"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , bpf) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::riscv"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , riscv) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::sh"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , sh) - 0usize] ; ["Offset of field: cs_detail__bindgen_ty_1::tricore"] [:: std :: mem :: offset_of ! (cs_detail__bindgen_ty_1 , tricore) - 0usize] ; } ; impl :: std :: fmt :: Debug for cs_detail__bindgen_ty_1 { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail__bindgen_ty_1 {{ union }}") } } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_detail"] [:: std :: mem :: size_of :: < cs_detail > () - 1864usize] ; ["Alignment of cs_detail"] [:: std :: mem :: align_of :: < cs_detail > () - 8usize] ; ["Offset of field: cs_detail::regs_read"] [:: std :: mem :: offset_of ! (cs_detail , regs_read) - 0usize] ; ["Offset of field: cs_detail::regs_read_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_read_count) - 40usize] ; ["Offset of field: cs_detail::regs_write"] [:: std :: mem :: offset_of ! (cs_detail , regs_write) - 42usize] ; ["Offset of field: cs_detail::regs_write_count"] [:: std :: mem :: offset_of ! (cs_detail , regs_write_count) - 82usize] ; ["Offset of field: cs_detail::groups"] [:: std :: mem :: offset_of ! (cs_detail , groups) - 83usize] ; ["Offset of field: cs_detail::groups_count"] [:: std :: mem :: offset_of ! (cs_detail , groups_count) - 91usize] ; ["Offset of field: cs_detail::writeback"] [:: std :: mem :: offset_of ! (cs_detail , writeback) - 92usize] ; } ; impl :: std :: fmt :: Debug for cs_detail { fn fmt (& self , f : & mut :: std :: fmt :: Formatter < '_ >) -> :: std :: fmt :: Result { write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, writeback: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . writeback , self . __bindgen_anon_1) } } # [doc = " Detail information of disassembled instruction"] # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct cs_insn { # [doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."] pub id : :: std :: os :: raw :: c_uint , # [doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub address : u64 , # [doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub size : u16 , # [doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub bytes : [u8 ; 24usize] , # [doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub mnemonic : [:: std :: os :: raw :: c_char ; 32usize] , # [doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"] pub op_str : [:: std :: os :: raw :: c_char ; 160usize] , # [doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."] pub detail : * mut cs_detail , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of cs_insn"] [:: std :: mem :: size_of :: < cs_insn > () - 248usize] ; ["Alignment of cs_insn"] [:: std :: mem :: align_of :: < cs_insn > () - 8usize] ; ["Offset of field: cs_insn::id"] [:: std :: mem :: offset_of ! (cs_insn , id) - 0usize] ; ["Offset of field: cs_insn::address"] [:: std :: mem :: offset_of ! (cs_insn , address) - 8usize] ; ["Offset of field: cs_insn::size"] [:: std :: mem :: offset_of ! (cs_insn , size) - 16usize] ; ["Offset of field: cs_insn::bytes"] [:: std :: mem :: offset_of ! (cs_insn , bytes) - 18usize] ; ["Offset of field: cs_insn::mnemonic"] [:: std :: mem :: offset_of ! (cs_insn , mnemonic) - 42usize] ; ["Offset of field: cs_insn::op_str"] [:: std :: mem :: offset_of ! (cs_insn , op_str) - 74usize] ; ["Offset of field: cs_insn::detail"] [:: std :: mem :: offset_of ! (cs_insn , detail) - 240usize] ; } ; # [repr (u32)] # [doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"] # [derive (Debug , Copy , Clone , Hash , PartialEq , Eq)] pub enum cs_err { # [doc = "< No error: everything was fine"] CS_ERR_OK = 0 , # [doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"] CS_ERR_MEM = 1 , # [doc = "< Unsupported architecture: cs_open()"] CS_ERR_ARCH = 2 , # [doc = "< Invalid handle: cs_op_count(), cs_op_index()"] CS_ERR_HANDLE = 3 , # [doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"] CS_ERR_CSH = 4 , # [doc = "< Invalid/unsupported mode: cs_open()"] CS_ERR_MODE = 5 , # [doc = "< Invalid/unsupported option: cs_option()"] CS_ERR_OPTION = 6 , # [doc = "< Information is unavailable because detail option is OFF"] CS_ERR_DETAIL = 7 , # [doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"] CS_ERR_MEMSETUP = 8 , # [doc = "< Unsupported version (bindings)"] CS_ERR_VERSION = 9 , # [doc = "< Access irrelevant data in \"diet\" engine"] CS_ERR_DIET = 10 , # [doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"] CS_ERR_SKIPDATA = 11 , # [doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_ATT = 12 , # [doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_INTEL = 13 , # [doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"] CS_ERR_X86_MASM = 14 , } unsafe extern "C" { # [doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."] pub fn cs_version (major : * mut :: std :: os :: raw :: c_int , minor : * mut :: std :: os :: raw :: c_int) -> :: std :: os :: raw :: c_uint ; } unsafe extern "C" { # [doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."] pub fn cs_support (query : :: std :: os :: raw :: c_int) -> bool ; } unsafe extern "C" { # [doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_open (arch : cs_arch , mode : cs_mode , handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_close (handle : * mut csh) -> cs_err ; } unsafe extern "C" { # [doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"] pub fn cs_option (handle : csh , type_ : cs_opt_type , value : usize) -> cs_err ; } unsafe extern "C" { # [doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"] pub fn cs_errno (handle : csh) -> cs_err ; } unsafe extern "C" { # [doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"] pub fn cs_strerror (code : cs_err) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm (handle : csh , code : * const u8 , code_size : usize , address : u64 , count : usize , insn : * mut * mut cs_insn) -> usize ; } unsafe extern "C" { # [doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."] pub fn cs_free (insn : * mut cs_insn , count : usize) ; } unsafe extern "C" { # [doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"] pub fn cs_malloc (handle : csh) -> * mut cs_insn ; } unsafe extern "C" { # [doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."] pub fn cs_disasm_iter (handle : csh , code : * mut * const u8 , size : * mut usize , address : * mut u64 , insn : * mut cs_insn) -> bool ; } unsafe extern "C" { # [doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."] pub fn cs_reg_name (handle : csh , reg_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."] pub fn cs_insn_name (handle : csh , insn_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."] pub fn cs_group_name (handle : csh , group_id : :: std :: os :: raw :: c_uint) -> * const :: std :: os :: raw :: c_char ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."] pub fn cs_insn_group (handle : csh , insn : * const cs_insn , group_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."] pub fn cs_reg_read (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."] pub fn cs_reg_write (handle : csh , insn : * const cs_insn , reg_id : :: std :: os :: raw :: c_uint) -> bool ; } unsafe extern "C" { # [doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."] pub fn cs_op_count (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } unsafe extern "C" { # [doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."] pub fn cs_op_index (handle : csh , insn : * const cs_insn , op_type : :: std :: os :: raw :: c_uint , position : :: std :: os :: raw :: c_uint) -> :: std :: os :: raw :: c_int ; } # [doc = " Type of array to keep the list of registers"] pub type cs_regs = [u16 ; 64usize] ; unsafe extern "C" { # [doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."] pub fn cs_regs_access (handle : csh , insn : * const cs_insn , regs_read : * mut u16 , regs_read_count : * mut u8 , regs_write : * mut u16 , regs_write_count : * mut u8) -> cs_err ; } pub type __builtin_va_list = [__va_list_tag ; 1usize] ; # [repr (C)] # [derive (Debug , Copy , Clone)] pub struct __va_list_tag { pub gp_offset : :: std :: os :: raw :: c_uint , pub fp_offset : :: std :: os :: raw :: c_uint , pub overflow_arg_area : * mut :: std :: os :: raw :: c_void , pub reg_save_area : * mut :: std :: os :: raw :: c_void , } # [allow (clippy :: unnecessary_operation , clippy :: identity_op)] const _ : () = { ["Size of __va_list_tag"] [:: std :: mem :: size_of :: < __va_list_tag > () - 24usize] ; ["Alignment of __va_list_tag"] [:: std :: mem :: align_of :: < __va_list_tag > () - 8usize] ; ["Offset of field: __va_list_tag::gp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , gp_offset) - 0usize] ; ["Offset of field: __va_list_tag::fp_offset"] [:: std :: mem :: offset_of ! (__va_list_tag , fp_offset) - 4usize] ; ["Offset of field: __va_list_tag::overflow_arg_area"] [:: std :: mem :: offset_of ! (__va_list_tag , overflow_arg_area) - 8usize] ; ["Offset of field: __va_list_tag::reg_save_area"] [:: std :: mem :: offset_of ! (__va_list_tag , reg_save_area) - 16usize] ; } ;
[INFO] [stdout]   |
[INFO] [stdout] 
[INFO] [stdout] 
[INFO] [stdout] warning: unnecessary transmute
[INFO] [stdout]  --> /opt/rustwide/target/debug/build/falcon_capstone/f982cdb455ed4cf6/out/bindings.rs:3:81296
[INFO] [stdout]   |
[INFO] [stdout] 3 | ...0usize , 24u8 , { let _flags2 : u32 = unsafe { :: std :: mem :: transmute (_flags2) } ; _flags2 as u64 }) ; __bindgen_bitfield_uni...
[INFO] [stdout]   |                                                   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[INFO] [stdout]   |
[INFO] [stdout] help: replace this with
[INFO] [stdout]   |
[WARN] too much data in the log, truncating it
